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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/instance/ins_i2s.h@592:a274ee790e56, 2015-07-17 (annotated)

Committer:
mbed_official
Date:
Fri Jul 17 09:15:10 2015 +0100
Revision:
592:a274ee790e56
Parent:
579:53297373a894 
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6



Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/



More API implementation for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 #ifndef _SAMD21_I2S_INSTANCE_
mbed_official 579:53297373a894 2 #define _SAMD21_I2S_INSTANCE_
mbed_official 579:53297373a894 3
mbed_official 579:53297373a894 4 /* ========== Register definition for I2S peripheral ========== */
mbed_official 579:53297373a894 5 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 6 #define REG_I2S_CTRLA (0x42005000U) /**< \brief (I2S) Control A */
mbed_official 579:53297373a894 7 #define REG_I2S_CLKCTRL0 (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
mbed_official 579:53297373a894 8 #define REG_I2S_CLKCTRL1 (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
mbed_official 579:53297373a894 9 #define REG_I2S_INTENCLR (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
mbed_official 579:53297373a894 10 #define REG_I2S_INTENSET (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
mbed_official 579:53297373a894 11 #define REG_I2S_INTFLAG (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 12 #define REG_I2S_SYNCBUSY (0x42005018U) /**< \brief (I2S) Synchronization Status */
mbed_official 579:53297373a894 13 #define REG_I2S_SERCTRL0 (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
mbed_official 579:53297373a894 14 #define REG_I2S_SERCTRL1 (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
mbed_official 579:53297373a894 15 #define REG_I2S_DATA0 (0x42005030U) /**< \brief (I2S) Data 0 */
mbed_official 579:53297373a894 16 #define REG_I2S_DATA1 (0x42005034U) /**< \brief (I2S) Data 1 */
mbed_official 579:53297373a894 17 #else
mbed_official 579:53297373a894 18 #define REG_I2S_CTRLA (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
mbed_official 579:53297373a894 19 #define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
mbed_official 579:53297373a894 20 #define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
mbed_official 579:53297373a894 21 #define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
mbed_official 579:53297373a894 22 #define REG_I2S_INTENSET (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
mbed_official 579:53297373a894 23 #define REG_I2S_INTFLAG (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 24 #define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
mbed_official 579:53297373a894 25 #define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
mbed_official 579:53297373a894 26 #define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
mbed_official 579:53297373a894 27 #define REG_I2S_DATA0 (*(RwReg *)0x42005030U) /**< \brief (I2S) Data 0 */
mbed_official 579:53297373a894 28 #define REG_I2S_DATA1 (*(RwReg *)0x42005034U) /**< \brief (I2S) Data 1 */
mbed_official 579:53297373a894 29 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 30
mbed_official 579:53297373a894 31 /* ========== Instance parameters for I2S peripheral ========== */
mbed_official 579:53297373a894 32 #define I2S_CLK_NUM 2 // Number of clock units
mbed_official 579:53297373a894 33 #define I2S_DMAC_ID_RX_0 41
mbed_official 579:53297373a894 34 #define I2S_DMAC_ID_RX_1 42
mbed_official 579:53297373a894 35 #define I2S_DMAC_ID_RX_LSB 41
mbed_official 579:53297373a894 36 #define I2S_DMAC_ID_RX_MSB 42
mbed_official 579:53297373a894 37 #define I2S_DMAC_ID_RX_SIZE 2
mbed_official 579:53297373a894 38 #define I2S_DMAC_ID_TX_0 43
mbed_official 579:53297373a894 39 #define I2S_DMAC_ID_TX_1 44
mbed_official 579:53297373a894 40 #define I2S_DMAC_ID_TX_LSB 43
mbed_official 579:53297373a894 41 #define I2S_DMAC_ID_TX_MSB 44
mbed_official 579:53297373a894 42 #define I2S_DMAC_ID_TX_SIZE 2
mbed_official 579:53297373a894 43 #define I2S_GCLK_ID_0 35
mbed_official 579:53297373a894 44 #define I2S_GCLK_ID_1 36
mbed_official 579:53297373a894 45 #define I2S_GCLK_ID_LSB 35
mbed_official 579:53297373a894 46 #define I2S_GCLK_ID_MSB 36
mbed_official 579:53297373a894 47 #define I2S_GCLK_ID_SIZE 2
mbed_official 579:53297373a894 48 #define I2S_MAX_SLOTS 8 // Max number of data slots in frame
mbed_official 579:53297373a894 49 #define I2S_SER_NUM 2 // Number of serializers
mbed_official 579:53297373a894 50
mbed_official 579:53297373a894 51 #endif /* _SAMD21_I2S_INSTANCE_ */