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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_gclk.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_GCLK_COMPONENT_ |
mbed_official | 579:53297373a894 | 2 | #define _SAMD21_GCLK_COMPONENT_ |
mbed_official | 579:53297373a894 | 3 | |
mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR GCLK */ |
mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_GCLK Generic Clock Generator */ |
mbed_official | 579:53297373a894 | 8 | /*@{*/ |
mbed_official | 579:53297373a894 | 9 | |
mbed_official | 579:53297373a894 | 10 | #define GCLK_U2102 |
mbed_official | 579:53297373a894 | 11 | #define REV_GCLK 0x210 |
mbed_official | 579:53297373a894 | 12 | |
mbed_official | 579:53297373a894 | 13 | /* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */ |
mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 15 | typedef union { |
mbed_official | 579:53297373a894 | 16 | struct { |
mbed_official | 579:53297373a894 | 17 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 18 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 19 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 20 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 21 | } GCLK_CTRL_Type; |
mbed_official | 579:53297373a894 | 22 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 23 | |
mbed_official | 579:53297373a894 | 24 | #define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */ |
mbed_official | 579:53297373a894 | 25 | #define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */ |
mbed_official | 579:53297373a894 | 26 | |
mbed_official | 579:53297373a894 | 27 | #define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */ |
mbed_official | 579:53297373a894 | 28 | #define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos) |
mbed_official | 579:53297373a894 | 29 | #define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 30 | |
mbed_official | 579:53297373a894 | 31 | /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */ |
mbed_official | 579:53297373a894 | 32 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 33 | typedef union { |
mbed_official | 579:53297373a894 | 34 | struct { |
mbed_official | 579:53297373a894 | 35 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 36 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ |
mbed_official | 579:53297373a894 | 37 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 38 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 39 | } GCLK_STATUS_Type; |
mbed_official | 579:53297373a894 | 40 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 41 | |
mbed_official | 579:53297373a894 | 42 | #define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */ |
mbed_official | 579:53297373a894 | 43 | #define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */ |
mbed_official | 579:53297373a894 | 44 | |
mbed_official | 579:53297373a894 | 45 | #define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */ |
mbed_official | 579:53297373a894 | 46 | #define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos) |
mbed_official | 579:53297373a894 | 47 | #define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 48 | |
mbed_official | 579:53297373a894 | 49 | /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */ |
mbed_official | 579:53297373a894 | 50 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 51 | typedef union { |
mbed_official | 579:53297373a894 | 52 | struct { |
mbed_official | 579:53297373a894 | 53 | uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ |
mbed_official | 579:53297373a894 | 54 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 55 | uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ |
mbed_official | 579:53297373a894 | 56 | uint16_t :2; /*!< bit: 12..13 Reserved */ |
mbed_official | 579:53297373a894 | 57 | uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ |
mbed_official | 579:53297373a894 | 58 | uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ |
mbed_official | 579:53297373a894 | 59 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 60 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 61 | } GCLK_CLKCTRL_Type; |
mbed_official | 579:53297373a894 | 62 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 63 | |
mbed_official | 579:53297373a894 | 64 | #define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */ |
mbed_official | 579:53297373a894 | 65 | #define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */ |
mbed_official | 579:53297373a894 | 66 | |
mbed_official | 579:53297373a894 | 67 | #define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */ |
mbed_official | 579:53297373a894 | 68 | #define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 69 | #define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))) |
mbed_official | 579:53297373a894 | 70 | #define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */ |
mbed_official | 579:53297373a894 | 71 | #define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */ |
mbed_official | 579:53297373a894 | 72 | #define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */ |
mbed_official | 579:53297373a894 | 73 | #define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */ |
mbed_official | 579:53297373a894 | 74 | #define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */ |
mbed_official | 579:53297373a894 | 75 | #define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */ |
mbed_official | 579:53297373a894 | 76 | #define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */ |
mbed_official | 579:53297373a894 | 77 | #define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */ |
mbed_official | 579:53297373a894 | 78 | #define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */ |
mbed_official | 579:53297373a894 | 79 | #define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */ |
mbed_official | 579:53297373a894 | 80 | #define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */ |
mbed_official | 579:53297373a894 | 81 | #define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */ |
mbed_official | 579:53297373a894 | 82 | #define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */ |
mbed_official | 579:53297373a894 | 83 | #define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */ |
mbed_official | 579:53297373a894 | 84 | #define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */ |
mbed_official | 579:53297373a894 | 85 | #define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */ |
mbed_official | 579:53297373a894 | 86 | #define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */ |
mbed_official | 579:53297373a894 | 87 | #define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */ |
mbed_official | 579:53297373a894 | 88 | #define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */ |
mbed_official | 579:53297373a894 | 89 | #define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */ |
mbed_official | 579:53297373a894 | 90 | #define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */ |
mbed_official | 579:53297373a894 | 91 | #define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */ |
mbed_official | 579:53297373a894 | 92 | #define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */ |
mbed_official | 579:53297373a894 | 93 | #define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */ |
mbed_official | 579:53297373a894 | 94 | #define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */ |
mbed_official | 579:53297373a894 | 95 | #define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */ |
mbed_official | 579:53297373a894 | 96 | #define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */ |
mbed_official | 579:53297373a894 | 97 | #define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */ |
mbed_official | 579:53297373a894 | 98 | #define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */ |
mbed_official | 579:53297373a894 | 99 | #define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */ |
mbed_official | 579:53297373a894 | 100 | #define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */ |
mbed_official | 579:53297373a894 | 101 | #define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */ |
mbed_official | 579:53297373a894 | 102 | #define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */ |
mbed_official | 579:53297373a894 | 103 | #define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */ |
mbed_official | 579:53297373a894 | 104 | #define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */ |
mbed_official | 579:53297373a894 | 105 | #define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */ |
mbed_official | 579:53297373a894 | 106 | #define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */ |
mbed_official | 579:53297373a894 | 107 | #define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 108 | #define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 109 | #define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 110 | #define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 111 | #define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 112 | #define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 113 | #define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 114 | #define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 115 | #define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 116 | #define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 117 | #define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 118 | #define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 119 | #define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 120 | #define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 121 | #define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 122 | #define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 123 | #define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 124 | #define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 125 | #define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 126 | #define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 127 | #define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 128 | #define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 129 | #define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 130 | #define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 131 | #define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 132 | #define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 133 | #define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 134 | #define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 135 | #define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 136 | #define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 137 | #define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 138 | #define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 139 | #define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 140 | #define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 141 | #define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 142 | #define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 143 | #define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 144 | #define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */ |
mbed_official | 579:53297373a894 | 145 | #define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 146 | #define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))) |
mbed_official | 579:53297373a894 | 147 | #define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */ |
mbed_official | 579:53297373a894 | 148 | #define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */ |
mbed_official | 579:53297373a894 | 149 | #define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */ |
mbed_official | 579:53297373a894 | 150 | #define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */ |
mbed_official | 579:53297373a894 | 151 | #define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */ |
mbed_official | 579:53297373a894 | 152 | #define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */ |
mbed_official | 579:53297373a894 | 153 | #define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */ |
mbed_official | 579:53297373a894 | 154 | #define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */ |
mbed_official | 579:53297373a894 | 155 | #define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 156 | #define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 157 | #define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 158 | #define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 159 | #define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 160 | #define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 161 | #define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 162 | #define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos) |
mbed_official | 579:53297373a894 | 163 | #define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */ |
mbed_official | 579:53297373a894 | 164 | #define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos) |
mbed_official | 579:53297373a894 | 165 | #define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */ |
mbed_official | 579:53297373a894 | 166 | #define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos) |
mbed_official | 579:53297373a894 | 167 | #define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 168 | |
mbed_official | 579:53297373a894 | 169 | /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */ |
mbed_official | 579:53297373a894 | 170 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 171 | typedef union { |
mbed_official | 579:53297373a894 | 172 | struct { |
mbed_official | 579:53297373a894 | 173 | uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ |
mbed_official | 579:53297373a894 | 174 | uint32_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 175 | uint32_t SRC:5; /*!< bit: 8..12 Source Select */ |
mbed_official | 579:53297373a894 | 176 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
mbed_official | 579:53297373a894 | 177 | uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ |
mbed_official | 579:53297373a894 | 178 | uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ |
mbed_official | 579:53297373a894 | 179 | uint32_t OOV:1; /*!< bit: 18 Output Off Value */ |
mbed_official | 579:53297373a894 | 180 | uint32_t OE:1; /*!< bit: 19 Output Enable */ |
mbed_official | 579:53297373a894 | 181 | uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ |
mbed_official | 579:53297373a894 | 182 | uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ |
mbed_official | 579:53297373a894 | 183 | uint32_t :10; /*!< bit: 22..31 Reserved */ |
mbed_official | 579:53297373a894 | 184 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 185 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 186 | } GCLK_GENCTRL_Type; |
mbed_official | 579:53297373a894 | 187 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 188 | |
mbed_official | 579:53297373a894 | 189 | #define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ |
mbed_official | 579:53297373a894 | 190 | #define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ |
mbed_official | 579:53297373a894 | 191 | |
mbed_official | 579:53297373a894 | 192 | #define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */ |
mbed_official | 579:53297373a894 | 193 | #define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos) |
mbed_official | 579:53297373a894 | 194 | #define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))) |
mbed_official | 579:53297373a894 | 195 | #define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */ |
mbed_official | 579:53297373a894 | 196 | #define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 197 | #define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))) |
mbed_official | 579:53297373a894 | 198 | #define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ |
mbed_official | 579:53297373a894 | 199 | #define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */ |
mbed_official | 579:53297373a894 | 200 | #define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ |
mbed_official | 579:53297373a894 | 201 | #define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ |
mbed_official | 579:53297373a894 | 202 | #define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ |
mbed_official | 579:53297373a894 | 203 | #define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ |
mbed_official | 579:53297373a894 | 204 | #define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */ |
mbed_official | 579:53297373a894 | 205 | #define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */ |
mbed_official | 579:53297373a894 | 206 | #define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */ |
mbed_official | 579:53297373a894 | 207 | #define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 208 | #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 209 | #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 210 | #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 211 | #define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 212 | #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 213 | #define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 214 | #define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 215 | #define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos) |
mbed_official | 579:53297373a894 | 216 | #define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ |
mbed_official | 579:53297373a894 | 217 | #define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos) |
mbed_official | 579:53297373a894 | 218 | #define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ |
mbed_official | 579:53297373a894 | 219 | #define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos) |
mbed_official | 579:53297373a894 | 220 | #define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */ |
mbed_official | 579:53297373a894 | 221 | #define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos) |
mbed_official | 579:53297373a894 | 222 | #define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */ |
mbed_official | 579:53297373a894 | 223 | #define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos) |
mbed_official | 579:53297373a894 | 224 | #define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */ |
mbed_official | 579:53297373a894 | 225 | #define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos) |
mbed_official | 579:53297373a894 | 226 | #define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */ |
mbed_official | 579:53297373a894 | 227 | #define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos) |
mbed_official | 579:53297373a894 | 228 | #define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 229 | |
mbed_official | 579:53297373a894 | 230 | /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */ |
mbed_official | 579:53297373a894 | 231 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 232 | typedef union { |
mbed_official | 579:53297373a894 | 233 | struct { |
mbed_official | 579:53297373a894 | 234 | uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ |
mbed_official | 579:53297373a894 | 235 | uint32_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 236 | uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ |
mbed_official | 579:53297373a894 | 237 | uint32_t :8; /*!< bit: 24..31 Reserved */ |
mbed_official | 579:53297373a894 | 238 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 239 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 240 | } GCLK_GENDIV_Type; |
mbed_official | 579:53297373a894 | 241 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 242 | |
mbed_official | 579:53297373a894 | 243 | #define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */ |
mbed_official | 579:53297373a894 | 244 | #define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */ |
mbed_official | 579:53297373a894 | 245 | |
mbed_official | 579:53297373a894 | 246 | #define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */ |
mbed_official | 579:53297373a894 | 247 | #define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos) |
mbed_official | 579:53297373a894 | 248 | #define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))) |
mbed_official | 579:53297373a894 | 249 | #define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */ |
mbed_official | 579:53297373a894 | 250 | #define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos) |
mbed_official | 579:53297373a894 | 251 | #define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))) |
mbed_official | 579:53297373a894 | 252 | #define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */ |
mbed_official | 579:53297373a894 | 253 | |
mbed_official | 579:53297373a894 | 254 | /** \brief GCLK hardware registers */ |
mbed_official | 579:53297373a894 | 255 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 256 | typedef struct { |
mbed_official | 579:53297373a894 | 257 | __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ |
mbed_official | 579:53297373a894 | 258 | __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ |
mbed_official | 579:53297373a894 | 259 | __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ |
mbed_official | 579:53297373a894 | 260 | __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ |
mbed_official | 579:53297373a894 | 261 | __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ |
mbed_official | 579:53297373a894 | 262 | } Gclk; |
mbed_official | 579:53297373a894 | 263 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 264 | |
mbed_official | 579:53297373a894 | 265 | /*@}*/ |
mbed_official | 579:53297373a894 | 266 | |
mbed_official | 579:53297373a894 | 267 | #endif /* _SAMD21_GCLK_COMPONENT_ */ |