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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_adc.h@592:a274ee790e56, 2015-07-17 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jul 17 09:15:10 2015 +0100
- Revision:
- 592:a274ee790e56
- Parent:
- 579:53297373a894
Synchronized with git revision e7144f83a8d75df80c4877936b6ffe552b0be9e6
Full URL: https://github.com/mbedmicro/mbed/commit/e7144f83a8d75df80c4877936b6ffe552b0be9e6/
More API implementation for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | #ifndef _SAMD21_ADC_COMPONENT_ |
| mbed_official | 579:53297373a894 | 2 | #define _SAMD21_ADC_COMPONENT_ |
| mbed_official | 579:53297373a894 | 3 | |
| mbed_official | 579:53297373a894 | 4 | /* ========================================================================== */ |
| mbed_official | 579:53297373a894 | 5 | /** SOFTWARE API DEFINITION FOR ADC */ |
| mbed_official | 579:53297373a894 | 6 | /* ========================================================================== */ |
| mbed_official | 579:53297373a894 | 7 | /** \addtogroup SAMD21_ADC Analog Digital Converter */ |
| mbed_official | 579:53297373a894 | 8 | /*@{*/ |
| mbed_official | 579:53297373a894 | 9 | |
| mbed_official | 579:53297373a894 | 10 | #define ADC_U2204 |
| mbed_official | 579:53297373a894 | 11 | #define REV_ADC 0x120 |
| mbed_official | 579:53297373a894 | 12 | |
| mbed_official | 579:53297373a894 | 13 | /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ |
| mbed_official | 579:53297373a894 | 14 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 15 | typedef union { |
| mbed_official | 579:53297373a894 | 16 | struct { |
| mbed_official | 579:53297373a894 | 17 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
| mbed_official | 579:53297373a894 | 18 | uint8_t ENABLE:1; /*!< bit: 1 Enable */ |
| mbed_official | 579:53297373a894 | 19 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ |
| mbed_official | 579:53297373a894 | 20 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 21 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 22 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 23 | } ADC_CTRLA_Type; |
| mbed_official | 579:53297373a894 | 24 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 25 | |
| mbed_official | 579:53297373a894 | 26 | #define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ |
| mbed_official | 579:53297373a894 | 27 | #define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ |
| mbed_official | 579:53297373a894 | 28 | |
| mbed_official | 579:53297373a894 | 29 | #define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ |
| mbed_official | 579:53297373a894 | 30 | #define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) |
| mbed_official | 579:53297373a894 | 31 | #define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ |
| mbed_official | 579:53297373a894 | 32 | #define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) |
| mbed_official | 579:53297373a894 | 33 | #define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ |
| mbed_official | 579:53297373a894 | 34 | #define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) |
| mbed_official | 579:53297373a894 | 35 | #define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */ |
| mbed_official | 579:53297373a894 | 36 | |
| mbed_official | 579:53297373a894 | 37 | /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ |
| mbed_official | 579:53297373a894 | 38 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 39 | typedef union { |
| mbed_official | 579:53297373a894 | 40 | struct { |
| mbed_official | 579:53297373a894 | 41 | uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ |
| mbed_official | 579:53297373a894 | 42 | uint8_t :3; /*!< bit: 4.. 6 Reserved */ |
| mbed_official | 579:53297373a894 | 43 | uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ |
| mbed_official | 579:53297373a894 | 44 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 45 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 46 | } ADC_REFCTRL_Type; |
| mbed_official | 579:53297373a894 | 47 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 48 | |
| mbed_official | 579:53297373a894 | 49 | #define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ |
| mbed_official | 579:53297373a894 | 50 | #define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ |
| mbed_official | 579:53297373a894 | 51 | |
| mbed_official | 579:53297373a894 | 52 | #define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ |
| mbed_official | 579:53297373a894 | 53 | #define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 579:53297373a894 | 54 | #define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))) |
| mbed_official | 579:53297373a894 | 55 | #define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ |
| mbed_official | 579:53297373a894 | 56 | #define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ |
| mbed_official | 579:53297373a894 | 57 | #define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ |
| mbed_official | 579:53297373a894 | 58 | #define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */ |
| mbed_official | 579:53297373a894 | 59 | #define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */ |
| mbed_official | 579:53297373a894 | 60 | #define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 579:53297373a894 | 61 | #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 579:53297373a894 | 62 | #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 579:53297373a894 | 63 | #define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 579:53297373a894 | 64 | #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 579:53297373a894 | 65 | #define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ |
| mbed_official | 579:53297373a894 | 66 | #define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) |
| mbed_official | 579:53297373a894 | 67 | #define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 68 | |
| mbed_official | 579:53297373a894 | 69 | /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ |
| mbed_official | 579:53297373a894 | 70 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 71 | typedef union { |
| mbed_official | 579:53297373a894 | 72 | struct { |
| mbed_official | 579:53297373a894 | 73 | uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ |
| mbed_official | 579:53297373a894 | 74 | uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ |
| mbed_official | 579:53297373a894 | 75 | uint8_t :1; /*!< bit: 7 Reserved */ |
| mbed_official | 579:53297373a894 | 76 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 77 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 78 | } ADC_AVGCTRL_Type; |
| mbed_official | 579:53297373a894 | 79 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 80 | |
| mbed_official | 579:53297373a894 | 81 | #define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ |
| mbed_official | 579:53297373a894 | 82 | #define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ |
| mbed_official | 579:53297373a894 | 83 | |
| mbed_official | 579:53297373a894 | 84 | #define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ |
| mbed_official | 579:53297373a894 | 85 | #define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 86 | #define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))) |
| mbed_official | 579:53297373a894 | 87 | #define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ |
| mbed_official | 579:53297373a894 | 88 | #define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ |
| mbed_official | 579:53297373a894 | 89 | #define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ |
| mbed_official | 579:53297373a894 | 90 | #define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ |
| mbed_official | 579:53297373a894 | 91 | #define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ |
| mbed_official | 579:53297373a894 | 92 | #define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ |
| mbed_official | 579:53297373a894 | 93 | #define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ |
| mbed_official | 579:53297373a894 | 94 | #define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ |
| mbed_official | 579:53297373a894 | 95 | #define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ |
| mbed_official | 579:53297373a894 | 96 | #define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ |
| mbed_official | 579:53297373a894 | 97 | #define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ |
| mbed_official | 579:53297373a894 | 98 | #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 99 | #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 100 | #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 101 | #define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 102 | #define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 103 | #define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 104 | #define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 105 | #define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 106 | #define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 107 | #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 108 | #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 579:53297373a894 | 109 | #define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ |
| mbed_official | 579:53297373a894 | 110 | #define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) |
| mbed_official | 579:53297373a894 | 111 | #define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))) |
| mbed_official | 579:53297373a894 | 112 | #define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 113 | |
| mbed_official | 579:53297373a894 | 114 | /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ |
| mbed_official | 579:53297373a894 | 115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 116 | typedef union { |
| mbed_official | 579:53297373a894 | 117 | struct { |
| mbed_official | 579:53297373a894 | 118 | uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ |
| mbed_official | 579:53297373a894 | 119 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 120 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 121 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 122 | } ADC_SAMPCTRL_Type; |
| mbed_official | 579:53297373a894 | 123 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 124 | |
| mbed_official | 579:53297373a894 | 125 | #define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ |
| mbed_official | 579:53297373a894 | 126 | #define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ |
| mbed_official | 579:53297373a894 | 127 | |
| mbed_official | 579:53297373a894 | 128 | #define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ |
| mbed_official | 579:53297373a894 | 129 | #define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) |
| mbed_official | 579:53297373a894 | 130 | #define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))) |
| mbed_official | 579:53297373a894 | 131 | #define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 132 | |
| mbed_official | 579:53297373a894 | 133 | /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ |
| mbed_official | 579:53297373a894 | 134 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 135 | typedef union { |
| mbed_official | 579:53297373a894 | 136 | struct { |
| mbed_official | 579:53297373a894 | 137 | uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ |
| mbed_official | 579:53297373a894 | 138 | uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ |
| mbed_official | 579:53297373a894 | 139 | uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ |
| mbed_official | 579:53297373a894 | 140 | uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ |
| mbed_official | 579:53297373a894 | 141 | uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ |
| mbed_official | 579:53297373a894 | 142 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 143 | uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ |
| mbed_official | 579:53297373a894 | 144 | uint16_t :5; /*!< bit: 11..15 Reserved */ |
| mbed_official | 579:53297373a894 | 145 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 146 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 147 | } ADC_CTRLB_Type; |
| mbed_official | 579:53297373a894 | 148 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 149 | |
| mbed_official | 579:53297373a894 | 150 | #define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ |
| mbed_official | 579:53297373a894 | 151 | #define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */ |
| mbed_official | 579:53297373a894 | 152 | |
| mbed_official | 579:53297373a894 | 153 | #define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ |
| mbed_official | 579:53297373a894 | 154 | #define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos) |
| mbed_official | 579:53297373a894 | 155 | #define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ |
| mbed_official | 579:53297373a894 | 156 | #define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos) |
| mbed_official | 579:53297373a894 | 157 | #define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ |
| mbed_official | 579:53297373a894 | 158 | #define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos) |
| mbed_official | 579:53297373a894 | 159 | #define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ |
| mbed_official | 579:53297373a894 | 160 | #define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos) |
| mbed_official | 579:53297373a894 | 161 | #define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ |
| mbed_official | 579:53297373a894 | 162 | #define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 579:53297373a894 | 163 | #define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))) |
| mbed_official | 579:53297373a894 | 164 | #define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */ |
| mbed_official | 579:53297373a894 | 165 | #define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */ |
| mbed_official | 579:53297373a894 | 166 | #define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */ |
| mbed_official | 579:53297373a894 | 167 | #define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */ |
| mbed_official | 579:53297373a894 | 168 | #define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 579:53297373a894 | 169 | #define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 579:53297373a894 | 170 | #define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 579:53297373a894 | 171 | #define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 579:53297373a894 | 172 | #define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ |
| mbed_official | 579:53297373a894 | 173 | #define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 174 | #define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))) |
| mbed_official | 579:53297373a894 | 175 | #define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ |
| mbed_official | 579:53297373a894 | 176 | #define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ |
| mbed_official | 579:53297373a894 | 177 | #define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ |
| mbed_official | 579:53297373a894 | 178 | #define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ |
| mbed_official | 579:53297373a894 | 179 | #define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ |
| mbed_official | 579:53297373a894 | 180 | #define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ |
| mbed_official | 579:53297373a894 | 181 | #define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ |
| mbed_official | 579:53297373a894 | 182 | #define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ |
| mbed_official | 579:53297373a894 | 183 | #define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 184 | #define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 185 | #define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 186 | #define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 187 | #define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 188 | #define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 189 | #define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 190 | #define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 579:53297373a894 | 191 | #define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */ |
| mbed_official | 579:53297373a894 | 192 | |
| mbed_official | 579:53297373a894 | 193 | /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ |
| mbed_official | 579:53297373a894 | 194 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 195 | typedef union { |
| mbed_official | 579:53297373a894 | 196 | struct { |
| mbed_official | 579:53297373a894 | 197 | uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ |
| mbed_official | 579:53297373a894 | 198 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 199 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 200 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 201 | } ADC_WINCTRL_Type; |
| mbed_official | 579:53297373a894 | 202 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 203 | |
| mbed_official | 579:53297373a894 | 204 | #define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ |
| mbed_official | 579:53297373a894 | 205 | #define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ |
| mbed_official | 579:53297373a894 | 206 | |
| mbed_official | 579:53297373a894 | 207 | #define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ |
| mbed_official | 579:53297373a894 | 208 | #define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 579:53297373a894 | 209 | #define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))) |
| mbed_official | 579:53297373a894 | 210 | #define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */ |
| mbed_official | 579:53297373a894 | 211 | #define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ |
| mbed_official | 579:53297373a894 | 212 | #define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ |
| mbed_official | 579:53297373a894 | 213 | #define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ |
| mbed_official | 579:53297373a894 | 214 | #define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ |
| mbed_official | 579:53297373a894 | 215 | #define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 579:53297373a894 | 216 | #define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 579:53297373a894 | 217 | #define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 579:53297373a894 | 218 | #define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 579:53297373a894 | 219 | #define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 579:53297373a894 | 220 | #define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 221 | |
| mbed_official | 579:53297373a894 | 222 | /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ |
| mbed_official | 579:53297373a894 | 223 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 224 | typedef union { |
| mbed_official | 579:53297373a894 | 225 | struct { |
| mbed_official | 579:53297373a894 | 226 | uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ |
| mbed_official | 579:53297373a894 | 227 | uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ |
| mbed_official | 579:53297373a894 | 228 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 229 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 230 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 231 | } ADC_SWTRIG_Type; |
| mbed_official | 579:53297373a894 | 232 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 233 | |
| mbed_official | 579:53297373a894 | 234 | #define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ |
| mbed_official | 579:53297373a894 | 235 | #define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ |
| mbed_official | 579:53297373a894 | 236 | |
| mbed_official | 579:53297373a894 | 237 | #define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ |
| mbed_official | 579:53297373a894 | 238 | #define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) |
| mbed_official | 579:53297373a894 | 239 | #define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ |
| mbed_official | 579:53297373a894 | 240 | #define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) |
| mbed_official | 579:53297373a894 | 241 | #define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ |
| mbed_official | 579:53297373a894 | 242 | |
| mbed_official | 579:53297373a894 | 243 | /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ |
| mbed_official | 579:53297373a894 | 244 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 245 | typedef union { |
| mbed_official | 579:53297373a894 | 246 | struct { |
| mbed_official | 579:53297373a894 | 247 | uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ |
| mbed_official | 579:53297373a894 | 248 | uint32_t :3; /*!< bit: 5.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 249 | uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ |
| mbed_official | 579:53297373a894 | 250 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
| mbed_official | 579:53297373a894 | 251 | uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ |
| mbed_official | 579:53297373a894 | 252 | uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ |
| mbed_official | 579:53297373a894 | 253 | uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ |
| mbed_official | 579:53297373a894 | 254 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
| mbed_official | 579:53297373a894 | 255 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 256 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 257 | } ADC_INPUTCTRL_Type; |
| mbed_official | 579:53297373a894 | 258 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 259 | |
| mbed_official | 579:53297373a894 | 260 | #define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ |
| mbed_official | 579:53297373a894 | 261 | #define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ |
| mbed_official | 579:53297373a894 | 262 | |
| mbed_official | 579:53297373a894 | 263 | #define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ |
| mbed_official | 579:53297373a894 | 264 | #define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 265 | #define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))) |
| mbed_official | 579:53297373a894 | 266 | #define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ |
| mbed_official | 579:53297373a894 | 267 | #define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ |
| mbed_official | 579:53297373a894 | 268 | #define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ |
| mbed_official | 579:53297373a894 | 269 | #define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ |
| mbed_official | 579:53297373a894 | 270 | #define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ |
| mbed_official | 579:53297373a894 | 271 | #define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ |
| mbed_official | 579:53297373a894 | 272 | #define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ |
| mbed_official | 579:53297373a894 | 273 | #define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ |
| mbed_official | 579:53297373a894 | 274 | #define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ |
| mbed_official | 579:53297373a894 | 275 | #define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ |
| mbed_official | 579:53297373a894 | 276 | #define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ |
| mbed_official | 579:53297373a894 | 277 | #define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ |
| mbed_official | 579:53297373a894 | 278 | #define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ |
| mbed_official | 579:53297373a894 | 279 | #define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ |
| mbed_official | 579:53297373a894 | 280 | #define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ |
| mbed_official | 579:53297373a894 | 281 | #define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ |
| mbed_official | 579:53297373a894 | 282 | #define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ |
| mbed_official | 579:53297373a894 | 283 | #define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ |
| mbed_official | 579:53297373a894 | 284 | #define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ |
| mbed_official | 579:53297373a894 | 285 | #define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ |
| mbed_official | 579:53297373a894 | 286 | #define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */ |
| mbed_official | 579:53297373a894 | 287 | #define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ |
| mbed_official | 579:53297373a894 | 288 | #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ |
| mbed_official | 579:53297373a894 | 289 | #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ |
| mbed_official | 579:53297373a894 | 290 | #define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ |
| mbed_official | 579:53297373a894 | 291 | #define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 292 | #define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 293 | #define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 294 | #define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 295 | #define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 296 | #define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 297 | #define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 298 | #define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 299 | #define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 300 | #define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 301 | #define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 302 | #define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 303 | #define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 304 | #define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 305 | #define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 306 | #define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 307 | #define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 308 | #define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 309 | #define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 310 | #define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 311 | #define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 312 | #define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 313 | #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 314 | #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 315 | #define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 579:53297373a894 | 316 | #define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ |
| mbed_official | 579:53297373a894 | 317 | #define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 318 | #define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))) |
| mbed_official | 579:53297373a894 | 319 | #define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ |
| mbed_official | 579:53297373a894 | 320 | #define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ |
| mbed_official | 579:53297373a894 | 321 | #define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ |
| mbed_official | 579:53297373a894 | 322 | #define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ |
| mbed_official | 579:53297373a894 | 323 | #define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ |
| mbed_official | 579:53297373a894 | 324 | #define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ |
| mbed_official | 579:53297373a894 | 325 | #define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ |
| mbed_official | 579:53297373a894 | 326 | #define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ |
| mbed_official | 579:53297373a894 | 327 | #define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */ |
| mbed_official | 579:53297373a894 | 328 | #define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */ |
| mbed_official | 579:53297373a894 | 329 | #define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 330 | #define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 331 | #define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 332 | #define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 333 | #define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 334 | #define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 335 | #define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 336 | #define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 337 | #define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 338 | #define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 579:53297373a894 | 339 | #define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ |
| mbed_official | 579:53297373a894 | 340 | #define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos) |
| mbed_official | 579:53297373a894 | 341 | #define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))) |
| mbed_official | 579:53297373a894 | 342 | #define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ |
| mbed_official | 579:53297373a894 | 343 | #define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
| mbed_official | 579:53297373a894 | 344 | #define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))) |
| mbed_official | 579:53297373a894 | 345 | #define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ |
| mbed_official | 579:53297373a894 | 346 | #define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 579:53297373a894 | 347 | #define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))) |
| mbed_official | 579:53297373a894 | 348 | #define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */ |
| mbed_official | 579:53297373a894 | 349 | #define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */ |
| mbed_official | 579:53297373a894 | 350 | #define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */ |
| mbed_official | 579:53297373a894 | 351 | #define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */ |
| mbed_official | 579:53297373a894 | 352 | #define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */ |
| mbed_official | 579:53297373a894 | 353 | #define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */ |
| mbed_official | 579:53297373a894 | 354 | #define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 579:53297373a894 | 355 | #define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 579:53297373a894 | 356 | #define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 579:53297373a894 | 357 | #define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 579:53297373a894 | 358 | #define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 579:53297373a894 | 359 | #define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 579:53297373a894 | 360 | #define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 361 | |
| mbed_official | 579:53297373a894 | 362 | /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ |
| mbed_official | 579:53297373a894 | 363 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 364 | typedef union { |
| mbed_official | 579:53297373a894 | 365 | struct { |
| mbed_official | 579:53297373a894 | 366 | uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ |
| mbed_official | 579:53297373a894 | 367 | uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ |
| mbed_official | 579:53297373a894 | 368 | uint8_t :2; /*!< bit: 2.. 3 Reserved */ |
| mbed_official | 579:53297373a894 | 369 | uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ |
| mbed_official | 579:53297373a894 | 370 | uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ |
| mbed_official | 579:53297373a894 | 371 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 372 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 373 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 374 | } ADC_EVCTRL_Type; |
| mbed_official | 579:53297373a894 | 375 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 376 | |
| mbed_official | 579:53297373a894 | 377 | #define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ |
| mbed_official | 579:53297373a894 | 378 | #define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ |
| mbed_official | 579:53297373a894 | 379 | |
| mbed_official | 579:53297373a894 | 380 | #define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ |
| mbed_official | 579:53297373a894 | 381 | #define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) |
| mbed_official | 579:53297373a894 | 382 | #define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ |
| mbed_official | 579:53297373a894 | 383 | #define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos) |
| mbed_official | 579:53297373a894 | 384 | #define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ |
| mbed_official | 579:53297373a894 | 385 | #define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) |
| mbed_official | 579:53297373a894 | 386 | #define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ |
| mbed_official | 579:53297373a894 | 387 | #define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) |
| mbed_official | 579:53297373a894 | 388 | #define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 389 | |
| mbed_official | 579:53297373a894 | 390 | /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ |
| mbed_official | 579:53297373a894 | 391 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 392 | typedef union { |
| mbed_official | 579:53297373a894 | 393 | struct { |
| mbed_official | 579:53297373a894 | 394 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 395 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 396 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 397 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 398 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 399 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 400 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 401 | } ADC_INTENCLR_Type; |
| mbed_official | 579:53297373a894 | 402 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 403 | |
| mbed_official | 579:53297373a894 | 404 | #define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 405 | #define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 406 | |
| mbed_official | 579:53297373a894 | 407 | #define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 408 | #define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) |
| mbed_official | 579:53297373a894 | 409 | #define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 410 | #define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) |
| mbed_official | 579:53297373a894 | 411 | #define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 412 | #define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) |
| mbed_official | 579:53297373a894 | 413 | #define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 414 | #define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos) |
| mbed_official | 579:53297373a894 | 415 | #define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */ |
| mbed_official | 579:53297373a894 | 416 | |
| mbed_official | 579:53297373a894 | 417 | /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ |
| mbed_official | 579:53297373a894 | 418 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 419 | typedef union { |
| mbed_official | 579:53297373a894 | 420 | struct { |
| mbed_official | 579:53297373a894 | 421 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 422 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 423 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 424 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 425 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 426 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 427 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 428 | } ADC_INTENSET_Type; |
| mbed_official | 579:53297373a894 | 429 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 430 | |
| mbed_official | 579:53297373a894 | 431 | #define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 432 | #define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 433 | |
| mbed_official | 579:53297373a894 | 434 | #define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 435 | #define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) |
| mbed_official | 579:53297373a894 | 436 | #define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 437 | #define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) |
| mbed_official | 579:53297373a894 | 438 | #define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 439 | #define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) |
| mbed_official | 579:53297373a894 | 440 | #define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ |
| mbed_official | 579:53297373a894 | 441 | #define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos) |
| mbed_official | 579:53297373a894 | 442 | #define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */ |
| mbed_official | 579:53297373a894 | 443 | |
| mbed_official | 579:53297373a894 | 444 | /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ |
| mbed_official | 579:53297373a894 | 445 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 446 | typedef union { |
| mbed_official | 579:53297373a894 | 447 | struct { |
| mbed_official | 579:53297373a894 | 448 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ |
| mbed_official | 579:53297373a894 | 449 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ |
| mbed_official | 579:53297373a894 | 450 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ |
| mbed_official | 579:53297373a894 | 451 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ |
| mbed_official | 579:53297373a894 | 452 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 453 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 454 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 455 | } ADC_INTFLAG_Type; |
| mbed_official | 579:53297373a894 | 456 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 457 | |
| mbed_official | 579:53297373a894 | 458 | #define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 459 | #define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 460 | |
| mbed_official | 579:53297373a894 | 461 | #define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ |
| mbed_official | 579:53297373a894 | 462 | #define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) |
| mbed_official | 579:53297373a894 | 463 | #define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ |
| mbed_official | 579:53297373a894 | 464 | #define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) |
| mbed_official | 579:53297373a894 | 465 | #define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ |
| mbed_official | 579:53297373a894 | 466 | #define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) |
| mbed_official | 579:53297373a894 | 467 | #define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ |
| mbed_official | 579:53297373a894 | 468 | #define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos) |
| mbed_official | 579:53297373a894 | 469 | #define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */ |
| mbed_official | 579:53297373a894 | 470 | |
| mbed_official | 579:53297373a894 | 471 | /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ |
| mbed_official | 579:53297373a894 | 472 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 473 | typedef union { |
| mbed_official | 579:53297373a894 | 474 | struct { |
| mbed_official | 579:53297373a894 | 475 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
| mbed_official | 579:53297373a894 | 476 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ |
| mbed_official | 579:53297373a894 | 477 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 478 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 479 | } ADC_STATUS_Type; |
| mbed_official | 579:53297373a894 | 480 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 481 | |
| mbed_official | 579:53297373a894 | 482 | #define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ |
| mbed_official | 579:53297373a894 | 483 | #define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */ |
| mbed_official | 579:53297373a894 | 484 | |
| mbed_official | 579:53297373a894 | 485 | #define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ |
| mbed_official | 579:53297373a894 | 486 | #define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos) |
| mbed_official | 579:53297373a894 | 487 | #define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */ |
| mbed_official | 579:53297373a894 | 488 | |
| mbed_official | 579:53297373a894 | 489 | /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ |
| mbed_official | 579:53297373a894 | 490 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 491 | typedef union { |
| mbed_official | 579:53297373a894 | 492 | struct { |
| mbed_official | 579:53297373a894 | 493 | uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ |
| mbed_official | 579:53297373a894 | 494 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 495 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 496 | } ADC_RESULT_Type; |
| mbed_official | 579:53297373a894 | 497 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 498 | |
| mbed_official | 579:53297373a894 | 499 | #define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ |
| mbed_official | 579:53297373a894 | 500 | #define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ |
| mbed_official | 579:53297373a894 | 501 | |
| mbed_official | 579:53297373a894 | 502 | #define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ |
| mbed_official | 579:53297373a894 | 503 | #define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) |
| mbed_official | 579:53297373a894 | 504 | #define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))) |
| mbed_official | 579:53297373a894 | 505 | #define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ |
| mbed_official | 579:53297373a894 | 506 | |
| mbed_official | 579:53297373a894 | 507 | /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ |
| mbed_official | 579:53297373a894 | 508 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 509 | typedef union { |
| mbed_official | 579:53297373a894 | 510 | struct { |
| mbed_official | 579:53297373a894 | 511 | uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ |
| mbed_official | 579:53297373a894 | 512 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 513 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 514 | } ADC_WINLT_Type; |
| mbed_official | 579:53297373a894 | 515 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 516 | |
| mbed_official | 579:53297373a894 | 517 | #define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ |
| mbed_official | 579:53297373a894 | 518 | #define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ |
| mbed_official | 579:53297373a894 | 519 | |
| mbed_official | 579:53297373a894 | 520 | #define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ |
| mbed_official | 579:53297373a894 | 521 | #define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) |
| mbed_official | 579:53297373a894 | 522 | #define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))) |
| mbed_official | 579:53297373a894 | 523 | #define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ |
| mbed_official | 579:53297373a894 | 524 | |
| mbed_official | 579:53297373a894 | 525 | /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ |
| mbed_official | 579:53297373a894 | 526 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 527 | typedef union { |
| mbed_official | 579:53297373a894 | 528 | struct { |
| mbed_official | 579:53297373a894 | 529 | uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ |
| mbed_official | 579:53297373a894 | 530 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 531 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 532 | } ADC_WINUT_Type; |
| mbed_official | 579:53297373a894 | 533 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 534 | |
| mbed_official | 579:53297373a894 | 535 | #define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ |
| mbed_official | 579:53297373a894 | 536 | #define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ |
| mbed_official | 579:53297373a894 | 537 | |
| mbed_official | 579:53297373a894 | 538 | #define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ |
| mbed_official | 579:53297373a894 | 539 | #define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) |
| mbed_official | 579:53297373a894 | 540 | #define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))) |
| mbed_official | 579:53297373a894 | 541 | #define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ |
| mbed_official | 579:53297373a894 | 542 | |
| mbed_official | 579:53297373a894 | 543 | /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ |
| mbed_official | 579:53297373a894 | 544 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 545 | typedef union { |
| mbed_official | 579:53297373a894 | 546 | struct { |
| mbed_official | 579:53297373a894 | 547 | uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ |
| mbed_official | 579:53297373a894 | 548 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
| mbed_official | 579:53297373a894 | 549 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 550 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 551 | } ADC_GAINCORR_Type; |
| mbed_official | 579:53297373a894 | 552 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 553 | |
| mbed_official | 579:53297373a894 | 554 | #define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ |
| mbed_official | 579:53297373a894 | 555 | #define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ |
| mbed_official | 579:53297373a894 | 556 | |
| mbed_official | 579:53297373a894 | 557 | #define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ |
| mbed_official | 579:53297373a894 | 558 | #define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) |
| mbed_official | 579:53297373a894 | 559 | #define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))) |
| mbed_official | 579:53297373a894 | 560 | #define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ |
| mbed_official | 579:53297373a894 | 561 | |
| mbed_official | 579:53297373a894 | 562 | /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ |
| mbed_official | 579:53297373a894 | 563 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 564 | typedef union { |
| mbed_official | 579:53297373a894 | 565 | struct { |
| mbed_official | 579:53297373a894 | 566 | uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ |
| mbed_official | 579:53297373a894 | 567 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
| mbed_official | 579:53297373a894 | 568 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 569 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 570 | } ADC_OFFSETCORR_Type; |
| mbed_official | 579:53297373a894 | 571 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 572 | |
| mbed_official | 579:53297373a894 | 573 | #define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ |
| mbed_official | 579:53297373a894 | 574 | #define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ |
| mbed_official | 579:53297373a894 | 575 | |
| mbed_official | 579:53297373a894 | 576 | #define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ |
| mbed_official | 579:53297373a894 | 577 | #define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) |
| mbed_official | 579:53297373a894 | 578 | #define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))) |
| mbed_official | 579:53297373a894 | 579 | #define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ |
| mbed_official | 579:53297373a894 | 580 | |
| mbed_official | 579:53297373a894 | 581 | /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ |
| mbed_official | 579:53297373a894 | 582 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 583 | typedef union { |
| mbed_official | 579:53297373a894 | 584 | struct { |
| mbed_official | 579:53297373a894 | 585 | uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ |
| mbed_official | 579:53297373a894 | 586 | uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ |
| mbed_official | 579:53297373a894 | 587 | uint16_t :5; /*!< bit: 11..15 Reserved */ |
| mbed_official | 579:53297373a894 | 588 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 589 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 590 | } ADC_CALIB_Type; |
| mbed_official | 579:53297373a894 | 591 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 592 | |
| mbed_official | 579:53297373a894 | 593 | #define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ |
| mbed_official | 579:53297373a894 | 594 | #define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ |
| mbed_official | 579:53297373a894 | 595 | |
| mbed_official | 579:53297373a894 | 596 | #define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ |
| mbed_official | 579:53297373a894 | 597 | #define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos) |
| mbed_official | 579:53297373a894 | 598 | #define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))) |
| mbed_official | 579:53297373a894 | 599 | #define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ |
| mbed_official | 579:53297373a894 | 600 | #define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos) |
| mbed_official | 579:53297373a894 | 601 | #define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))) |
| mbed_official | 579:53297373a894 | 602 | #define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */ |
| mbed_official | 579:53297373a894 | 603 | |
| mbed_official | 579:53297373a894 | 604 | /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ |
| mbed_official | 579:53297373a894 | 605 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 606 | typedef union { |
| mbed_official | 579:53297373a894 | 607 | struct { |
| mbed_official | 579:53297373a894 | 608 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ |
| mbed_official | 579:53297373a894 | 609 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| mbed_official | 579:53297373a894 | 610 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 579:53297373a894 | 611 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 579:53297373a894 | 612 | } ADC_DBGCTRL_Type; |
| mbed_official | 579:53297373a894 | 613 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 614 | |
| mbed_official | 579:53297373a894 | 615 | #define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ |
| mbed_official | 579:53297373a894 | 616 | #define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ |
| mbed_official | 579:53297373a894 | 617 | |
| mbed_official | 579:53297373a894 | 618 | #define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ |
| mbed_official | 579:53297373a894 | 619 | #define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) |
| mbed_official | 579:53297373a894 | 620 | #define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ |
| mbed_official | 579:53297373a894 | 621 | |
| mbed_official | 579:53297373a894 | 622 | /** \brief ADC hardware registers */ |
| mbed_official | 579:53297373a894 | 623 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 579:53297373a894 | 624 | typedef struct { |
| mbed_official | 579:53297373a894 | 625 | __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ |
| mbed_official | 579:53297373a894 | 626 | __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ |
| mbed_official | 579:53297373a894 | 627 | __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ |
| mbed_official | 579:53297373a894 | 628 | __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ |
| mbed_official | 579:53297373a894 | 629 | __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ |
| mbed_official | 579:53297373a894 | 630 | RoReg8 Reserved1[0x2]; |
| mbed_official | 579:53297373a894 | 631 | __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ |
| mbed_official | 579:53297373a894 | 632 | RoReg8 Reserved2[0x3]; |
| mbed_official | 579:53297373a894 | 633 | __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ |
| mbed_official | 579:53297373a894 | 634 | RoReg8 Reserved3[0x3]; |
| mbed_official | 579:53297373a894 | 635 | __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ |
| mbed_official | 579:53297373a894 | 636 | __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ |
| mbed_official | 579:53297373a894 | 637 | RoReg8 Reserved4[0x1]; |
| mbed_official | 579:53297373a894 | 638 | __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ |
| mbed_official | 579:53297373a894 | 639 | __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ |
| mbed_official | 579:53297373a894 | 640 | __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ |
| mbed_official | 579:53297373a894 | 641 | __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ |
| mbed_official | 579:53297373a894 | 642 | __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ |
| mbed_official | 579:53297373a894 | 643 | __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ |
| mbed_official | 579:53297373a894 | 644 | RoReg8 Reserved5[0x2]; |
| mbed_official | 579:53297373a894 | 645 | __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ |
| mbed_official | 579:53297373a894 | 646 | RoReg8 Reserved6[0x2]; |
| mbed_official | 579:53297373a894 | 647 | __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ |
| mbed_official | 579:53297373a894 | 648 | __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ |
| mbed_official | 579:53297373a894 | 649 | __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ |
| mbed_official | 579:53297373a894 | 650 | __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ |
| mbed_official | 579:53297373a894 | 651 | } Adc; |
| mbed_official | 579:53297373a894 | 652 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 579:53297373a894 | 653 | |
| mbed_official | 579:53297373a894 | 654 | /*@}*/ |
| mbed_official | 579:53297373a894 | 655 | |
| mbed_official | 579:53297373a894 | 656 | #endif /* _SAMD21_ADC_COMPONENT_ */ |
