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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h@600:7d17ca308cd1, 2015-07-31 (annotated)

Committer:
mbed_official
Date:
Fri Jul 31 14:15:09 2015 +0100
Revision:
600:7d17ca308cd1
Parent:
390:35c2c1cf29cd 
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0



Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/



Enable LPC8xx usart when configuring it

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 2 * DISCLAIMER
mbed_official 390:35c2c1cf29cd 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 390:35c2c1cf29cd 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 390:35c2c1cf29cd 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 390:35c2c1cf29cd 6 * all applicable laws, including copyright laws.
mbed_official 390:35c2c1cf29cd 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 390:35c2c1cf29cd 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 390:35c2c1cf29cd 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 390:35c2c1cf29cd 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 390:35c2c1cf29cd 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 390:35c2c1cf29cd 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 390:35c2c1cf29cd 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 390:35c2c1cf29cd 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 390:35c2c1cf29cd 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 390:35c2c1cf29cd 17 * and to discontinue the availability of this software. By using this software,
mbed_official 390:35c2c1cf29cd 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 390:35c2c1cf29cd 19 * following link:
mbed_official 390:35c2c1cf29cd 20 * http://www.renesas.com/disclaimer*
mbed_official 390:35c2c1cf29cd 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 390:35c2c1cf29cd 22 *******************************************************************************/
mbed_official 390:35c2c1cf29cd 23 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 24 * File Name : spibsc_iodefine.h
mbed_official 390:35c2c1cf29cd 25 * $Rev: $
mbed_official 390:35c2c1cf29cd 26 * $Date:: $
mbed_official 390:35c2c1cf29cd 27 * Description : Definition of I/O Register (V1.00a)
mbed_official 390:35c2c1cf29cd 28 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 29 #ifndef SPIBSC_IODEFINE_H
mbed_official 390:35c2c1cf29cd 30 #define SPIBSC_IODEFINE_H
mbed_official 390:35c2c1cf29cd 31 /* ->SEC M1.10.1 : Not magic number */
mbed_official 390:35c2c1cf29cd 32
mbed_official 390:35c2c1cf29cd 33 struct st_spibsc
mbed_official 390:35c2c1cf29cd 34 { /* SPIBSC */
mbed_official 390:35c2c1cf29cd 35 volatile uint32_t CMNCR; /* CMNCR */
mbed_official 390:35c2c1cf29cd 36 volatile uint32_t SSLDR; /* SSLDR */
mbed_official 390:35c2c1cf29cd 37 volatile uint32_t SPBCR; /* SPBCR */
mbed_official 390:35c2c1cf29cd 38 volatile uint32_t DRCR; /* DRCR */
mbed_official 390:35c2c1cf29cd 39 volatile uint32_t DRCMR; /* DRCMR */
mbed_official 390:35c2c1cf29cd 40 volatile uint32_t DREAR; /* DREAR */
mbed_official 390:35c2c1cf29cd 41 volatile uint32_t DROPR; /* DROPR */
mbed_official 390:35c2c1cf29cd 42 volatile uint32_t DRENR; /* DRENR */
mbed_official 390:35c2c1cf29cd 43 volatile uint32_t SMCR; /* SMCR */
mbed_official 390:35c2c1cf29cd 44 volatile uint32_t SMCMR; /* SMCMR */
mbed_official 390:35c2c1cf29cd 45 volatile uint32_t SMADR; /* SMADR */
mbed_official 390:35c2c1cf29cd 46 volatile uint32_t SMOPR; /* SMOPR */
mbed_official 390:35c2c1cf29cd 47 volatile uint32_t SMENR; /* SMENR */
mbed_official 390:35c2c1cf29cd 48 volatile uint8_t dummy1[4]; /* */
mbed_official 390:35c2c1cf29cd 49 union iodefine_reg32_t SMRDR0; /* SMRDR0 */
mbed_official 390:35c2c1cf29cd 50 union iodefine_reg32_t SMRDR1; /* SMRDR1 */
mbed_official 390:35c2c1cf29cd 51 union iodefine_reg32_t SMWDR0; /* SMWDR0 */
mbed_official 390:35c2c1cf29cd 52 union iodefine_reg32_t SMWDR1; /* SMWDR1 */
mbed_official 390:35c2c1cf29cd 53
mbed_official 390:35c2c1cf29cd 54 volatile uint32_t CMNSR; /* CMNSR */
mbed_official 390:35c2c1cf29cd 55 volatile uint8_t dummy2[12]; /* */
mbed_official 390:35c2c1cf29cd 56 volatile uint32_t DRDMCR; /* DRDMCR */
mbed_official 390:35c2c1cf29cd 57 volatile uint32_t DRDRENR; /* DRDRENR */
mbed_official 390:35c2c1cf29cd 58 volatile uint32_t SMDMCR; /* SMDMCR */
mbed_official 390:35c2c1cf29cd 59 volatile uint32_t SMDRENR; /* SMDRENR */
mbed_official 390:35c2c1cf29cd 60 };
mbed_official 390:35c2c1cf29cd 61
mbed_official 390:35c2c1cf29cd 62
mbed_official 390:35c2c1cf29cd 63 #define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
mbed_official 390:35c2c1cf29cd 64 #define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
mbed_official 390:35c2c1cf29cd 65
mbed_official 390:35c2c1cf29cd 66
mbed_official 390:35c2c1cf29cd 67 /* Start of channnel array defines of SPIBSC */
mbed_official 390:35c2c1cf29cd 68
mbed_official 390:35c2c1cf29cd 69 /* Channnel array defines of SPIBSC */
mbed_official 390:35c2c1cf29cd 70 /*(Sample) value = SPIBSC[ channel ]->CMNCR; */
mbed_official 390:35c2c1cf29cd 71 #define SPIBSC_COUNT 2
mbed_official 390:35c2c1cf29cd 72 #define SPIBSC_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 73 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 74 &SPIBSC0, &SPIBSC1 \
mbed_official 390:35c2c1cf29cd 75 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 76
mbed_official 390:35c2c1cf29cd 77 /* End of channnel array defines of SPIBSC */
mbed_official 390:35c2c1cf29cd 78
mbed_official 390:35c2c1cf29cd 79
mbed_official 390:35c2c1cf29cd 80 #define CMNCR_0 SPIBSC0.CMNCR
mbed_official 390:35c2c1cf29cd 81 #define SSLDR_0 SPIBSC0.SSLDR
mbed_official 390:35c2c1cf29cd 82 #define SPBCR_0 SPIBSC0.SPBCR
mbed_official 390:35c2c1cf29cd 83 #define DRCR_0 SPIBSC0.DRCR
mbed_official 390:35c2c1cf29cd 84 #define DRCMR_0 SPIBSC0.DRCMR
mbed_official 390:35c2c1cf29cd 85 #define DREAR_0 SPIBSC0.DREAR
mbed_official 390:35c2c1cf29cd 86 #define DROPR_0 SPIBSC0.DROPR
mbed_official 390:35c2c1cf29cd 87 #define DRENR_0 SPIBSC0.DRENR
mbed_official 390:35c2c1cf29cd 88 #define SMCR_0 SPIBSC0.SMCR
mbed_official 390:35c2c1cf29cd 89 #define SMCMR_0 SPIBSC0.SMCMR
mbed_official 390:35c2c1cf29cd 90 #define SMADR_0 SPIBSC0.SMADR
mbed_official 390:35c2c1cf29cd 91 #define SMOPR_0 SPIBSC0.SMOPR
mbed_official 390:35c2c1cf29cd 92 #define SMENR_0 SPIBSC0.SMENR
mbed_official 390:35c2c1cf29cd 93 #define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
mbed_official 390:35c2c1cf29cd 94 #define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
mbed_official 390:35c2c1cf29cd 95 #define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
mbed_official 390:35c2c1cf29cd 96 #define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
mbed_official 390:35c2c1cf29cd 97 #define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
mbed_official 390:35c2c1cf29cd 98 #define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
mbed_official 390:35c2c1cf29cd 99 #define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
mbed_official 390:35c2c1cf29cd 100 #define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
mbed_official 390:35c2c1cf29cd 101 #define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
mbed_official 390:35c2c1cf29cd 102 #define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
mbed_official 390:35c2c1cf29cd 103 #define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
mbed_official 390:35c2c1cf29cd 104 #define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
mbed_official 390:35c2c1cf29cd 105 #define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
mbed_official 390:35c2c1cf29cd 106 #define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
mbed_official 390:35c2c1cf29cd 107 #define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
mbed_official 390:35c2c1cf29cd 108 #define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
mbed_official 390:35c2c1cf29cd 109 #define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
mbed_official 390:35c2c1cf29cd 110 #define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
mbed_official 390:35c2c1cf29cd 111 #define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
mbed_official 390:35c2c1cf29cd 112 #define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
mbed_official 390:35c2c1cf29cd 113 #define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
mbed_official 390:35c2c1cf29cd 114 #define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
mbed_official 390:35c2c1cf29cd 115 #define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
mbed_official 390:35c2c1cf29cd 116 #define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
mbed_official 390:35c2c1cf29cd 117 #define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
mbed_official 390:35c2c1cf29cd 118 #define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
mbed_official 390:35c2c1cf29cd 119 #define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
mbed_official 390:35c2c1cf29cd 120 #define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
mbed_official 390:35c2c1cf29cd 121 #define CMNSR_0 SPIBSC0.CMNSR
mbed_official 390:35c2c1cf29cd 122 #define DRDMCR_0 SPIBSC0.DRDMCR
mbed_official 390:35c2c1cf29cd 123 #define DRDRENR_0 SPIBSC0.DRDRENR
mbed_official 390:35c2c1cf29cd 124 #define SMDMCR_0 SPIBSC0.SMDMCR
mbed_official 390:35c2c1cf29cd 125 #define SMDRENR_0 SPIBSC0.SMDRENR
mbed_official 390:35c2c1cf29cd 126 #define CMNCR_1 SPIBSC1.CMNCR
mbed_official 390:35c2c1cf29cd 127 #define SSLDR_1 SPIBSC1.SSLDR
mbed_official 390:35c2c1cf29cd 128 #define SPBCR_1 SPIBSC1.SPBCR
mbed_official 390:35c2c1cf29cd 129 #define DRCR_1 SPIBSC1.DRCR
mbed_official 390:35c2c1cf29cd 130 #define DRCMR_1 SPIBSC1.DRCMR
mbed_official 390:35c2c1cf29cd 131 #define DREAR_1 SPIBSC1.DREAR
mbed_official 390:35c2c1cf29cd 132 #define DROPR_1 SPIBSC1.DROPR
mbed_official 390:35c2c1cf29cd 133 #define DRENR_1 SPIBSC1.DRENR
mbed_official 390:35c2c1cf29cd 134 #define SMCR_1 SPIBSC1.SMCR
mbed_official 390:35c2c1cf29cd 135 #define SMCMR_1 SPIBSC1.SMCMR
mbed_official 390:35c2c1cf29cd 136 #define SMADR_1 SPIBSC1.SMADR
mbed_official 390:35c2c1cf29cd 137 #define SMOPR_1 SPIBSC1.SMOPR
mbed_official 390:35c2c1cf29cd 138 #define SMENR_1 SPIBSC1.SMENR
mbed_official 390:35c2c1cf29cd 139 #define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
mbed_official 390:35c2c1cf29cd 140 #define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
mbed_official 390:35c2c1cf29cd 141 #define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
mbed_official 390:35c2c1cf29cd 142 #define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
mbed_official 390:35c2c1cf29cd 143 #define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
mbed_official 390:35c2c1cf29cd 144 #define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
mbed_official 390:35c2c1cf29cd 145 #define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
mbed_official 390:35c2c1cf29cd 146 #define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
mbed_official 390:35c2c1cf29cd 147 #define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
mbed_official 390:35c2c1cf29cd 148 #define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
mbed_official 390:35c2c1cf29cd 149 #define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
mbed_official 390:35c2c1cf29cd 150 #define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
mbed_official 390:35c2c1cf29cd 151 #define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
mbed_official 390:35c2c1cf29cd 152 #define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
mbed_official 390:35c2c1cf29cd 153 #define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
mbed_official 390:35c2c1cf29cd 154 #define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
mbed_official 390:35c2c1cf29cd 155 #define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
mbed_official 390:35c2c1cf29cd 156 #define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
mbed_official 390:35c2c1cf29cd 157 #define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
mbed_official 390:35c2c1cf29cd 158 #define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
mbed_official 390:35c2c1cf29cd 159 #define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
mbed_official 390:35c2c1cf29cd 160 #define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
mbed_official 390:35c2c1cf29cd 161 #define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
mbed_official 390:35c2c1cf29cd 162 #define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
mbed_official 390:35c2c1cf29cd 163 #define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
mbed_official 390:35c2c1cf29cd 164 #define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
mbed_official 390:35c2c1cf29cd 165 #define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
mbed_official 390:35c2c1cf29cd 166 #define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
mbed_official 390:35c2c1cf29cd 167 #define CMNSR_1 SPIBSC1.CMNSR
mbed_official 390:35c2c1cf29cd 168 #define DRDMCR_1 SPIBSC1.DRDMCR
mbed_official 390:35c2c1cf29cd 169 #define DRDRENR_1 SPIBSC1.DRDRENR
mbed_official 390:35c2c1cf29cd 170 #define SMDMCR_1 SPIBSC1.SMDMCR
mbed_official 390:35c2c1cf29cd 171 #define SMDRENR_1 SPIBSC1.SMDRENR
mbed_official 390:35c2c1cf29cd 172 /* <-SEC M1.10.1 */
mbed_official 390:35c2c1cf29cd 173 #endif