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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.c@274:6937b19af361, 2014-08-06 (annotated)

Committer:
mbed_official
Date:
Wed Aug 06 08:15:07 2014 +0100
Revision:
274:6937b19af361
Parent:
226:b062af740e40
Child:
369:2e96f1b71984
Synchronized with git revision 5b145e4f6c509376173c3ea2aa35a6da879a2124



Full URL: https://github.com/mbedmicro/mbed/commit/5b145e4f6c509376173c3ea2aa35a6da879a2124/



[TARGET_LPC11UXX] PeripheralNames.h and PinMap definitions separation for LPC11UXX platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_rcc.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 226:b062af740e40 5 * @version V1.1.0RC2
mbed_official 226:b062af740e40 6 * @date 14-May-2014
mbed_official 87:085cde657901 7 * @brief RCC HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
mbed_official 87:085cde657901 10 * + Initialization and de-initialization functions
mbed_official 87:085cde657901 11 * + Peripheral Control functions
mbed_official 87:085cde657901 12 *
mbed_official 87:085cde657901 13 @verbatim
mbed_official 87:085cde657901 14 ==============================================================================
mbed_official 87:085cde657901 15 ##### RCC specific features #####
mbed_official 87:085cde657901 16 ==============================================================================
mbed_official 87:085cde657901 17 [..]
mbed_official 87:085cde657901 18 After reset the device is running from Internal High Speed oscillator
mbed_official 87:085cde657901 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
mbed_official 87:085cde657901 20 and I-Cache are disabled, and all peripherals are off except internal
mbed_official 87:085cde657901 21 SRAM, Flash and JTAG.
mbed_official 87:085cde657901 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
mbed_official 87:085cde657901 23 all peripherals mapped on these busses are running at HSI speed.
mbed_official 87:085cde657901 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
mbed_official 87:085cde657901 25 (+) All GPIOs are in input floating state, except the JTAG pins which
mbed_official 87:085cde657901 26 are assigned to be used for debug purpose.
mbed_official 87:085cde657901 27
mbed_official 87:085cde657901 28 [..]
mbed_official 87:085cde657901 29 Once the device started from reset, the user application has to:
mbed_official 87:085cde657901 30 (+) Configure the clock source to be used to drive the System clock
mbed_official 87:085cde657901 31 (if the application needs higher frequency/performance)
mbed_official 87:085cde657901 32 (+) Configure the System clock frequency and Flash settings
mbed_official 87:085cde657901 33 (+) Configure the AHB and APB busses prescalers
mbed_official 87:085cde657901 34 (+) Enable the clock for the peripheral(s) to be used
mbed_official 87:085cde657901 35 (+) Configure the clock source(s) for peripherals which clocks are not
mbed_official 87:085cde657901 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
mbed_official 87:085cde657901 37
mbed_official 87:085cde657901 38 @endverbatim
mbed_official 87:085cde657901 39 ******************************************************************************
mbed_official 87:085cde657901 40 * @attention
mbed_official 87:085cde657901 41 *
mbed_official 87:085cde657901 42 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 43 *
mbed_official 87:085cde657901 44 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 45 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 46 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 47 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 49 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 50 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 52 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 53 * without specific prior written permission.
mbed_official 87:085cde657901 54 *
mbed_official 87:085cde657901 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 65 *
mbed_official 87:085cde657901 66 ******************************************************************************
mbed_official 87:085cde657901 67 */
mbed_official 87:085cde657901 68
mbed_official 87:085cde657901 69 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 70 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 71
mbed_official 87:085cde657901 72 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 73 * @{
mbed_official 87:085cde657901 74 */
mbed_official 87:085cde657901 75
mbed_official 87:085cde657901 76 /** @defgroup RCC
mbed_official 87:085cde657901 77 * @brief RCC HAL module driver
mbed_official 87:085cde657901 78 * @{
mbed_official 87:085cde657901 79 */
mbed_official 87:085cde657901 80
mbed_official 87:085cde657901 81 #ifdef HAL_RCC_MODULE_ENABLED
mbed_official 87:085cde657901 82
mbed_official 87:085cde657901 83 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 84 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 85 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official 87:085cde657901 86 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official 87:085cde657901 87 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official 87:085cde657901 88 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official 87:085cde657901 89 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official 87:085cde657901 90
mbed_official 87:085cde657901 91 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 92 #define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
mbed_official 87:085cde657901 93 #define MCO1_GPIO_PORT GPIOA
mbed_official 87:085cde657901 94 #define MCO1_PIN GPIO_PIN_8
mbed_official 87:085cde657901 95
mbed_official 87:085cde657901 96 #define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
mbed_official 87:085cde657901 97 #define MCO2_GPIO_PORT GPIOC
mbed_official 87:085cde657901 98 #define MCO2_PIN GPIO_PIN_9
mbed_official 87:085cde657901 99
mbed_official 87:085cde657901 100 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 101 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 87:085cde657901 102
mbed_official 87:085cde657901 103 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 104 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 105
mbed_official 87:085cde657901 106 /** @defgroup RCC_Private_Functions
mbed_official 87:085cde657901 107 * @{
mbed_official 87:085cde657901 108 */
mbed_official 87:085cde657901 109
mbed_official 87:085cde657901 110 /** @defgroup RCC_Group1 Initialization and de-initialization functions
mbed_official 87:085cde657901 111 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 112 *
mbed_official 87:085cde657901 113 @verbatim
mbed_official 87:085cde657901 114 ===============================================================================
mbed_official 87:085cde657901 115 ##### Initialization and de-initialization functions #####
mbed_official 87:085cde657901 116 ===============================================================================
mbed_official 87:085cde657901 117 [..]
mbed_official 226:b062af740e40 118 This section provides functions allowing to configure the internal/external oscillators
mbed_official 87:085cde657901 119 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
mbed_official 87:085cde657901 120 and APB2).
mbed_official 87:085cde657901 121
mbed_official 87:085cde657901 122 [..] Internal/external clock and PLL configuration
mbed_official 87:085cde657901 123 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
mbed_official 87:085cde657901 124 the PLL as System clock source.
mbed_official 87:085cde657901 125
mbed_official 87:085cde657901 126 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
mbed_official 87:085cde657901 127 clock source.
mbed_official 87:085cde657901 128
mbed_official 87:085cde657901 129 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
mbed_official 87:085cde657901 130 through the PLL as System clock source. Can be used also as RTC clock source.
mbed_official 87:085cde657901 131
mbed_official 87:085cde657901 132 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
mbed_official 87:085cde657901 133
mbed_official 87:085cde657901 134 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
mbed_official 87:085cde657901 135 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
mbed_official 87:085cde657901 136 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
mbed_official 87:085cde657901 137 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
mbed_official 87:085cde657901 138
mbed_official 87:085cde657901 139 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
mbed_official 87:085cde657901 140 and if a HSE clock failure occurs(HSE used directly or through PLL as System
mbed_official 87:085cde657901 141 clock source), the System clockis automatically switched to HSI and an interrupt
mbed_official 87:085cde657901 142 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
mbed_official 87:085cde657901 143 (Non-Maskable Interrupt) exception vector.
mbed_official 87:085cde657901 144
mbed_official 87:085cde657901 145 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
mbed_official 87:085cde657901 146 clock (through a configurable prescaler) on PA8 pin.
mbed_official 87:085cde657901 147
mbed_official 87:085cde657901 148 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
mbed_official 87:085cde657901 149 clock (through a configurable prescaler) on PC9 pin.
mbed_official 87:085cde657901 150
mbed_official 87:085cde657901 151 [..] System, AHB and APB busses clocks configuration
mbed_official 87:085cde657901 152 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
mbed_official 87:085cde657901 153 HSE and PLL.
mbed_official 87:085cde657901 154 The AHB clock (HCLK) is derived from System clock through configurable
mbed_official 87:085cde657901 155 prescaler and used to clock the CPU, memory and peripherals mapped
mbed_official 87:085cde657901 156 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
mbed_official 87:085cde657901 157 from AHB clock through configurable prescalers and used to clock
mbed_official 87:085cde657901 158 the peripherals mapped on these busses. You can use
mbed_official 87:085cde657901 159 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
mbed_official 87:085cde657901 160
mbed_official 87:085cde657901 161 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
mbed_official 87:085cde657901 162 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
mbed_official 87:085cde657901 163 from an external clock mapped on the I2S_CKIN pin.
mbed_official 87:085cde657901 164 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official 87:085cde657901 165 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
mbed_official 87:085cde657901 166 from an external clock mapped on the I2S_CKIN pin.
mbed_official 87:085cde657901 167 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
mbed_official 87:085cde657901 168 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
mbed_official 87:085cde657901 169 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
mbed_official 87:085cde657901 170 macros to configure this clock.
mbed_official 87:085cde657901 171 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
mbed_official 87:085cde657901 172 to work correctly, while the SDIO require a frequency equal or lower than
mbed_official 87:085cde657901 173 to 48. This clock is derived of the main PLL through PLLQ divider.
mbed_official 87:085cde657901 174 (+@) IWDG clock which is always the LSI clock.
mbed_official 87:085cde657901 175
mbed_official 87:085cde657901 176 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
mbed_official 87:085cde657901 177 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official 87:085cde657901 178 Depending on the device voltage range, the maximum frequency should
mbed_official 226:b062af740e40 179 be adapted accordingly (refer to the product datasheets for more details).
mbed_official 226:b062af740e40 180
mbed_official 87:085cde657901 181 (#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
mbed_official 87:085cde657901 182 of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
mbed_official 87:085cde657901 183 Depending on the device voltage range, the maximum frequency should
mbed_official 226:b062af740e40 184 be adapted accordingly (refer to the product datasheets for more details).
mbed_official 226:b062af740e40 185
mbed_official 87:085cde657901 186 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
mbed_official 87:085cde657901 187 PCLK2 84 MHz and PCLK1 42 MHz.
mbed_official 87:085cde657901 188 Depending on the device voltage range, the maximum frequency should
mbed_official 226:b062af740e40 189 be adapted accordingly (refer to the product datasheets for more details).
mbed_official 87:085cde657901 190 @endverbatim
mbed_official 87:085cde657901 191 * @{
mbed_official 87:085cde657901 192 */
mbed_official 87:085cde657901 193
mbed_official 87:085cde657901 194 /**
mbed_official 87:085cde657901 195 * @brief Resets the RCC clock configuration to the default reset state.
mbed_official 87:085cde657901 196 * @note The default reset state of the clock configuration is given below:
mbed_official 87:085cde657901 197 * - HSI ON and used as system clock source
mbed_official 87:085cde657901 198 * - HSE, PLL and PLLI2S OFF
mbed_official 87:085cde657901 199 * - AHB, APB1 and APB2 prescaler set to 1.
mbed_official 87:085cde657901 200 * - CSS, MCO1 and MCO2 OFF
mbed_official 87:085cde657901 201 * - All interrupts disabled
mbed_official 87:085cde657901 202 * @note This function doesn't modify the configuration of the
mbed_official 87:085cde657901 203 * - Peripheral clocks
mbed_official 87:085cde657901 204 * - LSI, LSE and RTC clocks
mbed_official 87:085cde657901 205 * @param None
mbed_official 87:085cde657901 206 * @retval None
mbed_official 87:085cde657901 207 */
mbed_official 87:085cde657901 208 void HAL_RCC_DeInit(void)
mbed_official 87:085cde657901 209 {
mbed_official 87:085cde657901 210 /* Set HSION bit */
mbed_official 87:085cde657901 211 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
mbed_official 87:085cde657901 212
mbed_official 87:085cde657901 213 /* Reset CFGR register */
mbed_official 87:085cde657901 214 CLEAR_REG(RCC->CFGR);
mbed_official 87:085cde657901 215
mbed_official 87:085cde657901 216 /* Reset HSEON, CSSON, PLLON, PLLI2S */
mbed_official 87:085cde657901 217 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
mbed_official 87:085cde657901 218
mbed_official 87:085cde657901 219 /* Reset PLLCFGR register */
mbed_official 87:085cde657901 220 CLEAR_REG(RCC->PLLCFGR);
mbed_official 87:085cde657901 221 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
mbed_official 87:085cde657901 222
mbed_official 87:085cde657901 223 /* Reset PLLI2SCFGR register */
mbed_official 87:085cde657901 224 CLEAR_REG(RCC->PLLI2SCFGR);
mbed_official 87:085cde657901 225 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
mbed_official 87:085cde657901 226
mbed_official 87:085cde657901 227 /* Reset HSEBYP bit */
mbed_official 87:085cde657901 228 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official 87:085cde657901 229
mbed_official 87:085cde657901 230 /* Disable all interrupts */
mbed_official 87:085cde657901 231 CLEAR_REG(RCC->CIR);
mbed_official 87:085cde657901 232 }
mbed_official 87:085cde657901 233
mbed_official 87:085cde657901 234 /**
mbed_official 87:085cde657901 235 * @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official 87:085cde657901 236 * RCC_OscInitTypeDef.
mbed_official 87:085cde657901 237 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 87:085cde657901 238 * contains the configuration information for the RCC Oscillators.
mbed_official 87:085cde657901 239 * @note The PLL is not disabled when used as system clock.
mbed_official 87:085cde657901 240 * @retval HAL status
mbed_official 87:085cde657901 241 */
mbed_official 87:085cde657901 242 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 87:085cde657901 243 {
mbed_official 226:b062af740e40 244 uint32_t tickstart = 0;
mbed_official 87:085cde657901 245
mbed_official 87:085cde657901 246 /* Check the parameters */
mbed_official 87:085cde657901 247 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
mbed_official 87:085cde657901 248 /*------------------------------- HSE Configuration ------------------------*/
mbed_official 87:085cde657901 249 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
mbed_official 87:085cde657901 250 {
mbed_official 87:085cde657901 251 /* Check the parameters */
mbed_official 87:085cde657901 252 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
mbed_official 87:085cde657901 253 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
mbed_official 87:085cde657901 254 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
mbed_official 87:085cde657901 255 {
mbed_official 87:085cde657901 256 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
mbed_official 87:085cde657901 257 {
mbed_official 87:085cde657901 258 return HAL_ERROR;
mbed_official 87:085cde657901 259 }
mbed_official 87:085cde657901 260 }
mbed_official 87:085cde657901 261 else
mbed_official 87:085cde657901 262 {
mbed_official 87:085cde657901 263 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
mbed_official 87:085cde657901 264 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
mbed_official 87:085cde657901 265
mbed_official 226:b062af740e40 266 /* Get Start Tick*/
mbed_official 226:b062af740e40 267 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 268
mbed_official 87:085cde657901 269 /* Wait till HSE is disabled */
mbed_official 87:085cde657901 270 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official 87:085cde657901 271 {
mbed_official 226:b062af740e40 272 if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official 87:085cde657901 273 {
mbed_official 87:085cde657901 274 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 275 }
mbed_official 87:085cde657901 276 }
mbed_official 87:085cde657901 277
mbed_official 87:085cde657901 278 /* Set the new HSE configuration ---------------------------------------*/
mbed_official 87:085cde657901 279 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
mbed_official 87:085cde657901 280
mbed_official 87:085cde657901 281 /* Check the HSE State */
mbed_official 87:085cde657901 282 if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON)
mbed_official 87:085cde657901 283 {
mbed_official 226:b062af740e40 284 /* Get Start Tick*/
mbed_official 226:b062af740e40 285 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 286
mbed_official 87:085cde657901 287 /* Wait till HSE is ready */
mbed_official 87:085cde657901 288 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 87:085cde657901 289 {
mbed_official 226:b062af740e40 290 if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official 87:085cde657901 291 {
mbed_official 87:085cde657901 292 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 293 }
mbed_official 87:085cde657901 294 }
mbed_official 87:085cde657901 295 }
mbed_official 87:085cde657901 296 else
mbed_official 87:085cde657901 297 {
mbed_official 226:b062af740e40 298 /* Get Start Tick*/
mbed_official 226:b062af740e40 299 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 300
mbed_official 87:085cde657901 301 /* Wait till HSE is bypassed or disabled */
mbed_official 87:085cde657901 302 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official 87:085cde657901 303 {
mbed_official 226:b062af740e40 304 if((int32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official 87:085cde657901 305 {
mbed_official 87:085cde657901 306 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 307 }
mbed_official 87:085cde657901 308 }
mbed_official 87:085cde657901 309 }
mbed_official 87:085cde657901 310 }
mbed_official 87:085cde657901 311 }
mbed_official 87:085cde657901 312 /*----------------------------- HSI Configuration --------------------------*/
mbed_official 87:085cde657901 313 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
mbed_official 87:085cde657901 314 {
mbed_official 87:085cde657901 315 /* Check the parameters */
mbed_official 87:085cde657901 316 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
mbed_official 87:085cde657901 317 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
mbed_official 87:085cde657901 318
mbed_official 87:085cde657901 319 /* When the HSI is used as system clock it will not disabled */
mbed_official 87:085cde657901 320 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
mbed_official 87:085cde657901 321 {
mbed_official 87:085cde657901 322 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
mbed_official 87:085cde657901 323 {
mbed_official 87:085cde657901 324 return HAL_ERROR;
mbed_official 87:085cde657901 325 }
mbed_official 87:085cde657901 326 }
mbed_official 87:085cde657901 327 else
mbed_official 87:085cde657901 328 {
mbed_official 87:085cde657901 329 /* Check the HSI State */
mbed_official 87:085cde657901 330 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
mbed_official 87:085cde657901 331 {
mbed_official 87:085cde657901 332 /* Enable the Internal High Speed oscillator (HSI). */
mbed_official 87:085cde657901 333 __HAL_RCC_HSI_ENABLE();
mbed_official 87:085cde657901 334
mbed_official 226:b062af740e40 335 /* Get Start Tick*/
mbed_official 226:b062af740e40 336 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 337
mbed_official 87:085cde657901 338 /* Wait till HSI is ready */
mbed_official 87:085cde657901 339 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 87:085cde657901 340 {
mbed_official 226:b062af740e40 341 if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official 87:085cde657901 342 {
mbed_official 87:085cde657901 343 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 344 }
mbed_official 87:085cde657901 345 }
mbed_official 87:085cde657901 346
mbed_official 87:085cde657901 347 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official 87:085cde657901 348 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official 87:085cde657901 349 }
mbed_official 87:085cde657901 350 else
mbed_official 87:085cde657901 351 {
mbed_official 87:085cde657901 352 /* Disable the Internal High Speed oscillator (HSI). */
mbed_official 87:085cde657901 353 __HAL_RCC_HSI_DISABLE();
mbed_official 87:085cde657901 354
mbed_official 226:b062af740e40 355 /* Get Start Tick*/
mbed_official 226:b062af740e40 356 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 357
mbed_official 87:085cde657901 358 /* Wait till HSI is ready */
mbed_official 87:085cde657901 359 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official 87:085cde657901 360 {
mbed_official 226:b062af740e40 361 if((int32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official 87:085cde657901 362 {
mbed_official 87:085cde657901 363 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 364 }
mbed_official 87:085cde657901 365 }
mbed_official 87:085cde657901 366 }
mbed_official 87:085cde657901 367 }
mbed_official 87:085cde657901 368 }
mbed_official 87:085cde657901 369 /*------------------------------ LSI Configuration -------------------------*/
mbed_official 87:085cde657901 370 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
mbed_official 87:085cde657901 371 {
mbed_official 87:085cde657901 372 /* Check the parameters */
mbed_official 87:085cde657901 373 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
mbed_official 87:085cde657901 374
mbed_official 87:085cde657901 375 /* Check the LSI State */
mbed_official 87:085cde657901 376 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
mbed_official 87:085cde657901 377 {
mbed_official 87:085cde657901 378 /* Enable the Internal Low Speed oscillator (LSI). */
mbed_official 87:085cde657901 379 __HAL_RCC_LSI_ENABLE();
mbed_official 226:b062af740e40 380
mbed_official 226:b062af740e40 381 /* Get Start Tick*/
mbed_official 226:b062af740e40 382 tickstart = HAL_GetTick();
mbed_official 226:b062af740e40 383
mbed_official 87:085cde657901 384 /* Wait till LSI is ready */
mbed_official 87:085cde657901 385 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
mbed_official 87:085cde657901 386 {
mbed_official 226:b062af740e40 387 if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official 87:085cde657901 388 {
mbed_official 87:085cde657901 389 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 390 }
mbed_official 87:085cde657901 391 }
mbed_official 87:085cde657901 392 }
mbed_official 87:085cde657901 393 else
mbed_official 87:085cde657901 394 {
mbed_official 87:085cde657901 395 /* Disable the Internal Low Speed oscillator (LSI). */
mbed_official 87:085cde657901 396 __HAL_RCC_LSI_DISABLE();
mbed_official 226:b062af740e40 397
mbed_official 226:b062af740e40 398 /* Get Start Tick*/
mbed_official 226:b062af740e40 399 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 400
mbed_official 87:085cde657901 401 /* Wait till LSI is ready */
mbed_official 87:085cde657901 402 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
mbed_official 87:085cde657901 403 {
mbed_official 226:b062af740e40 404 if((int32_t) (HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official 87:085cde657901 405 {
mbed_official 87:085cde657901 406 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 407 }
mbed_official 87:085cde657901 408 }
mbed_official 87:085cde657901 409 }
mbed_official 87:085cde657901 410 }
mbed_official 87:085cde657901 411 /*------------------------------ LSE Configuration -------------------------*/
mbed_official 87:085cde657901 412 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
mbed_official 87:085cde657901 413 {
mbed_official 87:085cde657901 414 /* Check the parameters */
mbed_official 87:085cde657901 415 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
mbed_official 87:085cde657901 416
mbed_official 106:ced8cbb51063 417 /* Enable Power Clock*/
mbed_official 106:ced8cbb51063 418 __PWR_CLK_ENABLE();
mbed_official 106:ced8cbb51063 419
mbed_official 106:ced8cbb51063 420 /* Enable write access to Backup domain */
mbed_official 106:ced8cbb51063 421 PWR->CR |= PWR_CR_DBP;
mbed_official 106:ced8cbb51063 422
mbed_official 106:ced8cbb51063 423 /* Wait for Backup domain Write protection disable */
mbed_official 226:b062af740e40 424 tickstart = HAL_GetTick();
mbed_official 106:ced8cbb51063 425
mbed_official 106:ced8cbb51063 426 while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official 87:085cde657901 427 {
mbed_official 226:b062af740e40 428 if((int32_t) (HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
mbed_official 106:ced8cbb51063 429 {
mbed_official 106:ced8cbb51063 430 return HAL_TIMEOUT;
mbed_official 106:ced8cbb51063 431 }
mbed_official 87:085cde657901 432 }
mbed_official 226:b062af740e40 433
mbed_official 87:085cde657901 434 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
mbed_official 87:085cde657901 435 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
mbed_official 87:085cde657901 436
mbed_official 226:b062af740e40 437 /* Get Start Tick*/
mbed_official 226:b062af740e40 438 tickstart = HAL_GetTick();
mbed_official 226:b062af740e40 439
mbed_official 87:085cde657901 440 /* Wait till LSE is ready */
mbed_official 87:085cde657901 441 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official 87:085cde657901 442 {
mbed_official 226:b062af740e40 443 if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
mbed_official 87:085cde657901 444 {
mbed_official 87:085cde657901 445 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 446 }
mbed_official 87:085cde657901 447 }
mbed_official 87:085cde657901 448
mbed_official 87:085cde657901 449 /* Set the new LSE configuration -----------------------------------------*/
mbed_official 87:085cde657901 450 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
mbed_official 87:085cde657901 451 /* Check the LSE State */
mbed_official 87:085cde657901 452 if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
mbed_official 87:085cde657901 453 {
mbed_official 226:b062af740e40 454 /* Get Start Tick*/
mbed_official 226:b062af740e40 455 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 456
mbed_official 87:085cde657901 457 /* Wait till LSE is ready */
mbed_official 87:085cde657901 458 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official 87:085cde657901 459 {
mbed_official 226:b062af740e40 460 if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
mbed_official 87:085cde657901 461 {
mbed_official 87:085cde657901 462 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 463 }
mbed_official 87:085cde657901 464 }
mbed_official 87:085cde657901 465 }
mbed_official 87:085cde657901 466 else
mbed_official 87:085cde657901 467 {
mbed_official 226:b062af740e40 468 /* Get Start Tick*/
mbed_official 226:b062af740e40 469 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 470
mbed_official 87:085cde657901 471 /* Wait till LSE is ready */
mbed_official 87:085cde657901 472 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official 87:085cde657901 473 {
mbed_official 226:b062af740e40 474 if((int32_t) (HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
mbed_official 87:085cde657901 475 {
mbed_official 87:085cde657901 476 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 477 }
mbed_official 87:085cde657901 478 }
mbed_official 87:085cde657901 479 }
mbed_official 87:085cde657901 480 }
mbed_official 87:085cde657901 481 /*-------------------------------- PLL Configuration -----------------------*/
mbed_official 87:085cde657901 482 /* Check the parameters */
mbed_official 87:085cde657901 483 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
mbed_official 87:085cde657901 484 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
mbed_official 87:085cde657901 485 {
mbed_official 87:085cde657901 486 /* Check if the PLL is used as system clock or not */
mbed_official 87:085cde657901 487 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official 87:085cde657901 488 {
mbed_official 87:085cde657901 489 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
mbed_official 87:085cde657901 490 {
mbed_official 87:085cde657901 491 /* Check the parameters */
mbed_official 87:085cde657901 492 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
mbed_official 87:085cde657901 493 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
mbed_official 87:085cde657901 494 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
mbed_official 87:085cde657901 495 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
mbed_official 87:085cde657901 496 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
mbed_official 87:085cde657901 497
mbed_official 87:085cde657901 498 /* Disable the main PLL. */
mbed_official 87:085cde657901 499 __HAL_RCC_PLL_DISABLE();
mbed_official 226:b062af740e40 500
mbed_official 226:b062af740e40 501 /* Get Start Tick*/
mbed_official 226:b062af740e40 502 tickstart = HAL_GetTick();
mbed_official 226:b062af740e40 503
mbed_official 87:085cde657901 504 /* Wait till PLL is ready */
mbed_official 87:085cde657901 505 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official 87:085cde657901 506 {
mbed_official 226:b062af740e40 507 if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official 87:085cde657901 508 {
mbed_official 87:085cde657901 509 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 510 }
mbed_official 87:085cde657901 511 }
mbed_official 87:085cde657901 512
mbed_official 87:085cde657901 513 /* Configure the main PLL clock source, multiplication and division factors. */
mbed_official 87:085cde657901 514 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
mbed_official 87:085cde657901 515 RCC_OscInitStruct->PLL.PLLM,
mbed_official 87:085cde657901 516 RCC_OscInitStruct->PLL.PLLN,
mbed_official 87:085cde657901 517 RCC_OscInitStruct->PLL.PLLP,
mbed_official 87:085cde657901 518 RCC_OscInitStruct->PLL.PLLQ);
mbed_official 87:085cde657901 519 /* Enable the main PLL. */
mbed_official 87:085cde657901 520 __HAL_RCC_PLL_ENABLE();
mbed_official 87:085cde657901 521
mbed_official 226:b062af740e40 522 /* Get Start Tick*/
mbed_official 226:b062af740e40 523 tickstart = HAL_GetTick();
mbed_official 226:b062af740e40 524
mbed_official 87:085cde657901 525 /* Wait till PLL is ready */
mbed_official 87:085cde657901 526 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 87:085cde657901 527 {
mbed_official 226:b062af740e40 528 if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official 87:085cde657901 529 {
mbed_official 87:085cde657901 530 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 531 }
mbed_official 87:085cde657901 532 }
mbed_official 87:085cde657901 533 }
mbed_official 87:085cde657901 534 else
mbed_official 87:085cde657901 535 {
mbed_official 87:085cde657901 536 /* Disable the main PLL. */
mbed_official 87:085cde657901 537 __HAL_RCC_PLL_DISABLE();
mbed_official 226:b062af740e40 538
mbed_official 226:b062af740e40 539 /* Get Start Tick*/
mbed_official 226:b062af740e40 540 tickstart = HAL_GetTick();
mbed_official 226:b062af740e40 541
mbed_official 87:085cde657901 542 /* Wait till PLL is ready */
mbed_official 87:085cde657901 543 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official 87:085cde657901 544 {
mbed_official 226:b062af740e40 545 if((int32_t) (HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official 87:085cde657901 546 {
mbed_official 87:085cde657901 547 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 548 }
mbed_official 87:085cde657901 549 }
mbed_official 87:085cde657901 550 }
mbed_official 87:085cde657901 551 }
mbed_official 87:085cde657901 552 else
mbed_official 87:085cde657901 553 {
mbed_official 87:085cde657901 554 return HAL_ERROR;
mbed_official 87:085cde657901 555 }
mbed_official 87:085cde657901 556 }
mbed_official 87:085cde657901 557 return HAL_OK;
mbed_official 87:085cde657901 558 }
mbed_official 87:085cde657901 559
mbed_official 87:085cde657901 560 /**
mbed_official 87:085cde657901 561 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
mbed_official 87:085cde657901 562 * parameters in the RCC_ClkInitStruct.
mbed_official 87:085cde657901 563 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 87:085cde657901 564 * contains the configuration information for the RCC peripheral.
mbed_official 87:085cde657901 565 * @param FLatency: FLASH Latency, this parameter depend on device selected
mbed_official 87:085cde657901 566 *
mbed_official 87:085cde657901 567 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official 87:085cde657901 568 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
mbed_official 87:085cde657901 569 *
mbed_official 87:085cde657901 570 * @note The HSI is used (enabled by hardware) as system clock source after
mbed_official 87:085cde657901 571 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official 87:085cde657901 572 * of failure of the HSE used directly or indirectly as system clock
mbed_official 87:085cde657901 573 * (if the Clock Security System CSS is enabled).
mbed_official 87:085cde657901 574 *
mbed_official 87:085cde657901 575 * @note A switch from one clock source to another occurs only if the target
mbed_official 87:085cde657901 576 * clock source is ready (clock stable after startup delay or PLL locked).
mbed_official 87:085cde657901 577 * If a clock source which is not yet ready is selected, the switch will
mbed_official 87:085cde657901 578 * occur when the clock source will be ready.
mbed_official 87:085cde657901 579 *
mbed_official 87:085cde657901 580 * @note Depending on the device voltage range, the software has to set correctly
mbed_official 87:085cde657901 581 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
mbed_official 87:085cde657901 582 * (for more details refer to section above "Initialization/de-initialization functions")
mbed_official 87:085cde657901 583 * @retval None
mbed_official 87:085cde657901 584 */
mbed_official 87:085cde657901 585 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
mbed_official 87:085cde657901 586 {
mbed_official 226:b062af740e40 587 uint32_t tickstart = 0;
mbed_official 87:085cde657901 588
mbed_official 87:085cde657901 589 /* Check the parameters */
mbed_official 87:085cde657901 590 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
mbed_official 87:085cde657901 591 assert_param(IS_FLASH_LATENCY(FLatency));
mbed_official 87:085cde657901 592
mbed_official 87:085cde657901 593 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
mbed_official 87:085cde657901 594 must be correctly programmed according to the frequency of the CPU clock
mbed_official 87:085cde657901 595 (HCLK) and the supply voltage of the device. */
mbed_official 87:085cde657901 596
mbed_official 87:085cde657901 597 /* Increasing the CPU frequency */
mbed_official 87:085cde657901 598 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official 87:085cde657901 599 {
mbed_official 87:085cde657901 600 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official 87:085cde657901 601 __HAL_FLASH_SET_LATENCY(FLatency);
mbed_official 87:085cde657901 602
mbed_official 87:085cde657901 603 /* Check that the new number of wait states is taken into account to access the Flash
mbed_official 87:085cde657901 604 memory by reading the FLASH_ACR register */
mbed_official 87:085cde657901 605 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official 87:085cde657901 606 {
mbed_official 87:085cde657901 607 return HAL_ERROR;
mbed_official 87:085cde657901 608 }
mbed_official 87:085cde657901 609
mbed_official 226:b062af740e40 610 /*-------------------------- HCLK Configuration --------------------------*/
mbed_official 226:b062af740e40 611 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official 226:b062af740e40 612 {
mbed_official 226:b062af740e40 613 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official 226:b062af740e40 614 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official 226:b062af740e40 615 }
mbed_official 226:b062af740e40 616
mbed_official 87:085cde657901 617 /*------------------------- SYSCLK Configuration ---------------------------*/
mbed_official 87:085cde657901 618 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official 87:085cde657901 619 {
mbed_official 87:085cde657901 620 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official 87:085cde657901 621
mbed_official 87:085cde657901 622 /* HSE is selected as System Clock Source */
mbed_official 87:085cde657901 623 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 87:085cde657901 624 {
mbed_official 87:085cde657901 625 /* Check the HSE ready flag */
mbed_official 87:085cde657901 626 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 87:085cde657901 627 {
mbed_official 87:085cde657901 628 return HAL_ERROR;
mbed_official 87:085cde657901 629 }
mbed_official 87:085cde657901 630 }
mbed_official 87:085cde657901 631 /* PLL is selected as System Clock Source */
mbed_official 87:085cde657901 632 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 87:085cde657901 633 {
mbed_official 87:085cde657901 634 /* Check the PLL ready flag */
mbed_official 87:085cde657901 635 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 87:085cde657901 636 {
mbed_official 87:085cde657901 637 return HAL_ERROR;
mbed_official 87:085cde657901 638 }
mbed_official 87:085cde657901 639 }
mbed_official 87:085cde657901 640 /* HSI is selected as System Clock Source */
mbed_official 87:085cde657901 641 else
mbed_official 87:085cde657901 642 {
mbed_official 87:085cde657901 643 /* Check the HSI ready flag */
mbed_official 87:085cde657901 644 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 87:085cde657901 645 {
mbed_official 87:085cde657901 646 return HAL_ERROR;
mbed_official 87:085cde657901 647 }
mbed_official 87:085cde657901 648 }
mbed_official 87:085cde657901 649 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official 87:085cde657901 650
mbed_official 226:b062af740e40 651 /* Get Start Tick*/
mbed_official 226:b062af740e40 652 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 653
mbed_official 87:085cde657901 654 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 87:085cde657901 655 {
mbed_official 87:085cde657901 656 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official 87:085cde657901 657 {
mbed_official 226:b062af740e40 658 if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 87:085cde657901 659 {
mbed_official 87:085cde657901 660 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 661 }
mbed_official 87:085cde657901 662 }
mbed_official 87:085cde657901 663 }
mbed_official 87:085cde657901 664 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 87:085cde657901 665 {
mbed_official 87:085cde657901 666 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official 87:085cde657901 667 {
mbed_official 226:b062af740e40 668 if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 87:085cde657901 669 {
mbed_official 87:085cde657901 670 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 671 }
mbed_official 87:085cde657901 672 }
mbed_official 87:085cde657901 673 }
mbed_official 87:085cde657901 674 else
mbed_official 87:085cde657901 675 {
mbed_official 87:085cde657901 676 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official 87:085cde657901 677 {
mbed_official 226:b062af740e40 678 if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 87:085cde657901 679 {
mbed_official 87:085cde657901 680 return HAL_TIMEOUT;
mbed_official 87:085cde657901 681 }
mbed_official 87:085cde657901 682 }
mbed_official 87:085cde657901 683 }
mbed_official 87:085cde657901 684 }
mbed_official 87:085cde657901 685 }
mbed_official 87:085cde657901 686 /* Decreasing the CPU frequency */
mbed_official 87:085cde657901 687 else
mbed_official 87:085cde657901 688 {
mbed_official 226:b062af740e40 689 /*-------------------------- HCLK Configuration --------------------------*/
mbed_official 226:b062af740e40 690 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official 226:b062af740e40 691 {
mbed_official 226:b062af740e40 692 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official 226:b062af740e40 693 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official 226:b062af740e40 694 }
mbed_official 226:b062af740e40 695
mbed_official 226:b062af740e40 696 /*------------------------- SYSCLK Configuration -------------------------*/
mbed_official 87:085cde657901 697 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official 87:085cde657901 698 {
mbed_official 87:085cde657901 699 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official 87:085cde657901 700
mbed_official 87:085cde657901 701 /* HSE is selected as System Clock Source */
mbed_official 87:085cde657901 702 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 87:085cde657901 703 {
mbed_official 87:085cde657901 704 /* Check the HSE ready flag */
mbed_official 87:085cde657901 705 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 87:085cde657901 706 {
mbed_official 87:085cde657901 707 return HAL_ERROR;
mbed_official 87:085cde657901 708 }
mbed_official 87:085cde657901 709 }
mbed_official 87:085cde657901 710 /* PLL is selected as System Clock Source */
mbed_official 87:085cde657901 711 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 87:085cde657901 712 {
mbed_official 87:085cde657901 713 /* Check the PLL ready flag */
mbed_official 87:085cde657901 714 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 87:085cde657901 715 {
mbed_official 87:085cde657901 716 return HAL_ERROR;
mbed_official 87:085cde657901 717 }
mbed_official 87:085cde657901 718 }
mbed_official 87:085cde657901 719 /* HSI is selected as System Clock Source */
mbed_official 87:085cde657901 720 else
mbed_official 87:085cde657901 721 {
mbed_official 87:085cde657901 722 /* Check the HSI ready flag */
mbed_official 87:085cde657901 723 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 87:085cde657901 724 {
mbed_official 87:085cde657901 725 return HAL_ERROR;
mbed_official 87:085cde657901 726 }
mbed_official 87:085cde657901 727 }
mbed_official 87:085cde657901 728 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official 87:085cde657901 729
mbed_official 226:b062af740e40 730 /* Get Start Tick*/
mbed_official 226:b062af740e40 731 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 732
mbed_official 87:085cde657901 733 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 87:085cde657901 734 {
mbed_official 87:085cde657901 735 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
mbed_official 87:085cde657901 736 {
mbed_official 226:b062af740e40 737 if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 87:085cde657901 738 {
mbed_official 87:085cde657901 739 return HAL_TIMEOUT;
mbed_official 87:085cde657901 740 }
mbed_official 87:085cde657901 741 }
mbed_official 87:085cde657901 742 }
mbed_official 87:085cde657901 743 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 87:085cde657901 744 {
mbed_official 87:085cde657901 745 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official 87:085cde657901 746 {
mbed_official 226:b062af740e40 747 if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 87:085cde657901 748 {
mbed_official 87:085cde657901 749 return HAL_TIMEOUT;
mbed_official 87:085cde657901 750 }
mbed_official 87:085cde657901 751 }
mbed_official 87:085cde657901 752 }
mbed_official 87:085cde657901 753 else
mbed_official 87:085cde657901 754 {
mbed_official 87:085cde657901 755 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
mbed_official 87:085cde657901 756 {
mbed_official 226:b062af740e40 757 if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 87:085cde657901 758 {
mbed_official 87:085cde657901 759 return HAL_TIMEOUT;
mbed_official 226:b062af740e40 760 }
mbed_official 87:085cde657901 761 }
mbed_official 87:085cde657901 762 }
mbed_official 87:085cde657901 763 }
mbed_official 87:085cde657901 764
mbed_official 87:085cde657901 765 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official 87:085cde657901 766 __HAL_FLASH_SET_LATENCY(FLatency);
mbed_official 87:085cde657901 767
mbed_official 87:085cde657901 768 /* Check that the new number of wait states is taken into account to access the Flash
mbed_official 87:085cde657901 769 memory by reading the FLASH_ACR register */
mbed_official 87:085cde657901 770 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official 87:085cde657901 771 {
mbed_official 87:085cde657901 772 return HAL_ERROR;
mbed_official 87:085cde657901 773 }
mbed_official 87:085cde657901 774 }
mbed_official 226:b062af740e40 775
mbed_official 87:085cde657901 776 /*-------------------------- PCLK1 Configuration ---------------------------*/
mbed_official 87:085cde657901 777 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
mbed_official 87:085cde657901 778 {
mbed_official 87:085cde657901 779 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
mbed_official 87:085cde657901 780 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
mbed_official 87:085cde657901 781 }
mbed_official 87:085cde657901 782
mbed_official 87:085cde657901 783 /*-------------------------- PCLK2 Configuration ---------------------------*/
mbed_official 87:085cde657901 784 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
mbed_official 87:085cde657901 785 {
mbed_official 87:085cde657901 786 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
mbed_official 87:085cde657901 787 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
mbed_official 87:085cde657901 788 }
mbed_official 87:085cde657901 789
mbed_official 226:b062af740e40 790 /* Configure the source of time base considering new system clocks settings*/
mbed_official 226:b062af740e40 791 HAL_InitTick (TICK_INT_PRIORITY);
mbed_official 87:085cde657901 792
mbed_official 87:085cde657901 793 return HAL_OK;
mbed_official 87:085cde657901 794 }
mbed_official 87:085cde657901 795
mbed_official 87:085cde657901 796 /**
mbed_official 87:085cde657901 797 * @}
mbed_official 87:085cde657901 798 */
mbed_official 87:085cde657901 799
mbed_official 87:085cde657901 800 /** @defgroup RCC_Group2 Peripheral Control functions
mbed_official 87:085cde657901 801 * @brief RCC clocks control functions
mbed_official 87:085cde657901 802 *
mbed_official 87:085cde657901 803 @verbatim
mbed_official 87:085cde657901 804 ===============================================================================
mbed_official 87:085cde657901 805 ##### Peripheral Control functions #####
mbed_official 87:085cde657901 806 ===============================================================================
mbed_official 87:085cde657901 807 [..]
mbed_official 87:085cde657901 808 This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official 87:085cde657901 809 frequencies.
mbed_official 87:085cde657901 810
mbed_official 87:085cde657901 811 @endverbatim
mbed_official 87:085cde657901 812 * @{
mbed_official 87:085cde657901 813 */
mbed_official 87:085cde657901 814
mbed_official 87:085cde657901 815 /**
mbed_official 87:085cde657901 816 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
mbed_official 87:085cde657901 817 * @note PA8/PC9 should be configured in alternate function mode.
mbed_official 87:085cde657901 818 * @param RCC_MCOx: specifies the output direction for the clock source.
mbed_official 87:085cde657901 819 * This parameter can be one of the following values:
mbed_official 87:085cde657901 820 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
mbed_official 87:085cde657901 821 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
mbed_official 87:085cde657901 822 * @param RCC_MCOSource: specifies the clock source to output.
mbed_official 87:085cde657901 823 * This parameter can be one of the following values:
mbed_official 87:085cde657901 824 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
mbed_official 87:085cde657901 825 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
mbed_official 87:085cde657901 826 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
mbed_official 87:085cde657901 827 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
mbed_official 87:085cde657901 828 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
mbed_official 87:085cde657901 829 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
mbed_official 87:085cde657901 830 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
mbed_official 87:085cde657901 831 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
mbed_official 87:085cde657901 832 * @param RCC_MCODiv: specifies the MCOx prescaler.
mbed_official 87:085cde657901 833 * This parameter can be one of the following values:
mbed_official 87:085cde657901 834 * @arg RCC_MCODIV_1: no division applied to MCOx clock
mbed_official 87:085cde657901 835 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
mbed_official 87:085cde657901 836 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
mbed_official 87:085cde657901 837 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
mbed_official 87:085cde657901 838 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
mbed_official 87:085cde657901 839 * @retval None
mbed_official 87:085cde657901 840 */
mbed_official 87:085cde657901 841 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
mbed_official 87:085cde657901 842 {
mbed_official 87:085cde657901 843 GPIO_InitTypeDef GPIO_InitStruct;
mbed_official 87:085cde657901 844 /* Check the parameters */
mbed_official 87:085cde657901 845 assert_param(IS_RCC_MCO(RCC_MCOx));
mbed_official 87:085cde657901 846 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
mbed_official 87:085cde657901 847 /* RCC_MCO1 */
mbed_official 87:085cde657901 848 if(RCC_MCOx == RCC_MCO1)
mbed_official 87:085cde657901 849 {
mbed_official 87:085cde657901 850 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
mbed_official 87:085cde657901 851
mbed_official 87:085cde657901 852 /* MCO1 Clock Enable */
mbed_official 87:085cde657901 853 __MCO1_CLK_ENABLE();
mbed_official 87:085cde657901 854
mbed_official 87:085cde657901 855 /* Configue the MCO1 pin in alternate function mode */
mbed_official 87:085cde657901 856 GPIO_InitStruct.Pin = MCO1_PIN;
mbed_official 87:085cde657901 857 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official 87:085cde657901 858 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official 87:085cde657901 859 GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official 87:085cde657901 860 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official 87:085cde657901 861 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
mbed_official 87:085cde657901 862
mbed_official 87:085cde657901 863 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
mbed_official 87:085cde657901 864 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
mbed_official 87:085cde657901 865 }
mbed_official 87:085cde657901 866 else
mbed_official 87:085cde657901 867 {
mbed_official 87:085cde657901 868 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
mbed_official 87:085cde657901 869
mbed_official 87:085cde657901 870 /* MCO2 Clock Enable */
mbed_official 87:085cde657901 871 __MCO2_CLK_ENABLE();
mbed_official 87:085cde657901 872
mbed_official 87:085cde657901 873 /* Configue the MCO2 pin in alternate function mode */
mbed_official 87:085cde657901 874 GPIO_InitStruct.Pin = MCO2_PIN;
mbed_official 87:085cde657901 875 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
mbed_official 87:085cde657901 876 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
mbed_official 87:085cde657901 877 GPIO_InitStruct.Pull = GPIO_NOPULL;
mbed_official 87:085cde657901 878 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
mbed_official 87:085cde657901 879 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
mbed_official 87:085cde657901 880
mbed_official 87:085cde657901 881 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
mbed_official 87:085cde657901 882 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
mbed_official 87:085cde657901 883 }
mbed_official 87:085cde657901 884 }
mbed_official 87:085cde657901 885
mbed_official 87:085cde657901 886 /**
mbed_official 87:085cde657901 887 * @brief Enables the Clock Security System.
mbed_official 87:085cde657901 888 * @note If a failure is detected on the HSE oscillator clock, this oscillator
mbed_official 87:085cde657901 889 * is automatically disabled and an interrupt is generated to inform the
mbed_official 87:085cde657901 890 * software about the failure (Clock Security System Interrupt, CSSI),
mbed_official 87:085cde657901 891 * allowing the MCU to perform rescue operations. The CSSI is linked to
mbed_official 87:085cde657901 892 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
mbed_official 87:085cde657901 893 * @param None
mbed_official 87:085cde657901 894 * @retval None
mbed_official 87:085cde657901 895 */
mbed_official 87:085cde657901 896 void HAL_RCC_EnableCSS(void)
mbed_official 87:085cde657901 897 {
mbed_official 87:085cde657901 898 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
mbed_official 87:085cde657901 899 }
mbed_official 87:085cde657901 900
mbed_official 87:085cde657901 901 /**
mbed_official 87:085cde657901 902 * @brief Disables the Clock Security System.
mbed_official 87:085cde657901 903 * @param None
mbed_official 87:085cde657901 904 * @retval None
mbed_official 87:085cde657901 905 */
mbed_official 87:085cde657901 906 void HAL_RCC_DisableCSS(void)
mbed_official 87:085cde657901 907 {
mbed_official 87:085cde657901 908 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
mbed_official 87:085cde657901 909 }
mbed_official 87:085cde657901 910
mbed_official 87:085cde657901 911 /**
mbed_official 87:085cde657901 912 * @brief Returns the SYSCLK frequency
mbed_official 87:085cde657901 913 *
mbed_official 87:085cde657901 914 * @note The system frequency computed by this function is not the real
mbed_official 87:085cde657901 915 * frequency in the chip. It is calculated based on the predefined
mbed_official 87:085cde657901 916 * constant and the selected clock source:
mbed_official 87:085cde657901 917 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official 87:085cde657901 918 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official 87:085cde657901 919 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
mbed_official 87:085cde657901 920 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 87:085cde657901 921 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 87:085cde657901 922 * 16 MHz) but the real value may vary depending on the variations
mbed_official 87:085cde657901 923 * in voltage and temperature.
mbed_official 87:085cde657901 924 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 87:085cde657901 925 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 87:085cde657901 926 * frequency of the crystal used. Otherwise, this function may
mbed_official 87:085cde657901 927 * have wrong result.
mbed_official 87:085cde657901 928 *
mbed_official 87:085cde657901 929 * @note The result of this function could be not correct when using fractional
mbed_official 87:085cde657901 930 * value for HSE crystal.
mbed_official 87:085cde657901 931 *
mbed_official 87:085cde657901 932 * @note This function can be used by the user application to compute the
mbed_official 87:085cde657901 933 * baudrate for the communication peripherals or configure other parameters.
mbed_official 87:085cde657901 934 *
mbed_official 87:085cde657901 935 * @note Each time SYSCLK changes, this function must be called to update the
mbed_official 87:085cde657901 936 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 87:085cde657901 937 *
mbed_official 87:085cde657901 938 *
mbed_official 87:085cde657901 939 * @param None
mbed_official 87:085cde657901 940 * @retval SYSCLK frequency
mbed_official 87:085cde657901 941 */
mbed_official 87:085cde657901 942 uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official 87:085cde657901 943 {
mbed_official 87:085cde657901 944 uint32_t pllm = 0, pllvco = 0, pllp = 0;
mbed_official 87:085cde657901 945 uint32_t sysclockfreq = 0;
mbed_official 87:085cde657901 946
mbed_official 87:085cde657901 947 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 87:085cde657901 948 switch (RCC->CFGR & RCC_CFGR_SWS)
mbed_official 87:085cde657901 949 {
mbed_official 87:085cde657901 950 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
mbed_official 87:085cde657901 951 {
mbed_official 87:085cde657901 952 sysclockfreq = HSI_VALUE;
mbed_official 87:085cde657901 953 break;
mbed_official 87:085cde657901 954 }
mbed_official 87:085cde657901 955 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
mbed_official 87:085cde657901 956 {
mbed_official 87:085cde657901 957 sysclockfreq = HSE_VALUE;
mbed_official 87:085cde657901 958 break;
mbed_official 87:085cde657901 959 }
mbed_official 87:085cde657901 960 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
mbed_official 87:085cde657901 961 {
mbed_official 87:085cde657901 962 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
mbed_official 87:085cde657901 963 SYSCLK = PLL_VCO / PLLP */
mbed_official 87:085cde657901 964 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 87:085cde657901 965 if (__RCC_PLLSRC() != 0)
mbed_official 87:085cde657901 966 {
mbed_official 87:085cde657901 967 /* HSE used as PLL clock source */
mbed_official 87:085cde657901 968 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official 87:085cde657901 969 }
mbed_official 87:085cde657901 970 else
mbed_official 87:085cde657901 971 {
mbed_official 87:085cde657901 972 /* HSI used as PLL clock source */
mbed_official 87:085cde657901 973 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official 87:085cde657901 974 }
mbed_official 87:085cde657901 975 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
mbed_official 87:085cde657901 976
mbed_official 87:085cde657901 977 sysclockfreq = pllvco/pllp;
mbed_official 87:085cde657901 978 break;
mbed_official 87:085cde657901 979 }
mbed_official 87:085cde657901 980 default:
mbed_official 87:085cde657901 981 {
mbed_official 87:085cde657901 982 sysclockfreq = HSI_VALUE;
mbed_official 87:085cde657901 983 break;
mbed_official 87:085cde657901 984 }
mbed_official 87:085cde657901 985 }
mbed_official 87:085cde657901 986 return sysclockfreq;
mbed_official 87:085cde657901 987 }
mbed_official 87:085cde657901 988
mbed_official 87:085cde657901 989 /**
mbed_official 87:085cde657901 990 * @brief Returns the HCLK frequency
mbed_official 87:085cde657901 991 * @note Each time HCLK changes, this function must be called to update the
mbed_official 87:085cde657901 992 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 87:085cde657901 993 *
mbed_official 87:085cde657901 994 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official 87:085cde657901 995 * and updated within this function
mbed_official 87:085cde657901 996 * @param None
mbed_official 87:085cde657901 997 * @retval HCLK frequency
mbed_official 87:085cde657901 998 */
mbed_official 87:085cde657901 999 uint32_t HAL_RCC_GetHCLKFreq(void)
mbed_official 87:085cde657901 1000 {
mbed_official 87:085cde657901 1001 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
mbed_official 87:085cde657901 1002 return SystemCoreClock;
mbed_official 87:085cde657901 1003 }
mbed_official 87:085cde657901 1004
mbed_official 87:085cde657901 1005 /**
mbed_official 87:085cde657901 1006 * @brief Returns the PCLK1 frequency
mbed_official 87:085cde657901 1007 * @note Each time PCLK1 changes, this function must be called to update the
mbed_official 87:085cde657901 1008 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 87:085cde657901 1009 * @param None
mbed_official 87:085cde657901 1010 * @retval PCLK1 frequency
mbed_official 87:085cde657901 1011 */
mbed_official 87:085cde657901 1012 uint32_t HAL_RCC_GetPCLK1Freq(void)
mbed_official 87:085cde657901 1013 {
mbed_official 87:085cde657901 1014 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
mbed_official 87:085cde657901 1015 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
mbed_official 87:085cde657901 1016 }
mbed_official 87:085cde657901 1017
mbed_official 87:085cde657901 1018 /**
mbed_official 87:085cde657901 1019 * @brief Returns the PCLK2 frequency
mbed_official 87:085cde657901 1020 * @note Each time PCLK2 changes, this function must be called to update the
mbed_official 87:085cde657901 1021 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 87:085cde657901 1022 * @param None
mbed_official 87:085cde657901 1023 * @retval PCLK2 frequency
mbed_official 87:085cde657901 1024 */
mbed_official 87:085cde657901 1025 uint32_t HAL_RCC_GetPCLK2Freq(void)
mbed_official 87:085cde657901 1026 {
mbed_official 87:085cde657901 1027 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
mbed_official 87:085cde657901 1028 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
mbed_official 87:085cde657901 1029 }
mbed_official 87:085cde657901 1030
mbed_official 87:085cde657901 1031 /**
mbed_official 87:085cde657901 1032 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 87:085cde657901 1033 * RCC configuration registers.
mbed_official 87:085cde657901 1034 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 87:085cde657901 1035 * will be configured.
mbed_official 87:085cde657901 1036 * @retval None
mbed_official 87:085cde657901 1037 */
mbed_official 87:085cde657901 1038 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 87:085cde657901 1039 {
mbed_official 87:085cde657901 1040 /* Set all possible values for the Oscillator type parameter ---------------*/
mbed_official 87:085cde657901 1041 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
mbed_official 87:085cde657901 1042
mbed_official 87:085cde657901 1043 /* Get the HSE configuration -----------------------------------------------*/
mbed_official 87:085cde657901 1044 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
mbed_official 87:085cde657901 1045 {
mbed_official 87:085cde657901 1046 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
mbed_official 87:085cde657901 1047 }
mbed_official 87:085cde657901 1048 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
mbed_official 87:085cde657901 1049 {
mbed_official 87:085cde657901 1050 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
mbed_official 87:085cde657901 1051 }
mbed_official 87:085cde657901 1052 else
mbed_official 87:085cde657901 1053 {
mbed_official 87:085cde657901 1054 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
mbed_official 87:085cde657901 1055 }
mbed_official 87:085cde657901 1056
mbed_official 87:085cde657901 1057 /* Get the HSI configuration -----------------------------------------------*/
mbed_official 87:085cde657901 1058 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
mbed_official 87:085cde657901 1059 {
mbed_official 87:085cde657901 1060 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
mbed_official 87:085cde657901 1061 }
mbed_official 87:085cde657901 1062 else
mbed_official 87:085cde657901 1063 {
mbed_official 87:085cde657901 1064 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
mbed_official 87:085cde657901 1065 }
mbed_official 87:085cde657901 1066
mbed_official 87:085cde657901 1067 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
mbed_official 87:085cde657901 1068
mbed_official 87:085cde657901 1069 /* Get the LSE configuration -----------------------------------------------*/
mbed_official 87:085cde657901 1070 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
mbed_official 87:085cde657901 1071 {
mbed_official 87:085cde657901 1072 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
mbed_official 87:085cde657901 1073 }
mbed_official 87:085cde657901 1074 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
mbed_official 87:085cde657901 1075 {
mbed_official 87:085cde657901 1076 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
mbed_official 87:085cde657901 1077 }
mbed_official 87:085cde657901 1078 else
mbed_official 87:085cde657901 1079 {
mbed_official 87:085cde657901 1080 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
mbed_official 87:085cde657901 1081 }
mbed_official 87:085cde657901 1082
mbed_official 87:085cde657901 1083 /* Get the LSI configuration -----------------------------------------------*/
mbed_official 87:085cde657901 1084 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
mbed_official 87:085cde657901 1085 {
mbed_official 87:085cde657901 1086 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
mbed_official 87:085cde657901 1087 }
mbed_official 87:085cde657901 1088 else
mbed_official 87:085cde657901 1089 {
mbed_official 87:085cde657901 1090 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
mbed_official 87:085cde657901 1091 }
mbed_official 87:085cde657901 1092
mbed_official 87:085cde657901 1093 /* Get the PLL configuration -----------------------------------------------*/
mbed_official 87:085cde657901 1094 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
mbed_official 87:085cde657901 1095 {
mbed_official 87:085cde657901 1096 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
mbed_official 87:085cde657901 1097 }
mbed_official 87:085cde657901 1098 else
mbed_official 87:085cde657901 1099 {
mbed_official 87:085cde657901 1100 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
mbed_official 87:085cde657901 1101 }
mbed_official 87:085cde657901 1102 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
mbed_official 87:085cde657901 1103 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
mbed_official 87:085cde657901 1104 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
mbed_official 87:085cde657901 1105 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
mbed_official 87:085cde657901 1106 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
mbed_official 87:085cde657901 1107 }
mbed_official 87:085cde657901 1108
mbed_official 87:085cde657901 1109 /**
mbed_official 87:085cde657901 1110 * @brief Configures the RCC_ClkInitStruct according to the internal
mbed_official 87:085cde657901 1111 * RCC configuration registers.
mbed_official 87:085cde657901 1112 * @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
mbed_official 87:085cde657901 1113 * will be configured.
mbed_official 87:085cde657901 1114 * @param pFLatency: Pointer on the Flash Latency.
mbed_official 87:085cde657901 1115 * @retval None
mbed_official 87:085cde657901 1116 */
mbed_official 87:085cde657901 1117 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
mbed_official 87:085cde657901 1118 {
mbed_official 87:085cde657901 1119 /* Set all possible values for the Clock type parameter --------------------*/
mbed_official 87:085cde657901 1120 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
mbed_official 87:085cde657901 1121
mbed_official 87:085cde657901 1122 /* Get the SYSCLK configuration --------------------------------------------*/
mbed_official 87:085cde657901 1123 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
mbed_official 87:085cde657901 1124
mbed_official 87:085cde657901 1125 /* Get the HCLK configuration ----------------------------------------------*/
mbed_official 87:085cde657901 1126 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
mbed_official 87:085cde657901 1127
mbed_official 87:085cde657901 1128 /* Get the APB1 configuration ----------------------------------------------*/
mbed_official 87:085cde657901 1129 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
mbed_official 87:085cde657901 1130
mbed_official 87:085cde657901 1131 /* Get the APB2 configuration ----------------------------------------------*/
mbed_official 87:085cde657901 1132 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
mbed_official 87:085cde657901 1133
mbed_official 87:085cde657901 1134 /* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official 87:085cde657901 1135 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official 87:085cde657901 1136 }
mbed_official 87:085cde657901 1137
mbed_official 87:085cde657901 1138 /**
mbed_official 87:085cde657901 1139 * @brief This function handles the RCC CSS interrupt request.
mbed_official 87:085cde657901 1140 * @note This API should be called under the NMI_Handler().
mbed_official 87:085cde657901 1141 * @param None
mbed_official 87:085cde657901 1142 * @retval None
mbed_official 87:085cde657901 1143 */
mbed_official 87:085cde657901 1144 void HAL_RCC_NMI_IRQHandler(void)
mbed_official 87:085cde657901 1145 {
mbed_official 87:085cde657901 1146 /* Check RCC CSSF flag */
mbed_official 87:085cde657901 1147 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
mbed_official 87:085cde657901 1148 {
mbed_official 87:085cde657901 1149 /* RCC Clock Security System interrupt user callback */
mbed_official 87:085cde657901 1150 HAL_RCC_CCSCallback();
mbed_official 87:085cde657901 1151
mbed_official 87:085cde657901 1152 /* Clear RCC CSS pending bit */
mbed_official 87:085cde657901 1153 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
mbed_official 87:085cde657901 1154 }
mbed_official 87:085cde657901 1155 }
mbed_official 87:085cde657901 1156
mbed_official 87:085cde657901 1157 /**
mbed_official 87:085cde657901 1158 * @brief RCC Clock Security System interrupt callback
mbed_official 87:085cde657901 1159 * @param none
mbed_official 87:085cde657901 1160 * @retval none
mbed_official 87:085cde657901 1161 */
mbed_official 87:085cde657901 1162 __weak void HAL_RCC_CCSCallback(void)
mbed_official 87:085cde657901 1163 {
mbed_official 87:085cde657901 1164 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 1165 the HAL_RCC_CCSCallback could be implemented in the user file
mbed_official 87:085cde657901 1166 */
mbed_official 87:085cde657901 1167 }
mbed_official 87:085cde657901 1168
mbed_official 87:085cde657901 1169 /**
mbed_official 87:085cde657901 1170 * @}
mbed_official 87:085cde657901 1171 */
mbed_official 87:085cde657901 1172
mbed_official 87:085cde657901 1173 /**
mbed_official 87:085cde657901 1174 * @}
mbed_official 87:085cde657901 1175 */
mbed_official 87:085cde657901 1176
mbed_official 87:085cde657901 1177 #endif /* HAL_RCC_MODULE_ENABLED */
mbed_official 87:085cde657901 1178 /**
mbed_official 87:085cde657901 1179 * @}
mbed_official 87:085cde657901 1180 */
mbed_official 87:085cde657901 1181
mbed_official 87:085cde657901 1182 /**
mbed_official 87:085cde657901 1183 * @}
mbed_official 87:085cde657901 1184 */
mbed_official 87:085cde657901 1185
mbed_official 87:085cde657901 1186 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/