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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Atmel/TARGET_SAM21/drivers/system/clock/clock_samd21_r21/clock.c@579:53297373a894, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Revision:
- 579:53297373a894
- Child:
- 592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 579:53297373a894 | 1 | /** |
| mbed_official | 579:53297373a894 | 2 | * \file |
| mbed_official | 579:53297373a894 | 3 | * |
| mbed_official | 579:53297373a894 | 4 | * \brief SAM D21/R21 Clock Driver |
| mbed_official | 579:53297373a894 | 5 | * |
| mbed_official | 579:53297373a894 | 6 | * Copyright (C) 2013-2014 Atmel Corporation. All rights reserved. |
| mbed_official | 579:53297373a894 | 7 | * |
| mbed_official | 579:53297373a894 | 8 | * \asf_license_start |
| mbed_official | 579:53297373a894 | 9 | * |
| mbed_official | 579:53297373a894 | 10 | * \page License |
| mbed_official | 579:53297373a894 | 11 | * |
| mbed_official | 579:53297373a894 | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 579:53297373a894 | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 579:53297373a894 | 14 | * |
| mbed_official | 579:53297373a894 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 579:53297373a894 | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 579:53297373a894 | 17 | * |
| mbed_official | 579:53297373a894 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 579:53297373a894 | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 579:53297373a894 | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 579:53297373a894 | 21 | * |
| mbed_official | 579:53297373a894 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| mbed_official | 579:53297373a894 | 23 | * from this software without specific prior written permission. |
| mbed_official | 579:53297373a894 | 24 | * |
| mbed_official | 579:53297373a894 | 25 | * 4. This software may only be redistributed and used in connection with an |
| mbed_official | 579:53297373a894 | 26 | * Atmel microcontroller product. |
| mbed_official | 579:53297373a894 | 27 | * |
| mbed_official | 579:53297373a894 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| mbed_official | 579:53297373a894 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| mbed_official | 579:53297373a894 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| mbed_official | 579:53297373a894 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| mbed_official | 579:53297373a894 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 579:53297373a894 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| mbed_official | 579:53297373a894 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| mbed_official | 579:53297373a894 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| mbed_official | 579:53297373a894 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| mbed_official | 579:53297373a894 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| mbed_official | 579:53297373a894 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 579:53297373a894 | 39 | * |
| mbed_official | 579:53297373a894 | 40 | * \asf_license_stop |
| mbed_official | 579:53297373a894 | 41 | * |
| mbed_official | 579:53297373a894 | 42 | */ |
| mbed_official | 579:53297373a894 | 43 | /** |
| mbed_official | 579:53297373a894 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
| mbed_official | 579:53297373a894 | 45 | */ |
| mbed_official | 579:53297373a894 | 46 | #include <compiler.h> |
| mbed_official | 579:53297373a894 | 47 | #include <clock.h> |
| mbed_official | 579:53297373a894 | 48 | #include <conf_clocks.h> |
| mbed_official | 579:53297373a894 | 49 | #include <system.h> |
| mbed_official | 579:53297373a894 | 50 | |
| mbed_official | 579:53297373a894 | 51 | #ifndef SYSCTRL_FUSES_OSC32K_ADDR |
| mbed_official | 579:53297373a894 | 52 | # define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR |
| mbed_official | 579:53297373a894 | 53 | # define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos |
| mbed_official | 579:53297373a894 | 54 | #endif |
| mbed_official | 579:53297373a894 | 55 | |
| mbed_official | 579:53297373a894 | 56 | /** |
| mbed_official | 579:53297373a894 | 57 | * \internal |
| mbed_official | 579:53297373a894 | 58 | * \brief DFLL-specific data container. |
| mbed_official | 579:53297373a894 | 59 | */ |
| mbed_official | 579:53297373a894 | 60 | struct _system_clock_dfll_config { |
| mbed_official | 579:53297373a894 | 61 | uint32_t control; |
| mbed_official | 579:53297373a894 | 62 | uint32_t val; |
| mbed_official | 579:53297373a894 | 63 | uint32_t mul; |
| mbed_official | 579:53297373a894 | 64 | }; |
| mbed_official | 579:53297373a894 | 65 | |
| mbed_official | 579:53297373a894 | 66 | /** |
| mbed_official | 579:53297373a894 | 67 | * \internal |
| mbed_official | 579:53297373a894 | 68 | * \brief DPLL-specific data container. |
| mbed_official | 579:53297373a894 | 69 | */ |
| mbed_official | 579:53297373a894 | 70 | struct _system_clock_dpll_config { |
| mbed_official | 579:53297373a894 | 71 | uint32_t frequency; |
| mbed_official | 579:53297373a894 | 72 | }; |
| mbed_official | 579:53297373a894 | 73 | |
| mbed_official | 579:53297373a894 | 74 | |
| mbed_official | 579:53297373a894 | 75 | /** |
| mbed_official | 579:53297373a894 | 76 | * \internal |
| mbed_official | 579:53297373a894 | 77 | * \brief XOSC-specific data container. |
| mbed_official | 579:53297373a894 | 78 | */ |
| mbed_official | 579:53297373a894 | 79 | struct _system_clock_xosc_config { |
| mbed_official | 579:53297373a894 | 80 | uint32_t frequency; |
| mbed_official | 579:53297373a894 | 81 | }; |
| mbed_official | 579:53297373a894 | 82 | |
| mbed_official | 579:53297373a894 | 83 | /** |
| mbed_official | 579:53297373a894 | 84 | * \internal |
| mbed_official | 579:53297373a894 | 85 | * \brief System clock module data container. |
| mbed_official | 579:53297373a894 | 86 | */ |
| mbed_official | 579:53297373a894 | 87 | struct _system_clock_module { |
| mbed_official | 579:53297373a894 | 88 | volatile struct _system_clock_dfll_config dfll; |
| mbed_official | 579:53297373a894 | 89 | |
| mbed_official | 579:53297373a894 | 90 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 91 | volatile struct _system_clock_dpll_config dpll; |
| mbed_official | 579:53297373a894 | 92 | #endif |
| mbed_official | 579:53297373a894 | 93 | |
| mbed_official | 579:53297373a894 | 94 | volatile struct _system_clock_xosc_config xosc; |
| mbed_official | 579:53297373a894 | 95 | volatile struct _system_clock_xosc_config xosc32k; |
| mbed_official | 579:53297373a894 | 96 | }; |
| mbed_official | 579:53297373a894 | 97 | |
| mbed_official | 579:53297373a894 | 98 | /** |
| mbed_official | 579:53297373a894 | 99 | * \internal |
| mbed_official | 579:53297373a894 | 100 | * \brief Internal module instance to cache configuration values. |
| mbed_official | 579:53297373a894 | 101 | */ |
| mbed_official | 579:53297373a894 | 102 | static struct _system_clock_module _system_clock_inst = { |
| mbed_official | 579:53297373a894 | 103 | .dfll = { |
| mbed_official | 579:53297373a894 | 104 | .control = 0, |
| mbed_official | 579:53297373a894 | 105 | .val = 0, |
| mbed_official | 579:53297373a894 | 106 | .mul = 0, |
| mbed_official | 579:53297373a894 | 107 | }, |
| mbed_official | 579:53297373a894 | 108 | |
| mbed_official | 579:53297373a894 | 109 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 110 | .dpll = { |
| mbed_official | 579:53297373a894 | 111 | .frequency = 0, |
| mbed_official | 579:53297373a894 | 112 | }, |
| mbed_official | 579:53297373a894 | 113 | #endif |
| mbed_official | 579:53297373a894 | 114 | .xosc = { |
| mbed_official | 579:53297373a894 | 115 | .frequency = 0, |
| mbed_official | 579:53297373a894 | 116 | }, |
| mbed_official | 579:53297373a894 | 117 | .xosc32k = { |
| mbed_official | 579:53297373a894 | 118 | .frequency = 0, |
| mbed_official | 579:53297373a894 | 119 | }, |
| mbed_official | 579:53297373a894 | 120 | }; |
| mbed_official | 579:53297373a894 | 121 | |
| mbed_official | 579:53297373a894 | 122 | /** |
| mbed_official | 579:53297373a894 | 123 | * \internal |
| mbed_official | 579:53297373a894 | 124 | * \brief Wait for sync to the DFLL control registers. |
| mbed_official | 579:53297373a894 | 125 | */ |
| mbed_official | 579:53297373a894 | 126 | static inline void _system_dfll_wait_for_sync(void) |
| mbed_official | 579:53297373a894 | 127 | { |
| mbed_official | 579:53297373a894 | 128 | while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { |
| mbed_official | 579:53297373a894 | 129 | /* Wait for DFLL sync */ |
| mbed_official | 579:53297373a894 | 130 | } |
| mbed_official | 579:53297373a894 | 131 | } |
| mbed_official | 579:53297373a894 | 132 | |
| mbed_official | 579:53297373a894 | 133 | /** |
| mbed_official | 579:53297373a894 | 134 | * \internal |
| mbed_official | 579:53297373a894 | 135 | * \brief Wait for sync to the OSC32K control registers. |
| mbed_official | 579:53297373a894 | 136 | */ |
| mbed_official | 579:53297373a894 | 137 | static inline void _system_osc32k_wait_for_sync(void) |
| mbed_official | 579:53297373a894 | 138 | { |
| mbed_official | 579:53297373a894 | 139 | while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { |
| mbed_official | 579:53297373a894 | 140 | /* Wait for OSC32K sync */ |
| mbed_official | 579:53297373a894 | 141 | } |
| mbed_official | 579:53297373a894 | 142 | } |
| mbed_official | 579:53297373a894 | 143 | |
| mbed_official | 579:53297373a894 | 144 | static inline void _system_clock_source_dfll_set_config_errata_9905(void) |
| mbed_official | 579:53297373a894 | 145 | { |
| mbed_official | 579:53297373a894 | 146 | |
| mbed_official | 579:53297373a894 | 147 | /* Disable ONDEMAND mode while writing configurations */ |
| mbed_official | 579:53297373a894 | 148 | SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND; |
| mbed_official | 579:53297373a894 | 149 | _system_dfll_wait_for_sync(); |
| mbed_official | 579:53297373a894 | 150 | |
| mbed_official | 579:53297373a894 | 151 | SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; |
| mbed_official | 579:53297373a894 | 152 | SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; |
| mbed_official | 579:53297373a894 | 153 | |
| mbed_official | 579:53297373a894 | 154 | /* Write full configuration to DFLL control register */ |
| mbed_official | 579:53297373a894 | 155 | SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; |
| mbed_official | 579:53297373a894 | 156 | } |
| mbed_official | 579:53297373a894 | 157 | |
| mbed_official | 579:53297373a894 | 158 | /** |
| mbed_official | 579:53297373a894 | 159 | * \brief Retrieve the frequency of a clock source. |
| mbed_official | 579:53297373a894 | 160 | * |
| mbed_official | 579:53297373a894 | 161 | * Determines the current operating frequency of a given clock source. |
| mbed_official | 579:53297373a894 | 162 | * |
| mbed_official | 579:53297373a894 | 163 | * \param[in] clock_source Clock source to get the frequency |
| mbed_official | 579:53297373a894 | 164 | * |
| mbed_official | 579:53297373a894 | 165 | * \returns Frequency of the given clock source, in Hz. |
| mbed_official | 579:53297373a894 | 166 | */ |
| mbed_official | 579:53297373a894 | 167 | uint32_t system_clock_source_get_hz( |
| mbed_official | 579:53297373a894 | 168 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 169 | { |
| mbed_official | 579:53297373a894 | 170 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 171 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 172 | return _system_clock_inst.xosc.frequency; |
| mbed_official | 579:53297373a894 | 173 | |
| mbed_official | 579:53297373a894 | 174 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 175 | return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; |
| mbed_official | 579:53297373a894 | 176 | |
| mbed_official | 579:53297373a894 | 177 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 178 | return 32768UL; |
| mbed_official | 579:53297373a894 | 179 | |
| mbed_official | 579:53297373a894 | 180 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 181 | return 32768UL; |
| mbed_official | 579:53297373a894 | 182 | |
| mbed_official | 579:53297373a894 | 183 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 184 | return _system_clock_inst.xosc32k.frequency; |
| mbed_official | 579:53297373a894 | 185 | |
| mbed_official | 579:53297373a894 | 186 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 187 | |
| mbed_official | 579:53297373a894 | 188 | /* Check if the DFLL has been configured */ |
| mbed_official | 579:53297373a894 | 189 | if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) |
| mbed_official | 579:53297373a894 | 190 | return 0; |
| mbed_official | 579:53297373a894 | 191 | |
| mbed_official | 579:53297373a894 | 192 | /* Make sure that the DFLL module is ready */ |
| mbed_official | 579:53297373a894 | 193 | _system_dfll_wait_for_sync(); |
| mbed_official | 579:53297373a894 | 194 | |
| mbed_official | 579:53297373a894 | 195 | /* Check if operating in closed loop mode */ |
| mbed_official | 579:53297373a894 | 196 | if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) { |
| mbed_official | 579:53297373a894 | 197 | return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * |
| mbed_official | 579:53297373a894 | 198 | (_system_clock_inst.dfll.mul & 0xffff); |
| mbed_official | 579:53297373a894 | 199 | } |
| mbed_official | 579:53297373a894 | 200 | |
| mbed_official | 579:53297373a894 | 201 | return 48000000UL; |
| mbed_official | 579:53297373a894 | 202 | |
| mbed_official | 579:53297373a894 | 203 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 204 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 205 | if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { |
| mbed_official | 579:53297373a894 | 206 | return 0; |
| mbed_official | 579:53297373a894 | 207 | } |
| mbed_official | 579:53297373a894 | 208 | |
| mbed_official | 579:53297373a894 | 209 | return _system_clock_inst.dpll.frequency; |
| mbed_official | 579:53297373a894 | 210 | #endif |
| mbed_official | 579:53297373a894 | 211 | |
| mbed_official | 579:53297373a894 | 212 | default: |
| mbed_official | 579:53297373a894 | 213 | return 0; |
| mbed_official | 579:53297373a894 | 214 | } |
| mbed_official | 579:53297373a894 | 215 | } |
| mbed_official | 579:53297373a894 | 216 | |
| mbed_official | 579:53297373a894 | 217 | /** |
| mbed_official | 579:53297373a894 | 218 | * \brief Configure the internal OSC8M oscillator clock source. |
| mbed_official | 579:53297373a894 | 219 | * |
| mbed_official | 579:53297373a894 | 220 | * Configures the 8MHz (nominal) internal RC oscillator with the given |
| mbed_official | 579:53297373a894 | 221 | * configuration settings. |
| mbed_official | 579:53297373a894 | 222 | * |
| mbed_official | 579:53297373a894 | 223 | * \param[in] config OSC8M configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 224 | */ |
| mbed_official | 579:53297373a894 | 225 | void system_clock_source_osc8m_set_config( |
| mbed_official | 579:53297373a894 | 226 | struct system_clock_source_osc8m_config *const config) |
| mbed_official | 579:53297373a894 | 227 | { |
| mbed_official | 579:53297373a894 | 228 | SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; |
| mbed_official | 579:53297373a894 | 229 | |
| mbed_official | 579:53297373a894 | 230 | /* Use temporary struct to reduce register access */ |
| mbed_official | 579:53297373a894 | 231 | temp.bit.PRESC = config->prescaler; |
| mbed_official | 579:53297373a894 | 232 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 233 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 234 | |
| mbed_official | 579:53297373a894 | 235 | SYSCTRL->OSC8M = temp; |
| mbed_official | 579:53297373a894 | 236 | } |
| mbed_official | 579:53297373a894 | 237 | |
| mbed_official | 579:53297373a894 | 238 | /** |
| mbed_official | 579:53297373a894 | 239 | * \brief Configure the internal OSC32K oscillator clock source. |
| mbed_official | 579:53297373a894 | 240 | * |
| mbed_official | 579:53297373a894 | 241 | * Configures the 32KHz (nominal) internal RC oscillator with the given |
| mbed_official | 579:53297373a894 | 242 | * configuration settings. |
| mbed_official | 579:53297373a894 | 243 | * |
| mbed_official | 579:53297373a894 | 244 | * \param[in] config OSC32K configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 245 | */ |
| mbed_official | 579:53297373a894 | 246 | void system_clock_source_osc32k_set_config( |
| mbed_official | 579:53297373a894 | 247 | struct system_clock_source_osc32k_config *const config) |
| mbed_official | 579:53297373a894 | 248 | { |
| mbed_official | 579:53297373a894 | 249 | SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; |
| mbed_official | 579:53297373a894 | 250 | |
| mbed_official | 579:53297373a894 | 251 | /* Update settings via a temporary struct to reduce register access */ |
| mbed_official | 579:53297373a894 | 252 | temp.bit.EN1K = config->enable_1khz_output; |
| mbed_official | 579:53297373a894 | 253 | temp.bit.EN32K = config->enable_32khz_output; |
| mbed_official | 579:53297373a894 | 254 | temp.bit.STARTUP = config->startup_time; |
| mbed_official | 579:53297373a894 | 255 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 256 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 257 | temp.bit.WRTLOCK = config->write_once; |
| mbed_official | 579:53297373a894 | 258 | |
| mbed_official | 579:53297373a894 | 259 | SYSCTRL->OSC32K = temp; |
| mbed_official | 579:53297373a894 | 260 | } |
| mbed_official | 579:53297373a894 | 261 | |
| mbed_official | 579:53297373a894 | 262 | /** |
| mbed_official | 579:53297373a894 | 263 | * \brief Configure the external oscillator clock source. |
| mbed_official | 579:53297373a894 | 264 | * |
| mbed_official | 579:53297373a894 | 265 | * Configures the external oscillator clock source with the given configuration |
| mbed_official | 579:53297373a894 | 266 | * settings. |
| mbed_official | 579:53297373a894 | 267 | * |
| mbed_official | 579:53297373a894 | 268 | * \param[in] config External oscillator configuration structure containing |
| mbed_official | 579:53297373a894 | 269 | * the new config |
| mbed_official | 579:53297373a894 | 270 | */ |
| mbed_official | 579:53297373a894 | 271 | void system_clock_source_xosc_set_config( |
| mbed_official | 579:53297373a894 | 272 | struct system_clock_source_xosc_config *const config) |
| mbed_official | 579:53297373a894 | 273 | { |
| mbed_official | 579:53297373a894 | 274 | SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; |
| mbed_official | 579:53297373a894 | 275 | |
| mbed_official | 579:53297373a894 | 276 | temp.bit.STARTUP = config->startup_time; |
| mbed_official | 579:53297373a894 | 277 | |
| mbed_official | 579:53297373a894 | 278 | if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { |
| mbed_official | 579:53297373a894 | 279 | temp.bit.XTALEN = 1; |
| mbed_official | 579:53297373a894 | 280 | } else { |
| mbed_official | 579:53297373a894 | 281 | temp.bit.XTALEN = 0; |
| mbed_official | 579:53297373a894 | 282 | } |
| mbed_official | 579:53297373a894 | 283 | |
| mbed_official | 579:53297373a894 | 284 | temp.bit.AMPGC = config->auto_gain_control; |
| mbed_official | 579:53297373a894 | 285 | |
| mbed_official | 579:53297373a894 | 286 | /* Set gain if automatic gain control is not selected */ |
| mbed_official | 579:53297373a894 | 287 | if (!config->auto_gain_control) { |
| mbed_official | 579:53297373a894 | 288 | if (config->frequency <= 2000000) { |
| mbed_official | 579:53297373a894 | 289 | temp.bit.GAIN = 0; |
| mbed_official | 579:53297373a894 | 290 | } else if (config->frequency <= 4000000) { |
| mbed_official | 579:53297373a894 | 291 | temp.bit.GAIN = 1; |
| mbed_official | 579:53297373a894 | 292 | } else if (config->frequency <= 8000000) { |
| mbed_official | 579:53297373a894 | 293 | temp.bit.GAIN = 2; |
| mbed_official | 579:53297373a894 | 294 | } else if (config->frequency <= 16000000) { |
| mbed_official | 579:53297373a894 | 295 | temp.bit.GAIN = 3; |
| mbed_official | 579:53297373a894 | 296 | } else if (config->frequency <= 30000000) { |
| mbed_official | 579:53297373a894 | 297 | temp.bit.GAIN = 4; |
| mbed_official | 579:53297373a894 | 298 | } |
| mbed_official | 579:53297373a894 | 299 | |
| mbed_official | 579:53297373a894 | 300 | } |
| mbed_official | 579:53297373a894 | 301 | |
| mbed_official | 579:53297373a894 | 302 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 303 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 304 | |
| mbed_official | 579:53297373a894 | 305 | /* Store XOSC frequency for internal use */ |
| mbed_official | 579:53297373a894 | 306 | _system_clock_inst.xosc.frequency = config->frequency; |
| mbed_official | 579:53297373a894 | 307 | |
| mbed_official | 579:53297373a894 | 308 | SYSCTRL->XOSC = temp; |
| mbed_official | 579:53297373a894 | 309 | } |
| mbed_official | 579:53297373a894 | 310 | |
| mbed_official | 579:53297373a894 | 311 | /** |
| mbed_official | 579:53297373a894 | 312 | * \brief Configure the XOSC32K external 32KHz oscillator clock source. |
| mbed_official | 579:53297373a894 | 313 | * |
| mbed_official | 579:53297373a894 | 314 | * Configures the external 32KHz oscillator clock source with the given |
| mbed_official | 579:53297373a894 | 315 | * configuration settings. |
| mbed_official | 579:53297373a894 | 316 | * |
| mbed_official | 579:53297373a894 | 317 | * \param[in] config XOSC32K configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 318 | */ |
| mbed_official | 579:53297373a894 | 319 | void system_clock_source_xosc32k_set_config( |
| mbed_official | 579:53297373a894 | 320 | struct system_clock_source_xosc32k_config *const config) |
| mbed_official | 579:53297373a894 | 321 | { |
| mbed_official | 579:53297373a894 | 322 | SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; |
| mbed_official | 579:53297373a894 | 323 | |
| mbed_official | 579:53297373a894 | 324 | temp.bit.STARTUP = config->startup_time; |
| mbed_official | 579:53297373a894 | 325 | |
| mbed_official | 579:53297373a894 | 326 | if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { |
| mbed_official | 579:53297373a894 | 327 | temp.bit.XTALEN = 1; |
| mbed_official | 579:53297373a894 | 328 | } else { |
| mbed_official | 579:53297373a894 | 329 | temp.bit.XTALEN = 0; |
| mbed_official | 579:53297373a894 | 330 | } |
| mbed_official | 579:53297373a894 | 331 | |
| mbed_official | 579:53297373a894 | 332 | temp.bit.AAMPEN = config->auto_gain_control; |
| mbed_official | 579:53297373a894 | 333 | temp.bit.EN1K = config->enable_1khz_output; |
| mbed_official | 579:53297373a894 | 334 | temp.bit.EN32K = config->enable_32khz_output; |
| mbed_official | 579:53297373a894 | 335 | |
| mbed_official | 579:53297373a894 | 336 | temp.bit.ONDEMAND = config->on_demand; |
| mbed_official | 579:53297373a894 | 337 | temp.bit.RUNSTDBY = config->run_in_standby; |
| mbed_official | 579:53297373a894 | 338 | temp.bit.WRTLOCK = config->write_once; |
| mbed_official | 579:53297373a894 | 339 | |
| mbed_official | 579:53297373a894 | 340 | /* Cache the new frequency in case the user needs to check the current |
| mbed_official | 579:53297373a894 | 341 | * operating frequency later */ |
| mbed_official | 579:53297373a894 | 342 | _system_clock_inst.xosc32k.frequency = config->frequency; |
| mbed_official | 579:53297373a894 | 343 | |
| mbed_official | 579:53297373a894 | 344 | SYSCTRL->XOSC32K = temp; |
| mbed_official | 579:53297373a894 | 345 | } |
| mbed_official | 579:53297373a894 | 346 | |
| mbed_official | 579:53297373a894 | 347 | /** |
| mbed_official | 579:53297373a894 | 348 | * \brief Configure the DFLL clock source. |
| mbed_official | 579:53297373a894 | 349 | * |
| mbed_official | 579:53297373a894 | 350 | * Configures the Digital Frequency Locked Loop clock source with the given |
| mbed_official | 579:53297373a894 | 351 | * configuration settings. |
| mbed_official | 579:53297373a894 | 352 | * |
| mbed_official | 579:53297373a894 | 353 | * \note The DFLL will be running when this function returns, as the DFLL module |
| mbed_official | 579:53297373a894 | 354 | * needs to be enabled in order to perform the module configuration. |
| mbed_official | 579:53297373a894 | 355 | * |
| mbed_official | 579:53297373a894 | 356 | * \param[in] config DFLL configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 357 | */ |
| mbed_official | 579:53297373a894 | 358 | void system_clock_source_dfll_set_config( |
| mbed_official | 579:53297373a894 | 359 | struct system_clock_source_dfll_config *const config) |
| mbed_official | 579:53297373a894 | 360 | { |
| mbed_official | 579:53297373a894 | 361 | _system_clock_inst.dfll.val = |
| mbed_official | 579:53297373a894 | 362 | SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | |
| mbed_official | 579:53297373a894 | 363 | SYSCTRL_DFLLVAL_FINE(config->fine_value); |
| mbed_official | 579:53297373a894 | 364 | |
| mbed_official | 579:53297373a894 | 365 | _system_clock_inst.dfll.control = |
| mbed_official | 579:53297373a894 | 366 | (uint32_t)config->wakeup_lock | |
| mbed_official | 579:53297373a894 | 367 | (uint32_t)config->stable_tracking | |
| mbed_official | 579:53297373a894 | 368 | (uint32_t)config->quick_lock | |
| mbed_official | 579:53297373a894 | 369 | (uint32_t)config->chill_cycle | |
| mbed_official | 579:53297373a894 | 370 | ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); |
| mbed_official | 579:53297373a894 | 371 | |
| mbed_official | 579:53297373a894 | 372 | if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 373 | |
| mbed_official | 579:53297373a894 | 374 | _system_clock_inst.dfll.mul = |
| mbed_official | 579:53297373a894 | 375 | SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | |
| mbed_official | 579:53297373a894 | 376 | SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | |
| mbed_official | 579:53297373a894 | 377 | SYSCTRL_DFLLMUL_MUL(config->multiply_factor); |
| mbed_official | 579:53297373a894 | 378 | |
| mbed_official | 579:53297373a894 | 379 | /* Enable the closed loop mode */ |
| mbed_official | 579:53297373a894 | 380 | _system_clock_inst.dfll.control |= config->loop_mode; |
| mbed_official | 579:53297373a894 | 381 | } |
| mbed_official | 579:53297373a894 | 382 | if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { |
| mbed_official | 579:53297373a894 | 383 | |
| mbed_official | 579:53297373a894 | 384 | _system_clock_inst.dfll.mul = |
| mbed_official | 579:53297373a894 | 385 | SYSCTRL_DFLLMUL_MUL(config->multiply_factor); |
| mbed_official | 579:53297373a894 | 386 | |
| mbed_official | 579:53297373a894 | 387 | /* Enable the USB recovery mode */ |
| mbed_official | 579:53297373a894 | 388 | _system_clock_inst.dfll.control |= config->loop_mode | |
| mbed_official | 579:53297373a894 | 389 | SYSCTRL_DFLLCTRL_BPLCKC; |
| mbed_official | 579:53297373a894 | 390 | } |
| mbed_official | 579:53297373a894 | 391 | } |
| mbed_official | 579:53297373a894 | 392 | |
| mbed_official | 579:53297373a894 | 393 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 394 | /** |
| mbed_official | 579:53297373a894 | 395 | * \brief Configure the DPLL clock source. |
| mbed_official | 579:53297373a894 | 396 | * |
| mbed_official | 579:53297373a894 | 397 | * Configures the Digital Phase-Locked Loop clock source with the given |
| mbed_official | 579:53297373a894 | 398 | * configuration settings. |
| mbed_official | 579:53297373a894 | 399 | * |
| mbed_official | 579:53297373a894 | 400 | * \note The DPLL will be running when this function returns, as the DPLL module |
| mbed_official | 579:53297373a894 | 401 | * needs to be enabled in order to perform the module configuration. |
| mbed_official | 579:53297373a894 | 402 | * |
| mbed_official | 579:53297373a894 | 403 | * \param[in] config DPLL configuration structure containing the new config |
| mbed_official | 579:53297373a894 | 404 | */ |
| mbed_official | 579:53297373a894 | 405 | void system_clock_source_dpll_set_config( |
| mbed_official | 579:53297373a894 | 406 | struct system_clock_source_dpll_config *const config) |
| mbed_official | 579:53297373a894 | 407 | { |
| mbed_official | 579:53297373a894 | 408 | |
| mbed_official | 579:53297373a894 | 409 | uint32_t tmpldr; |
| mbed_official | 579:53297373a894 | 410 | uint8_t tmpldrfrac; |
| mbed_official | 579:53297373a894 | 411 | uint32_t refclk; |
| mbed_official | 579:53297373a894 | 412 | |
| mbed_official | 579:53297373a894 | 413 | refclk = config->reference_frequency; |
| mbed_official | 579:53297373a894 | 414 | |
| mbed_official | 579:53297373a894 | 415 | /* Only reference clock REF1 can be divided */ |
| mbed_official | 579:53297373a894 | 416 | if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1) { |
| mbed_official | 579:53297373a894 | 417 | refclk = refclk / config->reference_divider; |
| mbed_official | 579:53297373a894 | 418 | } |
| mbed_official | 579:53297373a894 | 419 | |
| mbed_official | 579:53297373a894 | 420 | /* Calculate LDRFRAC and LDR */ |
| mbed_official | 579:53297373a894 | 421 | tmpldr = (config->output_frequency << 4) / refclk; |
| mbed_official | 579:53297373a894 | 422 | tmpldrfrac = tmpldr & 0x0f; |
| mbed_official | 579:53297373a894 | 423 | tmpldr = (tmpldr >> 4) - 1; |
| mbed_official | 579:53297373a894 | 424 | |
| mbed_official | 579:53297373a894 | 425 | SYSCTRL->DPLLCTRLA.reg = |
| mbed_official | 579:53297373a894 | 426 | ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | |
| mbed_official | 579:53297373a894 | 427 | ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); |
| mbed_official | 579:53297373a894 | 428 | |
| mbed_official | 579:53297373a894 | 429 | SYSCTRL->DPLLRATIO.reg = |
| mbed_official | 579:53297373a894 | 430 | SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | |
| mbed_official | 579:53297373a894 | 431 | SYSCTRL_DPLLRATIO_LDR(tmpldr); |
| mbed_official | 579:53297373a894 | 432 | |
| mbed_official | 579:53297373a894 | 433 | SYSCTRL->DPLLCTRLB.reg = |
| mbed_official | 579:53297373a894 | 434 | SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | |
| mbed_official | 579:53297373a894 | 435 | ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | |
| mbed_official | 579:53297373a894 | 436 | SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | |
| mbed_official | 579:53297373a894 | 437 | SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | |
| mbed_official | 579:53297373a894 | 438 | ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | |
| mbed_official | 579:53297373a894 | 439 | ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | |
| mbed_official | 579:53297373a894 | 440 | SYSCTRL_DPLLCTRLB_FILTER(config->filter); |
| mbed_official | 579:53297373a894 | 441 | |
| mbed_official | 579:53297373a894 | 442 | /* |
| mbed_official | 579:53297373a894 | 443 | * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) |
| mbed_official | 579:53297373a894 | 444 | */ |
| mbed_official | 579:53297373a894 | 445 | _system_clock_inst.dpll.frequency = |
| mbed_official | 579:53297373a894 | 446 | (config->reference_frequency * |
| mbed_official | 579:53297373a894 | 447 | (((tmpldr + 1) << 4) + tmpldrfrac) |
| mbed_official | 579:53297373a894 | 448 | ) >> 4; |
| mbed_official | 579:53297373a894 | 449 | } |
| mbed_official | 579:53297373a894 | 450 | #endif |
| mbed_official | 579:53297373a894 | 451 | |
| mbed_official | 579:53297373a894 | 452 | /** |
| mbed_official | 579:53297373a894 | 453 | * \brief Writes the calibration values for a given oscillator clock source. |
| mbed_official | 579:53297373a894 | 454 | * |
| mbed_official | 579:53297373a894 | 455 | * Writes an oscillator calibration value to the given oscillator control |
| mbed_official | 579:53297373a894 | 456 | * registers. The acceptable ranges are: |
| mbed_official | 579:53297373a894 | 457 | * |
| mbed_official | 579:53297373a894 | 458 | * For OSC32K: |
| mbed_official | 579:53297373a894 | 459 | * - 7 bits (max value 128) |
| mbed_official | 579:53297373a894 | 460 | * For OSC8MHZ: |
| mbed_official | 579:53297373a894 | 461 | * - 8 bits (Max value 255) |
| mbed_official | 579:53297373a894 | 462 | * For OSCULP: |
| mbed_official | 579:53297373a894 | 463 | * - 5 bits (Max value 32) |
| mbed_official | 579:53297373a894 | 464 | * |
| mbed_official | 579:53297373a894 | 465 | * \note The frequency range parameter applies only when configuring the 8MHz |
| mbed_official | 579:53297373a894 | 466 | * oscillator and will be ignored for the other oscillators. |
| mbed_official | 579:53297373a894 | 467 | * |
| mbed_official | 579:53297373a894 | 468 | * \param[in] clock_source Clock source to calibrate |
| mbed_official | 579:53297373a894 | 469 | * \param[in] calibration_value Calibration value to write |
| mbed_official | 579:53297373a894 | 470 | * \param[in] freq_range Frequency range (8MHz oscillator only) |
| mbed_official | 579:53297373a894 | 471 | * |
| mbed_official | 579:53297373a894 | 472 | * \retval STATUS_OK The calibration value was written |
| mbed_official | 579:53297373a894 | 473 | * successfully. |
| mbed_official | 579:53297373a894 | 474 | * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock |
| mbed_official | 579:53297373a894 | 475 | * source. |
| mbed_official | 579:53297373a894 | 476 | */ |
| mbed_official | 579:53297373a894 | 477 | enum status_code system_clock_source_write_calibration( |
| mbed_official | 579:53297373a894 | 478 | const enum system_clock_source clock_source, |
| mbed_official | 579:53297373a894 | 479 | const uint16_t calibration_value, |
| mbed_official | 579:53297373a894 | 480 | const uint8_t freq_range) |
| mbed_official | 579:53297373a894 | 481 | { |
| mbed_official | 579:53297373a894 | 482 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 483 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 484 | |
| mbed_official | 579:53297373a894 | 485 | if (calibration_value > 0xfff || freq_range > 4) { |
| mbed_official | 579:53297373a894 | 486 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 487 | } |
| mbed_official | 579:53297373a894 | 488 | |
| mbed_official | 579:53297373a894 | 489 | SYSCTRL->OSC8M.bit.CALIB = calibration_value; |
| mbed_official | 579:53297373a894 | 490 | SYSCTRL->OSC8M.bit.FRANGE = freq_range; |
| mbed_official | 579:53297373a894 | 491 | break; |
| mbed_official | 579:53297373a894 | 492 | |
| mbed_official | 579:53297373a894 | 493 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 494 | |
| mbed_official | 579:53297373a894 | 495 | if (calibration_value > 128) { |
| mbed_official | 579:53297373a894 | 496 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 497 | } |
| mbed_official | 579:53297373a894 | 498 | |
| mbed_official | 579:53297373a894 | 499 | _system_osc32k_wait_for_sync(); |
| mbed_official | 579:53297373a894 | 500 | SYSCTRL->OSC32K.bit.CALIB = calibration_value; |
| mbed_official | 579:53297373a894 | 501 | break; |
| mbed_official | 579:53297373a894 | 502 | |
| mbed_official | 579:53297373a894 | 503 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 504 | |
| mbed_official | 579:53297373a894 | 505 | if (calibration_value > 32) { |
| mbed_official | 579:53297373a894 | 506 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 507 | } |
| mbed_official | 579:53297373a894 | 508 | |
| mbed_official | 579:53297373a894 | 509 | SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; |
| mbed_official | 579:53297373a894 | 510 | break; |
| mbed_official | 579:53297373a894 | 511 | |
| mbed_official | 579:53297373a894 | 512 | default: |
| mbed_official | 579:53297373a894 | 513 | Assert(false); |
| mbed_official | 579:53297373a894 | 514 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 515 | break; |
| mbed_official | 579:53297373a894 | 516 | } |
| mbed_official | 579:53297373a894 | 517 | |
| mbed_official | 579:53297373a894 | 518 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 519 | } |
| mbed_official | 579:53297373a894 | 520 | |
| mbed_official | 579:53297373a894 | 521 | /** |
| mbed_official | 579:53297373a894 | 522 | * \brief Enables a clock source. |
| mbed_official | 579:53297373a894 | 523 | * |
| mbed_official | 579:53297373a894 | 524 | * Enables a clock source which has been previously configured. |
| mbed_official | 579:53297373a894 | 525 | * |
| mbed_official | 579:53297373a894 | 526 | * \param[in] clock_source Clock source to enable |
| mbed_official | 579:53297373a894 | 527 | * |
| mbed_official | 579:53297373a894 | 528 | * \retval STATUS_OK Clock source was enabled successfully and |
| mbed_official | 579:53297373a894 | 529 | * is ready |
| mbed_official | 579:53297373a894 | 530 | * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this |
| mbed_official | 579:53297373a894 | 531 | * device |
| mbed_official | 579:53297373a894 | 532 | */ |
| mbed_official | 579:53297373a894 | 533 | enum status_code system_clock_source_enable( |
| mbed_official | 579:53297373a894 | 534 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 535 | { |
| mbed_official | 579:53297373a894 | 536 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 537 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 538 | SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; |
| mbed_official | 579:53297373a894 | 539 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 540 | |
| mbed_official | 579:53297373a894 | 541 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 542 | SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 543 | break; |
| mbed_official | 579:53297373a894 | 544 | |
| mbed_official | 579:53297373a894 | 545 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 546 | SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; |
| mbed_official | 579:53297373a894 | 547 | break; |
| mbed_official | 579:53297373a894 | 548 | |
| mbed_official | 579:53297373a894 | 549 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 550 | SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 551 | break; |
| mbed_official | 579:53297373a894 | 552 | |
| mbed_official | 579:53297373a894 | 553 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 554 | _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; |
| mbed_official | 579:53297373a894 | 555 | _system_clock_source_dfll_set_config_errata_9905(); |
| mbed_official | 579:53297373a894 | 556 | break; |
| mbed_official | 579:53297373a894 | 557 | |
| mbed_official | 579:53297373a894 | 558 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 559 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 560 | SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; |
| mbed_official | 579:53297373a894 | 561 | break; |
| mbed_official | 579:53297373a894 | 562 | #endif |
| mbed_official | 579:53297373a894 | 563 | |
| mbed_official | 579:53297373a894 | 564 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 565 | /* Always enabled */ |
| mbed_official | 579:53297373a894 | 566 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 567 | |
| mbed_official | 579:53297373a894 | 568 | default: |
| mbed_official | 579:53297373a894 | 569 | Assert(false); |
| mbed_official | 579:53297373a894 | 570 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 571 | } |
| mbed_official | 579:53297373a894 | 572 | |
| mbed_official | 579:53297373a894 | 573 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 574 | } |
| mbed_official | 579:53297373a894 | 575 | |
| mbed_official | 579:53297373a894 | 576 | /** |
| mbed_official | 579:53297373a894 | 577 | * \brief Disables a clock source. |
| mbed_official | 579:53297373a894 | 578 | * |
| mbed_official | 579:53297373a894 | 579 | * Disables a clock source that was previously enabled. |
| mbed_official | 579:53297373a894 | 580 | * |
| mbed_official | 579:53297373a894 | 581 | * \param[in] clock_source Clock source to disable |
| mbed_official | 579:53297373a894 | 582 | * |
| mbed_official | 579:53297373a894 | 583 | * \retval STATUS_OK Clock source was disabled successfully |
| mbed_official | 579:53297373a894 | 584 | * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was |
| mbed_official | 579:53297373a894 | 585 | * given |
| mbed_official | 579:53297373a894 | 586 | */ |
| mbed_official | 579:53297373a894 | 587 | enum status_code system_clock_source_disable( |
| mbed_official | 579:53297373a894 | 588 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 589 | { |
| mbed_official | 579:53297373a894 | 590 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 591 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 592 | SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; |
| mbed_official | 579:53297373a894 | 593 | break; |
| mbed_official | 579:53297373a894 | 594 | |
| mbed_official | 579:53297373a894 | 595 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 596 | SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 597 | break; |
| mbed_official | 579:53297373a894 | 598 | |
| mbed_official | 579:53297373a894 | 599 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 600 | SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; |
| mbed_official | 579:53297373a894 | 601 | break; |
| mbed_official | 579:53297373a894 | 602 | |
| mbed_official | 579:53297373a894 | 603 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 604 | SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; |
| mbed_official | 579:53297373a894 | 605 | break; |
| mbed_official | 579:53297373a894 | 606 | |
| mbed_official | 579:53297373a894 | 607 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 608 | _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; |
| mbed_official | 579:53297373a894 | 609 | SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; |
| mbed_official | 579:53297373a894 | 610 | break; |
| mbed_official | 579:53297373a894 | 611 | |
| mbed_official | 579:53297373a894 | 612 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 613 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 614 | SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; |
| mbed_official | 579:53297373a894 | 615 | break; |
| mbed_official | 579:53297373a894 | 616 | #endif |
| mbed_official | 579:53297373a894 | 617 | |
| mbed_official | 579:53297373a894 | 618 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 619 | /* Not possible to disable */ |
| mbed_official | 579:53297373a894 | 620 | |
| mbed_official | 579:53297373a894 | 621 | default: |
| mbed_official | 579:53297373a894 | 622 | Assert(false); |
| mbed_official | 579:53297373a894 | 623 | return STATUS_ERR_INVALID_ARG; |
| mbed_official | 579:53297373a894 | 624 | |
| mbed_official | 579:53297373a894 | 625 | } |
| mbed_official | 579:53297373a894 | 626 | |
| mbed_official | 579:53297373a894 | 627 | return STATUS_OK; |
| mbed_official | 579:53297373a894 | 628 | } |
| mbed_official | 579:53297373a894 | 629 | |
| mbed_official | 579:53297373a894 | 630 | /** |
| mbed_official | 579:53297373a894 | 631 | * \brief Checks if a clock source is ready. |
| mbed_official | 579:53297373a894 | 632 | * |
| mbed_official | 579:53297373a894 | 633 | * Checks if a given clock source is ready to be used. |
| mbed_official | 579:53297373a894 | 634 | * |
| mbed_official | 579:53297373a894 | 635 | * \param[in] clock_source Clock source to check if ready |
| mbed_official | 579:53297373a894 | 636 | * |
| mbed_official | 579:53297373a894 | 637 | * \returns Ready state of the given clock source. |
| mbed_official | 579:53297373a894 | 638 | * |
| mbed_official | 579:53297373a894 | 639 | * \retval true Clock source is enabled and ready |
| mbed_official | 579:53297373a894 | 640 | * \retval false Clock source is disabled or not yet ready |
| mbed_official | 579:53297373a894 | 641 | */ |
| mbed_official | 579:53297373a894 | 642 | bool system_clock_source_is_ready( |
| mbed_official | 579:53297373a894 | 643 | const enum system_clock_source clock_source) |
| mbed_official | 579:53297373a894 | 644 | { |
| mbed_official | 579:53297373a894 | 645 | uint32_t mask = 0; |
| mbed_official | 579:53297373a894 | 646 | |
| mbed_official | 579:53297373a894 | 647 | switch (clock_source) { |
| mbed_official | 579:53297373a894 | 648 | case SYSTEM_CLOCK_SOURCE_OSC8M: |
| mbed_official | 579:53297373a894 | 649 | mask = SYSCTRL_PCLKSR_OSC8MRDY; |
| mbed_official | 579:53297373a894 | 650 | break; |
| mbed_official | 579:53297373a894 | 651 | |
| mbed_official | 579:53297373a894 | 652 | case SYSTEM_CLOCK_SOURCE_OSC32K: |
| mbed_official | 579:53297373a894 | 653 | mask = SYSCTRL_PCLKSR_OSC32KRDY; |
| mbed_official | 579:53297373a894 | 654 | break; |
| mbed_official | 579:53297373a894 | 655 | |
| mbed_official | 579:53297373a894 | 656 | case SYSTEM_CLOCK_SOURCE_XOSC: |
| mbed_official | 579:53297373a894 | 657 | mask = SYSCTRL_PCLKSR_XOSCRDY; |
| mbed_official | 579:53297373a894 | 658 | break; |
| mbed_official | 579:53297373a894 | 659 | |
| mbed_official | 579:53297373a894 | 660 | case SYSTEM_CLOCK_SOURCE_XOSC32K: |
| mbed_official | 579:53297373a894 | 661 | mask = SYSCTRL_PCLKSR_XOSC32KRDY; |
| mbed_official | 579:53297373a894 | 662 | break; |
| mbed_official | 579:53297373a894 | 663 | |
| mbed_official | 579:53297373a894 | 664 | case SYSTEM_CLOCK_SOURCE_DFLL: |
| mbed_official | 579:53297373a894 | 665 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 666 | mask = (SYSCTRL_PCLKSR_DFLLRDY | |
| mbed_official | 579:53297373a894 | 667 | SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); |
| mbed_official | 579:53297373a894 | 668 | } else { |
| mbed_official | 579:53297373a894 | 669 | mask = SYSCTRL_PCLKSR_DFLLRDY; |
| mbed_official | 579:53297373a894 | 670 | } |
| mbed_official | 579:53297373a894 | 671 | break; |
| mbed_official | 579:53297373a894 | 672 | |
| mbed_official | 579:53297373a894 | 673 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 674 | case SYSTEM_CLOCK_SOURCE_DPLL: |
| mbed_official | 579:53297373a894 | 675 | return ((SYSCTRL->DPLLSTATUS.reg & |
| mbed_official | 579:53297373a894 | 676 | (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == |
| mbed_official | 579:53297373a894 | 677 | (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); |
| mbed_official | 579:53297373a894 | 678 | #endif |
| mbed_official | 579:53297373a894 | 679 | |
| mbed_official | 579:53297373a894 | 680 | case SYSTEM_CLOCK_SOURCE_ULP32K: |
| mbed_official | 579:53297373a894 | 681 | /* Not possible to disable */ |
| mbed_official | 579:53297373a894 | 682 | return true; |
| mbed_official | 579:53297373a894 | 683 | |
| mbed_official | 579:53297373a894 | 684 | default: |
| mbed_official | 579:53297373a894 | 685 | return false; |
| mbed_official | 579:53297373a894 | 686 | } |
| mbed_official | 579:53297373a894 | 687 | |
| mbed_official | 579:53297373a894 | 688 | return ((SYSCTRL->PCLKSR.reg & mask) == mask); |
| mbed_official | 579:53297373a894 | 689 | } |
| mbed_official | 579:53297373a894 | 690 | |
| mbed_official | 579:53297373a894 | 691 | /* Include some checks for conf_clocks.h validation */ |
| mbed_official | 579:53297373a894 | 692 | #include "clock_config_check.h" |
| mbed_official | 579:53297373a894 | 693 | |
| mbed_official | 579:53297373a894 | 694 | #if !defined(__DOXYGEN__) |
| mbed_official | 579:53297373a894 | 695 | /** \internal |
| mbed_official | 579:53297373a894 | 696 | * |
| mbed_official | 579:53297373a894 | 697 | * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. |
| mbed_official | 579:53297373a894 | 698 | */ |
| mbed_official | 579:53297373a894 | 699 | # define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ |
| mbed_official | 579:53297373a894 | 700 | if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ |
| mbed_official | 579:53297373a894 | 701 | struct system_gclk_gen_config gclk_conf; \ |
| mbed_official | 579:53297373a894 | 702 | system_gclk_gen_get_config_defaults(&gclk_conf); \ |
| mbed_official | 579:53297373a894 | 703 | gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ |
| mbed_official | 579:53297373a894 | 704 | gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ |
| mbed_official | 579:53297373a894 | 705 | gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ |
| mbed_official | 579:53297373a894 | 706 | gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ |
| mbed_official | 579:53297373a894 | 707 | system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ |
| mbed_official | 579:53297373a894 | 708 | system_gclk_gen_enable(GCLK_GENERATOR_##n); \ |
| mbed_official | 579:53297373a894 | 709 | } |
| mbed_official | 579:53297373a894 | 710 | |
| mbed_official | 579:53297373a894 | 711 | /** \internal |
| mbed_official | 579:53297373a894 | 712 | * |
| mbed_official | 579:53297373a894 | 713 | * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, |
| mbed_official | 579:53297373a894 | 714 | * provided that it is not the main Generic Clock Generator channel. |
| mbed_official | 579:53297373a894 | 715 | */ |
| mbed_official | 579:53297373a894 | 716 | # define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ |
| mbed_official | 579:53297373a894 | 717 | if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } |
| mbed_official | 579:53297373a894 | 718 | #endif |
| mbed_official | 579:53297373a894 | 719 | |
| mbed_official | 579:53297373a894 | 720 | /** \internal |
| mbed_official | 579:53297373a894 | 721 | * |
| mbed_official | 579:53297373a894 | 722 | * Switch all peripheral clock to a not enabled general clock |
| mbed_official | 579:53297373a894 | 723 | * to save power. |
| mbed_official | 579:53297373a894 | 724 | */ |
| mbed_official | 579:53297373a894 | 725 | static void _switch_peripheral_gclk(void) |
| mbed_official | 579:53297373a894 | 726 | { |
| mbed_official | 579:53297373a894 | 727 | uint32_t gclk_id; |
| mbed_official | 579:53297373a894 | 728 | struct system_gclk_chan_config gclk_conf; |
| mbed_official | 579:53297373a894 | 729 | |
| mbed_official | 579:53297373a894 | 730 | #if CONF_CLOCK_GCLK_1_ENABLE == false |
| mbed_official | 579:53297373a894 | 731 | gclk_conf.source_generator = GCLK_GENERATOR_1; |
| mbed_official | 579:53297373a894 | 732 | #elif CONF_CLOCK_GCLK_2_ENABLE == false |
| mbed_official | 579:53297373a894 | 733 | gclk_conf.source_generator = GCLK_GENERATOR_2; |
| mbed_official | 579:53297373a894 | 734 | #elif CONF_CLOCK_GCLK_3_ENABLE == false |
| mbed_official | 579:53297373a894 | 735 | gclk_conf.source_generator = GCLK_GENERATOR_3; |
| mbed_official | 579:53297373a894 | 736 | #elif CONF_CLOCK_GCLK_4_ENABLE == false |
| mbed_official | 579:53297373a894 | 737 | gclk_conf.source_generator = GCLK_GENERATOR_4; |
| mbed_official | 579:53297373a894 | 738 | #elif CONF_CLOCK_GCLK_5_ENABLE == false |
| mbed_official | 579:53297373a894 | 739 | gclk_conf.source_generator = GCLK_GENERATOR_5; |
| mbed_official | 579:53297373a894 | 740 | #elif CONF_CLOCK_GCLK_6_ENABLE == false |
| mbed_official | 579:53297373a894 | 741 | gclk_conf.source_generator = GCLK_GENERATOR_6; |
| mbed_official | 579:53297373a894 | 742 | #elif CONF_CLOCK_GCLK_7_ENABLE == false |
| mbed_official | 579:53297373a894 | 743 | gclk_conf.source_generator = GCLK_GENERATOR_7; |
| mbed_official | 579:53297373a894 | 744 | #else |
| mbed_official | 579:53297373a894 | 745 | gclk_conf.source_generator = GCLK_GENERATOR_7; |
| mbed_official | 579:53297373a894 | 746 | #endif |
| mbed_official | 579:53297373a894 | 747 | |
| mbed_official | 579:53297373a894 | 748 | for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { |
| mbed_official | 579:53297373a894 | 749 | system_gclk_chan_set_config(gclk_id, &gclk_conf); |
| mbed_official | 579:53297373a894 | 750 | } |
| mbed_official | 579:53297373a894 | 751 | } |
| mbed_official | 579:53297373a894 | 752 | |
| mbed_official | 579:53297373a894 | 753 | /** |
| mbed_official | 579:53297373a894 | 754 | * \brief Initialize clock system based on the configuration in conf_clocks.h. |
| mbed_official | 579:53297373a894 | 755 | * |
| mbed_official | 579:53297373a894 | 756 | * This function will apply the settings in conf_clocks.h when run from the user |
| mbed_official | 579:53297373a894 | 757 | * application. All clock sources and GCLK generators are running when this function |
| mbed_official | 579:53297373a894 | 758 | * returns. |
| mbed_official | 579:53297373a894 | 759 | * |
| mbed_official | 579:53297373a894 | 760 | * \note OSC8M is always enabled and if user selects other clocks for GCLK generators, |
| mbed_official | 579:53297373a894 | 761 | * the OSC8M default enable can be disabled after system_clock_init. Make sure the |
| mbed_official | 579:53297373a894 | 762 | * clock switch successfully before disabling OSC8M. |
| mbed_official | 579:53297373a894 | 763 | */ |
| mbed_official | 579:53297373a894 | 764 | void system_clock_init(void) |
| mbed_official | 579:53297373a894 | 765 | { |
| mbed_official | 579:53297373a894 | 766 | /* Various bits in the INTFLAG register can be set to one at startup. |
| mbed_official | 579:53297373a894 | 767 | This will ensure that these bits are cleared */ |
| mbed_official | 579:53297373a894 | 768 | SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | |
| mbed_official | 579:53297373a894 | 769 | SYSCTRL_INTFLAG_DFLLRDY; |
| mbed_official | 579:53297373a894 | 770 | |
| mbed_official | 579:53297373a894 | 771 | system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); |
| mbed_official | 579:53297373a894 | 772 | |
| mbed_official | 579:53297373a894 | 773 | /* Switch all peripheral clock to a not enabled general clock to save power. */ |
| mbed_official | 579:53297373a894 | 774 | _switch_peripheral_gclk(); |
| mbed_official | 579:53297373a894 | 775 | |
| mbed_official | 579:53297373a894 | 776 | /* XOSC */ |
| mbed_official | 579:53297373a894 | 777 | #if CONF_CLOCK_XOSC_ENABLE == true |
| mbed_official | 579:53297373a894 | 778 | struct system_clock_source_xosc_config xosc_conf; |
| mbed_official | 579:53297373a894 | 779 | system_clock_source_xosc_get_config_defaults(&xosc_conf); |
| mbed_official | 579:53297373a894 | 780 | |
| mbed_official | 579:53297373a894 | 781 | xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; |
| mbed_official | 579:53297373a894 | 782 | xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; |
| mbed_official | 579:53297373a894 | 783 | xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; |
| mbed_official | 579:53297373a894 | 784 | xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; |
| mbed_official | 579:53297373a894 | 785 | xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; |
| mbed_official | 579:53297373a894 | 786 | xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 787 | |
| mbed_official | 579:53297373a894 | 788 | system_clock_source_xosc_set_config(&xosc_conf); |
| mbed_official | 579:53297373a894 | 789 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); |
| mbed_official | 579:53297373a894 | 790 | #endif |
| mbed_official | 579:53297373a894 | 791 | |
| mbed_official | 579:53297373a894 | 792 | |
| mbed_official | 579:53297373a894 | 793 | /* XOSC32K */ |
| mbed_official | 579:53297373a894 | 794 | #if CONF_CLOCK_XOSC32K_ENABLE == true |
| mbed_official | 579:53297373a894 | 795 | struct system_clock_source_xosc32k_config xosc32k_conf; |
| mbed_official | 579:53297373a894 | 796 | system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); |
| mbed_official | 579:53297373a894 | 797 | |
| mbed_official | 579:53297373a894 | 798 | xosc32k_conf.frequency = 32768UL; |
| mbed_official | 579:53297373a894 | 799 | xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; |
| mbed_official | 579:53297373a894 | 800 | xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; |
| mbed_official | 579:53297373a894 | 801 | xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; |
| mbed_official | 579:53297373a894 | 802 | xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; |
| mbed_official | 579:53297373a894 | 803 | xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; |
| mbed_official | 579:53297373a894 | 804 | xosc32k_conf.on_demand = false; |
| mbed_official | 579:53297373a894 | 805 | xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 806 | |
| mbed_official | 579:53297373a894 | 807 | system_clock_source_xosc32k_set_config(&xosc32k_conf); |
| mbed_official | 579:53297373a894 | 808 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); |
| mbed_official | 579:53297373a894 | 809 | while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); |
| mbed_official | 579:53297373a894 | 810 | if (CONF_CLOCK_XOSC32K_ON_DEMAND) { |
| mbed_official | 579:53297373a894 | 811 | SYSCTRL->XOSC32K.bit.ONDEMAND = 1; |
| mbed_official | 579:53297373a894 | 812 | } |
| mbed_official | 579:53297373a894 | 813 | #endif |
| mbed_official | 579:53297373a894 | 814 | |
| mbed_official | 579:53297373a894 | 815 | |
| mbed_official | 579:53297373a894 | 816 | /* OSCK32K */ |
| mbed_official | 579:53297373a894 | 817 | #if CONF_CLOCK_OSC32K_ENABLE == true |
| mbed_official | 579:53297373a894 | 818 | SYSCTRL->OSC32K.bit.CALIB = |
| mbed_official | 579:53297373a894 | 819 | (*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> SYSCTRL_FUSES_OSC32K_Pos); |
| mbed_official | 579:53297373a894 | 820 | |
| mbed_official | 579:53297373a894 | 821 | struct system_clock_source_osc32k_config osc32k_conf; |
| mbed_official | 579:53297373a894 | 822 | system_clock_source_osc32k_get_config_defaults(&osc32k_conf); |
| mbed_official | 579:53297373a894 | 823 | |
| mbed_official | 579:53297373a894 | 824 | osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; |
| mbed_official | 579:53297373a894 | 825 | osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; |
| mbed_official | 579:53297373a894 | 826 | osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; |
| mbed_official | 579:53297373a894 | 827 | osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; |
| mbed_official | 579:53297373a894 | 828 | osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 829 | |
| mbed_official | 579:53297373a894 | 830 | system_clock_source_osc32k_set_config(&osc32k_conf); |
| mbed_official | 579:53297373a894 | 831 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); |
| mbed_official | 579:53297373a894 | 832 | #endif |
| mbed_official | 579:53297373a894 | 833 | |
| mbed_official | 579:53297373a894 | 834 | |
| mbed_official | 579:53297373a894 | 835 | /* DFLL Config (Open and Closed Loop) */ |
| mbed_official | 579:53297373a894 | 836 | #if CONF_CLOCK_DFLL_ENABLE == true |
| mbed_official | 579:53297373a894 | 837 | struct system_clock_source_dfll_config dfll_conf; |
| mbed_official | 579:53297373a894 | 838 | system_clock_source_dfll_get_config_defaults(&dfll_conf); |
| mbed_official | 579:53297373a894 | 839 | |
| mbed_official | 579:53297373a894 | 840 | dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; |
| mbed_official | 579:53297373a894 | 841 | dfll_conf.on_demand = false; |
| mbed_official | 579:53297373a894 | 842 | |
| mbed_official | 579:53297373a894 | 843 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { |
| mbed_official | 579:53297373a894 | 844 | dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE; |
| mbed_official | 579:53297373a894 | 845 | dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; |
| mbed_official | 579:53297373a894 | 846 | } |
| mbed_official | 579:53297373a894 | 847 | |
| mbed_official | 579:53297373a894 | 848 | # if CONF_CLOCK_DFLL_QUICK_LOCK == true |
| mbed_official | 579:53297373a894 | 849 | dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; |
| mbed_official | 579:53297373a894 | 850 | # else |
| mbed_official | 579:53297373a894 | 851 | dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; |
| mbed_official | 579:53297373a894 | 852 | # endif |
| mbed_official | 579:53297373a894 | 853 | |
| mbed_official | 579:53297373a894 | 854 | # if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true |
| mbed_official | 579:53297373a894 | 855 | dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; |
| mbed_official | 579:53297373a894 | 856 | # else |
| mbed_official | 579:53297373a894 | 857 | dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; |
| mbed_official | 579:53297373a894 | 858 | # endif |
| mbed_official | 579:53297373a894 | 859 | |
| mbed_official | 579:53297373a894 | 860 | # if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true |
| mbed_official | 579:53297373a894 | 861 | dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; |
| mbed_official | 579:53297373a894 | 862 | # else |
| mbed_official | 579:53297373a894 | 863 | dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; |
| mbed_official | 579:53297373a894 | 864 | # endif |
| mbed_official | 579:53297373a894 | 865 | |
| mbed_official | 579:53297373a894 | 866 | # if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true |
| mbed_official | 579:53297373a894 | 867 | dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; |
| mbed_official | 579:53297373a894 | 868 | # else |
| mbed_official | 579:53297373a894 | 869 | dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; |
| mbed_official | 579:53297373a894 | 870 | # endif |
| mbed_official | 579:53297373a894 | 871 | |
| mbed_official | 579:53297373a894 | 872 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 873 | dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; |
| mbed_official | 579:53297373a894 | 874 | } |
| mbed_official | 579:53297373a894 | 875 | |
| mbed_official | 579:53297373a894 | 876 | dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; |
| mbed_official | 579:53297373a894 | 877 | dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; |
| mbed_official | 579:53297373a894 | 878 | |
| mbed_official | 579:53297373a894 | 879 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { |
| mbed_official | 579:53297373a894 | 880 | #define NVM_DFLL_COARSE_POS 58 |
| mbed_official | 579:53297373a894 | 881 | #define NVM_DFLL_COARSE_SIZE 6 |
| mbed_official | 579:53297373a894 | 882 | #define NVM_DFLL_FINE_POS 64 |
| mbed_official | 579:53297373a894 | 883 | #define NVM_DFLL_FINE_SIZE 10 |
| mbed_official | 579:53297373a894 | 884 | uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) |
| mbed_official | 579:53297373a894 | 885 | + (NVM_DFLL_COARSE_POS / 32)) |
| mbed_official | 579:53297373a894 | 886 | >> (NVM_DFLL_COARSE_POS % 32)) |
| mbed_official | 579:53297373a894 | 887 | & ((1 << NVM_DFLL_COARSE_SIZE) - 1); |
| mbed_official | 579:53297373a894 | 888 | if (coarse == 0x3f) { |
| mbed_official | 579:53297373a894 | 889 | coarse = 0x1f; |
| mbed_official | 579:53297373a894 | 890 | } |
| mbed_official | 579:53297373a894 | 891 | uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4) |
| mbed_official | 579:53297373a894 | 892 | + (NVM_DFLL_FINE_POS / 32)) |
| mbed_official | 579:53297373a894 | 893 | >> (NVM_DFLL_FINE_POS % 32)) |
| mbed_official | 579:53297373a894 | 894 | & ((1 << NVM_DFLL_FINE_SIZE) - 1); |
| mbed_official | 579:53297373a894 | 895 | if (fine == 0x3ff) { |
| mbed_official | 579:53297373a894 | 896 | fine = 0x1ff; |
| mbed_official | 579:53297373a894 | 897 | } |
| mbed_official | 579:53297373a894 | 898 | dfll_conf.coarse_value = coarse; |
| mbed_official | 579:53297373a894 | 899 | dfll_conf.fine_value = fine; |
| mbed_official | 579:53297373a894 | 900 | |
| mbed_official | 579:53297373a894 | 901 | dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; |
| mbed_official | 579:53297373a894 | 902 | dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; |
| mbed_official | 579:53297373a894 | 903 | dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; |
| mbed_official | 579:53297373a894 | 904 | dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; |
| mbed_official | 579:53297373a894 | 905 | |
| mbed_official | 579:53297373a894 | 906 | dfll_conf.multiply_factor = 48000; |
| mbed_official | 579:53297373a894 | 907 | } |
| mbed_official | 579:53297373a894 | 908 | |
| mbed_official | 579:53297373a894 | 909 | system_clock_source_dfll_set_config(&dfll_conf); |
| mbed_official | 579:53297373a894 | 910 | #endif |
| mbed_official | 579:53297373a894 | 911 | |
| mbed_official | 579:53297373a894 | 912 | |
| mbed_official | 579:53297373a894 | 913 | /* OSC8M */ |
| mbed_official | 579:53297373a894 | 914 | struct system_clock_source_osc8m_config osc8m_conf; |
| mbed_official | 579:53297373a894 | 915 | system_clock_source_osc8m_get_config_defaults(&osc8m_conf); |
| mbed_official | 579:53297373a894 | 916 | |
| mbed_official | 579:53297373a894 | 917 | osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; |
| mbed_official | 579:53297373a894 | 918 | osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; |
| mbed_official | 579:53297373a894 | 919 | osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 920 | |
| mbed_official | 579:53297373a894 | 921 | system_clock_source_osc8m_set_config(&osc8m_conf); |
| mbed_official | 579:53297373a894 | 922 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); |
| mbed_official | 579:53297373a894 | 923 | |
| mbed_official | 579:53297373a894 | 924 | |
| mbed_official | 579:53297373a894 | 925 | /* GCLK */ |
| mbed_official | 579:53297373a894 | 926 | #if CONF_CLOCK_CONFIGURE_GCLK == true |
| mbed_official | 579:53297373a894 | 927 | system_gclk_init(); |
| mbed_official | 579:53297373a894 | 928 | |
| mbed_official | 579:53297373a894 | 929 | /* Configure all GCLK generators except for the main generator, which |
| mbed_official | 579:53297373a894 | 930 | * is configured later after all other clock systems are set up */ |
| mbed_official | 579:53297373a894 | 931 | MREPEAT(8, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); |
| mbed_official | 579:53297373a894 | 932 | |
| mbed_official | 579:53297373a894 | 933 | # if CONF_CLOCK_DFLL_ENABLE == true |
| mbed_official | 579:53297373a894 | 934 | /* Enable DFLL reference clock if in closed loop mode */ |
| mbed_official | 579:53297373a894 | 935 | if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { |
| mbed_official | 579:53297373a894 | 936 | struct system_gclk_chan_config dfll_gclk_chan_conf; |
| mbed_official | 579:53297373a894 | 937 | |
| mbed_official | 579:53297373a894 | 938 | system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); |
| mbed_official | 579:53297373a894 | 939 | dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; |
| mbed_official | 579:53297373a894 | 940 | system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); |
| mbed_official | 579:53297373a894 | 941 | system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); |
| mbed_official | 579:53297373a894 | 942 | } |
| mbed_official | 579:53297373a894 | 943 | # endif |
| mbed_official | 579:53297373a894 | 944 | #endif |
| mbed_official | 579:53297373a894 | 945 | |
| mbed_official | 579:53297373a894 | 946 | |
| mbed_official | 579:53297373a894 | 947 | /* DFLL Enable (Open and Closed Loop) */ |
| mbed_official | 579:53297373a894 | 948 | #if CONF_CLOCK_DFLL_ENABLE == true |
| mbed_official | 579:53297373a894 | 949 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); |
| mbed_official | 579:53297373a894 | 950 | while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); |
| mbed_official | 579:53297373a894 | 951 | if (CONF_CLOCK_DFLL_ON_DEMAND) { |
| mbed_official | 579:53297373a894 | 952 | SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; |
| mbed_official | 579:53297373a894 | 953 | } |
| mbed_official | 579:53297373a894 | 954 | #endif |
| mbed_official | 579:53297373a894 | 955 | |
| mbed_official | 579:53297373a894 | 956 | /* DPLL */ |
| mbed_official | 579:53297373a894 | 957 | #ifdef FEATURE_SYSTEM_CLOCK_DPLL |
| mbed_official | 579:53297373a894 | 958 | # if (CONF_CLOCK_DPLL_ENABLE == true) |
| mbed_official | 579:53297373a894 | 959 | |
| mbed_official | 579:53297373a894 | 960 | /* Enable DPLL reference clock */ |
| mbed_official | 579:53297373a894 | 961 | if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0) { |
| mbed_official | 579:53297373a894 | 962 | /* XOSC32K should have been enabled for DPLL_REF0 */ |
| mbed_official | 579:53297373a894 | 963 | Assert(CONF_CLOCK_XOSC32K_ENABLE); |
| mbed_official | 579:53297373a894 | 964 | } |
| mbed_official | 579:53297373a894 | 965 | |
| mbed_official | 579:53297373a894 | 966 | struct system_clock_source_dpll_config dpll_config; |
| mbed_official | 579:53297373a894 | 967 | system_clock_source_dpll_get_config_defaults(&dpll_config); |
| mbed_official | 579:53297373a894 | 968 | |
| mbed_official | 579:53297373a894 | 969 | dpll_config.on_demand = false; |
| mbed_official | 579:53297373a894 | 970 | dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; |
| mbed_official | 579:53297373a894 | 971 | dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; |
| mbed_official | 579:53297373a894 | 972 | dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; |
| mbed_official | 579:53297373a894 | 973 | dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; |
| mbed_official | 579:53297373a894 | 974 | |
| mbed_official | 579:53297373a894 | 975 | dpll_config.filter = CONF_CLOCK_DPLL_FILTER; |
| mbed_official | 579:53297373a894 | 976 | |
| mbed_official | 579:53297373a894 | 977 | dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; |
| mbed_official | 579:53297373a894 | 978 | dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; |
| mbed_official | 579:53297373a894 | 979 | dpll_config.reference_divider = CONF_CLOCK_DPLL_REFEREMCE_DIVIDER; |
| mbed_official | 579:53297373a894 | 980 | dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; |
| mbed_official | 579:53297373a894 | 981 | |
| mbed_official | 579:53297373a894 | 982 | system_clock_source_dpll_set_config(&dpll_config); |
| mbed_official | 579:53297373a894 | 983 | system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); |
| mbed_official | 579:53297373a894 | 984 | while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); |
| mbed_official | 579:53297373a894 | 985 | if (CONF_CLOCK_DPLL_ON_DEMAND) { |
| mbed_official | 579:53297373a894 | 986 | SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; |
| mbed_official | 579:53297373a894 | 987 | } |
| mbed_official | 579:53297373a894 | 988 | |
| mbed_official | 579:53297373a894 | 989 | # endif |
| mbed_official | 579:53297373a894 | 990 | #endif |
| mbed_official | 579:53297373a894 | 991 | |
| mbed_official | 579:53297373a894 | 992 | /* CPU and BUS clocks */ |
| mbed_official | 579:53297373a894 | 993 | system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); |
| mbed_official | 579:53297373a894 | 994 | |
| mbed_official | 579:53297373a894 | 995 | system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); |
| mbed_official | 579:53297373a894 | 996 | system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); |
| mbed_official | 579:53297373a894 | 997 | |
| mbed_official | 579:53297373a894 | 998 | /* GCLK 0 */ |
| mbed_official | 579:53297373a894 | 999 | #if CONF_CLOCK_CONFIGURE_GCLK == true |
| mbed_official | 579:53297373a894 | 1000 | /* Configure the main GCLK last as it might depend on other generators */ |
| mbed_official | 579:53297373a894 | 1001 | _CONF_CLOCK_GCLK_CONFIG(0, ~); |
| mbed_official | 579:53297373a894 | 1002 | #endif |
| mbed_official | 579:53297373a894 | 1003 | } |
