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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_nvmctrl.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Child:
592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 /**
mbed_official 579:53297373a894 2 * \file
mbed_official 579:53297373a894 3 *
mbed_official 579:53297373a894 4 * \brief Component description for NVMCTRL
mbed_official 579:53297373a894 5 *
mbed_official 579:53297373a894 6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
mbed_official 579:53297373a894 7 *
mbed_official 579:53297373a894 8 * \asf_license_start
mbed_official 579:53297373a894 9 *
mbed_official 579:53297373a894 10 * \page License
mbed_official 579:53297373a894 11 *
mbed_official 579:53297373a894 12 * Redistribution and use in source and binary forms, with or without
mbed_official 579:53297373a894 13 * modification, are permitted provided that the following conditions are met:
mbed_official 579:53297373a894 14 *
mbed_official 579:53297373a894 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 579:53297373a894 16 * this list of conditions and the following disclaimer.
mbed_official 579:53297373a894 17 *
mbed_official 579:53297373a894 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 579:53297373a894 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 579:53297373a894 20 * and/or other materials provided with the distribution.
mbed_official 579:53297373a894 21 *
mbed_official 579:53297373a894 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 579:53297373a894 23 * from this software without specific prior written permission.
mbed_official 579:53297373a894 24 *
mbed_official 579:53297373a894 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 579:53297373a894 26 * Atmel microcontroller product.
mbed_official 579:53297373a894 27 *
mbed_official 579:53297373a894 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 579:53297373a894 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 579:53297373a894 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 579:53297373a894 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 579:53297373a894 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 579:53297373a894 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 579:53297373a894 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 579:53297373a894 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 579:53297373a894 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 579:53297373a894 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 579:53297373a894 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 579:53297373a894 39 *
mbed_official 579:53297373a894 40 * \asf_license_stop
mbed_official 579:53297373a894 41 *
mbed_official 579:53297373a894 42 */
mbed_official 579:53297373a894 43 /**
mbed_official 579:53297373a894 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 579:53297373a894 45 */
mbed_official 579:53297373a894 46
mbed_official 579:53297373a894 47 #ifndef _SAMD21_NVMCTRL_COMPONENT_
mbed_official 579:53297373a894 48 #define _SAMD21_NVMCTRL_COMPONENT_
mbed_official 579:53297373a894 49
mbed_official 579:53297373a894 50 /* ========================================================================== */
mbed_official 579:53297373a894 51 /** SOFTWARE API DEFINITION FOR NVMCTRL */
mbed_official 579:53297373a894 52 /* ========================================================================== */
mbed_official 579:53297373a894 53 /** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
mbed_official 579:53297373a894 54 /*@{*/
mbed_official 579:53297373a894 55
mbed_official 579:53297373a894 56 #define NVMCTRL_U2207
mbed_official 579:53297373a894 57 #define REV_NVMCTRL 0x106
mbed_official 579:53297373a894 58
mbed_official 579:53297373a894 59 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
mbed_official 579:53297373a894 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 61 typedef union {
mbed_official 579:53297373a894 62 struct {
mbed_official 579:53297373a894 63 uint16_t CMD:7; /*!< bit: 0.. 6 Command */
mbed_official 579:53297373a894 64 uint16_t :1; /*!< bit: 7 Reserved */
mbed_official 579:53297373a894 65 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
mbed_official 579:53297373a894 66 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 67 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 68 } NVMCTRL_CTRLA_Type;
mbed_official 579:53297373a894 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 70
mbed_official 579:53297373a894 71 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
mbed_official 579:53297373a894 72 #define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
mbed_official 579:53297373a894 73
mbed_official 579:53297373a894 74 #define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
mbed_official 579:53297373a894 75 #define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 76 #define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))
mbed_official 579:53297373a894 77 #define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
mbed_official 579:53297373a894 78 #define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
mbed_official 579:53297373a894 79 #define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
mbed_official 579:53297373a894 80 #define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
mbed_official 579:53297373a894 81 #define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
mbed_official 579:53297373a894 82 #define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */
mbed_official 579:53297373a894 83 #define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
mbed_official 579:53297373a894 84 #define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
mbed_official 579:53297373a894 85 #define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
mbed_official 579:53297373a894 86 #define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
mbed_official 579:53297373a894 87 #define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
mbed_official 579:53297373a894 88 #define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
mbed_official 579:53297373a894 89 #define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
mbed_official 579:53297373a894 90 #define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 91 #define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 92 #define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 93 #define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 94 #define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 95 #define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 96 #define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 97 #define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 98 #define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 99 #define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 100 #define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 101 #define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 102 #define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
mbed_official 579:53297373a894 103 #define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
mbed_official 579:53297373a894 104 #define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
mbed_official 579:53297373a894 105 #define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))
mbed_official 579:53297373a894 106 #define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */
mbed_official 579:53297373a894 107 #define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
mbed_official 579:53297373a894 108 #define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */
mbed_official 579:53297373a894 109
mbed_official 579:53297373a894 110 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
mbed_official 579:53297373a894 111 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 112 typedef union {
mbed_official 579:53297373a894 113 struct {
mbed_official 579:53297373a894 114 uint32_t :1; /*!< bit: 0 Reserved */
mbed_official 579:53297373a894 115 uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
mbed_official 579:53297373a894 116 uint32_t :2; /*!< bit: 5.. 6 Reserved */
mbed_official 579:53297373a894 117 uint32_t MANW:1; /*!< bit: 7 Manual Write */
mbed_official 579:53297373a894 118 uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
mbed_official 579:53297373a894 119 uint32_t :6; /*!< bit: 10..15 Reserved */
mbed_official 579:53297373a894 120 uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
mbed_official 579:53297373a894 121 uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
mbed_official 579:53297373a894 122 uint32_t :13; /*!< bit: 19..31 Reserved */
mbed_official 579:53297373a894 123 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 124 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 125 } NVMCTRL_CTRLB_Type;
mbed_official 579:53297373a894 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 127
mbed_official 579:53297373a894 128 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
mbed_official 579:53297373a894 129 #define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
mbed_official 579:53297373a894 130
mbed_official 579:53297373a894 131 #define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
mbed_official 579:53297373a894 132 #define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos)
mbed_official 579:53297373a894 133 #define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))
mbed_official 579:53297373a894 134 #define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
mbed_official 579:53297373a894 135 #define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
mbed_official 579:53297373a894 136 #define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
mbed_official 579:53297373a894 137 #define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
mbed_official 579:53297373a894 138 #define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
mbed_official 579:53297373a894 139 #define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
mbed_official 579:53297373a894 140 #define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
mbed_official 579:53297373a894 141 #define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
mbed_official 579:53297373a894 142 #define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
mbed_official 579:53297373a894 143 #define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
mbed_official 579:53297373a894 144 #define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))
mbed_official 579:53297373a894 145 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
mbed_official 579:53297373a894 146 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
mbed_official 579:53297373a894 147 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
mbed_official 579:53297373a894 148 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
mbed_official 579:53297373a894 149 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
mbed_official 579:53297373a894 150 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
mbed_official 579:53297373a894 151 #define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
mbed_official 579:53297373a894 152 #define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
mbed_official 579:53297373a894 153 #define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))
mbed_official 579:53297373a894 154 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
mbed_official 579:53297373a894 155 #define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
mbed_official 579:53297373a894 156 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
mbed_official 579:53297373a894 157 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
mbed_official 579:53297373a894 158 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
mbed_official 579:53297373a894 159 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
mbed_official 579:53297373a894 160 #define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
mbed_official 579:53297373a894 161 #define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
mbed_official 579:53297373a894 162 #define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
mbed_official 579:53297373a894 163
mbed_official 579:53297373a894 164 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
mbed_official 579:53297373a894 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 166 typedef union {
mbed_official 579:53297373a894 167 struct {
mbed_official 579:53297373a894 168 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
mbed_official 579:53297373a894 169 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
mbed_official 579:53297373a894 170 uint32_t :13; /*!< bit: 19..31 Reserved */
mbed_official 579:53297373a894 171 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 172 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 173 } NVMCTRL_PARAM_Type;
mbed_official 579:53297373a894 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 175
mbed_official 579:53297373a894 176 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
mbed_official 579:53297373a894 177 #define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
mbed_official 579:53297373a894 178
mbed_official 579:53297373a894 179 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
mbed_official 579:53297373a894 180 #define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
mbed_official 579:53297373a894 181 #define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))
mbed_official 579:53297373a894 182 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
mbed_official 579:53297373a894 183 #define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 184 #define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))
mbed_official 579:53297373a894 185 #define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */
mbed_official 579:53297373a894 186 #define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */
mbed_official 579:53297373a894 187 #define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */
mbed_official 579:53297373a894 188 #define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */
mbed_official 579:53297373a894 189 #define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */
mbed_official 579:53297373a894 190 #define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */
mbed_official 579:53297373a894 191 #define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */
mbed_official 579:53297373a894 192 #define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */
mbed_official 579:53297373a894 193 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 194 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 195 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 196 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 197 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 198 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 199 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 200 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
mbed_official 579:53297373a894 201 #define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
mbed_official 579:53297373a894 202
mbed_official 579:53297373a894 203 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
mbed_official 579:53297373a894 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 205 typedef union {
mbed_official 579:53297373a894 206 struct {
mbed_official 579:53297373a894 207 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
mbed_official 579:53297373a894 208 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
mbed_official 579:53297373a894 209 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 579:53297373a894 210 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 211 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 212 } NVMCTRL_INTENCLR_Type;
mbed_official 579:53297373a894 213 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 214
mbed_official 579:53297373a894 215 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
mbed_official 579:53297373a894 216 #define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
mbed_official 579:53297373a894 217
mbed_official 579:53297373a894 218 #define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
mbed_official 579:53297373a894 219 #define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
mbed_official 579:53297373a894 220 #define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
mbed_official 579:53297373a894 221 #define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
mbed_official 579:53297373a894 222 #define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */
mbed_official 579:53297373a894 223
mbed_official 579:53297373a894 224 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
mbed_official 579:53297373a894 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 226 typedef union {
mbed_official 579:53297373a894 227 struct {
mbed_official 579:53297373a894 228 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
mbed_official 579:53297373a894 229 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
mbed_official 579:53297373a894 230 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 579:53297373a894 231 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 232 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 233 } NVMCTRL_INTENSET_Type;
mbed_official 579:53297373a894 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 235
mbed_official 579:53297373a894 236 #define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
mbed_official 579:53297373a894 237 #define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
mbed_official 579:53297373a894 238
mbed_official 579:53297373a894 239 #define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
mbed_official 579:53297373a894 240 #define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos)
mbed_official 579:53297373a894 241 #define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
mbed_official 579:53297373a894 242 #define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
mbed_official 579:53297373a894 243 #define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */
mbed_official 579:53297373a894 244
mbed_official 579:53297373a894 245 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
mbed_official 579:53297373a894 246 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 247 typedef union {
mbed_official 579:53297373a894 248 struct {
mbed_official 579:53297373a894 249 uint8_t READY:1; /*!< bit: 0 NVM Ready */
mbed_official 579:53297373a894 250 uint8_t ERROR:1; /*!< bit: 1 Error */
mbed_official 579:53297373a894 251 uint8_t :6; /*!< bit: 2.. 7 Reserved */
mbed_official 579:53297373a894 252 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 253 uint8_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 254 } NVMCTRL_INTFLAG_Type;
mbed_official 579:53297373a894 255 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 256
mbed_official 579:53297373a894 257 #define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 258 #define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 259
mbed_official 579:53297373a894 260 #define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
mbed_official 579:53297373a894 261 #define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
mbed_official 579:53297373a894 262 #define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
mbed_official 579:53297373a894 263 #define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
mbed_official 579:53297373a894 264 #define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */
mbed_official 579:53297373a894 265
mbed_official 579:53297373a894 266 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
mbed_official 579:53297373a894 267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 268 typedef union {
mbed_official 579:53297373a894 269 struct {
mbed_official 579:53297373a894 270 uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
mbed_official 579:53297373a894 271 uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
mbed_official 579:53297373a894 272 uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
mbed_official 579:53297373a894 273 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
mbed_official 579:53297373a894 274 uint16_t NVME:1; /*!< bit: 4 NVM Error */
mbed_official 579:53297373a894 275 uint16_t :3; /*!< bit: 5.. 7 Reserved */
mbed_official 579:53297373a894 276 uint16_t SB:1; /*!< bit: 8 Security Bit Status */
mbed_official 579:53297373a894 277 uint16_t :7; /*!< bit: 9..15 Reserved */
mbed_official 579:53297373a894 278 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 279 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 280 } NVMCTRL_STATUS_Type;
mbed_official 579:53297373a894 281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 282
mbed_official 579:53297373a894 283 #define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
mbed_official 579:53297373a894 284 #define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */
mbed_official 579:53297373a894 285
mbed_official 579:53297373a894 286 #define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
mbed_official 579:53297373a894 287 #define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos)
mbed_official 579:53297373a894 288 #define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
mbed_official 579:53297373a894 289 #define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
mbed_official 579:53297373a894 290 #define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
mbed_official 579:53297373a894 291 #define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
mbed_official 579:53297373a894 292 #define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
mbed_official 579:53297373a894 293 #define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
mbed_official 579:53297373a894 294 #define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
mbed_official 579:53297373a894 295 #define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos)
mbed_official 579:53297373a894 296 #define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
mbed_official 579:53297373a894 297 #define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos)
mbed_official 579:53297373a894 298 #define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */
mbed_official 579:53297373a894 299
mbed_official 579:53297373a894 300 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
mbed_official 579:53297373a894 301 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 302 typedef union {
mbed_official 579:53297373a894 303 struct {
mbed_official 579:53297373a894 304 uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
mbed_official 579:53297373a894 305 uint32_t :10; /*!< bit: 22..31 Reserved */
mbed_official 579:53297373a894 306 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 307 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 308 } NVMCTRL_ADDR_Type;
mbed_official 579:53297373a894 309 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 310
mbed_official 579:53297373a894 311 #define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
mbed_official 579:53297373a894 312 #define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
mbed_official 579:53297373a894 313
mbed_official 579:53297373a894 314 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
mbed_official 579:53297373a894 315 #define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
mbed_official 579:53297373a894 316 #define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))
mbed_official 579:53297373a894 317 #define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
mbed_official 579:53297373a894 318
mbed_official 579:53297373a894 319 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
mbed_official 579:53297373a894 320 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 321 typedef union {
mbed_official 579:53297373a894 322 struct {
mbed_official 579:53297373a894 323 uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
mbed_official 579:53297373a894 324 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 325 uint16_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 326 } NVMCTRL_LOCK_Type;
mbed_official 579:53297373a894 327 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 328
mbed_official 579:53297373a894 329 #define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
mbed_official 579:53297373a894 330
mbed_official 579:53297373a894 331 #define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
mbed_official 579:53297373a894 332 #define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
mbed_official 579:53297373a894 333 #define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))
mbed_official 579:53297373a894 334 #define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */
mbed_official 579:53297373a894 335
mbed_official 579:53297373a894 336 /** \brief NVMCTRL APB hardware registers */
mbed_official 579:53297373a894 337 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 338 typedef struct {
mbed_official 579:53297373a894 339 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
mbed_official 579:53297373a894 340 RoReg8 Reserved1[0x2];
mbed_official 579:53297373a894 341 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
mbed_official 579:53297373a894 342 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
mbed_official 579:53297373a894 343 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
mbed_official 579:53297373a894 344 RoReg8 Reserved2[0x3];
mbed_official 579:53297373a894 345 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
mbed_official 579:53297373a894 346 RoReg8 Reserved3[0x3];
mbed_official 579:53297373a894 347 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
mbed_official 579:53297373a894 348 RoReg8 Reserved4[0x3];
mbed_official 579:53297373a894 349 __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
mbed_official 579:53297373a894 350 RoReg8 Reserved5[0x2];
mbed_official 579:53297373a894 351 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
mbed_official 579:53297373a894 352 __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
mbed_official 579:53297373a894 353 } Nvmctrl;
mbed_official 579:53297373a894 354 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 355 #define SECTION_NVMCTRL_CAL
mbed_official 579:53297373a894 356 #define SECTION_NVMCTRL_LOCKBIT
mbed_official 579:53297373a894 357 #define SECTION_NVMCTRL_OTP1
mbed_official 579:53297373a894 358 #define SECTION_NVMCTRL_OTP2
mbed_official 579:53297373a894 359 #define SECTION_NVMCTRL_OTP4
mbed_official 579:53297373a894 360 #define SECTION_NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 361 #define SECTION_NVMCTRL_USER
mbed_official 579:53297373a894 362
mbed_official 579:53297373a894 363 /*@}*/
mbed_official 579:53297373a894 364
mbed_official 579:53297373a894 365 /* ************************************************************************** */
mbed_official 579:53297373a894 366 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
mbed_official 579:53297373a894 367 /* ************************************************************************** */
mbed_official 579:53297373a894 368 /** \addtogroup fuses_api Peripheral Software API */
mbed_official 579:53297373a894 369 /*@{*/
mbed_official 579:53297373a894 370
mbed_official 579:53297373a894 371
mbed_official 579:53297373a894 372 #define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 373 #define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
mbed_official 579:53297373a894 374 #define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos)
mbed_official 579:53297373a894 375 #define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))
mbed_official 579:53297373a894 376
mbed_official 579:53297373a894 377 #define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
mbed_official 579:53297373a894 378 #define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
mbed_official 579:53297373a894 379 #define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
mbed_official 579:53297373a894 380 #define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))
mbed_official 579:53297373a894 381
mbed_official 579:53297373a894 382 #define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 383 #define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
mbed_official 579:53297373a894 384 #define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
mbed_official 579:53297373a894 385 #define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))
mbed_official 579:53297373a894 386
mbed_official 579:53297373a894 387 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 388 #define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
mbed_official 579:53297373a894 389 #define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
mbed_official 579:53297373a894 390 #define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)))
mbed_official 579:53297373a894 391
mbed_official 579:53297373a894 392 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 393 #define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
mbed_official 579:53297373a894 394 #define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos)
mbed_official 579:53297373a894 395 #define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)))
mbed_official 579:53297373a894 396
mbed_official 579:53297373a894 397 #define FUSES_BOD33_EN_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 398 #define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
mbed_official 579:53297373a894 399 #define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos)
mbed_official 579:53297373a894 400
mbed_official 579:53297373a894 401 #define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
mbed_official 579:53297373a894 402 #define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
mbed_official 579:53297373a894 403 #define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos)
mbed_official 579:53297373a894 404
mbed_official 579:53297373a894 405 #define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 406 #define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
mbed_official 579:53297373a894 407 #define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
mbed_official 579:53297373a894 408 #define FUSES_DFLL48M_COARSE_CAL(value) ((FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos)))
mbed_official 579:53297373a894 409
mbed_official 579:53297373a894 410 #define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
mbed_official 579:53297373a894 411 #define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
mbed_official 579:53297373a894 412 #define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
mbed_official 579:53297373a894 413 #define FUSES_DFLL48M_FINE_CAL(value) ((FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos)))
mbed_official 579:53297373a894 414
mbed_official 579:53297373a894 415 #define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
mbed_official 579:53297373a894 416 #define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
mbed_official 579:53297373a894 417 #define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
mbed_official 579:53297373a894 418 #define FUSES_HOT_ADC_VAL(value) ((FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos)))
mbed_official 579:53297373a894 419
mbed_official 579:53297373a894 420 #define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
mbed_official 579:53297373a894 421 #define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
mbed_official 579:53297373a894 422 #define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
mbed_official 579:53297373a894 423 #define FUSES_HOT_INT1V_VAL(value) ((FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)))
mbed_official 579:53297373a894 424
mbed_official 579:53297373a894 425 #define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 426 #define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
mbed_official 579:53297373a894 427 #define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
mbed_official 579:53297373a894 428 #define FUSES_HOT_TEMP_VAL_DEC(value) ((FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos)))
mbed_official 579:53297373a894 429
mbed_official 579:53297373a894 430 #define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 431 #define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
mbed_official 579:53297373a894 432 #define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
mbed_official 579:53297373a894 433 #define FUSES_HOT_TEMP_VAL_INT(value) ((FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos)))
mbed_official 579:53297373a894 434
mbed_official 579:53297373a894 435 #define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 436 #define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
mbed_official 579:53297373a894 437 #define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos)
mbed_official 579:53297373a894 438 #define FUSES_OSC32K_CAL(value) ((FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos)))
mbed_official 579:53297373a894 439
mbed_official 579:53297373a894 440 #define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
mbed_official 579:53297373a894 441 #define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
mbed_official 579:53297373a894 442 #define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
mbed_official 579:53297373a894 443 #define FUSES_ROOM_ADC_VAL(value) ((FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos)))
mbed_official 579:53297373a894 444
mbed_official 579:53297373a894 445 #define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 446 #define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
mbed_official 579:53297373a894 447 #define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
mbed_official 579:53297373a894 448 #define FUSES_ROOM_INT1V_VAL(value) ((FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos)))
mbed_official 579:53297373a894 449
mbed_official 579:53297373a894 450 #define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 451 #define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
mbed_official 579:53297373a894 452 #define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
mbed_official 579:53297373a894 453 #define FUSES_ROOM_TEMP_VAL_DEC(value) ((FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos)))
mbed_official 579:53297373a894 454
mbed_official 579:53297373a894 455 #define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 456 #define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
mbed_official 579:53297373a894 457 #define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
mbed_official 579:53297373a894 458 #define FUSES_ROOM_TEMP_VAL_INT(value) ((FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos)))
mbed_official 579:53297373a894 459
mbed_official 579:53297373a894 460 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 461 #define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
mbed_official 579:53297373a894 462 #define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
mbed_official 579:53297373a894 463 #define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))
mbed_official 579:53297373a894 464
mbed_official 579:53297373a894 465 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 466 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
mbed_official 579:53297373a894 467 #define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
mbed_official 579:53297373a894 468 #define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))
mbed_official 579:53297373a894 469
mbed_official 579:53297373a894 470 /* Compabible definition for previous driver (begin 1) */
mbed_official 579:53297373a894 471 #define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
mbed_official 579:53297373a894 472 #define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
mbed_official 579:53297373a894 473 #define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
mbed_official 579:53297373a894 474 #define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
mbed_official 579:53297373a894 475
mbed_official 579:53297373a894 476 #define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
mbed_official 579:53297373a894 477 #define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
mbed_official 579:53297373a894 478 #define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
mbed_official 579:53297373a894 479 #define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
mbed_official 579:53297373a894 480
mbed_official 579:53297373a894 481 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 482 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
mbed_official 579:53297373a894 483 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
mbed_official 579:53297373a894 484 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
mbed_official 579:53297373a894 485
mbed_official 579:53297373a894 486 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 487 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
mbed_official 579:53297373a894 488 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
mbed_official 579:53297373a894 489 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
mbed_official 579:53297373a894 490 /* Compabible definition for previous driver (end 1) */
mbed_official 579:53297373a894 491
mbed_official 579:53297373a894 492 #define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
mbed_official 579:53297373a894 493 #define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
mbed_official 579:53297373a894 494 #define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos)
mbed_official 579:53297373a894 495 #define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))
mbed_official 579:53297373a894 496
mbed_official 579:53297373a894 497 #define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
mbed_official 579:53297373a894 498 #define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
mbed_official 579:53297373a894 499 #define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
mbed_official 579:53297373a894 500 #define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))
mbed_official 579:53297373a894 501
mbed_official 579:53297373a894 502 #define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
mbed_official 579:53297373a894 503 #define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
mbed_official 579:53297373a894 504 #define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos)
mbed_official 579:53297373a894 505 #define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))
mbed_official 579:53297373a894 506
mbed_official 579:53297373a894 507 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
mbed_official 579:53297373a894 508 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
mbed_official 579:53297373a894 509 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
mbed_official 579:53297373a894 510 #define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))
mbed_official 579:53297373a894 511
mbed_official 579:53297373a894 512 /* Compabible definition for previous driver (begin 2) */
mbed_official 579:53297373a894 513 #define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
mbed_official 579:53297373a894 514 #define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
mbed_official 579:53297373a894 515 #define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
mbed_official 579:53297373a894 516 #define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
mbed_official 579:53297373a894 517
mbed_official 579:53297373a894 518 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 519 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
mbed_official 579:53297373a894 520 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
mbed_official 579:53297373a894 521 #define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
mbed_official 579:53297373a894 522
mbed_official 579:53297373a894 523 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 524 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
mbed_official 579:53297373a894 525 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
mbed_official 579:53297373a894 526 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
mbed_official 579:53297373a894 527
mbed_official 579:53297373a894 528 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
mbed_official 579:53297373a894 529 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
mbed_official 579:53297373a894 530 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
mbed_official 579:53297373a894 531 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
mbed_official 579:53297373a894 532
mbed_official 579:53297373a894 533 #define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 534 #define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
mbed_official 579:53297373a894 535 #define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
mbed_official 579:53297373a894 536 #define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
mbed_official 579:53297373a894 537
mbed_official 579:53297373a894 538 #define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 539 #define SYSCTRL_FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
mbed_official 579:53297373a894 540 #define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
mbed_official 579:53297373a894 541 #define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
mbed_official 579:53297373a894 542
mbed_official 579:53297373a894 543 #define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 544 #define SYSCTRL_FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
mbed_official 579:53297373a894 545 #define SYSCTRL_FUSES_BOD33_EN_Msk (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
mbed_official 579:53297373a894 546
mbed_official 579:53297373a894 547 #define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
mbed_official 579:53297373a894 548 #define SYSCTRL_FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
mbed_official 579:53297373a894 549 #define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
mbed_official 579:53297373a894 550
mbed_official 579:53297373a894 551 #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 552 #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
mbed_official 579:53297373a894 553 #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
mbed_official 579:53297373a894 554 #define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
mbed_official 579:53297373a894 555
mbed_official 579:53297373a894 556 #define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 557 #define SYSCTRL_FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
mbed_official 579:53297373a894 558 #define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
mbed_official 579:53297373a894 559 #define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
mbed_official 579:53297373a894 560 /* Compabible definition for previous driver (end 2) */
mbed_official 579:53297373a894 561
mbed_official 579:53297373a894 562 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 563 #define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
mbed_official 579:53297373a894 564 #define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos)
mbed_official 579:53297373a894 565 #define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)))
mbed_official 579:53297373a894 566
mbed_official 579:53297373a894 567 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 568 #define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
mbed_official 579:53297373a894 569 #define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos)
mbed_official 579:53297373a894 570 #define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)))
mbed_official 579:53297373a894 571
mbed_official 579:53297373a894 572 #define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
mbed_official 579:53297373a894 573 #define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
mbed_official 579:53297373a894 574 #define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos)
mbed_official 579:53297373a894 575 #define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)))
mbed_official 579:53297373a894 576
mbed_official 579:53297373a894 577 #define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 578 #define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
mbed_official 579:53297373a894 579 #define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos)
mbed_official 579:53297373a894 580
mbed_official 579:53297373a894 581 #define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 582 #define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */
mbed_official 579:53297373a894 583 #define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos)
mbed_official 579:53297373a894 584
mbed_official 579:53297373a894 585 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
mbed_official 579:53297373a894 586 #define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
mbed_official 579:53297373a894 587 #define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos)
mbed_official 579:53297373a894 588 #define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))
mbed_official 579:53297373a894 589
mbed_official 579:53297373a894 590 #define WDT_FUSES_PER_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 591 #define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
mbed_official 579:53297373a894 592 #define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos)
mbed_official 579:53297373a894 593 #define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))
mbed_official 579:53297373a894 594
mbed_official 579:53297373a894 595 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
mbed_official 579:53297373a894 596 #define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
mbed_official 579:53297373a894 597 #define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos)
mbed_official 579:53297373a894 598
mbed_official 579:53297373a894 599 #define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER
mbed_official 579:53297373a894 600 #define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
mbed_official 579:53297373a894 601 #define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos)
mbed_official 579:53297373a894 602
mbed_official 579:53297373a894 603 #define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
mbed_official 579:53297373a894 604 #define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
mbed_official 579:53297373a894 605 #define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos)
mbed_official 579:53297373a894 606 #define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))
mbed_official 579:53297373a894 607
mbed_official 579:53297373a894 608 /*@}*/
mbed_official 579:53297373a894 609
mbed_official 579:53297373a894 610 #endif /* _SAMD21_NVMCTRL_COMPONENT_ */