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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_mtb.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Child:
592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 579:53297373a894 1 /**
mbed_official 579:53297373a894 2 * \file
mbed_official 579:53297373a894 3 *
mbed_official 579:53297373a894 4 * \brief Component description for MTB
mbed_official 579:53297373a894 5 *
mbed_official 579:53297373a894 6 * Copyright (c) 2014 Atmel Corporation. All rights reserved.
mbed_official 579:53297373a894 7 *
mbed_official 579:53297373a894 8 * \asf_license_start
mbed_official 579:53297373a894 9 *
mbed_official 579:53297373a894 10 * \page License
mbed_official 579:53297373a894 11 *
mbed_official 579:53297373a894 12 * Redistribution and use in source and binary forms, with or without
mbed_official 579:53297373a894 13 * modification, are permitted provided that the following conditions are met:
mbed_official 579:53297373a894 14 *
mbed_official 579:53297373a894 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 579:53297373a894 16 * this list of conditions and the following disclaimer.
mbed_official 579:53297373a894 17 *
mbed_official 579:53297373a894 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 579:53297373a894 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 579:53297373a894 20 * and/or other materials provided with the distribution.
mbed_official 579:53297373a894 21 *
mbed_official 579:53297373a894 22 * 3. The name of Atmel may not be used to endorse or promote products derived
mbed_official 579:53297373a894 23 * from this software without specific prior written permission.
mbed_official 579:53297373a894 24 *
mbed_official 579:53297373a894 25 * 4. This software may only be redistributed and used in connection with an
mbed_official 579:53297373a894 26 * Atmel microcontroller product.
mbed_official 579:53297373a894 27 *
mbed_official 579:53297373a894 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
mbed_official 579:53297373a894 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
mbed_official 579:53297373a894 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
mbed_official 579:53297373a894 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
mbed_official 579:53297373a894 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 579:53297373a894 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
mbed_official 579:53297373a894 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
mbed_official 579:53297373a894 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
mbed_official 579:53297373a894 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 579:53297373a894 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 579:53297373a894 38 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 579:53297373a894 39 *
mbed_official 579:53297373a894 40 * \asf_license_stop
mbed_official 579:53297373a894 41 *
mbed_official 579:53297373a894 42 */
mbed_official 579:53297373a894 43 /**
mbed_official 579:53297373a894 44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
mbed_official 579:53297373a894 45 */
mbed_official 579:53297373a894 46
mbed_official 579:53297373a894 47 #ifndef _SAMD21_MTB_COMPONENT_
mbed_official 579:53297373a894 48 #define _SAMD21_MTB_COMPONENT_
mbed_official 579:53297373a894 49
mbed_official 579:53297373a894 50 /* ========================================================================== */
mbed_official 579:53297373a894 51 /** SOFTWARE API DEFINITION FOR MTB */
mbed_official 579:53297373a894 52 /* ========================================================================== */
mbed_official 579:53297373a894 53 /** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
mbed_official 579:53297373a894 54 /*@{*/
mbed_official 579:53297373a894 55
mbed_official 579:53297373a894 56 #define MTB_U2002
mbed_official 579:53297373a894 57 #define REV_MTB 0x100
mbed_official 579:53297373a894 58
mbed_official 579:53297373a894 59 /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
mbed_official 579:53297373a894 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 61 typedef union {
mbed_official 579:53297373a894 62 struct {
mbed_official 579:53297373a894 63 uint32_t :2; /*!< bit: 0.. 1 Reserved */
mbed_official 579:53297373a894 64 uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
mbed_official 579:53297373a894 65 uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
mbed_official 579:53297373a894 66 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 67 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 68 } MTB_POSITION_Type;
mbed_official 579:53297373a894 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 70
mbed_official 579:53297373a894 71 #define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
mbed_official 579:53297373a894 72
mbed_official 579:53297373a894 73 #define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
mbed_official 579:53297373a894 74 #define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos)
mbed_official 579:53297373a894 75 #define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
mbed_official 579:53297373a894 76 #define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
mbed_official 579:53297373a894 77 #define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
mbed_official 579:53297373a894 78 #define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
mbed_official 579:53297373a894 79
mbed_official 579:53297373a894 80 /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
mbed_official 579:53297373a894 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 82 typedef union {
mbed_official 579:53297373a894 83 struct {
mbed_official 579:53297373a894 84 uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
mbed_official 579:53297373a894 85 uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
mbed_official 579:53297373a894 86 uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
mbed_official 579:53297373a894 87 uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
mbed_official 579:53297373a894 88 uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
mbed_official 579:53297373a894 89 uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
mbed_official 579:53297373a894 90 uint32_t :21; /*!< bit: 10..30 Reserved */
mbed_official 579:53297373a894 91 uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
mbed_official 579:53297373a894 92 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 93 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 94 } MTB_MASTER_Type;
mbed_official 579:53297373a894 95 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 96
mbed_official 579:53297373a894 97 #define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
mbed_official 579:53297373a894 98 #define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
mbed_official 579:53297373a894 99
mbed_official 579:53297373a894 100 #define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
mbed_official 579:53297373a894 101 #define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos)
mbed_official 579:53297373a894 102 #define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
mbed_official 579:53297373a894 103 #define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
mbed_official 579:53297373a894 104 #define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos)
mbed_official 579:53297373a894 105 #define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
mbed_official 579:53297373a894 106 #define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos)
mbed_official 579:53297373a894 107 #define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
mbed_official 579:53297373a894 108 #define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
mbed_official 579:53297373a894 109 #define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
mbed_official 579:53297373a894 110 #define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos)
mbed_official 579:53297373a894 111 #define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
mbed_official 579:53297373a894 112 #define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos)
mbed_official 579:53297373a894 113 #define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
mbed_official 579:53297373a894 114 #define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos)
mbed_official 579:53297373a894 115 #define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
mbed_official 579:53297373a894 116
mbed_official 579:53297373a894 117 /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
mbed_official 579:53297373a894 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 119 typedef union {
mbed_official 579:53297373a894 120 struct {
mbed_official 579:53297373a894 121 uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
mbed_official 579:53297373a894 122 uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
mbed_official 579:53297373a894 123 uint32_t :1; /*!< bit: 2 Reserved */
mbed_official 579:53297373a894 124 uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
mbed_official 579:53297373a894 125 } bit; /*!< Structure used for bit access */
mbed_official 579:53297373a894 126 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 127 } MTB_FLOW_Type;
mbed_official 579:53297373a894 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 129
mbed_official 579:53297373a894 130 #define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
mbed_official 579:53297373a894 131 #define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
mbed_official 579:53297373a894 132
mbed_official 579:53297373a894 133 #define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
mbed_official 579:53297373a894 134 #define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
mbed_official 579:53297373a894 135 #define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
mbed_official 579:53297373a894 136 #define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos)
mbed_official 579:53297373a894 137 #define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
mbed_official 579:53297373a894 138 #define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
mbed_official 579:53297373a894 139 #define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
mbed_official 579:53297373a894 140 #define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
mbed_official 579:53297373a894 141
mbed_official 579:53297373a894 142 /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
mbed_official 579:53297373a894 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 144 typedef union {
mbed_official 579:53297373a894 145 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 146 } MTB_BASE_Type;
mbed_official 579:53297373a894 147 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 148
mbed_official 579:53297373a894 149 #define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
mbed_official 579:53297373a894 150 #define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
mbed_official 579:53297373a894 151
mbed_official 579:53297373a894 152 /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
mbed_official 579:53297373a894 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 154 typedef union {
mbed_official 579:53297373a894 155 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 156 } MTB_ITCTRL_Type;
mbed_official 579:53297373a894 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 158
mbed_official 579:53297373a894 159 #define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
mbed_official 579:53297373a894 160 #define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
mbed_official 579:53297373a894 161
mbed_official 579:53297373a894 162 /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
mbed_official 579:53297373a894 163 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 164 typedef union {
mbed_official 579:53297373a894 165 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 166 } MTB_CLAIMSET_Type;
mbed_official 579:53297373a894 167 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 168
mbed_official 579:53297373a894 169 #define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
mbed_official 579:53297373a894 170 #define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
mbed_official 579:53297373a894 171
mbed_official 579:53297373a894 172 /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
mbed_official 579:53297373a894 173 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 174 typedef union {
mbed_official 579:53297373a894 175 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 176 } MTB_CLAIMCLR_Type;
mbed_official 579:53297373a894 177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 178
mbed_official 579:53297373a894 179 #define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
mbed_official 579:53297373a894 180 #define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
mbed_official 579:53297373a894 181
mbed_official 579:53297373a894 182 /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
mbed_official 579:53297373a894 183 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 184 typedef union {
mbed_official 579:53297373a894 185 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 186 } MTB_LOCKACCESS_Type;
mbed_official 579:53297373a894 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 188
mbed_official 579:53297373a894 189 #define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
mbed_official 579:53297373a894 190 #define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
mbed_official 579:53297373a894 191
mbed_official 579:53297373a894 192 /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
mbed_official 579:53297373a894 193 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 194 typedef union {
mbed_official 579:53297373a894 195 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 196 } MTB_LOCKSTATUS_Type;
mbed_official 579:53297373a894 197 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 198
mbed_official 579:53297373a894 199 #define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
mbed_official 579:53297373a894 200 #define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
mbed_official 579:53297373a894 201
mbed_official 579:53297373a894 202 /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
mbed_official 579:53297373a894 203 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 204 typedef union {
mbed_official 579:53297373a894 205 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 206 } MTB_AUTHSTATUS_Type;
mbed_official 579:53297373a894 207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 208
mbed_official 579:53297373a894 209 #define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
mbed_official 579:53297373a894 210 #define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
mbed_official 579:53297373a894 211
mbed_official 579:53297373a894 212 /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
mbed_official 579:53297373a894 213 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 214 typedef union {
mbed_official 579:53297373a894 215 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 216 } MTB_DEVARCH_Type;
mbed_official 579:53297373a894 217 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 218
mbed_official 579:53297373a894 219 #define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
mbed_official 579:53297373a894 220 #define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
mbed_official 579:53297373a894 221
mbed_official 579:53297373a894 222 /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
mbed_official 579:53297373a894 223 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 224 typedef union {
mbed_official 579:53297373a894 225 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 226 } MTB_DEVID_Type;
mbed_official 579:53297373a894 227 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 228
mbed_official 579:53297373a894 229 #define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
mbed_official 579:53297373a894 230 #define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
mbed_official 579:53297373a894 231
mbed_official 579:53297373a894 232 /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
mbed_official 579:53297373a894 233 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 234 typedef union {
mbed_official 579:53297373a894 235 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 236 } MTB_DEVTYPE_Type;
mbed_official 579:53297373a894 237 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 238
mbed_official 579:53297373a894 239 #define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
mbed_official 579:53297373a894 240 #define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
mbed_official 579:53297373a894 241
mbed_official 579:53297373a894 242 /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 244 typedef union {
mbed_official 579:53297373a894 245 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 246 } MTB_PID4_Type;
mbed_official 579:53297373a894 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 248
mbed_official 579:53297373a894 249 #define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
mbed_official 579:53297373a894 250 #define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
mbed_official 579:53297373a894 251
mbed_official 579:53297373a894 252 /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 253 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 254 typedef union {
mbed_official 579:53297373a894 255 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 256 } MTB_PID5_Type;
mbed_official 579:53297373a894 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 258
mbed_official 579:53297373a894 259 #define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
mbed_official 579:53297373a894 260 #define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
mbed_official 579:53297373a894 261
mbed_official 579:53297373a894 262 /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 263 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 264 typedef union {
mbed_official 579:53297373a894 265 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 266 } MTB_PID6_Type;
mbed_official 579:53297373a894 267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 268
mbed_official 579:53297373a894 269 #define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
mbed_official 579:53297373a894 270 #define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
mbed_official 579:53297373a894 271
mbed_official 579:53297373a894 272 /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 274 typedef union {
mbed_official 579:53297373a894 275 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 276 } MTB_PID7_Type;
mbed_official 579:53297373a894 277 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 278
mbed_official 579:53297373a894 279 #define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
mbed_official 579:53297373a894 280 #define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
mbed_official 579:53297373a894 281
mbed_official 579:53297373a894 282 /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 283 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 284 typedef union {
mbed_official 579:53297373a894 285 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 286 } MTB_PID0_Type;
mbed_official 579:53297373a894 287 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 288
mbed_official 579:53297373a894 289 #define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
mbed_official 579:53297373a894 290 #define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
mbed_official 579:53297373a894 291
mbed_official 579:53297373a894 292 /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 294 typedef union {
mbed_official 579:53297373a894 295 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 296 } MTB_PID1_Type;
mbed_official 579:53297373a894 297 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 298
mbed_official 579:53297373a894 299 #define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
mbed_official 579:53297373a894 300 #define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
mbed_official 579:53297373a894 301
mbed_official 579:53297373a894 302 /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 303 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 304 typedef union {
mbed_official 579:53297373a894 305 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 306 } MTB_PID2_Type;
mbed_official 579:53297373a894 307 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 308
mbed_official 579:53297373a894 309 #define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
mbed_official 579:53297373a894 310 #define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
mbed_official 579:53297373a894 311
mbed_official 579:53297373a894 312 /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 314 typedef union {
mbed_official 579:53297373a894 315 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 316 } MTB_PID3_Type;
mbed_official 579:53297373a894 317 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 318
mbed_official 579:53297373a894 319 #define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
mbed_official 579:53297373a894 320 #define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
mbed_official 579:53297373a894 321
mbed_official 579:53297373a894 322 /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 323 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 324 typedef union {
mbed_official 579:53297373a894 325 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 326 } MTB_CID0_Type;
mbed_official 579:53297373a894 327 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 328
mbed_official 579:53297373a894 329 #define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
mbed_official 579:53297373a894 330 #define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
mbed_official 579:53297373a894 331
mbed_official 579:53297373a894 332 /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 333 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 334 typedef union {
mbed_official 579:53297373a894 335 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 336 } MTB_CID1_Type;
mbed_official 579:53297373a894 337 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 338
mbed_official 579:53297373a894 339 #define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
mbed_official 579:53297373a894 340 #define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
mbed_official 579:53297373a894 341
mbed_official 579:53297373a894 342 /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 344 typedef union {
mbed_official 579:53297373a894 345 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 346 } MTB_CID2_Type;
mbed_official 579:53297373a894 347 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 348
mbed_official 579:53297373a894 349 #define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
mbed_official 579:53297373a894 350 #define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
mbed_official 579:53297373a894 351
mbed_official 579:53297373a894 352 /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
mbed_official 579:53297373a894 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 354 typedef union {
mbed_official 579:53297373a894 355 uint32_t reg; /*!< Type used for register access */
mbed_official 579:53297373a894 356 } MTB_CID3_Type;
mbed_official 579:53297373a894 357 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 358
mbed_official 579:53297373a894 359 #define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
mbed_official 579:53297373a894 360 #define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
mbed_official 579:53297373a894 361
mbed_official 579:53297373a894 362 /** \brief MTB hardware registers */
mbed_official 579:53297373a894 363 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
mbed_official 579:53297373a894 364 typedef struct {
mbed_official 579:53297373a894 365 __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
mbed_official 579:53297373a894 366 __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
mbed_official 579:53297373a894 367 __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
mbed_official 579:53297373a894 368 __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
mbed_official 579:53297373a894 369 RoReg8 Reserved1[0xEF0];
mbed_official 579:53297373a894 370 __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
mbed_official 579:53297373a894 371 RoReg8 Reserved2[0x9C];
mbed_official 579:53297373a894 372 __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
mbed_official 579:53297373a894 373 __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
mbed_official 579:53297373a894 374 RoReg8 Reserved3[0x8];
mbed_official 579:53297373a894 375 __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
mbed_official 579:53297373a894 376 __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
mbed_official 579:53297373a894 377 __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
mbed_official 579:53297373a894 378 __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
mbed_official 579:53297373a894 379 RoReg8 Reserved4[0x8];
mbed_official 579:53297373a894 380 __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
mbed_official 579:53297373a894 381 __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
mbed_official 579:53297373a894 382 __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
mbed_official 579:53297373a894 383 __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
mbed_official 579:53297373a894 384 __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
mbed_official 579:53297373a894 385 __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
mbed_official 579:53297373a894 386 __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
mbed_official 579:53297373a894 387 __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
mbed_official 579:53297373a894 388 __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
mbed_official 579:53297373a894 389 __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
mbed_official 579:53297373a894 390 __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
mbed_official 579:53297373a894 391 __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
mbed_official 579:53297373a894 392 __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
mbed_official 579:53297373a894 393 __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
mbed_official 579:53297373a894 394 } Mtb;
mbed_official 579:53297373a894 395 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
mbed_official 579:53297373a894 396
mbed_official 579:53297373a894 397 /*@}*/
mbed_official 579:53297373a894 398
mbed_official 579:53297373a894 399 #endif /* _SAMD21_MTB_COMPONENT_ */