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targets/cmsis/TARGET_Atmel/TARGET_SAM21/utils/cmsis/samd21/include/component/comp_dmac.h@579:53297373a894, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Revision:
- 579:53297373a894
- Child:
- 592:a274ee790e56
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 579:53297373a894 | 1 | /** |
mbed_official | 579:53297373a894 | 2 | * \file |
mbed_official | 579:53297373a894 | 3 | * |
mbed_official | 579:53297373a894 | 4 | * \brief Component description for DMAC |
mbed_official | 579:53297373a894 | 5 | * |
mbed_official | 579:53297373a894 | 6 | * Copyright (c) 2014 Atmel Corporation. All rights reserved. |
mbed_official | 579:53297373a894 | 7 | * |
mbed_official | 579:53297373a894 | 8 | * \asf_license_start |
mbed_official | 579:53297373a894 | 9 | * |
mbed_official | 579:53297373a894 | 10 | * \page License |
mbed_official | 579:53297373a894 | 11 | * |
mbed_official | 579:53297373a894 | 12 | * Redistribution and use in source and binary forms, with or without |
mbed_official | 579:53297373a894 | 13 | * modification, are permitted provided that the following conditions are met: |
mbed_official | 579:53297373a894 | 14 | * |
mbed_official | 579:53297373a894 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 579:53297373a894 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 579:53297373a894 | 17 | * |
mbed_official | 579:53297373a894 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 579:53297373a894 | 19 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 579:53297373a894 | 20 | * and/or other materials provided with the distribution. |
mbed_official | 579:53297373a894 | 21 | * |
mbed_official | 579:53297373a894 | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
mbed_official | 579:53297373a894 | 23 | * from this software without specific prior written permission. |
mbed_official | 579:53297373a894 | 24 | * |
mbed_official | 579:53297373a894 | 25 | * 4. This software may only be redistributed and used in connection with an |
mbed_official | 579:53297373a894 | 26 | * Atmel microcontroller product. |
mbed_official | 579:53297373a894 | 27 | * |
mbed_official | 579:53297373a894 | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 579:53297373a894 | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 579:53297373a894 | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
mbed_official | 579:53297373a894 | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
mbed_official | 579:53297373a894 | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 579:53297373a894 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
mbed_official | 579:53297373a894 | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
mbed_official | 579:53297373a894 | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
mbed_official | 579:53297373a894 | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
mbed_official | 579:53297373a894 | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
mbed_official | 579:53297373a894 | 38 | * POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 579:53297373a894 | 39 | * |
mbed_official | 579:53297373a894 | 40 | * \asf_license_stop |
mbed_official | 579:53297373a894 | 41 | * |
mbed_official | 579:53297373a894 | 42 | */ |
mbed_official | 579:53297373a894 | 43 | /** |
mbed_official | 579:53297373a894 | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
mbed_official | 579:53297373a894 | 45 | */ |
mbed_official | 579:53297373a894 | 46 | |
mbed_official | 579:53297373a894 | 47 | #ifndef _SAMD21_DMAC_COMPONENT_ |
mbed_official | 579:53297373a894 | 48 | #define _SAMD21_DMAC_COMPONENT_ |
mbed_official | 579:53297373a894 | 49 | |
mbed_official | 579:53297373a894 | 50 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 51 | /** SOFTWARE API DEFINITION FOR DMAC */ |
mbed_official | 579:53297373a894 | 52 | /* ========================================================================== */ |
mbed_official | 579:53297373a894 | 53 | /** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ |
mbed_official | 579:53297373a894 | 54 | /*@{*/ |
mbed_official | 579:53297373a894 | 55 | |
mbed_official | 579:53297373a894 | 56 | #define DMAC_U2223 |
mbed_official | 579:53297373a894 | 57 | #define REV_DMAC 0x100 |
mbed_official | 579:53297373a894 | 58 | |
mbed_official | 579:53297373a894 | 59 | /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ |
mbed_official | 579:53297373a894 | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 61 | typedef union { |
mbed_official | 579:53297373a894 | 62 | struct { |
mbed_official | 579:53297373a894 | 63 | uint16_t SWRST:1; /*!< bit: 0 Software Reset */ |
mbed_official | 579:53297373a894 | 64 | uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ |
mbed_official | 579:53297373a894 | 65 | uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ |
mbed_official | 579:53297373a894 | 66 | uint16_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 67 | uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ |
mbed_official | 579:53297373a894 | 68 | uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ |
mbed_official | 579:53297373a894 | 69 | uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ |
mbed_official | 579:53297373a894 | 70 | uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ |
mbed_official | 579:53297373a894 | 71 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
mbed_official | 579:53297373a894 | 72 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 73 | struct { |
mbed_official | 579:53297373a894 | 74 | uint16_t :8; /*!< bit: 0.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 75 | uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ |
mbed_official | 579:53297373a894 | 76 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
mbed_official | 579:53297373a894 | 77 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 78 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 79 | } DMAC_CTRL_Type; |
mbed_official | 579:53297373a894 | 80 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 81 | |
mbed_official | 579:53297373a894 | 82 | #define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ |
mbed_official | 579:53297373a894 | 83 | #define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ |
mbed_official | 579:53297373a894 | 84 | |
mbed_official | 579:53297373a894 | 85 | #define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ |
mbed_official | 579:53297373a894 | 86 | #define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) |
mbed_official | 579:53297373a894 | 87 | #define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ |
mbed_official | 579:53297373a894 | 88 | #define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) |
mbed_official | 579:53297373a894 | 89 | #define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ |
mbed_official | 579:53297373a894 | 90 | #define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) |
mbed_official | 579:53297373a894 | 91 | #define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ |
mbed_official | 579:53297373a894 | 92 | #define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) |
mbed_official | 579:53297373a894 | 93 | #define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ |
mbed_official | 579:53297373a894 | 94 | #define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) |
mbed_official | 579:53297373a894 | 95 | #define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ |
mbed_official | 579:53297373a894 | 96 | #define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) |
mbed_official | 579:53297373a894 | 97 | #define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ |
mbed_official | 579:53297373a894 | 98 | #define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) |
mbed_official | 579:53297373a894 | 99 | #define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ |
mbed_official | 579:53297373a894 | 100 | #define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) |
mbed_official | 579:53297373a894 | 101 | #define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))) |
mbed_official | 579:53297373a894 | 102 | #define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 103 | |
mbed_official | 579:53297373a894 | 104 | /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ |
mbed_official | 579:53297373a894 | 105 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 106 | typedef union { |
mbed_official | 579:53297373a894 | 107 | struct { |
mbed_official | 579:53297373a894 | 108 | uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ |
mbed_official | 579:53297373a894 | 109 | uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ |
mbed_official | 579:53297373a894 | 110 | uint16_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 111 | uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ |
mbed_official | 579:53297373a894 | 112 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
mbed_official | 579:53297373a894 | 113 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 114 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 115 | } DMAC_CRCCTRL_Type; |
mbed_official | 579:53297373a894 | 116 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 117 | |
mbed_official | 579:53297373a894 | 118 | #define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ |
mbed_official | 579:53297373a894 | 119 | #define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ |
mbed_official | 579:53297373a894 | 120 | |
mbed_official | 579:53297373a894 | 121 | #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ |
mbed_official | 579:53297373a894 | 122 | #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 123 | #define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))) |
mbed_official | 579:53297373a894 | 124 | #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ |
mbed_official | 579:53297373a894 | 125 | #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ |
mbed_official | 579:53297373a894 | 126 | #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ |
mbed_official | 579:53297373a894 | 127 | #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 128 | #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 129 | #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 130 | #define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ |
mbed_official | 579:53297373a894 | 131 | #define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) |
mbed_official | 579:53297373a894 | 132 | #define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))) |
mbed_official | 579:53297373a894 | 133 | #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ |
mbed_official | 579:53297373a894 | 134 | #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ |
mbed_official | 579:53297373a894 | 135 | #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) |
mbed_official | 579:53297373a894 | 136 | #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) |
mbed_official | 579:53297373a894 | 137 | #define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ |
mbed_official | 579:53297373a894 | 138 | #define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) |
mbed_official | 579:53297373a894 | 139 | #define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))) |
mbed_official | 579:53297373a894 | 140 | #define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ |
mbed_official | 579:53297373a894 | 141 | #define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ |
mbed_official | 579:53297373a894 | 142 | #define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) |
mbed_official | 579:53297373a894 | 143 | #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) |
mbed_official | 579:53297373a894 | 144 | #define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 145 | |
mbed_official | 579:53297373a894 | 146 | /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ |
mbed_official | 579:53297373a894 | 147 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 148 | typedef union { |
mbed_official | 579:53297373a894 | 149 | struct { |
mbed_official | 579:53297373a894 | 150 | uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ |
mbed_official | 579:53297373a894 | 151 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 152 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 153 | } DMAC_CRCDATAIN_Type; |
mbed_official | 579:53297373a894 | 154 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 155 | |
mbed_official | 579:53297373a894 | 156 | #define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ |
mbed_official | 579:53297373a894 | 157 | #define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ |
mbed_official | 579:53297373a894 | 158 | |
mbed_official | 579:53297373a894 | 159 | #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ |
mbed_official | 579:53297373a894 | 160 | #define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) |
mbed_official | 579:53297373a894 | 161 | #define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))) |
mbed_official | 579:53297373a894 | 162 | #define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ |
mbed_official | 579:53297373a894 | 163 | |
mbed_official | 579:53297373a894 | 164 | /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ |
mbed_official | 579:53297373a894 | 165 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 166 | typedef union { |
mbed_official | 579:53297373a894 | 167 | struct { |
mbed_official | 579:53297373a894 | 168 | uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ |
mbed_official | 579:53297373a894 | 169 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 170 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 171 | } DMAC_CRCCHKSUM_Type; |
mbed_official | 579:53297373a894 | 172 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 173 | |
mbed_official | 579:53297373a894 | 174 | #define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ |
mbed_official | 579:53297373a894 | 175 | #define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ |
mbed_official | 579:53297373a894 | 176 | |
mbed_official | 579:53297373a894 | 177 | #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ |
mbed_official | 579:53297373a894 | 178 | #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) |
mbed_official | 579:53297373a894 | 179 | #define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))) |
mbed_official | 579:53297373a894 | 180 | #define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ |
mbed_official | 579:53297373a894 | 181 | |
mbed_official | 579:53297373a894 | 182 | /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ |
mbed_official | 579:53297373a894 | 183 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 184 | typedef union { |
mbed_official | 579:53297373a894 | 185 | struct { |
mbed_official | 579:53297373a894 | 186 | uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ |
mbed_official | 579:53297373a894 | 187 | uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ |
mbed_official | 579:53297373a894 | 188 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 189 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 190 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 191 | } DMAC_CRCSTATUS_Type; |
mbed_official | 579:53297373a894 | 192 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 193 | |
mbed_official | 579:53297373a894 | 194 | #define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ |
mbed_official | 579:53297373a894 | 195 | #define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ |
mbed_official | 579:53297373a894 | 196 | |
mbed_official | 579:53297373a894 | 197 | #define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ |
mbed_official | 579:53297373a894 | 198 | #define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) |
mbed_official | 579:53297373a894 | 199 | #define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ |
mbed_official | 579:53297373a894 | 200 | #define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) |
mbed_official | 579:53297373a894 | 201 | #define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 202 | |
mbed_official | 579:53297373a894 | 203 | /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ |
mbed_official | 579:53297373a894 | 204 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 205 | typedef union { |
mbed_official | 579:53297373a894 | 206 | struct { |
mbed_official | 579:53297373a894 | 207 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ |
mbed_official | 579:53297373a894 | 208 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 209 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 210 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 211 | } DMAC_DBGCTRL_Type; |
mbed_official | 579:53297373a894 | 212 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 213 | |
mbed_official | 579:53297373a894 | 214 | #define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ |
mbed_official | 579:53297373a894 | 215 | #define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ |
mbed_official | 579:53297373a894 | 216 | |
mbed_official | 579:53297373a894 | 217 | #define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ |
mbed_official | 579:53297373a894 | 218 | #define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) |
mbed_official | 579:53297373a894 | 219 | #define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 220 | |
mbed_official | 579:53297373a894 | 221 | /* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ |
mbed_official | 579:53297373a894 | 222 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 223 | typedef union { |
mbed_official | 579:53297373a894 | 224 | struct { |
mbed_official | 579:53297373a894 | 225 | uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ |
mbed_official | 579:53297373a894 | 226 | uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ |
mbed_official | 579:53297373a894 | 227 | uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ |
mbed_official | 579:53297373a894 | 228 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 229 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 230 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 231 | } DMAC_QOSCTRL_Type; |
mbed_official | 579:53297373a894 | 232 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 233 | |
mbed_official | 579:53297373a894 | 234 | #define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ |
mbed_official | 579:53297373a894 | 235 | #define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ |
mbed_official | 579:53297373a894 | 236 | |
mbed_official | 579:53297373a894 | 237 | #define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ |
mbed_official | 579:53297373a894 | 238 | #define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos) |
mbed_official | 579:53297373a894 | 239 | #define DMAC_QOSCTRL_WRBQOS(value) ((DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))) |
mbed_official | 579:53297373a894 | 240 | #define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ |
mbed_official | 579:53297373a894 | 241 | #define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ |
mbed_official | 579:53297373a894 | 242 | #define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ |
mbed_official | 579:53297373a894 | 243 | #define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ |
mbed_official | 579:53297373a894 | 244 | #define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) |
mbed_official | 579:53297373a894 | 245 | #define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) |
mbed_official | 579:53297373a894 | 246 | #define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) |
mbed_official | 579:53297373a894 | 247 | #define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) |
mbed_official | 579:53297373a894 | 248 | #define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ |
mbed_official | 579:53297373a894 | 249 | #define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos) |
mbed_official | 579:53297373a894 | 250 | #define DMAC_QOSCTRL_FQOS(value) ((DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))) |
mbed_official | 579:53297373a894 | 251 | #define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ |
mbed_official | 579:53297373a894 | 252 | #define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ |
mbed_official | 579:53297373a894 | 253 | #define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ |
mbed_official | 579:53297373a894 | 254 | #define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ |
mbed_official | 579:53297373a894 | 255 | #define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) |
mbed_official | 579:53297373a894 | 256 | #define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) |
mbed_official | 579:53297373a894 | 257 | #define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) |
mbed_official | 579:53297373a894 | 258 | #define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) |
mbed_official | 579:53297373a894 | 259 | #define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ |
mbed_official | 579:53297373a894 | 260 | #define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos) |
mbed_official | 579:53297373a894 | 261 | #define DMAC_QOSCTRL_DQOS(value) ((DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))) |
mbed_official | 579:53297373a894 | 262 | #define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ |
mbed_official | 579:53297373a894 | 263 | #define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ |
mbed_official | 579:53297373a894 | 264 | #define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ |
mbed_official | 579:53297373a894 | 265 | #define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ |
mbed_official | 579:53297373a894 | 266 | #define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) |
mbed_official | 579:53297373a894 | 267 | #define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) |
mbed_official | 579:53297373a894 | 268 | #define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) |
mbed_official | 579:53297373a894 | 269 | #define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) |
mbed_official | 579:53297373a894 | 270 | #define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 271 | |
mbed_official | 579:53297373a894 | 272 | /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ |
mbed_official | 579:53297373a894 | 273 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 274 | typedef union { |
mbed_official | 579:53297373a894 | 275 | struct { |
mbed_official | 579:53297373a894 | 276 | uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ |
mbed_official | 579:53297373a894 | 277 | uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ |
mbed_official | 579:53297373a894 | 278 | uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ |
mbed_official | 579:53297373a894 | 279 | uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ |
mbed_official | 579:53297373a894 | 280 | uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ |
mbed_official | 579:53297373a894 | 281 | uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ |
mbed_official | 579:53297373a894 | 282 | uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ |
mbed_official | 579:53297373a894 | 283 | uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ |
mbed_official | 579:53297373a894 | 284 | uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ |
mbed_official | 579:53297373a894 | 285 | uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ |
mbed_official | 579:53297373a894 | 286 | uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ |
mbed_official | 579:53297373a894 | 287 | uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ |
mbed_official | 579:53297373a894 | 288 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 289 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 290 | struct { |
mbed_official | 579:53297373a894 | 291 | uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ |
mbed_official | 579:53297373a894 | 292 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 293 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 294 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 295 | } DMAC_SWTRIGCTRL_Type; |
mbed_official | 579:53297373a894 | 296 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 297 | |
mbed_official | 579:53297373a894 | 298 | #define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ |
mbed_official | 579:53297373a894 | 299 | #define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ |
mbed_official | 579:53297373a894 | 300 | |
mbed_official | 579:53297373a894 | 301 | #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ |
mbed_official | 579:53297373a894 | 302 | #define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) |
mbed_official | 579:53297373a894 | 303 | #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ |
mbed_official | 579:53297373a894 | 304 | #define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) |
mbed_official | 579:53297373a894 | 305 | #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ |
mbed_official | 579:53297373a894 | 306 | #define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) |
mbed_official | 579:53297373a894 | 307 | #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ |
mbed_official | 579:53297373a894 | 308 | #define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) |
mbed_official | 579:53297373a894 | 309 | #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ |
mbed_official | 579:53297373a894 | 310 | #define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) |
mbed_official | 579:53297373a894 | 311 | #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ |
mbed_official | 579:53297373a894 | 312 | #define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) |
mbed_official | 579:53297373a894 | 313 | #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ |
mbed_official | 579:53297373a894 | 314 | #define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) |
mbed_official | 579:53297373a894 | 315 | #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ |
mbed_official | 579:53297373a894 | 316 | #define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) |
mbed_official | 579:53297373a894 | 317 | #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ |
mbed_official | 579:53297373a894 | 318 | #define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) |
mbed_official | 579:53297373a894 | 319 | #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ |
mbed_official | 579:53297373a894 | 320 | #define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) |
mbed_official | 579:53297373a894 | 321 | #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ |
mbed_official | 579:53297373a894 | 322 | #define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) |
mbed_official | 579:53297373a894 | 323 | #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ |
mbed_official | 579:53297373a894 | 324 | #define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) |
mbed_official | 579:53297373a894 | 325 | #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ |
mbed_official | 579:53297373a894 | 326 | #define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) |
mbed_official | 579:53297373a894 | 327 | #define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))) |
mbed_official | 579:53297373a894 | 328 | #define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 329 | |
mbed_official | 579:53297373a894 | 330 | /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ |
mbed_official | 579:53297373a894 | 331 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 332 | typedef union { |
mbed_official | 579:53297373a894 | 333 | struct { |
mbed_official | 579:53297373a894 | 334 | uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 335 | uint32_t :3; /*!< bit: 4.. 6 Reserved */ |
mbed_official | 579:53297373a894 | 336 | uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 337 | uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 338 | uint32_t :3; /*!< bit: 12..14 Reserved */ |
mbed_official | 579:53297373a894 | 339 | uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 340 | uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 341 | uint32_t :3; /*!< bit: 20..22 Reserved */ |
mbed_official | 579:53297373a894 | 342 | uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 343 | uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 344 | uint32_t :3; /*!< bit: 28..30 Reserved */ |
mbed_official | 579:53297373a894 | 345 | uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 346 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 347 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 348 | } DMAC_PRICTRL0_Type; |
mbed_official | 579:53297373a894 | 349 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 350 | |
mbed_official | 579:53297373a894 | 351 | #define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ |
mbed_official | 579:53297373a894 | 352 | #define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ |
mbed_official | 579:53297373a894 | 353 | |
mbed_official | 579:53297373a894 | 354 | #define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 355 | #define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) |
mbed_official | 579:53297373a894 | 356 | #define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))) |
mbed_official | 579:53297373a894 | 357 | #define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 358 | #define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) |
mbed_official | 579:53297373a894 | 359 | #define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 360 | #define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) |
mbed_official | 579:53297373a894 | 361 | #define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))) |
mbed_official | 579:53297373a894 | 362 | #define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 363 | #define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) |
mbed_official | 579:53297373a894 | 364 | #define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 365 | #define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) |
mbed_official | 579:53297373a894 | 366 | #define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))) |
mbed_official | 579:53297373a894 | 367 | #define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 368 | #define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) |
mbed_official | 579:53297373a894 | 369 | #define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ |
mbed_official | 579:53297373a894 | 370 | #define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) |
mbed_official | 579:53297373a894 | 371 | #define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))) |
mbed_official | 579:53297373a894 | 372 | #define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ |
mbed_official | 579:53297373a894 | 373 | #define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) |
mbed_official | 579:53297373a894 | 374 | #define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ |
mbed_official | 579:53297373a894 | 375 | |
mbed_official | 579:53297373a894 | 376 | /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ |
mbed_official | 579:53297373a894 | 377 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 378 | typedef union { |
mbed_official | 579:53297373a894 | 379 | struct { |
mbed_official | 579:53297373a894 | 380 | uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ |
mbed_official | 579:53297373a894 | 381 | uint16_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 382 | uint16_t TERR:1; /*!< bit: 8 Transfer Error */ |
mbed_official | 579:53297373a894 | 383 | uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ |
mbed_official | 579:53297373a894 | 384 | uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ |
mbed_official | 579:53297373a894 | 385 | uint16_t :2; /*!< bit: 11..12 Reserved */ |
mbed_official | 579:53297373a894 | 386 | uint16_t FERR:1; /*!< bit: 13 Fetch Error */ |
mbed_official | 579:53297373a894 | 387 | uint16_t BUSY:1; /*!< bit: 14 Busy */ |
mbed_official | 579:53297373a894 | 388 | uint16_t PEND:1; /*!< bit: 15 Pending */ |
mbed_official | 579:53297373a894 | 389 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 390 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 391 | } DMAC_INTPEND_Type; |
mbed_official | 579:53297373a894 | 392 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 393 | |
mbed_official | 579:53297373a894 | 394 | #define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ |
mbed_official | 579:53297373a894 | 395 | #define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ |
mbed_official | 579:53297373a894 | 396 | |
mbed_official | 579:53297373a894 | 397 | #define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ |
mbed_official | 579:53297373a894 | 398 | #define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) |
mbed_official | 579:53297373a894 | 399 | #define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))) |
mbed_official | 579:53297373a894 | 400 | #define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ |
mbed_official | 579:53297373a894 | 401 | #define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) |
mbed_official | 579:53297373a894 | 402 | #define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ |
mbed_official | 579:53297373a894 | 403 | #define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) |
mbed_official | 579:53297373a894 | 404 | #define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ |
mbed_official | 579:53297373a894 | 405 | #define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) |
mbed_official | 579:53297373a894 | 406 | #define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ |
mbed_official | 579:53297373a894 | 407 | #define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) |
mbed_official | 579:53297373a894 | 408 | #define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ |
mbed_official | 579:53297373a894 | 409 | #define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) |
mbed_official | 579:53297373a894 | 410 | #define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ |
mbed_official | 579:53297373a894 | 411 | #define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) |
mbed_official | 579:53297373a894 | 412 | #define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ |
mbed_official | 579:53297373a894 | 413 | |
mbed_official | 579:53297373a894 | 414 | /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ |
mbed_official | 579:53297373a894 | 415 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 416 | typedef union { |
mbed_official | 579:53297373a894 | 417 | struct { |
mbed_official | 579:53297373a894 | 418 | uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 419 | uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 420 | uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 421 | uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 422 | uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 423 | uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 424 | uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 425 | uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 426 | uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 427 | uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 428 | uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 429 | uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 430 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 431 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 432 | struct { |
mbed_official | 579:53297373a894 | 433 | uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ |
mbed_official | 579:53297373a894 | 434 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 435 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 436 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 437 | } DMAC_INTSTATUS_Type; |
mbed_official | 579:53297373a894 | 438 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 439 | |
mbed_official | 579:53297373a894 | 440 | #define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ |
mbed_official | 579:53297373a894 | 441 | #define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ |
mbed_official | 579:53297373a894 | 442 | |
mbed_official | 579:53297373a894 | 443 | #define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 444 | #define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) |
mbed_official | 579:53297373a894 | 445 | #define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 446 | #define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) |
mbed_official | 579:53297373a894 | 447 | #define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 448 | #define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) |
mbed_official | 579:53297373a894 | 449 | #define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 450 | #define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) |
mbed_official | 579:53297373a894 | 451 | #define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 452 | #define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) |
mbed_official | 579:53297373a894 | 453 | #define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 454 | #define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) |
mbed_official | 579:53297373a894 | 455 | #define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 456 | #define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) |
mbed_official | 579:53297373a894 | 457 | #define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 458 | #define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) |
mbed_official | 579:53297373a894 | 459 | #define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 460 | #define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) |
mbed_official | 579:53297373a894 | 461 | #define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 462 | #define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) |
mbed_official | 579:53297373a894 | 463 | #define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 464 | #define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) |
mbed_official | 579:53297373a894 | 465 | #define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ |
mbed_official | 579:53297373a894 | 466 | #define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) |
mbed_official | 579:53297373a894 | 467 | #define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ |
mbed_official | 579:53297373a894 | 468 | #define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos) |
mbed_official | 579:53297373a894 | 469 | #define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))) |
mbed_official | 579:53297373a894 | 470 | #define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 471 | |
mbed_official | 579:53297373a894 | 472 | /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ |
mbed_official | 579:53297373a894 | 473 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 474 | typedef union { |
mbed_official | 579:53297373a894 | 475 | struct { |
mbed_official | 579:53297373a894 | 476 | uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ |
mbed_official | 579:53297373a894 | 477 | uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ |
mbed_official | 579:53297373a894 | 478 | uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ |
mbed_official | 579:53297373a894 | 479 | uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ |
mbed_official | 579:53297373a894 | 480 | uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ |
mbed_official | 579:53297373a894 | 481 | uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ |
mbed_official | 579:53297373a894 | 482 | uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ |
mbed_official | 579:53297373a894 | 483 | uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ |
mbed_official | 579:53297373a894 | 484 | uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ |
mbed_official | 579:53297373a894 | 485 | uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ |
mbed_official | 579:53297373a894 | 486 | uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ |
mbed_official | 579:53297373a894 | 487 | uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ |
mbed_official | 579:53297373a894 | 488 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 489 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 490 | struct { |
mbed_official | 579:53297373a894 | 491 | uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ |
mbed_official | 579:53297373a894 | 492 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 493 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 494 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 495 | } DMAC_BUSYCH_Type; |
mbed_official | 579:53297373a894 | 496 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 497 | |
mbed_official | 579:53297373a894 | 498 | #define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ |
mbed_official | 579:53297373a894 | 499 | #define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ |
mbed_official | 579:53297373a894 | 500 | |
mbed_official | 579:53297373a894 | 501 | #define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ |
mbed_official | 579:53297373a894 | 502 | #define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) |
mbed_official | 579:53297373a894 | 503 | #define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ |
mbed_official | 579:53297373a894 | 504 | #define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) |
mbed_official | 579:53297373a894 | 505 | #define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ |
mbed_official | 579:53297373a894 | 506 | #define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) |
mbed_official | 579:53297373a894 | 507 | #define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ |
mbed_official | 579:53297373a894 | 508 | #define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) |
mbed_official | 579:53297373a894 | 509 | #define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ |
mbed_official | 579:53297373a894 | 510 | #define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) |
mbed_official | 579:53297373a894 | 511 | #define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ |
mbed_official | 579:53297373a894 | 512 | #define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) |
mbed_official | 579:53297373a894 | 513 | #define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ |
mbed_official | 579:53297373a894 | 514 | #define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) |
mbed_official | 579:53297373a894 | 515 | #define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ |
mbed_official | 579:53297373a894 | 516 | #define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) |
mbed_official | 579:53297373a894 | 517 | #define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ |
mbed_official | 579:53297373a894 | 518 | #define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) |
mbed_official | 579:53297373a894 | 519 | #define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ |
mbed_official | 579:53297373a894 | 520 | #define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) |
mbed_official | 579:53297373a894 | 521 | #define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ |
mbed_official | 579:53297373a894 | 522 | #define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) |
mbed_official | 579:53297373a894 | 523 | #define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ |
mbed_official | 579:53297373a894 | 524 | #define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) |
mbed_official | 579:53297373a894 | 525 | #define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ |
mbed_official | 579:53297373a894 | 526 | #define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos) |
mbed_official | 579:53297373a894 | 527 | #define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))) |
mbed_official | 579:53297373a894 | 528 | #define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */ |
mbed_official | 579:53297373a894 | 529 | |
mbed_official | 579:53297373a894 | 530 | /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ |
mbed_official | 579:53297373a894 | 531 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 532 | typedef union { |
mbed_official | 579:53297373a894 | 533 | struct { |
mbed_official | 579:53297373a894 | 534 | uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ |
mbed_official | 579:53297373a894 | 535 | uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ |
mbed_official | 579:53297373a894 | 536 | uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ |
mbed_official | 579:53297373a894 | 537 | uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ |
mbed_official | 579:53297373a894 | 538 | uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ |
mbed_official | 579:53297373a894 | 539 | uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ |
mbed_official | 579:53297373a894 | 540 | uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ |
mbed_official | 579:53297373a894 | 541 | uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ |
mbed_official | 579:53297373a894 | 542 | uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ |
mbed_official | 579:53297373a894 | 543 | uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ |
mbed_official | 579:53297373a894 | 544 | uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ |
mbed_official | 579:53297373a894 | 545 | uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ |
mbed_official | 579:53297373a894 | 546 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 547 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 548 | struct { |
mbed_official | 579:53297373a894 | 549 | uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ |
mbed_official | 579:53297373a894 | 550 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
mbed_official | 579:53297373a894 | 551 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 552 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 553 | } DMAC_PENDCH_Type; |
mbed_official | 579:53297373a894 | 554 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 555 | |
mbed_official | 579:53297373a894 | 556 | #define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ |
mbed_official | 579:53297373a894 | 557 | #define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ |
mbed_official | 579:53297373a894 | 558 | |
mbed_official | 579:53297373a894 | 559 | #define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ |
mbed_official | 579:53297373a894 | 560 | #define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) |
mbed_official | 579:53297373a894 | 561 | #define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ |
mbed_official | 579:53297373a894 | 562 | #define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) |
mbed_official | 579:53297373a894 | 563 | #define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ |
mbed_official | 579:53297373a894 | 564 | #define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) |
mbed_official | 579:53297373a894 | 565 | #define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ |
mbed_official | 579:53297373a894 | 566 | #define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) |
mbed_official | 579:53297373a894 | 567 | #define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ |
mbed_official | 579:53297373a894 | 568 | #define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) |
mbed_official | 579:53297373a894 | 569 | #define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ |
mbed_official | 579:53297373a894 | 570 | #define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) |
mbed_official | 579:53297373a894 | 571 | #define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ |
mbed_official | 579:53297373a894 | 572 | #define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) |
mbed_official | 579:53297373a894 | 573 | #define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ |
mbed_official | 579:53297373a894 | 574 | #define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) |
mbed_official | 579:53297373a894 | 575 | #define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ |
mbed_official | 579:53297373a894 | 576 | #define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) |
mbed_official | 579:53297373a894 | 577 | #define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ |
mbed_official | 579:53297373a894 | 578 | #define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) |
mbed_official | 579:53297373a894 | 579 | #define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ |
mbed_official | 579:53297373a894 | 580 | #define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) |
mbed_official | 579:53297373a894 | 581 | #define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ |
mbed_official | 579:53297373a894 | 582 | #define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) |
mbed_official | 579:53297373a894 | 583 | #define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ |
mbed_official | 579:53297373a894 | 584 | #define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos) |
mbed_official | 579:53297373a894 | 585 | #define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))) |
mbed_official | 579:53297373a894 | 586 | #define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */ |
mbed_official | 579:53297373a894 | 587 | |
mbed_official | 579:53297373a894 | 588 | /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ |
mbed_official | 579:53297373a894 | 589 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 590 | typedef union { |
mbed_official | 579:53297373a894 | 591 | struct { |
mbed_official | 579:53297373a894 | 592 | uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 593 | uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 594 | uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 595 | uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 596 | uint32_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 597 | uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ |
mbed_official | 579:53297373a894 | 598 | uint32_t :2; /*!< bit: 13..14 Reserved */ |
mbed_official | 579:53297373a894 | 599 | uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ |
mbed_official | 579:53297373a894 | 600 | uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ |
mbed_official | 579:53297373a894 | 601 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 602 | struct { |
mbed_official | 579:53297373a894 | 603 | uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 604 | uint32_t :28; /*!< bit: 4..31 Reserved */ |
mbed_official | 579:53297373a894 | 605 | } vec; /*!< Structure used for vec access */ |
mbed_official | 579:53297373a894 | 606 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 607 | } DMAC_ACTIVE_Type; |
mbed_official | 579:53297373a894 | 608 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 609 | |
mbed_official | 579:53297373a894 | 610 | #define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ |
mbed_official | 579:53297373a894 | 611 | #define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ |
mbed_official | 579:53297373a894 | 612 | |
mbed_official | 579:53297373a894 | 613 | #define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 614 | #define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) |
mbed_official | 579:53297373a894 | 615 | #define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 616 | #define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) |
mbed_official | 579:53297373a894 | 617 | #define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 618 | #define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) |
mbed_official | 579:53297373a894 | 619 | #define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 620 | #define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) |
mbed_official | 579:53297373a894 | 621 | #define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ |
mbed_official | 579:53297373a894 | 622 | #define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) |
mbed_official | 579:53297373a894 | 623 | #define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))) |
mbed_official | 579:53297373a894 | 624 | #define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ |
mbed_official | 579:53297373a894 | 625 | #define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) |
mbed_official | 579:53297373a894 | 626 | #define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))) |
mbed_official | 579:53297373a894 | 627 | #define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ |
mbed_official | 579:53297373a894 | 628 | #define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) |
mbed_official | 579:53297373a894 | 629 | #define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ |
mbed_official | 579:53297373a894 | 630 | #define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) |
mbed_official | 579:53297373a894 | 631 | #define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))) |
mbed_official | 579:53297373a894 | 632 | #define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ |
mbed_official | 579:53297373a894 | 633 | |
mbed_official | 579:53297373a894 | 634 | /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ |
mbed_official | 579:53297373a894 | 635 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 636 | typedef union { |
mbed_official | 579:53297373a894 | 637 | struct { |
mbed_official | 579:53297373a894 | 638 | uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ |
mbed_official | 579:53297373a894 | 639 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 640 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 641 | } DMAC_BASEADDR_Type; |
mbed_official | 579:53297373a894 | 642 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 643 | |
mbed_official | 579:53297373a894 | 644 | #define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ |
mbed_official | 579:53297373a894 | 645 | #define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ |
mbed_official | 579:53297373a894 | 646 | |
mbed_official | 579:53297373a894 | 647 | #define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ |
mbed_official | 579:53297373a894 | 648 | #define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) |
mbed_official | 579:53297373a894 | 649 | #define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))) |
mbed_official | 579:53297373a894 | 650 | #define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 651 | |
mbed_official | 579:53297373a894 | 652 | /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ |
mbed_official | 579:53297373a894 | 653 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 654 | typedef union { |
mbed_official | 579:53297373a894 | 655 | struct { |
mbed_official | 579:53297373a894 | 656 | uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ |
mbed_official | 579:53297373a894 | 657 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 658 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 659 | } DMAC_WRBADDR_Type; |
mbed_official | 579:53297373a894 | 660 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 661 | |
mbed_official | 579:53297373a894 | 662 | #define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ |
mbed_official | 579:53297373a894 | 663 | #define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ |
mbed_official | 579:53297373a894 | 664 | |
mbed_official | 579:53297373a894 | 665 | #define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ |
mbed_official | 579:53297373a894 | 666 | #define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) |
mbed_official | 579:53297373a894 | 667 | #define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))) |
mbed_official | 579:53297373a894 | 668 | #define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 669 | |
mbed_official | 579:53297373a894 | 670 | /* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ |
mbed_official | 579:53297373a894 | 671 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 672 | typedef union { |
mbed_official | 579:53297373a894 | 673 | struct { |
mbed_official | 579:53297373a894 | 674 | uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ |
mbed_official | 579:53297373a894 | 675 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 676 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 677 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 678 | } DMAC_CHID_Type; |
mbed_official | 579:53297373a894 | 679 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 680 | |
mbed_official | 579:53297373a894 | 681 | #define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ |
mbed_official | 579:53297373a894 | 682 | #define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ |
mbed_official | 579:53297373a894 | 683 | |
mbed_official | 579:53297373a894 | 684 | #define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ |
mbed_official | 579:53297373a894 | 685 | #define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) |
mbed_official | 579:53297373a894 | 686 | #define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))) |
mbed_official | 579:53297373a894 | 687 | #define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ |
mbed_official | 579:53297373a894 | 688 | |
mbed_official | 579:53297373a894 | 689 | /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ |
mbed_official | 579:53297373a894 | 690 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 691 | typedef union { |
mbed_official | 579:53297373a894 | 692 | struct { |
mbed_official | 579:53297373a894 | 693 | uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ |
mbed_official | 579:53297373a894 | 694 | uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ |
mbed_official | 579:53297373a894 | 695 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 696 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 697 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 698 | } DMAC_CHCTRLA_Type; |
mbed_official | 579:53297373a894 | 699 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 700 | |
mbed_official | 579:53297373a894 | 701 | #define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ |
mbed_official | 579:53297373a894 | 702 | #define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ |
mbed_official | 579:53297373a894 | 703 | |
mbed_official | 579:53297373a894 | 704 | #define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ |
mbed_official | 579:53297373a894 | 705 | #define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) |
mbed_official | 579:53297373a894 | 706 | #define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ |
mbed_official | 579:53297373a894 | 707 | #define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) |
mbed_official | 579:53297373a894 | 708 | #define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */ |
mbed_official | 579:53297373a894 | 709 | |
mbed_official | 579:53297373a894 | 710 | /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ |
mbed_official | 579:53297373a894 | 711 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 712 | typedef union { |
mbed_official | 579:53297373a894 | 713 | struct { |
mbed_official | 579:53297373a894 | 714 | uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ |
mbed_official | 579:53297373a894 | 715 | uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ |
mbed_official | 579:53297373a894 | 716 | uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ |
mbed_official | 579:53297373a894 | 717 | uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ |
mbed_official | 579:53297373a894 | 718 | uint32_t :1; /*!< bit: 7 Reserved */ |
mbed_official | 579:53297373a894 | 719 | uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ |
mbed_official | 579:53297373a894 | 720 | uint32_t :8; /*!< bit: 14..21 Reserved */ |
mbed_official | 579:53297373a894 | 721 | uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ |
mbed_official | 579:53297373a894 | 722 | uint32_t CMD:2; /*!< bit: 24..25 Software Command */ |
mbed_official | 579:53297373a894 | 723 | uint32_t :6; /*!< bit: 26..31 Reserved */ |
mbed_official | 579:53297373a894 | 724 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 725 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 726 | } DMAC_CHCTRLB_Type; |
mbed_official | 579:53297373a894 | 727 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 728 | |
mbed_official | 579:53297373a894 | 729 | #define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ |
mbed_official | 579:53297373a894 | 730 | #define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ |
mbed_official | 579:53297373a894 | 731 | |
mbed_official | 579:53297373a894 | 732 | #define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ |
mbed_official | 579:53297373a894 | 733 | #define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 734 | #define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))) |
mbed_official | 579:53297373a894 | 735 | #define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ |
mbed_official | 579:53297373a894 | 736 | #define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ |
mbed_official | 579:53297373a894 | 737 | #define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ |
mbed_official | 579:53297373a894 | 738 | #define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ |
mbed_official | 579:53297373a894 | 739 | #define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ |
mbed_official | 579:53297373a894 | 740 | #define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ |
mbed_official | 579:53297373a894 | 741 | #define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ |
mbed_official | 579:53297373a894 | 742 | #define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 743 | #define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 744 | #define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 745 | #define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 746 | #define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 747 | #define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 748 | #define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) |
mbed_official | 579:53297373a894 | 749 | #define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ |
mbed_official | 579:53297373a894 | 750 | #define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) |
mbed_official | 579:53297373a894 | 751 | #define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ |
mbed_official | 579:53297373a894 | 752 | #define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) |
mbed_official | 579:53297373a894 | 753 | #define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ |
mbed_official | 579:53297373a894 | 754 | #define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) |
mbed_official | 579:53297373a894 | 755 | #define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))) |
mbed_official | 579:53297373a894 | 756 | #define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ |
mbed_official | 579:53297373a894 | 757 | #define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ |
mbed_official | 579:53297373a894 | 758 | #define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ |
mbed_official | 579:53297373a894 | 759 | #define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ |
mbed_official | 579:53297373a894 | 760 | #define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) |
mbed_official | 579:53297373a894 | 761 | #define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) |
mbed_official | 579:53297373a894 | 762 | #define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) |
mbed_official | 579:53297373a894 | 763 | #define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) |
mbed_official | 579:53297373a894 | 764 | #define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ |
mbed_official | 579:53297373a894 | 765 | #define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) |
mbed_official | 579:53297373a894 | 766 | #define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))) |
mbed_official | 579:53297373a894 | 767 | #define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ |
mbed_official | 579:53297373a894 | 768 | #define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) |
mbed_official | 579:53297373a894 | 769 | #define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ |
mbed_official | 579:53297373a894 | 770 | #define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) |
mbed_official | 579:53297373a894 | 771 | #define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))) |
mbed_official | 579:53297373a894 | 772 | #define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ |
mbed_official | 579:53297373a894 | 773 | #define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ |
mbed_official | 579:53297373a894 | 774 | #define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ |
mbed_official | 579:53297373a894 | 775 | #define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) |
mbed_official | 579:53297373a894 | 776 | #define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) |
mbed_official | 579:53297373a894 | 777 | #define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) |
mbed_official | 579:53297373a894 | 778 | #define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ |
mbed_official | 579:53297373a894 | 779 | #define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) |
mbed_official | 579:53297373a894 | 780 | #define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))) |
mbed_official | 579:53297373a894 | 781 | #define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ |
mbed_official | 579:53297373a894 | 782 | #define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ |
mbed_official | 579:53297373a894 | 783 | #define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ |
mbed_official | 579:53297373a894 | 784 | #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) |
mbed_official | 579:53297373a894 | 785 | #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) |
mbed_official | 579:53297373a894 | 786 | #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) |
mbed_official | 579:53297373a894 | 787 | #define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ |
mbed_official | 579:53297373a894 | 788 | |
mbed_official | 579:53297373a894 | 789 | /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ |
mbed_official | 579:53297373a894 | 790 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 791 | typedef union { |
mbed_official | 579:53297373a894 | 792 | struct { |
mbed_official | 579:53297373a894 | 793 | uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 794 | uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 795 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ |
mbed_official | 579:53297373a894 | 796 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 797 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 798 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 799 | } DMAC_CHINTENCLR_Type; |
mbed_official | 579:53297373a894 | 800 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 801 | |
mbed_official | 579:53297373a894 | 802 | #define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 803 | #define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 804 | |
mbed_official | 579:53297373a894 | 805 | #define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 806 | #define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) |
mbed_official | 579:53297373a894 | 807 | #define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 808 | #define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) |
mbed_official | 579:53297373a894 | 809 | #define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ |
mbed_official | 579:53297373a894 | 810 | #define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) |
mbed_official | 579:53297373a894 | 811 | #define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ |
mbed_official | 579:53297373a894 | 812 | |
mbed_official | 579:53297373a894 | 813 | /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ |
mbed_official | 579:53297373a894 | 814 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 815 | typedef union { |
mbed_official | 579:53297373a894 | 816 | struct { |
mbed_official | 579:53297373a894 | 817 | uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 818 | uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 819 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ |
mbed_official | 579:53297373a894 | 820 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 821 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 822 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 823 | } DMAC_CHINTENSET_Type; |
mbed_official | 579:53297373a894 | 824 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 825 | |
mbed_official | 579:53297373a894 | 826 | #define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 827 | #define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 828 | |
mbed_official | 579:53297373a894 | 829 | #define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ |
mbed_official | 579:53297373a894 | 830 | #define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) |
mbed_official | 579:53297373a894 | 831 | #define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ |
mbed_official | 579:53297373a894 | 832 | #define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) |
mbed_official | 579:53297373a894 | 833 | #define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ |
mbed_official | 579:53297373a894 | 834 | #define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) |
mbed_official | 579:53297373a894 | 835 | #define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ |
mbed_official | 579:53297373a894 | 836 | |
mbed_official | 579:53297373a894 | 837 | /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ |
mbed_official | 579:53297373a894 | 838 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 839 | typedef union { |
mbed_official | 579:53297373a894 | 840 | struct { |
mbed_official | 579:53297373a894 | 841 | uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ |
mbed_official | 579:53297373a894 | 842 | uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ |
mbed_official | 579:53297373a894 | 843 | uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ |
mbed_official | 579:53297373a894 | 844 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 845 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 846 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 847 | } DMAC_CHINTFLAG_Type; |
mbed_official | 579:53297373a894 | 848 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 849 | |
mbed_official | 579:53297373a894 | 850 | #define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 851 | #define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 852 | |
mbed_official | 579:53297373a894 | 853 | #define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ |
mbed_official | 579:53297373a894 | 854 | #define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) |
mbed_official | 579:53297373a894 | 855 | #define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ |
mbed_official | 579:53297373a894 | 856 | #define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) |
mbed_official | 579:53297373a894 | 857 | #define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ |
mbed_official | 579:53297373a894 | 858 | #define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) |
mbed_official | 579:53297373a894 | 859 | #define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ |
mbed_official | 579:53297373a894 | 860 | |
mbed_official | 579:53297373a894 | 861 | /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ |
mbed_official | 579:53297373a894 | 862 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 863 | typedef union { |
mbed_official | 579:53297373a894 | 864 | struct { |
mbed_official | 579:53297373a894 | 865 | uint8_t PEND:1; /*!< bit: 0 Channel Pending */ |
mbed_official | 579:53297373a894 | 866 | uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ |
mbed_official | 579:53297373a894 | 867 | uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ |
mbed_official | 579:53297373a894 | 868 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 869 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 870 | uint8_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 871 | } DMAC_CHSTATUS_Type; |
mbed_official | 579:53297373a894 | 872 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 873 | |
mbed_official | 579:53297373a894 | 874 | #define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ |
mbed_official | 579:53297373a894 | 875 | #define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ |
mbed_official | 579:53297373a894 | 876 | |
mbed_official | 579:53297373a894 | 877 | #define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ |
mbed_official | 579:53297373a894 | 878 | #define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) |
mbed_official | 579:53297373a894 | 879 | #define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ |
mbed_official | 579:53297373a894 | 880 | #define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) |
mbed_official | 579:53297373a894 | 881 | #define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ |
mbed_official | 579:53297373a894 | 882 | #define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) |
mbed_official | 579:53297373a894 | 883 | #define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ |
mbed_official | 579:53297373a894 | 884 | |
mbed_official | 579:53297373a894 | 885 | /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ |
mbed_official | 579:53297373a894 | 886 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 887 | typedef union { |
mbed_official | 579:53297373a894 | 888 | struct { |
mbed_official | 579:53297373a894 | 889 | uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ |
mbed_official | 579:53297373a894 | 890 | uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ |
mbed_official | 579:53297373a894 | 891 | uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ |
mbed_official | 579:53297373a894 | 892 | uint16_t :3; /*!< bit: 5.. 7 Reserved */ |
mbed_official | 579:53297373a894 | 893 | uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ |
mbed_official | 579:53297373a894 | 894 | uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ |
mbed_official | 579:53297373a894 | 895 | uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ |
mbed_official | 579:53297373a894 | 896 | uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ |
mbed_official | 579:53297373a894 | 897 | uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ |
mbed_official | 579:53297373a894 | 898 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 899 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 900 | } DMAC_BTCTRL_Type; |
mbed_official | 579:53297373a894 | 901 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 902 | |
mbed_official | 579:53297373a894 | 903 | #define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ |
mbed_official | 579:53297373a894 | 904 | #define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ |
mbed_official | 579:53297373a894 | 905 | |
mbed_official | 579:53297373a894 | 906 | #define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ |
mbed_official | 579:53297373a894 | 907 | #define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) |
mbed_official | 579:53297373a894 | 908 | #define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ |
mbed_official | 579:53297373a894 | 909 | #define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) |
mbed_official | 579:53297373a894 | 910 | #define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))) |
mbed_official | 579:53297373a894 | 911 | #define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ |
mbed_official | 579:53297373a894 | 912 | #define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ |
mbed_official | 579:53297373a894 | 913 | #define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ |
mbed_official | 579:53297373a894 | 914 | #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) |
mbed_official | 579:53297373a894 | 915 | #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) |
mbed_official | 579:53297373a894 | 916 | #define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) |
mbed_official | 579:53297373a894 | 917 | #define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ |
mbed_official | 579:53297373a894 | 918 | #define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) |
mbed_official | 579:53297373a894 | 919 | #define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))) |
mbed_official | 579:53297373a894 | 920 | #define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ |
mbed_official | 579:53297373a894 | 921 | #define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ |
mbed_official | 579:53297373a894 | 922 | #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ |
mbed_official | 579:53297373a894 | 923 | #define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ |
mbed_official | 579:53297373a894 | 924 | #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) |
mbed_official | 579:53297373a894 | 925 | #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) |
mbed_official | 579:53297373a894 | 926 | #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) |
mbed_official | 579:53297373a894 | 927 | #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) |
mbed_official | 579:53297373a894 | 928 | #define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ |
mbed_official | 579:53297373a894 | 929 | #define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 930 | #define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))) |
mbed_official | 579:53297373a894 | 931 | #define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ |
mbed_official | 579:53297373a894 | 932 | #define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ |
mbed_official | 579:53297373a894 | 933 | #define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ |
mbed_official | 579:53297373a894 | 934 | #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 935 | #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 936 | #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) |
mbed_official | 579:53297373a894 | 937 | #define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ |
mbed_official | 579:53297373a894 | 938 | #define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) |
mbed_official | 579:53297373a894 | 939 | #define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ |
mbed_official | 579:53297373a894 | 940 | #define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) |
mbed_official | 579:53297373a894 | 941 | #define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ |
mbed_official | 579:53297373a894 | 942 | #define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) |
mbed_official | 579:53297373a894 | 943 | #define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ |
mbed_official | 579:53297373a894 | 944 | #define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ |
mbed_official | 579:53297373a894 | 945 | #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) |
mbed_official | 579:53297373a894 | 946 | #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) |
mbed_official | 579:53297373a894 | 947 | #define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ |
mbed_official | 579:53297373a894 | 948 | #define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 949 | #define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))) |
mbed_official | 579:53297373a894 | 950 | #define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 1 */ |
mbed_official | 579:53297373a894 | 951 | #define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 2 */ |
mbed_official | 579:53297373a894 | 952 | #define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 4 */ |
mbed_official | 579:53297373a894 | 953 | #define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 8 */ |
mbed_official | 579:53297373a894 | 954 | #define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 16 */ |
mbed_official | 579:53297373a894 | 955 | #define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 32 */ |
mbed_official | 579:53297373a894 | 956 | #define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 64 */ |
mbed_official | 579:53297373a894 | 957 | #define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (BEATSIZE+1) * 128 */ |
mbed_official | 579:53297373a894 | 958 | #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 959 | #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 960 | #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 961 | #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 962 | #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 963 | #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 964 | #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 965 | #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos) |
mbed_official | 579:53297373a894 | 966 | #define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */ |
mbed_official | 579:53297373a894 | 967 | |
mbed_official | 579:53297373a894 | 968 | /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */ |
mbed_official | 579:53297373a894 | 969 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 970 | typedef union { |
mbed_official | 579:53297373a894 | 971 | struct { |
mbed_official | 579:53297373a894 | 972 | uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */ |
mbed_official | 579:53297373a894 | 973 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 974 | uint16_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 975 | } DMAC_BTCNT_Type; |
mbed_official | 579:53297373a894 | 976 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 977 | |
mbed_official | 579:53297373a894 | 978 | #define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */ |
mbed_official | 579:53297373a894 | 979 | |
mbed_official | 579:53297373a894 | 980 | #define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */ |
mbed_official | 579:53297373a894 | 981 | #define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos) |
mbed_official | 579:53297373a894 | 982 | #define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))) |
mbed_official | 579:53297373a894 | 983 | #define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */ |
mbed_official | 579:53297373a894 | 984 | |
mbed_official | 579:53297373a894 | 985 | /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */ |
mbed_official | 579:53297373a894 | 986 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 987 | typedef union { |
mbed_official | 579:53297373a894 | 988 | struct { |
mbed_official | 579:53297373a894 | 989 | uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */ |
mbed_official | 579:53297373a894 | 990 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 991 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 992 | } DMAC_SRCADDR_Type; |
mbed_official | 579:53297373a894 | 993 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 994 | |
mbed_official | 579:53297373a894 | 995 | #define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */ |
mbed_official | 579:53297373a894 | 996 | |
mbed_official | 579:53297373a894 | 997 | #define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */ |
mbed_official | 579:53297373a894 | 998 | #define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos) |
mbed_official | 579:53297373a894 | 999 | #define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))) |
mbed_official | 579:53297373a894 | 1000 | #define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 1001 | |
mbed_official | 579:53297373a894 | 1002 | /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */ |
mbed_official | 579:53297373a894 | 1003 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1004 | typedef union { |
mbed_official | 579:53297373a894 | 1005 | struct { |
mbed_official | 579:53297373a894 | 1006 | uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */ |
mbed_official | 579:53297373a894 | 1007 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1008 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1009 | } DMAC_DSTADDR_Type; |
mbed_official | 579:53297373a894 | 1010 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1011 | |
mbed_official | 579:53297373a894 | 1012 | #define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */ |
mbed_official | 579:53297373a894 | 1013 | |
mbed_official | 579:53297373a894 | 1014 | #define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */ |
mbed_official | 579:53297373a894 | 1015 | #define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos) |
mbed_official | 579:53297373a894 | 1016 | #define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))) |
mbed_official | 579:53297373a894 | 1017 | #define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 1018 | |
mbed_official | 579:53297373a894 | 1019 | /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */ |
mbed_official | 579:53297373a894 | 1020 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1021 | typedef union { |
mbed_official | 579:53297373a894 | 1022 | struct { |
mbed_official | 579:53297373a894 | 1023 | uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */ |
mbed_official | 579:53297373a894 | 1024 | } bit; /*!< Structure used for bit access */ |
mbed_official | 579:53297373a894 | 1025 | uint32_t reg; /*!< Type used for register access */ |
mbed_official | 579:53297373a894 | 1026 | } DMAC_DESCADDR_Type; |
mbed_official | 579:53297373a894 | 1027 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1028 | |
mbed_official | 579:53297373a894 | 1029 | #define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */ |
mbed_official | 579:53297373a894 | 1030 | |
mbed_official | 579:53297373a894 | 1031 | #define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */ |
mbed_official | 579:53297373a894 | 1032 | #define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos) |
mbed_official | 579:53297373a894 | 1033 | #define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))) |
mbed_official | 579:53297373a894 | 1034 | #define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */ |
mbed_official | 579:53297373a894 | 1035 | |
mbed_official | 579:53297373a894 | 1036 | /** \brief DMAC APB hardware registers */ |
mbed_official | 579:53297373a894 | 1037 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1038 | typedef struct { |
mbed_official | 579:53297373a894 | 1039 | __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */ |
mbed_official | 579:53297373a894 | 1040 | __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */ |
mbed_official | 579:53297373a894 | 1041 | __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */ |
mbed_official | 579:53297373a894 | 1042 | __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */ |
mbed_official | 579:53297373a894 | 1043 | __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */ |
mbed_official | 579:53297373a894 | 1044 | __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */ |
mbed_official | 579:53297373a894 | 1045 | __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */ |
mbed_official | 579:53297373a894 | 1046 | RoReg8 Reserved1[0x1]; |
mbed_official | 579:53297373a894 | 1047 | __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */ |
mbed_official | 579:53297373a894 | 1048 | __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */ |
mbed_official | 579:53297373a894 | 1049 | RoReg8 Reserved2[0x8]; |
mbed_official | 579:53297373a894 | 1050 | __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */ |
mbed_official | 579:53297373a894 | 1051 | RoReg8 Reserved3[0x2]; |
mbed_official | 579:53297373a894 | 1052 | __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */ |
mbed_official | 579:53297373a894 | 1053 | __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */ |
mbed_official | 579:53297373a894 | 1054 | __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */ |
mbed_official | 579:53297373a894 | 1055 | __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */ |
mbed_official | 579:53297373a894 | 1056 | __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */ |
mbed_official | 579:53297373a894 | 1057 | __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */ |
mbed_official | 579:53297373a894 | 1058 | RoReg8 Reserved4[0x3]; |
mbed_official | 579:53297373a894 | 1059 | __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */ |
mbed_official | 579:53297373a894 | 1060 | __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */ |
mbed_official | 579:53297373a894 | 1061 | RoReg8 Reserved5[0x3]; |
mbed_official | 579:53297373a894 | 1062 | __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */ |
mbed_official | 579:53297373a894 | 1063 | RoReg8 Reserved6[0x4]; |
mbed_official | 579:53297373a894 | 1064 | __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */ |
mbed_official | 579:53297373a894 | 1065 | __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */ |
mbed_official | 579:53297373a894 | 1066 | __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */ |
mbed_official | 579:53297373a894 | 1067 | __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */ |
mbed_official | 579:53297373a894 | 1068 | } Dmac; |
mbed_official | 579:53297373a894 | 1069 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1070 | |
mbed_official | 579:53297373a894 | 1071 | /** \brief DMAC Descriptor SRAM registers */ |
mbed_official | 579:53297373a894 | 1072 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
mbed_official | 579:53297373a894 | 1073 | typedef struct { |
mbed_official | 579:53297373a894 | 1074 | __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */ |
mbed_official | 579:53297373a894 | 1075 | __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */ |
mbed_official | 579:53297373a894 | 1076 | __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */ |
mbed_official | 579:53297373a894 | 1077 | __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */ |
mbed_official | 579:53297373a894 | 1078 | __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */ |
mbed_official | 579:53297373a894 | 1079 | } DmacDescriptor |
mbed_official | 579:53297373a894 | 1080 | #ifdef __GNUC__ |
mbed_official | 579:53297373a894 | 1081 | __attribute__ ((aligned (8))) |
mbed_official | 579:53297373a894 | 1082 | #endif |
mbed_official | 579:53297373a894 | 1083 | ; |
mbed_official | 579:53297373a894 | 1084 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
mbed_official | 579:53297373a894 | 1085 | #define SECTION_DMAC_DESCRIPTOR |
mbed_official | 579:53297373a894 | 1086 | |
mbed_official | 579:53297373a894 | 1087 | /*@}*/ |
mbed_official | 579:53297373a894 | 1088 | |
mbed_official | 579:53297373a894 | 1089 | #endif /* _SAMD21_DMAC_COMPONENT_ */ |