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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 2 * DISCLAIMER
mbed_official 390:35c2c1cf29cd 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 390:35c2c1cf29cd 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 390:35c2c1cf29cd 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 390:35c2c1cf29cd 6 * all applicable laws, including copyright laws.
mbed_official 390:35c2c1cf29cd 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 390:35c2c1cf29cd 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 390:35c2c1cf29cd 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 390:35c2c1cf29cd 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 390:35c2c1cf29cd 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 390:35c2c1cf29cd 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 390:35c2c1cf29cd 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 390:35c2c1cf29cd 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 390:35c2c1cf29cd 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 390:35c2c1cf29cd 17 * and to discontinue the availability of this software. By using this software,
mbed_official 390:35c2c1cf29cd 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 390:35c2c1cf29cd 19 * following link:
mbed_official 390:35c2c1cf29cd 20 * http://www.renesas.com/disclaimer*
mbed_official 390:35c2c1cf29cd 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 390:35c2c1cf29cd 22 *******************************************************************************/
mbed_official 390:35c2c1cf29cd 23 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 24 * File Name : vdc5_iodefine.h
mbed_official 390:35c2c1cf29cd 25 * $Rev: $
mbed_official 390:35c2c1cf29cd 26 * $Date:: $
mbed_official 390:35c2c1cf29cd 27 * Description : Definition of I/O Register (V1.00a)
mbed_official 390:35c2c1cf29cd 28 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 29 #ifndef VDC5_IODEFINE_H
mbed_official 390:35c2c1cf29cd 30 #define VDC5_IODEFINE_H
mbed_official 390:35c2c1cf29cd 31 /* ->QAC 0639 : Over 127 members (C90) */
mbed_official 390:35c2c1cf29cd 32 /* ->SEC M1.10.1 : Not magic number */
mbed_official 390:35c2c1cf29cd 33
mbed_official 390:35c2c1cf29cd 34 struct st_vdc5
mbed_official 390:35c2c1cf29cd 35 { /* VDC5 */
mbed_official 390:35c2c1cf29cd 36 volatile uint32_t INP_UPDATE; /* INP_UPDATE */
mbed_official 390:35c2c1cf29cd 37 volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */
mbed_official 390:35c2c1cf29cd 38 volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */
mbed_official 390:35c2c1cf29cd 39 volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */
mbed_official 390:35c2c1cf29cd 40 volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */
mbed_official 390:35c2c1cf29cd 41 volatile uint8_t dummy1[108]; /* */
mbed_official 390:35c2c1cf29cd 42 volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */
mbed_official 390:35c2c1cf29cd 43 #define VDC5_IMGCNT_NR_CNT0_COUNT 2
mbed_official 390:35c2c1cf29cd 44 volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */
mbed_official 390:35c2c1cf29cd 45 volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */
mbed_official 390:35c2c1cf29cd 46 volatile uint8_t dummy2[20]; /* */
mbed_official 390:35c2c1cf29cd 47 volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */
mbed_official 390:35c2c1cf29cd 48 volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */
mbed_official 390:35c2c1cf29cd 49 volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */
mbed_official 390:35c2c1cf29cd 50 volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */
mbed_official 390:35c2c1cf29cd 51 volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */
mbed_official 390:35c2c1cf29cd 52 volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */
mbed_official 390:35c2c1cf29cd 53 volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */
mbed_official 390:35c2c1cf29cd 54 volatile uint8_t dummy3[4]; /* */
mbed_official 390:35c2c1cf29cd 55 volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */
mbed_official 390:35c2c1cf29cd 56 volatile uint8_t dummy4[60]; /* */
mbed_official 390:35c2c1cf29cd 57 /* start of struct st_vdc5_from_sc0_scl0_update */
mbed_official 390:35c2c1cf29cd 58 volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 59 #define VDC5_SC0_SCL0_FRC1_COUNT 7
mbed_official 390:35c2c1cf29cd 60 volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
mbed_official 390:35c2c1cf29cd 61 volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
mbed_official 390:35c2c1cf29cd 62 volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
mbed_official 390:35c2c1cf29cd 63 volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
mbed_official 390:35c2c1cf29cd 64 volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
mbed_official 390:35c2c1cf29cd 65 volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
mbed_official 390:35c2c1cf29cd 66 volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
mbed_official 390:35c2c1cf29cd 67 volatile uint8_t dummy5[4]; /* */
mbed_official 390:35c2c1cf29cd 68 volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
mbed_official 390:35c2c1cf29cd 69 volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
mbed_official 390:35c2c1cf29cd 70 volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
mbed_official 390:35c2c1cf29cd 71 #define VDC5_SC0_SCL0_DS1_COUNT 7
mbed_official 390:35c2c1cf29cd 72 volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
mbed_official 390:35c2c1cf29cd 73 volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
mbed_official 390:35c2c1cf29cd 74 volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
mbed_official 390:35c2c1cf29cd 75 volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
mbed_official 390:35c2c1cf29cd 76 volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
mbed_official 390:35c2c1cf29cd 77 volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
mbed_official 390:35c2c1cf29cd 78 volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
mbed_official 390:35c2c1cf29cd 79 #define VDC5_SC0_SCL0_US1_COUNT 8
mbed_official 390:35c2c1cf29cd 80 volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
mbed_official 390:35c2c1cf29cd 81 volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
mbed_official 390:35c2c1cf29cd 82 volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
mbed_official 390:35c2c1cf29cd 83 volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
mbed_official 390:35c2c1cf29cd 84 volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
mbed_official 390:35c2c1cf29cd 85 volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
mbed_official 390:35c2c1cf29cd 86 volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
mbed_official 390:35c2c1cf29cd 87 volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
mbed_official 390:35c2c1cf29cd 88 volatile uint8_t dummy6[4]; /* */
mbed_official 390:35c2c1cf29cd 89 volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
mbed_official 390:35c2c1cf29cd 90 volatile uint8_t dummy7[16]; /* */
mbed_official 390:35c2c1cf29cd 91 volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
mbed_official 390:35c2c1cf29cd 92 volatile uint8_t dummy8[4]; /* */
mbed_official 390:35c2c1cf29cd 93 #define VDC5_SC0_SCL1_WR1_COUNT 4
mbed_official 390:35c2c1cf29cd 94 volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
mbed_official 390:35c2c1cf29cd 95 volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
mbed_official 390:35c2c1cf29cd 96 volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
mbed_official 390:35c2c1cf29cd 97 volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
mbed_official 390:35c2c1cf29cd 98 volatile uint8_t dummy9[4]; /* */
mbed_official 390:35c2c1cf29cd 99 volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
mbed_official 390:35c2c1cf29cd 100 volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
mbed_official 390:35c2c1cf29cd 101 volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
mbed_official 390:35c2c1cf29cd 102 volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
mbed_official 390:35c2c1cf29cd 103 volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
mbed_official 390:35c2c1cf29cd 104 volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
mbed_official 390:35c2c1cf29cd 105 /* end of struct st_vdc5_from_sc0_scl0_update */
mbed_official 390:35c2c1cf29cd 106 volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */
mbed_official 390:35c2c1cf29cd 107 volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */
mbed_official 390:35c2c1cf29cd 108 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
mbed_official 390:35c2c1cf29cd 109 #define VDC5_SC0_SCL1_PBUF0_COUNT 4
mbed_official 390:35c2c1cf29cd 110 volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
mbed_official 390:35c2c1cf29cd 111 volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
mbed_official 390:35c2c1cf29cd 112 volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
mbed_official 390:35c2c1cf29cd 113 volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
mbed_official 390:35c2c1cf29cd 114 volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
mbed_official 390:35c2c1cf29cd 115 volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
mbed_official 390:35c2c1cf29cd 116 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
mbed_official 390:35c2c1cf29cd 117 volatile uint8_t dummy10[44]; /* */
mbed_official 390:35c2c1cf29cd 118 /* start of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 119 volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
mbed_official 390:35c2c1cf29cd 120 volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
mbed_official 390:35c2c1cf29cd 121 #define VDC5_GR0_FLM1_COUNT 6
mbed_official 390:35c2c1cf29cd 122 volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
mbed_official 390:35c2c1cf29cd 123 volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
mbed_official 390:35c2c1cf29cd 124 volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
mbed_official 390:35c2c1cf29cd 125 volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
mbed_official 390:35c2c1cf29cd 126 volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
mbed_official 390:35c2c1cf29cd 127 volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
mbed_official 390:35c2c1cf29cd 128 #define VDC5_GR0_AB1_COUNT 3
mbed_official 390:35c2c1cf29cd 129 volatile uint32_t GR0_AB1; /* GR0_AB1 */
mbed_official 390:35c2c1cf29cd 130 volatile uint32_t GR0_AB2; /* GR0_AB2 */
mbed_official 390:35c2c1cf29cd 131 volatile uint32_t GR0_AB3; /* GR0_AB3 */
mbed_official 390:35c2c1cf29cd 132 /* end of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 133 volatile uint8_t dummy11[12]; /* */
mbed_official 390:35c2c1cf29cd 134 /* start of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 135 volatile uint32_t GR0_AB7; /* GR0_AB7 */
mbed_official 390:35c2c1cf29cd 136 volatile uint32_t GR0_AB8; /* GR0_AB8 */
mbed_official 390:35c2c1cf29cd 137 volatile uint32_t GR0_AB9; /* GR0_AB9 */
mbed_official 390:35c2c1cf29cd 138 volatile uint32_t GR0_AB10; /* GR0_AB10 */
mbed_official 390:35c2c1cf29cd 139 volatile uint32_t GR0_AB11; /* GR0_AB11 */
mbed_official 390:35c2c1cf29cd 140 volatile uint32_t GR0_BASE; /* GR0_BASE */
mbed_official 390:35c2c1cf29cd 141 /* end of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 142 volatile uint32_t GR0_CLUT; /* GR0_CLUT */
mbed_official 390:35c2c1cf29cd 143 volatile uint8_t dummy12[44]; /* */
mbed_official 390:35c2c1cf29cd 144 /* start of struct st_vdc5_from_adj0_update */
mbed_official 390:35c2c1cf29cd 145 volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
mbed_official 390:35c2c1cf29cd 146 volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
mbed_official 390:35c2c1cf29cd 147 #define VDC5_ADJ0_ENH_TIM1_COUNT 3
mbed_official 390:35c2c1cf29cd 148 volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
mbed_official 390:35c2c1cf29cd 149 volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
mbed_official 390:35c2c1cf29cd 150 volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
mbed_official 390:35c2c1cf29cd 151 #define VDC5_ADJ0_ENH_SHP1_COUNT 6
mbed_official 390:35c2c1cf29cd 152 volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
mbed_official 390:35c2c1cf29cd 153 volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
mbed_official 390:35c2c1cf29cd 154 volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
mbed_official 390:35c2c1cf29cd 155 volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
mbed_official 390:35c2c1cf29cd 156 volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
mbed_official 390:35c2c1cf29cd 157 volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
mbed_official 390:35c2c1cf29cd 158 #define VDC5_ADJ0_ENH_LTI1_COUNT 2
mbed_official 390:35c2c1cf29cd 159 volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
mbed_official 390:35c2c1cf29cd 160 volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
mbed_official 390:35c2c1cf29cd 161 volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
mbed_official 390:35c2c1cf29cd 162 volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
mbed_official 390:35c2c1cf29cd 163 volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
mbed_official 390:35c2c1cf29cd 164 volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
mbed_official 390:35c2c1cf29cd 165 volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
mbed_official 390:35c2c1cf29cd 166 volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
mbed_official 390:35c2c1cf29cd 167 volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
mbed_official 390:35c2c1cf29cd 168 /* end of struct st_vdc5_from_adj0_update */
mbed_official 390:35c2c1cf29cd 169 volatile uint8_t dummy13[48]; /* */
mbed_official 390:35c2c1cf29cd 170 /* start of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 171 volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */
mbed_official 390:35c2c1cf29cd 172 volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */
mbed_official 390:35c2c1cf29cd 173 #define VDC5_GR2_FLM1_COUNT 6
mbed_official 390:35c2c1cf29cd 174 volatile uint32_t GR2_FLM1; /* GR2_FLM1 */
mbed_official 390:35c2c1cf29cd 175 volatile uint32_t GR2_FLM2; /* GR2_FLM2 */
mbed_official 390:35c2c1cf29cd 176 volatile uint32_t GR2_FLM3; /* GR2_FLM3 */
mbed_official 390:35c2c1cf29cd 177 volatile uint32_t GR2_FLM4; /* GR2_FLM4 */
mbed_official 390:35c2c1cf29cd 178 volatile uint32_t GR2_FLM5; /* GR2_FLM5 */
mbed_official 390:35c2c1cf29cd 179 volatile uint32_t GR2_FLM6; /* GR2_FLM6 */
mbed_official 390:35c2c1cf29cd 180 #define VDC5_GR2_AB1_COUNT 3
mbed_official 390:35c2c1cf29cd 181 volatile uint32_t GR2_AB1; /* GR2_AB1 */
mbed_official 390:35c2c1cf29cd 182 volatile uint32_t GR2_AB2; /* GR2_AB2 */
mbed_official 390:35c2c1cf29cd 183 volatile uint32_t GR2_AB3; /* GR2_AB3 */
mbed_official 390:35c2c1cf29cd 184 /* end of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 185 volatile uint32_t GR2_AB4; /* GR2_AB4 */
mbed_official 390:35c2c1cf29cd 186 volatile uint32_t GR2_AB5; /* GR2_AB5 */
mbed_official 390:35c2c1cf29cd 187 volatile uint32_t GR2_AB6; /* GR2_AB6 */
mbed_official 390:35c2c1cf29cd 188 /* start of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 189 volatile uint32_t GR2_AB7; /* GR2_AB7 */
mbed_official 390:35c2c1cf29cd 190 volatile uint32_t GR2_AB8; /* GR2_AB8 */
mbed_official 390:35c2c1cf29cd 191 volatile uint32_t GR2_AB9; /* GR2_AB9 */
mbed_official 390:35c2c1cf29cd 192 volatile uint32_t GR2_AB10; /* GR2_AB10 */
mbed_official 390:35c2c1cf29cd 193 volatile uint32_t GR2_AB11; /* GR2_AB11 */
mbed_official 390:35c2c1cf29cd 194 volatile uint32_t GR2_BASE; /* GR2_BASE */
mbed_official 390:35c2c1cf29cd 195 /* end of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 196 volatile uint32_t GR2_CLUT; /* GR2_CLUT */
mbed_official 390:35c2c1cf29cd 197 volatile uint32_t GR2_MON; /* GR2_MON */
mbed_official 390:35c2c1cf29cd 198 volatile uint8_t dummy14[40]; /* */
mbed_official 390:35c2c1cf29cd 199 /* start of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 200 volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */
mbed_official 390:35c2c1cf29cd 201 volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */
mbed_official 390:35c2c1cf29cd 202 #define VDC5_GR3_FLM1_COUNT 6
mbed_official 390:35c2c1cf29cd 203 volatile uint32_t GR3_FLM1; /* GR3_FLM1 */
mbed_official 390:35c2c1cf29cd 204 volatile uint32_t GR3_FLM2; /* GR3_FLM2 */
mbed_official 390:35c2c1cf29cd 205 volatile uint32_t GR3_FLM3; /* GR3_FLM3 */
mbed_official 390:35c2c1cf29cd 206 volatile uint32_t GR3_FLM4; /* GR3_FLM4 */
mbed_official 390:35c2c1cf29cd 207 volatile uint32_t GR3_FLM5; /* GR3_FLM5 */
mbed_official 390:35c2c1cf29cd 208 volatile uint32_t GR3_FLM6; /* GR3_FLM6 */
mbed_official 390:35c2c1cf29cd 209 #define VDC5_GR3_AB1_COUNT 3
mbed_official 390:35c2c1cf29cd 210 volatile uint32_t GR3_AB1; /* GR3_AB1 */
mbed_official 390:35c2c1cf29cd 211 volatile uint32_t GR3_AB2; /* GR3_AB2 */
mbed_official 390:35c2c1cf29cd 212 volatile uint32_t GR3_AB3; /* GR3_AB3 */
mbed_official 390:35c2c1cf29cd 213 /* end of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 214 volatile uint32_t GR3_AB4; /* GR3_AB4 */
mbed_official 390:35c2c1cf29cd 215 volatile uint32_t GR3_AB5; /* GR3_AB5 */
mbed_official 390:35c2c1cf29cd 216 volatile uint32_t GR3_AB6; /* GR3_AB6 */
mbed_official 390:35c2c1cf29cd 217 /* start of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 218 volatile uint32_t GR3_AB7; /* GR3_AB7 */
mbed_official 390:35c2c1cf29cd 219 volatile uint32_t GR3_AB8; /* GR3_AB8 */
mbed_official 390:35c2c1cf29cd 220 volatile uint32_t GR3_AB9; /* GR3_AB9 */
mbed_official 390:35c2c1cf29cd 221 volatile uint32_t GR3_AB10; /* GR3_AB10 */
mbed_official 390:35c2c1cf29cd 222 volatile uint32_t GR3_AB11; /* GR3_AB11 */
mbed_official 390:35c2c1cf29cd 223 volatile uint32_t GR3_BASE; /* GR3_BASE */
mbed_official 390:35c2c1cf29cd 224 /* end of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 225 volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */
mbed_official 390:35c2c1cf29cd 226 volatile uint32_t GR3_MON; /* GR3_MON */
mbed_official 390:35c2c1cf29cd 227 volatile uint8_t dummy15[40]; /* */
mbed_official 390:35c2c1cf29cd 228 volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */
mbed_official 390:35c2c1cf29cd 229 volatile uint32_t GAM_SW; /* GAM_SW */
mbed_official 390:35c2c1cf29cd 230 #define VDC5_GAM_G_LUT1_COUNT 16
mbed_official 390:35c2c1cf29cd 231 volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */
mbed_official 390:35c2c1cf29cd 232 volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */
mbed_official 390:35c2c1cf29cd 233 volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */
mbed_official 390:35c2c1cf29cd 234 volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */
mbed_official 390:35c2c1cf29cd 235 volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */
mbed_official 390:35c2c1cf29cd 236 volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */
mbed_official 390:35c2c1cf29cd 237 volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */
mbed_official 390:35c2c1cf29cd 238 volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */
mbed_official 390:35c2c1cf29cd 239 volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */
mbed_official 390:35c2c1cf29cd 240 volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */
mbed_official 390:35c2c1cf29cd 241 volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */
mbed_official 390:35c2c1cf29cd 242 volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */
mbed_official 390:35c2c1cf29cd 243 volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */
mbed_official 390:35c2c1cf29cd 244 volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */
mbed_official 390:35c2c1cf29cd 245 volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */
mbed_official 390:35c2c1cf29cd 246 volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */
mbed_official 390:35c2c1cf29cd 247 #define VDC5_GAM_G_AREA1_COUNT 8
mbed_official 390:35c2c1cf29cd 248 volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */
mbed_official 390:35c2c1cf29cd 249 volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */
mbed_official 390:35c2c1cf29cd 250 volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */
mbed_official 390:35c2c1cf29cd 251 volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */
mbed_official 390:35c2c1cf29cd 252 volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */
mbed_official 390:35c2c1cf29cd 253 volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */
mbed_official 390:35c2c1cf29cd 254 volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */
mbed_official 390:35c2c1cf29cd 255 volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */
mbed_official 390:35c2c1cf29cd 256 volatile uint8_t dummy16[24]; /* */
mbed_official 390:35c2c1cf29cd 257 volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */
mbed_official 390:35c2c1cf29cd 258 volatile uint8_t dummy17[4]; /* */
mbed_official 390:35c2c1cf29cd 259 #define VDC5_GAM_B_LUT1_COUNT 16
mbed_official 390:35c2c1cf29cd 260 volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */
mbed_official 390:35c2c1cf29cd 261 volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */
mbed_official 390:35c2c1cf29cd 262 volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */
mbed_official 390:35c2c1cf29cd 263 volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */
mbed_official 390:35c2c1cf29cd 264 volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */
mbed_official 390:35c2c1cf29cd 265 volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */
mbed_official 390:35c2c1cf29cd 266 volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */
mbed_official 390:35c2c1cf29cd 267 volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */
mbed_official 390:35c2c1cf29cd 268 volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */
mbed_official 390:35c2c1cf29cd 269 volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */
mbed_official 390:35c2c1cf29cd 270 volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */
mbed_official 390:35c2c1cf29cd 271 volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */
mbed_official 390:35c2c1cf29cd 272 volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */
mbed_official 390:35c2c1cf29cd 273 volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */
mbed_official 390:35c2c1cf29cd 274 volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */
mbed_official 390:35c2c1cf29cd 275 volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */
mbed_official 390:35c2c1cf29cd 276 #define VDC5_GAM_B_AREA1_COUNT 8
mbed_official 390:35c2c1cf29cd 277 volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */
mbed_official 390:35c2c1cf29cd 278 volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */
mbed_official 390:35c2c1cf29cd 279 volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */
mbed_official 390:35c2c1cf29cd 280 volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */
mbed_official 390:35c2c1cf29cd 281 volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */
mbed_official 390:35c2c1cf29cd 282 volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */
mbed_official 390:35c2c1cf29cd 283 volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */
mbed_official 390:35c2c1cf29cd 284 volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */
mbed_official 390:35c2c1cf29cd 285 volatile uint8_t dummy18[24]; /* */
mbed_official 390:35c2c1cf29cd 286 volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */
mbed_official 390:35c2c1cf29cd 287 volatile uint8_t dummy19[4]; /* */
mbed_official 390:35c2c1cf29cd 288 #define VDC5_GAM_R_LUT1_COUNT 16
mbed_official 390:35c2c1cf29cd 289 volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */
mbed_official 390:35c2c1cf29cd 290 volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */
mbed_official 390:35c2c1cf29cd 291 volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */
mbed_official 390:35c2c1cf29cd 292 volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */
mbed_official 390:35c2c1cf29cd 293 volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */
mbed_official 390:35c2c1cf29cd 294 volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */
mbed_official 390:35c2c1cf29cd 295 volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */
mbed_official 390:35c2c1cf29cd 296 volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */
mbed_official 390:35c2c1cf29cd 297 volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */
mbed_official 390:35c2c1cf29cd 298 volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */
mbed_official 390:35c2c1cf29cd 299 volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */
mbed_official 390:35c2c1cf29cd 300 volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */
mbed_official 390:35c2c1cf29cd 301 volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */
mbed_official 390:35c2c1cf29cd 302 volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */
mbed_official 390:35c2c1cf29cd 303 volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */
mbed_official 390:35c2c1cf29cd 304 volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */
mbed_official 390:35c2c1cf29cd 305 #define VDC5_GAM_R_AREA1_COUNT 8
mbed_official 390:35c2c1cf29cd 306 volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */
mbed_official 390:35c2c1cf29cd 307 volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */
mbed_official 390:35c2c1cf29cd 308 volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */
mbed_official 390:35c2c1cf29cd 309 volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */
mbed_official 390:35c2c1cf29cd 310 volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */
mbed_official 390:35c2c1cf29cd 311 volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */
mbed_official 390:35c2c1cf29cd 312 volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */
mbed_official 390:35c2c1cf29cd 313 volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */
mbed_official 390:35c2c1cf29cd 314 volatile uint8_t dummy20[24]; /* */
mbed_official 390:35c2c1cf29cd 315 volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */
mbed_official 390:35c2c1cf29cd 316 volatile uint32_t TCON_TIM; /* TCON_TIM */
mbed_official 390:35c2c1cf29cd 317 #define VDC5_TCON_TIM_STVA1_COUNT 2
mbed_official 390:35c2c1cf29cd 318 volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */
mbed_official 390:35c2c1cf29cd 319 volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */
mbed_official 390:35c2c1cf29cd 320 #define VDC5_TCON_TIM_STVB1_COUNT 2
mbed_official 390:35c2c1cf29cd 321 volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */
mbed_official 390:35c2c1cf29cd 322 volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */
mbed_official 390:35c2c1cf29cd 323 #define VDC5_TCON_TIM_STH1_COUNT 2
mbed_official 390:35c2c1cf29cd 324 volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */
mbed_official 390:35c2c1cf29cd 325 volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */
mbed_official 390:35c2c1cf29cd 326 #define VDC5_TCON_TIM_STB1_COUNT 2
mbed_official 390:35c2c1cf29cd 327 volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */
mbed_official 390:35c2c1cf29cd 328 volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */
mbed_official 390:35c2c1cf29cd 329 #define VDC5_TCON_TIM_CPV1_COUNT 2
mbed_official 390:35c2c1cf29cd 330 volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */
mbed_official 390:35c2c1cf29cd 331 volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */
mbed_official 390:35c2c1cf29cd 332 #define VDC5_TCON_TIM_POLA1_COUNT 2
mbed_official 390:35c2c1cf29cd 333 volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */
mbed_official 390:35c2c1cf29cd 334 volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */
mbed_official 390:35c2c1cf29cd 335 #define VDC5_TCON_TIM_POLB1_COUNT 2
mbed_official 390:35c2c1cf29cd 336 volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */
mbed_official 390:35c2c1cf29cd 337 volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */
mbed_official 390:35c2c1cf29cd 338 volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */
mbed_official 390:35c2c1cf29cd 339 volatile uint8_t dummy21[60]; /* */
mbed_official 390:35c2c1cf29cd 340 volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */
mbed_official 390:35c2c1cf29cd 341 volatile uint32_t OUT_SET; /* OUT_SET */
mbed_official 390:35c2c1cf29cd 342 #define VDC5_OUT_BRIGHT1_COUNT 2
mbed_official 390:35c2c1cf29cd 343 volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */
mbed_official 390:35c2c1cf29cd 344 volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */
mbed_official 390:35c2c1cf29cd 345 volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */
mbed_official 390:35c2c1cf29cd 346 volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */
mbed_official 390:35c2c1cf29cd 347 volatile uint8_t dummy22[12]; /* */
mbed_official 390:35c2c1cf29cd 348 volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */
mbed_official 390:35c2c1cf29cd 349 volatile uint8_t dummy23[88]; /* */
mbed_official 390:35c2c1cf29cd 350 #define VDC5_SYSCNT_INT1_COUNT 6
mbed_official 390:35c2c1cf29cd 351 volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */
mbed_official 390:35c2c1cf29cd 352 volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */
mbed_official 390:35c2c1cf29cd 353 volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */
mbed_official 390:35c2c1cf29cd 354 volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */
mbed_official 390:35c2c1cf29cd 355 volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */
mbed_official 390:35c2c1cf29cd 356 volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */
mbed_official 390:35c2c1cf29cd 357 volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */
mbed_official 390:35c2c1cf29cd 358 volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */
mbed_official 390:35c2c1cf29cd 359 volatile uint8_t dummy24[356]; /* */
mbed_official 390:35c2c1cf29cd 360 /* start of struct st_vdc5_from_sc0_scl0_update */
mbed_official 390:35c2c1cf29cd 361 volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 362 #define VDC5_SC1_SCL0_FRC1_COUNT 7
mbed_official 390:35c2c1cf29cd 363 volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */
mbed_official 390:35c2c1cf29cd 364 volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */
mbed_official 390:35c2c1cf29cd 365 volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */
mbed_official 390:35c2c1cf29cd 366 volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */
mbed_official 390:35c2c1cf29cd 367 volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */
mbed_official 390:35c2c1cf29cd 368 volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */
mbed_official 390:35c2c1cf29cd 369 volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */
mbed_official 390:35c2c1cf29cd 370 volatile uint8_t dummy25[4]; /* */
mbed_official 390:35c2c1cf29cd 371 volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */
mbed_official 390:35c2c1cf29cd 372 volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */
mbed_official 390:35c2c1cf29cd 373 volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */
mbed_official 390:35c2c1cf29cd 374 #define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
mbed_official 390:35c2c1cf29cd 375 volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */
mbed_official 390:35c2c1cf29cd 376 volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */
mbed_official 390:35c2c1cf29cd 377 volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */
mbed_official 390:35c2c1cf29cd 378 volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */
mbed_official 390:35c2c1cf29cd 379 volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */
mbed_official 390:35c2c1cf29cd 380 volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */
mbed_official 390:35c2c1cf29cd 381 volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */
mbed_official 390:35c2c1cf29cd 382 #define VDC5_SC1_SC1_SCL0_US1_COUNT 8
mbed_official 390:35c2c1cf29cd 383 volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */
mbed_official 390:35c2c1cf29cd 384 volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */
mbed_official 390:35c2c1cf29cd 385 volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */
mbed_official 390:35c2c1cf29cd 386 volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */
mbed_official 390:35c2c1cf29cd 387 volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */
mbed_official 390:35c2c1cf29cd 388 volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */
mbed_official 390:35c2c1cf29cd 389 volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */
mbed_official 390:35c2c1cf29cd 390 volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */
mbed_official 390:35c2c1cf29cd 391 volatile uint8_t dummy26[4]; /* */
mbed_official 390:35c2c1cf29cd 392 volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */
mbed_official 390:35c2c1cf29cd 393 volatile uint8_t dummy27[16]; /* */
mbed_official 390:35c2c1cf29cd 394 volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */
mbed_official 390:35c2c1cf29cd 395 volatile uint8_t dummy28[4]; /* */
mbed_official 390:35c2c1cf29cd 396 #define VDC5_SC1_SCL1_WR1_COUNT 4
mbed_official 390:35c2c1cf29cd 397 volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */
mbed_official 390:35c2c1cf29cd 398 volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */
mbed_official 390:35c2c1cf29cd 399 volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */
mbed_official 390:35c2c1cf29cd 400 volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */
mbed_official 390:35c2c1cf29cd 401 volatile uint8_t dummy29[4]; /* */
mbed_official 390:35c2c1cf29cd 402 volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */
mbed_official 390:35c2c1cf29cd 403 volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */
mbed_official 390:35c2c1cf29cd 404 volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */
mbed_official 390:35c2c1cf29cd 405 volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */
mbed_official 390:35c2c1cf29cd 406 volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */
mbed_official 390:35c2c1cf29cd 407 volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */
mbed_official 390:35c2c1cf29cd 408 /* end of struct st_vdc5_from_sc0_scl0_update */
mbed_official 390:35c2c1cf29cd 409 volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */
mbed_official 390:35c2c1cf29cd 410 volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */
mbed_official 390:35c2c1cf29cd 411 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
mbed_official 390:35c2c1cf29cd 412 #define VDC5_SC1_SCL1_PBUF0_COUNT 4
mbed_official 390:35c2c1cf29cd 413 volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */
mbed_official 390:35c2c1cf29cd 414 volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */
mbed_official 390:35c2c1cf29cd 415 volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */
mbed_official 390:35c2c1cf29cd 416 volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */
mbed_official 390:35c2c1cf29cd 417 volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */
mbed_official 390:35c2c1cf29cd 418 volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */
mbed_official 390:35c2c1cf29cd 419 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
mbed_official 390:35c2c1cf29cd 420 volatile uint8_t dummy30[44]; /* */
mbed_official 390:35c2c1cf29cd 421 /* start of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 422 volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */
mbed_official 390:35c2c1cf29cd 423 volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */
mbed_official 390:35c2c1cf29cd 424 #define VDC5_GR1_FLM1_COUNT 6
mbed_official 390:35c2c1cf29cd 425 volatile uint32_t GR1_FLM1; /* GR1_FLM1 */
mbed_official 390:35c2c1cf29cd 426 volatile uint32_t GR1_FLM2; /* GR1_FLM2 */
mbed_official 390:35c2c1cf29cd 427 volatile uint32_t GR1_FLM3; /* GR1_FLM3 */
mbed_official 390:35c2c1cf29cd 428 volatile uint32_t GR1_FLM4; /* GR1_FLM4 */
mbed_official 390:35c2c1cf29cd 429 volatile uint32_t GR1_FLM5; /* GR1_FLM5 */
mbed_official 390:35c2c1cf29cd 430 volatile uint32_t GR1_FLM6; /* GR1_FLM6 */
mbed_official 390:35c2c1cf29cd 431 #define VDC5_GR1_AB1_COUNT 3
mbed_official 390:35c2c1cf29cd 432 volatile uint32_t GR1_AB1; /* GR1_AB1 */
mbed_official 390:35c2c1cf29cd 433 volatile uint32_t GR1_AB2; /* GR1_AB2 */
mbed_official 390:35c2c1cf29cd 434 volatile uint32_t GR1_AB3; /* GR1_AB3 */
mbed_official 390:35c2c1cf29cd 435 /* end of struct st_vdc5_from_gr0_update */
mbed_official 390:35c2c1cf29cd 436 volatile uint32_t GR1_AB4; /* GR1_AB4 */
mbed_official 390:35c2c1cf29cd 437 volatile uint32_t GR1_AB5; /* GR1_AB5 */
mbed_official 390:35c2c1cf29cd 438 volatile uint32_t GR1_AB6; /* GR1_AB6 */
mbed_official 390:35c2c1cf29cd 439 /* start of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 440 volatile uint32_t GR1_AB7; /* GR1_AB7 */
mbed_official 390:35c2c1cf29cd 441 volatile uint32_t GR1_AB8; /* GR1_AB8 */
mbed_official 390:35c2c1cf29cd 442 volatile uint32_t GR1_AB9; /* GR1_AB9 */
mbed_official 390:35c2c1cf29cd 443 volatile uint32_t GR1_AB10; /* GR1_AB10 */
mbed_official 390:35c2c1cf29cd 444 volatile uint32_t GR1_AB11; /* GR1_AB11 */
mbed_official 390:35c2c1cf29cd 445 volatile uint32_t GR1_BASE; /* GR1_BASE */
mbed_official 390:35c2c1cf29cd 446 /* end of struct st_vdc5_from_gr0_ab7 */
mbed_official 390:35c2c1cf29cd 447 volatile uint32_t GR1_CLUT; /* GR1_CLUT */
mbed_official 390:35c2c1cf29cd 448 volatile uint32_t GR1_MON; /* GR1_MON */
mbed_official 390:35c2c1cf29cd 449 volatile uint8_t dummy31[40]; /* */
mbed_official 390:35c2c1cf29cd 450 /* start of struct st_vdc5_from_adj0_update */
mbed_official 390:35c2c1cf29cd 451 volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */
mbed_official 390:35c2c1cf29cd 452 volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */
mbed_official 390:35c2c1cf29cd 453 #define VDC5_ADJ1_ENH_TIM1_COUNT 3
mbed_official 390:35c2c1cf29cd 454 volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */
mbed_official 390:35c2c1cf29cd 455 volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */
mbed_official 390:35c2c1cf29cd 456 volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */
mbed_official 390:35c2c1cf29cd 457 #define VDC5_ADJ1_ENH_SHP1_COUNT 6
mbed_official 390:35c2c1cf29cd 458 volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */
mbed_official 390:35c2c1cf29cd 459 volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */
mbed_official 390:35c2c1cf29cd 460 volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */
mbed_official 390:35c2c1cf29cd 461 volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */
mbed_official 390:35c2c1cf29cd 462 volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */
mbed_official 390:35c2c1cf29cd 463 volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */
mbed_official 390:35c2c1cf29cd 464 #define VDC5_ADJ1_ENH_LTI1_COUNT 2
mbed_official 390:35c2c1cf29cd 465 volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */
mbed_official 390:35c2c1cf29cd 466 volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */
mbed_official 390:35c2c1cf29cd 467 volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */
mbed_official 390:35c2c1cf29cd 468 volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */
mbed_official 390:35c2c1cf29cd 469 volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */
mbed_official 390:35c2c1cf29cd 470 volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */
mbed_official 390:35c2c1cf29cd 471 volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */
mbed_official 390:35c2c1cf29cd 472 volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */
mbed_official 390:35c2c1cf29cd 473 volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */
mbed_official 390:35c2c1cf29cd 474 /* end of struct st_vdc5_from_adj0_update */
mbed_official 390:35c2c1cf29cd 475 volatile uint8_t dummy32[48]; /* */
mbed_official 390:35c2c1cf29cd 476 volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */
mbed_official 390:35c2c1cf29cd 477 volatile uint8_t dummy33[28]; /* */
mbed_official 390:35c2c1cf29cd 478 #define VDC5_GR_VIN_AB1_COUNT 7
mbed_official 390:35c2c1cf29cd 479 volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */
mbed_official 390:35c2c1cf29cd 480 volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */
mbed_official 390:35c2c1cf29cd 481 volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */
mbed_official 390:35c2c1cf29cd 482 volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */
mbed_official 390:35c2c1cf29cd 483 volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */
mbed_official 390:35c2c1cf29cd 484 volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */
mbed_official 390:35c2c1cf29cd 485 volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */
mbed_official 390:35c2c1cf29cd 486 volatile uint8_t dummy34[16]; /* */
mbed_official 390:35c2c1cf29cd 487 volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */
mbed_official 390:35c2c1cf29cd 488 volatile uint8_t dummy35[4]; /* */
mbed_official 390:35c2c1cf29cd 489 volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */
mbed_official 390:35c2c1cf29cd 490 volatile uint8_t dummy36[40]; /* */
mbed_official 390:35c2c1cf29cd 491 volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 492 #define VDC5_OIR_SCL0_FRC1_COUNT 7
mbed_official 390:35c2c1cf29cd 493 volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */
mbed_official 390:35c2c1cf29cd 494 volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */
mbed_official 390:35c2c1cf29cd 495 volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */
mbed_official 390:35c2c1cf29cd 496 volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */
mbed_official 390:35c2c1cf29cd 497 volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */
mbed_official 390:35c2c1cf29cd 498 volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */
mbed_official 390:35c2c1cf29cd 499 volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */
mbed_official 390:35c2c1cf29cd 500 volatile uint8_t dummy37[12]; /* */
mbed_official 390:35c2c1cf29cd 501 #define VDC5_OIR_SCL0_DS1_COUNT 3
mbed_official 390:35c2c1cf29cd 502 volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */
mbed_official 390:35c2c1cf29cd 503 volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */
mbed_official 390:35c2c1cf29cd 504 volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */
mbed_official 390:35c2c1cf29cd 505 volatile uint8_t dummy38[12]; /* */
mbed_official 390:35c2c1cf29cd 506 volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */
mbed_official 390:35c2c1cf29cd 507 volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */
mbed_official 390:35c2c1cf29cd 508 volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */
mbed_official 390:35c2c1cf29cd 509 volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */
mbed_official 390:35c2c1cf29cd 510 volatile uint8_t dummy39[16]; /* */
mbed_official 390:35c2c1cf29cd 511 volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */
mbed_official 390:35c2c1cf29cd 512 volatile uint8_t dummy40[4]; /* */
mbed_official 390:35c2c1cf29cd 513 volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */
mbed_official 390:35c2c1cf29cd 514 volatile uint8_t dummy41[16]; /* */
mbed_official 390:35c2c1cf29cd 515 volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */
mbed_official 390:35c2c1cf29cd 516 volatile uint8_t dummy42[4]; /* */
mbed_official 390:35c2c1cf29cd 517 #define VDC5_OIR_SCL1_WR1_COUNT 4
mbed_official 390:35c2c1cf29cd 518 volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */
mbed_official 390:35c2c1cf29cd 519 volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */
mbed_official 390:35c2c1cf29cd 520 volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */
mbed_official 390:35c2c1cf29cd 521 volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */
mbed_official 390:35c2c1cf29cd 522 volatile uint8_t dummy43[4]; /* */
mbed_official 390:35c2c1cf29cd 523 volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */
mbed_official 390:35c2c1cf29cd 524 volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */
mbed_official 390:35c2c1cf29cd 525 volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */
mbed_official 390:35c2c1cf29cd 526 volatile uint8_t dummy44[88]; /* */
mbed_official 390:35c2c1cf29cd 527 volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */
mbed_official 390:35c2c1cf29cd 528 volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */
mbed_official 390:35c2c1cf29cd 529 #define VDC5_GR_OIR_FLM1_COUNT 6
mbed_official 390:35c2c1cf29cd 530 volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */
mbed_official 390:35c2c1cf29cd 531 volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */
mbed_official 390:35c2c1cf29cd 532 volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */
mbed_official 390:35c2c1cf29cd 533 volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */
mbed_official 390:35c2c1cf29cd 534 volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */
mbed_official 390:35c2c1cf29cd 535 volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */
mbed_official 390:35c2c1cf29cd 536 #define VDC5_GR_OIR_AB1_COUNT 3
mbed_official 390:35c2c1cf29cd 537 volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */
mbed_official 390:35c2c1cf29cd 538 volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */
mbed_official 390:35c2c1cf29cd 539 volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */
mbed_official 390:35c2c1cf29cd 540 volatile uint8_t dummy45[12]; /* */
mbed_official 390:35c2c1cf29cd 541 volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */
mbed_official 390:35c2c1cf29cd 542 volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */
mbed_official 390:35c2c1cf29cd 543 volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */
mbed_official 390:35c2c1cf29cd 544 volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */
mbed_official 390:35c2c1cf29cd 545 volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */
mbed_official 390:35c2c1cf29cd 546 volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */
mbed_official 390:35c2c1cf29cd 547 volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */
mbed_official 390:35c2c1cf29cd 548 volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */
mbed_official 390:35c2c1cf29cd 549 };
mbed_official 390:35c2c1cf29cd 550
mbed_official 390:35c2c1cf29cd 551
mbed_official 390:35c2c1cf29cd 552 struct st_vdc5_from_gr0_update
mbed_official 390:35c2c1cf29cd 553 {
mbed_official 390:35c2c1cf29cd 554 volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */
mbed_official 390:35c2c1cf29cd 555 volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */
mbed_official 390:35c2c1cf29cd 556 volatile uint32_t GR0_FLM1; /* GR0_FLM1 */
mbed_official 390:35c2c1cf29cd 557 volatile uint32_t GR0_FLM2; /* GR0_FLM2 */
mbed_official 390:35c2c1cf29cd 558 volatile uint32_t GR0_FLM3; /* GR0_FLM3 */
mbed_official 390:35c2c1cf29cd 559 volatile uint32_t GR0_FLM4; /* GR0_FLM4 */
mbed_official 390:35c2c1cf29cd 560 volatile uint32_t GR0_FLM5; /* GR0_FLM5 */
mbed_official 390:35c2c1cf29cd 561 volatile uint32_t GR0_FLM6; /* GR0_FLM6 */
mbed_official 390:35c2c1cf29cd 562 volatile uint32_t GR0_AB1; /* GR0_AB1 */
mbed_official 390:35c2c1cf29cd 563 volatile uint32_t GR0_AB2; /* GR0_AB2 */
mbed_official 390:35c2c1cf29cd 564 volatile uint32_t GR0_AB3; /* GR0_AB3 */
mbed_official 390:35c2c1cf29cd 565 };
mbed_official 390:35c2c1cf29cd 566
mbed_official 390:35c2c1cf29cd 567
mbed_official 390:35c2c1cf29cd 568 struct st_vdc5_from_gr0_ab7
mbed_official 390:35c2c1cf29cd 569 {
mbed_official 390:35c2c1cf29cd 570 volatile uint32_t GR0_AB7; /* GR0_AB7 */
mbed_official 390:35c2c1cf29cd 571 volatile uint32_t GR0_AB8; /* GR0_AB8 */
mbed_official 390:35c2c1cf29cd 572 volatile uint32_t GR0_AB9; /* GR0_AB9 */
mbed_official 390:35c2c1cf29cd 573 volatile uint32_t GR0_AB10; /* GR0_AB10 */
mbed_official 390:35c2c1cf29cd 574 volatile uint32_t GR0_AB11; /* GR0_AB11 */
mbed_official 390:35c2c1cf29cd 575 volatile uint32_t GR0_BASE; /* GR0_BASE */
mbed_official 390:35c2c1cf29cd 576 };
mbed_official 390:35c2c1cf29cd 577
mbed_official 390:35c2c1cf29cd 578
mbed_official 390:35c2c1cf29cd 579 struct st_vdc5_from_adj0_update
mbed_official 390:35c2c1cf29cd 580 {
mbed_official 390:35c2c1cf29cd 581 volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */
mbed_official 390:35c2c1cf29cd 582 volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */
mbed_official 390:35c2c1cf29cd 583 volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */
mbed_official 390:35c2c1cf29cd 584 volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */
mbed_official 390:35c2c1cf29cd 585 volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */
mbed_official 390:35c2c1cf29cd 586 volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */
mbed_official 390:35c2c1cf29cd 587 volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */
mbed_official 390:35c2c1cf29cd 588 volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */
mbed_official 390:35c2c1cf29cd 589 volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */
mbed_official 390:35c2c1cf29cd 590 volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */
mbed_official 390:35c2c1cf29cd 591 volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */
mbed_official 390:35c2c1cf29cd 592 volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */
mbed_official 390:35c2c1cf29cd 593 volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */
mbed_official 390:35c2c1cf29cd 594 volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */
mbed_official 390:35c2c1cf29cd 595 volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */
mbed_official 390:35c2c1cf29cd 596 volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */
mbed_official 390:35c2c1cf29cd 597 volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */
mbed_official 390:35c2c1cf29cd 598 volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */
mbed_official 390:35c2c1cf29cd 599 volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */
mbed_official 390:35c2c1cf29cd 600 volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */
mbed_official 390:35c2c1cf29cd 601 };
mbed_official 390:35c2c1cf29cd 602
mbed_official 390:35c2c1cf29cd 603
mbed_official 390:35c2c1cf29cd 604 struct st_vdc5_from_sc0_scl0_update
mbed_official 390:35c2c1cf29cd 605 {
mbed_official 390:35c2c1cf29cd 606 volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 607 volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */
mbed_official 390:35c2c1cf29cd 608 volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */
mbed_official 390:35c2c1cf29cd 609 volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */
mbed_official 390:35c2c1cf29cd 610 volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */
mbed_official 390:35c2c1cf29cd 611 volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */
mbed_official 390:35c2c1cf29cd 612 volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */
mbed_official 390:35c2c1cf29cd 613 volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */
mbed_official 390:35c2c1cf29cd 614 volatile uint8_t dummy5[4]; /* */
mbed_official 390:35c2c1cf29cd 615 volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */
mbed_official 390:35c2c1cf29cd 616 volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */
mbed_official 390:35c2c1cf29cd 617 volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */
mbed_official 390:35c2c1cf29cd 618 volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */
mbed_official 390:35c2c1cf29cd 619 volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */
mbed_official 390:35c2c1cf29cd 620 volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */
mbed_official 390:35c2c1cf29cd 621 volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */
mbed_official 390:35c2c1cf29cd 622 volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */
mbed_official 390:35c2c1cf29cd 623 volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */
mbed_official 390:35c2c1cf29cd 624 volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */
mbed_official 390:35c2c1cf29cd 625 volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */
mbed_official 390:35c2c1cf29cd 626 volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */
mbed_official 390:35c2c1cf29cd 627 volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */
mbed_official 390:35c2c1cf29cd 628 volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */
mbed_official 390:35c2c1cf29cd 629 volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */
mbed_official 390:35c2c1cf29cd 630 volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */
mbed_official 390:35c2c1cf29cd 631 volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */
mbed_official 390:35c2c1cf29cd 632 volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */
mbed_official 390:35c2c1cf29cd 633 volatile uint8_t dummy6[4]; /* */
mbed_official 390:35c2c1cf29cd 634 volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */
mbed_official 390:35c2c1cf29cd 635 volatile uint8_t dummy7[16]; /* */
mbed_official 390:35c2c1cf29cd 636 volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */
mbed_official 390:35c2c1cf29cd 637 volatile uint8_t dummy8[4]; /* */
mbed_official 390:35c2c1cf29cd 638 volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */
mbed_official 390:35c2c1cf29cd 639 volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */
mbed_official 390:35c2c1cf29cd 640 volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */
mbed_official 390:35c2c1cf29cd 641 volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */
mbed_official 390:35c2c1cf29cd 642 volatile uint8_t dummy9[4]; /* */
mbed_official 390:35c2c1cf29cd 643 volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */
mbed_official 390:35c2c1cf29cd 644 volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */
mbed_official 390:35c2c1cf29cd 645 volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */
mbed_official 390:35c2c1cf29cd 646 volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */
mbed_official 390:35c2c1cf29cd 647 volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */
mbed_official 390:35c2c1cf29cd 648 volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */
mbed_official 390:35c2c1cf29cd 649 };
mbed_official 390:35c2c1cf29cd 650
mbed_official 390:35c2c1cf29cd 651
mbed_official 390:35c2c1cf29cd 652 struct st_vdc5_from_sc0_scl1_pbuf0
mbed_official 390:35c2c1cf29cd 653 {
mbed_official 390:35c2c1cf29cd 654 volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */
mbed_official 390:35c2c1cf29cd 655 volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */
mbed_official 390:35c2c1cf29cd 656 volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */
mbed_official 390:35c2c1cf29cd 657 volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */
mbed_official 390:35c2c1cf29cd 658 volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */
mbed_official 390:35c2c1cf29cd 659 volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */
mbed_official 390:35c2c1cf29cd 660 };
mbed_official 390:35c2c1cf29cd 661
mbed_official 390:35c2c1cf29cd 662
mbed_official 390:35c2c1cf29cd 663 #define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */
mbed_official 390:35c2c1cf29cd 664 #define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */
mbed_official 390:35c2c1cf29cd 665
mbed_official 390:35c2c1cf29cd 666
mbed_official 390:35c2c1cf29cd 667 /* Start of channnel array defines of VDC5 */
mbed_official 390:35c2c1cf29cd 668
mbed_official 390:35c2c1cf29cd 669 /* Channnel array defines of VDC5 */
mbed_official 390:35c2c1cf29cd 670 /*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
mbed_official 390:35c2c1cf29cd 671 #define VDC5_COUNT 2
mbed_official 390:35c2c1cf29cd 672 #define VDC5_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 673 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 674 &VDC50, &VDC51 \
mbed_official 390:35c2c1cf29cd 675 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 676
mbed_official 390:35c2c1cf29cd 677
mbed_official 390:35c2c1cf29cd 678
mbed_official 390:35c2c1cf29cd 679 /* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
mbed_official 390:35c2c1cf29cd 680 /*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
mbed_official 390:35c2c1cf29cd 681 #define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2
mbed_official 390:35c2c1cf29cd 682 #define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 683 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 684 { \
mbed_official 390:35c2c1cf29cd 685 &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
mbed_official 390:35c2c1cf29cd 686 &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
mbed_official 390:35c2c1cf29cd 687 } \
mbed_official 390:35c2c1cf29cd 688 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 689 #define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
mbed_official 390:35c2c1cf29cd 690 #define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
mbed_official 390:35c2c1cf29cd 691 #define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
mbed_official 390:35c2c1cf29cd 692 #define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
mbed_official 390:35c2c1cf29cd 693
mbed_official 390:35c2c1cf29cd 694
mbed_official 390:35c2c1cf29cd 695
mbed_official 390:35c2c1cf29cd 696
mbed_official 390:35c2c1cf29cd 697 /* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
mbed_official 390:35c2c1cf29cd 698 /*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
mbed_official 390:35c2c1cf29cd 699 #define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2
mbed_official 390:35c2c1cf29cd 700 #define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 701 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 702 { \
mbed_official 390:35c2c1cf29cd 703 &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
mbed_official 390:35c2c1cf29cd 704 &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
mbed_official 390:35c2c1cf29cd 705 } \
mbed_official 390:35c2c1cf29cd 706 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 707 #define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
mbed_official 390:35c2c1cf29cd 708 #define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
mbed_official 390:35c2c1cf29cd 709 #define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
mbed_official 390:35c2c1cf29cd 710 #define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
mbed_official 390:35c2c1cf29cd 711
mbed_official 390:35c2c1cf29cd 712
mbed_official 390:35c2c1cf29cd 713
mbed_official 390:35c2c1cf29cd 714
mbed_official 390:35c2c1cf29cd 715 /* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
mbed_official 390:35c2c1cf29cd 716 /*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
mbed_official 390:35c2c1cf29cd 717 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2
mbed_official 390:35c2c1cf29cd 718 #define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 719 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 720 { \
mbed_official 390:35c2c1cf29cd 721 &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
mbed_official 390:35c2c1cf29cd 722 &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
mbed_official 390:35c2c1cf29cd 723 } \
mbed_official 390:35c2c1cf29cd 724 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 725 #define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
mbed_official 390:35c2c1cf29cd 726 #define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
mbed_official 390:35c2c1cf29cd 727 #define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
mbed_official 390:35c2c1cf29cd 728 #define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
mbed_official 390:35c2c1cf29cd 729
mbed_official 390:35c2c1cf29cd 730
mbed_official 390:35c2c1cf29cd 731
mbed_official 390:35c2c1cf29cd 732
mbed_official 390:35c2c1cf29cd 733 /* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
mbed_official 390:35c2c1cf29cd 734 /*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
mbed_official 390:35c2c1cf29cd 735 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2
mbed_official 390:35c2c1cf29cd 736 #define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 737 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 738 { \
mbed_official 390:35c2c1cf29cd 739 &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
mbed_official 390:35c2c1cf29cd 740 &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
mbed_official 390:35c2c1cf29cd 741 } \
mbed_official 390:35c2c1cf29cd 742 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 743 #define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 744 #define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 745 #define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 746 #define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
mbed_official 390:35c2c1cf29cd 747
mbed_official 390:35c2c1cf29cd 748
mbed_official 390:35c2c1cf29cd 749
mbed_official 390:35c2c1cf29cd 750
mbed_official 390:35c2c1cf29cd 751 /* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
mbed_official 390:35c2c1cf29cd 752 /*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
mbed_official 390:35c2c1cf29cd 753 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2
mbed_official 390:35c2c1cf29cd 754 #define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 755 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 756 { \
mbed_official 390:35c2c1cf29cd 757 &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
mbed_official 390:35c2c1cf29cd 758 &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
mbed_official 390:35c2c1cf29cd 759 } \
mbed_official 390:35c2c1cf29cd 760 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 761 #define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
mbed_official 390:35c2c1cf29cd 762 #define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
mbed_official 390:35c2c1cf29cd 763 #define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
mbed_official 390:35c2c1cf29cd 764 #define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
mbed_official 390:35c2c1cf29cd 765
mbed_official 390:35c2c1cf29cd 766
mbed_official 390:35c2c1cf29cd 767
mbed_official 390:35c2c1cf29cd 768
mbed_official 390:35c2c1cf29cd 769 /* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
mbed_official 390:35c2c1cf29cd 770 /*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
mbed_official 390:35c2c1cf29cd 771 #define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2
mbed_official 390:35c2c1cf29cd 772 #define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 773 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 774 { \
mbed_official 390:35c2c1cf29cd 775 &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
mbed_official 390:35c2c1cf29cd 776 &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
mbed_official 390:35c2c1cf29cd 777 } \
mbed_official 390:35c2c1cf29cd 778 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 779 #define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
mbed_official 390:35c2c1cf29cd 780 #define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
mbed_official 390:35c2c1cf29cd 781 #define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
mbed_official 390:35c2c1cf29cd 782 #define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
mbed_official 390:35c2c1cf29cd 783
mbed_official 390:35c2c1cf29cd 784
mbed_official 390:35c2c1cf29cd 785
mbed_official 390:35c2c1cf29cd 786
mbed_official 390:35c2c1cf29cd 787 /* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
mbed_official 390:35c2c1cf29cd 788 /*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
mbed_official 390:35c2c1cf29cd 789 #define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2
mbed_official 390:35c2c1cf29cd 790 #define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
mbed_official 390:35c2c1cf29cd 791 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 390:35c2c1cf29cd 792 { \
mbed_official 390:35c2c1cf29cd 793 &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
mbed_official 390:35c2c1cf29cd 794 &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
mbed_official 390:35c2c1cf29cd 795 } \
mbed_official 390:35c2c1cf29cd 796 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 390:35c2c1cf29cd 797 #define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
mbed_official 390:35c2c1cf29cd 798 #define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
mbed_official 390:35c2c1cf29cd 799 #define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
mbed_official 390:35c2c1cf29cd 800 #define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
mbed_official 390:35c2c1cf29cd 801
mbed_official 390:35c2c1cf29cd 802
mbed_official 390:35c2c1cf29cd 803 /* End of channnel array defines of VDC5 */
mbed_official 390:35c2c1cf29cd 804
mbed_official 390:35c2c1cf29cd 805
mbed_official 390:35c2c1cf29cd 806 #define VDC50INP_UPDATE VDC50.INP_UPDATE
mbed_official 390:35c2c1cf29cd 807 #define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
mbed_official 390:35c2c1cf29cd 808 #define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
mbed_official 390:35c2c1cf29cd 809 #define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
mbed_official 390:35c2c1cf29cd 810 #define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
mbed_official 390:35c2c1cf29cd 811 #define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
mbed_official 390:35c2c1cf29cd 812 #define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
mbed_official 390:35c2c1cf29cd 813 #define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
mbed_official 390:35c2c1cf29cd 814 #define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
mbed_official 390:35c2c1cf29cd 815 #define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 816 #define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 817 #define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 818 #define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 819 #define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 820 #define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 821 #define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
mbed_official 390:35c2c1cf29cd 822 #define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
mbed_official 390:35c2c1cf29cd 823 #define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
mbed_official 390:35c2c1cf29cd 824 #define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
mbed_official 390:35c2c1cf29cd 825 #define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
mbed_official 390:35c2c1cf29cd 826 #define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
mbed_official 390:35c2c1cf29cd 827 #define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
mbed_official 390:35c2c1cf29cd 828 #define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
mbed_official 390:35c2c1cf29cd 829 #define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
mbed_official 390:35c2c1cf29cd 830 #define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
mbed_official 390:35c2c1cf29cd 831 #define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
mbed_official 390:35c2c1cf29cd 832 #define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
mbed_official 390:35c2c1cf29cd 833 #define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
mbed_official 390:35c2c1cf29cd 834 #define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
mbed_official 390:35c2c1cf29cd 835 #define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
mbed_official 390:35c2c1cf29cd 836 #define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
mbed_official 390:35c2c1cf29cd 837 #define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
mbed_official 390:35c2c1cf29cd 838 #define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
mbed_official 390:35c2c1cf29cd 839 #define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
mbed_official 390:35c2c1cf29cd 840 #define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
mbed_official 390:35c2c1cf29cd 841 #define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
mbed_official 390:35c2c1cf29cd 842 #define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
mbed_official 390:35c2c1cf29cd 843 #define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
mbed_official 390:35c2c1cf29cd 844 #define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
mbed_official 390:35c2c1cf29cd 845 #define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
mbed_official 390:35c2c1cf29cd 846 #define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
mbed_official 390:35c2c1cf29cd 847 #define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
mbed_official 390:35c2c1cf29cd 848 #define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
mbed_official 390:35c2c1cf29cd 849 #define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
mbed_official 390:35c2c1cf29cd 850 #define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
mbed_official 390:35c2c1cf29cd 851 #define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
mbed_official 390:35c2c1cf29cd 852 #define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
mbed_official 390:35c2c1cf29cd 853 #define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
mbed_official 390:35c2c1cf29cd 854 #define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
mbed_official 390:35c2c1cf29cd 855 #define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
mbed_official 390:35c2c1cf29cd 856 #define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
mbed_official 390:35c2c1cf29cd 857 #define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
mbed_official 390:35c2c1cf29cd 858 #define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
mbed_official 390:35c2c1cf29cd 859 #define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
mbed_official 390:35c2c1cf29cd 860 #define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
mbed_official 390:35c2c1cf29cd 861 #define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
mbed_official 390:35c2c1cf29cd 862 #define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
mbed_official 390:35c2c1cf29cd 863 #define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
mbed_official 390:35c2c1cf29cd 864 #define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
mbed_official 390:35c2c1cf29cd 865 #define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
mbed_official 390:35c2c1cf29cd 866 #define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
mbed_official 390:35c2c1cf29cd 867 #define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
mbed_official 390:35c2c1cf29cd 868 #define VDC50GR0_UPDATE VDC50.GR0_UPDATE
mbed_official 390:35c2c1cf29cd 869 #define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
mbed_official 390:35c2c1cf29cd 870 #define VDC50GR0_FLM1 VDC50.GR0_FLM1
mbed_official 390:35c2c1cf29cd 871 #define VDC50GR0_FLM2 VDC50.GR0_FLM2
mbed_official 390:35c2c1cf29cd 872 #define VDC50GR0_FLM3 VDC50.GR0_FLM3
mbed_official 390:35c2c1cf29cd 873 #define VDC50GR0_FLM4 VDC50.GR0_FLM4
mbed_official 390:35c2c1cf29cd 874 #define VDC50GR0_FLM5 VDC50.GR0_FLM5
mbed_official 390:35c2c1cf29cd 875 #define VDC50GR0_FLM6 VDC50.GR0_FLM6
mbed_official 390:35c2c1cf29cd 876 #define VDC50GR0_AB1 VDC50.GR0_AB1
mbed_official 390:35c2c1cf29cd 877 #define VDC50GR0_AB2 VDC50.GR0_AB2
mbed_official 390:35c2c1cf29cd 878 #define VDC50GR0_AB3 VDC50.GR0_AB3
mbed_official 390:35c2c1cf29cd 879 #define VDC50GR0_AB7 VDC50.GR0_AB7
mbed_official 390:35c2c1cf29cd 880 #define VDC50GR0_AB8 VDC50.GR0_AB8
mbed_official 390:35c2c1cf29cd 881 #define VDC50GR0_AB9 VDC50.GR0_AB9
mbed_official 390:35c2c1cf29cd 882 #define VDC50GR0_AB10 VDC50.GR0_AB10
mbed_official 390:35c2c1cf29cd 883 #define VDC50GR0_AB11 VDC50.GR0_AB11
mbed_official 390:35c2c1cf29cd 884 #define VDC50GR0_BASE VDC50.GR0_BASE
mbed_official 390:35c2c1cf29cd 885 #define VDC50GR0_CLUT VDC50.GR0_CLUT
mbed_official 390:35c2c1cf29cd 886 #define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
mbed_official 390:35c2c1cf29cd 887 #define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
mbed_official 390:35c2c1cf29cd 888 #define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
mbed_official 390:35c2c1cf29cd 889 #define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
mbed_official 390:35c2c1cf29cd 890 #define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
mbed_official 390:35c2c1cf29cd 891 #define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
mbed_official 390:35c2c1cf29cd 892 #define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
mbed_official 390:35c2c1cf29cd 893 #define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
mbed_official 390:35c2c1cf29cd 894 #define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
mbed_official 390:35c2c1cf29cd 895 #define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
mbed_official 390:35c2c1cf29cd 896 #define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
mbed_official 390:35c2c1cf29cd 897 #define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
mbed_official 390:35c2c1cf29cd 898 #define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
mbed_official 390:35c2c1cf29cd 899 #define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
mbed_official 390:35c2c1cf29cd 900 #define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 901 #define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 902 #define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 903 #define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 904 #define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 905 #define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 906 #define VDC50GR2_UPDATE VDC50.GR2_UPDATE
mbed_official 390:35c2c1cf29cd 907 #define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
mbed_official 390:35c2c1cf29cd 908 #define VDC50GR2_FLM1 VDC50.GR2_FLM1
mbed_official 390:35c2c1cf29cd 909 #define VDC50GR2_FLM2 VDC50.GR2_FLM2
mbed_official 390:35c2c1cf29cd 910 #define VDC50GR2_FLM3 VDC50.GR2_FLM3
mbed_official 390:35c2c1cf29cd 911 #define VDC50GR2_FLM4 VDC50.GR2_FLM4
mbed_official 390:35c2c1cf29cd 912 #define VDC50GR2_FLM5 VDC50.GR2_FLM5
mbed_official 390:35c2c1cf29cd 913 #define VDC50GR2_FLM6 VDC50.GR2_FLM6
mbed_official 390:35c2c1cf29cd 914 #define VDC50GR2_AB1 VDC50.GR2_AB1
mbed_official 390:35c2c1cf29cd 915 #define VDC50GR2_AB2 VDC50.GR2_AB2
mbed_official 390:35c2c1cf29cd 916 #define VDC50GR2_AB3 VDC50.GR2_AB3
mbed_official 390:35c2c1cf29cd 917 #define VDC50GR2_AB4 VDC50.GR2_AB4
mbed_official 390:35c2c1cf29cd 918 #define VDC50GR2_AB5 VDC50.GR2_AB5
mbed_official 390:35c2c1cf29cd 919 #define VDC50GR2_AB6 VDC50.GR2_AB6
mbed_official 390:35c2c1cf29cd 920 #define VDC50GR2_AB7 VDC50.GR2_AB7
mbed_official 390:35c2c1cf29cd 921 #define VDC50GR2_AB8 VDC50.GR2_AB8
mbed_official 390:35c2c1cf29cd 922 #define VDC50GR2_AB9 VDC50.GR2_AB9
mbed_official 390:35c2c1cf29cd 923 #define VDC50GR2_AB10 VDC50.GR2_AB10
mbed_official 390:35c2c1cf29cd 924 #define VDC50GR2_AB11 VDC50.GR2_AB11
mbed_official 390:35c2c1cf29cd 925 #define VDC50GR2_BASE VDC50.GR2_BASE
mbed_official 390:35c2c1cf29cd 926 #define VDC50GR2_CLUT VDC50.GR2_CLUT
mbed_official 390:35c2c1cf29cd 927 #define VDC50GR2_MON VDC50.GR2_MON
mbed_official 390:35c2c1cf29cd 928 #define VDC50GR3_UPDATE VDC50.GR3_UPDATE
mbed_official 390:35c2c1cf29cd 929 #define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
mbed_official 390:35c2c1cf29cd 930 #define VDC50GR3_FLM1 VDC50.GR3_FLM1
mbed_official 390:35c2c1cf29cd 931 #define VDC50GR3_FLM2 VDC50.GR3_FLM2
mbed_official 390:35c2c1cf29cd 932 #define VDC50GR3_FLM3 VDC50.GR3_FLM3
mbed_official 390:35c2c1cf29cd 933 #define VDC50GR3_FLM4 VDC50.GR3_FLM4
mbed_official 390:35c2c1cf29cd 934 #define VDC50GR3_FLM5 VDC50.GR3_FLM5
mbed_official 390:35c2c1cf29cd 935 #define VDC50GR3_FLM6 VDC50.GR3_FLM6
mbed_official 390:35c2c1cf29cd 936 #define VDC50GR3_AB1 VDC50.GR3_AB1
mbed_official 390:35c2c1cf29cd 937 #define VDC50GR3_AB2 VDC50.GR3_AB2
mbed_official 390:35c2c1cf29cd 938 #define VDC50GR3_AB3 VDC50.GR3_AB3
mbed_official 390:35c2c1cf29cd 939 #define VDC50GR3_AB4 VDC50.GR3_AB4
mbed_official 390:35c2c1cf29cd 940 #define VDC50GR3_AB5 VDC50.GR3_AB5
mbed_official 390:35c2c1cf29cd 941 #define VDC50GR3_AB6 VDC50.GR3_AB6
mbed_official 390:35c2c1cf29cd 942 #define VDC50GR3_AB7 VDC50.GR3_AB7
mbed_official 390:35c2c1cf29cd 943 #define VDC50GR3_AB8 VDC50.GR3_AB8
mbed_official 390:35c2c1cf29cd 944 #define VDC50GR3_AB9 VDC50.GR3_AB9
mbed_official 390:35c2c1cf29cd 945 #define VDC50GR3_AB10 VDC50.GR3_AB10
mbed_official 390:35c2c1cf29cd 946 #define VDC50GR3_AB11 VDC50.GR3_AB11
mbed_official 390:35c2c1cf29cd 947 #define VDC50GR3_BASE VDC50.GR3_BASE
mbed_official 390:35c2c1cf29cd 948 #define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
mbed_official 390:35c2c1cf29cd 949 #define VDC50GR3_MON VDC50.GR3_MON
mbed_official 390:35c2c1cf29cd 950 #define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
mbed_official 390:35c2c1cf29cd 951 #define VDC50GAM_SW VDC50.GAM_SW
mbed_official 390:35c2c1cf29cd 952 #define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
mbed_official 390:35c2c1cf29cd 953 #define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
mbed_official 390:35c2c1cf29cd 954 #define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
mbed_official 390:35c2c1cf29cd 955 #define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
mbed_official 390:35c2c1cf29cd 956 #define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
mbed_official 390:35c2c1cf29cd 957 #define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
mbed_official 390:35c2c1cf29cd 958 #define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
mbed_official 390:35c2c1cf29cd 959 #define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
mbed_official 390:35c2c1cf29cd 960 #define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
mbed_official 390:35c2c1cf29cd 961 #define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
mbed_official 390:35c2c1cf29cd 962 #define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
mbed_official 390:35c2c1cf29cd 963 #define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
mbed_official 390:35c2c1cf29cd 964 #define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
mbed_official 390:35c2c1cf29cd 965 #define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
mbed_official 390:35c2c1cf29cd 966 #define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
mbed_official 390:35c2c1cf29cd 967 #define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
mbed_official 390:35c2c1cf29cd 968 #define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
mbed_official 390:35c2c1cf29cd 969 #define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
mbed_official 390:35c2c1cf29cd 970 #define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
mbed_official 390:35c2c1cf29cd 971 #define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
mbed_official 390:35c2c1cf29cd 972 #define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
mbed_official 390:35c2c1cf29cd 973 #define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
mbed_official 390:35c2c1cf29cd 974 #define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
mbed_official 390:35c2c1cf29cd 975 #define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
mbed_official 390:35c2c1cf29cd 976 #define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
mbed_official 390:35c2c1cf29cd 977 #define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
mbed_official 390:35c2c1cf29cd 978 #define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
mbed_official 390:35c2c1cf29cd 979 #define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
mbed_official 390:35c2c1cf29cd 980 #define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
mbed_official 390:35c2c1cf29cd 981 #define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
mbed_official 390:35c2c1cf29cd 982 #define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
mbed_official 390:35c2c1cf29cd 983 #define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
mbed_official 390:35c2c1cf29cd 984 #define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
mbed_official 390:35c2c1cf29cd 985 #define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
mbed_official 390:35c2c1cf29cd 986 #define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
mbed_official 390:35c2c1cf29cd 987 #define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
mbed_official 390:35c2c1cf29cd 988 #define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
mbed_official 390:35c2c1cf29cd 989 #define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
mbed_official 390:35c2c1cf29cd 990 #define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
mbed_official 390:35c2c1cf29cd 991 #define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
mbed_official 390:35c2c1cf29cd 992 #define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
mbed_official 390:35c2c1cf29cd 993 #define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
mbed_official 390:35c2c1cf29cd 994 #define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
mbed_official 390:35c2c1cf29cd 995 #define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
mbed_official 390:35c2c1cf29cd 996 #define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
mbed_official 390:35c2c1cf29cd 997 #define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
mbed_official 390:35c2c1cf29cd 998 #define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
mbed_official 390:35c2c1cf29cd 999 #define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
mbed_official 390:35c2c1cf29cd 1000 #define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
mbed_official 390:35c2c1cf29cd 1001 #define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
mbed_official 390:35c2c1cf29cd 1002 #define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
mbed_official 390:35c2c1cf29cd 1003 #define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
mbed_official 390:35c2c1cf29cd 1004 #define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
mbed_official 390:35c2c1cf29cd 1005 #define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
mbed_official 390:35c2c1cf29cd 1006 #define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
mbed_official 390:35c2c1cf29cd 1007 #define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
mbed_official 390:35c2c1cf29cd 1008 #define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
mbed_official 390:35c2c1cf29cd 1009 #define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
mbed_official 390:35c2c1cf29cd 1010 #define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
mbed_official 390:35c2c1cf29cd 1011 #define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
mbed_official 390:35c2c1cf29cd 1012 #define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
mbed_official 390:35c2c1cf29cd 1013 #define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
mbed_official 390:35c2c1cf29cd 1014 #define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
mbed_official 390:35c2c1cf29cd 1015 #define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
mbed_official 390:35c2c1cf29cd 1016 #define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
mbed_official 390:35c2c1cf29cd 1017 #define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
mbed_official 390:35c2c1cf29cd 1018 #define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
mbed_official 390:35c2c1cf29cd 1019 #define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
mbed_official 390:35c2c1cf29cd 1020 #define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
mbed_official 390:35c2c1cf29cd 1021 #define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
mbed_official 390:35c2c1cf29cd 1022 #define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
mbed_official 390:35c2c1cf29cd 1023 #define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
mbed_official 390:35c2c1cf29cd 1024 #define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
mbed_official 390:35c2c1cf29cd 1025 #define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
mbed_official 390:35c2c1cf29cd 1026 #define VDC50TCON_UPDATE VDC50.TCON_UPDATE
mbed_official 390:35c2c1cf29cd 1027 #define VDC50TCON_TIM VDC50.TCON_TIM
mbed_official 390:35c2c1cf29cd 1028 #define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
mbed_official 390:35c2c1cf29cd 1029 #define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
mbed_official 390:35c2c1cf29cd 1030 #define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
mbed_official 390:35c2c1cf29cd 1031 #define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
mbed_official 390:35c2c1cf29cd 1032 #define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
mbed_official 390:35c2c1cf29cd 1033 #define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
mbed_official 390:35c2c1cf29cd 1034 #define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
mbed_official 390:35c2c1cf29cd 1035 #define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
mbed_official 390:35c2c1cf29cd 1036 #define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
mbed_official 390:35c2c1cf29cd 1037 #define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
mbed_official 390:35c2c1cf29cd 1038 #define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
mbed_official 390:35c2c1cf29cd 1039 #define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
mbed_official 390:35c2c1cf29cd 1040 #define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
mbed_official 390:35c2c1cf29cd 1041 #define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
mbed_official 390:35c2c1cf29cd 1042 #define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
mbed_official 390:35c2c1cf29cd 1043 #define VDC50OUT_UPDATE VDC50.OUT_UPDATE
mbed_official 390:35c2c1cf29cd 1044 #define VDC50OUT_SET VDC50.OUT_SET
mbed_official 390:35c2c1cf29cd 1045 #define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
mbed_official 390:35c2c1cf29cd 1046 #define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
mbed_official 390:35c2c1cf29cd 1047 #define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
mbed_official 390:35c2c1cf29cd 1048 #define VDC50OUT_PDTHA VDC50.OUT_PDTHA
mbed_official 390:35c2c1cf29cd 1049 #define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
mbed_official 390:35c2c1cf29cd 1050 #define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
mbed_official 390:35c2c1cf29cd 1051 #define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
mbed_official 390:35c2c1cf29cd 1052 #define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
mbed_official 390:35c2c1cf29cd 1053 #define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
mbed_official 390:35c2c1cf29cd 1054 #define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
mbed_official 390:35c2c1cf29cd 1055 #define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
mbed_official 390:35c2c1cf29cd 1056 #define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
mbed_official 390:35c2c1cf29cd 1057 #define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
mbed_official 390:35c2c1cf29cd 1058 #define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
mbed_official 390:35c2c1cf29cd 1059 #define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
mbed_official 390:35c2c1cf29cd 1060 #define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
mbed_official 390:35c2c1cf29cd 1061 #define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
mbed_official 390:35c2c1cf29cd 1062 #define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
mbed_official 390:35c2c1cf29cd 1063 #define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
mbed_official 390:35c2c1cf29cd 1064 #define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
mbed_official 390:35c2c1cf29cd 1065 #define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
mbed_official 390:35c2c1cf29cd 1066 #define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
mbed_official 390:35c2c1cf29cd 1067 #define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
mbed_official 390:35c2c1cf29cd 1068 #define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
mbed_official 390:35c2c1cf29cd 1069 #define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
mbed_official 390:35c2c1cf29cd 1070 #define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
mbed_official 390:35c2c1cf29cd 1071 #define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
mbed_official 390:35c2c1cf29cd 1072 #define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
mbed_official 390:35c2c1cf29cd 1073 #define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
mbed_official 390:35c2c1cf29cd 1074 #define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
mbed_official 390:35c2c1cf29cd 1075 #define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
mbed_official 390:35c2c1cf29cd 1076 #define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
mbed_official 390:35c2c1cf29cd 1077 #define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
mbed_official 390:35c2c1cf29cd 1078 #define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
mbed_official 390:35c2c1cf29cd 1079 #define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
mbed_official 390:35c2c1cf29cd 1080 #define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
mbed_official 390:35c2c1cf29cd 1081 #define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
mbed_official 390:35c2c1cf29cd 1082 #define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
mbed_official 390:35c2c1cf29cd 1083 #define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
mbed_official 390:35c2c1cf29cd 1084 #define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
mbed_official 390:35c2c1cf29cd 1085 #define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
mbed_official 390:35c2c1cf29cd 1086 #define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
mbed_official 390:35c2c1cf29cd 1087 #define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
mbed_official 390:35c2c1cf29cd 1088 #define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
mbed_official 390:35c2c1cf29cd 1089 #define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
mbed_official 390:35c2c1cf29cd 1090 #define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
mbed_official 390:35c2c1cf29cd 1091 #define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
mbed_official 390:35c2c1cf29cd 1092 #define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
mbed_official 390:35c2c1cf29cd 1093 #define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
mbed_official 390:35c2c1cf29cd 1094 #define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
mbed_official 390:35c2c1cf29cd 1095 #define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
mbed_official 390:35c2c1cf29cd 1096 #define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
mbed_official 390:35c2c1cf29cd 1097 #define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
mbed_official 390:35c2c1cf29cd 1098 #define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
mbed_official 390:35c2c1cf29cd 1099 #define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
mbed_official 390:35c2c1cf29cd 1100 #define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
mbed_official 390:35c2c1cf29cd 1101 #define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
mbed_official 390:35c2c1cf29cd 1102 #define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
mbed_official 390:35c2c1cf29cd 1103 #define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
mbed_official 390:35c2c1cf29cd 1104 #define VDC50GR1_UPDATE VDC50.GR1_UPDATE
mbed_official 390:35c2c1cf29cd 1105 #define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
mbed_official 390:35c2c1cf29cd 1106 #define VDC50GR1_FLM1 VDC50.GR1_FLM1
mbed_official 390:35c2c1cf29cd 1107 #define VDC50GR1_FLM2 VDC50.GR1_FLM2
mbed_official 390:35c2c1cf29cd 1108 #define VDC50GR1_FLM3 VDC50.GR1_FLM3
mbed_official 390:35c2c1cf29cd 1109 #define VDC50GR1_FLM4 VDC50.GR1_FLM4
mbed_official 390:35c2c1cf29cd 1110 #define VDC50GR1_FLM5 VDC50.GR1_FLM5
mbed_official 390:35c2c1cf29cd 1111 #define VDC50GR1_FLM6 VDC50.GR1_FLM6
mbed_official 390:35c2c1cf29cd 1112 #define VDC50GR1_AB1 VDC50.GR1_AB1
mbed_official 390:35c2c1cf29cd 1113 #define VDC50GR1_AB2 VDC50.GR1_AB2
mbed_official 390:35c2c1cf29cd 1114 #define VDC50GR1_AB3 VDC50.GR1_AB3
mbed_official 390:35c2c1cf29cd 1115 #define VDC50GR1_AB4 VDC50.GR1_AB4
mbed_official 390:35c2c1cf29cd 1116 #define VDC50GR1_AB5 VDC50.GR1_AB5
mbed_official 390:35c2c1cf29cd 1117 #define VDC50GR1_AB6 VDC50.GR1_AB6
mbed_official 390:35c2c1cf29cd 1118 #define VDC50GR1_AB7 VDC50.GR1_AB7
mbed_official 390:35c2c1cf29cd 1119 #define VDC50GR1_AB8 VDC50.GR1_AB8
mbed_official 390:35c2c1cf29cd 1120 #define VDC50GR1_AB9 VDC50.GR1_AB9
mbed_official 390:35c2c1cf29cd 1121 #define VDC50GR1_AB10 VDC50.GR1_AB10
mbed_official 390:35c2c1cf29cd 1122 #define VDC50GR1_AB11 VDC50.GR1_AB11
mbed_official 390:35c2c1cf29cd 1123 #define VDC50GR1_BASE VDC50.GR1_BASE
mbed_official 390:35c2c1cf29cd 1124 #define VDC50GR1_CLUT VDC50.GR1_CLUT
mbed_official 390:35c2c1cf29cd 1125 #define VDC50GR1_MON VDC50.GR1_MON
mbed_official 390:35c2c1cf29cd 1126 #define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
mbed_official 390:35c2c1cf29cd 1127 #define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
mbed_official 390:35c2c1cf29cd 1128 #define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
mbed_official 390:35c2c1cf29cd 1129 #define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
mbed_official 390:35c2c1cf29cd 1130 #define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
mbed_official 390:35c2c1cf29cd 1131 #define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
mbed_official 390:35c2c1cf29cd 1132 #define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
mbed_official 390:35c2c1cf29cd 1133 #define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
mbed_official 390:35c2c1cf29cd 1134 #define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
mbed_official 390:35c2c1cf29cd 1135 #define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
mbed_official 390:35c2c1cf29cd 1136 #define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
mbed_official 390:35c2c1cf29cd 1137 #define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
mbed_official 390:35c2c1cf29cd 1138 #define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
mbed_official 390:35c2c1cf29cd 1139 #define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
mbed_official 390:35c2c1cf29cd 1140 #define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 1141 #define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 1142 #define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 1143 #define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 1144 #define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 1145 #define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 1146 #define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
mbed_official 390:35c2c1cf29cd 1147 #define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
mbed_official 390:35c2c1cf29cd 1148 #define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
mbed_official 390:35c2c1cf29cd 1149 #define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
mbed_official 390:35c2c1cf29cd 1150 #define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
mbed_official 390:35c2c1cf29cd 1151 #define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
mbed_official 390:35c2c1cf29cd 1152 #define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
mbed_official 390:35c2c1cf29cd 1153 #define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
mbed_official 390:35c2c1cf29cd 1154 #define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
mbed_official 390:35c2c1cf29cd 1155 #define VDC50GR_VIN_MON VDC50.GR_VIN_MON
mbed_official 390:35c2c1cf29cd 1156 #define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
mbed_official 390:35c2c1cf29cd 1157 #define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
mbed_official 390:35c2c1cf29cd 1158 #define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
mbed_official 390:35c2c1cf29cd 1159 #define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
mbed_official 390:35c2c1cf29cd 1160 #define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
mbed_official 390:35c2c1cf29cd 1161 #define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
mbed_official 390:35c2c1cf29cd 1162 #define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
mbed_official 390:35c2c1cf29cd 1163 #define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
mbed_official 390:35c2c1cf29cd 1164 #define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
mbed_official 390:35c2c1cf29cd 1165 #define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
mbed_official 390:35c2c1cf29cd 1166 #define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
mbed_official 390:35c2c1cf29cd 1167 #define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
mbed_official 390:35c2c1cf29cd 1168 #define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
mbed_official 390:35c2c1cf29cd 1169 #define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
mbed_official 390:35c2c1cf29cd 1170 #define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
mbed_official 390:35c2c1cf29cd 1171 #define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
mbed_official 390:35c2c1cf29cd 1172 #define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
mbed_official 390:35c2c1cf29cd 1173 #define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
mbed_official 390:35c2c1cf29cd 1174 #define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
mbed_official 390:35c2c1cf29cd 1175 #define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
mbed_official 390:35c2c1cf29cd 1176 #define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
mbed_official 390:35c2c1cf29cd 1177 #define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
mbed_official 390:35c2c1cf29cd 1178 #define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
mbed_official 390:35c2c1cf29cd 1179 #define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
mbed_official 390:35c2c1cf29cd 1180 #define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
mbed_official 390:35c2c1cf29cd 1181 #define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
mbed_official 390:35c2c1cf29cd 1182 #define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
mbed_official 390:35c2c1cf29cd 1183 #define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
mbed_official 390:35c2c1cf29cd 1184 #define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
mbed_official 390:35c2c1cf29cd 1185 #define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
mbed_official 390:35c2c1cf29cd 1186 #define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
mbed_official 390:35c2c1cf29cd 1187 #define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
mbed_official 390:35c2c1cf29cd 1188 #define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
mbed_official 390:35c2c1cf29cd 1189 #define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
mbed_official 390:35c2c1cf29cd 1190 #define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
mbed_official 390:35c2c1cf29cd 1191 #define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
mbed_official 390:35c2c1cf29cd 1192 #define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
mbed_official 390:35c2c1cf29cd 1193 #define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
mbed_official 390:35c2c1cf29cd 1194 #define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
mbed_official 390:35c2c1cf29cd 1195 #define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
mbed_official 390:35c2c1cf29cd 1196 #define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
mbed_official 390:35c2c1cf29cd 1197 #define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
mbed_official 390:35c2c1cf29cd 1198 #define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
mbed_official 390:35c2c1cf29cd 1199 #define VDC50GR_OIR_MON VDC50.GR_OIR_MON
mbed_official 390:35c2c1cf29cd 1200 #define VDC51INP_UPDATE VDC51.INP_UPDATE
mbed_official 390:35c2c1cf29cd 1201 #define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
mbed_official 390:35c2c1cf29cd 1202 #define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
mbed_official 390:35c2c1cf29cd 1203 #define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
mbed_official 390:35c2c1cf29cd 1204 #define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
mbed_official 390:35c2c1cf29cd 1205 #define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
mbed_official 390:35c2c1cf29cd 1206 #define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
mbed_official 390:35c2c1cf29cd 1207 #define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
mbed_official 390:35c2c1cf29cd 1208 #define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
mbed_official 390:35c2c1cf29cd 1209 #define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 1210 #define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 1211 #define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 1212 #define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 1213 #define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 1214 #define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 1215 #define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
mbed_official 390:35c2c1cf29cd 1216 #define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
mbed_official 390:35c2c1cf29cd 1217 #define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
mbed_official 390:35c2c1cf29cd 1218 #define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
mbed_official 390:35c2c1cf29cd 1219 #define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
mbed_official 390:35c2c1cf29cd 1220 #define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
mbed_official 390:35c2c1cf29cd 1221 #define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
mbed_official 390:35c2c1cf29cd 1222 #define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
mbed_official 390:35c2c1cf29cd 1223 #define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
mbed_official 390:35c2c1cf29cd 1224 #define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
mbed_official 390:35c2c1cf29cd 1225 #define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
mbed_official 390:35c2c1cf29cd 1226 #define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
mbed_official 390:35c2c1cf29cd 1227 #define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
mbed_official 390:35c2c1cf29cd 1228 #define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
mbed_official 390:35c2c1cf29cd 1229 #define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
mbed_official 390:35c2c1cf29cd 1230 #define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
mbed_official 390:35c2c1cf29cd 1231 #define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
mbed_official 390:35c2c1cf29cd 1232 #define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
mbed_official 390:35c2c1cf29cd 1233 #define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
mbed_official 390:35c2c1cf29cd 1234 #define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
mbed_official 390:35c2c1cf29cd 1235 #define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
mbed_official 390:35c2c1cf29cd 1236 #define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
mbed_official 390:35c2c1cf29cd 1237 #define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
mbed_official 390:35c2c1cf29cd 1238 #define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
mbed_official 390:35c2c1cf29cd 1239 #define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
mbed_official 390:35c2c1cf29cd 1240 #define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
mbed_official 390:35c2c1cf29cd 1241 #define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
mbed_official 390:35c2c1cf29cd 1242 #define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
mbed_official 390:35c2c1cf29cd 1243 #define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
mbed_official 390:35c2c1cf29cd 1244 #define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
mbed_official 390:35c2c1cf29cd 1245 #define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
mbed_official 390:35c2c1cf29cd 1246 #define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
mbed_official 390:35c2c1cf29cd 1247 #define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
mbed_official 390:35c2c1cf29cd 1248 #define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
mbed_official 390:35c2c1cf29cd 1249 #define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
mbed_official 390:35c2c1cf29cd 1250 #define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
mbed_official 390:35c2c1cf29cd 1251 #define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
mbed_official 390:35c2c1cf29cd 1252 #define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
mbed_official 390:35c2c1cf29cd 1253 #define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
mbed_official 390:35c2c1cf29cd 1254 #define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
mbed_official 390:35c2c1cf29cd 1255 #define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
mbed_official 390:35c2c1cf29cd 1256 #define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
mbed_official 390:35c2c1cf29cd 1257 #define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
mbed_official 390:35c2c1cf29cd 1258 #define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
mbed_official 390:35c2c1cf29cd 1259 #define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
mbed_official 390:35c2c1cf29cd 1260 #define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
mbed_official 390:35c2c1cf29cd 1261 #define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
mbed_official 390:35c2c1cf29cd 1262 #define VDC51GR0_UPDATE VDC51.GR0_UPDATE
mbed_official 390:35c2c1cf29cd 1263 #define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
mbed_official 390:35c2c1cf29cd 1264 #define VDC51GR0_FLM1 VDC51.GR0_FLM1
mbed_official 390:35c2c1cf29cd 1265 #define VDC51GR0_FLM2 VDC51.GR0_FLM2
mbed_official 390:35c2c1cf29cd 1266 #define VDC51GR0_FLM3 VDC51.GR0_FLM3
mbed_official 390:35c2c1cf29cd 1267 #define VDC51GR0_FLM4 VDC51.GR0_FLM4
mbed_official 390:35c2c1cf29cd 1268 #define VDC51GR0_FLM5 VDC51.GR0_FLM5
mbed_official 390:35c2c1cf29cd 1269 #define VDC51GR0_FLM6 VDC51.GR0_FLM6
mbed_official 390:35c2c1cf29cd 1270 #define VDC51GR0_AB1 VDC51.GR0_AB1
mbed_official 390:35c2c1cf29cd 1271 #define VDC51GR0_AB2 VDC51.GR0_AB2
mbed_official 390:35c2c1cf29cd 1272 #define VDC51GR0_AB3 VDC51.GR0_AB3
mbed_official 390:35c2c1cf29cd 1273 #define VDC51GR0_AB7 VDC51.GR0_AB7
mbed_official 390:35c2c1cf29cd 1274 #define VDC51GR0_AB8 VDC51.GR0_AB8
mbed_official 390:35c2c1cf29cd 1275 #define VDC51GR0_AB9 VDC51.GR0_AB9
mbed_official 390:35c2c1cf29cd 1276 #define VDC51GR0_AB10 VDC51.GR0_AB10
mbed_official 390:35c2c1cf29cd 1277 #define VDC51GR0_AB11 VDC51.GR0_AB11
mbed_official 390:35c2c1cf29cd 1278 #define VDC51GR0_BASE VDC51.GR0_BASE
mbed_official 390:35c2c1cf29cd 1279 #define VDC51GR0_CLUT VDC51.GR0_CLUT
mbed_official 390:35c2c1cf29cd 1280 #define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
mbed_official 390:35c2c1cf29cd 1281 #define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
mbed_official 390:35c2c1cf29cd 1282 #define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
mbed_official 390:35c2c1cf29cd 1283 #define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
mbed_official 390:35c2c1cf29cd 1284 #define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
mbed_official 390:35c2c1cf29cd 1285 #define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
mbed_official 390:35c2c1cf29cd 1286 #define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
mbed_official 390:35c2c1cf29cd 1287 #define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
mbed_official 390:35c2c1cf29cd 1288 #define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
mbed_official 390:35c2c1cf29cd 1289 #define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
mbed_official 390:35c2c1cf29cd 1290 #define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
mbed_official 390:35c2c1cf29cd 1291 #define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
mbed_official 390:35c2c1cf29cd 1292 #define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
mbed_official 390:35c2c1cf29cd 1293 #define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
mbed_official 390:35c2c1cf29cd 1294 #define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 1295 #define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 1296 #define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 1297 #define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 1298 #define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 1299 #define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 1300 #define VDC51GR2_UPDATE VDC51.GR2_UPDATE
mbed_official 390:35c2c1cf29cd 1301 #define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
mbed_official 390:35c2c1cf29cd 1302 #define VDC51GR2_FLM1 VDC51.GR2_FLM1
mbed_official 390:35c2c1cf29cd 1303 #define VDC51GR2_FLM2 VDC51.GR2_FLM2
mbed_official 390:35c2c1cf29cd 1304 #define VDC51GR2_FLM3 VDC51.GR2_FLM3
mbed_official 390:35c2c1cf29cd 1305 #define VDC51GR2_FLM4 VDC51.GR2_FLM4
mbed_official 390:35c2c1cf29cd 1306 #define VDC51GR2_FLM5 VDC51.GR2_FLM5
mbed_official 390:35c2c1cf29cd 1307 #define VDC51GR2_FLM6 VDC51.GR2_FLM6
mbed_official 390:35c2c1cf29cd 1308 #define VDC51GR2_AB1 VDC51.GR2_AB1
mbed_official 390:35c2c1cf29cd 1309 #define VDC51GR2_AB2 VDC51.GR2_AB2
mbed_official 390:35c2c1cf29cd 1310 #define VDC51GR2_AB3 VDC51.GR2_AB3
mbed_official 390:35c2c1cf29cd 1311 #define VDC51GR2_AB4 VDC51.GR2_AB4
mbed_official 390:35c2c1cf29cd 1312 #define VDC51GR2_AB5 VDC51.GR2_AB5
mbed_official 390:35c2c1cf29cd 1313 #define VDC51GR2_AB6 VDC51.GR2_AB6
mbed_official 390:35c2c1cf29cd 1314 #define VDC51GR2_AB7 VDC51.GR2_AB7
mbed_official 390:35c2c1cf29cd 1315 #define VDC51GR2_AB8 VDC51.GR2_AB8
mbed_official 390:35c2c1cf29cd 1316 #define VDC51GR2_AB9 VDC51.GR2_AB9
mbed_official 390:35c2c1cf29cd 1317 #define VDC51GR2_AB10 VDC51.GR2_AB10
mbed_official 390:35c2c1cf29cd 1318 #define VDC51GR2_AB11 VDC51.GR2_AB11
mbed_official 390:35c2c1cf29cd 1319 #define VDC51GR2_BASE VDC51.GR2_BASE
mbed_official 390:35c2c1cf29cd 1320 #define VDC51GR2_CLUT VDC51.GR2_CLUT
mbed_official 390:35c2c1cf29cd 1321 #define VDC51GR2_MON VDC51.GR2_MON
mbed_official 390:35c2c1cf29cd 1322 #define VDC51GR3_UPDATE VDC51.GR3_UPDATE
mbed_official 390:35c2c1cf29cd 1323 #define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
mbed_official 390:35c2c1cf29cd 1324 #define VDC51GR3_FLM1 VDC51.GR3_FLM1
mbed_official 390:35c2c1cf29cd 1325 #define VDC51GR3_FLM2 VDC51.GR3_FLM2
mbed_official 390:35c2c1cf29cd 1326 #define VDC51GR3_FLM3 VDC51.GR3_FLM3
mbed_official 390:35c2c1cf29cd 1327 #define VDC51GR3_FLM4 VDC51.GR3_FLM4
mbed_official 390:35c2c1cf29cd 1328 #define VDC51GR3_FLM5 VDC51.GR3_FLM5
mbed_official 390:35c2c1cf29cd 1329 #define VDC51GR3_FLM6 VDC51.GR3_FLM6
mbed_official 390:35c2c1cf29cd 1330 #define VDC51GR3_AB1 VDC51.GR3_AB1
mbed_official 390:35c2c1cf29cd 1331 #define VDC51GR3_AB2 VDC51.GR3_AB2
mbed_official 390:35c2c1cf29cd 1332 #define VDC51GR3_AB3 VDC51.GR3_AB3
mbed_official 390:35c2c1cf29cd 1333 #define VDC51GR3_AB4 VDC51.GR3_AB4
mbed_official 390:35c2c1cf29cd 1334 #define VDC51GR3_AB5 VDC51.GR3_AB5
mbed_official 390:35c2c1cf29cd 1335 #define VDC51GR3_AB6 VDC51.GR3_AB6
mbed_official 390:35c2c1cf29cd 1336 #define VDC51GR3_AB7 VDC51.GR3_AB7
mbed_official 390:35c2c1cf29cd 1337 #define VDC51GR3_AB8 VDC51.GR3_AB8
mbed_official 390:35c2c1cf29cd 1338 #define VDC51GR3_AB9 VDC51.GR3_AB9
mbed_official 390:35c2c1cf29cd 1339 #define VDC51GR3_AB10 VDC51.GR3_AB10
mbed_official 390:35c2c1cf29cd 1340 #define VDC51GR3_AB11 VDC51.GR3_AB11
mbed_official 390:35c2c1cf29cd 1341 #define VDC51GR3_BASE VDC51.GR3_BASE
mbed_official 390:35c2c1cf29cd 1342 #define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
mbed_official 390:35c2c1cf29cd 1343 #define VDC51GR3_MON VDC51.GR3_MON
mbed_official 390:35c2c1cf29cd 1344 #define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
mbed_official 390:35c2c1cf29cd 1345 #define VDC51GAM_SW VDC51.GAM_SW
mbed_official 390:35c2c1cf29cd 1346 #define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
mbed_official 390:35c2c1cf29cd 1347 #define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
mbed_official 390:35c2c1cf29cd 1348 #define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
mbed_official 390:35c2c1cf29cd 1349 #define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
mbed_official 390:35c2c1cf29cd 1350 #define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
mbed_official 390:35c2c1cf29cd 1351 #define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
mbed_official 390:35c2c1cf29cd 1352 #define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
mbed_official 390:35c2c1cf29cd 1353 #define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
mbed_official 390:35c2c1cf29cd 1354 #define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
mbed_official 390:35c2c1cf29cd 1355 #define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
mbed_official 390:35c2c1cf29cd 1356 #define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
mbed_official 390:35c2c1cf29cd 1357 #define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
mbed_official 390:35c2c1cf29cd 1358 #define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
mbed_official 390:35c2c1cf29cd 1359 #define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
mbed_official 390:35c2c1cf29cd 1360 #define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
mbed_official 390:35c2c1cf29cd 1361 #define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
mbed_official 390:35c2c1cf29cd 1362 #define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
mbed_official 390:35c2c1cf29cd 1363 #define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
mbed_official 390:35c2c1cf29cd 1364 #define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
mbed_official 390:35c2c1cf29cd 1365 #define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
mbed_official 390:35c2c1cf29cd 1366 #define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
mbed_official 390:35c2c1cf29cd 1367 #define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
mbed_official 390:35c2c1cf29cd 1368 #define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
mbed_official 390:35c2c1cf29cd 1369 #define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
mbed_official 390:35c2c1cf29cd 1370 #define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
mbed_official 390:35c2c1cf29cd 1371 #define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
mbed_official 390:35c2c1cf29cd 1372 #define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
mbed_official 390:35c2c1cf29cd 1373 #define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
mbed_official 390:35c2c1cf29cd 1374 #define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
mbed_official 390:35c2c1cf29cd 1375 #define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
mbed_official 390:35c2c1cf29cd 1376 #define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
mbed_official 390:35c2c1cf29cd 1377 #define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
mbed_official 390:35c2c1cf29cd 1378 #define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
mbed_official 390:35c2c1cf29cd 1379 #define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
mbed_official 390:35c2c1cf29cd 1380 #define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
mbed_official 390:35c2c1cf29cd 1381 #define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
mbed_official 390:35c2c1cf29cd 1382 #define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
mbed_official 390:35c2c1cf29cd 1383 #define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
mbed_official 390:35c2c1cf29cd 1384 #define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
mbed_official 390:35c2c1cf29cd 1385 #define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
mbed_official 390:35c2c1cf29cd 1386 #define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
mbed_official 390:35c2c1cf29cd 1387 #define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
mbed_official 390:35c2c1cf29cd 1388 #define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
mbed_official 390:35c2c1cf29cd 1389 #define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
mbed_official 390:35c2c1cf29cd 1390 #define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
mbed_official 390:35c2c1cf29cd 1391 #define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
mbed_official 390:35c2c1cf29cd 1392 #define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
mbed_official 390:35c2c1cf29cd 1393 #define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
mbed_official 390:35c2c1cf29cd 1394 #define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
mbed_official 390:35c2c1cf29cd 1395 #define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
mbed_official 390:35c2c1cf29cd 1396 #define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
mbed_official 390:35c2c1cf29cd 1397 #define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
mbed_official 390:35c2c1cf29cd 1398 #define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
mbed_official 390:35c2c1cf29cd 1399 #define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
mbed_official 390:35c2c1cf29cd 1400 #define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
mbed_official 390:35c2c1cf29cd 1401 #define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
mbed_official 390:35c2c1cf29cd 1402 #define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
mbed_official 390:35c2c1cf29cd 1403 #define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
mbed_official 390:35c2c1cf29cd 1404 #define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
mbed_official 390:35c2c1cf29cd 1405 #define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
mbed_official 390:35c2c1cf29cd 1406 #define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
mbed_official 390:35c2c1cf29cd 1407 #define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
mbed_official 390:35c2c1cf29cd 1408 #define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
mbed_official 390:35c2c1cf29cd 1409 #define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
mbed_official 390:35c2c1cf29cd 1410 #define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
mbed_official 390:35c2c1cf29cd 1411 #define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
mbed_official 390:35c2c1cf29cd 1412 #define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
mbed_official 390:35c2c1cf29cd 1413 #define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
mbed_official 390:35c2c1cf29cd 1414 #define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
mbed_official 390:35c2c1cf29cd 1415 #define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
mbed_official 390:35c2c1cf29cd 1416 #define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
mbed_official 390:35c2c1cf29cd 1417 #define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
mbed_official 390:35c2c1cf29cd 1418 #define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
mbed_official 390:35c2c1cf29cd 1419 #define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
mbed_official 390:35c2c1cf29cd 1420 #define VDC51TCON_UPDATE VDC51.TCON_UPDATE
mbed_official 390:35c2c1cf29cd 1421 #define VDC51TCON_TIM VDC51.TCON_TIM
mbed_official 390:35c2c1cf29cd 1422 #define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
mbed_official 390:35c2c1cf29cd 1423 #define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
mbed_official 390:35c2c1cf29cd 1424 #define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
mbed_official 390:35c2c1cf29cd 1425 #define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
mbed_official 390:35c2c1cf29cd 1426 #define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
mbed_official 390:35c2c1cf29cd 1427 #define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
mbed_official 390:35c2c1cf29cd 1428 #define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
mbed_official 390:35c2c1cf29cd 1429 #define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
mbed_official 390:35c2c1cf29cd 1430 #define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
mbed_official 390:35c2c1cf29cd 1431 #define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
mbed_official 390:35c2c1cf29cd 1432 #define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
mbed_official 390:35c2c1cf29cd 1433 #define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
mbed_official 390:35c2c1cf29cd 1434 #define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
mbed_official 390:35c2c1cf29cd 1435 #define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
mbed_official 390:35c2c1cf29cd 1436 #define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
mbed_official 390:35c2c1cf29cd 1437 #define VDC51OUT_UPDATE VDC51.OUT_UPDATE
mbed_official 390:35c2c1cf29cd 1438 #define VDC51OUT_SET VDC51.OUT_SET
mbed_official 390:35c2c1cf29cd 1439 #define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
mbed_official 390:35c2c1cf29cd 1440 #define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
mbed_official 390:35c2c1cf29cd 1441 #define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
mbed_official 390:35c2c1cf29cd 1442 #define VDC51OUT_PDTHA VDC51.OUT_PDTHA
mbed_official 390:35c2c1cf29cd 1443 #define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
mbed_official 390:35c2c1cf29cd 1444 #define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
mbed_official 390:35c2c1cf29cd 1445 #define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
mbed_official 390:35c2c1cf29cd 1446 #define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
mbed_official 390:35c2c1cf29cd 1447 #define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
mbed_official 390:35c2c1cf29cd 1448 #define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
mbed_official 390:35c2c1cf29cd 1449 #define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
mbed_official 390:35c2c1cf29cd 1450 #define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
mbed_official 390:35c2c1cf29cd 1451 #define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
mbed_official 390:35c2c1cf29cd 1452 #define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
mbed_official 390:35c2c1cf29cd 1453 #define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
mbed_official 390:35c2c1cf29cd 1454 #define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
mbed_official 390:35c2c1cf29cd 1455 #define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
mbed_official 390:35c2c1cf29cd 1456 #define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
mbed_official 390:35c2c1cf29cd 1457 #define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
mbed_official 390:35c2c1cf29cd 1458 #define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
mbed_official 390:35c2c1cf29cd 1459 #define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
mbed_official 390:35c2c1cf29cd 1460 #define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
mbed_official 390:35c2c1cf29cd 1461 #define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
mbed_official 390:35c2c1cf29cd 1462 #define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
mbed_official 390:35c2c1cf29cd 1463 #define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
mbed_official 390:35c2c1cf29cd 1464 #define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
mbed_official 390:35c2c1cf29cd 1465 #define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
mbed_official 390:35c2c1cf29cd 1466 #define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
mbed_official 390:35c2c1cf29cd 1467 #define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
mbed_official 390:35c2c1cf29cd 1468 #define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
mbed_official 390:35c2c1cf29cd 1469 #define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
mbed_official 390:35c2c1cf29cd 1470 #define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
mbed_official 390:35c2c1cf29cd 1471 #define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
mbed_official 390:35c2c1cf29cd 1472 #define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
mbed_official 390:35c2c1cf29cd 1473 #define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
mbed_official 390:35c2c1cf29cd 1474 #define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
mbed_official 390:35c2c1cf29cd 1475 #define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
mbed_official 390:35c2c1cf29cd 1476 #define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
mbed_official 390:35c2c1cf29cd 1477 #define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
mbed_official 390:35c2c1cf29cd 1478 #define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
mbed_official 390:35c2c1cf29cd 1479 #define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
mbed_official 390:35c2c1cf29cd 1480 #define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
mbed_official 390:35c2c1cf29cd 1481 #define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
mbed_official 390:35c2c1cf29cd 1482 #define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
mbed_official 390:35c2c1cf29cd 1483 #define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
mbed_official 390:35c2c1cf29cd 1484 #define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
mbed_official 390:35c2c1cf29cd 1485 #define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
mbed_official 390:35c2c1cf29cd 1486 #define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
mbed_official 390:35c2c1cf29cd 1487 #define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
mbed_official 390:35c2c1cf29cd 1488 #define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
mbed_official 390:35c2c1cf29cd 1489 #define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
mbed_official 390:35c2c1cf29cd 1490 #define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
mbed_official 390:35c2c1cf29cd 1491 #define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
mbed_official 390:35c2c1cf29cd 1492 #define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
mbed_official 390:35c2c1cf29cd 1493 #define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
mbed_official 390:35c2c1cf29cd 1494 #define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
mbed_official 390:35c2c1cf29cd 1495 #define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
mbed_official 390:35c2c1cf29cd 1496 #define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
mbed_official 390:35c2c1cf29cd 1497 #define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
mbed_official 390:35c2c1cf29cd 1498 #define VDC51GR1_UPDATE VDC51.GR1_UPDATE
mbed_official 390:35c2c1cf29cd 1499 #define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
mbed_official 390:35c2c1cf29cd 1500 #define VDC51GR1_FLM1 VDC51.GR1_FLM1
mbed_official 390:35c2c1cf29cd 1501 #define VDC51GR1_FLM2 VDC51.GR1_FLM2
mbed_official 390:35c2c1cf29cd 1502 #define VDC51GR1_FLM3 VDC51.GR1_FLM3
mbed_official 390:35c2c1cf29cd 1503 #define VDC51GR1_FLM4 VDC51.GR1_FLM4
mbed_official 390:35c2c1cf29cd 1504 #define VDC51GR1_FLM5 VDC51.GR1_FLM5
mbed_official 390:35c2c1cf29cd 1505 #define VDC51GR1_FLM6 VDC51.GR1_FLM6
mbed_official 390:35c2c1cf29cd 1506 #define VDC51GR1_AB1 VDC51.GR1_AB1
mbed_official 390:35c2c1cf29cd 1507 #define VDC51GR1_AB2 VDC51.GR1_AB2
mbed_official 390:35c2c1cf29cd 1508 #define VDC51GR1_AB3 VDC51.GR1_AB3
mbed_official 390:35c2c1cf29cd 1509 #define VDC51GR1_AB4 VDC51.GR1_AB4
mbed_official 390:35c2c1cf29cd 1510 #define VDC51GR1_AB5 VDC51.GR1_AB5
mbed_official 390:35c2c1cf29cd 1511 #define VDC51GR1_AB6 VDC51.GR1_AB6
mbed_official 390:35c2c1cf29cd 1512 #define VDC51GR1_AB7 VDC51.GR1_AB7
mbed_official 390:35c2c1cf29cd 1513 #define VDC51GR1_AB8 VDC51.GR1_AB8
mbed_official 390:35c2c1cf29cd 1514 #define VDC51GR1_AB9 VDC51.GR1_AB9
mbed_official 390:35c2c1cf29cd 1515 #define VDC51GR1_AB10 VDC51.GR1_AB10
mbed_official 390:35c2c1cf29cd 1516 #define VDC51GR1_AB11 VDC51.GR1_AB11
mbed_official 390:35c2c1cf29cd 1517 #define VDC51GR1_BASE VDC51.GR1_BASE
mbed_official 390:35c2c1cf29cd 1518 #define VDC51GR1_CLUT VDC51.GR1_CLUT
mbed_official 390:35c2c1cf29cd 1519 #define VDC51GR1_MON VDC51.GR1_MON
mbed_official 390:35c2c1cf29cd 1520 #define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
mbed_official 390:35c2c1cf29cd 1521 #define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
mbed_official 390:35c2c1cf29cd 1522 #define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
mbed_official 390:35c2c1cf29cd 1523 #define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
mbed_official 390:35c2c1cf29cd 1524 #define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
mbed_official 390:35c2c1cf29cd 1525 #define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
mbed_official 390:35c2c1cf29cd 1526 #define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
mbed_official 390:35c2c1cf29cd 1527 #define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
mbed_official 390:35c2c1cf29cd 1528 #define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
mbed_official 390:35c2c1cf29cd 1529 #define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
mbed_official 390:35c2c1cf29cd 1530 #define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
mbed_official 390:35c2c1cf29cd 1531 #define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
mbed_official 390:35c2c1cf29cd 1532 #define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
mbed_official 390:35c2c1cf29cd 1533 #define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
mbed_official 390:35c2c1cf29cd 1534 #define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
mbed_official 390:35c2c1cf29cd 1535 #define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
mbed_official 390:35c2c1cf29cd 1536 #define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
mbed_official 390:35c2c1cf29cd 1537 #define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
mbed_official 390:35c2c1cf29cd 1538 #define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
mbed_official 390:35c2c1cf29cd 1539 #define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
mbed_official 390:35c2c1cf29cd 1540 #define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
mbed_official 390:35c2c1cf29cd 1541 #define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
mbed_official 390:35c2c1cf29cd 1542 #define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
mbed_official 390:35c2c1cf29cd 1543 #define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
mbed_official 390:35c2c1cf29cd 1544 #define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
mbed_official 390:35c2c1cf29cd 1545 #define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
mbed_official 390:35c2c1cf29cd 1546 #define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
mbed_official 390:35c2c1cf29cd 1547 #define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
mbed_official 390:35c2c1cf29cd 1548 #define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
mbed_official 390:35c2c1cf29cd 1549 #define VDC51GR_VIN_MON VDC51.GR_VIN_MON
mbed_official 390:35c2c1cf29cd 1550 #define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
mbed_official 390:35c2c1cf29cd 1551 #define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
mbed_official 390:35c2c1cf29cd 1552 #define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
mbed_official 390:35c2c1cf29cd 1553 #define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
mbed_official 390:35c2c1cf29cd 1554 #define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
mbed_official 390:35c2c1cf29cd 1555 #define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
mbed_official 390:35c2c1cf29cd 1556 #define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
mbed_official 390:35c2c1cf29cd 1557 #define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
mbed_official 390:35c2c1cf29cd 1558 #define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
mbed_official 390:35c2c1cf29cd 1559 #define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
mbed_official 390:35c2c1cf29cd 1560 #define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
mbed_official 390:35c2c1cf29cd 1561 #define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
mbed_official 390:35c2c1cf29cd 1562 #define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
mbed_official 390:35c2c1cf29cd 1563 #define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
mbed_official 390:35c2c1cf29cd 1564 #define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
mbed_official 390:35c2c1cf29cd 1565 #define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
mbed_official 390:35c2c1cf29cd 1566 #define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
mbed_official 390:35c2c1cf29cd 1567 #define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
mbed_official 390:35c2c1cf29cd 1568 #define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
mbed_official 390:35c2c1cf29cd 1569 #define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
mbed_official 390:35c2c1cf29cd 1570 #define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
mbed_official 390:35c2c1cf29cd 1571 #define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
mbed_official 390:35c2c1cf29cd 1572 #define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
mbed_official 390:35c2c1cf29cd 1573 #define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
mbed_official 390:35c2c1cf29cd 1574 #define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
mbed_official 390:35c2c1cf29cd 1575 #define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
mbed_official 390:35c2c1cf29cd 1576 #define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
mbed_official 390:35c2c1cf29cd 1577 #define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
mbed_official 390:35c2c1cf29cd 1578 #define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
mbed_official 390:35c2c1cf29cd 1579 #define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
mbed_official 390:35c2c1cf29cd 1580 #define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
mbed_official 390:35c2c1cf29cd 1581 #define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
mbed_official 390:35c2c1cf29cd 1582 #define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
mbed_official 390:35c2c1cf29cd 1583 #define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
mbed_official 390:35c2c1cf29cd 1584 #define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
mbed_official 390:35c2c1cf29cd 1585 #define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
mbed_official 390:35c2c1cf29cd 1586 #define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
mbed_official 390:35c2c1cf29cd 1587 #define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
mbed_official 390:35c2c1cf29cd 1588 #define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
mbed_official 390:35c2c1cf29cd 1589 #define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
mbed_official 390:35c2c1cf29cd 1590 #define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
mbed_official 390:35c2c1cf29cd 1591 #define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
mbed_official 390:35c2c1cf29cd 1592 #define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
mbed_official 390:35c2c1cf29cd 1593 #define VDC51GR_OIR_MON VDC51.GR_OIR_MON
mbed_official 390:35c2c1cf29cd 1594 /* <-SEC M1.10.1 */
mbed_official 390:35c2c1cf29cd 1595 /* <-QAC 0639 */
mbed_official 390:35c2c1cf29cd 1596 #endif