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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h@392:2b59412bb664, 2014-11-07 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Nov 07 08:15:08 2014 +0000
- Revision:
- 392:2b59412bb664
- Parent:
- targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/stm32f0xx_hal_dma_ex.h@340:28d1f895c6fe
- Child:
- 441:d2c15dda23c1
Synchronized with git revision eec0be05cd92349bee83c65f9e1302b25b5badf4
Full URL: https://github.com/mbedmicro/mbed/commit/eec0be05cd92349bee83c65f9e1302b25b5badf4/
Targets: STM32F0 - Factorisation of NUCLEO_F030R8/F072RB/F091RC cmsis folders
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal_dma_ex.h |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 340:28d1f895c6fe | 5 | * @version V1.1.0 |
| mbed_official | 340:28d1f895c6fe | 6 | * @date 03-Oct-2014 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief Header file of DMA HAL Extension module. |
| mbed_official | 340:28d1f895c6fe | 8 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 9 | * @attention |
| mbed_official | 340:28d1f895c6fe | 10 | * |
| mbed_official | 340:28d1f895c6fe | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 12 | * |
| mbed_official | 340:28d1f895c6fe | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 22 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 23 | * |
| mbed_official | 340:28d1f895c6fe | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 34 | * |
| mbed_official | 340:28d1f895c6fe | 35 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 36 | */ |
| mbed_official | 340:28d1f895c6fe | 37 | |
| mbed_official | 340:28d1f895c6fe | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 39 | #ifndef __STM32F0xx_HAL_DMA_EX_H |
| mbed_official | 340:28d1f895c6fe | 40 | #define __STM32F0xx_HAL_DMA_EX_H |
| mbed_official | 340:28d1f895c6fe | 41 | |
| mbed_official | 340:28d1f895c6fe | 42 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 43 | extern "C" { |
| mbed_official | 340:28d1f895c6fe | 44 | #endif |
| mbed_official | 340:28d1f895c6fe | 45 | |
| mbed_official | 340:28d1f895c6fe | 46 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 47 | #include "stm32f0xx_hal_def.h" |
| mbed_official | 340:28d1f895c6fe | 48 | |
| mbed_official | 340:28d1f895c6fe | 49 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 50 | * @{ |
| mbed_official | 340:28d1f895c6fe | 51 | */ |
| mbed_official | 340:28d1f895c6fe | 52 | |
| mbed_official | 340:28d1f895c6fe | 53 | /** @addtogroup DMAEx |
| mbed_official | 340:28d1f895c6fe | 54 | * @{ |
| mbed_official | 340:28d1f895c6fe | 55 | */ |
| mbed_official | 340:28d1f895c6fe | 56 | |
| mbed_official | 340:28d1f895c6fe | 57 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 58 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 59 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 60 | /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants |
| mbed_official | 340:28d1f895c6fe | 61 | * @{ |
| mbed_official | 340:28d1f895c6fe | 62 | */ |
| mbed_official | 340:28d1f895c6fe | 63 | #define DMA1_CHANNEL1_RMP 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 64 | #define DMA1_CHANNEL2_RMP 0x10000000 |
| mbed_official | 340:28d1f895c6fe | 65 | #define DMA1_CHANNEL3_RMP 0x20000000 |
| mbed_official | 340:28d1f895c6fe | 66 | #define DMA1_CHANNEL4_RMP 0x30000000 |
| mbed_official | 340:28d1f895c6fe | 67 | #define DMA1_CHANNEL5_RMP 0x40000000 |
| mbed_official | 340:28d1f895c6fe | 68 | #define DMA1_CHANNEL6_RMP 0x50000000 |
| mbed_official | 340:28d1f895c6fe | 69 | #define DMA1_CHANNEL7_RMP 0x60000000 |
| mbed_official | 340:28d1f895c6fe | 70 | #define DMA2_CHANNEL1_RMP 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 71 | #define DMA2_CHANNEL2_RMP 0x10000000 |
| mbed_official | 340:28d1f895c6fe | 72 | #define DMA2_CHANNEL3_RMP 0x20000000 |
| mbed_official | 340:28d1f895c6fe | 73 | #define DMA2_CHANNEL4_RMP 0x30000000 |
| mbed_official | 340:28d1f895c6fe | 74 | #define DMA2_CHANNEL5_RMP 0x40000000 |
| mbed_official | 340:28d1f895c6fe | 75 | |
| mbed_official | 340:28d1f895c6fe | 76 | /****************** DMA1 remap bit field definition********************/ |
| mbed_official | 340:28d1f895c6fe | 77 | /* DMA1 - Channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 78 | #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| mbed_official | 340:28d1f895c6fe | 79 | #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/ |
| mbed_official | 340:28d1f895c6fe | 80 | #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 81 | #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 82 | #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 83 | #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 84 | #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 85 | #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 86 | #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 87 | #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 88 | #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 89 | #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA_RMPCR1_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 90 | /* DMA1 - Channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 91 | #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| mbed_official | 340:28d1f895c6fe | 92 | #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 93 | #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 94 | #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 95 | #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 96 | #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 97 | #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 98 | #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 99 | #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 100 | #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 101 | #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 102 | #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 103 | #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 104 | #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 105 | #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA_RMPCR1_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 106 | /* DMA1 - Channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 107 | #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| mbed_official | 340:28d1f895c6fe | 108 | #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 109 | #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 110 | #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 111 | #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 112 | #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 113 | #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 114 | #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 115 | #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 116 | #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 117 | #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 118 | #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 119 | #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 120 | #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 121 | #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 122 | #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 123 | #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA_RMPCR1_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 124 | /* DMA1 - Channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 125 | #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| mbed_official | 340:28d1f895c6fe | 126 | #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 127 | #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 128 | #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 129 | #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 130 | #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 131 | #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 132 | #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 133 | #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 134 | #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 135 | #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 136 | #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 137 | #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 138 | #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 139 | #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 140 | #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 141 | #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 142 | #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA_RMPCR1_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 143 | /* DMA1 - Channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 144 | #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| mbed_official | 340:28d1f895c6fe | 145 | #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 146 | #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 147 | #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 148 | #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 149 | #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 150 | #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 151 | #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 152 | #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 153 | #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 154 | #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 155 | #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA_RMPCR1_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 156 | /* DMA1 - Channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 157 | #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| mbed_official | 340:28d1f895c6fe | 158 | #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 159 | #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 160 | #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 161 | #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 162 | #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 163 | #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 164 | #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 165 | #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 166 | #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 167 | #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 168 | #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 169 | #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 170 | #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 171 | #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 172 | #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 173 | #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 174 | #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA_RMPCR1_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 175 | /* DMA1 - Channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 176 | #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_DEFAULT) /*!< Default remap position for DMA1 */ |
| mbed_official | 340:28d1f895c6fe | 177 | #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 178 | #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 179 | #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 180 | #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 181 | #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 182 | #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 183 | #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 184 | #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 185 | #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 186 | #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 187 | #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 188 | #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 189 | #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 190 | #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA_RMPCR1_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 191 | |
| mbed_official | 340:28d1f895c6fe | 192 | /****************** DMA2 remap bit field definition********************/ |
| mbed_official | 340:28d1f895c6fe | 193 | /* DMA2 - Channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 194 | #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| mbed_official | 340:28d1f895c6fe | 195 | #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 196 | #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 197 | #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 198 | #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 199 | #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 200 | #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 201 | #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 202 | #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 203 | #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA_RMPCR2_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */ |
| mbed_official | 340:28d1f895c6fe | 204 | /* DMA2 - Channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 205 | #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| mbed_official | 340:28d1f895c6fe | 206 | #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 207 | #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 208 | #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 209 | #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 210 | #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 211 | #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 212 | #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 213 | #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 214 | #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA_RMPCR2_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 215 | /* DMA2 - Channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 216 | #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| mbed_official | 340:28d1f895c6fe | 217 | #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 218 | #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 219 | #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 220 | #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 221 | #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 222 | #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 223 | #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 224 | #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 225 | #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 226 | #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 227 | #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA_RMPCR2_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */ |
| mbed_official | 340:28d1f895c6fe | 228 | /* DMA2 - Channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 229 | #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| mbed_official | 340:28d1f895c6fe | 230 | #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 231 | #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 232 | #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 233 | #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 234 | #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 235 | #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 236 | #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 237 | #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 238 | #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 239 | #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 240 | #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA_RMPCR2_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 241 | /* DMA2 - Channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 242 | #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_DEFAULT) /*!< Default remap position for DMA2 */ |
| mbed_official | 340:28d1f895c6fe | 243 | #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 244 | #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 245 | #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 246 | #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 247 | #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 248 | #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 249 | #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 250 | #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 251 | #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA_RMPCR2_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 252 | |
| mbed_official | 340:28d1f895c6fe | 253 | #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 254 | ((REQUEST) == HAL_DMA1_CH1_ADC) ||\ |
| mbed_official | 340:28d1f895c6fe | 255 | ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 256 | ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 257 | ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 258 | ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 259 | ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 260 | ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 261 | ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 262 | ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 263 | ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 264 | ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 265 | ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 266 | ((REQUEST) == HAL_DMA1_CH2_ADC) ||\ |
| mbed_official | 340:28d1f895c6fe | 267 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 268 | ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 269 | ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 270 | ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 271 | ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 272 | ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 273 | ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 274 | ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 275 | ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 276 | ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 277 | ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 278 | ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 279 | ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 280 | ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 281 | ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 282 | ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 283 | ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 284 | ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 285 | ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 286 | ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\ |
| mbed_official | 340:28d1f895c6fe | 287 | ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\ |
| mbed_official | 340:28d1f895c6fe | 288 | ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 289 | ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 290 | ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 291 | ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 292 | ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 293 | ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 294 | ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 295 | ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 296 | ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 297 | ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 298 | ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 299 | ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 300 | ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\ |
| mbed_official | 340:28d1f895c6fe | 301 | ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 302 | ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 303 | ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\ |
| mbed_official | 340:28d1f895c6fe | 304 | ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 305 | ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\ |
| mbed_official | 340:28d1f895c6fe | 306 | ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 307 | ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 308 | ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 309 | ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 310 | ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 311 | ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 312 | ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 313 | ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 314 | ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 315 | ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 316 | ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 317 | ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 318 | ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 319 | ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\ |
| mbed_official | 340:28d1f895c6fe | 320 | ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 321 | ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 322 | ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 323 | ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 324 | ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 325 | ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 326 | ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 327 | ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 328 | ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 329 | ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 330 | ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 331 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 332 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\ |
| mbed_official | 340:28d1f895c6fe | 333 | ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\ |
| mbed_official | 340:28d1f895c6fe | 334 | ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 335 | ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\ |
| mbed_official | 340:28d1f895c6fe | 336 | ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 337 | ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 338 | ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 339 | ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 340 | ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 341 | ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 342 | ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 343 | ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 344 | ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 345 | ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 346 | ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 347 | ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 348 | ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 349 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\ |
| mbed_official | 340:28d1f895c6fe | 350 | ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\ |
| mbed_official | 340:28d1f895c6fe | 351 | ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 352 | ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 353 | ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 354 | ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 355 | ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 356 | ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 357 | ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 358 | ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 359 | ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 360 | ((REQUEST) == HAL_DMA1_CH7_USART8_TX)) |
| mbed_official | 340:28d1f895c6fe | 361 | |
| mbed_official | 340:28d1f895c6fe | 362 | #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 363 | ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 364 | ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 365 | ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 366 | ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 367 | ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 368 | ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 369 | ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 370 | ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 371 | ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 372 | ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 373 | ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 374 | ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 375 | ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 376 | ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 377 | ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 378 | ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 379 | ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 380 | ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 381 | ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 382 | ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 383 | ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 384 | ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\ |
| mbed_official | 340:28d1f895c6fe | 385 | ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 386 | ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 387 | ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 388 | ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 389 | ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 390 | ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 391 | ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 392 | ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 393 | ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\ |
| mbed_official | 340:28d1f895c6fe | 394 | ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 395 | ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\ |
| mbed_official | 340:28d1f895c6fe | 396 | ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\ |
| mbed_official | 340:28d1f895c6fe | 397 | ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 398 | ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 399 | ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 400 | ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 401 | ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 402 | ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 403 | ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 404 | ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 405 | ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 406 | ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\ |
| mbed_official | 340:28d1f895c6fe | 407 | ((REQUEST) == HAL_DMA2_CH5_ADC) ||\ |
| mbed_official | 340:28d1f895c6fe | 408 | ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 409 | ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 410 | ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 411 | ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 412 | ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 413 | ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 414 | ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\ |
| mbed_official | 340:28d1f895c6fe | 415 | ((REQUEST) == HAL_DMA2_CH5_USART8_TX )) |
| mbed_official | 340:28d1f895c6fe | 416 | /** |
| mbed_official | 340:28d1f895c6fe | 417 | * @} |
| mbed_official | 340:28d1f895c6fe | 418 | */ |
| mbed_official | 340:28d1f895c6fe | 419 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 420 | |
| mbed_official | 340:28d1f895c6fe | 421 | /* Exported macros -----------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 422 | |
| mbed_official | 340:28d1f895c6fe | 423 | /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros |
| mbed_official | 340:28d1f895c6fe | 424 | * @{ |
| mbed_official | 340:28d1f895c6fe | 425 | */ |
| mbed_official | 340:28d1f895c6fe | 426 | /* Interrupt & Flag management */ |
| mbed_official | 340:28d1f895c6fe | 427 | |
| mbed_official | 340:28d1f895c6fe | 428 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
| mbed_official | 340:28d1f895c6fe | 429 | /** |
| mbed_official | 340:28d1f895c6fe | 430 | * @brief Returns the current DMA Channel transfer complete flag. |
| mbed_official | 340:28d1f895c6fe | 431 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 432 | * @retval The specified transfer complete flag index. |
| mbed_official | 340:28d1f895c6fe | 433 | */ |
| mbed_official | 340:28d1f895c6fe | 434 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 435 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| mbed_official | 340:28d1f895c6fe | 436 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| mbed_official | 340:28d1f895c6fe | 437 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| mbed_official | 340:28d1f895c6fe | 438 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| mbed_official | 340:28d1f895c6fe | 439 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| mbed_official | 340:28d1f895c6fe | 440 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| mbed_official | 340:28d1f895c6fe | 441 | DMA_FLAG_TC7) |
| mbed_official | 340:28d1f895c6fe | 442 | |
| mbed_official | 340:28d1f895c6fe | 443 | /** |
| mbed_official | 340:28d1f895c6fe | 444 | * @brief Returns the current DMA Channel half transfer complete flag. |
| mbed_official | 340:28d1f895c6fe | 445 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 446 | * @retval The specified half transfer complete flag index. |
| mbed_official | 340:28d1f895c6fe | 447 | */ |
| mbed_official | 340:28d1f895c6fe | 448 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 340:28d1f895c6fe | 449 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| mbed_official | 340:28d1f895c6fe | 450 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| mbed_official | 340:28d1f895c6fe | 451 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| mbed_official | 340:28d1f895c6fe | 452 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| mbed_official | 340:28d1f895c6fe | 453 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| mbed_official | 340:28d1f895c6fe | 454 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| mbed_official | 340:28d1f895c6fe | 455 | DMA_FLAG_HT7) |
| mbed_official | 340:28d1f895c6fe | 456 | |
| mbed_official | 340:28d1f895c6fe | 457 | /** |
| mbed_official | 340:28d1f895c6fe | 458 | * @brief Returns the current DMA Channel transfer error flag. |
| mbed_official | 340:28d1f895c6fe | 459 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 460 | * @retval The specified transfer error flag index. |
| mbed_official | 340:28d1f895c6fe | 461 | */ |
| mbed_official | 340:28d1f895c6fe | 462 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 340:28d1f895c6fe | 463 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| mbed_official | 340:28d1f895c6fe | 464 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| mbed_official | 340:28d1f895c6fe | 465 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| mbed_official | 340:28d1f895c6fe | 466 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| mbed_official | 340:28d1f895c6fe | 467 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| mbed_official | 340:28d1f895c6fe | 468 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| mbed_official | 340:28d1f895c6fe | 469 | DMA_FLAG_TE7) |
| mbed_official | 340:28d1f895c6fe | 470 | |
| mbed_official | 340:28d1f895c6fe | 471 | /** |
| mbed_official | 340:28d1f895c6fe | 472 | * @brief Get the DMA Channel pending flags. |
| mbed_official | 340:28d1f895c6fe | 473 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 474 | * @param __FLAG__: Get the specified flag. |
| mbed_official | 340:28d1f895c6fe | 475 | * This parameter can be any combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 476 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 477 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 478 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| mbed_official | 340:28d1f895c6fe | 479 | * Where x can be 1_7 to select the DMA Channel flag. |
| mbed_official | 340:28d1f895c6fe | 480 | * @retval The state of FLAG (SET or RESET). |
| mbed_official | 340:28d1f895c6fe | 481 | */ |
| mbed_official | 340:28d1f895c6fe | 482 | |
| mbed_official | 340:28d1f895c6fe | 483 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 484 | |
| mbed_official | 340:28d1f895c6fe | 485 | /** |
| mbed_official | 340:28d1f895c6fe | 486 | * @brief Clears the DMA Channel pending flags. |
| mbed_official | 340:28d1f895c6fe | 487 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 488 | * @param __FLAG__: specifies the flag to clear. |
| mbed_official | 340:28d1f895c6fe | 489 | * This parameter can be any combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 490 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 491 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 492 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| mbed_official | 340:28d1f895c6fe | 493 | * Where x can be 1_7 to select the DMA Channel flag. |
| mbed_official | 340:28d1f895c6fe | 494 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 495 | */ |
| mbed_official | 340:28d1f895c6fe | 496 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 497 | |
| mbed_official | 340:28d1f895c6fe | 498 | #elif defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 499 | /** |
| mbed_official | 340:28d1f895c6fe | 500 | * @brief Returns the current DMA Channel transfer complete flag. |
| mbed_official | 340:28d1f895c6fe | 501 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 502 | * @retval The specified transfer complete flag index. |
| mbed_official | 340:28d1f895c6fe | 503 | */ |
| mbed_official | 340:28d1f895c6fe | 504 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 505 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| mbed_official | 340:28d1f895c6fe | 506 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| mbed_official | 340:28d1f895c6fe | 507 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| mbed_official | 340:28d1f895c6fe | 508 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| mbed_official | 340:28d1f895c6fe | 509 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
| mbed_official | 340:28d1f895c6fe | 510 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
| mbed_official | 340:28d1f895c6fe | 511 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ |
| mbed_official | 340:28d1f895c6fe | 512 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ |
| mbed_official | 340:28d1f895c6fe | 513 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ |
| mbed_official | 340:28d1f895c6fe | 514 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ |
| mbed_official | 340:28d1f895c6fe | 515 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ |
| mbed_official | 340:28d1f895c6fe | 516 | DMA_FLAG_TC5) |
| mbed_official | 340:28d1f895c6fe | 517 | |
| mbed_official | 340:28d1f895c6fe | 518 | /** |
| mbed_official | 340:28d1f895c6fe | 519 | * @brief Returns the current DMA Channel half transfer complete flag. |
| mbed_official | 340:28d1f895c6fe | 520 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 521 | * @retval The specified half transfer complete flag index. |
| mbed_official | 340:28d1f895c6fe | 522 | */ |
| mbed_official | 340:28d1f895c6fe | 523 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 340:28d1f895c6fe | 524 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| mbed_official | 340:28d1f895c6fe | 525 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| mbed_official | 340:28d1f895c6fe | 526 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| mbed_official | 340:28d1f895c6fe | 527 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| mbed_official | 340:28d1f895c6fe | 528 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
| mbed_official | 340:28d1f895c6fe | 529 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
| mbed_official | 340:28d1f895c6fe | 530 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ |
| mbed_official | 340:28d1f895c6fe | 531 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ |
| mbed_official | 340:28d1f895c6fe | 532 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ |
| mbed_official | 340:28d1f895c6fe | 533 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ |
| mbed_official | 340:28d1f895c6fe | 534 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ |
| mbed_official | 340:28d1f895c6fe | 535 | DMA_FLAG_HT5) |
| mbed_official | 340:28d1f895c6fe | 536 | |
| mbed_official | 340:28d1f895c6fe | 537 | /** |
| mbed_official | 340:28d1f895c6fe | 538 | * @brief Returns the current DMA Channel transfer error flag. |
| mbed_official | 340:28d1f895c6fe | 539 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 540 | * @retval The specified transfer error flag index. |
| mbed_official | 340:28d1f895c6fe | 541 | */ |
| mbed_official | 340:28d1f895c6fe | 542 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 340:28d1f895c6fe | 543 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| mbed_official | 340:28d1f895c6fe | 544 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| mbed_official | 340:28d1f895c6fe | 545 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| mbed_official | 340:28d1f895c6fe | 546 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| mbed_official | 340:28d1f895c6fe | 547 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
| mbed_official | 340:28d1f895c6fe | 548 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
| mbed_official | 340:28d1f895c6fe | 549 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ |
| mbed_official | 340:28d1f895c6fe | 550 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ |
| mbed_official | 340:28d1f895c6fe | 551 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ |
| mbed_official | 340:28d1f895c6fe | 552 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ |
| mbed_official | 340:28d1f895c6fe | 553 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ |
| mbed_official | 340:28d1f895c6fe | 554 | DMA_FLAG_TE5) |
| mbed_official | 340:28d1f895c6fe | 555 | |
| mbed_official | 340:28d1f895c6fe | 556 | /** |
| mbed_official | 340:28d1f895c6fe | 557 | * @brief Get the DMA Channel pending flags. |
| mbed_official | 340:28d1f895c6fe | 558 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 559 | * @param __FLAG__: Get the specified flag. |
| mbed_official | 340:28d1f895c6fe | 560 | * This parameter can be any combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 561 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 562 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 563 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| mbed_official | 340:28d1f895c6fe | 564 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| mbed_official | 340:28d1f895c6fe | 565 | * @retval The state of FLAG (SET or RESET). |
| mbed_official | 340:28d1f895c6fe | 566 | */ |
| mbed_official | 340:28d1f895c6fe | 567 | |
| mbed_official | 340:28d1f895c6fe | 568 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
| mbed_official | 340:28d1f895c6fe | 569 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ |
| mbed_official | 340:28d1f895c6fe | 570 | (DMA1->ISR & (__FLAG__))) |
| mbed_official | 340:28d1f895c6fe | 571 | |
| mbed_official | 340:28d1f895c6fe | 572 | /** |
| mbed_official | 340:28d1f895c6fe | 573 | * @brief Clears the DMA Channel pending flags. |
| mbed_official | 340:28d1f895c6fe | 574 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 575 | * @param __FLAG__: specifies the flag to clear. |
| mbed_official | 340:28d1f895c6fe | 576 | * This parameter can be any combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 577 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 578 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 579 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| mbed_official | 340:28d1f895c6fe | 580 | * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag. |
| mbed_official | 340:28d1f895c6fe | 581 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 582 | */ |
| mbed_official | 340:28d1f895c6fe | 583 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| mbed_official | 340:28d1f895c6fe | 584 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ |
| mbed_official | 340:28d1f895c6fe | 585 | (DMA1->IFCR = (__FLAG__))) |
| mbed_official | 340:28d1f895c6fe | 586 | |
| mbed_official | 340:28d1f895c6fe | 587 | #else /* STM32F030x8_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx Product devices */ |
| mbed_official | 340:28d1f895c6fe | 588 | /** |
| mbed_official | 340:28d1f895c6fe | 589 | * @brief Returns the current DMA Channel transfer complete flag. |
| mbed_official | 340:28d1f895c6fe | 590 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 591 | * @retval The specified transfer complete flag index. |
| mbed_official | 340:28d1f895c6fe | 592 | */ |
| mbed_official | 340:28d1f895c6fe | 593 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
| mbed_official | 340:28d1f895c6fe | 594 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
| mbed_official | 340:28d1f895c6fe | 595 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
| mbed_official | 340:28d1f895c6fe | 596 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
| mbed_official | 340:28d1f895c6fe | 597 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
| mbed_official | 340:28d1f895c6fe | 598 | DMA_FLAG_TC5) |
| mbed_official | 340:28d1f895c6fe | 599 | |
| mbed_official | 340:28d1f895c6fe | 600 | /** |
| mbed_official | 340:28d1f895c6fe | 601 | * @brief Returns the current DMA Channel half transfer complete flag. |
| mbed_official | 340:28d1f895c6fe | 602 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 603 | * @retval The specified half transfer complete flag index. |
| mbed_official | 340:28d1f895c6fe | 604 | */ |
| mbed_official | 340:28d1f895c6fe | 605 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 340:28d1f895c6fe | 606 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
| mbed_official | 340:28d1f895c6fe | 607 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
| mbed_official | 340:28d1f895c6fe | 608 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
| mbed_official | 340:28d1f895c6fe | 609 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
| mbed_official | 340:28d1f895c6fe | 610 | DMA_FLAG_HT5) |
| mbed_official | 340:28d1f895c6fe | 611 | |
| mbed_official | 340:28d1f895c6fe | 612 | /** |
| mbed_official | 340:28d1f895c6fe | 613 | * @brief Returns the current DMA Channel transfer error flag. |
| mbed_official | 340:28d1f895c6fe | 614 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 615 | * @retval The specified transfer error flag index. |
| mbed_official | 340:28d1f895c6fe | 616 | */ |
| mbed_official | 340:28d1f895c6fe | 617 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
| mbed_official | 340:28d1f895c6fe | 618 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
| mbed_official | 340:28d1f895c6fe | 619 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
| mbed_official | 340:28d1f895c6fe | 620 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
| mbed_official | 340:28d1f895c6fe | 621 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
| mbed_official | 340:28d1f895c6fe | 622 | DMA_FLAG_TE5) |
| mbed_official | 340:28d1f895c6fe | 623 | |
| mbed_official | 340:28d1f895c6fe | 624 | /** |
| mbed_official | 340:28d1f895c6fe | 625 | * @brief Get the DMA Channel pending flags. |
| mbed_official | 340:28d1f895c6fe | 626 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 627 | * @param __FLAG__: Get the specified flag. |
| mbed_official | 340:28d1f895c6fe | 628 | * This parameter can be any combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 629 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 630 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 631 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| mbed_official | 340:28d1f895c6fe | 632 | * Where x can be 1_5 to select the DMA Channel flag. |
| mbed_official | 340:28d1f895c6fe | 633 | * @retval The state of FLAG (SET or RESET). |
| mbed_official | 340:28d1f895c6fe | 634 | */ |
| mbed_official | 340:28d1f895c6fe | 635 | |
| mbed_official | 340:28d1f895c6fe | 636 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 637 | |
| mbed_official | 340:28d1f895c6fe | 638 | /** |
| mbed_official | 340:28d1f895c6fe | 639 | * @brief Clears the DMA Channel pending flags. |
| mbed_official | 340:28d1f895c6fe | 640 | * @param __HANDLE__: DMA handle |
| mbed_official | 340:28d1f895c6fe | 641 | * @param __FLAG__: specifies the flag to clear. |
| mbed_official | 340:28d1f895c6fe | 642 | * This parameter can be any combination of the following values: |
| mbed_official | 340:28d1f895c6fe | 643 | * @arg DMA_FLAG_TCIFx: Transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 644 | * @arg DMA_FLAG_HTIFx: Half transfer complete flag |
| mbed_official | 340:28d1f895c6fe | 645 | * @arg DMA_FLAG_TEIFx: Transfer error flag |
| mbed_official | 340:28d1f895c6fe | 646 | * Where x can be 1_5 to select the DMA Channel flag. |
| mbed_official | 340:28d1f895c6fe | 647 | * @retval None |
| mbed_official | 340:28d1f895c6fe | 648 | */ |
| mbed_official | 340:28d1f895c6fe | 649 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
| mbed_official | 340:28d1f895c6fe | 650 | |
| mbed_official | 340:28d1f895c6fe | 651 | #endif |
| mbed_official | 340:28d1f895c6fe | 652 | |
| mbed_official | 340:28d1f895c6fe | 653 | |
| mbed_official | 340:28d1f895c6fe | 654 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 655 | #define __HAL_DMA1_REMAP(__REQUEST__) \ |
| mbed_official | 340:28d1f895c6fe | 656 | do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \ |
| mbed_official | 340:28d1f895c6fe | 657 | DMA1->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ |
| mbed_official | 340:28d1f895c6fe | 658 | DMA1->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ |
| mbed_official | 340:28d1f895c6fe | 659 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 660 | |
| mbed_official | 340:28d1f895c6fe | 661 | #define __HAL_DMA2_REMAP(__REQUEST__) \ |
| mbed_official | 340:28d1f895c6fe | 662 | do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \ |
| mbed_official | 340:28d1f895c6fe | 663 | DMA2->RMPCR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \ |
| mbed_official | 340:28d1f895c6fe | 664 | DMA2->RMPCR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \ |
| mbed_official | 340:28d1f895c6fe | 665 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 666 | |
| mbed_official | 340:28d1f895c6fe | 667 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 668 | |
| mbed_official | 340:28d1f895c6fe | 669 | /** |
| mbed_official | 340:28d1f895c6fe | 670 | * @} |
| mbed_official | 340:28d1f895c6fe | 671 | */ |
| mbed_official | 340:28d1f895c6fe | 672 | |
| mbed_official | 340:28d1f895c6fe | 673 | /** |
| mbed_official | 340:28d1f895c6fe | 674 | * @} |
| mbed_official | 340:28d1f895c6fe | 675 | */ |
| mbed_official | 340:28d1f895c6fe | 676 | |
| mbed_official | 340:28d1f895c6fe | 677 | /** |
| mbed_official | 340:28d1f895c6fe | 678 | * @} |
| mbed_official | 340:28d1f895c6fe | 679 | */ |
| mbed_official | 340:28d1f895c6fe | 680 | |
| mbed_official | 340:28d1f895c6fe | 681 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 682 | } |
| mbed_official | 340:28d1f895c6fe | 683 | #endif |
| mbed_official | 340:28d1f895c6fe | 684 | |
| mbed_official | 340:28d1f895c6fe | 685 | #endif /* __STM32F0xx_HAL_DMA_EX_H */ |
| mbed_official | 340:28d1f895c6fe | 686 | |
| mbed_official | 340:28d1f895c6fe | 687 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
