mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c@392:2b59412bb664, 2014-11-07 (annotated)

Committer:
mbed_official
Date:
Fri Nov 07 08:15:08 2014 +0000
Revision:
392:2b59412bb664
Child:
441:d2c15dda23c1
Synchronized with git revision eec0be05cd92349bee83c65f9e1302b25b5badf4



Full URL: https://github.com/mbedmicro/mbed/commit/eec0be05cd92349bee83c65f9e1302b25b5badf4/



Targets: STM32F0 - Factorisation of NUCLEO_F030R8/F072RB/F091RC cmsis folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 392:2b59412bb664 1 /**
mbed_official 392:2b59412bb664 2 ******************************************************************************
mbed_official 392:2b59412bb664 3 * @file system_stm32f0xx.c
mbed_official 392:2b59412bb664 4 * @author MCD Application Team
mbed_official 392:2b59412bb664 5 * @version V2.1.0
mbed_official 392:2b59412bb664 6 * @date 03-Oct-2014
mbed_official 392:2b59412bb664 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official 392:2b59412bb664 8 *
mbed_official 392:2b59412bb664 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 392:2b59412bb664 10 * user application:
mbed_official 392:2b59412bb664 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 392:2b59412bb664 12 * before branch to main program. This call is made inside
mbed_official 392:2b59412bb664 13 * the "startup_stm32f0xx.s" file.
mbed_official 392:2b59412bb664 14 *
mbed_official 392:2b59412bb664 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 392:2b59412bb664 16 * by the user application to setup the SysTick
mbed_official 392:2b59412bb664 17 * timer or configure other parameters.
mbed_official 392:2b59412bb664 18 *
mbed_official 392:2b59412bb664 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 392:2b59412bb664 20 * be called whenever the core clock is changed
mbed_official 392:2b59412bb664 21 * during program execution.
mbed_official 392:2b59412bb664 22 *
mbed_official 392:2b59412bb664 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 392:2b59412bb664 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official 392:2b59412bb664 25 * configure the system clock before to branch to main program.
mbed_official 392:2b59412bb664 26 *
mbed_official 392:2b59412bb664 27 * 3. This file configures the system clock as follows:
mbed_official 392:2b59412bb664 28 *=============================================================================
mbed_official 392:2b59412bb664 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 392:2b59412bb664 30 * | (external 8 MHz clock) | (internal 48 MHz)
mbed_official 392:2b59412bb664 31 * | 2- PLL_HSE_XTAL |
mbed_official 392:2b59412bb664 32 * | (external 8 MHz xtal) |
mbed_official 392:2b59412bb664 33 *-----------------------------------------------------------------------------
mbed_official 392:2b59412bb664 34 * SYSCLK(MHz) | 48 | 48
mbed_official 392:2b59412bb664 35 *-----------------------------------------------------------------------------
mbed_official 392:2b59412bb664 36 * AHBCLK (MHz) | 48 | 48
mbed_official 392:2b59412bb664 37 *-----------------------------------------------------------------------------
mbed_official 392:2b59412bb664 38 * APB1CLK (MHz) | 48 | 48
mbed_official 392:2b59412bb664 39 *-----------------------------------------------------------------------------
mbed_official 392:2b59412bb664 40 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 392:2b59412bb664 41 *=============================================================================
mbed_official 392:2b59412bb664 42 ******************************************************************************
mbed_official 392:2b59412bb664 43 * @attention
mbed_official 392:2b59412bb664 44 *
mbed_official 392:2b59412bb664 45 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 392:2b59412bb664 46 *
mbed_official 392:2b59412bb664 47 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 392:2b59412bb664 48 * are permitted provided that the following conditions are met:
mbed_official 392:2b59412bb664 49 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 392:2b59412bb664 50 * this list of conditions and the following disclaimer.
mbed_official 392:2b59412bb664 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 392:2b59412bb664 52 * this list of conditions and the following disclaimer in the documentation
mbed_official 392:2b59412bb664 53 * and/or other materials provided with the distribution.
mbed_official 392:2b59412bb664 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 392:2b59412bb664 55 * may be used to endorse or promote products derived from this software
mbed_official 392:2b59412bb664 56 * without specific prior written permission.
mbed_official 392:2b59412bb664 57 *
mbed_official 392:2b59412bb664 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 392:2b59412bb664 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 392:2b59412bb664 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 392:2b59412bb664 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 392:2b59412bb664 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 392:2b59412bb664 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 392:2b59412bb664 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 392:2b59412bb664 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 392:2b59412bb664 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 392:2b59412bb664 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 392:2b59412bb664 68 *
mbed_official 392:2b59412bb664 69 ******************************************************************************
mbed_official 392:2b59412bb664 70 */
mbed_official 392:2b59412bb664 71
mbed_official 392:2b59412bb664 72 /** @addtogroup CMSIS
mbed_official 392:2b59412bb664 73 * @{
mbed_official 392:2b59412bb664 74 */
mbed_official 392:2b59412bb664 75
mbed_official 392:2b59412bb664 76 /** @addtogroup stm32f0xx_system
mbed_official 392:2b59412bb664 77 * @{
mbed_official 392:2b59412bb664 78 */
mbed_official 392:2b59412bb664 79
mbed_official 392:2b59412bb664 80 /** @addtogroup STM32F0xx_System_Private_Includes
mbed_official 392:2b59412bb664 81 * @{
mbed_official 392:2b59412bb664 82 */
mbed_official 392:2b59412bb664 83
mbed_official 392:2b59412bb664 84 #include "stm32f0xx.h"
mbed_official 392:2b59412bb664 85
mbed_official 392:2b59412bb664 86 /**
mbed_official 392:2b59412bb664 87 * @}
mbed_official 392:2b59412bb664 88 */
mbed_official 392:2b59412bb664 89
mbed_official 392:2b59412bb664 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official 392:2b59412bb664 91 * @{
mbed_official 392:2b59412bb664 92 */
mbed_official 392:2b59412bb664 93
mbed_official 392:2b59412bb664 94 /**
mbed_official 392:2b59412bb664 95 * @}
mbed_official 392:2b59412bb664 96 */
mbed_official 392:2b59412bb664 97
mbed_official 392:2b59412bb664 98 /** @addtogroup STM32F0xx_System_Private_Defines
mbed_official 392:2b59412bb664 99 * @{
mbed_official 392:2b59412bb664 100 */
mbed_official 392:2b59412bb664 101 #if !defined (HSE_VALUE)
mbed_official 392:2b59412bb664 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 392:2b59412bb664 103 This value can be provided and adapted by the user application. */
mbed_official 392:2b59412bb664 104 #endif /* HSE_VALUE */
mbed_official 392:2b59412bb664 105
mbed_official 392:2b59412bb664 106 #if !defined (HSI_VALUE)
mbed_official 392:2b59412bb664 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 392:2b59412bb664 108 This value can be provided and adapted by the user application. */
mbed_official 392:2b59412bb664 109 #endif /* HSI_VALUE */
mbed_official 392:2b59412bb664 110 /**
mbed_official 392:2b59412bb664 111 * @}
mbed_official 392:2b59412bb664 112 */
mbed_official 392:2b59412bb664 113
mbed_official 392:2b59412bb664 114 /** @addtogroup STM32F0xx_System_Private_Macros
mbed_official 392:2b59412bb664 115 * @{
mbed_official 392:2b59412bb664 116 */
mbed_official 392:2b59412bb664 117
mbed_official 392:2b59412bb664 118 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 392:2b59412bb664 119 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 392:2b59412bb664 120 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 392:2b59412bb664 121
mbed_official 392:2b59412bb664 122 /**
mbed_official 392:2b59412bb664 123 * @}
mbed_official 392:2b59412bb664 124 */
mbed_official 392:2b59412bb664 125
mbed_official 392:2b59412bb664 126 /** @addtogroup STM32F0xx_System_Private_Variables
mbed_official 392:2b59412bb664 127 * @{
mbed_official 392:2b59412bb664 128 */
mbed_official 392:2b59412bb664 129 /* This variable is updated in three ways:
mbed_official 392:2b59412bb664 130 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 392:2b59412bb664 131 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 392:2b59412bb664 132 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 392:2b59412bb664 133 Note: If you use this function to configure the system clock there is no need to
mbed_official 392:2b59412bb664 134 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 392:2b59412bb664 135 updated automatically.
mbed_official 392:2b59412bb664 136 */
mbed_official 392:2b59412bb664 137 uint32_t SystemCoreClock = 48000000;
mbed_official 392:2b59412bb664 138 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 392:2b59412bb664 139
mbed_official 392:2b59412bb664 140 /**
mbed_official 392:2b59412bb664 141 * @}
mbed_official 392:2b59412bb664 142 */
mbed_official 392:2b59412bb664 143
mbed_official 392:2b59412bb664 144 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official 392:2b59412bb664 145 * @{
mbed_official 392:2b59412bb664 146 */
mbed_official 392:2b59412bb664 147
mbed_official 392:2b59412bb664 148 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 392:2b59412bb664 149 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 392:2b59412bb664 150 #endif
mbed_official 392:2b59412bb664 151
mbed_official 392:2b59412bb664 152 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 392:2b59412bb664 153
mbed_official 392:2b59412bb664 154 /**
mbed_official 392:2b59412bb664 155 * @}
mbed_official 392:2b59412bb664 156 */
mbed_official 392:2b59412bb664 157
mbed_official 392:2b59412bb664 158 /** @addtogroup STM32F0xx_System_Private_Functions
mbed_official 392:2b59412bb664 159 * @{
mbed_official 392:2b59412bb664 160 */
mbed_official 392:2b59412bb664 161
mbed_official 392:2b59412bb664 162 /**
mbed_official 392:2b59412bb664 163 * @brief Setup the microcontroller system.
mbed_official 392:2b59412bb664 164 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
mbed_official 392:2b59412bb664 165 * @param None
mbed_official 392:2b59412bb664 166 * @retval None
mbed_official 392:2b59412bb664 167 */
mbed_official 392:2b59412bb664 168 void SystemInit(void)
mbed_official 392:2b59412bb664 169 {
mbed_official 392:2b59412bb664 170 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 392:2b59412bb664 171 /* Set HSION bit */
mbed_official 392:2b59412bb664 172 RCC->CR |= (uint32_t)0x00000001;
mbed_official 392:2b59412bb664 173
mbed_official 392:2b59412bb664 174 #if defined (STM32F051x8) || defined (STM32F058x8)
mbed_official 392:2b59412bb664 175 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official 392:2b59412bb664 176 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 392:2b59412bb664 177 #else
mbed_official 392:2b59412bb664 178 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official 392:2b59412bb664 179 RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official 392:2b59412bb664 180 #endif /* STM32F051x8 or STM32F058x8 */
mbed_official 392:2b59412bb664 181
mbed_official 392:2b59412bb664 182 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 392:2b59412bb664 183 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 392:2b59412bb664 184
mbed_official 392:2b59412bb664 185 /* Reset HSEBYP bit */
mbed_official 392:2b59412bb664 186 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 392:2b59412bb664 187
mbed_official 392:2b59412bb664 188 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 392:2b59412bb664 189 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 392:2b59412bb664 190
mbed_official 392:2b59412bb664 191 /* Reset PREDIV[3:0] bits */
mbed_official 392:2b59412bb664 192 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 392:2b59412bb664 193
mbed_official 392:2b59412bb664 194 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
mbed_official 392:2b59412bb664 195 /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 392:2b59412bb664 196 RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
mbed_official 392:2b59412bb664 197 #elif defined (STM32F091xC) || defined (STM32F098xx)
mbed_official 392:2b59412bb664 198 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
mbed_official 392:2b59412bb664 199 RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
mbed_official 392:2b59412bb664 200 #else
mbed_official 392:2b59412bb664 201 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 392:2b59412bb664 202 RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
mbed_official 392:2b59412bb664 203 #endif
mbed_official 392:2b59412bb664 204
mbed_official 392:2b59412bb664 205 /* Reset HSI14 bit */
mbed_official 392:2b59412bb664 206 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 392:2b59412bb664 207
mbed_official 392:2b59412bb664 208 /* Disable all interrupts */
mbed_official 392:2b59412bb664 209 RCC->CIR = 0x00000000;
mbed_official 392:2b59412bb664 210
mbed_official 392:2b59412bb664 211 /* Configure the Cube driver */
mbed_official 392:2b59412bb664 212 HAL_Init();
mbed_official 392:2b59412bb664 213
mbed_official 392:2b59412bb664 214 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 392:2b59412bb664 215 AHB/APBx prescalers and Flash settings */
mbed_official 392:2b59412bb664 216 SetSysClock();
mbed_official 392:2b59412bb664 217 }
mbed_official 392:2b59412bb664 218
mbed_official 392:2b59412bb664 219 /**
mbed_official 392:2b59412bb664 220 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 392:2b59412bb664 221 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 392:2b59412bb664 222 * be used by the user application to setup the SysTick timer or configure
mbed_official 392:2b59412bb664 223 * other parameters.
mbed_official 392:2b59412bb664 224 *
mbed_official 392:2b59412bb664 225 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 392:2b59412bb664 226 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 392:2b59412bb664 227 * based on this variable will be incorrect.
mbed_official 392:2b59412bb664 228 *
mbed_official 392:2b59412bb664 229 * @note - The system frequency computed by this function is not the real
mbed_official 392:2b59412bb664 230 * frequency in the chip. It is calculated based on the predefined
mbed_official 392:2b59412bb664 231 * constant and the selected clock source:
mbed_official 392:2b59412bb664 232 *
mbed_official 392:2b59412bb664 233 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 392:2b59412bb664 234 *
mbed_official 392:2b59412bb664 235 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 392:2b59412bb664 236 *
mbed_official 392:2b59412bb664 237 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 392:2b59412bb664 238 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 392:2b59412bb664 239 *
mbed_official 392:2b59412bb664 240 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 392:2b59412bb664 241 * 8 MHz) but the real value may vary depending on the variations
mbed_official 392:2b59412bb664 242 * in voltage and temperature.
mbed_official 392:2b59412bb664 243 *
mbed_official 392:2b59412bb664 244 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 392:2b59412bb664 245 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 392:2b59412bb664 246 * frequency of the crystal used. Otherwise, this function may
mbed_official 392:2b59412bb664 247 * have wrong result.
mbed_official 392:2b59412bb664 248 *
mbed_official 392:2b59412bb664 249 * - The result of this function could be not correct when using fractional
mbed_official 392:2b59412bb664 250 * value for HSE crystal.
mbed_official 392:2b59412bb664 251 *
mbed_official 392:2b59412bb664 252 * @param None
mbed_official 392:2b59412bb664 253 * @retval None
mbed_official 392:2b59412bb664 254 */
mbed_official 392:2b59412bb664 255 void SystemCoreClockUpdate (void)
mbed_official 392:2b59412bb664 256 {
mbed_official 392:2b59412bb664 257 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 392:2b59412bb664 258
mbed_official 392:2b59412bb664 259 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 392:2b59412bb664 260 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 392:2b59412bb664 261
mbed_official 392:2b59412bb664 262 switch (tmp)
mbed_official 392:2b59412bb664 263 {
mbed_official 392:2b59412bb664 264 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 392:2b59412bb664 265 SystemCoreClock = HSI_VALUE;
mbed_official 392:2b59412bb664 266 break;
mbed_official 392:2b59412bb664 267 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 392:2b59412bb664 268 SystemCoreClock = HSE_VALUE;
mbed_official 392:2b59412bb664 269 break;
mbed_official 392:2b59412bb664 270 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 392:2b59412bb664 271 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 392:2b59412bb664 272 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 392:2b59412bb664 273 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 392:2b59412bb664 274 pllmull = ( pllmull >> 18) + 2;
mbed_official 392:2b59412bb664 275 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 392:2b59412bb664 276
mbed_official 392:2b59412bb664 277 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official 392:2b59412bb664 278 {
mbed_official 392:2b59412bb664 279 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
mbed_official 392:2b59412bb664 280 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
mbed_official 392:2b59412bb664 281 }
mbed_official 392:2b59412bb664 282 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
mbed_official 392:2b59412bb664 283 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
mbed_official 392:2b59412bb664 284 {
mbed_official 392:2b59412bb664 285 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
mbed_official 392:2b59412bb664 286 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
mbed_official 392:2b59412bb664 287 }
mbed_official 392:2b59412bb664 288 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
mbed_official 392:2b59412bb664 289 else
mbed_official 392:2b59412bb664 290 {
mbed_official 392:2b59412bb664 291 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
mbed_official 392:2b59412bb664 292 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
mbed_official 392:2b59412bb664 293 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
mbed_official 392:2b59412bb664 294 #else
mbed_official 392:2b59412bb664 295 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
mbed_official 392:2b59412bb664 296 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 392:2b59412bb664 297 #endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
mbed_official 392:2b59412bb664 298 }
mbed_official 392:2b59412bb664 299 break;
mbed_official 392:2b59412bb664 300 default: /* HSI used as system clock */
mbed_official 392:2b59412bb664 301 SystemCoreClock = HSI_VALUE;
mbed_official 392:2b59412bb664 302 break;
mbed_official 392:2b59412bb664 303 }
mbed_official 392:2b59412bb664 304 /* Compute HCLK clock frequency ----------------*/
mbed_official 392:2b59412bb664 305 /* Get HCLK prescaler */
mbed_official 392:2b59412bb664 306 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 392:2b59412bb664 307 /* HCLK clock frequency */
mbed_official 392:2b59412bb664 308 SystemCoreClock >>= tmp;
mbed_official 392:2b59412bb664 309 }
mbed_official 392:2b59412bb664 310
mbed_official 392:2b59412bb664 311 /**
mbed_official 392:2b59412bb664 312 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 392:2b59412bb664 313 * AHB/APBx prescalers and Flash settings
mbed_official 392:2b59412bb664 314 * @note This function should be called only once the RCC clock configuration
mbed_official 392:2b59412bb664 315 * is reset to the default reset state (done in SystemInit() function).
mbed_official 392:2b59412bb664 316 * @param None
mbed_official 392:2b59412bb664 317 * @retval None
mbed_official 392:2b59412bb664 318 */
mbed_official 392:2b59412bb664 319 void SetSysClock(void)
mbed_official 392:2b59412bb664 320 {
mbed_official 392:2b59412bb664 321 /* 1- Try to start with HSE and external clock */
mbed_official 392:2b59412bb664 322 #if USE_PLL_HSE_EXTC != 0
mbed_official 392:2b59412bb664 323 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 392:2b59412bb664 324 #endif
mbed_official 392:2b59412bb664 325 {
mbed_official 392:2b59412bb664 326 /* 2- If fail try to start with HSE and external xtal */
mbed_official 392:2b59412bb664 327 #if USE_PLL_HSE_XTAL != 0
mbed_official 392:2b59412bb664 328 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 392:2b59412bb664 329 #endif
mbed_official 392:2b59412bb664 330 {
mbed_official 392:2b59412bb664 331 /* 3- If fail start with HSI clock */
mbed_official 392:2b59412bb664 332 if (SetSysClock_PLL_HSI() == 0)
mbed_official 392:2b59412bb664 333 {
mbed_official 392:2b59412bb664 334 while(1)
mbed_official 392:2b59412bb664 335 {
mbed_official 392:2b59412bb664 336 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 392:2b59412bb664 337 }
mbed_official 392:2b59412bb664 338 }
mbed_official 392:2b59412bb664 339 }
mbed_official 392:2b59412bb664 340 }
mbed_official 392:2b59412bb664 341
mbed_official 392:2b59412bb664 342 // Output clock on MCO pin(PA8) for debugging purpose
mbed_official 392:2b59412bb664 343 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
mbed_official 392:2b59412bb664 344 }
mbed_official 392:2b59412bb664 345
mbed_official 392:2b59412bb664 346 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 392:2b59412bb664 347 /******************************************************************************/
mbed_official 392:2b59412bb664 348 /* PLL (clocked by HSE) used as System clock source */
mbed_official 392:2b59412bb664 349 /******************************************************************************/
mbed_official 392:2b59412bb664 350 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 392:2b59412bb664 351 {
mbed_official 392:2b59412bb664 352 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 392:2b59412bb664 353 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 392:2b59412bb664 354
mbed_official 392:2b59412bb664 355 // Select HSE oscillator as PLL source
mbed_official 392:2b59412bb664 356 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
mbed_official 392:2b59412bb664 357 if (bypass == 0) {
mbed_official 392:2b59412bb664 358 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official 392:2b59412bb664 359 } else {
mbed_official 392:2b59412bb664 360 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
mbed_official 392:2b59412bb664 361 }
mbed_official 392:2b59412bb664 362 RCC_OscInitStruct.HSI48State = 0; // not used
mbed_official 392:2b59412bb664 363 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 392:2b59412bb664 364 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 392:2b59412bb664 365 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official 392:2b59412bb664 366 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 392:2b59412bb664 367 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 392:2b59412bb664 368 return 0; // FAIL
mbed_official 392:2b59412bb664 369 }
mbed_official 392:2b59412bb664 370
mbed_official 392:2b59412bb664 371 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 392:2b59412bb664 372 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 392:2b59412bb664 373 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 392:2b59412bb664 374 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 392:2b59412bb664 375 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 392:2b59412bb664 376 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 392:2b59412bb664 377 return 0; // FAIL
mbed_official 392:2b59412bb664 378 }
mbed_official 392:2b59412bb664 379
mbed_official 392:2b59412bb664 380 return 1; // OK
mbed_official 392:2b59412bb664 381 }
mbed_official 392:2b59412bb664 382 #endif
mbed_official 392:2b59412bb664 383
mbed_official 392:2b59412bb664 384 /******************************************************************************/
mbed_official 392:2b59412bb664 385 /* PLL (clocked by HSI) used as System clock source */
mbed_official 392:2b59412bb664 386 /******************************************************************************/
mbed_official 392:2b59412bb664 387 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 392:2b59412bb664 388 {
mbed_official 392:2b59412bb664 389 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 392:2b59412bb664 390 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 392:2b59412bb664 391
mbed_official 392:2b59412bb664 392 // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
mbed_official 392:2b59412bb664 393 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
mbed_official 392:2b59412bb664 394 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 392:2b59412bb664 395 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 392:2b59412bb664 396 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
mbed_official 392:2b59412bb664 397 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
mbed_official 392:2b59412bb664 398 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 392:2b59412bb664 399 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 392:2b59412bb664 400 return 0; // FAIL
mbed_official 392:2b59412bb664 401 }
mbed_official 392:2b59412bb664 402
mbed_official 392:2b59412bb664 403 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 392:2b59412bb664 404 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 392:2b59412bb664 405 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 392:2b59412bb664 406 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 392:2b59412bb664 407 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 392:2b59412bb664 408 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 392:2b59412bb664 409 return 0; // FAIL
mbed_official 392:2b59412bb664 410 }
mbed_official 392:2b59412bb664 411
mbed_official 392:2b59412bb664 412 return 1; // OK
mbed_official 392:2b59412bb664 413 }
mbed_official 392:2b59412bb664 414
mbed_official 392:2b59412bb664 415 /* Used for the different timeouts in the HAL */
mbed_official 392:2b59412bb664 416 void SysTick_Handler(void)
mbed_official 392:2b59412bb664 417 {
mbed_official 392:2b59412bb664 418 HAL_IncTick();
mbed_official 392:2b59412bb664 419 }
mbed_official 392:2b59412bb664 420
mbed_official 392:2b59412bb664 421 /**
mbed_official 392:2b59412bb664 422 * @}
mbed_official 392:2b59412bb664 423 */
mbed_official 392:2b59412bb664 424
mbed_official 392:2b59412bb664 425 /**
mbed_official 392:2b59412bb664 426 * @}
mbed_official 392:2b59412bb664 427 */
mbed_official 392:2b59412bb664 428
mbed_official 392:2b59412bb664 429 /**
mbed_official 392:2b59412bb664 430 * @}
mbed_official 392:2b59412bb664 431 */
mbed_official 392:2b59412bb664 432
mbed_official 392:2b59412bb664 433 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 392:2b59412bb664 434