mbed library sources
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Superseded
This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.
Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.
If you are looking for a stable and tested release, please import one of the official mbed library releases:
Import librarymbed
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.S@577:15494b56c2f3, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 08:15:11 2015 +0100
- Revision:
- 577:15494b56c2f3
- Parent:
- targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s@390:35c2c1cf29cd
Synchronized with git revision 7766e75dd858812cd79aedb3080349715f55dd56
Full URL: https://github.com/mbedmicro/mbed/commit/7766e75dd858812cd79aedb3080349715f55dd56/
GCC asm updates
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 390:35c2c1cf29cd | 1 | ;/***************************************************************************** |
mbed_official | 390:35c2c1cf29cd | 2 | ; * @file: startup_MBRZA1H.s |
mbed_official | 390:35c2c1cf29cd | 3 | ; * @purpose: CMSIS Cortex-A9 Core Device Startup File |
mbed_official | 390:35c2c1cf29cd | 4 | ; * for the NXP MBRZA1H Device Series |
mbed_official | 390:35c2c1cf29cd | 5 | ; * @version: V1.02, modified for mbed |
mbed_official | 390:35c2c1cf29cd | 6 | ; * @date: 27. July 2009, modified 3rd Aug 2009 |
mbed_official | 390:35c2c1cf29cd | 7 | ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
mbed_official | 390:35c2c1cf29cd | 8 | ; * |
mbed_official | 390:35c2c1cf29cd | 9 | ; * Copyright (C) 2009 ARM Limited. All rights reserved. |
mbed_official | 390:35c2c1cf29cd | 10 | ; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 |
mbed_official | 390:35c2c1cf29cd | 11 | ; * processor based microcontrollers. This file can be freely distributed |
mbed_official | 390:35c2c1cf29cd | 12 | ; * within development tools that are supporting such ARM based processors. |
mbed_official | 390:35c2c1cf29cd | 13 | ; * |
mbed_official | 390:35c2c1cf29cd | 14 | ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
mbed_official | 390:35c2c1cf29cd | 15 | ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
mbed_official | 390:35c2c1cf29cd | 16 | ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
mbed_official | 390:35c2c1cf29cd | 17 | ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
mbed_official | 390:35c2c1cf29cd | 18 | ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
mbed_official | 390:35c2c1cf29cd | 19 | ; * |
mbed_official | 390:35c2c1cf29cd | 20 | ; *****************************************************************************/ |
mbed_official | 390:35c2c1cf29cd | 21 | |
mbed_official | 390:35c2c1cf29cd | 22 | GICI_BASE EQU 0xe8202000 |
mbed_official | 390:35c2c1cf29cd | 23 | ICCIAR_OFFSET EQU 0x0000000C |
mbed_official | 390:35c2c1cf29cd | 24 | ICCEOIR_OFFSET EQU 0x00000010 |
mbed_official | 390:35c2c1cf29cd | 25 | ICCHPIR_OFFSET EQU 0x00000018 |
mbed_official | 390:35c2c1cf29cd | 26 | |
mbed_official | 390:35c2c1cf29cd | 27 | GICD_BASE EQU 0xe8201000 |
mbed_official | 390:35c2c1cf29cd | 28 | ICDISER0_OFFSET EQU 0x00000100 |
mbed_official | 390:35c2c1cf29cd | 29 | ICDICER0_OFFSET EQU 0x00000180 |
mbed_official | 390:35c2c1cf29cd | 30 | ICDISPR0_OFFSET EQU 0x00000200 |
mbed_official | 390:35c2c1cf29cd | 31 | ICDABR0_OFFSET EQU 0x00000300 |
mbed_official | 390:35c2c1cf29cd | 32 | ICDIPR0_OFFSET EQU 0x00000400 |
mbed_official | 390:35c2c1cf29cd | 33 | |
mbed_official | 390:35c2c1cf29cd | 34 | Mode_USR EQU 0x10 |
mbed_official | 390:35c2c1cf29cd | 35 | Mode_FIQ EQU 0x11 |
mbed_official | 390:35c2c1cf29cd | 36 | Mode_IRQ EQU 0x12 |
mbed_official | 390:35c2c1cf29cd | 37 | Mode_SVC EQU 0x13 |
mbed_official | 390:35c2c1cf29cd | 38 | Mode_ABT EQU 0x17 |
mbed_official | 390:35c2c1cf29cd | 39 | Mode_UND EQU 0x1B |
mbed_official | 390:35c2c1cf29cd | 40 | Mode_SYS EQU 0x1F |
mbed_official | 390:35c2c1cf29cd | 41 | |
mbed_official | 390:35c2c1cf29cd | 42 | I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled |
mbed_official | 390:35c2c1cf29cd | 43 | F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled |
mbed_official | 390:35c2c1cf29cd | 44 | T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state |
mbed_official | 390:35c2c1cf29cd | 45 | |
mbed_official | 390:35c2c1cf29cd | 46 | GIC_ERRATA_CHECK_1 EQU 0x000003FE |
mbed_official | 390:35c2c1cf29cd | 47 | GIC_ERRATA_CHECK_2 EQU 0x000003FF |
mbed_official | 390:35c2c1cf29cd | 48 | |
mbed_official | 390:35c2c1cf29cd | 49 | |
mbed_official | 390:35c2c1cf29cd | 50 | Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 |
mbed_official | 390:35c2c1cf29cd | 51 | Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 |
mbed_official | 390:35c2c1cf29cd | 52 | Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable |
mbed_official | 390:35c2c1cf29cd | 53 | Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable |
mbed_official | 390:35c2c1cf29cd | 54 | Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 |
mbed_official | 390:35c2c1cf29cd | 55 | Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0 |
mbed_official | 390:35c2c1cf29cd | 56 | Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable |
mbed_official | 390:35c2c1cf29cd | 57 | Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored) |
mbed_official | 390:35c2c1cf29cd | 58 | |
mbed_official | 390:35c2c1cf29cd | 59 | RAM_BASE EQU 0x80000000 |
mbed_official | 390:35c2c1cf29cd | 60 | VRAM_BASE EQU 0x18000000 |
mbed_official | 390:35c2c1cf29cd | 61 | SRAM_BASE EQU 0x2e000000 |
mbed_official | 390:35c2c1cf29cd | 62 | ETHERNET EQU 0x1a000000 |
mbed_official | 390:35c2c1cf29cd | 63 | CS3_PERIPHERAL_BASE EQU 0x1c000000 |
mbed_official | 390:35c2c1cf29cd | 64 | |
mbed_official | 390:35c2c1cf29cd | 65 | ; <h> Stack Configuration |
mbed_official | 390:35c2c1cf29cd | 66 | ; <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8> |
mbed_official | 390:35c2c1cf29cd | 67 | ; </h> |
mbed_official | 390:35c2c1cf29cd | 68 | |
mbed_official | 390:35c2c1cf29cd | 69 | UND_Stack_Size EQU 0x00000100 |
mbed_official | 390:35c2c1cf29cd | 70 | SVC_Stack_Size EQU 0x00008000 |
mbed_official | 390:35c2c1cf29cd | 71 | ABT_Stack_Size EQU 0x00000100 |
mbed_official | 390:35c2c1cf29cd | 72 | FIQ_Stack_Size EQU 0x00000100 |
mbed_official | 390:35c2c1cf29cd | 73 | IRQ_Stack_Size EQU 0x00008000 |
mbed_official | 390:35c2c1cf29cd | 74 | USR_Stack_Size EQU 0x00004000 |
mbed_official | 390:35c2c1cf29cd | 75 | |
mbed_official | 390:35c2c1cf29cd | 76 | ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ |
mbed_official | 390:35c2c1cf29cd | 77 | FIQ_Stack_Size + IRQ_Stack_Size) |
mbed_official | 390:35c2c1cf29cd | 78 | |
mbed_official | 390:35c2c1cf29cd | 79 | AREA STACK, NOINIT, READWRITE, ALIGN=3 |
mbed_official | 390:35c2c1cf29cd | 80 | Stack_Mem SPACE USR_Stack_Size |
mbed_official | 390:35c2c1cf29cd | 81 | __initial_sp SPACE ISR_Stack_Size |
mbed_official | 390:35c2c1cf29cd | 82 | |
mbed_official | 390:35c2c1cf29cd | 83 | Stack_Top |
mbed_official | 390:35c2c1cf29cd | 84 | |
mbed_official | 390:35c2c1cf29cd | 85 | |
mbed_official | 390:35c2c1cf29cd | 86 | ; <h> Heap Configuration |
mbed_official | 390:35c2c1cf29cd | 87 | ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> |
mbed_official | 390:35c2c1cf29cd | 88 | ; </h> |
mbed_official | 390:35c2c1cf29cd | 89 | |
mbed_official | 390:35c2c1cf29cd | 90 | Heap_Size EQU 0x00080000 |
mbed_official | 390:35c2c1cf29cd | 91 | |
mbed_official | 390:35c2c1cf29cd | 92 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
mbed_official | 390:35c2c1cf29cd | 93 | __heap_base |
mbed_official | 390:35c2c1cf29cd | 94 | Heap_Mem SPACE Heap_Size |
mbed_official | 390:35c2c1cf29cd | 95 | __heap_limit |
mbed_official | 390:35c2c1cf29cd | 96 | |
mbed_official | 390:35c2c1cf29cd | 97 | |
mbed_official | 390:35c2c1cf29cd | 98 | PRESERVE8 |
mbed_official | 390:35c2c1cf29cd | 99 | ARM |
mbed_official | 390:35c2c1cf29cd | 100 | |
mbed_official | 390:35c2c1cf29cd | 101 | |
mbed_official | 390:35c2c1cf29cd | 102 | ; Vector Table Mapped to Address 0 at Reset |
mbed_official | 390:35c2c1cf29cd | 103 | |
mbed_official | 390:35c2c1cf29cd | 104 | AREA RESET, CODE, READONLY |
mbed_official | 390:35c2c1cf29cd | 105 | EXPORT __Vectors |
mbed_official | 390:35c2c1cf29cd | 106 | EXPORT __Vectors_End |
mbed_official | 390:35c2c1cf29cd | 107 | EXPORT __Vectors_Size |
mbed_official | 390:35c2c1cf29cd | 108 | |
mbed_official | 390:35c2c1cf29cd | 109 | __Vectors LDR PC, Reset_Addr ; Address of Reset Handler |
mbed_official | 390:35c2c1cf29cd | 110 | LDR PC, Undef_Addr ; Address of Undef Handler |
mbed_official | 390:35c2c1cf29cd | 111 | LDR PC, SVC_Addr ; Address of SVC Handler |
mbed_official | 390:35c2c1cf29cd | 112 | LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler |
mbed_official | 390:35c2c1cf29cd | 113 | LDR PC, DAbt_Addr ; Address of Data Abort Handler |
mbed_official | 390:35c2c1cf29cd | 114 | NOP ; Reserved Vector |
mbed_official | 390:35c2c1cf29cd | 115 | LDR PC, IRQ_Addr ; Address of IRQ Handler |
mbed_official | 390:35c2c1cf29cd | 116 | LDR PC, FIQ_Addr ; Address of FIQ Handler |
mbed_official | 390:35c2c1cf29cd | 117 | __Vectors_End |
mbed_official | 390:35c2c1cf29cd | 118 | |
mbed_official | 390:35c2c1cf29cd | 119 | __Vectors_Size EQU __Vectors_End - __Vectors |
mbed_official | 390:35c2c1cf29cd | 120 | |
mbed_official | 390:35c2c1cf29cd | 121 | Reset_Addr DCD Reset_Handler |
mbed_official | 390:35c2c1cf29cd | 122 | Undef_Addr DCD Undef_Handler |
mbed_official | 390:35c2c1cf29cd | 123 | SVC_Addr DCD SVC_Handler |
mbed_official | 390:35c2c1cf29cd | 124 | PAbt_Addr DCD PAbt_Handler |
mbed_official | 390:35c2c1cf29cd | 125 | DAbt_Addr DCD DAbt_Handler |
mbed_official | 390:35c2c1cf29cd | 126 | IRQ_Addr DCD IRQ_Handler |
mbed_official | 390:35c2c1cf29cd | 127 | FIQ_Addr DCD FIQ_Handler |
mbed_official | 390:35c2c1cf29cd | 128 | |
mbed_official | 390:35c2c1cf29cd | 129 | AREA |.text|, CODE, READONLY |
mbed_official | 390:35c2c1cf29cd | 130 | |
mbed_official | 390:35c2c1cf29cd | 131 | Reset_Handler PROC |
mbed_official | 390:35c2c1cf29cd | 132 | EXPORT Reset_Handler [WEAK] |
mbed_official | 390:35c2c1cf29cd | 133 | IMPORT SystemInit |
mbed_official | 390:35c2c1cf29cd | 134 | IMPORT InitMemorySubsystem |
mbed_official | 390:35c2c1cf29cd | 135 | IMPORT __main |
mbed_official | 390:35c2c1cf29cd | 136 | IMPORT RZ_A1_SetSramWriteEnable |
mbed_official | 390:35c2c1cf29cd | 137 | |
mbed_official | 390:35c2c1cf29cd | 138 | ; Put any cores other than 0 to sleep |
mbed_official | 390:35c2c1cf29cd | 139 | MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR |
mbed_official | 390:35c2c1cf29cd | 140 | ANDS R0, R0, #3 |
mbed_official | 390:35c2c1cf29cd | 141 | goToSleep |
mbed_official | 390:35c2c1cf29cd | 142 | WFINE |
mbed_official | 390:35c2c1cf29cd | 143 | BNE goToSleep |
mbed_official | 390:35c2c1cf29cd | 144 | |
mbed_official | 390:35c2c1cf29cd | 145 | ; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. |
mbed_official | 390:35c2c1cf29cd | 146 | ; Enables Full Access i.e. in both privileged and non privileged modes |
mbed_official | 390:35c2c1cf29cd | 147 | MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) |
mbed_official | 390:35c2c1cf29cd | 148 | ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 |
mbed_official | 390:35c2c1cf29cd | 149 | MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) |
mbed_official | 390:35c2c1cf29cd | 150 | ISB |
mbed_official | 390:35c2c1cf29cd | 151 | |
mbed_official | 390:35c2c1cf29cd | 152 | ; Switch on the VFP and NEON hardware |
mbed_official | 390:35c2c1cf29cd | 153 | MOV r0, #0x40000000 |
mbed_official | 390:35c2c1cf29cd | 154 | VMSR FPEXC, r0 ; Write FPEXC register, EN bit set |
mbed_official | 390:35c2c1cf29cd | 155 | |
mbed_official | 390:35c2c1cf29cd | 156 | MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register |
mbed_official | 390:35c2c1cf29cd | 157 | BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache |
mbed_official | 390:35c2c1cf29cd | 158 | BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache |
mbed_official | 390:35c2c1cf29cd | 159 | BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU |
mbed_official | 390:35c2c1cf29cd | 160 | BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction |
mbed_official | 390:35c2c1cf29cd | 161 | BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs |
mbed_official | 390:35c2c1cf29cd | 162 | MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register |
mbed_official | 390:35c2c1cf29cd | 163 | ISB |
mbed_official | 390:35c2c1cf29cd | 164 | |
mbed_official | 390:35c2c1cf29cd | 165 | ; Set Vector Base Address Register (VBAR) to point to this application's vector table |
mbed_official | 390:35c2c1cf29cd | 166 | LDR R0, =__Vectors |
mbed_official | 390:35c2c1cf29cd | 167 | MCR p15, 0, R0, c12, c0, 0 |
mbed_official | 390:35c2c1cf29cd | 168 | |
mbed_official | 390:35c2c1cf29cd | 169 | ; Setup Stack for each exceptional mode |
mbed_official | 390:35c2c1cf29cd | 170 | LDR R0, =Stack_Top |
mbed_official | 390:35c2c1cf29cd | 171 | |
mbed_official | 390:35c2c1cf29cd | 172 | ; Enter Undefined Instruction Mode and set its Stack Pointer |
mbed_official | 390:35c2c1cf29cd | 173 | MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit |
mbed_official | 390:35c2c1cf29cd | 174 | MOV SP, R0 |
mbed_official | 390:35c2c1cf29cd | 175 | SUB R0, R0, #UND_Stack_Size |
mbed_official | 390:35c2c1cf29cd | 176 | |
mbed_official | 390:35c2c1cf29cd | 177 | ; Enter Abort Mode and set its Stack Pointer |
mbed_official | 390:35c2c1cf29cd | 178 | MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit |
mbed_official | 390:35c2c1cf29cd | 179 | MOV SP, R0 |
mbed_official | 390:35c2c1cf29cd | 180 | SUB R0, R0, #ABT_Stack_Size |
mbed_official | 390:35c2c1cf29cd | 181 | |
mbed_official | 390:35c2c1cf29cd | 182 | ; Enter FIQ Mode and set its Stack Pointer |
mbed_official | 390:35c2c1cf29cd | 183 | MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit |
mbed_official | 390:35c2c1cf29cd | 184 | MOV SP, R0 |
mbed_official | 390:35c2c1cf29cd | 185 | SUB R0, R0, #FIQ_Stack_Size |
mbed_official | 390:35c2c1cf29cd | 186 | |
mbed_official | 390:35c2c1cf29cd | 187 | ; Enter IRQ Mode and set its Stack Pointer |
mbed_official | 390:35c2c1cf29cd | 188 | MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit |
mbed_official | 390:35c2c1cf29cd | 189 | MOV SP, R0 |
mbed_official | 390:35c2c1cf29cd | 190 | SUB R0, R0, #IRQ_Stack_Size |
mbed_official | 390:35c2c1cf29cd | 191 | |
mbed_official | 390:35c2c1cf29cd | 192 | ; Enter Supervisor Mode and set its Stack Pointer |
mbed_official | 390:35c2c1cf29cd | 193 | MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit |
mbed_official | 390:35c2c1cf29cd | 194 | MOV SP, R0 |
mbed_official | 390:35c2c1cf29cd | 195 | |
mbed_official | 390:35c2c1cf29cd | 196 | ; Enter System Mode to complete initialization and enter kernel |
mbed_official | 390:35c2c1cf29cd | 197 | MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit |
mbed_official | 390:35c2c1cf29cd | 198 | MOV SP, R0 |
mbed_official | 390:35c2c1cf29cd | 199 | |
mbed_official | 390:35c2c1cf29cd | 200 | ISB |
mbed_official | 390:35c2c1cf29cd | 201 | |
mbed_official | 390:35c2c1cf29cd | 202 | LDR R0, =RZ_A1_SetSramWriteEnable |
mbed_official | 390:35c2c1cf29cd | 203 | BLX R0 |
mbed_official | 390:35c2c1cf29cd | 204 | |
mbed_official | 390:35c2c1cf29cd | 205 | IMPORT create_translation_table |
mbed_official | 390:35c2c1cf29cd | 206 | BL create_translation_table |
mbed_official | 390:35c2c1cf29cd | 207 | |
mbed_official | 390:35c2c1cf29cd | 208 | ; USR/SYS stack pointer will be set during kernel init |
mbed_official | 390:35c2c1cf29cd | 209 | |
mbed_official | 390:35c2c1cf29cd | 210 | LDR R0, =SystemInit |
mbed_official | 390:35c2c1cf29cd | 211 | BLX R0 |
mbed_official | 390:35c2c1cf29cd | 212 | LDR R0, =InitMemorySubsystem |
mbed_official | 390:35c2c1cf29cd | 213 | BLX R0 |
mbed_official | 390:35c2c1cf29cd | 214 | LDR R0, =__main |
mbed_official | 390:35c2c1cf29cd | 215 | BLX R0 |
mbed_official | 390:35c2c1cf29cd | 216 | |
mbed_official | 390:35c2c1cf29cd | 217 | ENDP |
mbed_official | 390:35c2c1cf29cd | 218 | |
mbed_official | 390:35c2c1cf29cd | 219 | Undef_Handler\ |
mbed_official | 390:35c2c1cf29cd | 220 | PROC |
mbed_official | 390:35c2c1cf29cd | 221 | EXPORT Undef_Handler [WEAK] |
mbed_official | 390:35c2c1cf29cd | 222 | IMPORT CUndefHandler |
mbed_official | 390:35c2c1cf29cd | 223 | SRSFD SP!, #Mode_UND |
mbed_official | 390:35c2c1cf29cd | 224 | PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack |
mbed_official | 390:35c2c1cf29cd | 225 | |
mbed_official | 390:35c2c1cf29cd | 226 | MRS R0, SPSR |
mbed_official | 390:35c2c1cf29cd | 227 | TST R0, #T_Bit ; Check mode |
mbed_official | 390:35c2c1cf29cd | 228 | MOVEQ R1, #4 ; R1 = 4 ARM mode |
mbed_official | 390:35c2c1cf29cd | 229 | MOVNE R1, #2 ; R1 = 2 Thumb mode |
mbed_official | 390:35c2c1cf29cd | 230 | SUB R0, LR, R1 |
mbed_official | 390:35c2c1cf29cd | 231 | LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction |
mbed_official | 390:35c2c1cf29cd | 232 | BEQ undef_cont |
mbed_official | 390:35c2c1cf29cd | 233 | |
mbed_official | 390:35c2c1cf29cd | 234 | ;Thumb instruction |
mbed_official | 390:35c2c1cf29cd | 235 | ;Determine if it is a 32-bit Thumb instruction |
mbed_official | 390:35c2c1cf29cd | 236 | LDRH R0, [R0] |
mbed_official | 390:35c2c1cf29cd | 237 | MOV R2, #0x1c |
mbed_official | 390:35c2c1cf29cd | 238 | CMP R2, R0, LSR #11 |
mbed_official | 390:35c2c1cf29cd | 239 | BHS undef_cont ;16-bit Thumb instruction |
mbed_official | 390:35c2c1cf29cd | 240 | |
mbed_official | 390:35c2c1cf29cd | 241 | ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. |
mbed_official | 390:35c2c1cf29cd | 242 | LDRH R2, [LR] |
mbed_official | 390:35c2c1cf29cd | 243 | ORR R0, R2, R0, LSL #16 |
mbed_official | 390:35c2c1cf29cd | 244 | undef_cont |
mbed_official | 390:35c2c1cf29cd | 245 | MOV R2, LR ; Set LR to third argument |
mbed_official | 390:35c2c1cf29cd | 246 | |
mbed_official | 390:35c2c1cf29cd | 247 | ; AND R12, SP, #4 ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 248 | MOV R3, SP ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 249 | AND R12, R3, #4 |
mbed_official | 390:35c2c1cf29cd | 250 | SUB SP, SP, R12 ; Adjust stack |
mbed_official | 390:35c2c1cf29cd | 251 | PUSH {R12, LR} ; Store stack adjustment and dummy LR |
mbed_official | 390:35c2c1cf29cd | 252 | |
mbed_official | 390:35c2c1cf29cd | 253 | ;R0 Offending instruction |
mbed_official | 390:35c2c1cf29cd | 254 | ;R1 =2 (Thumb) or =4 (ARM) |
mbed_official | 390:35c2c1cf29cd | 255 | BL CUndefHandler |
mbed_official | 390:35c2c1cf29cd | 256 | |
mbed_official | 390:35c2c1cf29cd | 257 | POP {R12, LR} ; Get stack adjustment & discard dummy LR |
mbed_official | 390:35c2c1cf29cd | 258 | ADD SP, SP, R12 ; Unadjust stack |
mbed_official | 390:35c2c1cf29cd | 259 | |
mbed_official | 390:35c2c1cf29cd | 260 | LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry |
mbed_official | 390:35c2c1cf29cd | 261 | SUB LR, LR, R0 |
mbed_official | 390:35c2c1cf29cd | 262 | LDR R0, [SP, #28] ; Restore stacked SPSR |
mbed_official | 390:35c2c1cf29cd | 263 | MSR SPSR_CXSF, R0 |
mbed_official | 390:35c2c1cf29cd | 264 | POP {R0-R4, R12} ; Restore stacked APCS registers |
mbed_official | 390:35c2c1cf29cd | 265 | ADD SP, SP, #8 ; Adjust SP for already-restored banked registers |
mbed_official | 390:35c2c1cf29cd | 266 | MOVS PC, LR |
mbed_official | 390:35c2c1cf29cd | 267 | ENDP |
mbed_official | 390:35c2c1cf29cd | 268 | |
mbed_official | 390:35c2c1cf29cd | 269 | PAbt_Handler\ |
mbed_official | 390:35c2c1cf29cd | 270 | PROC |
mbed_official | 390:35c2c1cf29cd | 271 | EXPORT PAbt_Handler [WEAK] |
mbed_official | 390:35c2c1cf29cd | 272 | IMPORT CPAbtHandler |
mbed_official | 390:35c2c1cf29cd | 273 | SUB LR, LR, #4 ; Pre-adjust LR |
mbed_official | 390:35c2c1cf29cd | 274 | SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack |
mbed_official | 390:35c2c1cf29cd | 275 | PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack |
mbed_official | 390:35c2c1cf29cd | 276 | MRC p15, 0, R0, c5, c0, 1 ; IFSR |
mbed_official | 390:35c2c1cf29cd | 277 | MRC p15, 0, R1, c6, c0, 2 ; IFAR |
mbed_official | 390:35c2c1cf29cd | 278 | |
mbed_official | 390:35c2c1cf29cd | 279 | MOV R2, LR ; Set LR to third argument |
mbed_official | 390:35c2c1cf29cd | 280 | |
mbed_official | 390:35c2c1cf29cd | 281 | ; AND R12, SP, #4 ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 282 | MOV R3, SP ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 283 | AND R12, R3, #4 |
mbed_official | 390:35c2c1cf29cd | 284 | SUB SP, SP, R12 ; Adjust stack |
mbed_official | 390:35c2c1cf29cd | 285 | PUSH {R12, LR} ; Store stack adjustment and dummy LR |
mbed_official | 390:35c2c1cf29cd | 286 | |
mbed_official | 390:35c2c1cf29cd | 287 | BL CPAbtHandler |
mbed_official | 390:35c2c1cf29cd | 288 | |
mbed_official | 390:35c2c1cf29cd | 289 | POP {R12, LR} ; Get stack adjustment & discard dummy LR |
mbed_official | 390:35c2c1cf29cd | 290 | ADD SP, SP, R12 ; Unadjust stack |
mbed_official | 390:35c2c1cf29cd | 291 | |
mbed_official | 390:35c2c1cf29cd | 292 | POP {R0-R4, R12} ; Restore stack APCS registers |
mbed_official | 390:35c2c1cf29cd | 293 | RFEFD SP! ; Return from exception |
mbed_official | 390:35c2c1cf29cd | 294 | ENDP |
mbed_official | 390:35c2c1cf29cd | 295 | |
mbed_official | 390:35c2c1cf29cd | 296 | |
mbed_official | 390:35c2c1cf29cd | 297 | DAbt_Handler\ |
mbed_official | 390:35c2c1cf29cd | 298 | PROC |
mbed_official | 390:35c2c1cf29cd | 299 | EXPORT DAbt_Handler [WEAK] |
mbed_official | 390:35c2c1cf29cd | 300 | IMPORT CDAbtHandler |
mbed_official | 390:35c2c1cf29cd | 301 | SUB LR, LR, #8 ; Pre-adjust LR |
mbed_official | 390:35c2c1cf29cd | 302 | SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack |
mbed_official | 390:35c2c1cf29cd | 303 | PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack |
mbed_official | 390:35c2c1cf29cd | 304 | CLREX ; State of exclusive monitors unknown after taken data abort |
mbed_official | 390:35c2c1cf29cd | 305 | MRC p15, 0, R0, c5, c0, 0 ; DFSR |
mbed_official | 390:35c2c1cf29cd | 306 | MRC p15, 0, R1, c6, c0, 0 ; DFAR |
mbed_official | 390:35c2c1cf29cd | 307 | |
mbed_official | 390:35c2c1cf29cd | 308 | MOV R2, LR ; Set LR to third argument |
mbed_official | 390:35c2c1cf29cd | 309 | |
mbed_official | 390:35c2c1cf29cd | 310 | ; AND R12, SP, #4 ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 311 | MOV R3, SP ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 312 | AND R12, R3, #4 |
mbed_official | 390:35c2c1cf29cd | 313 | SUB SP, SP, R12 ; Adjust stack |
mbed_official | 390:35c2c1cf29cd | 314 | PUSH {R12, LR} ; Store stack adjustment and dummy LR |
mbed_official | 390:35c2c1cf29cd | 315 | |
mbed_official | 390:35c2c1cf29cd | 316 | BL CDAbtHandler |
mbed_official | 390:35c2c1cf29cd | 317 | |
mbed_official | 390:35c2c1cf29cd | 318 | POP {R12, LR} ; Get stack adjustment & discard dummy LR |
mbed_official | 390:35c2c1cf29cd | 319 | ADD SP, SP, R12 ; Unadjust stack |
mbed_official | 390:35c2c1cf29cd | 320 | |
mbed_official | 390:35c2c1cf29cd | 321 | POP {R0-R4, R12} ; Restore stacked APCS registers |
mbed_official | 390:35c2c1cf29cd | 322 | RFEFD SP! ; Return from exception |
mbed_official | 390:35c2c1cf29cd | 323 | ENDP |
mbed_official | 390:35c2c1cf29cd | 324 | |
mbed_official | 390:35c2c1cf29cd | 325 | FIQ_Handler\ |
mbed_official | 390:35c2c1cf29cd | 326 | PROC |
mbed_official | 390:35c2c1cf29cd | 327 | EXPORT FIQ_Handler [WEAK] |
mbed_official | 390:35c2c1cf29cd | 328 | ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, |
mbed_official | 390:35c2c1cf29cd | 329 | ;; so if a real FIQ Handler is implemented, this will be needed before returning: |
mbed_official | 390:35c2c1cf29cd | 330 | ;; LDR R1, =GICI_BASE |
mbed_official | 390:35c2c1cf29cd | 331 | ;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 |
mbed_official | 390:35c2c1cf29cd | 332 | B . |
mbed_official | 390:35c2c1cf29cd | 333 | ENDP |
mbed_official | 390:35c2c1cf29cd | 334 | |
mbed_official | 390:35c2c1cf29cd | 335 | SVC_Handler\ |
mbed_official | 390:35c2c1cf29cd | 336 | PROC |
mbed_official | 390:35c2c1cf29cd | 337 | EXPORT SVC_Handler [WEAK] |
mbed_official | 390:35c2c1cf29cd | 338 | B . |
mbed_official | 390:35c2c1cf29cd | 339 | ENDP |
mbed_official | 390:35c2c1cf29cd | 340 | |
mbed_official | 390:35c2c1cf29cd | 341 | IRQ_Handler\ |
mbed_official | 390:35c2c1cf29cd | 342 | PROC |
mbed_official | 390:35c2c1cf29cd | 343 | EXPORT IRQ_Handler [WEAK] |
mbed_official | 390:35c2c1cf29cd | 344 | IMPORT IRQCount |
mbed_official | 390:35c2c1cf29cd | 345 | IMPORT IRQTable |
mbed_official | 390:35c2c1cf29cd | 346 | IMPORT IRQNestLevel |
mbed_official | 390:35c2c1cf29cd | 347 | |
mbed_official | 390:35c2c1cf29cd | 348 | ;prologue |
mbed_official | 390:35c2c1cf29cd | 349 | SUB LR, LR, #4 ; Pre-adjust LR |
mbed_official | 390:35c2c1cf29cd | 350 | SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack |
mbed_official | 390:35c2c1cf29cd | 351 | CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL |
mbed_official | 390:35c2c1cf29cd | 352 | PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack |
mbed_official | 390:35c2c1cf29cd | 353 | |
mbed_official | 390:35c2c1cf29cd | 354 | ; AND R1, SP, #4 ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 355 | MOV R3, SP ; Ensure stack is 8-byte aligned |
mbed_official | 390:35c2c1cf29cd | 356 | AND R1, R3, #4 |
mbed_official | 390:35c2c1cf29cd | 357 | SUB SP, SP, R1 ; Adjust stack |
mbed_official | 390:35c2c1cf29cd | 358 | PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack |
mbed_official | 390:35c2c1cf29cd | 359 | |
mbed_official | 390:35c2c1cf29cd | 360 | LDR R0, =IRQNestLevel ; Get address of nesting counter |
mbed_official | 390:35c2c1cf29cd | 361 | LDR R1, [R0] |
mbed_official | 390:35c2c1cf29cd | 362 | ADD R1, R1, #1 ; Increment nesting counter |
mbed_official | 390:35c2c1cf29cd | 363 | STR R1, [R0] |
mbed_official | 390:35c2c1cf29cd | 364 | |
mbed_official | 390:35c2c1cf29cd | 365 | ;identify and acknowledge interrupt |
mbed_official | 390:35c2c1cf29cd | 366 | LDR R1, =GICI_BASE |
mbed_official | 390:35c2c1cf29cd | 367 | LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 |
mbed_official | 390:35c2c1cf29cd | 368 | LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register) |
mbed_official | 390:35c2c1cf29cd | 369 | DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts |
mbed_official | 390:35c2c1cf29cd | 370 | |
mbed_official | 390:35c2c1cf29cd | 371 | ; Workaround GIC 390 errata 733075 |
mbed_official | 390:35c2c1cf29cd | 372 | ; If the ID is not 0, then service the interrupt as normal. |
mbed_official | 390:35c2c1cf29cd | 373 | ; If the ID is 0 and active, then service interrupt ID 0 as normal. |
mbed_official | 390:35c2c1cf29cd | 374 | ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it |
mbed_official | 390:35c2c1cf29cd | 375 | ; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. |
mbed_official | 390:35c2c1cf29cd | 376 | ; |
mbed_official | 390:35c2c1cf29cd | 377 | LDR R2, =GICD_BASE |
mbed_official | 390:35c2c1cf29cd | 378 | LDR R3, =GIC_ERRATA_CHECK_1 |
mbed_official | 390:35c2c1cf29cd | 379 | CMP R0, R3 |
mbed_official | 390:35c2c1cf29cd | 380 | BEQ unlock_cpu |
mbed_official | 390:35c2c1cf29cd | 381 | LDR R3, =GIC_ERRATA_CHECK_2 |
mbed_official | 390:35c2c1cf29cd | 382 | CMP R0, R3 |
mbed_official | 390:35c2c1cf29cd | 383 | BEQ unlock_cpu |
mbed_official | 390:35c2c1cf29cd | 384 | CMP R0, #0 |
mbed_official | 390:35c2c1cf29cd | 385 | BNE int_active ; If the ID is not 0, then service the interrupt |
mbed_official | 390:35c2c1cf29cd | 386 | LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state |
mbed_official | 390:35c2c1cf29cd | 387 | TST R3, #1 |
mbed_official | 390:35c2c1cf29cd | 388 | BNE int_active ; If active, then service the interrupt |
mbed_official | 390:35c2c1cf29cd | 389 | unlock_cpu |
mbed_official | 390:35c2c1cf29cd | 390 | LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface |
mbed_official | 390:35c2c1cf29cd | 391 | STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write |
mbed_official | 390:35c2c1cf29cd | 392 | DSB ; Ensure the write completes before continuing |
mbed_official | 390:35c2c1cf29cd | 393 | B ret_irq ; Do not service the spurious interrupt |
mbed_official | 390:35c2c1cf29cd | 394 | ; End workaround |
mbed_official | 390:35c2c1cf29cd | 395 | |
mbed_official | 390:35c2c1cf29cd | 396 | int_active |
mbed_official | 390:35c2c1cf29cd | 397 | LDR R2, =IRQCount ; Read number of IRQs |
mbed_official | 390:35c2c1cf29cd | 398 | LDR R2, [R2] |
mbed_official | 390:35c2c1cf29cd | 399 | CMP R0, R2 ; Clean up and return if no handler |
mbed_official | 390:35c2c1cf29cd | 400 | BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling |
mbed_official | 390:35c2c1cf29cd | 401 | LDR R2, =IRQTable ; Get address of handler |
mbed_official | 390:35c2c1cf29cd | 402 | LDR R2, [R2, R0, LSL #2] |
mbed_official | 390:35c2c1cf29cd | 403 | CMP R2, #0 ; Clean up and return if handler address is 0 |
mbed_official | 390:35c2c1cf29cd | 404 | BEQ ret_irq |
mbed_official | 390:35c2c1cf29cd | 405 | PUSH {R0,R1} |
mbed_official | 390:35c2c1cf29cd | 406 | |
mbed_official | 390:35c2c1cf29cd | 407 | CPSIE i ; Now safe to re-enable interrupts |
mbed_official | 390:35c2c1cf29cd | 408 | BLX R2 ; Call handler. R0 will be IRQ number |
mbed_official | 390:35c2c1cf29cd | 409 | CPSID i ; Disable interrupts again |
mbed_official | 390:35c2c1cf29cd | 410 | |
mbed_official | 390:35c2c1cf29cd | 411 | ;write EOIR (GIC CPU Interface register) |
mbed_official | 390:35c2c1cf29cd | 412 | POP {R0,R1} |
mbed_official | 390:35c2c1cf29cd | 413 | DSB ; Ensure that interrupt source is cleared before we write the EOIR |
mbed_official | 390:35c2c1cf29cd | 414 | ret_irq |
mbed_official | 390:35c2c1cf29cd | 415 | ;epilogue |
mbed_official | 390:35c2c1cf29cd | 416 | STR R0, [R1, #ICCEOIR_OFFSET] |
mbed_official | 390:35c2c1cf29cd | 417 | |
mbed_official | 390:35c2c1cf29cd | 418 | LDR R0, =IRQNestLevel ; Get address of nesting counter |
mbed_official | 390:35c2c1cf29cd | 419 | LDR R1, [R0] |
mbed_official | 390:35c2c1cf29cd | 420 | SUB R1, R1, #1 ; Decrement nesting counter |
mbed_official | 390:35c2c1cf29cd | 421 | STR R1, [R0] |
mbed_official | 390:35c2c1cf29cd | 422 | |
mbed_official | 390:35c2c1cf29cd | 423 | POP {R1, LR} ; Get stack adjustment and restore LR_SVC |
mbed_official | 390:35c2c1cf29cd | 424 | ADD SP, SP, R1 ; Unadjust stack |
mbed_official | 390:35c2c1cf29cd | 425 | |
mbed_official | 390:35c2c1cf29cd | 426 | POP {R0-R3,R12} ; Restore stacked APCS registers |
mbed_official | 390:35c2c1cf29cd | 427 | RFEFD SP! ; Return from exception |
mbed_official | 390:35c2c1cf29cd | 428 | ENDP |
mbed_official | 390:35c2c1cf29cd | 429 | |
mbed_official | 390:35c2c1cf29cd | 430 | |
mbed_official | 390:35c2c1cf29cd | 431 | ; User Initial Stack & Heap |
mbed_official | 390:35c2c1cf29cd | 432 | |
mbed_official | 390:35c2c1cf29cd | 433 | IF :DEF:__MICROLIB |
mbed_official | 390:35c2c1cf29cd | 434 | |
mbed_official | 390:35c2c1cf29cd | 435 | EXPORT __initial_sp |
mbed_official | 390:35c2c1cf29cd | 436 | EXPORT __heap_base |
mbed_official | 390:35c2c1cf29cd | 437 | EXPORT __heap_limit |
mbed_official | 390:35c2c1cf29cd | 438 | |
mbed_official | 390:35c2c1cf29cd | 439 | ELSE |
mbed_official | 390:35c2c1cf29cd | 440 | |
mbed_official | 390:35c2c1cf29cd | 441 | IMPORT __use_two_region_memory |
mbed_official | 390:35c2c1cf29cd | 442 | EXPORT __user_initial_stackheap |
mbed_official | 390:35c2c1cf29cd | 443 | __user_initial_stackheap |
mbed_official | 390:35c2c1cf29cd | 444 | |
mbed_official | 390:35c2c1cf29cd | 445 | LDR R0, = Heap_Mem |
mbed_official | 390:35c2c1cf29cd | 446 | LDR R1, =(Stack_Mem + USR_Stack_Size) |
mbed_official | 390:35c2c1cf29cd | 447 | LDR R2, = (Heap_Mem + Heap_Size) |
mbed_official | 390:35c2c1cf29cd | 448 | LDR R3, = Stack_Mem |
mbed_official | 390:35c2c1cf29cd | 449 | BX LR |
mbed_official | 390:35c2c1cf29cd | 450 | |
mbed_official | 390:35c2c1cf29cd | 451 | ENDIF |
mbed_official | 390:35c2c1cf29cd | 452 | |
mbed_official | 390:35c2c1cf29cd | 453 | |
mbed_official | 390:35c2c1cf29cd | 454 | END |