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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_ll_sdmmc.h@87:085cde657901, 2014-02-08 (annotated)

Committer:
mbed_official
Date:
Sat Feb 08 19:45:06 2014 +0000
Revision:
87:085cde657901
Child:
106:ced8cbb51063
Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2



Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/



Add NUCLEO_F401RE, improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_ll_sdmmc.h
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 87:085cde657901 5 * @version V1.0.0RC2
mbed_official 87:085cde657901 6 * @date 04-February-2014
mbed_official 87:085cde657901 7 * @brief Header file of SDMMC HAL module.
mbed_official 87:085cde657901 8 ******************************************************************************
mbed_official 87:085cde657901 9 * @attention
mbed_official 87:085cde657901 10 *
mbed_official 87:085cde657901 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 12 *
mbed_official 87:085cde657901 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 14 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 16 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 19 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 21 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 22 * without specific prior written permission.
mbed_official 87:085cde657901 23 *
mbed_official 87:085cde657901 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 34 *
mbed_official 87:085cde657901 35 ******************************************************************************
mbed_official 87:085cde657901 36 */
mbed_official 87:085cde657901 37
mbed_official 87:085cde657901 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 87:085cde657901 39 #ifndef __STM32F4xx_LL_SDMMC_H
mbed_official 87:085cde657901 40 #define __STM32F4xx_LL_SDMMC_H
mbed_official 87:085cde657901 41
mbed_official 87:085cde657901 42 #ifdef __cplusplus
mbed_official 87:085cde657901 43 extern "C" {
mbed_official 87:085cde657901 44 #endif
mbed_official 87:085cde657901 45
mbed_official 87:085cde657901 46 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 47 #include "stm32f4xx_hal_def.h"
mbed_official 87:085cde657901 48
mbed_official 87:085cde657901 49 /** @addtogroup STM32F4xx_Driver
mbed_official 87:085cde657901 50 * @{
mbed_official 87:085cde657901 51 */
mbed_official 87:085cde657901 52
mbed_official 87:085cde657901 53 /** @addtogroup SDMMC
mbed_official 87:085cde657901 54 * @{
mbed_official 87:085cde657901 55 */
mbed_official 87:085cde657901 56
mbed_official 87:085cde657901 57 /* Exported types ------------------------------------------------------------*/
mbed_official 87:085cde657901 58
mbed_official 87:085cde657901 59 /**
mbed_official 87:085cde657901 60 * @brief SDMMC Configuration Structure definition
mbed_official 87:085cde657901 61 */
mbed_official 87:085cde657901 62 typedef struct
mbed_official 87:085cde657901 63 {
mbed_official 87:085cde657901 64 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
mbed_official 87:085cde657901 65 This parameter can be a value of @ref SDIO_Clock_Edge */
mbed_official 87:085cde657901 66
mbed_official 87:085cde657901 67 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
mbed_official 87:085cde657901 68 enabled or disabled.
mbed_official 87:085cde657901 69 This parameter can be a value of @ref SDIO_Clock_Bypass */
mbed_official 87:085cde657901 70
mbed_official 87:085cde657901 71 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
mbed_official 87:085cde657901 72 disabled when the bus is idle.
mbed_official 87:085cde657901 73 This parameter can be a value of @ref SDIO_Clock_Power_Save */
mbed_official 87:085cde657901 74
mbed_official 87:085cde657901 75 uint32_t BusWide; /*!< Specifies the SDIO bus width.
mbed_official 87:085cde657901 76 This parameter can be a value of @ref SDIO_Bus_Wide */
mbed_official 87:085cde657901 77
mbed_official 87:085cde657901 78 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
mbed_official 87:085cde657901 79 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
mbed_official 87:085cde657901 80
mbed_official 87:085cde657901 81 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
mbed_official 87:085cde657901 82 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official 87:085cde657901 83
mbed_official 87:085cde657901 84 }SDIO_InitTypeDef;
mbed_official 87:085cde657901 85
mbed_official 87:085cde657901 86
mbed_official 87:085cde657901 87 /**
mbed_official 87:085cde657901 88 * @brief SDIO Command Control structure
mbed_official 87:085cde657901 89 */
mbed_official 87:085cde657901 90 typedef struct
mbed_official 87:085cde657901 91 {
mbed_official 87:085cde657901 92 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
mbed_official 87:085cde657901 93 to a card as part of a command message. If a command
mbed_official 87:085cde657901 94 contains an argument, it must be loaded into this register
mbed_official 87:085cde657901 95 before writing the command to the command register. */
mbed_official 87:085cde657901 96
mbed_official 87:085cde657901 97 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
mbed_official 87:085cde657901 98 Max_Data = 64 */
mbed_official 87:085cde657901 99
mbed_official 87:085cde657901 100 uint32_t Response; /*!< Specifies the SDIO response type.
mbed_official 87:085cde657901 101 This parameter can be a value of @ref SDIO_Response_Type */
mbed_official 87:085cde657901 102
mbed_official 87:085cde657901 103 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
mbed_official 87:085cde657901 104 enabled or disabled.
mbed_official 87:085cde657901 105 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
mbed_official 87:085cde657901 106
mbed_official 87:085cde657901 107 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
mbed_official 87:085cde657901 108 is enabled or disabled.
mbed_official 87:085cde657901 109 This parameter can be a value of @ref SDIO_CPSM_State */
mbed_official 87:085cde657901 110 }SDIO_CmdInitTypeDef;
mbed_official 87:085cde657901 111
mbed_official 87:085cde657901 112
mbed_official 87:085cde657901 113 /**
mbed_official 87:085cde657901 114 * @brief SDIO Data Control structure
mbed_official 87:085cde657901 115 */
mbed_official 87:085cde657901 116 typedef struct
mbed_official 87:085cde657901 117 {
mbed_official 87:085cde657901 118 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
mbed_official 87:085cde657901 119
mbed_official 87:085cde657901 120 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
mbed_official 87:085cde657901 121
mbed_official 87:085cde657901 122 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
mbed_official 87:085cde657901 123 This parameter can be a value of @ref SDIO_Data_Block_Size */
mbed_official 87:085cde657901 124
mbed_official 87:085cde657901 125 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
mbed_official 87:085cde657901 126 is a read or write.
mbed_official 87:085cde657901 127 This parameter can be a value of @ref SDIO_Transfer_Direction */
mbed_official 87:085cde657901 128
mbed_official 87:085cde657901 129 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
mbed_official 87:085cde657901 130 This parameter can be a value of @ref SDIO_Transfer_Type */
mbed_official 87:085cde657901 131
mbed_official 87:085cde657901 132 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
mbed_official 87:085cde657901 133 is enabled or disabled.
mbed_official 87:085cde657901 134 This parameter can be a value of @ref SDIO_DPSM_State */
mbed_official 87:085cde657901 135 }SDIO_DataInitTypeDef;
mbed_official 87:085cde657901 136
mbed_official 87:085cde657901 137 /* Exported constants --------------------------------------------------------*/
mbed_official 87:085cde657901 138
mbed_official 87:085cde657901 139 /** @defgroup SDIO_Exported_Constants
mbed_official 87:085cde657901 140 * @{
mbed_official 87:085cde657901 141 */
mbed_official 87:085cde657901 142
mbed_official 87:085cde657901 143 /** @defgroup SDIO_Clock_Edge
mbed_official 87:085cde657901 144 * @{
mbed_official 87:085cde657901 145 */
mbed_official 87:085cde657901 146 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
mbed_official 87:085cde657901 147 #define SDIO_CLOCK_EDGE_FALLING ((uint32_t)0x00002000)
mbed_official 87:085cde657901 148
mbed_official 87:085cde657901 149 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
mbed_official 87:085cde657901 150 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
mbed_official 87:085cde657901 151 /**
mbed_official 87:085cde657901 152 * @}
mbed_official 87:085cde657901 153 */
mbed_official 87:085cde657901 154
mbed_official 87:085cde657901 155 /** @defgroup SDIO_Clock_Bypass
mbed_official 87:085cde657901 156 * @{
mbed_official 87:085cde657901 157 */
mbed_official 87:085cde657901 158 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 159 #define SDIO_CLOCK_BYPASS_ENABLE ((uint32_t)0x00000400)
mbed_official 87:085cde657901 160
mbed_official 87:085cde657901 161 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
mbed_official 87:085cde657901 162 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
mbed_official 87:085cde657901 163 /**
mbed_official 87:085cde657901 164 * @}
mbed_official 87:085cde657901 165 */
mbed_official 87:085cde657901 166
mbed_official 87:085cde657901 167 /** @defgroup SDIO_Clock_Power_Save
mbed_official 87:085cde657901 168 * @{
mbed_official 87:085cde657901 169 */
mbed_official 87:085cde657901 170 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 171 #define SDIO_CLOCK_POWER_SAVE_ENABLE ((uint32_t)0x00000200)
mbed_official 87:085cde657901 172
mbed_official 87:085cde657901 173 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
mbed_official 87:085cde657901 174 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
mbed_official 87:085cde657901 175 /**
mbed_official 87:085cde657901 176 * @}
mbed_official 87:085cde657901 177 */
mbed_official 87:085cde657901 178
mbed_official 87:085cde657901 179 /** @defgroup SDIO_Bus_Wide
mbed_official 87:085cde657901 180 * @{
mbed_official 87:085cde657901 181 */
mbed_official 87:085cde657901 182 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
mbed_official 87:085cde657901 183 #define SDIO_BUS_WIDE_4B ((uint32_t)0x00000800)
mbed_official 87:085cde657901 184 #define SDIO_BUS_WIDE_8B ((uint32_t)0x00001000)
mbed_official 87:085cde657901 185
mbed_official 87:085cde657901 186 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
mbed_official 87:085cde657901 187 ((WIDE) == SDIO_BUS_WIDE_4B) || \
mbed_official 87:085cde657901 188 ((WIDE) == SDIO_BUS_WIDE_8B))
mbed_official 87:085cde657901 189 /**
mbed_official 87:085cde657901 190 * @}
mbed_official 87:085cde657901 191 */
mbed_official 87:085cde657901 192
mbed_official 87:085cde657901 193 /** @defgroup SDIO_Hardware_Flow_Control
mbed_official 87:085cde657901 194 * @{
mbed_official 87:085cde657901 195 */
mbed_official 87:085cde657901 196 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 197 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE ((uint32_t)0x00004000)
mbed_official 87:085cde657901 198
mbed_official 87:085cde657901 199 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
mbed_official 87:085cde657901 200 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
mbed_official 87:085cde657901 201 /**
mbed_official 87:085cde657901 202 * @}
mbed_official 87:085cde657901 203 */
mbed_official 87:085cde657901 204
mbed_official 87:085cde657901 205 /** @defgroup SDIO_Clock_Division
mbed_official 87:085cde657901 206 * @{
mbed_official 87:085cde657901 207 */
mbed_official 87:085cde657901 208 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
mbed_official 87:085cde657901 209 /**
mbed_official 87:085cde657901 210 * @}
mbed_official 87:085cde657901 211 */
mbed_official 87:085cde657901 212
mbed_official 87:085cde657901 213 /**
mbed_official 87:085cde657901 214 * @}
mbed_official 87:085cde657901 215 */
mbed_official 87:085cde657901 216
mbed_official 87:085cde657901 217 /** @defgroup SDIO_Command_Index
mbed_official 87:085cde657901 218 * @{
mbed_official 87:085cde657901 219 */
mbed_official 87:085cde657901 220 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
mbed_official 87:085cde657901 221 /**
mbed_official 87:085cde657901 222 * @}
mbed_official 87:085cde657901 223 */
mbed_official 87:085cde657901 224
mbed_official 87:085cde657901 225 /** @defgroup SDIO_Response_Type
mbed_official 87:085cde657901 226 * @{
mbed_official 87:085cde657901 227 */
mbed_official 87:085cde657901 228 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
mbed_official 87:085cde657901 229 #define SDIO_RESPONSE_SHORT ((uint32_t)0x00000040)
mbed_official 87:085cde657901 230 #define SDIO_RESPONSE_LONG ((uint32_t)0x000000C0)
mbed_official 87:085cde657901 231
mbed_official 87:085cde657901 232 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
mbed_official 87:085cde657901 233 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
mbed_official 87:085cde657901 234 ((RESPONSE) == SDIO_RESPONSE_LONG))
mbed_official 87:085cde657901 235 /**
mbed_official 87:085cde657901 236 * @}
mbed_official 87:085cde657901 237 */
mbed_official 87:085cde657901 238
mbed_official 87:085cde657901 239 /** @defgroup SDIO_Wait_Interrupt_State
mbed_official 87:085cde657901 240 * @{
mbed_official 87:085cde657901 241 */
mbed_official 87:085cde657901 242 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
mbed_official 87:085cde657901 243 #define SDIO_WAIT_IT ((uint32_t)0x00000100)
mbed_official 87:085cde657901 244 #define SDIO_WAIT_PEND ((uint32_t)0x00000200)
mbed_official 87:085cde657901 245
mbed_official 87:085cde657901 246 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
mbed_official 87:085cde657901 247 ((WAIT) == SDIO_WAIT_IT) || \
mbed_official 87:085cde657901 248 ((WAIT) == SDIO_WAIT_PEND))
mbed_official 87:085cde657901 249 /**
mbed_official 87:085cde657901 250 * @}
mbed_official 87:085cde657901 251 */
mbed_official 87:085cde657901 252
mbed_official 87:085cde657901 253 /** @defgroup SDIO_CPSM_State
mbed_official 87:085cde657901 254 * @{
mbed_official 87:085cde657901 255 */
mbed_official 87:085cde657901 256 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 257 #define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
mbed_official 87:085cde657901 258
mbed_official 87:085cde657901 259 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
mbed_official 87:085cde657901 260 ((CPSM) == SDIO_CPSM_ENABLE))
mbed_official 87:085cde657901 261 /**
mbed_official 87:085cde657901 262 * @}
mbed_official 87:085cde657901 263 */
mbed_official 87:085cde657901 264
mbed_official 87:085cde657901 265 /** @defgroup SDIO_Response_Registers
mbed_official 87:085cde657901 266 * @{
mbed_official 87:085cde657901 267 */
mbed_official 87:085cde657901 268 #define SDIO_RESP1 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 269 #define SDIO_RESP2 ((uint32_t)0x00000004)
mbed_official 87:085cde657901 270 #define SDIO_RESP3 ((uint32_t)0x00000008)
mbed_official 87:085cde657901 271 #define SDIO_RESP4 ((uint32_t)0x0000000C)
mbed_official 87:085cde657901 272
mbed_official 87:085cde657901 273 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
mbed_official 87:085cde657901 274 ((RESP) == SDIO_RESP2) || \
mbed_official 87:085cde657901 275 ((RESP) == SDIO_RESP3) || \
mbed_official 87:085cde657901 276 ((RESP) == SDIO_RESP4))
mbed_official 87:085cde657901 277 /**
mbed_official 87:085cde657901 278 * @}
mbed_official 87:085cde657901 279 */
mbed_official 87:085cde657901 280
mbed_official 87:085cde657901 281 /** @defgroup SDIO_Data_Length
mbed_official 87:085cde657901 282 * @{
mbed_official 87:085cde657901 283 */
mbed_official 87:085cde657901 284 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
mbed_official 87:085cde657901 285 /**
mbed_official 87:085cde657901 286 * @}
mbed_official 87:085cde657901 287 */
mbed_official 87:085cde657901 288
mbed_official 87:085cde657901 289 /** @defgroup SDIO_Data_Block_Size
mbed_official 87:085cde657901 290 * @{
mbed_official 87:085cde657901 291 */
mbed_official 87:085cde657901 292 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
mbed_official 87:085cde657901 293 #define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000010)
mbed_official 87:085cde657901 294 #define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000020)
mbed_official 87:085cde657901 295 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
mbed_official 87:085cde657901 296 #define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000040)
mbed_official 87:085cde657901 297 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
mbed_official 87:085cde657901 298 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
mbed_official 87:085cde657901 299 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
mbed_official 87:085cde657901 300 #define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000080)
mbed_official 87:085cde657901 301 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
mbed_official 87:085cde657901 302 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
mbed_official 87:085cde657901 303 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
mbed_official 87:085cde657901 304 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
mbed_official 87:085cde657901 305 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
mbed_official 87:085cde657901 306 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
mbed_official 87:085cde657901 307
mbed_official 87:085cde657901 308 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
mbed_official 87:085cde657901 309 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
mbed_official 87:085cde657901 310 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
mbed_official 87:085cde657901 311 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
mbed_official 87:085cde657901 312 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
mbed_official 87:085cde657901 313 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
mbed_official 87:085cde657901 314 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
mbed_official 87:085cde657901 315 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
mbed_official 87:085cde657901 316 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
mbed_official 87:085cde657901 317 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
mbed_official 87:085cde657901 318 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
mbed_official 87:085cde657901 319 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
mbed_official 87:085cde657901 320 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
mbed_official 87:085cde657901 321 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
mbed_official 87:085cde657901 322 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
mbed_official 87:085cde657901 323 /**
mbed_official 87:085cde657901 324 * @}
mbed_official 87:085cde657901 325 */
mbed_official 87:085cde657901 326
mbed_official 87:085cde657901 327 /** @defgroup SDIO_Transfer_Direction
mbed_official 87:085cde657901 328 * @{
mbed_official 87:085cde657901 329 */
mbed_official 87:085cde657901 330 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
mbed_official 87:085cde657901 331 #define SDIO_TRANSFER_DIR_TO_SDIO ((uint32_t)0x00000002)
mbed_official 87:085cde657901 332
mbed_official 87:085cde657901 333 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
mbed_official 87:085cde657901 334 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
mbed_official 87:085cde657901 335 /**
mbed_official 87:085cde657901 336 * @}
mbed_official 87:085cde657901 337 */
mbed_official 87:085cde657901 338
mbed_official 87:085cde657901 339 /** @defgroup SDIO_Transfer_Type
mbed_official 87:085cde657901 340 * @{
mbed_official 87:085cde657901 341 */
mbed_official 87:085cde657901 342 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
mbed_official 87:085cde657901 343 #define SDIO_TRANSFER_MODE_STREAM ((uint32_t)0x00000004)
mbed_official 87:085cde657901 344
mbed_official 87:085cde657901 345 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
mbed_official 87:085cde657901 346 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
mbed_official 87:085cde657901 347 /**
mbed_official 87:085cde657901 348 * @}
mbed_official 87:085cde657901 349 */
mbed_official 87:085cde657901 350
mbed_official 87:085cde657901 351 /** @defgroup SDIO_DPSM_State
mbed_official 87:085cde657901 352 * @{
mbed_official 87:085cde657901 353 */
mbed_official 87:085cde657901 354 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 355 #define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
mbed_official 87:085cde657901 356
mbed_official 87:085cde657901 357 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
mbed_official 87:085cde657901 358 ((DPSM) == SDIO_DPSM_ENABLE))
mbed_official 87:085cde657901 359 /**
mbed_official 87:085cde657901 360 * @}
mbed_official 87:085cde657901 361 */
mbed_official 87:085cde657901 362
mbed_official 87:085cde657901 363 /** @defgroup SDIO_Read_Wait_Mode
mbed_official 87:085cde657901 364 * @{
mbed_official 87:085cde657901 365 */
mbed_official 87:085cde657901 366 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
mbed_official 87:085cde657901 367 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
mbed_official 87:085cde657901 368
mbed_official 87:085cde657901 369 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
mbed_official 87:085cde657901 370 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
mbed_official 87:085cde657901 371 /**
mbed_official 87:085cde657901 372 * @}
mbed_official 87:085cde657901 373 */
mbed_official 87:085cde657901 374
mbed_official 87:085cde657901 375 /** @defgroup SDIO_Interrupt_sources
mbed_official 87:085cde657901 376 * @{
mbed_official 87:085cde657901 377 */
mbed_official 87:085cde657901 378 #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
mbed_official 87:085cde657901 379 #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
mbed_official 87:085cde657901 380 #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
mbed_official 87:085cde657901 381 #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
mbed_official 87:085cde657901 382 #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
mbed_official 87:085cde657901 383 #define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
mbed_official 87:085cde657901 384 #define SDIO_IT_CMDREND ((uint32_t)0x00000040)
mbed_official 87:085cde657901 385 #define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
mbed_official 87:085cde657901 386 #define SDIO_IT_DATAEND ((uint32_t)0x00000100)
mbed_official 87:085cde657901 387 #define SDIO_IT_STBITERR ((uint32_t)0x00000200)
mbed_official 87:085cde657901 388 #define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
mbed_official 87:085cde657901 389 #define SDIO_IT_CMDACT ((uint32_t)0x00000800)
mbed_official 87:085cde657901 390 #define SDIO_IT_TXACT ((uint32_t)0x00001000)
mbed_official 87:085cde657901 391 #define SDIO_IT_RXACT ((uint32_t)0x00002000)
mbed_official 87:085cde657901 392 #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
mbed_official 87:085cde657901 393 #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
mbed_official 87:085cde657901 394 #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
mbed_official 87:085cde657901 395 #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
mbed_official 87:085cde657901 396 #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
mbed_official 87:085cde657901 397 #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
mbed_official 87:085cde657901 398 #define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
mbed_official 87:085cde657901 399 #define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
mbed_official 87:085cde657901 400 #define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
mbed_official 87:085cde657901 401 #define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
mbed_official 87:085cde657901 402
mbed_official 87:085cde657901 403 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
mbed_official 87:085cde657901 404 /**
mbed_official 87:085cde657901 405 * @}
mbed_official 87:085cde657901 406 */
mbed_official 87:085cde657901 407
mbed_official 87:085cde657901 408 /** @defgroup SDIO_Flags
mbed_official 87:085cde657901 409 * @{
mbed_official 87:085cde657901 410 */
mbed_official 87:085cde657901 411 #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
mbed_official 87:085cde657901 412 #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
mbed_official 87:085cde657901 413 #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
mbed_official 87:085cde657901 414 #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
mbed_official 87:085cde657901 415 #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
mbed_official 87:085cde657901 416 #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
mbed_official 87:085cde657901 417 #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
mbed_official 87:085cde657901 418 #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
mbed_official 87:085cde657901 419 #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
mbed_official 87:085cde657901 420 #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
mbed_official 87:085cde657901 421 #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
mbed_official 87:085cde657901 422 #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
mbed_official 87:085cde657901 423 #define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
mbed_official 87:085cde657901 424 #define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
mbed_official 87:085cde657901 425 #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
mbed_official 87:085cde657901 426 #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
mbed_official 87:085cde657901 427 #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
mbed_official 87:085cde657901 428 #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
mbed_official 87:085cde657901 429 #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
mbed_official 87:085cde657901 430 #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
mbed_official 87:085cde657901 431 #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
mbed_official 87:085cde657901 432 #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
mbed_official 87:085cde657901 433 #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
mbed_official 87:085cde657901 434 #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
mbed_official 87:085cde657901 435
mbed_official 87:085cde657901 436 #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
mbed_official 87:085cde657901 437 ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
mbed_official 87:085cde657901 438 ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
mbed_official 87:085cde657901 439 ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
mbed_official 87:085cde657901 440 ((FLAG) == SDIO_FLAG_TXUNDERR) || \
mbed_official 87:085cde657901 441 ((FLAG) == SDIO_FLAG_RXOVERR) || \
mbed_official 87:085cde657901 442 ((FLAG) == SDIO_FLAG_CMDREND) || \
mbed_official 87:085cde657901 443 ((FLAG) == SDIO_FLAG_CMDSENT) || \
mbed_official 87:085cde657901 444 ((FLAG) == SDIO_FLAG_DATAEND) || \
mbed_official 87:085cde657901 445 ((FLAG) == SDIO_FLAG_STBITERR) || \
mbed_official 87:085cde657901 446 ((FLAG) == SDIO_FLAG_DBCKEND) || \
mbed_official 87:085cde657901 447 ((FLAG) == SDIO_FLAG_CMDACT) || \
mbed_official 87:085cde657901 448 ((FLAG) == SDIO_FLAG_TXACT) || \
mbed_official 87:085cde657901 449 ((FLAG) == SDIO_FLAG_RXACT) || \
mbed_official 87:085cde657901 450 ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
mbed_official 87:085cde657901 451 ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
mbed_official 87:085cde657901 452 ((FLAG) == SDIO_FLAG_TXFIFOF) || \
mbed_official 87:085cde657901 453 ((FLAG) == SDIO_FLAG_RXFIFOF) || \
mbed_official 87:085cde657901 454 ((FLAG) == SDIO_FLAG_TXFIFOE) || \
mbed_official 87:085cde657901 455 ((FLAG) == SDIO_FLAG_RXFIFOE) || \
mbed_official 87:085cde657901 456 ((FLAG) == SDIO_FLAG_TXDAVL) || \
mbed_official 87:085cde657901 457 ((FLAG) == SDIO_FLAG_RXDAVL) || \
mbed_official 87:085cde657901 458 ((FLAG) == SDIO_FLAG_SDIOIT) || \
mbed_official 87:085cde657901 459 ((FLAG) == SDIO_FLAG_CEATAEND))
mbed_official 87:085cde657901 460
mbed_official 87:085cde657901 461 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
mbed_official 87:085cde657901 462
mbed_official 87:085cde657901 463 #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
mbed_official 87:085cde657901 464 ((IT) == SDIO_IT_DCRCFAIL) || \
mbed_official 87:085cde657901 465 ((IT) == SDIO_IT_CTIMEOUT) || \
mbed_official 87:085cde657901 466 ((IT) == SDIO_IT_DTIMEOUT) || \
mbed_official 87:085cde657901 467 ((IT) == SDIO_IT_TXUNDERR) || \
mbed_official 87:085cde657901 468 ((IT) == SDIO_IT_RXOVERR) || \
mbed_official 87:085cde657901 469 ((IT) == SDIO_IT_CMDREND) || \
mbed_official 87:085cde657901 470 ((IT) == SDIO_IT_CMDSENT) || \
mbed_official 87:085cde657901 471 ((IT) == SDIO_IT_DATAEND) || \
mbed_official 87:085cde657901 472 ((IT) == SDIO_IT_STBITERR) || \
mbed_official 87:085cde657901 473 ((IT) == SDIO_IT_DBCKEND) || \
mbed_official 87:085cde657901 474 ((IT) == SDIO_IT_CMDACT) || \
mbed_official 87:085cde657901 475 ((IT) == SDIO_IT_TXACT) || \
mbed_official 87:085cde657901 476 ((IT) == SDIO_IT_RXACT) || \
mbed_official 87:085cde657901 477 ((IT) == SDIO_IT_TXFIFOHE) || \
mbed_official 87:085cde657901 478 ((IT) == SDIO_IT_RXFIFOHF) || \
mbed_official 87:085cde657901 479 ((IT) == SDIO_IT_TXFIFOF) || \
mbed_official 87:085cde657901 480 ((IT) == SDIO_IT_RXFIFOF) || \
mbed_official 87:085cde657901 481 ((IT) == SDIO_IT_TXFIFOE) || \
mbed_official 87:085cde657901 482 ((IT) == SDIO_IT_RXFIFOE) || \
mbed_official 87:085cde657901 483 ((IT) == SDIO_IT_TXDAVL) || \
mbed_official 87:085cde657901 484 ((IT) == SDIO_IT_RXDAVL) || \
mbed_official 87:085cde657901 485 ((IT) == SDIO_IT_SDIOIT) || \
mbed_official 87:085cde657901 486 ((IT) == SDIO_IT_CEATAEND))
mbed_official 87:085cde657901 487
mbed_official 87:085cde657901 488 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
mbed_official 87:085cde657901 489
mbed_official 87:085cde657901 490 /**
mbed_official 87:085cde657901 491 * @}
mbed_official 87:085cde657901 492 */
mbed_official 87:085cde657901 493
mbed_official 87:085cde657901 494
mbed_official 87:085cde657901 495 /** @defgroup SDIO_Instance_definition
mbed_official 87:085cde657901 496 * @{
mbed_official 87:085cde657901 497 */
mbed_official 87:085cde657901 498 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
mbed_official 87:085cde657901 499
mbed_official 87:085cde657901 500 /**
mbed_official 87:085cde657901 501 * @}
mbed_official 87:085cde657901 502 */
mbed_official 87:085cde657901 503
mbed_official 87:085cde657901 504 /* Exported macro ------------------------------------------------------------*/
mbed_official 87:085cde657901 505 /* ------------ SDIO registers bit address in the alias region -------------- */
mbed_official 87:085cde657901 506 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
mbed_official 87:085cde657901 507
mbed_official 87:085cde657901 508 /* --- CLKCR Register ---*/
mbed_official 87:085cde657901 509 /* Alias word address of CLKEN bit */
mbed_official 87:085cde657901 510 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
mbed_official 87:085cde657901 511 #define CLKEN_BitNumber 0x08
mbed_official 87:085cde657901 512 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
mbed_official 87:085cde657901 513
mbed_official 87:085cde657901 514 /* --- CMD Register ---*/
mbed_official 87:085cde657901 515 /* Alias word address of SDIOSUSPEND bit */
mbed_official 87:085cde657901 516 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
mbed_official 87:085cde657901 517 #define SDIOSUSPEND_BitNumber 0x0B
mbed_official 87:085cde657901 518 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
mbed_official 87:085cde657901 519
mbed_official 87:085cde657901 520 /* Alias word address of ENCMDCOMPL bit */
mbed_official 87:085cde657901 521 #define ENCMDCOMPL_BitNumber 0x0C
mbed_official 87:085cde657901 522 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
mbed_official 87:085cde657901 523
mbed_official 87:085cde657901 524 /* Alias word address of NIEN bit */
mbed_official 87:085cde657901 525 #define NIEN_BitNumber 0x0D
mbed_official 87:085cde657901 526 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
mbed_official 87:085cde657901 527
mbed_official 87:085cde657901 528 /* Alias word address of ATACMD bit */
mbed_official 87:085cde657901 529 #define ATACMD_BitNumber 0x0E
mbed_official 87:085cde657901 530 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
mbed_official 87:085cde657901 531
mbed_official 87:085cde657901 532 /* --- DCTRL Register ---*/
mbed_official 87:085cde657901 533 /* Alias word address of DMAEN bit */
mbed_official 87:085cde657901 534 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
mbed_official 87:085cde657901 535 #define DMAEN_BitNumber 0x03
mbed_official 87:085cde657901 536 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
mbed_official 87:085cde657901 537
mbed_official 87:085cde657901 538 /* Alias word address of RWSTART bit */
mbed_official 87:085cde657901 539 #define RWSTART_BitNumber 0x08
mbed_official 87:085cde657901 540 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
mbed_official 87:085cde657901 541
mbed_official 87:085cde657901 542 /* Alias word address of RWSTOP bit */
mbed_official 87:085cde657901 543 #define RWSTOP_BitNumber 0x09
mbed_official 87:085cde657901 544 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
mbed_official 87:085cde657901 545
mbed_official 87:085cde657901 546 /* Alias word address of RWMOD bit */
mbed_official 87:085cde657901 547 #define RWMOD_BitNumber 0x0A
mbed_official 87:085cde657901 548 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
mbed_official 87:085cde657901 549
mbed_official 87:085cde657901 550 /* Alias word address of SDIOEN bit */
mbed_official 87:085cde657901 551 #define SDIOEN_BitNumber 0x0B
mbed_official 87:085cde657901 552 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
mbed_official 87:085cde657901 553
mbed_official 87:085cde657901 554 /* ---------------------- SDIO registers bit mask --------------------------- */
mbed_official 87:085cde657901 555 /* --- CLKCR Register ---*/
mbed_official 87:085cde657901 556 /* CLKCR register clear mask */
mbed_official 87:085cde657901 557 #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
mbed_official 87:085cde657901 558
mbed_official 87:085cde657901 559 /* --- PWRCTRL Register ---*/
mbed_official 87:085cde657901 560 /* SDIO PWRCTRL Mask */
mbed_official 87:085cde657901 561 #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
mbed_official 87:085cde657901 562
mbed_official 87:085cde657901 563 /* --- DCTRL Register ---*/
mbed_official 87:085cde657901 564 /* SDIO DCTRL Clear Mask */
mbed_official 87:085cde657901 565 #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
mbed_official 87:085cde657901 566
mbed_official 87:085cde657901 567 /* --- CMD Register ---*/
mbed_official 87:085cde657901 568 /* CMD Register clear mask */
mbed_official 87:085cde657901 569 #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
mbed_official 87:085cde657901 570
mbed_official 87:085cde657901 571 /* SDIO RESP Registers Address */
mbed_official 87:085cde657901 572 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
mbed_official 87:085cde657901 573
mbed_official 87:085cde657901 574 /* SD FLASH SDIO Interface */
mbed_official 87:085cde657901 575 #define SDIO_FIFO_ADDRESS ((uint32_t)0x40012C80)
mbed_official 87:085cde657901 576
mbed_official 87:085cde657901 577 /* SDIO Intialization Frequency (400KHz max) */
mbed_official 87:085cde657901 578 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
mbed_official 87:085cde657901 579
mbed_official 87:085cde657901 580 /* SDIO Data Transfer Frequency (25MHz max) */
mbed_official 87:085cde657901 581 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
mbed_official 87:085cde657901 582
mbed_official 87:085cde657901 583 /** @defgroup SDIO_Interrupt_Clock
mbed_official 87:085cde657901 584 * @brief macros to handle interrupts and specific clock configurations
mbed_official 87:085cde657901 585 * @{
mbed_official 87:085cde657901 586 */
mbed_official 87:085cde657901 587
mbed_official 87:085cde657901 588 /**
mbed_official 87:085cde657901 589 * @brief Enable the SDIO device.
mbed_official 87:085cde657901 590 * @param None
mbed_official 87:085cde657901 591 * @retval None
mbed_official 87:085cde657901 592 */
mbed_official 87:085cde657901 593 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
mbed_official 87:085cde657901 594
mbed_official 87:085cde657901 595 /**
mbed_official 87:085cde657901 596 * @brief Disable the SDIO device.
mbed_official 87:085cde657901 597 * @param None
mbed_official 87:085cde657901 598 * @retval None
mbed_official 87:085cde657901 599 */
mbed_official 87:085cde657901 600 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
mbed_official 87:085cde657901 601
mbed_official 87:085cde657901 602 /**
mbed_official 87:085cde657901 603 * @brief Enable the SDIO DMA transfer.
mbed_official 87:085cde657901 604 * @param None
mbed_official 87:085cde657901 605 * @retval None
mbed_official 87:085cde657901 606 */
mbed_official 87:085cde657901 607 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
mbed_official 87:085cde657901 608
mbed_official 87:085cde657901 609 /**
mbed_official 87:085cde657901 610 * @brief Disable the SDIO DMA transfer.
mbed_official 87:085cde657901 611 * @param None
mbed_official 87:085cde657901 612 * @retval None
mbed_official 87:085cde657901 613 */
mbed_official 87:085cde657901 614 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
mbed_official 87:085cde657901 615
mbed_official 87:085cde657901 616 /**
mbed_official 87:085cde657901 617 * @brief Enable the SDIO device interrupt.
mbed_official 87:085cde657901 618 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 87:085cde657901 619 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
mbed_official 87:085cde657901 620 * This parameter can be one or a combination of the following values:
mbed_official 87:085cde657901 621 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 87:085cde657901 622 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 87:085cde657901 623 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 87:085cde657901 624 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 87:085cde657901 625 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 87:085cde657901 626 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 87:085cde657901 627 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 87:085cde657901 628 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 87:085cde657901 629 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 87:085cde657901 630 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 87:085cde657901 631 * bus mode interrupt
mbed_official 87:085cde657901 632 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 87:085cde657901 633 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 87:085cde657901 634 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 87:085cde657901 635 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 87:085cde657901 636 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 87:085cde657901 637 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 87:085cde657901 638 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 87:085cde657901 639 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 87:085cde657901 640 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 87:085cde657901 641 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 87:085cde657901 642 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 87:085cde657901 643 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 87:085cde657901 644 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 87:085cde657901 645 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 87:085cde657901 646 * @retval None
mbed_official 87:085cde657901 647 */
mbed_official 87:085cde657901 648 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
mbed_official 87:085cde657901 649
mbed_official 87:085cde657901 650 /**
mbed_official 87:085cde657901 651 * @brief Disable the SDIO device interrupt.
mbed_official 87:085cde657901 652 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 87:085cde657901 653 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
mbed_official 87:085cde657901 654 * This parameter can be one or a combination of the following values:
mbed_official 87:085cde657901 655 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 87:085cde657901 656 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 87:085cde657901 657 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 87:085cde657901 658 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 87:085cde657901 659 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 87:085cde657901 660 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 87:085cde657901 661 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 87:085cde657901 662 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 87:085cde657901 663 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 87:085cde657901 664 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 87:085cde657901 665 * bus mode interrupt
mbed_official 87:085cde657901 666 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 87:085cde657901 667 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 87:085cde657901 668 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 87:085cde657901 669 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 87:085cde657901 670 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 87:085cde657901 671 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 87:085cde657901 672 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 87:085cde657901 673 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 87:085cde657901 674 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 87:085cde657901 675 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 87:085cde657901 676 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 87:085cde657901 677 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 87:085cde657901 678 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 87:085cde657901 679 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 87:085cde657901 680 * @retval None
mbed_official 87:085cde657901 681 */
mbed_official 87:085cde657901 682 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
mbed_official 87:085cde657901 683
mbed_official 87:085cde657901 684 /**
mbed_official 87:085cde657901 685 * @brief Checks whether the specified SDIO flag is set or not.
mbed_official 87:085cde657901 686 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 87:085cde657901 687 * @param __FLAG__: specifies the flag to check.
mbed_official 87:085cde657901 688 * This parameter can be one of the following values:
mbed_official 87:085cde657901 689 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 87:085cde657901 690 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 87:085cde657901 691 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
mbed_official 87:085cde657901 692 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
mbed_official 87:085cde657901 693 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 87:085cde657901 694 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 87:085cde657901 695 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 87:085cde657901 696 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
mbed_official 87:085cde657901 697 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 87:085cde657901 698 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
mbed_official 87:085cde657901 699 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 87:085cde657901 700 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
mbed_official 87:085cde657901 701 * @arg SDIO_FLAG_TXACT: Data transmit in progress
mbed_official 87:085cde657901 702 * @arg SDIO_FLAG_RXACT: Data receive in progress
mbed_official 87:085cde657901 703 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
mbed_official 87:085cde657901 704 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
mbed_official 87:085cde657901 705 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
mbed_official 87:085cde657901 706 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
mbed_official 87:085cde657901 707 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
mbed_official 87:085cde657901 708 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
mbed_official 87:085cde657901 709 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
mbed_official 87:085cde657901 710 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
mbed_official 87:085cde657901 711 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
mbed_official 87:085cde657901 712 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 87:085cde657901 713 * @retval The new state of SDIO_FLAG (SET or RESET).
mbed_official 87:085cde657901 714 */
mbed_official 87:085cde657901 715 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
mbed_official 87:085cde657901 716
mbed_official 87:085cde657901 717
mbed_official 87:085cde657901 718 /**
mbed_official 87:085cde657901 719 * @brief Clears the SDIO's pending flags.
mbed_official 87:085cde657901 720 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 87:085cde657901 721 * @param __FLAG__: specifies the flag to clear.
mbed_official 87:085cde657901 722 * This parameter can be one or a combination of the following values:
mbed_official 87:085cde657901 723 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
mbed_official 87:085cde657901 724 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
mbed_official 87:085cde657901 725 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
mbed_official 87:085cde657901 726 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
mbed_official 87:085cde657901 727 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
mbed_official 87:085cde657901 728 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
mbed_official 87:085cde657901 729 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
mbed_official 87:085cde657901 730 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
mbed_official 87:085cde657901 731 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
mbed_official 87:085cde657901 732 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
mbed_official 87:085cde657901 733 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
mbed_official 87:085cde657901 734 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
mbed_official 87:085cde657901 735 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 87:085cde657901 736 * @retval None
mbed_official 87:085cde657901 737 */
mbed_official 87:085cde657901 738 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
mbed_official 87:085cde657901 739
mbed_official 87:085cde657901 740 /**
mbed_official 87:085cde657901 741 * @brief Checks whether the specified SDIO interrupt has occurred or not.
mbed_official 87:085cde657901 742 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 87:085cde657901 743 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
mbed_official 87:085cde657901 744 * This parameter can be one of the following values:
mbed_official 87:085cde657901 745 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 87:085cde657901 746 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 87:085cde657901 747 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 87:085cde657901 748 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 87:085cde657901 749 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 87:085cde657901 750 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 87:085cde657901 751 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 87:085cde657901 752 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 87:085cde657901 753 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
mbed_official 87:085cde657901 754 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 87:085cde657901 755 * bus mode interrupt
mbed_official 87:085cde657901 756 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
mbed_official 87:085cde657901 757 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
mbed_official 87:085cde657901 758 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
mbed_official 87:085cde657901 759 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
mbed_official 87:085cde657901 760 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
mbed_official 87:085cde657901 761 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
mbed_official 87:085cde657901 762 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
mbed_official 87:085cde657901 763 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
mbed_official 87:085cde657901 764 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
mbed_official 87:085cde657901 765 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
mbed_official 87:085cde657901 766 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
mbed_official 87:085cde657901 767 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
mbed_official 87:085cde657901 768 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 87:085cde657901 769 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
mbed_official 87:085cde657901 770 * @retval The new state of SDIO_IT (SET or RESET).
mbed_official 87:085cde657901 771 */
mbed_official 87:085cde657901 772 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
mbed_official 87:085cde657901 773
mbed_official 87:085cde657901 774 /**
mbed_official 87:085cde657901 775 * @brief Clears the SDIO's interrupt pending bits.
mbed_official 87:085cde657901 776 * @param __INSTANCE__ : Pointer to SDIO register base
mbed_official 87:085cde657901 777 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official 87:085cde657901 778 * This parameter can be one or a combination of the following values:
mbed_official 87:085cde657901 779 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
mbed_official 87:085cde657901 780 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
mbed_official 87:085cde657901 781 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
mbed_official 87:085cde657901 782 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
mbed_official 87:085cde657901 783 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
mbed_official 87:085cde657901 784 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
mbed_official 87:085cde657901 785 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
mbed_official 87:085cde657901 786 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
mbed_official 87:085cde657901 787 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
mbed_official 87:085cde657901 788 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
mbed_official 87:085cde657901 789 * bus mode interrupt
mbed_official 87:085cde657901 790 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
mbed_official 87:085cde657901 791 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
mbed_official 87:085cde657901 792 * @retval None
mbed_official 87:085cde657901 793 */
mbed_official 87:085cde657901 794 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
mbed_official 87:085cde657901 795
mbed_official 87:085cde657901 796 /**
mbed_official 87:085cde657901 797 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 87:085cde657901 798 * @param None
mbed_official 87:085cde657901 799 * @retval None
mbed_official 87:085cde657901 800 */
mbed_official 87:085cde657901 801 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
mbed_official 87:085cde657901 802
mbed_official 87:085cde657901 803 /**
mbed_official 87:085cde657901 804 * @brief Disable Start the SD I/O Read Wait operations.
mbed_official 87:085cde657901 805 * @param None
mbed_official 87:085cde657901 806 * @retval None
mbed_official 87:085cde657901 807 */
mbed_official 87:085cde657901 808 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
mbed_official 87:085cde657901 809
mbed_official 87:085cde657901 810 /**
mbed_official 87:085cde657901 811 * @brief Enable Start the SD I/O Read Wait operation.
mbed_official 87:085cde657901 812 * @param None
mbed_official 87:085cde657901 813 * @retval None
mbed_official 87:085cde657901 814 */
mbed_official 87:085cde657901 815 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
mbed_official 87:085cde657901 816
mbed_official 87:085cde657901 817 /**
mbed_official 87:085cde657901 818 * @brief Disable Stop the SD I/O Read Wait operations.
mbed_official 87:085cde657901 819 * @param None
mbed_official 87:085cde657901 820 * @retval None
mbed_official 87:085cde657901 821 */
mbed_official 87:085cde657901 822 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
mbed_official 87:085cde657901 823
mbed_official 87:085cde657901 824 /**
mbed_official 87:085cde657901 825 * @brief Enable the SD I/O Mode Operation.
mbed_official 87:085cde657901 826 * @param None
mbed_official 87:085cde657901 827 * @retval None
mbed_official 87:085cde657901 828 */
mbed_official 87:085cde657901 829 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
mbed_official 87:085cde657901 830
mbed_official 87:085cde657901 831 /**
mbed_official 87:085cde657901 832 * @brief Disable the SD I/O Mode Operation.
mbed_official 87:085cde657901 833 * @param None
mbed_official 87:085cde657901 834 * @retval None
mbed_official 87:085cde657901 835 */
mbed_official 87:085cde657901 836 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
mbed_official 87:085cde657901 837
mbed_official 87:085cde657901 838 /**
mbed_official 87:085cde657901 839 * @brief Enable the SD I/O Suspend command sending.
mbed_official 87:085cde657901 840 * @param None
mbed_official 87:085cde657901 841 * @retval None
mbed_official 87:085cde657901 842 */
mbed_official 87:085cde657901 843 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
mbed_official 87:085cde657901 844
mbed_official 87:085cde657901 845 /**
mbed_official 87:085cde657901 846 * @brief Disable the SD I/O Suspend command sending.
mbed_official 87:085cde657901 847 * @param None
mbed_official 87:085cde657901 848 * @retval None
mbed_official 87:085cde657901 849 */
mbed_official 87:085cde657901 850 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
mbed_official 87:085cde657901 851
mbed_official 87:085cde657901 852 /**
mbed_official 87:085cde657901 853 * @brief Enable the command completion signal.
mbed_official 87:085cde657901 854 * @param None
mbed_official 87:085cde657901 855 * @retval None
mbed_official 87:085cde657901 856 */
mbed_official 87:085cde657901 857 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
mbed_official 87:085cde657901 858
mbed_official 87:085cde657901 859 /**
mbed_official 87:085cde657901 860 * @brief Disable the command completion signal.
mbed_official 87:085cde657901 861 * @param None
mbed_official 87:085cde657901 862 * @retval None
mbed_official 87:085cde657901 863 */
mbed_official 87:085cde657901 864 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
mbed_official 87:085cde657901 865
mbed_official 87:085cde657901 866 /**
mbed_official 87:085cde657901 867 * @brief Enable the CE-ATA interrupt.
mbed_official 87:085cde657901 868 * @param None
mbed_official 87:085cde657901 869 * @retval None
mbed_official 87:085cde657901 870 */
mbed_official 87:085cde657901 871 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
mbed_official 87:085cde657901 872
mbed_official 87:085cde657901 873 /**
mbed_official 87:085cde657901 874 * @brief Disable the CE-ATA interrupt.
mbed_official 87:085cde657901 875 * @param None
mbed_official 87:085cde657901 876 * @retval None
mbed_official 87:085cde657901 877 */
mbed_official 87:085cde657901 878 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
mbed_official 87:085cde657901 879
mbed_official 87:085cde657901 880 /**
mbed_official 87:085cde657901 881 * @brief Enable send CE-ATA command (CMD61).
mbed_official 87:085cde657901 882 * @param None
mbed_official 87:085cde657901 883 * @retval None
mbed_official 87:085cde657901 884 */
mbed_official 87:085cde657901 885 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
mbed_official 87:085cde657901 886
mbed_official 87:085cde657901 887 /**
mbed_official 87:085cde657901 888 * @brief Disable send CE-ATA command (CMD61).
mbed_official 87:085cde657901 889 * @param None
mbed_official 87:085cde657901 890 * @retval None
mbed_official 87:085cde657901 891 */
mbed_official 87:085cde657901 892 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
mbed_official 87:085cde657901 893
mbed_official 87:085cde657901 894 /**
mbed_official 87:085cde657901 895 * @}
mbed_official 87:085cde657901 896 */
mbed_official 87:085cde657901 897
mbed_official 87:085cde657901 898 /* Exported functions --------------------------------------------------------*/
mbed_official 87:085cde657901 899
mbed_official 87:085cde657901 900 /* Initialization/de-initialization functions **********************************/
mbed_official 87:085cde657901 901 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
mbed_official 87:085cde657901 902
mbed_official 87:085cde657901 903 /* I/O operation functions *****************************************************/
mbed_official 87:085cde657901 904 /* Blocking mode: Polling */
mbed_official 87:085cde657901 905 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
mbed_official 87:085cde657901 906 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
mbed_official 87:085cde657901 907
mbed_official 87:085cde657901 908 /* Peripheral Control functions ************************************************/
mbed_official 87:085cde657901 909 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
mbed_official 87:085cde657901 910 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
mbed_official 87:085cde657901 911 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
mbed_official 87:085cde657901 912
mbed_official 87:085cde657901 913 /* Command path state machine (CPSM) management functions */
mbed_official 87:085cde657901 914 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
mbed_official 87:085cde657901 915 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
mbed_official 87:085cde657901 916 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
mbed_official 87:085cde657901 917
mbed_official 87:085cde657901 918 /* Data path state machine (DPSM) management functions */
mbed_official 87:085cde657901 919 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
mbed_official 87:085cde657901 920 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
mbed_official 87:085cde657901 921 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
mbed_official 87:085cde657901 922
mbed_official 87:085cde657901 923 /* SDIO IO Cards mode management functions */
mbed_official 87:085cde657901 924 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
mbed_official 87:085cde657901 925
mbed_official 87:085cde657901 926 #ifdef __cplusplus
mbed_official 87:085cde657901 927 }
mbed_official 87:085cde657901 928 #endif
mbed_official 87:085cde657901 929
mbed_official 87:085cde657901 930 #endif /* __STM32F4xx_LL_SDMMC_H */
mbed_official 87:085cde657901 931
mbed_official 87:085cde657901 932 /**
mbed_official 87:085cde657901 933 * @}
mbed_official 87:085cde657901 934 */
mbed_official 87:085cde657901 935
mbed_official 87:085cde657901 936 /**
mbed_official 87:085cde657901 937 * @}
mbed_official 87:085cde657901 938 */
mbed_official 87:085cde657901 939
mbed_official 87:085cde657901 940 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/