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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s_ex.c@87:085cde657901, 2014-02-08 (annotated)

Committer:
mbed_official
Date:
Sat Feb 08 19:45:06 2014 +0000
Revision:
87:085cde657901
Child:
106:ced8cbb51063
Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2



Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/



Add NUCLEO_F401RE, improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_i2s_ex.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 87:085cde657901 5 * @version V1.0.0RC2
mbed_official 87:085cde657901 6 * @date 04-February-2014
mbed_official 87:085cde657901 7 * @brief I2S HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of I2S extension peripheral:
mbed_official 87:085cde657901 10 * + Extension features Functions
mbed_official 87:085cde657901 11 *
mbed_official 87:085cde657901 12 @verbatim
mbed_official 87:085cde657901 13 ==============================================================================
mbed_official 87:085cde657901 14 ##### I2S Extension features #####
mbed_official 87:085cde657901 15 ==============================================================================
mbed_official 87:085cde657901 16 [..]
mbed_official 87:085cde657901 17 (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
mbed_official 87:085cde657901 18 data simultaneously using two data lines. Each SPI peripheral has an extended block
mbed_official 87:085cde657901 19 called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
mbed_official 87:085cde657901 20 (#) The extension block is not a full SPI IP, it is used only as I2S slave to
mbed_official 87:085cde657901 21 implement full duplex mode. The extension block uses the same clock sources
mbed_official 87:085cde657901 22 as its master.
mbed_official 87:085cde657901 23
mbed_official 87:085cde657901 24 (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
mbed_official 87:085cde657901 25
mbed_official 87:085cde657901 26 -@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
mbed_official 87:085cde657901 27 I2Sx can be I2S2 or I2S3.
mbed_official 87:085cde657901 28
mbed_official 87:085cde657901 29 ===============================================================================
mbed_official 87:085cde657901 30 ##### How to use this driver #####
mbed_official 87:085cde657901 31 ===============================================================================
mbed_official 87:085cde657901 32 [..]
mbed_official 87:085cde657901 33 Three mode of operations are available within this driver :
mbed_official 87:085cde657901 34
mbed_official 87:085cde657901 35 *** Polling mode IO operation ***
mbed_official 87:085cde657901 36 =================================
mbed_official 87:085cde657901 37 [..]
mbed_official 87:085cde657901 38 (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
mbed_official 87:085cde657901 39
mbed_official 87:085cde657901 40 *** Interrupt mode IO operation ***
mbed_official 87:085cde657901 41 ===================================
mbed_official 87:085cde657901 42 [..]
mbed_official 87:085cde657901 43 (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
mbed_official 87:085cde657901 44 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 45 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
mbed_official 87:085cde657901 46 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
mbed_official 87:085cde657901 47 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
mbed_official 87:085cde657901 48 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 49 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
mbed_official 87:085cde657901 50 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
mbed_official 87:085cde657901 51 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
mbed_official 87:085cde657901 52 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
mbed_official 87:085cde657901 53 add his own code by customization of function pointer HAL_I2S_ErrorCallback
mbed_official 87:085cde657901 54
mbed_official 87:085cde657901 55 *** DMA mode IO operation ***
mbed_official 87:085cde657901 56 ==============================
mbed_official 87:085cde657901 57 [..]
mbed_official 87:085cde657901 58 (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
mbed_official 87:085cde657901 59 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 60 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
mbed_official 87:085cde657901 61 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
mbed_official 87:085cde657901 62 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
mbed_official 87:085cde657901 63 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
mbed_official 87:085cde657901 64 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
mbed_official 87:085cde657901 65 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
mbed_official 87:085cde657901 66 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
mbed_official 87:085cde657901 67 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
mbed_official 87:085cde657901 68 add his own code by customization of function pointer HAL_I2S_ErrorCallback
mbed_official 87:085cde657901 69 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
mbed_official 87:085cde657901 70 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
mbed_official 87:085cde657901 71 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
mbed_official 87:085cde657901 72
mbed_official 87:085cde657901 73 @endverbatim
mbed_official 87:085cde657901 74 ******************************************************************************
mbed_official 87:085cde657901 75 * @attention
mbed_official 87:085cde657901 76 *
mbed_official 87:085cde657901 77 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 78 *
mbed_official 87:085cde657901 79 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 80 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 81 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 82 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 83 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 84 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 85 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 86 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 87 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 88 * without specific prior written permission.
mbed_official 87:085cde657901 89 *
mbed_official 87:085cde657901 90 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 91 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 92 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 93 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 94 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 95 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 96 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 97 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 98 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 99 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 100 *
mbed_official 87:085cde657901 101 ******************************************************************************
mbed_official 87:085cde657901 102 */
mbed_official 87:085cde657901 103
mbed_official 87:085cde657901 104 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 105 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 106
mbed_official 87:085cde657901 107 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 108 * @{
mbed_official 87:085cde657901 109 */
mbed_official 87:085cde657901 110
mbed_official 87:085cde657901 111 /** @defgroup I2SEx
mbed_official 87:085cde657901 112 * @brief I2S HAL module driver
mbed_official 87:085cde657901 113 * @{
mbed_official 87:085cde657901 114 */
mbed_official 87:085cde657901 115
mbed_official 87:085cde657901 116 #ifdef HAL_I2S_MODULE_ENABLED
mbed_official 87:085cde657901 117
mbed_official 87:085cde657901 118 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 119 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 120 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 121 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 122 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 123 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 124
mbed_official 87:085cde657901 125 /** @defgroup I2SEx_Private_Functions
mbed_official 87:085cde657901 126 * @{
mbed_official 87:085cde657901 127 */
mbed_official 87:085cde657901 128
mbed_official 87:085cde657901 129 /** @defgroup I2SEx_Group1 Extension features functions
mbed_official 87:085cde657901 130 * @brief Extension features functions
mbed_official 87:085cde657901 131 *
mbed_official 87:085cde657901 132 @verbatim
mbed_official 87:085cde657901 133 ===============================================================================
mbed_official 87:085cde657901 134 ##### Extension features Functions #####
mbed_official 87:085cde657901 135 ===============================================================================
mbed_official 87:085cde657901 136 [..]
mbed_official 87:085cde657901 137 This subsection provides a set of functions allowing to manage the I2S data
mbed_official 87:085cde657901 138 transfers.
mbed_official 87:085cde657901 139
mbed_official 87:085cde657901 140 (#) There is two mode of transfer:
mbed_official 87:085cde657901 141 (++) Blocking mode : The communication is performed in the polling mode.
mbed_official 87:085cde657901 142 The status of all data processing is returned by the same function
mbed_official 87:085cde657901 143 after finishing transfer.
mbed_official 87:085cde657901 144 (++) No-Blocking mode : The communication is performed using Interrupts
mbed_official 87:085cde657901 145 or DMA. These functions return the status of the transfer startup.
mbed_official 87:085cde657901 146 The end of the data processing will be indicated through the
mbed_official 87:085cde657901 147 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 87:085cde657901 148 using DMA mode.
mbed_official 87:085cde657901 149
mbed_official 87:085cde657901 150 (#) Blocking mode functions are :
mbed_official 87:085cde657901 151 (++) HAL_I2S_TransmitReceive()
mbed_official 87:085cde657901 152
mbed_official 87:085cde657901 153 (#) No-Blocking mode functions with Interrupt are :
mbed_official 87:085cde657901 154 (++) HAL_I2S_TransmitReceive_IT()
mbed_official 87:085cde657901 155
mbed_official 87:085cde657901 156 (#) No-Blocking mode functions with DMA are :
mbed_official 87:085cde657901 157 (++) HAL_I2S_TransmitReceive_DMA()
mbed_official 87:085cde657901 158
mbed_official 87:085cde657901 159 (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official 87:085cde657901 160 (++) HAL_I2S_TxCpltCallback()
mbed_official 87:085cde657901 161 (++) HAL_I2S_RxCpltCallback()
mbed_official 87:085cde657901 162 (++) HAL_I2S_ErrorCallback()
mbed_official 87:085cde657901 163
mbed_official 87:085cde657901 164 @endverbatim
mbed_official 87:085cde657901 165 * @{
mbed_official 87:085cde657901 166 */
mbed_official 87:085cde657901 167
mbed_official 87:085cde657901 168 /**
mbed_official 87:085cde657901 169 * @brief Full-Duplex Transmit/Receive data in blocking mode.
mbed_official 87:085cde657901 170 * @param hi2s: I2S handle
mbed_official 87:085cde657901 171 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
mbed_official 87:085cde657901 172 * @param pRxData: a 16-bit pointer to the Receive data buffer.
mbed_official 87:085cde657901 173 * @param Size: number of data sample to be sent:
mbed_official 87:085cde657901 174 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 87:085cde657901 175 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 87:085cde657901 176 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 87:085cde657901 177 * the Size parameter means the number of 16-bit data length.
mbed_official 87:085cde657901 178 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 179 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 87:085cde657901 180 * between Master and Slave(example: audio streaming).
mbed_official 87:085cde657901 181 * @retval HAL status
mbed_official 87:085cde657901 182 */
mbed_official 87:085cde657901 183 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 87:085cde657901 184 {
mbed_official 87:085cde657901 185 uint32_t timeout = 0;
mbed_official 87:085cde657901 186 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 187
mbed_official 87:085cde657901 188 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 87:085cde657901 189 {
mbed_official 87:085cde657901 190 return HAL_ERROR;
mbed_official 87:085cde657901 191 }
mbed_official 87:085cde657901 192
mbed_official 87:085cde657901 193 /* Check the I2S State */
mbed_official 87:085cde657901 194 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 87:085cde657901 195 {
mbed_official 87:085cde657901 196 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 197 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 198 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
mbed_official 87:085cde657901 199 is selected during the I2S configuration phase, the Size parameter means the number
mbed_official 87:085cde657901 200 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
mbed_official 87:085cde657901 201 frame is selected the Size parameter means the number of 16-bit data length. */
mbed_official 87:085cde657901 202 if((tmp1 == I2S_DATAFORMAT_24B)|| \
mbed_official 87:085cde657901 203 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 87:085cde657901 204 {
mbed_official 87:085cde657901 205 hi2s->TxXferSize = Size*2;
mbed_official 87:085cde657901 206 hi2s->TxXferCount = Size*2;
mbed_official 87:085cde657901 207 hi2s->RxXferSize = Size*2;
mbed_official 87:085cde657901 208 hi2s->RxXferCount = Size*2;
mbed_official 87:085cde657901 209 }
mbed_official 87:085cde657901 210 else
mbed_official 87:085cde657901 211 {
mbed_official 87:085cde657901 212 hi2s->TxXferSize = Size;
mbed_official 87:085cde657901 213 hi2s->TxXferCount = Size;
mbed_official 87:085cde657901 214 hi2s->RxXferSize = Size;
mbed_official 87:085cde657901 215 hi2s->RxXferCount = Size;
mbed_official 87:085cde657901 216 }
mbed_official 87:085cde657901 217
mbed_official 87:085cde657901 218 /* Process Locked */
mbed_official 87:085cde657901 219 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 220
mbed_official 87:085cde657901 221 /* Set the I2S State busy TX/RX */
mbed_official 87:085cde657901 222 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 223
mbed_official 87:085cde657901 224 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 225 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 226 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 227 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 228 {
mbed_official 87:085cde657901 229 /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
mbed_official 87:085cde657901 230 to avoid the clock de-synchronization between Master and Slave. */
mbed_official 87:085cde657901 231 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 232 {
mbed_official 87:085cde657901 233 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
mbed_official 87:085cde657901 234 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 235
mbed_official 87:085cde657901 236 /* Enable I2Sx peripheral */
mbed_official 87:085cde657901 237 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 238 }
mbed_official 87:085cde657901 239
mbed_official 87:085cde657901 240 while(hi2s->TxXferCount > 0)
mbed_official 87:085cde657901 241 {
mbed_official 87:085cde657901 242 /* Wait until TXE flag is set */
mbed_official 87:085cde657901 243 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 244 {
mbed_official 87:085cde657901 245 return HAL_TIMEOUT;
mbed_official 87:085cde657901 246 }
mbed_official 87:085cde657901 247 hi2s->Instance->DR = (*pTxData++);
mbed_official 87:085cde657901 248
mbed_official 87:085cde657901 249 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 250 timeout = HAL_GetTick() + Timeout;
mbed_official 87:085cde657901 251
mbed_official 87:085cde657901 252 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
mbed_official 87:085cde657901 253 {
mbed_official 87:085cde657901 254 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 255 {
mbed_official 87:085cde657901 256 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 257 {
mbed_official 87:085cde657901 258 /* Process Unlocked */
mbed_official 87:085cde657901 259 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 260
mbed_official 87:085cde657901 261 return HAL_TIMEOUT;
mbed_official 87:085cde657901 262 }
mbed_official 87:085cde657901 263 }
mbed_official 87:085cde657901 264 }
mbed_official 87:085cde657901 265 (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
mbed_official 87:085cde657901 266
mbed_official 87:085cde657901 267 hi2s->TxXferCount--;
mbed_official 87:085cde657901 268 hi2s->RxXferCount--;
mbed_official 87:085cde657901 269 }
mbed_official 87:085cde657901 270 }
mbed_official 87:085cde657901 271 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
mbed_official 87:085cde657901 272 else
mbed_official 87:085cde657901 273 {
mbed_official 87:085cde657901 274 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 275 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 276 {
mbed_official 87:085cde657901 277 /* Enable I2S peripheral before the I2Sext*/
mbed_official 87:085cde657901 278 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 279
mbed_official 87:085cde657901 280 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
mbed_official 87:085cde657901 281 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 282 }
mbed_official 87:085cde657901 283 else
mbed_official 87:085cde657901 284 {
mbed_official 87:085cde657901 285 /* Check if Master Receiver mode is selected */
mbed_official 87:085cde657901 286 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 87:085cde657901 287 {
mbed_official 87:085cde657901 288 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
mbed_official 87:085cde657901 289 access to the SPI_SR register. */
mbed_official 87:085cde657901 290 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 87:085cde657901 291 }
mbed_official 87:085cde657901 292 }
mbed_official 87:085cde657901 293 while(hi2s->TxXferCount > 0)
mbed_official 87:085cde657901 294 {
mbed_official 87:085cde657901 295 /* Wait until TXE flag is set */
mbed_official 87:085cde657901 296 timeout = HAL_GetTick() + Timeout;
mbed_official 87:085cde657901 297
mbed_official 87:085cde657901 298 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
mbed_official 87:085cde657901 299 {
mbed_official 87:085cde657901 300 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 301 {
mbed_official 87:085cde657901 302 if(HAL_GetTick() >= timeout)
mbed_official 87:085cde657901 303 {
mbed_official 87:085cde657901 304 /* Process Unlocked */
mbed_official 87:085cde657901 305 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 306
mbed_official 87:085cde657901 307 return HAL_TIMEOUT;
mbed_official 87:085cde657901 308 }
mbed_official 87:085cde657901 309 }
mbed_official 87:085cde657901 310 }
mbed_official 87:085cde657901 311 I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
mbed_official 87:085cde657901 312
mbed_official 87:085cde657901 313 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 314 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 315 {
mbed_official 87:085cde657901 316 return HAL_TIMEOUT;
mbed_official 87:085cde657901 317 }
mbed_official 87:085cde657901 318 (*pRxData++) = hi2s->Instance->DR;
mbed_official 87:085cde657901 319
mbed_official 87:085cde657901 320 hi2s->TxXferCount--;
mbed_official 87:085cde657901 321 hi2s->RxXferCount--;
mbed_official 87:085cde657901 322 }
mbed_official 87:085cde657901 323 }
mbed_official 87:085cde657901 324
mbed_official 87:085cde657901 325 /* Set the I2S State ready */
mbed_official 87:085cde657901 326 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 87:085cde657901 327
mbed_official 87:085cde657901 328 /* Process Unlocked */
mbed_official 87:085cde657901 329 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 330
mbed_official 87:085cde657901 331 return HAL_OK;
mbed_official 87:085cde657901 332 }
mbed_official 87:085cde657901 333 else
mbed_official 87:085cde657901 334 {
mbed_official 87:085cde657901 335 return HAL_BUSY;
mbed_official 87:085cde657901 336 }
mbed_official 87:085cde657901 337 }
mbed_official 87:085cde657901 338
mbed_official 87:085cde657901 339 /**
mbed_official 87:085cde657901 340 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
mbed_official 87:085cde657901 341 * @param hi2s: I2S handle
mbed_official 87:085cde657901 342 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
mbed_official 87:085cde657901 343 * @param pRxData: a 16-bit pointer to the Receive data buffer.
mbed_official 87:085cde657901 344 * @param Size: number of data sample to be sent:
mbed_official 87:085cde657901 345 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 87:085cde657901 346 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 87:085cde657901 347 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 87:085cde657901 348 * the Size parameter means the number of 16-bit data length.
mbed_official 87:085cde657901 349 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 350 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 87:085cde657901 351 * between Master and Slave(example: audio streaming).
mbed_official 87:085cde657901 352 * @retval HAL status
mbed_official 87:085cde657901 353 */
mbed_official 87:085cde657901 354 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
mbed_official 87:085cde657901 355 {
mbed_official 87:085cde657901 356 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 357
mbed_official 87:085cde657901 358 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 87:085cde657901 359 {
mbed_official 87:085cde657901 360 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 87:085cde657901 361 {
mbed_official 87:085cde657901 362 return HAL_ERROR;
mbed_official 87:085cde657901 363 }
mbed_official 87:085cde657901 364
mbed_official 87:085cde657901 365 hi2s->pTxBuffPtr = pTxData;
mbed_official 87:085cde657901 366 hi2s->pRxBuffPtr = pRxData;
mbed_official 87:085cde657901 367
mbed_official 87:085cde657901 368 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 369 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 370 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
mbed_official 87:085cde657901 371 is selected during the I2S configuration phase, the Size parameter means the number
mbed_official 87:085cde657901 372 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
mbed_official 87:085cde657901 373 frame is selected the Size parameter means the number of 16-bit data length. */
mbed_official 87:085cde657901 374 if((tmp1 == I2S_DATAFORMAT_24B)||\
mbed_official 87:085cde657901 375 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 87:085cde657901 376 {
mbed_official 87:085cde657901 377 hi2s->TxXferSize = Size*2;
mbed_official 87:085cde657901 378 hi2s->TxXferCount = Size*2;
mbed_official 87:085cde657901 379 hi2s->RxXferSize = Size*2;
mbed_official 87:085cde657901 380 hi2s->RxXferCount = Size*2;
mbed_official 87:085cde657901 381 }
mbed_official 87:085cde657901 382 else
mbed_official 87:085cde657901 383 {
mbed_official 87:085cde657901 384 hi2s->TxXferSize = Size;
mbed_official 87:085cde657901 385 hi2s->TxXferCount = Size;
mbed_official 87:085cde657901 386 hi2s->RxXferSize = Size;
mbed_official 87:085cde657901 387 hi2s->RxXferCount = Size;
mbed_official 87:085cde657901 388 }
mbed_official 87:085cde657901 389
mbed_official 87:085cde657901 390 /* Process Locked */
mbed_official 87:085cde657901 391 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 392
mbed_official 87:085cde657901 393 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 394 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 87:085cde657901 395
mbed_official 87:085cde657901 396 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 397 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 398 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 399 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 400 {
mbed_official 87:085cde657901 401 /* Enable I2Sext RXNE and ERR interrupts */
mbed_official 87:085cde657901 402 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
mbed_official 87:085cde657901 403
mbed_official 87:085cde657901 404 /* Enable I2Sx TXE and ERR interrupts */
mbed_official 87:085cde657901 405 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
mbed_official 87:085cde657901 406
mbed_official 87:085cde657901 407 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 408 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 409 {
mbed_official 87:085cde657901 410 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
mbed_official 87:085cde657901 411 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 412
mbed_official 87:085cde657901 413 /* Enable I2Sx peripheral */
mbed_official 87:085cde657901 414 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 415 }
mbed_official 87:085cde657901 416 }
mbed_official 87:085cde657901 417 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
mbed_official 87:085cde657901 418 else
mbed_official 87:085cde657901 419 {
mbed_official 87:085cde657901 420 /* Enable I2Sext TXE and ERR interrupts */
mbed_official 87:085cde657901 421 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
mbed_official 87:085cde657901 422
mbed_official 87:085cde657901 423 /* Enable I2Sext RXNE and ERR interrupts */
mbed_official 87:085cde657901 424 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
mbed_official 87:085cde657901 425
mbed_official 87:085cde657901 426 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 427 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 428 {
mbed_official 87:085cde657901 429 /* Check if the I2S_MODE_MASTER_RX is selected */
mbed_official 87:085cde657901 430 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 87:085cde657901 431 {
mbed_official 87:085cde657901 432 /* Prepare the First Data before enabling the I2S */
mbed_official 87:085cde657901 433 if(hi2s->TxXferCount != 0)
mbed_official 87:085cde657901 434 {
mbed_official 87:085cde657901 435 /* Transmit First data */
mbed_official 87:085cde657901 436 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
mbed_official 87:085cde657901 437 hi2s->TxXferCount--;
mbed_official 87:085cde657901 438
mbed_official 87:085cde657901 439 if(hi2s->TxXferCount == 0)
mbed_official 87:085cde657901 440 {
mbed_official 87:085cde657901 441 /* Disable I2Sext TXE interrupt */
mbed_official 87:085cde657901 442 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
mbed_official 87:085cde657901 443 }
mbed_official 87:085cde657901 444 }
mbed_official 87:085cde657901 445 }
mbed_official 87:085cde657901 446 /* Enable I2S peripheral */
mbed_official 87:085cde657901 447 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 448
mbed_official 87:085cde657901 449 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
mbed_official 87:085cde657901 450 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 451 }
mbed_official 87:085cde657901 452 }
mbed_official 87:085cde657901 453 /* Process Unlocked */
mbed_official 87:085cde657901 454 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 455
mbed_official 87:085cde657901 456 return HAL_OK;
mbed_official 87:085cde657901 457 }
mbed_official 87:085cde657901 458 else
mbed_official 87:085cde657901 459 {
mbed_official 87:085cde657901 460 return HAL_BUSY;
mbed_official 87:085cde657901 461 }
mbed_official 87:085cde657901 462 }
mbed_official 87:085cde657901 463
mbed_official 87:085cde657901 464
mbed_official 87:085cde657901 465 /**
mbed_official 87:085cde657901 466 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
mbed_official 87:085cde657901 467 * @param hi2s: I2S handle
mbed_official 87:085cde657901 468 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
mbed_official 87:085cde657901 469 * @param pRxData: a 16-bit pointer to the Receive data buffer.
mbed_official 87:085cde657901 470 * @param Size: number of data sample to be sent:
mbed_official 87:085cde657901 471 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
mbed_official 87:085cde657901 472 * configuration phase, the Size parameter means the number of 16-bit data length
mbed_official 87:085cde657901 473 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
mbed_official 87:085cde657901 474 * the Size parameter means the number of 16-bit data length.
mbed_official 87:085cde657901 475 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 476 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
mbed_official 87:085cde657901 477 * between Master and Slave(example: audio streaming).
mbed_official 87:085cde657901 478 * @retval HAL status
mbed_official 87:085cde657901 479 */
mbed_official 87:085cde657901 480 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
mbed_official 87:085cde657901 481 {
mbed_official 87:085cde657901 482 uint32_t *tmp;
mbed_official 87:085cde657901 483 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 484
mbed_official 87:085cde657901 485 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 87:085cde657901 486 {
mbed_official 87:085cde657901 487 return HAL_ERROR;
mbed_official 87:085cde657901 488 }
mbed_official 87:085cde657901 489
mbed_official 87:085cde657901 490 if(hi2s->State == HAL_I2S_STATE_READY)
mbed_official 87:085cde657901 491 {
mbed_official 87:085cde657901 492 hi2s->pTxBuffPtr = pTxData;
mbed_official 87:085cde657901 493 hi2s->pRxBuffPtr = pRxData;
mbed_official 87:085cde657901 494
mbed_official 87:085cde657901 495 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 496 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
mbed_official 87:085cde657901 497 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
mbed_official 87:085cde657901 498 is selected during the I2S configuration phase, the Size parameter means the number
mbed_official 87:085cde657901 499 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
mbed_official 87:085cde657901 500 frame is selected the Size parameter means the number of 16-bit data length. */
mbed_official 87:085cde657901 501 if((tmp1 == I2S_DATAFORMAT_24B)||\
mbed_official 87:085cde657901 502 (tmp2 == I2S_DATAFORMAT_32B))
mbed_official 87:085cde657901 503 {
mbed_official 87:085cde657901 504 hi2s->TxXferSize = Size*2;
mbed_official 87:085cde657901 505 hi2s->TxXferCount = Size*2;
mbed_official 87:085cde657901 506 hi2s->RxXferSize = Size*2;
mbed_official 87:085cde657901 507 hi2s->RxXferCount = Size*2;
mbed_official 87:085cde657901 508 }
mbed_official 87:085cde657901 509 else
mbed_official 87:085cde657901 510 {
mbed_official 87:085cde657901 511 hi2s->TxXferSize = Size;
mbed_official 87:085cde657901 512 hi2s->TxXferCount = Size;
mbed_official 87:085cde657901 513 hi2s->RxXferSize = Size;
mbed_official 87:085cde657901 514 hi2s->RxXferCount = Size;
mbed_official 87:085cde657901 515 }
mbed_official 87:085cde657901 516
mbed_official 87:085cde657901 517 /* Process Locked */
mbed_official 87:085cde657901 518 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 519
mbed_official 87:085cde657901 520 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 521 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
mbed_official 87:085cde657901 522
mbed_official 87:085cde657901 523 /* Set the I2S Rx DMA Half transfert complete callback */
mbed_official 87:085cde657901 524 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
mbed_official 87:085cde657901 525
mbed_official 87:085cde657901 526 /* Set the I2S Rx DMA transfert complete callback */
mbed_official 87:085cde657901 527 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
mbed_official 87:085cde657901 528
mbed_official 87:085cde657901 529 /* Set the I2S Rx DMA error callback */
mbed_official 87:085cde657901 530 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
mbed_official 87:085cde657901 531
mbed_official 87:085cde657901 532 /* Set the I2S Tx DMA Half transfert complete callback */
mbed_official 87:085cde657901 533 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
mbed_official 87:085cde657901 534
mbed_official 87:085cde657901 535 /* Set the I2S Tx DMA transfert complete callback */
mbed_official 87:085cde657901 536 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
mbed_official 87:085cde657901 537
mbed_official 87:085cde657901 538 /* Set the I2S Tx DMA error callback */
mbed_official 87:085cde657901 539 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
mbed_official 87:085cde657901 540
mbed_official 87:085cde657901 541 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 542 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 543 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 544 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 545 {
mbed_official 87:085cde657901 546 /* Enable the Rx DMA Stream */
mbed_official 87:085cde657901 547 tmp = (uint32_t*)&pRxData;
mbed_official 87:085cde657901 548 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
mbed_official 87:085cde657901 549
mbed_official 87:085cde657901 550 /* Enable Rx DMA Request */
mbed_official 87:085cde657901 551 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 87:085cde657901 552
mbed_official 87:085cde657901 553 /* Enable the Tx DMA Stream */
mbed_official 87:085cde657901 554 tmp = (uint32_t*)&pTxData;
mbed_official 87:085cde657901 555 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
mbed_official 87:085cde657901 556
mbed_official 87:085cde657901 557 /* Enable Tx DMA Request */
mbed_official 87:085cde657901 558 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 87:085cde657901 559
mbed_official 87:085cde657901 560 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 561 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 562 {
mbed_official 87:085cde657901 563 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
mbed_official 87:085cde657901 564 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 565
mbed_official 87:085cde657901 566 /* Enable I2S peripheral after the I2Sext */
mbed_official 87:085cde657901 567 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 568 }
mbed_official 87:085cde657901 569 }
mbed_official 87:085cde657901 570 else
mbed_official 87:085cde657901 571 {
mbed_official 87:085cde657901 572 /* Enable the Tx DMA Stream */
mbed_official 87:085cde657901 573 tmp = (uint32_t*)&pTxData;
mbed_official 87:085cde657901 574 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
mbed_official 87:085cde657901 575
mbed_official 87:085cde657901 576 /* Enable Tx DMA Request */
mbed_official 87:085cde657901 577 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 87:085cde657901 578
mbed_official 87:085cde657901 579 /* Enable the Rx DMA Stream */
mbed_official 87:085cde657901 580 tmp = (uint32_t*)&pRxData;
mbed_official 87:085cde657901 581 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
mbed_official 87:085cde657901 582
mbed_official 87:085cde657901 583 /* Enable Rx DMA Request */
mbed_official 87:085cde657901 584 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 87:085cde657901 585
mbed_official 87:085cde657901 586 /* Check if the I2S is already enabled */
mbed_official 87:085cde657901 587 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
mbed_official 87:085cde657901 588 {
mbed_official 87:085cde657901 589 /* Enable I2S peripheral before the I2Sext */
mbed_official 87:085cde657901 590 __HAL_I2S_ENABLE(hi2s);
mbed_official 87:085cde657901 591
mbed_official 87:085cde657901 592 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
mbed_official 87:085cde657901 593 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
mbed_official 87:085cde657901 594 }
mbed_official 87:085cde657901 595 else
mbed_official 87:085cde657901 596 {
mbed_official 87:085cde657901 597 /* Check if Master Receiver mode is selected */
mbed_official 87:085cde657901 598 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
mbed_official 87:085cde657901 599 {
mbed_official 87:085cde657901 600 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
mbed_official 87:085cde657901 601 access to the SPI_SR register. */
mbed_official 87:085cde657901 602 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
mbed_official 87:085cde657901 603 }
mbed_official 87:085cde657901 604 }
mbed_official 87:085cde657901 605 }
mbed_official 87:085cde657901 606
mbed_official 87:085cde657901 607 /* Process Unlocked */
mbed_official 87:085cde657901 608 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 609
mbed_official 87:085cde657901 610 return HAL_OK;
mbed_official 87:085cde657901 611 }
mbed_official 87:085cde657901 612 else
mbed_official 87:085cde657901 613 {
mbed_official 87:085cde657901 614 return HAL_BUSY;
mbed_official 87:085cde657901 615 }
mbed_official 87:085cde657901 616 }
mbed_official 87:085cde657901 617
mbed_official 87:085cde657901 618 /**
mbed_official 87:085cde657901 619 * @}
mbed_official 87:085cde657901 620 */
mbed_official 87:085cde657901 621
mbed_official 87:085cde657901 622 /**
mbed_official 87:085cde657901 623 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
mbed_official 87:085cde657901 624 * @param hi2s: I2S handle
mbed_official 87:085cde657901 625 * @retval HAL status
mbed_official 87:085cde657901 626 */
mbed_official 87:085cde657901 627 HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
mbed_official 87:085cde657901 628 {
mbed_official 87:085cde657901 629 uint32_t tmp1 = 0, tmp2 = 0;
mbed_official 87:085cde657901 630
mbed_official 87:085cde657901 631 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
mbed_official 87:085cde657901 632 {
mbed_official 87:085cde657901 633 /* Process Locked */
mbed_official 87:085cde657901 634 __HAL_LOCK(hi2s);
mbed_official 87:085cde657901 635
mbed_official 87:085cde657901 636 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 637 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
mbed_official 87:085cde657901 638 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
mbed_official 87:085cde657901 639 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
mbed_official 87:085cde657901 640 {
mbed_official 87:085cde657901 641 if(hi2s->TxXferCount != 0)
mbed_official 87:085cde657901 642 {
mbed_official 87:085cde657901 643 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
mbed_official 87:085cde657901 644 {
mbed_official 87:085cde657901 645 /* Transmit data */
mbed_official 87:085cde657901 646 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
mbed_official 87:085cde657901 647 hi2s->TxXferCount--;
mbed_official 87:085cde657901 648
mbed_official 87:085cde657901 649 if(hi2s->TxXferCount == 0)
mbed_official 87:085cde657901 650 {
mbed_official 87:085cde657901 651 /* Disable TXE interrupt */
mbed_official 87:085cde657901 652 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
mbed_official 87:085cde657901 653 }
mbed_official 87:085cde657901 654 }
mbed_official 87:085cde657901 655 }
mbed_official 87:085cde657901 656
mbed_official 87:085cde657901 657 if(hi2s->RxXferCount != 0)
mbed_official 87:085cde657901 658 {
mbed_official 87:085cde657901 659 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
mbed_official 87:085cde657901 660 {
mbed_official 87:085cde657901 661 /* Receive data */
mbed_official 87:085cde657901 662 (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
mbed_official 87:085cde657901 663 hi2s->RxXferCount--;
mbed_official 87:085cde657901 664
mbed_official 87:085cde657901 665 if(hi2s->RxXferCount == 0)
mbed_official 87:085cde657901 666 {
mbed_official 87:085cde657901 667 /* Disable I2Sext RXNE interrupt */
mbed_official 87:085cde657901 668 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
mbed_official 87:085cde657901 669 }
mbed_official 87:085cde657901 670 }
mbed_official 87:085cde657901 671 }
mbed_official 87:085cde657901 672 }
mbed_official 87:085cde657901 673 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
mbed_official 87:085cde657901 674 else
mbed_official 87:085cde657901 675 {
mbed_official 87:085cde657901 676 if(hi2s->TxXferCount != 0)
mbed_official 87:085cde657901 677 {
mbed_official 87:085cde657901 678 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
mbed_official 87:085cde657901 679 {
mbed_official 87:085cde657901 680 /* Transmit data */
mbed_official 87:085cde657901 681 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
mbed_official 87:085cde657901 682 hi2s->TxXferCount--;
mbed_official 87:085cde657901 683
mbed_official 87:085cde657901 684 if(hi2s->TxXferCount == 0)
mbed_official 87:085cde657901 685 {
mbed_official 87:085cde657901 686 /* Disable I2Sext TXE interrupt */
mbed_official 87:085cde657901 687 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
mbed_official 87:085cde657901 688
mbed_official 87:085cde657901 689 HAL_I2S_TxCpltCallback(hi2s);
mbed_official 87:085cde657901 690 }
mbed_official 87:085cde657901 691 }
mbed_official 87:085cde657901 692 }
mbed_official 87:085cde657901 693 if(hi2s->RxXferCount != 0)
mbed_official 87:085cde657901 694 {
mbed_official 87:085cde657901 695 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
mbed_official 87:085cde657901 696 {
mbed_official 87:085cde657901 697 /* Receive data */
mbed_official 87:085cde657901 698 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
mbed_official 87:085cde657901 699 hi2s->RxXferCount--;
mbed_official 87:085cde657901 700
mbed_official 87:085cde657901 701 if(hi2s->RxXferCount == 0)
mbed_official 87:085cde657901 702 {
mbed_official 87:085cde657901 703 /* Disable RXNE interrupt */
mbed_official 87:085cde657901 704 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
mbed_official 87:085cde657901 705
mbed_official 87:085cde657901 706 HAL_I2S_RxCpltCallback(hi2s);
mbed_official 87:085cde657901 707 }
mbed_official 87:085cde657901 708 }
mbed_official 87:085cde657901 709 }
mbed_official 87:085cde657901 710 }
mbed_official 87:085cde657901 711
mbed_official 87:085cde657901 712 tmp1 = hi2s->RxXferCount;
mbed_official 87:085cde657901 713 tmp2 = hi2s->TxXferCount;
mbed_official 87:085cde657901 714 if((tmp1 == 0) && (tmp2 == 0))
mbed_official 87:085cde657901 715 {
mbed_official 87:085cde657901 716 /* Disable I2Sx ERR interrupt */
mbed_official 87:085cde657901 717 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
mbed_official 87:085cde657901 718 /* Disable I2Sext ERR interrupt */
mbed_official 87:085cde657901 719 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
mbed_official 87:085cde657901 720
mbed_official 87:085cde657901 721 hi2s->State = HAL_I2S_STATE_READY;
mbed_official 87:085cde657901 722 }
mbed_official 87:085cde657901 723
mbed_official 87:085cde657901 724 /* Process Unlocked */
mbed_official 87:085cde657901 725 __HAL_UNLOCK(hi2s);
mbed_official 87:085cde657901 726
mbed_official 87:085cde657901 727 return HAL_OK;
mbed_official 87:085cde657901 728 }
mbed_official 87:085cde657901 729 else
mbed_official 87:085cde657901 730 {
mbed_official 87:085cde657901 731 return HAL_BUSY;
mbed_official 87:085cde657901 732 }
mbed_official 87:085cde657901 733 }
mbed_official 87:085cde657901 734
mbed_official 87:085cde657901 735 /**
mbed_official 87:085cde657901 736 * @}
mbed_official 87:085cde657901 737 */
mbed_official 87:085cde657901 738
mbed_official 87:085cde657901 739 #endif /* HAL_I2S_MODULE_ENABLED */
mbed_official 87:085cde657901 740 /**
mbed_official 87:085cde657901 741 * @}
mbed_official 87:085cde657901 742 */
mbed_official 87:085cde657901 743
mbed_official 87:085cde657901 744 /**
mbed_official 87:085cde657901 745 * @}
mbed_official 87:085cde657901 746 */
mbed_official 87:085cde657901 747
mbed_official 87:085cde657901 748 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/