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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_NUCLEO_F446RE/stm32f446xx.h@553:063b9f2f393c, 2015-06-01 (annotated)

Committer:
mbed_official
Date:
Mon Jun 01 10:30:08 2015 +0100
Revision:
553:063b9f2f393c
Child:
613:bc40b8d2aec4
Synchronized with git revision 7ab478cf5c5cb75ac77f65a4ea501ce34ce3bcdf



Full URL: https://github.com/mbedmicro/mbed/commit/7ab478cf5c5cb75ac77f65a4ea501ce34ce3bcdf/



Nucleo_F446RE - adding target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 553:063b9f2f393c 1 /**
mbed_official 553:063b9f2f393c 2 ******************************************************************************
mbed_official 553:063b9f2f393c 3 * @file stm32f446xx.h
mbed_official 553:063b9f2f393c 4 * @author MCD Application Team
mbed_official 553:063b9f2f393c 5 * @version V2.3.0
mbed_official 553:063b9f2f393c 6 * @date 02-March-2015
mbed_official 553:063b9f2f393c 7 * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File.
mbed_official 553:063b9f2f393c 8 *
mbed_official 553:063b9f2f393c 9 * This file contains:
mbed_official 553:063b9f2f393c 10 * - Data structures and the address mapping for all peripherals
mbed_official 553:063b9f2f393c 11 * - Peripheral's registers declarations and bits definition
mbed_official 553:063b9f2f393c 12 * - Macros to access peripheral’s registers hardware
mbed_official 553:063b9f2f393c 13 *
mbed_official 553:063b9f2f393c 14 ******************************************************************************
mbed_official 553:063b9f2f393c 15 * @attention
mbed_official 553:063b9f2f393c 16 *
mbed_official 553:063b9f2f393c 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 553:063b9f2f393c 18 *
mbed_official 553:063b9f2f393c 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 553:063b9f2f393c 20 * are permitted provided that the following conditions are met:
mbed_official 553:063b9f2f393c 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 553:063b9f2f393c 22 * this list of conditions and the following disclaimer.
mbed_official 553:063b9f2f393c 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 553:063b9f2f393c 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 553:063b9f2f393c 25 * and/or other materials provided with the distribution.
mbed_official 553:063b9f2f393c 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 553:063b9f2f393c 27 * may be used to endorse or promote products derived from this software
mbed_official 553:063b9f2f393c 28 * without specific prior written permission.
mbed_official 553:063b9f2f393c 29 *
mbed_official 553:063b9f2f393c 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 553:063b9f2f393c 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 553:063b9f2f393c 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 553:063b9f2f393c 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 553:063b9f2f393c 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 553:063b9f2f393c 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 553:063b9f2f393c 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 553:063b9f2f393c 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 553:063b9f2f393c 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 553:063b9f2f393c 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 553:063b9f2f393c 40 *
mbed_official 553:063b9f2f393c 41 ******************************************************************************
mbed_official 553:063b9f2f393c 42 */
mbed_official 553:063b9f2f393c 43
mbed_official 553:063b9f2f393c 44 /** @addtogroup CMSIS_Device
mbed_official 553:063b9f2f393c 45 * @{
mbed_official 553:063b9f2f393c 46 */
mbed_official 553:063b9f2f393c 47
mbed_official 553:063b9f2f393c 48 /** @addtogroup stm32f446xx
mbed_official 553:063b9f2f393c 49 * @{
mbed_official 553:063b9f2f393c 50 */
mbed_official 553:063b9f2f393c 51
mbed_official 553:063b9f2f393c 52 #ifndef __STM32F446xx_H
mbed_official 553:063b9f2f393c 53 #define __STM32F446xx_H
mbed_official 553:063b9f2f393c 54
mbed_official 553:063b9f2f393c 55 #ifdef __cplusplus
mbed_official 553:063b9f2f393c 56 extern "C" {
mbed_official 553:063b9f2f393c 57 #endif /* __cplusplus */
mbed_official 553:063b9f2f393c 58
mbed_official 553:063b9f2f393c 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 553:063b9f2f393c 60 * @{
mbed_official 553:063b9f2f393c 61 */
mbed_official 553:063b9f2f393c 62
mbed_official 553:063b9f2f393c 63 /**
mbed_official 553:063b9f2f393c 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 553:063b9f2f393c 65 */
mbed_official 553:063b9f2f393c 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 553:063b9f2f393c 67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
mbed_official 553:063b9f2f393c 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
mbed_official 553:063b9f2f393c 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 553:063b9f2f393c 70 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 553:063b9f2f393c 71
mbed_official 553:063b9f2f393c 72 /**
mbed_official 553:063b9f2f393c 73 * @}
mbed_official 553:063b9f2f393c 74 */
mbed_official 553:063b9f2f393c 75
mbed_official 553:063b9f2f393c 76 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 553:063b9f2f393c 77 * @{
mbed_official 553:063b9f2f393c 78 */
mbed_official 553:063b9f2f393c 79
mbed_official 553:063b9f2f393c 80 /**
mbed_official 553:063b9f2f393c 81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
mbed_official 553:063b9f2f393c 82 * in @ref Library_configuration_section
mbed_official 553:063b9f2f393c 83 */
mbed_official 553:063b9f2f393c 84 typedef enum
mbed_official 553:063b9f2f393c 85 {
mbed_official 553:063b9f2f393c 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 553:063b9f2f393c 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 553:063b9f2f393c 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 553:063b9f2f393c 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 553:063b9f2f393c 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 553:063b9f2f393c 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 553:063b9f2f393c 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 553:063b9f2f393c 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 553:063b9f2f393c 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 553:063b9f2f393c 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 553:063b9f2f393c 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 553:063b9f2f393c 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 553:063b9f2f393c 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 553:063b9f2f393c 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 553:063b9f2f393c 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 553:063b9f2f393c 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 553:063b9f2f393c 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 553:063b9f2f393c 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 553:063b9f2f393c 104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 553:063b9f2f393c 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 553:063b9f2f393c 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 553:063b9f2f393c 107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 553:063b9f2f393c 108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 553:063b9f2f393c 109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 553:063b9f2f393c 110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 553:063b9f2f393c 111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 553:063b9f2f393c 112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 553:063b9f2f393c 113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 553:063b9f2f393c 114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
mbed_official 553:063b9f2f393c 115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
mbed_official 553:063b9f2f393c 116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
mbed_official 553:063b9f2f393c 117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 553:063b9f2f393c 118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 553:063b9f2f393c 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 553:063b9f2f393c 120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 553:063b9f2f393c 121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
mbed_official 553:063b9f2f393c 122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 553:063b9f2f393c 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 553:063b9f2f393c 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 553:063b9f2f393c 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 553:063b9f2f393c 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 553:063b9f2f393c 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 553:063b9f2f393c 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 553:063b9f2f393c 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 553:063b9f2f393c 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 553:063b9f2f393c 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 553:063b9f2f393c 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 553:063b9f2f393c 133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 553:063b9f2f393c 134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 553:063b9f2f393c 135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 553:063b9f2f393c 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 553:063b9f2f393c 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 553:063b9f2f393c 138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
mbed_official 553:063b9f2f393c 139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
mbed_official 553:063b9f2f393c 140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
mbed_official 553:063b9f2f393c 141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
mbed_official 553:063b9f2f393c 142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
mbed_official 553:063b9f2f393c 143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 553:063b9f2f393c 144 FMC_IRQn = 48, /*!< FMC global Interrupt */
mbed_official 553:063b9f2f393c 145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
mbed_official 553:063b9f2f393c 146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 553:063b9f2f393c 147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 553:063b9f2f393c 148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
mbed_official 553:063b9f2f393c 149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
mbed_official 553:063b9f2f393c 150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 553:063b9f2f393c 151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
mbed_official 553:063b9f2f393c 152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 553:063b9f2f393c 153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 553:063b9f2f393c 154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 553:063b9f2f393c 155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 553:063b9f2f393c 156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 553:063b9f2f393c 157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
mbed_official 553:063b9f2f393c 158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
mbed_official 553:063b9f2f393c 159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
mbed_official 553:063b9f2f393c 160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
mbed_official 553:063b9f2f393c 161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
mbed_official 553:063b9f2f393c 162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 553:063b9f2f393c 163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 553:063b9f2f393c 164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 553:063b9f2f393c 165 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 553:063b9f2f393c 166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 553:063b9f2f393c 167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 553:063b9f2f393c 168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
mbed_official 553:063b9f2f393c 169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
mbed_official 553:063b9f2f393c 170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
mbed_official 553:063b9f2f393c 171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
mbed_official 553:063b9f2f393c 172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
mbed_official 553:063b9f2f393c 173 FPU_IRQn = 81, /*!< FPU global interrupt */
mbed_official 553:063b9f2f393c 174 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
mbed_official 553:063b9f2f393c 175 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
mbed_official 553:063b9f2f393c 176 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
mbed_official 553:063b9f2f393c 177 QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
mbed_official 553:063b9f2f393c 178 CEC_IRQn = 93, /*!< CEC global Interrupt */
mbed_official 553:063b9f2f393c 179 SPDIF_RX_IRQn = 94, /*!< SPDIF-RX global Interrupt */
mbed_official 553:063b9f2f393c 180 FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
mbed_official 553:063b9f2f393c 181 FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
mbed_official 553:063b9f2f393c 182 } IRQn_Type;
mbed_official 553:063b9f2f393c 183
mbed_official 553:063b9f2f393c 184 /**
mbed_official 553:063b9f2f393c 185 * @}
mbed_official 553:063b9f2f393c 186 */
mbed_official 553:063b9f2f393c 187
mbed_official 553:063b9f2f393c 188 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 553:063b9f2f393c 189 #include "system_stm32f4xx.h"
mbed_official 553:063b9f2f393c 190 #include <stdint.h>
mbed_official 553:063b9f2f393c 191
mbed_official 553:063b9f2f393c 192 /** @addtogroup Peripheral_registers_structures
mbed_official 553:063b9f2f393c 193 * @{
mbed_official 553:063b9f2f393c 194 */
mbed_official 553:063b9f2f393c 195
mbed_official 553:063b9f2f393c 196 /**
mbed_official 553:063b9f2f393c 197 * @brief Analog to Digital Converter
mbed_official 553:063b9f2f393c 198 */
mbed_official 553:063b9f2f393c 199
mbed_official 553:063b9f2f393c 200 typedef struct
mbed_official 553:063b9f2f393c 201 {
mbed_official 553:063b9f2f393c 202 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 203 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 204 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 205 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 206 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 207 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 208 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 209 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 210 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 211 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 212 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 213 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 553:063b9f2f393c 214 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 553:063b9f2f393c 215 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 553:063b9f2f393c 216 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 553:063b9f2f393c 217 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 553:063b9f2f393c 218 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 553:063b9f2f393c 219 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 553:063b9f2f393c 220 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 553:063b9f2f393c 221 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 553:063b9f2f393c 222 } ADC_TypeDef;
mbed_official 553:063b9f2f393c 223
mbed_official 553:063b9f2f393c 224 typedef struct
mbed_official 553:063b9f2f393c 225 {
mbed_official 553:063b9f2f393c 226 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 553:063b9f2f393c 227 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 553:063b9f2f393c 228 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 553:063b9f2f393c 229 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 553:063b9f2f393c 230 } ADC_Common_TypeDef;
mbed_official 553:063b9f2f393c 231
mbed_official 553:063b9f2f393c 232
mbed_official 553:063b9f2f393c 233 /**
mbed_official 553:063b9f2f393c 234 * @brief Controller Area Network TxMailBox
mbed_official 553:063b9f2f393c 235 */
mbed_official 553:063b9f2f393c 236
mbed_official 553:063b9f2f393c 237 typedef struct
mbed_official 553:063b9f2f393c 238 {
mbed_official 553:063b9f2f393c 239 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 553:063b9f2f393c 240 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 553:063b9f2f393c 241 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 553:063b9f2f393c 242 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 553:063b9f2f393c 243 } CAN_TxMailBox_TypeDef;
mbed_official 553:063b9f2f393c 244
mbed_official 553:063b9f2f393c 245 /**
mbed_official 553:063b9f2f393c 246 * @brief Controller Area Network FIFOMailBox
mbed_official 553:063b9f2f393c 247 */
mbed_official 553:063b9f2f393c 248
mbed_official 553:063b9f2f393c 249 typedef struct
mbed_official 553:063b9f2f393c 250 {
mbed_official 553:063b9f2f393c 251 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 553:063b9f2f393c 252 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 553:063b9f2f393c 253 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 553:063b9f2f393c 254 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 553:063b9f2f393c 255 } CAN_FIFOMailBox_TypeDef;
mbed_official 553:063b9f2f393c 256
mbed_official 553:063b9f2f393c 257 /**
mbed_official 553:063b9f2f393c 258 * @brief Controller Area Network FilterRegister
mbed_official 553:063b9f2f393c 259 */
mbed_official 553:063b9f2f393c 260
mbed_official 553:063b9f2f393c 261 typedef struct
mbed_official 553:063b9f2f393c 262 {
mbed_official 553:063b9f2f393c 263 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 553:063b9f2f393c 264 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 553:063b9f2f393c 265 } CAN_FilterRegister_TypeDef;
mbed_official 553:063b9f2f393c 266
mbed_official 553:063b9f2f393c 267 /**
mbed_official 553:063b9f2f393c 268 * @brief Controller Area Network
mbed_official 553:063b9f2f393c 269 */
mbed_official 553:063b9f2f393c 270
mbed_official 553:063b9f2f393c 271 typedef struct
mbed_official 553:063b9f2f393c 272 {
mbed_official 553:063b9f2f393c 273 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 274 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 275 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 276 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 277 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 278 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 279 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 280 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 281 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 553:063b9f2f393c 282 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 553:063b9f2f393c 283 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 553:063b9f2f393c 284 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 553:063b9f2f393c 285 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 553:063b9f2f393c 286 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 553:063b9f2f393c 287 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 553:063b9f2f393c 288 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 553:063b9f2f393c 289 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 553:063b9f2f393c 290 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 553:063b9f2f393c 291 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 553:063b9f2f393c 292 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 553:063b9f2f393c 293 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 553:063b9f2f393c 294 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 553:063b9f2f393c 295 } CAN_TypeDef;
mbed_official 553:063b9f2f393c 296
mbed_official 553:063b9f2f393c 297 /**
mbed_official 553:063b9f2f393c 298 * @brief Consumer Electronics Control
mbed_official 553:063b9f2f393c 299 */
mbed_official 553:063b9f2f393c 300
mbed_official 553:063b9f2f393c 301 typedef struct
mbed_official 553:063b9f2f393c 302 {
mbed_official 553:063b9f2f393c 303 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
mbed_official 553:063b9f2f393c 304 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
mbed_official 553:063b9f2f393c 305 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
mbed_official 553:063b9f2f393c 306 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
mbed_official 553:063b9f2f393c 307 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
mbed_official 553:063b9f2f393c 308 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
mbed_official 553:063b9f2f393c 309 }CEC_TypeDef;
mbed_official 553:063b9f2f393c 310
mbed_official 553:063b9f2f393c 311 /**
mbed_official 553:063b9f2f393c 312 * @brief CRC calculation unit
mbed_official 553:063b9f2f393c 313 */
mbed_official 553:063b9f2f393c 314
mbed_official 553:063b9f2f393c 315 typedef struct
mbed_official 553:063b9f2f393c 316 {
mbed_official 553:063b9f2f393c 317 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 318 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 319 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 553:063b9f2f393c 320 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 553:063b9f2f393c 321 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 322 } CRC_TypeDef;
mbed_official 553:063b9f2f393c 323
mbed_official 553:063b9f2f393c 324 /**
mbed_official 553:063b9f2f393c 325 * @brief Digital to Analog Converter
mbed_official 553:063b9f2f393c 326 */
mbed_official 553:063b9f2f393c 327
mbed_official 553:063b9f2f393c 328 typedef struct
mbed_official 553:063b9f2f393c 329 {
mbed_official 553:063b9f2f393c 330 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 331 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 332 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 333 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 334 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 335 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 336 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 337 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 338 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 339 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 340 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 341 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 553:063b9f2f393c 342 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 553:063b9f2f393c 343 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 553:063b9f2f393c 344 } DAC_TypeDef;
mbed_official 553:063b9f2f393c 345
mbed_official 553:063b9f2f393c 346 /**
mbed_official 553:063b9f2f393c 347 * @brief Debug MCU
mbed_official 553:063b9f2f393c 348 */
mbed_official 553:063b9f2f393c 349
mbed_official 553:063b9f2f393c 350 typedef struct
mbed_official 553:063b9f2f393c 351 {
mbed_official 553:063b9f2f393c 352 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 353 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 354 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 355 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 356 }DBGMCU_TypeDef;
mbed_official 553:063b9f2f393c 357
mbed_official 553:063b9f2f393c 358 /**
mbed_official 553:063b9f2f393c 359 * @brief DCMI
mbed_official 553:063b9f2f393c 360 */
mbed_official 553:063b9f2f393c 361
mbed_official 553:063b9f2f393c 362 typedef struct
mbed_official 553:063b9f2f393c 363 {
mbed_official 553:063b9f2f393c 364 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 365 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 366 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 367 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 368 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 369 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 370 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 371 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 372 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 373 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 374 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 375 } DCMI_TypeDef;
mbed_official 553:063b9f2f393c 376
mbed_official 553:063b9f2f393c 377 /**
mbed_official 553:063b9f2f393c 378 * @brief DMA Controller
mbed_official 553:063b9f2f393c 379 */
mbed_official 553:063b9f2f393c 380
mbed_official 553:063b9f2f393c 381 typedef struct
mbed_official 553:063b9f2f393c 382 {
mbed_official 553:063b9f2f393c 383 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 553:063b9f2f393c 384 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 553:063b9f2f393c 385 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 553:063b9f2f393c 386 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 553:063b9f2f393c 387 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 553:063b9f2f393c 388 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 553:063b9f2f393c 389 } DMA_Stream_TypeDef;
mbed_official 553:063b9f2f393c 390
mbed_official 553:063b9f2f393c 391 typedef struct
mbed_official 553:063b9f2f393c 392 {
mbed_official 553:063b9f2f393c 393 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 394 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 395 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 396 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 397 } DMA_TypeDef;
mbed_official 553:063b9f2f393c 398
mbed_official 553:063b9f2f393c 399
mbed_official 553:063b9f2f393c 400 /**
mbed_official 553:063b9f2f393c 401 * @brief External Interrupt/Event Controller
mbed_official 553:063b9f2f393c 402 */
mbed_official 553:063b9f2f393c 403
mbed_official 553:063b9f2f393c 404 typedef struct
mbed_official 553:063b9f2f393c 405 {
mbed_official 553:063b9f2f393c 406 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 407 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 408 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 409 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 410 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 411 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 412 } EXTI_TypeDef;
mbed_official 553:063b9f2f393c 413
mbed_official 553:063b9f2f393c 414 /**
mbed_official 553:063b9f2f393c 415 * @brief FLASH Registers
mbed_official 553:063b9f2f393c 416 */
mbed_official 553:063b9f2f393c 417
mbed_official 553:063b9f2f393c 418 typedef struct
mbed_official 553:063b9f2f393c 419 {
mbed_official 553:063b9f2f393c 420 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 421 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 422 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 423 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 424 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 425 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 553:063b9f2f393c 426 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 427 } FLASH_TypeDef;
mbed_official 553:063b9f2f393c 428
mbed_official 553:063b9f2f393c 429 /**
mbed_official 553:063b9f2f393c 430 * @brief Flexible Memory Controller
mbed_official 553:063b9f2f393c 431 */
mbed_official 553:063b9f2f393c 432
mbed_official 553:063b9f2f393c 433 typedef struct
mbed_official 553:063b9f2f393c 434 {
mbed_official 553:063b9f2f393c 435 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
mbed_official 553:063b9f2f393c 436 } FMC_Bank1_TypeDef;
mbed_official 553:063b9f2f393c 437
mbed_official 553:063b9f2f393c 438 /**
mbed_official 553:063b9f2f393c 439 * @brief Flexible Memory Controller Bank1E
mbed_official 553:063b9f2f393c 440 */
mbed_official 553:063b9f2f393c 441
mbed_official 553:063b9f2f393c 442 typedef struct
mbed_official 553:063b9f2f393c 443 {
mbed_official 553:063b9f2f393c 444 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
mbed_official 553:063b9f2f393c 445 } FMC_Bank1E_TypeDef;
mbed_official 553:063b9f2f393c 446
mbed_official 553:063b9f2f393c 447 /**
mbed_official 553:063b9f2f393c 448 * @brief Flexible Memory Controller Bank3
mbed_official 553:063b9f2f393c 449 */
mbed_official 553:063b9f2f393c 450
mbed_official 553:063b9f2f393c 451 typedef struct
mbed_official 553:063b9f2f393c 452 {
mbed_official 553:063b9f2f393c 453 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
mbed_official 553:063b9f2f393c 454 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
mbed_official 553:063b9f2f393c 455 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
mbed_official 553:063b9f2f393c 456 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
mbed_official 553:063b9f2f393c 457 uint32_t RESERVED; /*!< Reserved, 0x90 */
mbed_official 553:063b9f2f393c 458 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
mbed_official 553:063b9f2f393c 459 } FMC_Bank3_TypeDef;
mbed_official 553:063b9f2f393c 460
mbed_official 553:063b9f2f393c 461 /**
mbed_official 553:063b9f2f393c 462 * @brief Flexible Memory Controller Bank5_6
mbed_official 553:063b9f2f393c 463 */
mbed_official 553:063b9f2f393c 464
mbed_official 553:063b9f2f393c 465 typedef struct
mbed_official 553:063b9f2f393c 466 {
mbed_official 553:063b9f2f393c 467 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
mbed_official 553:063b9f2f393c 468 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
mbed_official 553:063b9f2f393c 469 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
mbed_official 553:063b9f2f393c 470 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
mbed_official 553:063b9f2f393c 471 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
mbed_official 553:063b9f2f393c 472 } FMC_Bank5_6_TypeDef;
mbed_official 553:063b9f2f393c 473
mbed_official 553:063b9f2f393c 474 /**
mbed_official 553:063b9f2f393c 475 * @brief General Purpose I/O
mbed_official 553:063b9f2f393c 476 */
mbed_official 553:063b9f2f393c 477
mbed_official 553:063b9f2f393c 478 typedef struct
mbed_official 553:063b9f2f393c 479 {
mbed_official 553:063b9f2f393c 480 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 481 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 482 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 483 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 484 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 485 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 486 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 487 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 488 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 553:063b9f2f393c 489 } GPIO_TypeDef;
mbed_official 553:063b9f2f393c 490
mbed_official 553:063b9f2f393c 491 /**
mbed_official 553:063b9f2f393c 492 * @brief System configuration controller
mbed_official 553:063b9f2f393c 493 */
mbed_official 553:063b9f2f393c 494
mbed_official 553:063b9f2f393c 495 typedef struct
mbed_official 553:063b9f2f393c 496 {
mbed_official 553:063b9f2f393c 497 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 498 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 499 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 553:063b9f2f393c 500 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 553:063b9f2f393c 501 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 502 uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
mbed_official 553:063b9f2f393c 503 __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
mbed_official 553:063b9f2f393c 504 } SYSCFG_TypeDef;
mbed_official 553:063b9f2f393c 505
mbed_official 553:063b9f2f393c 506 /**
mbed_official 553:063b9f2f393c 507 * @brief Inter-integrated Circuit Interface
mbed_official 553:063b9f2f393c 508 */
mbed_official 553:063b9f2f393c 509
mbed_official 553:063b9f2f393c 510 typedef struct
mbed_official 553:063b9f2f393c 511 {
mbed_official 553:063b9f2f393c 512 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 513 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 514 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 515 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 516 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 517 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 518 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 519 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 520 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 521 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 522 } I2C_TypeDef;
mbed_official 553:063b9f2f393c 523
mbed_official 553:063b9f2f393c 524 /**
mbed_official 553:063b9f2f393c 525 * @brief Inter-integrated Circuit Interface
mbed_official 553:063b9f2f393c 526 */
mbed_official 553:063b9f2f393c 527
mbed_official 553:063b9f2f393c 528 typedef struct
mbed_official 553:063b9f2f393c 529 {
mbed_official 553:063b9f2f393c 530 __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 531 __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 532 __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 533 __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 534 __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 535 __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 536 __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 537 __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 538 __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 539 __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 540 __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 541 } FMPI2C_TypeDef;
mbed_official 553:063b9f2f393c 542
mbed_official 553:063b9f2f393c 543 /**
mbed_official 553:063b9f2f393c 544 * @brief Independent WATCHDOG
mbed_official 553:063b9f2f393c 545 */
mbed_official 553:063b9f2f393c 546
mbed_official 553:063b9f2f393c 547 typedef struct
mbed_official 553:063b9f2f393c 548 {
mbed_official 553:063b9f2f393c 549 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 550 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 551 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 552 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 553 } IWDG_TypeDef;
mbed_official 553:063b9f2f393c 554
mbed_official 553:063b9f2f393c 555 /**
mbed_official 553:063b9f2f393c 556 * @brief Power Control
mbed_official 553:063b9f2f393c 557 */
mbed_official 553:063b9f2f393c 558
mbed_official 553:063b9f2f393c 559 typedef struct
mbed_official 553:063b9f2f393c 560 {
mbed_official 553:063b9f2f393c 561 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 562 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 563 } PWR_TypeDef;
mbed_official 553:063b9f2f393c 564
mbed_official 553:063b9f2f393c 565 /**
mbed_official 553:063b9f2f393c 566 * @brief Reset and Clock Control
mbed_official 553:063b9f2f393c 567 */
mbed_official 553:063b9f2f393c 568
mbed_official 553:063b9f2f393c 569 typedef struct
mbed_official 553:063b9f2f393c 570 {
mbed_official 553:063b9f2f393c 571 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 572 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 573 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 574 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 575 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 576 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 577 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 578 uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 553:063b9f2f393c 579 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 580 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 581 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 553:063b9f2f393c 582 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 553:063b9f2f393c 583 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
mbed_official 553:063b9f2f393c 584 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
mbed_official 553:063b9f2f393c 585 uint32_t RESERVED2; /*!< Reserved, 0x3C */
mbed_official 553:063b9f2f393c 586 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 553:063b9f2f393c 587 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 553:063b9f2f393c 588 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 553:063b9f2f393c 589 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 553:063b9f2f393c 590 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
mbed_official 553:063b9f2f393c 591 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
mbed_official 553:063b9f2f393c 592 uint32_t RESERVED4; /*!< Reserved, 0x5C */
mbed_official 553:063b9f2f393c 593 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 553:063b9f2f393c 594 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 553:063b9f2f393c 595 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 553:063b9f2f393c 596 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 553:063b9f2f393c 597 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 553:063b9f2f393c 598 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 553:063b9f2f393c 599 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 553:063b9f2f393c 600 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
mbed_official 553:063b9f2f393c 601 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
mbed_official 553:063b9f2f393c 602 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
mbed_official 553:063b9f2f393c 603 __IO uint32_t CKGATENR; /*!< RCC Clocks Gated ENable Register, Address offset: 0x90 */
mbed_official 553:063b9f2f393c 604 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */
mbed_official 553:063b9f2f393c 605 } RCC_TypeDef;
mbed_official 553:063b9f2f393c 606
mbed_official 553:063b9f2f393c 607 /**
mbed_official 553:063b9f2f393c 608 * @brief Real-Time Clock
mbed_official 553:063b9f2f393c 609 */
mbed_official 553:063b9f2f393c 610
mbed_official 553:063b9f2f393c 611 typedef struct
mbed_official 553:063b9f2f393c 612 {
mbed_official 553:063b9f2f393c 613 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 614 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 615 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 616 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 617 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 618 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 619 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 620 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 621 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 622 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 623 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 624 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 553:063b9f2f393c 625 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 553:063b9f2f393c 626 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 553:063b9f2f393c 627 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 553:063b9f2f393c 628 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 553:063b9f2f393c 629 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 553:063b9f2f393c 630 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 553:063b9f2f393c 631 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 553:063b9f2f393c 632 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 553:063b9f2f393c 633 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
mbed_official 553:063b9f2f393c 634 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 553:063b9f2f393c 635 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 553:063b9f2f393c 636 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 553:063b9f2f393c 637 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 553:063b9f2f393c 638 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 553:063b9f2f393c 639 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 553:063b9f2f393c 640 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 553:063b9f2f393c 641 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 553:063b9f2f393c 642 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 553:063b9f2f393c 643 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 553:063b9f2f393c 644 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 553:063b9f2f393c 645 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 553:063b9f2f393c 646 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 553:063b9f2f393c 647 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 553:063b9f2f393c 648 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 553:063b9f2f393c 649 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 553:063b9f2f393c 650 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 553:063b9f2f393c 651 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 553:063b9f2f393c 652 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 553:063b9f2f393c 653 } RTC_TypeDef;
mbed_official 553:063b9f2f393c 654
mbed_official 553:063b9f2f393c 655 /**
mbed_official 553:063b9f2f393c 656 * @brief Serial Audio Interface
mbed_official 553:063b9f2f393c 657 */
mbed_official 553:063b9f2f393c 658
mbed_official 553:063b9f2f393c 659 typedef struct
mbed_official 553:063b9f2f393c 660 {
mbed_official 553:063b9f2f393c 661 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 662 } SAI_TypeDef;
mbed_official 553:063b9f2f393c 663
mbed_official 553:063b9f2f393c 664 typedef struct
mbed_official 553:063b9f2f393c 665 {
mbed_official 553:063b9f2f393c 666 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 667 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 668 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 669 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 670 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 671 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 672 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 673 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 674 } SAI_Block_TypeDef;
mbed_official 553:063b9f2f393c 675
mbed_official 553:063b9f2f393c 676 /**
mbed_official 553:063b9f2f393c 677 * @brief SD host Interface
mbed_official 553:063b9f2f393c 678 */
mbed_official 553:063b9f2f393c 679
mbed_official 553:063b9f2f393c 680 typedef struct
mbed_official 553:063b9f2f393c 681 {
mbed_official 553:063b9f2f393c 682 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 683 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 684 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 685 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 686 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 687 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 688 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 689 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 690 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 691 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 692 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 693 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
mbed_official 553:063b9f2f393c 694 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
mbed_official 553:063b9f2f393c 695 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
mbed_official 553:063b9f2f393c 696 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
mbed_official 553:063b9f2f393c 697 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
mbed_official 553:063b9f2f393c 698 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
mbed_official 553:063b9f2f393c 699 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
mbed_official 553:063b9f2f393c 700 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
mbed_official 553:063b9f2f393c 701 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
mbed_official 553:063b9f2f393c 702 } SDIO_TypeDef;
mbed_official 553:063b9f2f393c 703
mbed_official 553:063b9f2f393c 704 /**
mbed_official 553:063b9f2f393c 705 * @brief Serial Peripheral Interface
mbed_official 553:063b9f2f393c 706 */
mbed_official 553:063b9f2f393c 707
mbed_official 553:063b9f2f393c 708 typedef struct
mbed_official 553:063b9f2f393c 709 {
mbed_official 553:063b9f2f393c 710 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 553:063b9f2f393c 711 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 712 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 713 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 714 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 553:063b9f2f393c 715 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 553:063b9f2f393c 716 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 553:063b9f2f393c 717 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 718 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 719 } SPI_TypeDef;
mbed_official 553:063b9f2f393c 720
mbed_official 553:063b9f2f393c 721 /**
mbed_official 553:063b9f2f393c 722 * @brief QUAD Serial Peripheral Interface
mbed_official 553:063b9f2f393c 723 */
mbed_official 553:063b9f2f393c 724
mbed_official 553:063b9f2f393c 725 typedef struct
mbed_official 553:063b9f2f393c 726 {
mbed_official 553:063b9f2f393c 727 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 728 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 729 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 730 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 731 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 732 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 733 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 734 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 735 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 736 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 737 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 738 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
mbed_official 553:063b9f2f393c 739 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
mbed_official 553:063b9f2f393c 740 } QUADSPI_TypeDef;
mbed_official 553:063b9f2f393c 741
mbed_official 553:063b9f2f393c 742 /**
mbed_official 553:063b9f2f393c 743 * @brief SPDIFRX Interface
mbed_official 553:063b9f2f393c 744 */
mbed_official 553:063b9f2f393c 745
mbed_official 553:063b9f2f393c 746 typedef struct
mbed_official 553:063b9f2f393c 747 {
mbed_official 553:063b9f2f393c 748 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 749 __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 750 uint16_t RESERVED0; /*!< Reserved, 0x06 */
mbed_official 553:063b9f2f393c 751 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 752 __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 753 uint16_t RESERVED1; /*!< Reserved, 0x0E */
mbed_official 553:063b9f2f393c 754 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 755 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 756 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 757 uint16_t RESERVED2; /*!< Reserved, 0x1A */
mbed_official 553:063b9f2f393c 758 } SPDIFRX_TypeDef;
mbed_official 553:063b9f2f393c 759
mbed_official 553:063b9f2f393c 760 /**
mbed_official 553:063b9f2f393c 761 * @brief TIM
mbed_official 553:063b9f2f393c 762 */
mbed_official 553:063b9f2f393c 763
mbed_official 553:063b9f2f393c 764 typedef struct
mbed_official 553:063b9f2f393c 765 {
mbed_official 553:063b9f2f393c 766 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 767 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 768 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 769 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 770 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 771 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 772 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 773 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 553:063b9f2f393c 774 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 553:063b9f2f393c 775 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 553:063b9f2f393c 776 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 553:063b9f2f393c 777 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 553:063b9f2f393c 778 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 553:063b9f2f393c 779 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 553:063b9f2f393c 780 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 553:063b9f2f393c 781 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 553:063b9f2f393c 782 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 553:063b9f2f393c 783 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 553:063b9f2f393c 784 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 553:063b9f2f393c 785 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 553:063b9f2f393c 786 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 553:063b9f2f393c 787 } TIM_TypeDef;
mbed_official 553:063b9f2f393c 788
mbed_official 553:063b9f2f393c 789 /**
mbed_official 553:063b9f2f393c 790 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 553:063b9f2f393c 791 */
mbed_official 553:063b9f2f393c 792
mbed_official 553:063b9f2f393c 793 typedef struct
mbed_official 553:063b9f2f393c 794 {
mbed_official 553:063b9f2f393c 795 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 796 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 797 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 798 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 553:063b9f2f393c 799 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 553:063b9f2f393c 800 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 553:063b9f2f393c 801 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 553:063b9f2f393c 802 } USART_TypeDef;
mbed_official 553:063b9f2f393c 803
mbed_official 553:063b9f2f393c 804 /**
mbed_official 553:063b9f2f393c 805 * @brief Window WATCHDOG
mbed_official 553:063b9f2f393c 806 */
mbed_official 553:063b9f2f393c 807
mbed_official 553:063b9f2f393c 808 typedef struct
mbed_official 553:063b9f2f393c 809 {
mbed_official 553:063b9f2f393c 810 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 553:063b9f2f393c 811 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 553:063b9f2f393c 812 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 553:063b9f2f393c 813 } WWDG_TypeDef;
mbed_official 553:063b9f2f393c 814
mbed_official 553:063b9f2f393c 815 /**
mbed_official 553:063b9f2f393c 816 * @brief USB_OTG_Core_Registers
mbed_official 553:063b9f2f393c 817 */
mbed_official 553:063b9f2f393c 818 typedef struct
mbed_official 553:063b9f2f393c 819 {
mbed_official 553:063b9f2f393c 820 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
mbed_official 553:063b9f2f393c 821 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
mbed_official 553:063b9f2f393c 822 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
mbed_official 553:063b9f2f393c 823 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
mbed_official 553:063b9f2f393c 824 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
mbed_official 553:063b9f2f393c 825 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
mbed_official 553:063b9f2f393c 826 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
mbed_official 553:063b9f2f393c 827 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
mbed_official 553:063b9f2f393c 828 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
mbed_official 553:063b9f2f393c 829 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
mbed_official 553:063b9f2f393c 830 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
mbed_official 553:063b9f2f393c 831 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
mbed_official 553:063b9f2f393c 832 uint32_t Reserved30[2]; /*!< Reserved 030h */
mbed_official 553:063b9f2f393c 833 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
mbed_official 553:063b9f2f393c 834 __IO uint32_t CID; /*!< User ID Register 03Ch */
mbed_official 553:063b9f2f393c 835 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
mbed_official 553:063b9f2f393c 836 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
mbed_official 553:063b9f2f393c 837 uint32_t Reserved6; /*!< Reserved 050h */
mbed_official 553:063b9f2f393c 838 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
mbed_official 553:063b9f2f393c 839 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
mbed_official 553:063b9f2f393c 840 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
mbed_official 553:063b9f2f393c 841 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
mbed_official 553:063b9f2f393c 842 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
mbed_official 553:063b9f2f393c 843 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
mbed_official 553:063b9f2f393c 844 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
mbed_official 553:063b9f2f393c 845 } USB_OTG_GlobalTypeDef;
mbed_official 553:063b9f2f393c 846
mbed_official 553:063b9f2f393c 847 /**
mbed_official 553:063b9f2f393c 848 * @brief USB_OTG_device_Registers
mbed_official 553:063b9f2f393c 849 */
mbed_official 553:063b9f2f393c 850 typedef struct
mbed_official 553:063b9f2f393c 851 {
mbed_official 553:063b9f2f393c 852 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
mbed_official 553:063b9f2f393c 853 __IO uint32_t DCTL; /*!< dev Control Register 804h */
mbed_official 553:063b9f2f393c 854 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
mbed_official 553:063b9f2f393c 855 uint32_t Reserved0C; /*!< Reserved 80Ch */
mbed_official 553:063b9f2f393c 856 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
mbed_official 553:063b9f2f393c 857 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
mbed_official 553:063b9f2f393c 858 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
mbed_official 553:063b9f2f393c 859 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
mbed_official 553:063b9f2f393c 860 uint32_t Reserved20; /*!< Reserved 820h */
mbed_official 553:063b9f2f393c 861 uint32_t Reserved9; /*!< Reserved 824h */
mbed_official 553:063b9f2f393c 862 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
mbed_official 553:063b9f2f393c 863 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
mbed_official 553:063b9f2f393c 864 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
mbed_official 553:063b9f2f393c 865 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
mbed_official 553:063b9f2f393c 866 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
mbed_official 553:063b9f2f393c 867 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
mbed_official 553:063b9f2f393c 868 uint32_t Reserved40; /*!< dedicated EP mask 840h */
mbed_official 553:063b9f2f393c 869 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
mbed_official 553:063b9f2f393c 870 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
mbed_official 553:063b9f2f393c 871 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
mbed_official 553:063b9f2f393c 872 } USB_OTG_DeviceTypeDef;
mbed_official 553:063b9f2f393c 873
mbed_official 553:063b9f2f393c 874 /**
mbed_official 553:063b9f2f393c 875 * @brief USB_OTG_IN_Endpoint-Specific_Register
mbed_official 553:063b9f2f393c 876 */
mbed_official 553:063b9f2f393c 877 typedef struct
mbed_official 553:063b9f2f393c 878 {
mbed_official 553:063b9f2f393c 879 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
mbed_official 553:063b9f2f393c 880 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
mbed_official 553:063b9f2f393c 881 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
mbed_official 553:063b9f2f393c 882 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
mbed_official 553:063b9f2f393c 883 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
mbed_official 553:063b9f2f393c 884 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
mbed_official 553:063b9f2f393c 885 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
mbed_official 553:063b9f2f393c 886 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
mbed_official 553:063b9f2f393c 887 } USB_OTG_INEndpointTypeDef;
mbed_official 553:063b9f2f393c 888
mbed_official 553:063b9f2f393c 889 /**
mbed_official 553:063b9f2f393c 890 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
mbed_official 553:063b9f2f393c 891 */
mbed_official 553:063b9f2f393c 892 typedef struct
mbed_official 553:063b9f2f393c 893 {
mbed_official 553:063b9f2f393c 894 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
mbed_official 553:063b9f2f393c 895 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
mbed_official 553:063b9f2f393c 896 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
mbed_official 553:063b9f2f393c 897 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
mbed_official 553:063b9f2f393c 898 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
mbed_official 553:063b9f2f393c 899 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
mbed_official 553:063b9f2f393c 900 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
mbed_official 553:063b9f2f393c 901 } USB_OTG_OUTEndpointTypeDef;
mbed_official 553:063b9f2f393c 902
mbed_official 553:063b9f2f393c 903 /**
mbed_official 553:063b9f2f393c 904 * @brief USB_OTG_Host_Mode_Register_Structures
mbed_official 553:063b9f2f393c 905 */
mbed_official 553:063b9f2f393c 906 typedef struct
mbed_official 553:063b9f2f393c 907 {
mbed_official 553:063b9f2f393c 908 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
mbed_official 553:063b9f2f393c 909 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
mbed_official 553:063b9f2f393c 910 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
mbed_official 553:063b9f2f393c 911 uint32_t Reserved40C; /*!< Reserved 40Ch */
mbed_official 553:063b9f2f393c 912 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
mbed_official 553:063b9f2f393c 913 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
mbed_official 553:063b9f2f393c 914 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
mbed_official 553:063b9f2f393c 915 } USB_OTG_HostTypeDef;
mbed_official 553:063b9f2f393c 916
mbed_official 553:063b9f2f393c 917 /**
mbed_official 553:063b9f2f393c 918 * @brief USB_OTG_Host_Channel_Specific_Registers
mbed_official 553:063b9f2f393c 919 */
mbed_official 553:063b9f2f393c 920 typedef struct
mbed_official 553:063b9f2f393c 921 {
mbed_official 553:063b9f2f393c 922 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
mbed_official 553:063b9f2f393c 923 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
mbed_official 553:063b9f2f393c 924 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
mbed_official 553:063b9f2f393c 925 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
mbed_official 553:063b9f2f393c 926 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
mbed_official 553:063b9f2f393c 927 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
mbed_official 553:063b9f2f393c 928 uint32_t Reserved[2]; /*!< Reserved */
mbed_official 553:063b9f2f393c 929 } USB_OTG_HostChannelTypeDef;
mbed_official 553:063b9f2f393c 930
mbed_official 553:063b9f2f393c 931 /**
mbed_official 553:063b9f2f393c 932 * @}
mbed_official 553:063b9f2f393c 933 */
mbed_official 553:063b9f2f393c 934
mbed_official 553:063b9f2f393c 935 /** @addtogroup Peripheral_memory_map
mbed_official 553:063b9f2f393c 936 * @{
mbed_official 553:063b9f2f393c 937 */
mbed_official 553:063b9f2f393c 938 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
mbed_official 553:063b9f2f393c 939 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
mbed_official 553:063b9f2f393c 940 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
mbed_official 553:063b9f2f393c 941 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 553:063b9f2f393c 942 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
mbed_official 553:063b9f2f393c 943 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
mbed_official 553:063b9f2f393c 944 #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
mbed_official 553:063b9f2f393c 945
mbed_official 553:063b9f2f393c 946 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
mbed_official 553:063b9f2f393c 947 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
mbed_official 553:063b9f2f393c 948 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 553:063b9f2f393c 949 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
mbed_official 553:063b9f2f393c 950 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
mbed_official 553:063b9f2f393c 951
mbed_official 553:063b9f2f393c 952 /* Legacy defines */
mbed_official 553:063b9f2f393c 953 #define SRAM_BASE SRAM1_BASE
mbed_official 553:063b9f2f393c 954 #define SRAM_BB_BASE SRAM1_BB_BASE
mbed_official 553:063b9f2f393c 955
mbed_official 553:063b9f2f393c 956
mbed_official 553:063b9f2f393c 957 /*!< Peripheral memory map */
mbed_official 553:063b9f2f393c 958 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 553:063b9f2f393c 959 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 553:063b9f2f393c 960 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 553:063b9f2f393c 961 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 553:063b9f2f393c 962
mbed_official 553:063b9f2f393c 963 /*!< APB1 peripherals */
mbed_official 553:063b9f2f393c 964 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official 553:063b9f2f393c 965 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official 553:063b9f2f393c 966 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official 553:063b9f2f393c 967 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official 553:063b9f2f393c 968 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official 553:063b9f2f393c 969 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
mbed_official 553:063b9f2f393c 970 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
mbed_official 553:063b9f2f393c 971 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
mbed_official 553:063b9f2f393c 972 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
mbed_official 553:063b9f2f393c 973 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 553:063b9f2f393c 974 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 553:063b9f2f393c 975 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 553:063b9f2f393c 976 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 553:063b9f2f393c 977 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
mbed_official 553:063b9f2f393c 978 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
mbed_official 553:063b9f2f393c 979 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 553:063b9f2f393c 980 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
mbed_official 553:063b9f2f393c 981 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
mbed_official 553:063b9f2f393c 982 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
mbed_official 553:063b9f2f393c 983 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 553:063b9f2f393c 984 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 553:063b9f2f393c 985 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
mbed_official 553:063b9f2f393c 986 #define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
mbed_official 553:063b9f2f393c 987 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
mbed_official 553:063b9f2f393c 988 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
mbed_official 553:063b9f2f393c 989 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
mbed_official 553:063b9f2f393c 990 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 553:063b9f2f393c 991 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official 553:063b9f2f393c 992
mbed_official 553:063b9f2f393c 993 /*!< APB2 peripherals */
mbed_official 553:063b9f2f393c 994 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 553:063b9f2f393c 995 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
mbed_official 553:063b9f2f393c 996 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 553:063b9f2f393c 997 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 553:063b9f2f393c 998 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
mbed_official 553:063b9f2f393c 999 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
mbed_official 553:063b9f2f393c 1000 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
mbed_official 553:063b9f2f393c 1001 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
mbed_official 553:063b9f2f393c 1002 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official 553:063b9f2f393c 1003 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 553:063b9f2f393c 1004 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
mbed_official 553:063b9f2f393c 1005 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 553:063b9f2f393c 1006 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
mbed_official 553:063b9f2f393c 1007 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 553:063b9f2f393c 1008 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
mbed_official 553:063b9f2f393c 1009 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 553:063b9f2f393c 1010 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
mbed_official 553:063b9f2f393c 1011 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
mbed_official 553:063b9f2f393c 1012 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
mbed_official 553:063b9f2f393c 1013 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
mbed_official 553:063b9f2f393c 1014 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
mbed_official 553:063b9f2f393c 1015 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
mbed_official 553:063b9f2f393c 1016
mbed_official 553:063b9f2f393c 1017 /*!< AHB1 peripherals */
mbed_official 553:063b9f2f393c 1018 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
mbed_official 553:063b9f2f393c 1019 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
mbed_official 553:063b9f2f393c 1020 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
mbed_official 553:063b9f2f393c 1021 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
mbed_official 553:063b9f2f393c 1022 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
mbed_official 553:063b9f2f393c 1023 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
mbed_official 553:063b9f2f393c 1024 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
mbed_official 553:063b9f2f393c 1025 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
mbed_official 553:063b9f2f393c 1026 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
mbed_official 553:063b9f2f393c 1027 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
mbed_official 553:063b9f2f393c 1028 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
mbed_official 553:063b9f2f393c 1029 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
mbed_official 553:063b9f2f393c 1030 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
mbed_official 553:063b9f2f393c 1031 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
mbed_official 553:063b9f2f393c 1032 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
mbed_official 553:063b9f2f393c 1033 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
mbed_official 553:063b9f2f393c 1034 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
mbed_official 553:063b9f2f393c 1035 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
mbed_official 553:063b9f2f393c 1036 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
mbed_official 553:063b9f2f393c 1037 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
mbed_official 553:063b9f2f393c 1038 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
mbed_official 553:063b9f2f393c 1039 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
mbed_official 553:063b9f2f393c 1040 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
mbed_official 553:063b9f2f393c 1041 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
mbed_official 553:063b9f2f393c 1042 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
mbed_official 553:063b9f2f393c 1043 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
mbed_official 553:063b9f2f393c 1044 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
mbed_official 553:063b9f2f393c 1045 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
mbed_official 553:063b9f2f393c 1046 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
mbed_official 553:063b9f2f393c 1047
mbed_official 553:063b9f2f393c 1048 /*!< AHB2 peripherals */
mbed_official 553:063b9f2f393c 1049 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
mbed_official 553:063b9f2f393c 1050
mbed_official 553:063b9f2f393c 1051 /*!< FMC Bankx registers base address */
mbed_official 553:063b9f2f393c 1052 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
mbed_official 553:063b9f2f393c 1053 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
mbed_official 553:063b9f2f393c 1054 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
mbed_official 553:063b9f2f393c 1055 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
mbed_official 553:063b9f2f393c 1056
mbed_official 553:063b9f2f393c 1057 /*!< Debug MCU registers base address */
mbed_official 553:063b9f2f393c 1058 #define DBGMCU_BASE ((uint32_t )0xE0042000)
mbed_official 553:063b9f2f393c 1059
mbed_official 553:063b9f2f393c 1060 /*!< USB registers base address */
mbed_official 553:063b9f2f393c 1061 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
mbed_official 553:063b9f2f393c 1062 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
mbed_official 553:063b9f2f393c 1063
mbed_official 553:063b9f2f393c 1064 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
mbed_official 553:063b9f2f393c 1065 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
mbed_official 553:063b9f2f393c 1066 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
mbed_official 553:063b9f2f393c 1067 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
mbed_official 553:063b9f2f393c 1068 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
mbed_official 553:063b9f2f393c 1069 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
mbed_official 553:063b9f2f393c 1070 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
mbed_official 553:063b9f2f393c 1071 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
mbed_official 553:063b9f2f393c 1072 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
mbed_official 553:063b9f2f393c 1073 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
mbed_official 553:063b9f2f393c 1074 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
mbed_official 553:063b9f2f393c 1075 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
mbed_official 553:063b9f2f393c 1076
mbed_official 553:063b9f2f393c 1077 /**
mbed_official 553:063b9f2f393c 1078 * @}
mbed_official 553:063b9f2f393c 1079 */
mbed_official 553:063b9f2f393c 1080
mbed_official 553:063b9f2f393c 1081 /** @addtogroup Peripheral_declaration
mbed_official 553:063b9f2f393c 1082 * @{
mbed_official 553:063b9f2f393c 1083 */
mbed_official 553:063b9f2f393c 1084 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 553:063b9f2f393c 1085 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 553:063b9f2f393c 1086 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 553:063b9f2f393c 1087 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 553:063b9f2f393c 1088 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 553:063b9f2f393c 1089 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 553:063b9f2f393c 1090 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
mbed_official 553:063b9f2f393c 1091 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
mbed_official 553:063b9f2f393c 1092 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 553:063b9f2f393c 1093 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 553:063b9f2f393c 1094 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 553:063b9f2f393c 1095 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 553:063b9f2f393c 1096 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 553:063b9f2f393c 1097 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 553:063b9f2f393c 1098 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
mbed_official 553:063b9f2f393c 1099 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 553:063b9f2f393c 1100 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 553:063b9f2f393c 1101 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 553:063b9f2f393c 1102 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 553:063b9f2f393c 1103 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 553:063b9f2f393c 1104 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 553:063b9f2f393c 1105 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 553:063b9f2f393c 1106 #define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
mbed_official 553:063b9f2f393c 1107 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
mbed_official 553:063b9f2f393c 1108 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
mbed_official 553:063b9f2f393c 1109 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 553:063b9f2f393c 1110 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 553:063b9f2f393c 1111 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 553:063b9f2f393c 1112 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 553:063b9f2f393c 1113 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 553:063b9f2f393c 1114 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 553:063b9f2f393c 1115 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 553:063b9f2f393c 1116 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 553:063b9f2f393c 1117 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 553:063b9f2f393c 1118 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 553:063b9f2f393c 1119 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 553:063b9f2f393c 1120 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
mbed_official 553:063b9f2f393c 1121 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 553:063b9f2f393c 1122 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
mbed_official 553:063b9f2f393c 1123 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 553:063b9f2f393c 1124 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 553:063b9f2f393c 1125 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 553:063b9f2f393c 1126 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 553:063b9f2f393c 1127 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 553:063b9f2f393c 1128 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
mbed_official 553:063b9f2f393c 1129 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
mbed_official 553:063b9f2f393c 1130 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
mbed_official 553:063b9f2f393c 1131 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
mbed_official 553:063b9f2f393c 1132 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
mbed_official 553:063b9f2f393c 1133 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
mbed_official 553:063b9f2f393c 1134
mbed_official 553:063b9f2f393c 1135 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 553:063b9f2f393c 1136 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 553:063b9f2f393c 1137 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 553:063b9f2f393c 1138 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 553:063b9f2f393c 1139 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 553:063b9f2f393c 1140 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 553:063b9f2f393c 1141 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 553:063b9f2f393c 1142 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 553:063b9f2f393c 1143 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 553:063b9f2f393c 1144 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 553:063b9f2f393c 1145 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 553:063b9f2f393c 1146 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 553:063b9f2f393c 1147 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 553:063b9f2f393c 1148 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 553:063b9f2f393c 1149 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 553:063b9f2f393c 1150 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 553:063b9f2f393c 1151 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 553:063b9f2f393c 1152 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 553:063b9f2f393c 1153 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 553:063b9f2f393c 1154 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 553:063b9f2f393c 1155 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 553:063b9f2f393c 1156 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 553:063b9f2f393c 1157 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 553:063b9f2f393c 1158 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 553:063b9f2f393c 1159 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 553:063b9f2f393c 1160 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 553:063b9f2f393c 1161 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 553:063b9f2f393c 1162 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 553:063b9f2f393c 1163 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 553:063b9f2f393c 1164 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
mbed_official 553:063b9f2f393c 1165 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
mbed_official 553:063b9f2f393c 1166 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
mbed_official 553:063b9f2f393c 1167 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
mbed_official 553:063b9f2f393c 1168 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
mbed_official 553:063b9f2f393c 1169 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
mbed_official 553:063b9f2f393c 1170
mbed_official 553:063b9f2f393c 1171 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 553:063b9f2f393c 1172
mbed_official 553:063b9f2f393c 1173 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
mbed_official 553:063b9f2f393c 1174 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
mbed_official 553:063b9f2f393c 1175
mbed_official 553:063b9f2f393c 1176 /**
mbed_official 553:063b9f2f393c 1177 * @}
mbed_official 553:063b9f2f393c 1178 */
mbed_official 553:063b9f2f393c 1179
mbed_official 553:063b9f2f393c 1180 /** @addtogroup Exported_constants
mbed_official 553:063b9f2f393c 1181 * @{
mbed_official 553:063b9f2f393c 1182 */
mbed_official 553:063b9f2f393c 1183
mbed_official 553:063b9f2f393c 1184 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 553:063b9f2f393c 1185 * @{
mbed_official 553:063b9f2f393c 1186 */
mbed_official 553:063b9f2f393c 1187
mbed_official 553:063b9f2f393c 1188 /******************************************************************************/
mbed_official 553:063b9f2f393c 1189 /* Peripheral Registers_Bits_Definition */
mbed_official 553:063b9f2f393c 1190 /******************************************************************************/
mbed_official 553:063b9f2f393c 1191
mbed_official 553:063b9f2f393c 1192 /******************************************************************************/
mbed_official 553:063b9f2f393c 1193 /* */
mbed_official 553:063b9f2f393c 1194 /* Analog to Digital Converter */
mbed_official 553:063b9f2f393c 1195 /* */
mbed_official 553:063b9f2f393c 1196 /******************************************************************************/
mbed_official 553:063b9f2f393c 1197 /******************** Bit definition for ADC_SR register ********************/
mbed_official 553:063b9f2f393c 1198 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
mbed_official 553:063b9f2f393c 1199 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
mbed_official 553:063b9f2f393c 1200 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
mbed_official 553:063b9f2f393c 1201 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
mbed_official 553:063b9f2f393c 1202 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
mbed_official 553:063b9f2f393c 1203 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
mbed_official 553:063b9f2f393c 1204
mbed_official 553:063b9f2f393c 1205 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 553:063b9f2f393c 1206 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 553:063b9f2f393c 1207 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1208 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1209 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1210 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1211 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1212 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
mbed_official 553:063b9f2f393c 1213 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
mbed_official 553:063b9f2f393c 1214 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
mbed_official 553:063b9f2f393c 1215 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
mbed_official 553:063b9f2f393c 1216 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
mbed_official 553:063b9f2f393c 1217 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
mbed_official 553:063b9f2f393c 1218 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
mbed_official 553:063b9f2f393c 1219 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
mbed_official 553:063b9f2f393c 1220 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 553:063b9f2f393c 1221 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1222 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1223 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1224 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
mbed_official 553:063b9f2f393c 1225 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
mbed_official 553:063b9f2f393c 1226 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
mbed_official 553:063b9f2f393c 1227 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1228 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1229 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
mbed_official 553:063b9f2f393c 1230
mbed_official 553:063b9f2f393c 1231 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 553:063b9f2f393c 1232 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
mbed_official 553:063b9f2f393c 1233 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
mbed_official 553:063b9f2f393c 1234 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
mbed_official 553:063b9f2f393c 1235 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
mbed_official 553:063b9f2f393c 1236 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
mbed_official 553:063b9f2f393c 1237 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
mbed_official 553:063b9f2f393c 1238 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 553:063b9f2f393c 1239 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1240 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1241 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1242 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1243 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
mbed_official 553:063b9f2f393c 1244 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1245 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1246 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
mbed_official 553:063b9f2f393c 1247 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 553:063b9f2f393c 1248 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1249 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1250 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1251 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1252 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
mbed_official 553:063b9f2f393c 1253 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1254 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1255 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
mbed_official 553:063b9f2f393c 1256
mbed_official 553:063b9f2f393c 1257 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 553:063b9f2f393c 1258 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 553:063b9f2f393c 1259 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1260 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1261 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1262 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 553:063b9f2f393c 1263 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1264 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1265 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1266 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 553:063b9f2f393c 1267 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1268 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1269 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1270 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 553:063b9f2f393c 1271 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1272 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1273 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1274 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 553:063b9f2f393c 1275 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1276 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1277 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1278 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 553:063b9f2f393c 1279 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1280 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1281 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1282 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 553:063b9f2f393c 1283 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1284 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1285 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1286 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 553:063b9f2f393c 1287 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1288 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1289 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1290 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 553:063b9f2f393c 1291 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1292 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1293 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1294
mbed_official 553:063b9f2f393c 1295 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 553:063b9f2f393c 1296 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 553:063b9f2f393c 1297 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1298 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1299 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1300 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 553:063b9f2f393c 1301 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1302 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1303 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1304 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 553:063b9f2f393c 1305 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1306 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1307 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1308 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 553:063b9f2f393c 1309 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1310 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1311 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1312 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 553:063b9f2f393c 1313 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1314 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1315 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1316 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 553:063b9f2f393c 1317 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1318 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1319 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1320 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 553:063b9f2f393c 1321 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1322 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1323 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1324 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 553:063b9f2f393c 1325 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1326 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1327 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1328 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 553:063b9f2f393c 1329 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1330 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1331 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1332 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 553:063b9f2f393c 1333 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1334 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1335 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1336
mbed_official 553:063b9f2f393c 1337 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 553:063b9f2f393c 1338 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
mbed_official 553:063b9f2f393c 1339
mbed_official 553:063b9f2f393c 1340 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 553:063b9f2f393c 1341 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
mbed_official 553:063b9f2f393c 1342
mbed_official 553:063b9f2f393c 1343 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 553:063b9f2f393c 1344 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
mbed_official 553:063b9f2f393c 1345
mbed_official 553:063b9f2f393c 1346 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 553:063b9f2f393c 1347 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
mbed_official 553:063b9f2f393c 1348
mbed_official 553:063b9f2f393c 1349 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 553:063b9f2f393c 1350 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
mbed_official 553:063b9f2f393c 1351
mbed_official 553:063b9f2f393c 1352 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 553:063b9f2f393c 1353 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
mbed_official 553:063b9f2f393c 1354
mbed_official 553:063b9f2f393c 1355 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 553:063b9f2f393c 1356 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1357 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1358 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1359 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1360 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1361 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1362 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1363 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1364 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1365 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1366 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1367 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1368 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1369 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1370 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1371 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1372 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1373 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1374 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1375 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1376 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1377 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1378 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1379 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1380 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
mbed_official 553:063b9f2f393c 1381 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1382 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1383 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1384 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1385
mbed_official 553:063b9f2f393c 1386 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 553:063b9f2f393c 1387 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1388 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1389 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1390 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1391 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1392 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1393 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1394 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1395 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1396 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1397 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1398 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1399 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1400 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1401 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1402 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1403 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1404 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1405 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1406 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1407 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1408 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1409 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1410 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1411 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1412 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1413 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1414 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1415 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1416 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1417 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1418 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1419 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1420 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1421 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1422 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1423
mbed_official 553:063b9f2f393c 1424 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 553:063b9f2f393c 1425 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1426 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1427 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1428 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1429 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1430 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1431 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1432 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1433 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1434 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1435 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1436 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1437 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1438 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1439 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1440 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1441 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1442 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1443 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1444 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1445 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1446 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1447 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1448 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1449 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1450 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1451 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1452 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1453 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1454 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1455 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 553:063b9f2f393c 1456 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1457 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1458 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1459 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1460 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1461
mbed_official 553:063b9f2f393c 1462 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 553:063b9f2f393c 1463 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 553:063b9f2f393c 1464 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1465 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1466 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1467 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1468 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1469 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 553:063b9f2f393c 1470 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1471 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1472 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1473 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1474 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1475 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 553:063b9f2f393c 1476 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1477 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1478 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1479 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1480 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1481 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 553:063b9f2f393c 1482 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1483 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1484 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1485 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1486 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1487 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
mbed_official 553:063b9f2f393c 1488 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1489 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1490
mbed_official 553:063b9f2f393c 1491 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 553:063b9f2f393c 1492 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 553:063b9f2f393c 1493
mbed_official 553:063b9f2f393c 1494 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 553:063b9f2f393c 1495 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 553:063b9f2f393c 1496
mbed_official 553:063b9f2f393c 1497 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 553:063b9f2f393c 1498 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 553:063b9f2f393c 1499
mbed_official 553:063b9f2f393c 1500 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 553:063b9f2f393c 1501 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 553:063b9f2f393c 1502
mbed_official 553:063b9f2f393c 1503 /******************** Bit definition for ADC_DR register ********************/
mbed_official 553:063b9f2f393c 1504 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
mbed_official 553:063b9f2f393c 1505 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
mbed_official 553:063b9f2f393c 1506
mbed_official 553:063b9f2f393c 1507 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 553:063b9f2f393c 1508 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
mbed_official 553:063b9f2f393c 1509 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
mbed_official 553:063b9f2f393c 1510 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
mbed_official 553:063b9f2f393c 1511 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
mbed_official 553:063b9f2f393c 1512 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
mbed_official 553:063b9f2f393c 1513 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
mbed_official 553:063b9f2f393c 1514 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
mbed_official 553:063b9f2f393c 1515 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
mbed_official 553:063b9f2f393c 1516 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
mbed_official 553:063b9f2f393c 1517 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
mbed_official 553:063b9f2f393c 1518 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
mbed_official 553:063b9f2f393c 1519 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
mbed_official 553:063b9f2f393c 1520 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
mbed_official 553:063b9f2f393c 1521 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
mbed_official 553:063b9f2f393c 1522 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
mbed_official 553:063b9f2f393c 1523 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
mbed_official 553:063b9f2f393c 1524 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
mbed_official 553:063b9f2f393c 1525 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
mbed_official 553:063b9f2f393c 1526
mbed_official 553:063b9f2f393c 1527 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 553:063b9f2f393c 1528 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
mbed_official 553:063b9f2f393c 1529 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1530 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1531 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1532 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1533 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 1534 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
mbed_official 553:063b9f2f393c 1535 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1536 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1537 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1538 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1539 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
mbed_official 553:063b9f2f393c 1540 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
mbed_official 553:063b9f2f393c 1541 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1542 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1543 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 553:063b9f2f393c 1544 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1545 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1546 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
mbed_official 553:063b9f2f393c 1547 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
mbed_official 553:063b9f2f393c 1548
mbed_official 553:063b9f2f393c 1549 /******************* Bit definition for ADC_CDR register ********************/
mbed_official 553:063b9f2f393c 1550 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
mbed_official 553:063b9f2f393c 1551 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
mbed_official 553:063b9f2f393c 1552
mbed_official 553:063b9f2f393c 1553 /******************************************************************************/
mbed_official 553:063b9f2f393c 1554 /* */
mbed_official 553:063b9f2f393c 1555 /* Controller Area Network */
mbed_official 553:063b9f2f393c 1556 /* */
mbed_official 553:063b9f2f393c 1557 /******************************************************************************/
mbed_official 553:063b9f2f393c 1558 /*!<CAN control and status registers */
mbed_official 553:063b9f2f393c 1559 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 553:063b9f2f393c 1560 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 553:063b9f2f393c 1561 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 553:063b9f2f393c 1562 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 553:063b9f2f393c 1563 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 553:063b9f2f393c 1564 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 553:063b9f2f393c 1565 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 553:063b9f2f393c 1566 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 553:063b9f2f393c 1567 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 553:063b9f2f393c 1568 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 553:063b9f2f393c 1569 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
mbed_official 553:063b9f2f393c 1570 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 553:063b9f2f393c 1571 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
mbed_official 553:063b9f2f393c 1572 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
mbed_official 553:063b9f2f393c 1573 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
mbed_official 553:063b9f2f393c 1574 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
mbed_official 553:063b9f2f393c 1575 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
mbed_official 553:063b9f2f393c 1576 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
mbed_official 553:063b9f2f393c 1577 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
mbed_official 553:063b9f2f393c 1578 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
mbed_official 553:063b9f2f393c 1579 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
mbed_official 553:063b9f2f393c 1580
mbed_official 553:063b9f2f393c 1581 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 553:063b9f2f393c 1582 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 553:063b9f2f393c 1583 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 553:063b9f2f393c 1584 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 553:063b9f2f393c 1585 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 553:063b9f2f393c 1586 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 553:063b9f2f393c 1587 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 553:063b9f2f393c 1588 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 553:063b9f2f393c 1589 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 553:063b9f2f393c 1590 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 553:063b9f2f393c 1591 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 553:063b9f2f393c 1592 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 553:063b9f2f393c 1593 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 553:063b9f2f393c 1594 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 553:063b9f2f393c 1595 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 553:063b9f2f393c 1596 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 553:063b9f2f393c 1597 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 553:063b9f2f393c 1598
mbed_official 553:063b9f2f393c 1599 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 553:063b9f2f393c 1600 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 553:063b9f2f393c 1601 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 553:063b9f2f393c 1602 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 553:063b9f2f393c 1603
mbed_official 553:063b9f2f393c 1604 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 553:063b9f2f393c 1605 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 553:063b9f2f393c 1606 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 553:063b9f2f393c 1607 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 553:063b9f2f393c 1608
mbed_official 553:063b9f2f393c 1609 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 553:063b9f2f393c 1610 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
mbed_official 553:063b9f2f393c 1611 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
mbed_official 553:063b9f2f393c 1612 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
mbed_official 553:063b9f2f393c 1613 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
mbed_official 553:063b9f2f393c 1614
mbed_official 553:063b9f2f393c 1615 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 553:063b9f2f393c 1616 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
mbed_official 553:063b9f2f393c 1617 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
mbed_official 553:063b9f2f393c 1618 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
mbed_official 553:063b9f2f393c 1619 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
mbed_official 553:063b9f2f393c 1620
mbed_official 553:063b9f2f393c 1621 /******************** Bit definition for CAN_IER register *******************/
mbed_official 553:063b9f2f393c 1622 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 553:063b9f2f393c 1623 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 553:063b9f2f393c 1624 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 553:063b9f2f393c 1625 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 553:063b9f2f393c 1626 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 553:063b9f2f393c 1627 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 553:063b9f2f393c 1628 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 553:063b9f2f393c 1629 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 553:063b9f2f393c 1630 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 553:063b9f2f393c 1631 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 553:063b9f2f393c 1632 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 553:063b9f2f393c 1633 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 553:063b9f2f393c 1634 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 553:063b9f2f393c 1635 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 553:063b9f2f393c 1636 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
mbed_official 553:063b9f2f393c 1637 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
mbed_official 553:063b9f2f393c 1638 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
mbed_official 553:063b9f2f393c 1639 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
mbed_official 553:063b9f2f393c 1640 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
mbed_official 553:063b9f2f393c 1641
mbed_official 553:063b9f2f393c 1642
mbed_official 553:063b9f2f393c 1643 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 553:063b9f2f393c 1644 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 553:063b9f2f393c 1645 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 553:063b9f2f393c 1646 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 553:063b9f2f393c 1647
mbed_official 553:063b9f2f393c 1648 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 553:063b9f2f393c 1649 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1650 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1651 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1652
mbed_official 553:063b9f2f393c 1653 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 553:063b9f2f393c 1654 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 553:063b9f2f393c 1655
mbed_official 553:063b9f2f393c 1656 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 553:063b9f2f393c 1657 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 553:063b9f2f393c 1658 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 553:063b9f2f393c 1659 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1660 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1661 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1662 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 1663 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 553:063b9f2f393c 1664 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1665 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1666 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 1667 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 553:063b9f2f393c 1668 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 1669 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 1670 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 553:063b9f2f393c 1671 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 553:063b9f2f393c 1672
mbed_official 553:063b9f2f393c 1673
mbed_official 553:063b9f2f393c 1674 /*!<Mailbox registers */
mbed_official 553:063b9f2f393c 1675 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 553:063b9f2f393c 1676 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 553:063b9f2f393c 1677 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 553:063b9f2f393c 1678 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 553:063b9f2f393c 1679 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 553:063b9f2f393c 1680 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 553:063b9f2f393c 1681
mbed_official 553:063b9f2f393c 1682 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 553:063b9f2f393c 1683 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 553:063b9f2f393c 1684 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 553:063b9f2f393c 1685 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 553:063b9f2f393c 1686
mbed_official 553:063b9f2f393c 1687 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 553:063b9f2f393c 1688 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 553:063b9f2f393c 1689 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 553:063b9f2f393c 1690 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 553:063b9f2f393c 1691 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 553:063b9f2f393c 1692
mbed_official 553:063b9f2f393c 1693 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 553:063b9f2f393c 1694 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 553:063b9f2f393c 1695 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 553:063b9f2f393c 1696 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 553:063b9f2f393c 1697 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 553:063b9f2f393c 1698
mbed_official 553:063b9f2f393c 1699 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 553:063b9f2f393c 1700 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 553:063b9f2f393c 1701 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 553:063b9f2f393c 1702 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 553:063b9f2f393c 1703 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 553:063b9f2f393c 1704 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 553:063b9f2f393c 1705
mbed_official 553:063b9f2f393c 1706 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 553:063b9f2f393c 1707 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 553:063b9f2f393c 1708 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 553:063b9f2f393c 1709 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 553:063b9f2f393c 1710
mbed_official 553:063b9f2f393c 1711 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 553:063b9f2f393c 1712 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 553:063b9f2f393c 1713 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 553:063b9f2f393c 1714 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 553:063b9f2f393c 1715 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 553:063b9f2f393c 1716
mbed_official 553:063b9f2f393c 1717 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 553:063b9f2f393c 1718 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 553:063b9f2f393c 1719 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 553:063b9f2f393c 1720 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 553:063b9f2f393c 1721 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 553:063b9f2f393c 1722
mbed_official 553:063b9f2f393c 1723 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 553:063b9f2f393c 1724 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 553:063b9f2f393c 1725 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 553:063b9f2f393c 1726 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 553:063b9f2f393c 1727 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 553:063b9f2f393c 1728 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 553:063b9f2f393c 1729
mbed_official 553:063b9f2f393c 1730 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 553:063b9f2f393c 1731 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 553:063b9f2f393c 1732 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 553:063b9f2f393c 1733 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 553:063b9f2f393c 1734
mbed_official 553:063b9f2f393c 1735 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 553:063b9f2f393c 1736 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 553:063b9f2f393c 1737 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 553:063b9f2f393c 1738 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 553:063b9f2f393c 1739 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 553:063b9f2f393c 1740
mbed_official 553:063b9f2f393c 1741 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 553:063b9f2f393c 1742 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 553:063b9f2f393c 1743 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 553:063b9f2f393c 1744 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 553:063b9f2f393c 1745 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 553:063b9f2f393c 1746
mbed_official 553:063b9f2f393c 1747 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 553:063b9f2f393c 1748 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 553:063b9f2f393c 1749 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 553:063b9f2f393c 1750 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 553:063b9f2f393c 1751 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 553:063b9f2f393c 1752
mbed_official 553:063b9f2f393c 1753 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 553:063b9f2f393c 1754 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 553:063b9f2f393c 1755 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 553:063b9f2f393c 1756 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 553:063b9f2f393c 1757
mbed_official 553:063b9f2f393c 1758 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 553:063b9f2f393c 1759 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 553:063b9f2f393c 1760 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 553:063b9f2f393c 1761 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 553:063b9f2f393c 1762 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 553:063b9f2f393c 1763
mbed_official 553:063b9f2f393c 1764 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 553:063b9f2f393c 1765 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 553:063b9f2f393c 1766 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 553:063b9f2f393c 1767 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 553:063b9f2f393c 1768 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 553:063b9f2f393c 1769
mbed_official 553:063b9f2f393c 1770 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 553:063b9f2f393c 1771 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 553:063b9f2f393c 1772 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 553:063b9f2f393c 1773 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 553:063b9f2f393c 1774 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 553:063b9f2f393c 1775
mbed_official 553:063b9f2f393c 1776 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 553:063b9f2f393c 1777 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 553:063b9f2f393c 1778 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 553:063b9f2f393c 1779 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 553:063b9f2f393c 1780
mbed_official 553:063b9f2f393c 1781 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 553:063b9f2f393c 1782 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 553:063b9f2f393c 1783 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 553:063b9f2f393c 1784 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 553:063b9f2f393c 1785 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 553:063b9f2f393c 1786
mbed_official 553:063b9f2f393c 1787 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 553:063b9f2f393c 1788 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 553:063b9f2f393c 1789 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 553:063b9f2f393c 1790 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 553:063b9f2f393c 1791 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 553:063b9f2f393c 1792
mbed_official 553:063b9f2f393c 1793 /*!<CAN filter registers */
mbed_official 553:063b9f2f393c 1794 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 553:063b9f2f393c 1795 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
mbed_official 553:063b9f2f393c 1796 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
mbed_official 553:063b9f2f393c 1797
mbed_official 553:063b9f2f393c 1798 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 553:063b9f2f393c 1799 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
mbed_official 553:063b9f2f393c 1800 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 553:063b9f2f393c 1801 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 553:063b9f2f393c 1802 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 553:063b9f2f393c 1803 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 553:063b9f2f393c 1804 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 553:063b9f2f393c 1805 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 553:063b9f2f393c 1806 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 553:063b9f2f393c 1807 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 553:063b9f2f393c 1808 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 553:063b9f2f393c 1809 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 553:063b9f2f393c 1810 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 553:063b9f2f393c 1811 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 553:063b9f2f393c 1812 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 553:063b9f2f393c 1813 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 553:063b9f2f393c 1814 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
mbed_official 553:063b9f2f393c 1815 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
mbed_official 553:063b9f2f393c 1816 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
mbed_official 553:063b9f2f393c 1817 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
mbed_official 553:063b9f2f393c 1818 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
mbed_official 553:063b9f2f393c 1819 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
mbed_official 553:063b9f2f393c 1820 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
mbed_official 553:063b9f2f393c 1821 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
mbed_official 553:063b9f2f393c 1822 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
mbed_official 553:063b9f2f393c 1823 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
mbed_official 553:063b9f2f393c 1824 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
mbed_official 553:063b9f2f393c 1825 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
mbed_official 553:063b9f2f393c 1826 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
mbed_official 553:063b9f2f393c 1827 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
mbed_official 553:063b9f2f393c 1828
mbed_official 553:063b9f2f393c 1829 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 553:063b9f2f393c 1830 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
mbed_official 553:063b9f2f393c 1831 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 553:063b9f2f393c 1832 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 553:063b9f2f393c 1833 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 553:063b9f2f393c 1834 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 553:063b9f2f393c 1835 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 553:063b9f2f393c 1836 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 553:063b9f2f393c 1837 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 553:063b9f2f393c 1838 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 553:063b9f2f393c 1839 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 553:063b9f2f393c 1840 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 553:063b9f2f393c 1841 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 553:063b9f2f393c 1842 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 553:063b9f2f393c 1843 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 553:063b9f2f393c 1844 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 553:063b9f2f393c 1845 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
mbed_official 553:063b9f2f393c 1846 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
mbed_official 553:063b9f2f393c 1847 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
mbed_official 553:063b9f2f393c 1848 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
mbed_official 553:063b9f2f393c 1849 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
mbed_official 553:063b9f2f393c 1850 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
mbed_official 553:063b9f2f393c 1851 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
mbed_official 553:063b9f2f393c 1852 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
mbed_official 553:063b9f2f393c 1853 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
mbed_official 553:063b9f2f393c 1854 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
mbed_official 553:063b9f2f393c 1855 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
mbed_official 553:063b9f2f393c 1856 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
mbed_official 553:063b9f2f393c 1857 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
mbed_official 553:063b9f2f393c 1858 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
mbed_official 553:063b9f2f393c 1859
mbed_official 553:063b9f2f393c 1860 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 553:063b9f2f393c 1861 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
mbed_official 553:063b9f2f393c 1862 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
mbed_official 553:063b9f2f393c 1863 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
mbed_official 553:063b9f2f393c 1864 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
mbed_official 553:063b9f2f393c 1865 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
mbed_official 553:063b9f2f393c 1866 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
mbed_official 553:063b9f2f393c 1867 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
mbed_official 553:063b9f2f393c 1868 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
mbed_official 553:063b9f2f393c 1869 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
mbed_official 553:063b9f2f393c 1870 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
mbed_official 553:063b9f2f393c 1871 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
mbed_official 553:063b9f2f393c 1872 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
mbed_official 553:063b9f2f393c 1873 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
mbed_official 553:063b9f2f393c 1874 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
mbed_official 553:063b9f2f393c 1875 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
mbed_official 553:063b9f2f393c 1876 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
mbed_official 553:063b9f2f393c 1877 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
mbed_official 553:063b9f2f393c 1878 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
mbed_official 553:063b9f2f393c 1879 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
mbed_official 553:063b9f2f393c 1880 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
mbed_official 553:063b9f2f393c 1881 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
mbed_official 553:063b9f2f393c 1882 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
mbed_official 553:063b9f2f393c 1883 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
mbed_official 553:063b9f2f393c 1884 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
mbed_official 553:063b9f2f393c 1885 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
mbed_official 553:063b9f2f393c 1886 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
mbed_official 553:063b9f2f393c 1887 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
mbed_official 553:063b9f2f393c 1888 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
mbed_official 553:063b9f2f393c 1889 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
mbed_official 553:063b9f2f393c 1890
mbed_official 553:063b9f2f393c 1891 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 553:063b9f2f393c 1892 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
mbed_official 553:063b9f2f393c 1893 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
mbed_official 553:063b9f2f393c 1894 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
mbed_official 553:063b9f2f393c 1895 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
mbed_official 553:063b9f2f393c 1896 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
mbed_official 553:063b9f2f393c 1897 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
mbed_official 553:063b9f2f393c 1898 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
mbed_official 553:063b9f2f393c 1899 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
mbed_official 553:063b9f2f393c 1900 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
mbed_official 553:063b9f2f393c 1901 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
mbed_official 553:063b9f2f393c 1902 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
mbed_official 553:063b9f2f393c 1903 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
mbed_official 553:063b9f2f393c 1904 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
mbed_official 553:063b9f2f393c 1905 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
mbed_official 553:063b9f2f393c 1906 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
mbed_official 553:063b9f2f393c 1907 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
mbed_official 553:063b9f2f393c 1908 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
mbed_official 553:063b9f2f393c 1909 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
mbed_official 553:063b9f2f393c 1910 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
mbed_official 553:063b9f2f393c 1911 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
mbed_official 553:063b9f2f393c 1912 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
mbed_official 553:063b9f2f393c 1913 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
mbed_official 553:063b9f2f393c 1914 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
mbed_official 553:063b9f2f393c 1915 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
mbed_official 553:063b9f2f393c 1916 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
mbed_official 553:063b9f2f393c 1917 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
mbed_official 553:063b9f2f393c 1918 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
mbed_official 553:063b9f2f393c 1919 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
mbed_official 553:063b9f2f393c 1920 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
mbed_official 553:063b9f2f393c 1921
mbed_official 553:063b9f2f393c 1922
mbed_official 553:063b9f2f393c 1923 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 553:063b9f2f393c 1924 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 1925 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 1926 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 1927 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 1928 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 1929 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 1930 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 1931 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 1932 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 1933 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 1934 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 1935 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 1936 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 1937 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 1938 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 1939 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 1940 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 1941 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 1942 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 1943 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 1944 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 1945 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 1946 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 1947 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 1948 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 1949 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 1950 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 1951 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 1952 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 1953 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 1954 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 1955 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 1956
mbed_official 553:063b9f2f393c 1957 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 553:063b9f2f393c 1958 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 1959 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 1960 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 1961 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 1962 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 1963 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 1964 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 1965 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 1966 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 1967 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 1968 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 1969 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 1970 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 1971 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 1972 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 1973 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 1974 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 1975 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 1976 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 1977 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 1978 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 1979 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 1980 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 1981 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 1982 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 1983 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 1984 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 1985 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 1986 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 1987 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 1988 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 1989 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 1990
mbed_official 553:063b9f2f393c 1991 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 553:063b9f2f393c 1992 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 1993 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 1994 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 1995 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 1996 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 1997 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 1998 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 1999 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2000 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2001 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2002 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2003 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2004 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2005 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2006 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2007 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2008 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2009 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2010 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2011 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2012 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2013 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2014 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2015 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2016 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2017 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2018 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2019 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2020 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2021 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2022 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2023 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2024
mbed_official 553:063b9f2f393c 2025 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 553:063b9f2f393c 2026 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2027 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2028 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2029 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2030 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2031 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2032 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2033 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2034 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2035 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2036 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2037 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2038 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2039 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2040 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2041 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2042 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2043 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2044 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2045 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2046 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2047 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2048 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2049 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2050 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2051 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2052 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2053 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2054 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2055 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2056 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2057 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2058
mbed_official 553:063b9f2f393c 2059 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 553:063b9f2f393c 2060 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2061 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2062 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2063 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2064 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2065 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2066 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2067 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2068 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2069 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2070 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2071 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2072 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2073 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2074 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2075 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2076 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2077 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2078 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2079 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2080 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2081 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2082 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2083 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2084 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2085 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2086 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2087 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2088 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2089 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2090 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2091 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2092
mbed_official 553:063b9f2f393c 2093 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 553:063b9f2f393c 2094 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2095 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2096 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2097 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2098 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2099 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2100 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2101 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2102 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2103 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2104 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2105 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2106 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2107 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2108 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2109 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2110 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2111 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2112 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2113 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2114 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2115 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2116 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2117 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2118 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2119 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2120 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2121 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2122 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2123 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2124 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2125 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2126
mbed_official 553:063b9f2f393c 2127 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 553:063b9f2f393c 2128 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2129 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2130 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2131 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2132 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2133 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2134 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2135 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2136 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2137 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2138 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2139 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2140 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2141 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2142 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2143 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2144 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2145 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2146 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2147 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2148 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2149 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2150 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2151 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2152 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2153 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2154 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2155 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2156 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2157 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2158 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2159 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2160
mbed_official 553:063b9f2f393c 2161 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 553:063b9f2f393c 2162 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2163 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2164 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2165 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2166 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2167 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2168 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2169 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2170 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2171 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2172 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2173 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2174 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2175 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2176 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2177 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2178 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2179 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2180 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2181 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2182 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2183 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2184 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2185 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2186 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2187 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2188 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2189 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2190 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2191 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2192 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2193 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2194
mbed_official 553:063b9f2f393c 2195 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 553:063b9f2f393c 2196 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2197 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2198 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2199 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2200 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2201 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2202 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2203 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2204 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2205 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2206 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2207 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2208 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2209 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2210 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2211 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2212 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2213 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2214 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2215 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2216 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2217 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2218 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2219 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2220 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2221 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2222 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2223 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2224 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2225 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2226 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2227 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2228
mbed_official 553:063b9f2f393c 2229 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 553:063b9f2f393c 2230 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2231 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2232 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2233 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2234 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2235 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2236 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2237 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2238 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2239 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2240 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2241 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2242 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2243 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2244 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2245 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2246 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2247 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2248 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2249 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2250 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2251 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2252 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2253 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2254 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2255 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2256 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2257 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2258 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2259 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2260 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2261 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2262
mbed_official 553:063b9f2f393c 2263 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 553:063b9f2f393c 2264 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2265 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2266 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2267 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2268 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2269 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2270 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2271 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2272 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2273 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2274 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2275 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2276 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2277 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2278 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2279 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2280 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2281 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2282 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2283 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2284 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2285 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2286 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2287 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2288 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2289 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2290 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2291 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2292 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2293 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2294 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2295 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2296
mbed_official 553:063b9f2f393c 2297 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 553:063b9f2f393c 2298 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2299 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2300 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2301 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2302 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2303 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2304 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2305 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2306 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2307 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2308 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2309 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2310 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2311 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2312 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2313 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2314 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2315 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2316 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2317 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2318 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2319 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2320 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2321 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2322 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2323 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2324 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2325 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2326 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2327 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2328 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2329 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2330
mbed_official 553:063b9f2f393c 2331 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 553:063b9f2f393c 2332 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2333 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2334 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2335 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2336 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2337 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2338 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2339 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2340 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2341 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2342 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2343 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2344 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2345 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2346 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2347 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2348 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2349 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2350 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2351 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2352 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2353 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2354 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2355 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2356 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2357 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2358 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2359 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2360 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2361 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2362 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2363 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2364
mbed_official 553:063b9f2f393c 2365 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 553:063b9f2f393c 2366 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2367 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2368 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2369 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2370 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2371 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2372 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2373 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2374 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2375 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2376 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2377 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2378 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2379 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2380 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2381 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2382 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2383 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2384 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2385 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2386 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2387 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2388 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2389 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2390 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2391 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2392 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2393 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2394 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2395 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2396 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2397 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2398
mbed_official 553:063b9f2f393c 2399 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 553:063b9f2f393c 2400 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2401 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2402 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2403 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2404 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2405 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2406 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2407 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2408 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2409 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2410 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2411 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2412 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2413 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2414 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2415 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2416 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2417 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2418 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2419 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2420 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2421 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2422 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2423 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2424 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2425 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2426 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2427 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2428 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2429 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2430 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2431 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2432
mbed_official 553:063b9f2f393c 2433 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 553:063b9f2f393c 2434 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2435 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2436 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2437 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2438 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2439 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2440 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2441 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2442 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2443 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2444 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2445 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2446 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2447 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2448 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2449 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2450 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2451 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2452 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2453 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2454 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2455 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2456 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2457 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2458 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2459 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2460 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2461 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2462 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2463 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2464 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2465 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2466
mbed_official 553:063b9f2f393c 2467 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 553:063b9f2f393c 2468 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2469 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2470 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2471 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2472 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2473 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2474 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2475 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2476 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2477 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2478 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2479 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2480 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2481 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2482 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2483 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2484 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2485 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2486 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2487 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2488 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2489 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2490 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2491 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2492 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2493 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2494 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2495 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2496 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2497 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2498 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2499 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2500
mbed_official 553:063b9f2f393c 2501 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 553:063b9f2f393c 2502 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2503 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2504 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2505 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2506 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2507 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2508 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2509 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2510 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2511 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2512 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2513 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2514 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2515 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2516 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2517 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2518 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2519 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2520 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2521 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2522 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2523 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2524 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2525 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2526 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2527 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2528 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2529 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2530 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2531 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2532 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2533 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2534
mbed_official 553:063b9f2f393c 2535 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 553:063b9f2f393c 2536 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2537 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2538 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2539 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2540 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2541 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2542 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2543 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2544 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2545 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2546 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2547 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2548 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2549 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2550 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2551 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2552 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2553 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2554 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2555 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2556 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2557 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2558 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2559 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2560 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2561 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2562 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2563 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2564 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2565 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2566 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2567 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2568
mbed_official 553:063b9f2f393c 2569 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 553:063b9f2f393c 2570 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2571 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2572 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2573 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2574 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2575 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2576 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2577 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2578 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2579 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2580 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2581 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2582 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2583 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2584 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2585 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2586 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2587 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2588 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2589 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2590 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2591 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2592 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2593 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2594 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2595 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2596 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2597 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2598 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2599 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2600 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2601 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2602
mbed_official 553:063b9f2f393c 2603 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 553:063b9f2f393c 2604 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2605 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2606 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2607 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2608 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2609 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2610 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2611 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2612 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2613 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2614 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2615 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2616 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2617 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2618 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2619 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2620 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2621 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2622 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2623 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2624 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2625 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2626 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2627 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2628 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2629 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2630 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2631 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2632 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2633 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2634 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2635 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2636
mbed_official 553:063b9f2f393c 2637 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 553:063b9f2f393c 2638 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2639 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2640 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2641 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2642 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2643 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2644 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2645 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2646 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2647 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2648 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2649 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2650 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2651 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2652 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2653 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2654 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2655 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2656 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2657 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2658 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2659 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2660 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2661 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2662 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2663 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2664 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2665 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2666 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2667 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2668 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2669 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2670
mbed_official 553:063b9f2f393c 2671 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 553:063b9f2f393c 2672 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2673 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2674 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2675 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2676 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2677 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2678 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2679 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2680 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2681 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2682 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2683 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2684 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2685 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2686 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2687 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2688 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2689 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2690 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2691 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2692 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2693 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2694 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2695 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2696 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2697 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2698 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2699 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2700 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2701 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2702 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2703 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2704
mbed_official 553:063b9f2f393c 2705 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 553:063b9f2f393c 2706 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2707 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2708 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2709 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2710 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2711 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2712 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2713 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2714 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2715 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2716 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2717 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2718 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2719 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2720 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2721 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2722 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2723 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2724 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2725 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2726 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2727 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2728 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2729 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2730 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2731 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2732 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2733 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2734 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2735 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2736 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2737 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2738
mbed_official 553:063b9f2f393c 2739 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 553:063b9f2f393c 2740 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2741 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2742 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2743 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2744 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2745 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2746 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2747 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2748 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2749 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2750 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2751 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2752 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2753 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2754 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2755 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2756 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2757 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2758 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2759 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2760 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2761 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2762 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2763 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2764 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2765 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2766 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2767 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2768 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2769 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2770 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2771 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2772
mbed_official 553:063b9f2f393c 2773 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 553:063b9f2f393c 2774 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2775 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2776 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2777 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2778 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2779 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2780 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2781 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2782 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2783 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2784 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2785 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2786 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2787 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2788 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2789 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2790 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2791 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2792 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2793 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2794 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2795 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2796 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2797 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2798 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2799 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2800 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2801 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2802 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2803 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2804 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2805 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2806
mbed_official 553:063b9f2f393c 2807 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 553:063b9f2f393c 2808 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2809 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2810 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2811 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2812 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2813 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2814 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2815 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2816 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2817 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2818 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2819 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2820 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2821 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2822 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2823 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2824 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2825 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2826 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2827 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2828 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2829 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2830 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2831 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2832 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2833 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2834 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2835 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2836 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2837 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2838 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2839 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2840
mbed_official 553:063b9f2f393c 2841 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 553:063b9f2f393c 2842 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 553:063b9f2f393c 2843 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 553:063b9f2f393c 2844 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 553:063b9f2f393c 2845 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 553:063b9f2f393c 2846 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 553:063b9f2f393c 2847 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 553:063b9f2f393c 2848 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 553:063b9f2f393c 2849 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 553:063b9f2f393c 2850 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 553:063b9f2f393c 2851 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 553:063b9f2f393c 2852 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 553:063b9f2f393c 2853 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 553:063b9f2f393c 2854 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 553:063b9f2f393c 2855 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 553:063b9f2f393c 2856 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 553:063b9f2f393c 2857 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 553:063b9f2f393c 2858 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 553:063b9f2f393c 2859 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 553:063b9f2f393c 2860 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 553:063b9f2f393c 2861 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 553:063b9f2f393c 2862 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 553:063b9f2f393c 2863 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 553:063b9f2f393c 2864 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 553:063b9f2f393c 2865 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 553:063b9f2f393c 2866 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 553:063b9f2f393c 2867 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 553:063b9f2f393c 2868 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 553:063b9f2f393c 2869 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 553:063b9f2f393c 2870 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 553:063b9f2f393c 2871 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 553:063b9f2f393c 2872 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 553:063b9f2f393c 2873 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 553:063b9f2f393c 2874
mbed_official 553:063b9f2f393c 2875 /******************************************************************************/
mbed_official 553:063b9f2f393c 2876 /* */
mbed_official 553:063b9f2f393c 2877 /* HDMI-CEC (CEC) */
mbed_official 553:063b9f2f393c 2878 /* */
mbed_official 553:063b9f2f393c 2879 /******************************************************************************/
mbed_official 553:063b9f2f393c 2880
mbed_official 553:063b9f2f393c 2881 /******************* Bit definition for CEC_CR register *********************/
mbed_official 553:063b9f2f393c 2882 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
mbed_official 553:063b9f2f393c 2883 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
mbed_official 553:063b9f2f393c 2884 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
mbed_official 553:063b9f2f393c 2885
mbed_official 553:063b9f2f393c 2886 /******************* Bit definition for CEC_CFGR register *******************/
mbed_official 553:063b9f2f393c 2887 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
mbed_official 553:063b9f2f393c 2888 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
mbed_official 553:063b9f2f393c 2889 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
mbed_official 553:063b9f2f393c 2890 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
mbed_official 553:063b9f2f393c 2891 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error generation */
mbed_official 553:063b9f2f393c 2892 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
mbed_official 553:063b9f2f393c 2893 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No error generation */
mbed_official 553:063b9f2f393c 2894 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
mbed_official 553:063b9f2f393c 2895 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
mbed_official 553:063b9f2f393c 2896
mbed_official 553:063b9f2f393c 2897 /******************* Bit definition for CEC_TXDR register *******************/
mbed_official 553:063b9f2f393c 2898 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
mbed_official 553:063b9f2f393c 2899
mbed_official 553:063b9f2f393c 2900 /******************* Bit definition for CEC_RXDR register *******************/
mbed_official 553:063b9f2f393c 2901 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
mbed_official 553:063b9f2f393c 2902
mbed_official 553:063b9f2f393c 2903 /******************* Bit definition for CEC_ISR register ********************/
mbed_official 553:063b9f2f393c 2904 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
mbed_official 553:063b9f2f393c 2905 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
mbed_official 553:063b9f2f393c 2906 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
mbed_official 553:063b9f2f393c 2907 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
mbed_official 553:063b9f2f393c 2908 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
mbed_official 553:063b9f2f393c 2909 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
mbed_official 553:063b9f2f393c 2910 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
mbed_official 553:063b9f2f393c 2911 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
mbed_official 553:063b9f2f393c 2912 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
mbed_official 553:063b9f2f393c 2913 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
mbed_official 553:063b9f2f393c 2914 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
mbed_official 553:063b9f2f393c 2915 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
mbed_official 553:063b9f2f393c 2916 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
mbed_official 553:063b9f2f393c 2917
mbed_official 553:063b9f2f393c 2918 /******************* Bit definition for CEC_IER register ********************/
mbed_official 553:063b9f2f393c 2919 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
mbed_official 553:063b9f2f393c 2920 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
mbed_official 553:063b9f2f393c 2921 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
mbed_official 553:063b9f2f393c 2922 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
mbed_official 553:063b9f2f393c 2923 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable */
mbed_official 553:063b9f2f393c 2924 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
mbed_official 553:063b9f2f393c 2925 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
mbed_official 553:063b9f2f393c 2926 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
mbed_official 553:063b9f2f393c 2927 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
mbed_official 553:063b9f2f393c 2928 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
mbed_official 553:063b9f2f393c 2929 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
mbed_official 553:063b9f2f393c 2930 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
mbed_official 553:063b9f2f393c 2931 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
mbed_official 553:063b9f2f393c 2932
mbed_official 553:063b9f2f393c 2933 /******************************************************************************/
mbed_official 553:063b9f2f393c 2934 /* */
mbed_official 553:063b9f2f393c 2935 /* CRC calculation unit */
mbed_official 553:063b9f2f393c 2936 /* */
mbed_official 553:063b9f2f393c 2937 /******************************************************************************/
mbed_official 553:063b9f2f393c 2938 /******************* Bit definition for CRC_DR register *********************/
mbed_official 553:063b9f2f393c 2939 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 553:063b9f2f393c 2940
mbed_official 553:063b9f2f393c 2941
mbed_official 553:063b9f2f393c 2942 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 553:063b9f2f393c 2943 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 553:063b9f2f393c 2944
mbed_official 553:063b9f2f393c 2945
mbed_official 553:063b9f2f393c 2946 /******************** Bit definition for CRC_CR register ********************/
mbed_official 553:063b9f2f393c 2947 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
mbed_official 553:063b9f2f393c 2948
mbed_official 553:063b9f2f393c 2949 /******************************************************************************/
mbed_official 553:063b9f2f393c 2950 /* */
mbed_official 553:063b9f2f393c 2951 /* Digital to Analog Converter */
mbed_official 553:063b9f2f393c 2952 /* */
mbed_official 553:063b9f2f393c 2953 /******************************************************************************/
mbed_official 553:063b9f2f393c 2954 /******************** Bit definition for DAC_CR register ********************/
mbed_official 553:063b9f2f393c 2955 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 553:063b9f2f393c 2956 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 553:063b9f2f393c 2957 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 553:063b9f2f393c 2958
mbed_official 553:063b9f2f393c 2959 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 553:063b9f2f393c 2960 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 2961 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 2962 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 2963
mbed_official 553:063b9f2f393c 2964 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 553:063b9f2f393c 2965 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 2966 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 2967
mbed_official 553:063b9f2f393c 2968 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 553:063b9f2f393c 2969 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 2970 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 2971 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 2972 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 2973
mbed_official 553:063b9f2f393c 2974 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 553:063b9f2f393c 2975 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 553:063b9f2f393c 2976 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 553:063b9f2f393c 2977 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 553:063b9f2f393c 2978
mbed_official 553:063b9f2f393c 2979 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 553:063b9f2f393c 2980 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 2981 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 2982 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 2983
mbed_official 553:063b9f2f393c 2984 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 553:063b9f2f393c 2985 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 2986 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 2987
mbed_official 553:063b9f2f393c 2988 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 553:063b9f2f393c 2989 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 2990 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 2991 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 2992 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 2993
mbed_official 553:063b9f2f393c 2994 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 553:063b9f2f393c 2995
mbed_official 553:063b9f2f393c 2996 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 553:063b9f2f393c 2997 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
mbed_official 553:063b9f2f393c 2998 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
mbed_official 553:063b9f2f393c 2999
mbed_official 553:063b9f2f393c 3000 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 553:063b9f2f393c 3001 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 553:063b9f2f393c 3002
mbed_official 553:063b9f2f393c 3003 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 553:063b9f2f393c 3004 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 553:063b9f2f393c 3005
mbed_official 553:063b9f2f393c 3006 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 553:063b9f2f393c 3007 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 553:063b9f2f393c 3008
mbed_official 553:063b9f2f393c 3009 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 553:063b9f2f393c 3010 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 553:063b9f2f393c 3011
mbed_official 553:063b9f2f393c 3012 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 553:063b9f2f393c 3013 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 553:063b9f2f393c 3014
mbed_official 553:063b9f2f393c 3015 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 553:063b9f2f393c 3016 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 553:063b9f2f393c 3017
mbed_official 553:063b9f2f393c 3018 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 553:063b9f2f393c 3019 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 553:063b9f2f393c 3020 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 553:063b9f2f393c 3021
mbed_official 553:063b9f2f393c 3022 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 553:063b9f2f393c 3023 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 553:063b9f2f393c 3024 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 553:063b9f2f393c 3025
mbed_official 553:063b9f2f393c 3026 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 553:063b9f2f393c 3027 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 553:063b9f2f393c 3028 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 553:063b9f2f393c 3029
mbed_official 553:063b9f2f393c 3030 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 553:063b9f2f393c 3031 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
mbed_official 553:063b9f2f393c 3032
mbed_official 553:063b9f2f393c 3033 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 553:063b9f2f393c 3034 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
mbed_official 553:063b9f2f393c 3035
mbed_official 553:063b9f2f393c 3036 /******************** Bit definition for DAC_SR register ********************/
mbed_official 553:063b9f2f393c 3037 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 553:063b9f2f393c 3038 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 553:063b9f2f393c 3039
mbed_official 553:063b9f2f393c 3040 /******************************************************************************/
mbed_official 553:063b9f2f393c 3041 /* */
mbed_official 553:063b9f2f393c 3042 /* Debug MCU */
mbed_official 553:063b9f2f393c 3043 /* */
mbed_official 553:063b9f2f393c 3044 /******************************************************************************/
mbed_official 553:063b9f2f393c 3045
mbed_official 553:063b9f2f393c 3046 /******************************************************************************/
mbed_official 553:063b9f2f393c 3047 /* */
mbed_official 553:063b9f2f393c 3048 /* DCMI */
mbed_official 553:063b9f2f393c 3049 /* */
mbed_official 553:063b9f2f393c 3050 /******************************************************************************/
mbed_official 553:063b9f2f393c 3051 /******************** Bits definition for DCMI_CR register ******************/
mbed_official 553:063b9f2f393c 3052 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3053 #define DCMI_CR_CM ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3054 #define DCMI_CR_CROP ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3055 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3056 #define DCMI_CR_ESS ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3057 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3058 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3059 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 3060 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3061 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3062 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3063 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3064 #define DCMI_CR_OUTEN ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 3065 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 3066 #define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3067 #define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 3068 #define DCMI_CR_OEBS ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3069 #define DCMI_CR_LSM ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3070 #define DCMI_CR_OELS ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3071
mbed_official 553:063b9f2f393c 3072 /******************** Bits definition for DCMI_SR register ******************/
mbed_official 553:063b9f2f393c 3073 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3074 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3075 #define DCMI_SR_FNE ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3076
mbed_official 553:063b9f2f393c 3077 /******************** Bits definition for DCMI_RISR register ****************/
mbed_official 553:063b9f2f393c 3078 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3079 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3080 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3081 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3082 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3083
mbed_official 553:063b9f2f393c 3084 /******************** Bits definition for DCMI_IER register *****************/
mbed_official 553:063b9f2f393c 3085 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3086 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3087 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3088 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3089 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3090
mbed_official 553:063b9f2f393c 3091 /******************** Bits definition for DCMI_MISR register ****************/
mbed_official 553:063b9f2f393c 3092 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3093 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3094 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3095 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3096 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3097
mbed_official 553:063b9f2f393c 3098 /******************** Bits definition for DCMI_ICR register *****************/
mbed_official 553:063b9f2f393c 3099 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3100 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3101 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3102 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3103 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3104
mbed_official 553:063b9f2f393c 3105 /******************************************************************************/
mbed_official 553:063b9f2f393c 3106 /* */
mbed_official 553:063b9f2f393c 3107 /* DMA Controller */
mbed_official 553:063b9f2f393c 3108 /* */
mbed_official 553:063b9f2f393c 3109 /******************************************************************************/
mbed_official 553:063b9f2f393c 3110 /******************** Bits definition for DMA_SxCR register *****************/
mbed_official 553:063b9f2f393c 3111 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
mbed_official 553:063b9f2f393c 3112 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 3113 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 3114 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 3115 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
mbed_official 553:063b9f2f393c 3116 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 3117 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3118 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
mbed_official 553:063b9f2f393c 3119 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 3120 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 3121 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3122 #define DMA_SxCR_CT ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3123 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3124 #define DMA_SxCR_PL ((uint32_t)0x00030000)
mbed_official 553:063b9f2f393c 3125 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3126 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 3127 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 3128 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
mbed_official 553:063b9f2f393c 3129 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 3130 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 3131 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
mbed_official 553:063b9f2f393c 3132 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3133 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 3134 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3135 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3136 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3137 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
mbed_official 553:063b9f2f393c 3138 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3139 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 3140 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3141 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3142 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3143 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3144 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3145 #define DMA_SxCR_EN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3146
mbed_official 553:063b9f2f393c 3147 /******************** Bits definition for DMA_SxCNDTR register **************/
mbed_official 553:063b9f2f393c 3148 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
mbed_official 553:063b9f2f393c 3149 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3150 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3151 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3152 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3153 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3154 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3155 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3156 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 3157 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3158 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3159 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3160 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3161 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 3162 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 3163 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 3164 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 3165
mbed_official 553:063b9f2f393c 3166 /******************** Bits definition for DMA_SxFCR register ****************/
mbed_official 553:063b9f2f393c 3167 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 3168 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
mbed_official 553:063b9f2f393c 3169 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3170 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3171 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3172 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3173 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
mbed_official 553:063b9f2f393c 3174 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3175 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3176
mbed_official 553:063b9f2f393c 3177 /******************** Bits definition for DMA_LISR register *****************/
mbed_official 553:063b9f2f393c 3178 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 3179 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 3180 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 3181 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3182 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 3183 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 3184 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3185 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3186 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3187 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3188 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3189 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3190 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3191 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3192 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3193 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3194 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3195 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3196 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3197 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3198
mbed_official 553:063b9f2f393c 3199 /******************** Bits definition for DMA_HISR register *****************/
mbed_official 553:063b9f2f393c 3200 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 3201 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 3202 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 3203 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3204 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 3205 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 3206 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3207 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3208 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3209 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3210 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3211 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3212 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3213 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3214 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3215 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3216 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3217 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3218 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3219 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3220
mbed_official 553:063b9f2f393c 3221 /******************** Bits definition for DMA_LIFCR register ****************/
mbed_official 553:063b9f2f393c 3222 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 3223 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 3224 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 3225 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3226 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 3227 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 3228 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3229 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3230 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3231 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3232 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3233 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3234 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3235 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3236 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3237 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3238 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3239 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3240 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3241 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3242
mbed_official 553:063b9f2f393c 3243 /******************** Bits definition for DMA_HIFCR register ****************/
mbed_official 553:063b9f2f393c 3244 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 3245 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 3246 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 3247 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3248 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 3249 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 3250 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3251 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3252 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3253 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3254 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3255 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3256 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3257 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3258 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3259 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3260 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3261 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3262 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3263 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3264
mbed_official 553:063b9f2f393c 3265
mbed_official 553:063b9f2f393c 3266 /******************************************************************************/
mbed_official 553:063b9f2f393c 3267 /* */
mbed_official 553:063b9f2f393c 3268 /* External Interrupt/Event Controller */
mbed_official 553:063b9f2f393c 3269 /* */
mbed_official 553:063b9f2f393c 3270 /******************************************************************************/
mbed_official 553:063b9f2f393c 3271 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 553:063b9f2f393c 3272 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 553:063b9f2f393c 3273 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 553:063b9f2f393c 3274 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 553:063b9f2f393c 3275 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 553:063b9f2f393c 3276 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 553:063b9f2f393c 3277 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 553:063b9f2f393c 3278 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 553:063b9f2f393c 3279 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 553:063b9f2f393c 3280 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 553:063b9f2f393c 3281 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 553:063b9f2f393c 3282 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 553:063b9f2f393c 3283 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 553:063b9f2f393c 3284 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 553:063b9f2f393c 3285 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 553:063b9f2f393c 3286 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 553:063b9f2f393c 3287 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 553:063b9f2f393c 3288 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 553:063b9f2f393c 3289 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 553:063b9f2f393c 3290 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 553:063b9f2f393c 3291 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 553:063b9f2f393c 3292 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 553:063b9f2f393c 3293 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 553:063b9f2f393c 3294 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 553:063b9f2f393c 3295
mbed_official 553:063b9f2f393c 3296 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 553:063b9f2f393c 3297 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 553:063b9f2f393c 3298 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 553:063b9f2f393c 3299 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 553:063b9f2f393c 3300 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 553:063b9f2f393c 3301 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 553:063b9f2f393c 3302 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 553:063b9f2f393c 3303 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 553:063b9f2f393c 3304 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 553:063b9f2f393c 3305 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 553:063b9f2f393c 3306 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 553:063b9f2f393c 3307 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 553:063b9f2f393c 3308 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 553:063b9f2f393c 3309 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 553:063b9f2f393c 3310 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 553:063b9f2f393c 3311 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 553:063b9f2f393c 3312 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 553:063b9f2f393c 3313 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 553:063b9f2f393c 3314 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 553:063b9f2f393c 3315 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 553:063b9f2f393c 3316 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 553:063b9f2f393c 3317 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 553:063b9f2f393c 3318 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 553:063b9f2f393c 3319 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 553:063b9f2f393c 3320
mbed_official 553:063b9f2f393c 3321 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 553:063b9f2f393c 3322 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 553:063b9f2f393c 3323 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 553:063b9f2f393c 3324 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 553:063b9f2f393c 3325 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 553:063b9f2f393c 3326 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 553:063b9f2f393c 3327 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 553:063b9f2f393c 3328 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 553:063b9f2f393c 3329 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 553:063b9f2f393c 3330 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 553:063b9f2f393c 3331 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 553:063b9f2f393c 3332 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 553:063b9f2f393c 3333 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 553:063b9f2f393c 3334 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 553:063b9f2f393c 3335 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 553:063b9f2f393c 3336 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 553:063b9f2f393c 3337 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 553:063b9f2f393c 3338 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 553:063b9f2f393c 3339 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 553:063b9f2f393c 3340 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 553:063b9f2f393c 3341 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 553:063b9f2f393c 3342 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 553:063b9f2f393c 3343 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 553:063b9f2f393c 3344 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 553:063b9f2f393c 3345
mbed_official 553:063b9f2f393c 3346 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 553:063b9f2f393c 3347 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 553:063b9f2f393c 3348 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 553:063b9f2f393c 3349 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 553:063b9f2f393c 3350 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 553:063b9f2f393c 3351 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 553:063b9f2f393c 3352 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 553:063b9f2f393c 3353 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 553:063b9f2f393c 3354 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 553:063b9f2f393c 3355 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 553:063b9f2f393c 3356 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 553:063b9f2f393c 3357 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 553:063b9f2f393c 3358 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 553:063b9f2f393c 3359 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 553:063b9f2f393c 3360 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 553:063b9f2f393c 3361 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 553:063b9f2f393c 3362 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 553:063b9f2f393c 3363 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 553:063b9f2f393c 3364 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 553:063b9f2f393c 3365 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 553:063b9f2f393c 3366 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 553:063b9f2f393c 3367 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 553:063b9f2f393c 3368 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 553:063b9f2f393c 3369 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 553:063b9f2f393c 3370
mbed_official 553:063b9f2f393c 3371 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 553:063b9f2f393c 3372 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 553:063b9f2f393c 3373 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 553:063b9f2f393c 3374 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 553:063b9f2f393c 3375 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 553:063b9f2f393c 3376 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 553:063b9f2f393c 3377 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 553:063b9f2f393c 3378 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 553:063b9f2f393c 3379 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 553:063b9f2f393c 3380 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 553:063b9f2f393c 3381 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 553:063b9f2f393c 3382 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 553:063b9f2f393c 3383 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 553:063b9f2f393c 3384 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 553:063b9f2f393c 3385 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 553:063b9f2f393c 3386 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 553:063b9f2f393c 3387 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 553:063b9f2f393c 3388 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 553:063b9f2f393c 3389 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 553:063b9f2f393c 3390 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 553:063b9f2f393c 3391 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 553:063b9f2f393c 3392 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 553:063b9f2f393c 3393 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 553:063b9f2f393c 3394 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 553:063b9f2f393c 3395
mbed_official 553:063b9f2f393c 3396 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 553:063b9f2f393c 3397 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 553:063b9f2f393c 3398 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 553:063b9f2f393c 3399 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 553:063b9f2f393c 3400 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 553:063b9f2f393c 3401 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 553:063b9f2f393c 3402 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 553:063b9f2f393c 3403 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 553:063b9f2f393c 3404 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 553:063b9f2f393c 3405 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 553:063b9f2f393c 3406 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 553:063b9f2f393c 3407 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 553:063b9f2f393c 3408 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 553:063b9f2f393c 3409 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 553:063b9f2f393c 3410 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 553:063b9f2f393c 3411 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 553:063b9f2f393c 3412 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 553:063b9f2f393c 3413 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 553:063b9f2f393c 3414 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 553:063b9f2f393c 3415 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 553:063b9f2f393c 3416 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 553:063b9f2f393c 3417 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 553:063b9f2f393c 3418 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 553:063b9f2f393c 3419 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 553:063b9f2f393c 3420
mbed_official 553:063b9f2f393c 3421 /******************************************************************************/
mbed_official 553:063b9f2f393c 3422 /* */
mbed_official 553:063b9f2f393c 3423 /* FLASH */
mbed_official 553:063b9f2f393c 3424 /* */
mbed_official 553:063b9f2f393c 3425 /******************************************************************************/
mbed_official 553:063b9f2f393c 3426 /******************* Bits definition for FLASH_ACR register *****************/
mbed_official 553:063b9f2f393c 3427 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 3428 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
mbed_official 553:063b9f2f393c 3429 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3430 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3431 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
mbed_official 553:063b9f2f393c 3432 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3433 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
mbed_official 553:063b9f2f393c 3434 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
mbed_official 553:063b9f2f393c 3435 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
mbed_official 553:063b9f2f393c 3436 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3437 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
mbed_official 553:063b9f2f393c 3438 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
mbed_official 553:063b9f2f393c 3439 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
mbed_official 553:063b9f2f393c 3440 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
mbed_official 553:063b9f2f393c 3441 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
mbed_official 553:063b9f2f393c 3442 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
mbed_official 553:063b9f2f393c 3443 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 3444 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3445 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3446 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3447 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3448 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 3449 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
mbed_official 553:063b9f2f393c 3450 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
mbed_official 553:063b9f2f393c 3451
mbed_official 553:063b9f2f393c 3452 /******************* Bits definition for FLASH_SR register ******************/
mbed_official 553:063b9f2f393c 3453 #define FLASH_SR_EOP ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3454 #define FLASH_SR_SOP ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3455 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3456 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3457 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3458 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 3459 #define FLASH_SR_BSY ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3460
mbed_official 553:063b9f2f393c 3461 /******************* Bits definition for FLASH_CR register ******************/
mbed_official 553:063b9f2f393c 3462 #define FLASH_CR_PG ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3463 #define FLASH_CR_SER ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3464 #define FLASH_CR_MER ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3465 #define FLASH_CR_MER1 FLASH_CR_MER
mbed_official 553:063b9f2f393c 3466 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
mbed_official 553:063b9f2f393c 3467 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3468 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3469 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3470 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3471 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 3472 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
mbed_official 553:063b9f2f393c 3473 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3474 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3475 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 3476 #define FLASH_CR_STRT ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3477 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3478 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 3479
mbed_official 553:063b9f2f393c 3480 /******************* Bits definition for FLASH_OPTCR register ***************/
mbed_official 553:063b9f2f393c 3481 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 3482 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 3483 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 3484 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 3485 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
mbed_official 553:063b9f2f393c 3486 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 3487 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 3488 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 3489 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 3490 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
mbed_official 553:063b9f2f393c 3491 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 3492 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 3493 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 3494 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 3495 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 3496 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 3497 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 3498 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 3499 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
mbed_official 553:063b9f2f393c 3500 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3501 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 3502 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3503 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3504 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3505 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 3506 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 3507 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 3508 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3509 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 3510 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 3511 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 3512 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 3513 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 3514
mbed_official 553:063b9f2f393c 3515 /****************** Bits definition for FLASH_OPTCR1 register ***************/
mbed_official 553:063b9f2f393c 3516 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
mbed_official 553:063b9f2f393c 3517 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 3518 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 3519 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 3520 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 3521 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 3522 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 3523 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 3524 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 3525 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 3526 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 3527 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 3528 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 3529
mbed_official 553:063b9f2f393c 3530 /******************************************************************************/
mbed_official 553:063b9f2f393c 3531 /* */
mbed_official 553:063b9f2f393c 3532 /* Flexible Memory Controller */
mbed_official 553:063b9f2f393c 3533 /* */
mbed_official 553:063b9f2f393c 3534 /******************************************************************************/
mbed_official 553:063b9f2f393c 3535 /****************** Bit definition for FMC_BCR1 register *******************/
mbed_official 553:063b9f2f393c 3536 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 553:063b9f2f393c 3537 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 553:063b9f2f393c 3538
mbed_official 553:063b9f2f393c 3539 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 553:063b9f2f393c 3540 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3541 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3542
mbed_official 553:063b9f2f393c 3543 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 553:063b9f2f393c 3544 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3545 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3546
mbed_official 553:063b9f2f393c 3547 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 553:063b9f2f393c 3548 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 553:063b9f2f393c 3549 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 553:063b9f2f393c 3550 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 553:063b9f2f393c 3551 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 553:063b9f2f393c 3552 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 553:063b9f2f393c 3553 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 553:063b9f2f393c 3554 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 553:063b9f2f393c 3555 #define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
mbed_official 553:063b9f2f393c 3556 #define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3557 #define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3558 #define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3559 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 553:063b9f2f393c 3560 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
mbed_official 553:063b9f2f393c 3561 #define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
mbed_official 553:063b9f2f393c 3562
mbed_official 553:063b9f2f393c 3563 /****************** Bit definition for FMC_BCR2 register *******************/
mbed_official 553:063b9f2f393c 3564 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 553:063b9f2f393c 3565 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 553:063b9f2f393c 3566
mbed_official 553:063b9f2f393c 3567 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 553:063b9f2f393c 3568 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3569 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3570
mbed_official 553:063b9f2f393c 3571 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 553:063b9f2f393c 3572 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3573 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3574
mbed_official 553:063b9f2f393c 3575 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 553:063b9f2f393c 3576 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 553:063b9f2f393c 3577 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 553:063b9f2f393c 3578 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 553:063b9f2f393c 3579 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 553:063b9f2f393c 3580 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 553:063b9f2f393c 3581 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 553:063b9f2f393c 3582 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 553:063b9f2f393c 3583 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 553:063b9f2f393c 3584
mbed_official 553:063b9f2f393c 3585 /****************** Bit definition for FMC_BCR3 register *******************/
mbed_official 553:063b9f2f393c 3586 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 553:063b9f2f393c 3587 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 553:063b9f2f393c 3588
mbed_official 553:063b9f2f393c 3589 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 553:063b9f2f393c 3590 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3591 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3592
mbed_official 553:063b9f2f393c 3593 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 553:063b9f2f393c 3594 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3595 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3596
mbed_official 553:063b9f2f393c 3597 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 553:063b9f2f393c 3598 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 553:063b9f2f393c 3599 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 553:063b9f2f393c 3600 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 553:063b9f2f393c 3601 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 553:063b9f2f393c 3602 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 553:063b9f2f393c 3603 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 553:063b9f2f393c 3604 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 553:063b9f2f393c 3605 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 553:063b9f2f393c 3606
mbed_official 553:063b9f2f393c 3607 /****************** Bit definition for FMC_BCR4 register *******************/
mbed_official 553:063b9f2f393c 3608 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 553:063b9f2f393c 3609 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 553:063b9f2f393c 3610
mbed_official 553:063b9f2f393c 3611 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 553:063b9f2f393c 3612 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3613 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3614
mbed_official 553:063b9f2f393c 3615 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 553:063b9f2f393c 3616 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3617 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3618
mbed_official 553:063b9f2f393c 3619 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 553:063b9f2f393c 3620 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 553:063b9f2f393c 3621 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 553:063b9f2f393c 3622 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 553:063b9f2f393c 3623 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 553:063b9f2f393c 3624 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 553:063b9f2f393c 3625 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 553:063b9f2f393c 3626 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 553:063b9f2f393c 3627 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 553:063b9f2f393c 3628
mbed_official 553:063b9f2f393c 3629 /****************** Bit definition for FMC_BTR1 register ******************/
mbed_official 553:063b9f2f393c 3630 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3631 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3632 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3633 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3634 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3635
mbed_official 553:063b9f2f393c 3636 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3637 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3638 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3639 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3640 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3641
mbed_official 553:063b9f2f393c 3642 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3643 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3644 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3645 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3646 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3647 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3648 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3649 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3650 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3651
mbed_official 553:063b9f2f393c 3652 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 553:063b9f2f393c 3653 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3654 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3655 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3656 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3657
mbed_official 553:063b9f2f393c 3658 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 553:063b9f2f393c 3659 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3660 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3661 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3662 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3663
mbed_official 553:063b9f2f393c 3664 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 553:063b9f2f393c 3665 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3666 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3667 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3668 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3669
mbed_official 553:063b9f2f393c 3670 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3671 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3672 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3673
mbed_official 553:063b9f2f393c 3674 /****************** Bit definition for FMC_BTR2 register *******************/
mbed_official 553:063b9f2f393c 3675 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3676 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3677 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3678 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3679 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3680
mbed_official 553:063b9f2f393c 3681 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3682 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3683 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3684 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3685 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3686
mbed_official 553:063b9f2f393c 3687 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3688 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3689 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3690 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3691 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3692 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3693 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3694 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3695 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3696
mbed_official 553:063b9f2f393c 3697 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 553:063b9f2f393c 3698 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3699 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3700 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3701 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3702
mbed_official 553:063b9f2f393c 3703 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 553:063b9f2f393c 3704 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3705 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3706 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3707 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3708
mbed_official 553:063b9f2f393c 3709 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 553:063b9f2f393c 3710 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3711 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3712 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3713 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3714
mbed_official 553:063b9f2f393c 3715 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3716 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3717 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3718
mbed_official 553:063b9f2f393c 3719 /******************* Bit definition for FMC_BTR3 register *******************/
mbed_official 553:063b9f2f393c 3720 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3721 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3722 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3723 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3724 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3725
mbed_official 553:063b9f2f393c 3726 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3727 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3728 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3729 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3730 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3731
mbed_official 553:063b9f2f393c 3732 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3733 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3734 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3735 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3736 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3737 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3738 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3739 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3740 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3741
mbed_official 553:063b9f2f393c 3742 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 553:063b9f2f393c 3743 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3744 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3745 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3746 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3747
mbed_official 553:063b9f2f393c 3748 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 553:063b9f2f393c 3749 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3750 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3751 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3752 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3753
mbed_official 553:063b9f2f393c 3754 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 553:063b9f2f393c 3755 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3756 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3757 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3758 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3759
mbed_official 553:063b9f2f393c 3760 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3761 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3762 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3763
mbed_official 553:063b9f2f393c 3764 /****************** Bit definition for FMC_BTR4 register *******************/
mbed_official 553:063b9f2f393c 3765 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3766 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3767 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3768 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3769 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3770
mbed_official 553:063b9f2f393c 3771 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3772 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3773 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3774 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3775 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3776
mbed_official 553:063b9f2f393c 3777 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3778 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3779 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3780 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3781 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3782 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3783 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3784 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3785 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3786
mbed_official 553:063b9f2f393c 3787 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 553:063b9f2f393c 3788 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3789 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3790 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3791 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3792
mbed_official 553:063b9f2f393c 3793 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 553:063b9f2f393c 3794 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3795 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3796 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3797 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3798
mbed_official 553:063b9f2f393c 3799 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 553:063b9f2f393c 3800 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3801 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3802 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3803 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3804
mbed_official 553:063b9f2f393c 3805 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3806 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3807 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3808
mbed_official 553:063b9f2f393c 3809 /****************** Bit definition for FMC_BWTR1 register ******************/
mbed_official 553:063b9f2f393c 3810 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3811 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3812 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3813 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3814 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3815
mbed_official 553:063b9f2f393c 3816 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3817 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3818 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3819 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3820 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3821
mbed_official 553:063b9f2f393c 3822 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3823 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3824 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3825 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3826 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3827 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3828 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3829 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3830 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3831
mbed_official 553:063b9f2f393c 3832 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 553:063b9f2f393c 3833 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3834 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3835 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3836 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3837
mbed_official 553:063b9f2f393c 3838 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3839 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3840 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3841
mbed_official 553:063b9f2f393c 3842 /****************** Bit definition for FMC_BWTR2 register ******************/
mbed_official 553:063b9f2f393c 3843 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3844 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3845 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3846 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3847 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3848
mbed_official 553:063b9f2f393c 3849 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3850 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3851 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3852 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3853 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3854
mbed_official 553:063b9f2f393c 3855 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3856 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3857 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3858 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3859 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3860 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3861 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3862 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3863 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3864
mbed_official 553:063b9f2f393c 3865 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 553:063b9f2f393c 3866 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3867 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3868 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3869 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3870
mbed_official 553:063b9f2f393c 3871 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3872 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3873 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3874
mbed_official 553:063b9f2f393c 3875 /****************** Bit definition for FMC_BWTR3 register ******************/
mbed_official 553:063b9f2f393c 3876 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3877 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3878 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3879 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3880 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3881
mbed_official 553:063b9f2f393c 3882 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3883 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3884 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3885 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3886 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3887
mbed_official 553:063b9f2f393c 3888 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3889 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3890 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3891 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3892 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3893 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3894 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3895 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3896 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3897
mbed_official 553:063b9f2f393c 3898 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 553:063b9f2f393c 3899 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3900 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3901 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3902 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3903
mbed_official 553:063b9f2f393c 3904 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3905 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3906 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3907
mbed_official 553:063b9f2f393c 3908 /****************** Bit definition for FMC_BWTR4 register ******************/
mbed_official 553:063b9f2f393c 3909 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 553:063b9f2f393c 3910 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3911 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3912 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3913 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3914
mbed_official 553:063b9f2f393c 3915 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 553:063b9f2f393c 3916 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3917 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3918 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3919 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3920
mbed_official 553:063b9f2f393c 3921 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 553:063b9f2f393c 3922 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3923 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3924 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3925 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3926 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3927 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3928 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3929 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3930
mbed_official 553:063b9f2f393c 3931 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
mbed_official 553:063b9f2f393c 3932 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3933 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3934 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3935 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3936
mbed_official 553:063b9f2f393c 3937 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 553:063b9f2f393c 3938 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3939 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3940
mbed_official 553:063b9f2f393c 3941 /****************** Bit definition for FMC_PCR register *******************/
mbed_official 553:063b9f2f393c 3942 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 553:063b9f2f393c 3943 #define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 553:063b9f2f393c 3944 #define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 553:063b9f2f393c 3945
mbed_official 553:063b9f2f393c 3946 #define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 553:063b9f2f393c 3947 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3948 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3949
mbed_official 553:063b9f2f393c 3950 #define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 553:063b9f2f393c 3951
mbed_official 553:063b9f2f393c 3952 #define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 553:063b9f2f393c 3953 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3954 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3955 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3956 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3957
mbed_official 553:063b9f2f393c 3958 #define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 553:063b9f2f393c 3959 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3960 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3961 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3962 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3963
mbed_official 553:063b9f2f393c 3964 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
mbed_official 553:063b9f2f393c 3965 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3966 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3967 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3968
mbed_official 553:063b9f2f393c 3969 /******************* Bit definition for FMC_SR register *******************/
mbed_official 553:063b9f2f393c 3970 #define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 553:063b9f2f393c 3971 #define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 553:063b9f2f393c 3972 #define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 553:063b9f2f393c 3973 #define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 553:063b9f2f393c 3974 #define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 553:063b9f2f393c 3975 #define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 553:063b9f2f393c 3976 #define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 553:063b9f2f393c 3977
mbed_official 553:063b9f2f393c 3978 /****************** Bit definition for FMC_PMEM register ******************/
mbed_official 553:063b9f2f393c 3979 #define FMC_PMEM_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
mbed_official 553:063b9f2f393c 3980 #define FMC_PMEM_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3981 #define FMC_PMEM_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3982 #define FMC_PMEM_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3983 #define FMC_PMEM_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3984 #define FMC_PMEM_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3985 #define FMC_PMEM_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3986 #define FMC_PMEM_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3987 #define FMC_PMEM_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3988
mbed_official 553:063b9f2f393c 3989 #define FMC_PMEM_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
mbed_official 553:063b9f2f393c 3990 #define FMC_PMEM_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 3991 #define FMC_PMEM_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 3992 #define FMC_PMEM_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 3993 #define FMC_PMEM_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 3994 #define FMC_PMEM_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 3995 #define FMC_PMEM_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 3996 #define FMC_PMEM_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 3997 #define FMC_PMEM_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 3998
mbed_official 553:063b9f2f393c 3999 #define FMC_PMEM_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
mbed_official 553:063b9f2f393c 4000 #define FMC_PMEM_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4001 #define FMC_PMEM_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4002 #define FMC_PMEM_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4003 #define FMC_PMEM_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4004 #define FMC_PMEM_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4005 #define FMC_PMEM_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4006 #define FMC_PMEM_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 4007 #define FMC_PMEM_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 4008
mbed_official 553:063b9f2f393c 4009 #define FMC_PMEM_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
mbed_official 553:063b9f2f393c 4010 #define FMC_PMEM_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4011 #define FMC_PMEM_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4012 #define FMC_PMEM_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4013 #define FMC_PMEM_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4014 #define FMC_PMEM_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4015 #define FMC_PMEM_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4016 #define FMC_PMEM_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 4017 #define FMC_PMEM_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 4018
mbed_official 553:063b9f2f393c 4019 /****************** Bit definition for FMC_PATT register ******************/
mbed_official 553:063b9f2f393c 4020 #define FMC_PATT_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
mbed_official 553:063b9f2f393c 4021 #define FMC_PATT_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4022 #define FMC_PATT_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4023 #define FMC_PATT_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4024 #define FMC_PATT_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4025 #define FMC_PATT_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4026 #define FMC_PATT_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4027 #define FMC_PATT_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 4028 #define FMC_PATT_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 4029
mbed_official 553:063b9f2f393c 4030 #define FMC_PATT_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
mbed_official 553:063b9f2f393c 4031 #define FMC_PATT_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4032 #define FMC_PATT_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4033 #define FMC_PATT_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4034 #define FMC_PATT_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4035 #define FMC_PATT_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4036 #define FMC_PATT_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4037 #define FMC_PATT_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 4038 #define FMC_PATT_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 4039
mbed_official 553:063b9f2f393c 4040 #define FMC_PATT_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
mbed_official 553:063b9f2f393c 4041 #define FMC_PATT_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4042 #define FMC_PATT_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4043 #define FMC_PATT_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4044 #define FMC_PATT_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4045 #define FMC_PATT_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4046 #define FMC_PATT_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4047 #define FMC_PATT_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 4048 #define FMC_PATT_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 4049
mbed_official 553:063b9f2f393c 4050 #define FMC_PATT_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
mbed_official 553:063b9f2f393c 4051 #define FMC_PATT_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4052 #define FMC_PATT_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4053 #define FMC_PATT_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4054 #define FMC_PATT_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4055 #define FMC_PATT_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4056 #define FMC_PATT_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4057 #define FMC_PATT_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 4058 #define FMC_PATT_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 4059
mbed_official 553:063b9f2f393c 4060 /****************** Bit definition for FMC_ECCR register ******************/
mbed_official 553:063b9f2f393c 4061 #define FMC_ECCR_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 553:063b9f2f393c 4062
mbed_official 553:063b9f2f393c 4063 /****************** Bit definition for FMC_SDCR1 register ******************/
mbed_official 553:063b9f2f393c 4064 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 553:063b9f2f393c 4065 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4066 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4067
mbed_official 553:063b9f2f393c 4068 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 553:063b9f2f393c 4069 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4070 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4071
mbed_official 553:063b9f2f393c 4072 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 553:063b9f2f393c 4073 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4074 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4075
mbed_official 553:063b9f2f393c 4076 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 553:063b9f2f393c 4077
mbed_official 553:063b9f2f393c 4078 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 553:063b9f2f393c 4079 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4080 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4081
mbed_official 553:063b9f2f393c 4082 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 553:063b9f2f393c 4083
mbed_official 553:063b9f2f393c 4084 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
mbed_official 553:063b9f2f393c 4085 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4086 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4087
mbed_official 553:063b9f2f393c 4088 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 553:063b9f2f393c 4089
mbed_official 553:063b9f2f393c 4090 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
mbed_official 553:063b9f2f393c 4091 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4092 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4093
mbed_official 553:063b9f2f393c 4094 /****************** Bit definition for FMC_SDCR2 register ******************/
mbed_official 553:063b9f2f393c 4095 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 553:063b9f2f393c 4096 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4097 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4098
mbed_official 553:063b9f2f393c 4099 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 553:063b9f2f393c 4100 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4101 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4102
mbed_official 553:063b9f2f393c 4103 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 553:063b9f2f393c 4104 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4105 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4106
mbed_official 553:063b9f2f393c 4107 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 553:063b9f2f393c 4108
mbed_official 553:063b9f2f393c 4109 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 553:063b9f2f393c 4110 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4111 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4112
mbed_official 553:063b9f2f393c 4113 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 553:063b9f2f393c 4114
mbed_official 553:063b9f2f393c 4115 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
mbed_official 553:063b9f2f393c 4116 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4117 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4118
mbed_official 553:063b9f2f393c 4119 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 553:063b9f2f393c 4120
mbed_official 553:063b9f2f393c 4121 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
mbed_official 553:063b9f2f393c 4122 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4123 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4124
mbed_official 553:063b9f2f393c 4125 /****************** Bit definition for FMC_SDTR1 register ******************/
mbed_official 553:063b9f2f393c 4126 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 553:063b9f2f393c 4127 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4128 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4129 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4130 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4131
mbed_official 553:063b9f2f393c 4132 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 553:063b9f2f393c 4133 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4134 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4135 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4136 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4137
mbed_official 553:063b9f2f393c 4138 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 553:063b9f2f393c 4139 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4140 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4141 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4142 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4143
mbed_official 553:063b9f2f393c 4144 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 553:063b9f2f393c 4145 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4146 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4147 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4148
mbed_official 553:063b9f2f393c 4149 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 553:063b9f2f393c 4150 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4151 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4152 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4153
mbed_official 553:063b9f2f393c 4154 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 553:063b9f2f393c 4155 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4156 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4157 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4158
mbed_official 553:063b9f2f393c 4159 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 553:063b9f2f393c 4160 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4161 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4162 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4163
mbed_official 553:063b9f2f393c 4164 /****************** Bit definition for FMC_SDTR2 register ******************/
mbed_official 553:063b9f2f393c 4165 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 553:063b9f2f393c 4166 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4167 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4168 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4169 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4170
mbed_official 553:063b9f2f393c 4171 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 553:063b9f2f393c 4172 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4173 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4174 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4175 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4176
mbed_official 553:063b9f2f393c 4177 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 553:063b9f2f393c 4178 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4179 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4180 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4181 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4182
mbed_official 553:063b9f2f393c 4183 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 553:063b9f2f393c 4184 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4185 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4186 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4187
mbed_official 553:063b9f2f393c 4188 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 553:063b9f2f393c 4189 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4190 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4191 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4192
mbed_official 553:063b9f2f393c 4193 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 553:063b9f2f393c 4194 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4195 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4196 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4197
mbed_official 553:063b9f2f393c 4198 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 553:063b9f2f393c 4199 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4200 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4201 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4202
mbed_official 553:063b9f2f393c 4203 /****************** Bit definition for FMC_SDCMR register ******************/
mbed_official 553:063b9f2f393c 4204 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
mbed_official 553:063b9f2f393c 4205 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4206 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4207 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4208
mbed_official 553:063b9f2f393c 4209 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
mbed_official 553:063b9f2f393c 4210
mbed_official 553:063b9f2f393c 4211 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
mbed_official 553:063b9f2f393c 4212
mbed_official 553:063b9f2f393c 4213 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
mbed_official 553:063b9f2f393c 4214 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4215 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4216 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4217 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4218
mbed_official 553:063b9f2f393c 4219 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
mbed_official 553:063b9f2f393c 4220
mbed_official 553:063b9f2f393c 4221 /****************** Bit definition for FMC_SDRTR register ******************/
mbed_official 553:063b9f2f393c 4222 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
mbed_official 553:063b9f2f393c 4223
mbed_official 553:063b9f2f393c 4224 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
mbed_official 553:063b9f2f393c 4225
mbed_official 553:063b9f2f393c 4226 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
mbed_official 553:063b9f2f393c 4227
mbed_official 553:063b9f2f393c 4228 /****************** Bit definition for FMC_SDSR register ******************/
mbed_official 553:063b9f2f393c 4229 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
mbed_official 553:063b9f2f393c 4230
mbed_official 553:063b9f2f393c 4231 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
mbed_official 553:063b9f2f393c 4232 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4233 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4234
mbed_official 553:063b9f2f393c 4235 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
mbed_official 553:063b9f2f393c 4236 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4237 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4238 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
mbed_official 553:063b9f2f393c 4239
mbed_official 553:063b9f2f393c 4240 /******************************************************************************/
mbed_official 553:063b9f2f393c 4241 /* */
mbed_official 553:063b9f2f393c 4242 /* General Purpose I/O */
mbed_official 553:063b9f2f393c 4243 /* */
mbed_official 553:063b9f2f393c 4244 /******************************************************************************/
mbed_official 553:063b9f2f393c 4245 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 553:063b9f2f393c 4246 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 553:063b9f2f393c 4247 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4248 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4249
mbed_official 553:063b9f2f393c 4250 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 553:063b9f2f393c 4251 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4252 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4253
mbed_official 553:063b9f2f393c 4254 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 553:063b9f2f393c 4255 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4256 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4257
mbed_official 553:063b9f2f393c 4258 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 553:063b9f2f393c 4259 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4260 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4261
mbed_official 553:063b9f2f393c 4262 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 553:063b9f2f393c 4263 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4264 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4265
mbed_official 553:063b9f2f393c 4266 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 553:063b9f2f393c 4267 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4268 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4269
mbed_official 553:063b9f2f393c 4270 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 553:063b9f2f393c 4271 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4272 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4273
mbed_official 553:063b9f2f393c 4274 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 553:063b9f2f393c 4275 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4276 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4277
mbed_official 553:063b9f2f393c 4278 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 553:063b9f2f393c 4279 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 4280 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 4281
mbed_official 553:063b9f2f393c 4282 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 553:063b9f2f393c 4283 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 4284 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 4285
mbed_official 553:063b9f2f393c 4286 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 4287 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 4288 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 4289
mbed_official 553:063b9f2f393c 4290 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 553:063b9f2f393c 4291 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 4292 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 4293
mbed_official 553:063b9f2f393c 4294 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 553:063b9f2f393c 4295 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 4296 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 4297
mbed_official 553:063b9f2f393c 4298 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 553:063b9f2f393c 4299 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 4300 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 4301
mbed_official 553:063b9f2f393c 4302 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 553:063b9f2f393c 4303 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 4304 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 4305
mbed_official 553:063b9f2f393c 4306 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 553:063b9f2f393c 4307 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 4308 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 4309
mbed_official 553:063b9f2f393c 4310 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 553:063b9f2f393c 4311 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4312 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4313 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4314 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4315 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4316 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4317 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4318 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4319 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4320 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4321 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4322 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4323 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4324 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4325 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4326 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4327
mbed_official 553:063b9f2f393c 4328 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 553:063b9f2f393c 4329 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 553:063b9f2f393c 4330 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4331 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4332
mbed_official 553:063b9f2f393c 4333 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 553:063b9f2f393c 4334 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4335 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4336
mbed_official 553:063b9f2f393c 4337 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 553:063b9f2f393c 4338 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4339 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4340
mbed_official 553:063b9f2f393c 4341 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 553:063b9f2f393c 4342 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4343 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4344
mbed_official 553:063b9f2f393c 4345 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 553:063b9f2f393c 4346 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4347 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4348
mbed_official 553:063b9f2f393c 4349 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 553:063b9f2f393c 4350 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4351 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4352
mbed_official 553:063b9f2f393c 4353 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 553:063b9f2f393c 4354 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4355 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4356
mbed_official 553:063b9f2f393c 4357 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 553:063b9f2f393c 4358 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4359 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4360
mbed_official 553:063b9f2f393c 4361 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 553:063b9f2f393c 4362 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 4363 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 4364
mbed_official 553:063b9f2f393c 4365 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 553:063b9f2f393c 4366 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 4367 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 4368
mbed_official 553:063b9f2f393c 4369 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 4370 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 4371 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 4372
mbed_official 553:063b9f2f393c 4373 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 553:063b9f2f393c 4374 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 4375 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 4376
mbed_official 553:063b9f2f393c 4377 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 553:063b9f2f393c 4378 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 4379 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 4380
mbed_official 553:063b9f2f393c 4381 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 553:063b9f2f393c 4382 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 4383 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 4384
mbed_official 553:063b9f2f393c 4385 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 553:063b9f2f393c 4386 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 4387 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 4388
mbed_official 553:063b9f2f393c 4389 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 553:063b9f2f393c 4390 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 4391 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 4392
mbed_official 553:063b9f2f393c 4393 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 553:063b9f2f393c 4394 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 553:063b9f2f393c 4395 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4396 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4397
mbed_official 553:063b9f2f393c 4398 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 553:063b9f2f393c 4399 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4400 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4401
mbed_official 553:063b9f2f393c 4402 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 553:063b9f2f393c 4403 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4404 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4405
mbed_official 553:063b9f2f393c 4406 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 553:063b9f2f393c 4407 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4408 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4409
mbed_official 553:063b9f2f393c 4410 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 553:063b9f2f393c 4411 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4412 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4413
mbed_official 553:063b9f2f393c 4414 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 553:063b9f2f393c 4415 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4416 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4417
mbed_official 553:063b9f2f393c 4418 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 553:063b9f2f393c 4419 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4420 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4421
mbed_official 553:063b9f2f393c 4422 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 553:063b9f2f393c 4423 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4424 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4425
mbed_official 553:063b9f2f393c 4426 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 553:063b9f2f393c 4427 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 4428 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 4429
mbed_official 553:063b9f2f393c 4430 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 553:063b9f2f393c 4431 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 4432 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 4433
mbed_official 553:063b9f2f393c 4434 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 4435 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 4436 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 4437
mbed_official 553:063b9f2f393c 4438 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 553:063b9f2f393c 4439 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 4440 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 4441
mbed_official 553:063b9f2f393c 4442 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 553:063b9f2f393c 4443 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 4444 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 4445
mbed_official 553:063b9f2f393c 4446 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 553:063b9f2f393c 4447 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 4448 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 4449
mbed_official 553:063b9f2f393c 4450 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 553:063b9f2f393c 4451 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 4452 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 4453
mbed_official 553:063b9f2f393c 4454 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 553:063b9f2f393c 4455 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 4456 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 4457
mbed_official 553:063b9f2f393c 4458 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 553:063b9f2f393c 4459 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4460 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4461 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4462 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4463 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4464 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4465 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4466 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4467 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4468 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4469 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4470 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4471 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4472 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4473 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4474 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4475 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
mbed_official 553:063b9f2f393c 4476 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
mbed_official 553:063b9f2f393c 4477 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
mbed_official 553:063b9f2f393c 4478 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
mbed_official 553:063b9f2f393c 4479 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
mbed_official 553:063b9f2f393c 4480 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
mbed_official 553:063b9f2f393c 4481 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
mbed_official 553:063b9f2f393c 4482 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
mbed_official 553:063b9f2f393c 4483 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
mbed_official 553:063b9f2f393c 4484 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
mbed_official 553:063b9f2f393c 4485 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
mbed_official 553:063b9f2f393c 4486 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
mbed_official 553:063b9f2f393c 4487 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
mbed_official 553:063b9f2f393c 4488 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
mbed_official 553:063b9f2f393c 4489 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
mbed_official 553:063b9f2f393c 4490 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
mbed_official 553:063b9f2f393c 4491 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
mbed_official 553:063b9f2f393c 4492
mbed_official 553:063b9f2f393c 4493 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 553:063b9f2f393c 4494 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4495 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4496 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4497 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4498 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4499 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4500 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4501 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4502 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4503 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4504 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4505 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4506 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4507 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4508 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4509 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4510 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
mbed_official 553:063b9f2f393c 4511 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
mbed_official 553:063b9f2f393c 4512 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
mbed_official 553:063b9f2f393c 4513 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
mbed_official 553:063b9f2f393c 4514 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
mbed_official 553:063b9f2f393c 4515 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
mbed_official 553:063b9f2f393c 4516 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
mbed_official 553:063b9f2f393c 4517 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
mbed_official 553:063b9f2f393c 4518 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
mbed_official 553:063b9f2f393c 4519 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
mbed_official 553:063b9f2f393c 4520 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
mbed_official 553:063b9f2f393c 4521 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
mbed_official 553:063b9f2f393c 4522 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
mbed_official 553:063b9f2f393c 4523 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
mbed_official 553:063b9f2f393c 4524 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
mbed_official 553:063b9f2f393c 4525 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
mbed_official 553:063b9f2f393c 4526 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
mbed_official 553:063b9f2f393c 4527
mbed_official 553:063b9f2f393c 4528 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 553:063b9f2f393c 4529 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4530 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4531 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4532 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4533 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4534 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4535 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4536 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4537 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4538 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4539 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4540 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4541 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4542 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4543 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4544 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4545 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 4546 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 4547 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 4548 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 4549 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 4550 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 4551 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 4552 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 4553 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 4554 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 4555 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 4556 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 4557 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 4558 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 4559 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 4560 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 4561
mbed_official 553:063b9f2f393c 4562 /****************** Bit definition for GPIO_LCKR register *********************/
mbed_official 553:063b9f2f393c 4563 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 4564 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 4565 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 4566 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 4567 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 4568 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 4569 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 4570 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 4571 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 4572 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 4573 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 4574 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 4575 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 4576 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 4577 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 4578 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 4579 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 4580
mbed_official 553:063b9f2f393c 4581 /******************************************************************************/
mbed_official 553:063b9f2f393c 4582 /* */
mbed_official 553:063b9f2f393c 4583 /* Inter-integrated Circuit Interface */
mbed_official 553:063b9f2f393c 4584 /* */
mbed_official 553:063b9f2f393c 4585 /******************************************************************************/
mbed_official 553:063b9f2f393c 4586 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 553:063b9f2f393c 4587 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
mbed_official 553:063b9f2f393c 4588 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
mbed_official 553:063b9f2f393c 4589 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
mbed_official 553:063b9f2f393c 4590 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
mbed_official 553:063b9f2f393c 4591 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
mbed_official 553:063b9f2f393c 4592 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
mbed_official 553:063b9f2f393c 4593 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
mbed_official 553:063b9f2f393c 4594 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
mbed_official 553:063b9f2f393c 4595 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
mbed_official 553:063b9f2f393c 4596 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
mbed_official 553:063b9f2f393c 4597 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
mbed_official 553:063b9f2f393c 4598 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
mbed_official 553:063b9f2f393c 4599 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
mbed_official 553:063b9f2f393c 4600 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
mbed_official 553:063b9f2f393c 4601
mbed_official 553:063b9f2f393c 4602 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 553:063b9f2f393c 4603 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 553:063b9f2f393c 4604 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4605 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4606 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4607 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4608 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4609 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4610
mbed_official 553:063b9f2f393c 4611 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
mbed_official 553:063b9f2f393c 4612 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
mbed_official 553:063b9f2f393c 4613 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
mbed_official 553:063b9f2f393c 4614 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
mbed_official 553:063b9f2f393c 4615 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
mbed_official 553:063b9f2f393c 4616
mbed_official 553:063b9f2f393c 4617 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 553:063b9f2f393c 4618 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
mbed_official 553:063b9f2f393c 4619 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
mbed_official 553:063b9f2f393c 4620
mbed_official 553:063b9f2f393c 4621 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4622 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4623 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4624 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 4625 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 4626 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 4627 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 4628 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 4629 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
mbed_official 553:063b9f2f393c 4630 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
mbed_official 553:063b9f2f393c 4631
mbed_official 553:063b9f2f393c 4632 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
mbed_official 553:063b9f2f393c 4633
mbed_official 553:063b9f2f393c 4634 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 553:063b9f2f393c 4635 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
mbed_official 553:063b9f2f393c 4636 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
mbed_official 553:063b9f2f393c 4637
mbed_official 553:063b9f2f393c 4638 /******************** Bit definition for I2C_DR register ********************/
mbed_official 553:063b9f2f393c 4639 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
mbed_official 553:063b9f2f393c 4640
mbed_official 553:063b9f2f393c 4641 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 553:063b9f2f393c 4642 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
mbed_official 553:063b9f2f393c 4643 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
mbed_official 553:063b9f2f393c 4644 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
mbed_official 553:063b9f2f393c 4645 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
mbed_official 553:063b9f2f393c 4646 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
mbed_official 553:063b9f2f393c 4647 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
mbed_official 553:063b9f2f393c 4648 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
mbed_official 553:063b9f2f393c 4649 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
mbed_official 553:063b9f2f393c 4650 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
mbed_official 553:063b9f2f393c 4651 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
mbed_official 553:063b9f2f393c 4652 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
mbed_official 553:063b9f2f393c 4653 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
mbed_official 553:063b9f2f393c 4654 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
mbed_official 553:063b9f2f393c 4655 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
mbed_official 553:063b9f2f393c 4656
mbed_official 553:063b9f2f393c 4657 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 553:063b9f2f393c 4658 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
mbed_official 553:063b9f2f393c 4659 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
mbed_official 553:063b9f2f393c 4660 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
mbed_official 553:063b9f2f393c 4661 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
mbed_official 553:063b9f2f393c 4662 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
mbed_official 553:063b9f2f393c 4663 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
mbed_official 553:063b9f2f393c 4664 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
mbed_official 553:063b9f2f393c 4665 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
mbed_official 553:063b9f2f393c 4666
mbed_official 553:063b9f2f393c 4667 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 553:063b9f2f393c 4668 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 553:063b9f2f393c 4669 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
mbed_official 553:063b9f2f393c 4670 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
mbed_official 553:063b9f2f393c 4671
mbed_official 553:063b9f2f393c 4672 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 553:063b9f2f393c 4673 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 553:063b9f2f393c 4674
mbed_official 553:063b9f2f393c 4675 /****************** Bit definition for I2C_FLTR register *******************/
mbed_official 553:063b9f2f393c 4676 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
mbed_official 553:063b9f2f393c 4677 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
mbed_official 553:063b9f2f393c 4678
mbed_official 553:063b9f2f393c 4679 /******************************************************************************/
mbed_official 553:063b9f2f393c 4680 /* */
mbed_official 553:063b9f2f393c 4681 /* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
mbed_official 553:063b9f2f393c 4682 /* */
mbed_official 553:063b9f2f393c 4683 /******************************************************************************/
mbed_official 553:063b9f2f393c 4684 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 553:063b9f2f393c 4685 #define FMPI2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 553:063b9f2f393c 4686 #define FMPI2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 553:063b9f2f393c 4687 #define FMPI2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 553:063b9f2f393c 4688 #define FMPI2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 553:063b9f2f393c 4689 #define FMPI2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 553:063b9f2f393c 4690 #define FMPI2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 553:063b9f2f393c 4691 #define FMPI2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 553:063b9f2f393c 4692 #define FMPI2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 553:063b9f2f393c 4693 #define FMPI2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 553:063b9f2f393c 4694 #define FMPI2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 553:063b9f2f393c 4695 #define FMPI2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 553:063b9f2f393c 4696 #define FMPI2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 553:063b9f2f393c 4697 #define FMPI2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 553:063b9f2f393c 4698 #define FMPI2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 553:063b9f2f393c 4699 #define FMPI2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 553:063b9f2f393c 4700 #define FMPI2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 553:063b9f2f393c 4701 #define FMPI2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 553:063b9f2f393c 4702 #define FMPI2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 553:063b9f2f393c 4703 #define FMPI2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 553:063b9f2f393c 4704 #define FMPI2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 553:063b9f2f393c 4705 #define FMPI2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 553:063b9f2f393c 4706
mbed_official 553:063b9f2f393c 4707 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 553:063b9f2f393c 4708 #define FMPI2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 553:063b9f2f393c 4709 #define FMPI2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 553:063b9f2f393c 4710 #define FMPI2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 553:063b9f2f393c 4711 #define FMPI2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 553:063b9f2f393c 4712 #define FMPI2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 553:063b9f2f393c 4713 #define FMPI2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 553:063b9f2f393c 4714 #define FMPI2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 553:063b9f2f393c 4715 #define FMPI2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 553:063b9f2f393c 4716 #define FMPI2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 553:063b9f2f393c 4717 #define FMPI2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 553:063b9f2f393c 4718 #define FMPI2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 553:063b9f2f393c 4719
mbed_official 553:063b9f2f393c 4720 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 553:063b9f2f393c 4721 #define FMPI2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 553:063b9f2f393c 4722 #define FMPI2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 553:063b9f2f393c 4723 #define FMPI2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 553:063b9f2f393c 4724
mbed_official 553:063b9f2f393c 4725 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 553:063b9f2f393c 4726 #define FMPI2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 553:063b9f2f393c 4727 #define FMPI2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 553:063b9f2f393c 4728 #define FMPI2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 553:063b9f2f393c 4729
mbed_official 553:063b9f2f393c 4730 /******************* Bit definition for I2C_TIMINGR register *******************/
mbed_official 553:063b9f2f393c 4731 #define FMPI2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 553:063b9f2f393c 4732 #define FMPI2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 553:063b9f2f393c 4733 #define FMPI2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 553:063b9f2f393c 4734 #define FMPI2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 553:063b9f2f393c 4735 #define FMPI2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 553:063b9f2f393c 4736
mbed_official 553:063b9f2f393c 4737 /******************* Bit definition for I2C_TIMEOUTR register *******************/
mbed_official 553:063b9f2f393c 4738 #define FMPI2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 553:063b9f2f393c 4739 #define FMPI2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 553:063b9f2f393c 4740 #define FMPI2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 553:063b9f2f393c 4741 #define FMPI2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
mbed_official 553:063b9f2f393c 4742 #define FMPI2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 553:063b9f2f393c 4743
mbed_official 553:063b9f2f393c 4744 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 553:063b9f2f393c 4745 #define FMPI2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 553:063b9f2f393c 4746 #define FMPI2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 553:063b9f2f393c 4747 #define FMPI2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 553:063b9f2f393c 4748 #define FMPI2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
mbed_official 553:063b9f2f393c 4749 #define FMPI2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 553:063b9f2f393c 4750 #define FMPI2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 553:063b9f2f393c 4751 #define FMPI2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 553:063b9f2f393c 4752 #define FMPI2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 553:063b9f2f393c 4753 #define FMPI2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 553:063b9f2f393c 4754 #define FMPI2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 553:063b9f2f393c 4755 #define FMPI2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 553:063b9f2f393c 4756 #define FMPI2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 553:063b9f2f393c 4757 #define FMPI2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 553:063b9f2f393c 4758 #define FMPI2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 553:063b9f2f393c 4759 #define FMPI2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 553:063b9f2f393c 4760 #define FMPI2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 553:063b9f2f393c 4761 #define FMPI2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 553:063b9f2f393c 4762
mbed_official 553:063b9f2f393c 4763 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 553:063b9f2f393c 4764 #define FMPI2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 553:063b9f2f393c 4765 #define FMPI2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 553:063b9f2f393c 4766 #define FMPI2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 553:063b9f2f393c 4767 #define FMPI2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 553:063b9f2f393c 4768 #define FMPI2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 553:063b9f2f393c 4769 #define FMPI2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 553:063b9f2f393c 4770 #define FMPI2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 553:063b9f2f393c 4771 #define FMPI2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 553:063b9f2f393c 4772 #define FMPI2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 553:063b9f2f393c 4773
mbed_official 553:063b9f2f393c 4774 /****************** Bit definition for I2C_PECR register *********************/
mbed_official 553:063b9f2f393c 4775 #define FMPI2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 553:063b9f2f393c 4776
mbed_official 553:063b9f2f393c 4777 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 553:063b9f2f393c 4778 #define FMPI2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 553:063b9f2f393c 4779
mbed_official 553:063b9f2f393c 4780 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 553:063b9f2f393c 4781 #define FMPI2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 553:063b9f2f393c 4782
mbed_official 553:063b9f2f393c 4783 /******************************************************************************/
mbed_official 553:063b9f2f393c 4784 /* */
mbed_official 553:063b9f2f393c 4785 /* Independent WATCHDOG */
mbed_official 553:063b9f2f393c 4786 /* */
mbed_official 553:063b9f2f393c 4787 /******************************************************************************/
mbed_official 553:063b9f2f393c 4788 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 553:063b9f2f393c 4789 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
mbed_official 553:063b9f2f393c 4790
mbed_official 553:063b9f2f393c 4791 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 553:063b9f2f393c 4792 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
mbed_official 553:063b9f2f393c 4793 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 4794 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 4795 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 4796
mbed_official 553:063b9f2f393c 4797 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 553:063b9f2f393c 4798 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
mbed_official 553:063b9f2f393c 4799
mbed_official 553:063b9f2f393c 4800 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 553:063b9f2f393c 4801 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
mbed_official 553:063b9f2f393c 4802 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
mbed_official 553:063b9f2f393c 4803
mbed_official 553:063b9f2f393c 4804
mbed_official 553:063b9f2f393c 4805 /******************************************************************************/
mbed_official 553:063b9f2f393c 4806 /* */
mbed_official 553:063b9f2f393c 4807 /* Power Control */
mbed_official 553:063b9f2f393c 4808 /* */
mbed_official 553:063b9f2f393c 4809 /******************************************************************************/
mbed_official 553:063b9f2f393c 4810 /******************** Bit definition for PWR_CR register ********************/
mbed_official 553:063b9f2f393c 4811 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 553:063b9f2f393c 4812 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 553:063b9f2f393c 4813 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 553:063b9f2f393c 4814 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 553:063b9f2f393c 4815 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 553:063b9f2f393c 4816
mbed_official 553:063b9f2f393c 4817 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 553:063b9f2f393c 4818 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4819 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4820 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4821
mbed_official 553:063b9f2f393c 4822 /*!< PVD level configuration */
mbed_official 553:063b9f2f393c 4823 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 553:063b9f2f393c 4824 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 553:063b9f2f393c 4825 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 553:063b9f2f393c 4826 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 553:063b9f2f393c 4827 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 553:063b9f2f393c 4828 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 553:063b9f2f393c 4829 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 553:063b9f2f393c 4830 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 553:063b9f2f393c 4831 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 553:063b9f2f393c 4832 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
mbed_official 553:063b9f2f393c 4833 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
mbed_official 553:063b9f2f393c 4834 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
mbed_official 553:063b9f2f393c 4835 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 553:063b9f2f393c 4836 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
mbed_official 553:063b9f2f393c 4837 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4838 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4839 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
mbed_official 553:063b9f2f393c 4840 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
mbed_official 553:063b9f2f393c 4841 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
mbed_official 553:063b9f2f393c 4842 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4843 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4844 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
mbed_official 553:063b9f2f393c 4845 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
mbed_official 553:063b9f2f393c 4846
mbed_official 553:063b9f2f393c 4847 /* Legacy define */
mbed_official 553:063b9f2f393c 4848 #define PWR_CR_PMODE PWR_CR_VOS
mbed_official 553:063b9f2f393c 4849 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
mbed_official 553:063b9f2f393c 4850 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
mbed_official 553:063b9f2f393c 4851
mbed_official 553:063b9f2f393c 4852 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 553:063b9f2f393c 4853 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 553:063b9f2f393c 4854 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 553:063b9f2f393c 4855 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 553:063b9f2f393c 4856 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
mbed_official 553:063b9f2f393c 4857 #define PWR_CSR_EWUP2 ((uint32_t)0x00000080) /*!< Enable WKUP pin 2 */
mbed_official 553:063b9f2f393c 4858 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 553:063b9f2f393c 4859 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
mbed_official 553:063b9f2f393c 4860 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
mbed_official 553:063b9f2f393c 4861 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
mbed_official 553:063b9f2f393c 4862 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
mbed_official 553:063b9f2f393c 4863 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
mbed_official 553:063b9f2f393c 4864
mbed_official 553:063b9f2f393c 4865 /* Legacy define */
mbed_official 553:063b9f2f393c 4866 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
mbed_official 553:063b9f2f393c 4867
mbed_official 553:063b9f2f393c 4868 /******************************************************************************/
mbed_official 553:063b9f2f393c 4869 /* */
mbed_official 553:063b9f2f393c 4870 /* QUADSPI */
mbed_official 553:063b9f2f393c 4871 /* */
mbed_official 553:063b9f2f393c 4872 /******************************************************************************/
mbed_official 553:063b9f2f393c 4873 /***************** Bit definition for QUADSPI_CR register *******************/
mbed_official 553:063b9f2f393c 4874 #define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
mbed_official 553:063b9f2f393c 4875 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
mbed_official 553:063b9f2f393c 4876 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
mbed_official 553:063b9f2f393c 4877 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
mbed_official 553:063b9f2f393c 4878 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< SSHIFT Sample Shift */
mbed_official 553:063b9f2f393c 4879 #define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
mbed_official 553:063b9f2f393c 4880 #define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
mbed_official 553:063b9f2f393c 4881 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
mbed_official 553:063b9f2f393c 4882 #define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4883 #define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4884 #define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4885 #define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 553:063b9f2f393c 4886 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
mbed_official 553:063b9f2f393c 4887 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
mbed_official 553:063b9f2f393c 4888 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
mbed_official 553:063b9f2f393c 4889 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
mbed_official 553:063b9f2f393c 4890 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
mbed_official 553:063b9f2f393c 4891 #define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4892 #define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
mbed_official 553:063b9f2f393c 4893 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
mbed_official 553:063b9f2f393c 4894 #define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4895 #define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4896 #define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4897 #define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 553:063b9f2f393c 4898 #define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
mbed_official 553:063b9f2f393c 4899 #define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
mbed_official 553:063b9f2f393c 4900 #define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
mbed_official 553:063b9f2f393c 4901 #define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
mbed_official 553:063b9f2f393c 4902
mbed_official 553:063b9f2f393c 4903 /***************** Bit definition for QUADSPI_DCR register ******************/
mbed_official 553:063b9f2f393c 4904 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
mbed_official 553:063b9f2f393c 4905 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
mbed_official 553:063b9f2f393c 4906 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4907 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4908 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4909 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
mbed_official 553:063b9f2f393c 4910 #define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4911 #define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4912 #define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4913 #define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 553:063b9f2f393c 4914 #define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 553:063b9f2f393c 4915
mbed_official 553:063b9f2f393c 4916 /****************** Bit definition for QUADSPI_SR register *******************/
mbed_official 553:063b9f2f393c 4917 #define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
mbed_official 553:063b9f2f393c 4918 #define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
mbed_official 553:063b9f2f393c 4919 #define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
mbed_official 553:063b9f2f393c 4920 #define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
mbed_official 553:063b9f2f393c 4921 #define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
mbed_official 553:063b9f2f393c 4922 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
mbed_official 553:063b9f2f393c 4923 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00003F00) /*!< FIFO Threshlod Flag */
mbed_official 553:063b9f2f393c 4924 #define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4925 #define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4926 #define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4927 #define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 553:063b9f2f393c 4928 #define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
mbed_official 553:063b9f2f393c 4929 #define QUADSPI_SR_FLEVEL_5 ((uint32_t)0x00002000) /*!< Bit 5 */
mbed_official 553:063b9f2f393c 4930
mbed_official 553:063b9f2f393c 4931 /****************** Bit definition for QUADSPI_FCR register ******************/
mbed_official 553:063b9f2f393c 4932 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
mbed_official 553:063b9f2f393c 4933 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
mbed_official 553:063b9f2f393c 4934 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
mbed_official 553:063b9f2f393c 4935 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
mbed_official 553:063b9f2f393c 4936
mbed_official 553:063b9f2f393c 4937 /****************** Bit definition for QUADSPI_DLR register ******************/
mbed_official 553:063b9f2f393c 4938 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
mbed_official 553:063b9f2f393c 4939
mbed_official 553:063b9f2f393c 4940 /****************** Bit definition for QUADSPI_CCR register ******************/
mbed_official 553:063b9f2f393c 4941 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
mbed_official 553:063b9f2f393c 4942 #define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4943 #define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4944 #define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4945 #define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 553:063b9f2f393c 4946 #define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 553:063b9f2f393c 4947 #define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 553:063b9f2f393c 4948 #define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 553:063b9f2f393c 4949 #define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 553:063b9f2f393c 4950 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
mbed_official 553:063b9f2f393c 4951 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4952 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4953 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
mbed_official 553:063b9f2f393c 4954 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4955 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4956 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
mbed_official 553:063b9f2f393c 4957 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4958 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4959 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
mbed_official 553:063b9f2f393c 4960 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4961 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4962 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
mbed_official 553:063b9f2f393c 4963 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4964 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4965 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
mbed_official 553:063b9f2f393c 4966 #define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4967 #define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4968 #define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 4969 #define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 553:063b9f2f393c 4970 #define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
mbed_official 553:063b9f2f393c 4971 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
mbed_official 553:063b9f2f393c 4972 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4973 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4974 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
mbed_official 553:063b9f2f393c 4975 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 4976 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 4977 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
mbed_official 553:063b9f2f393c 4978 #define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
mbed_official 553:063b9f2f393c 4979 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
mbed_official 553:063b9f2f393c 4980 /****************** Bit definition for QUADSPI_AR register *******************/
mbed_official 553:063b9f2f393c 4981 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
mbed_official 553:063b9f2f393c 4982
mbed_official 553:063b9f2f393c 4983 /****************** Bit definition for QUADSPI_ABR register ******************/
mbed_official 553:063b9f2f393c 4984 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
mbed_official 553:063b9f2f393c 4985
mbed_official 553:063b9f2f393c 4986 /****************** Bit definition for QUADSPI_DR register *******************/
mbed_official 553:063b9f2f393c 4987 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
mbed_official 553:063b9f2f393c 4988
mbed_official 553:063b9f2f393c 4989 /****************** Bit definition for QUADSPI_PSMKR register ****************/
mbed_official 553:063b9f2f393c 4990 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
mbed_official 553:063b9f2f393c 4991
mbed_official 553:063b9f2f393c 4992 /****************** Bit definition for QUADSPI_PSMAR register ****************/
mbed_official 553:063b9f2f393c 4993 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
mbed_official 553:063b9f2f393c 4994
mbed_official 553:063b9f2f393c 4995 /****************** Bit definition for QUADSPI_PIR register *****************/
mbed_official 553:063b9f2f393c 4996 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
mbed_official 553:063b9f2f393c 4997
mbed_official 553:063b9f2f393c 4998 /****************** Bit definition for QUADSPI_LPTR register *****************/
mbed_official 553:063b9f2f393c 4999 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
mbed_official 553:063b9f2f393c 5000
mbed_official 553:063b9f2f393c 5001 /******************************************************************************/
mbed_official 553:063b9f2f393c 5002 /* */
mbed_official 553:063b9f2f393c 5003 /* Reset and Clock Control */
mbed_official 553:063b9f2f393c 5004 /* */
mbed_official 553:063b9f2f393c 5005 /******************************************************************************/
mbed_official 553:063b9f2f393c 5006 /******************** Bit definition for RCC_CR register ********************/
mbed_official 553:063b9f2f393c 5007 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5008 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5009
mbed_official 553:063b9f2f393c 5010 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 553:063b9f2f393c 5011 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 553:063b9f2f393c 5012 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 553:063b9f2f393c 5013 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 553:063b9f2f393c 5014 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 553:063b9f2f393c 5015 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 553:063b9f2f393c 5016
mbed_official 553:063b9f2f393c 5017 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 553:063b9f2f393c 5018 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 553:063b9f2f393c 5019 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 553:063b9f2f393c 5020 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 553:063b9f2f393c 5021 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 553:063b9f2f393c 5022 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 553:063b9f2f393c 5023 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 553:063b9f2f393c 5024 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 553:063b9f2f393c 5025 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 553:063b9f2f393c 5026
mbed_official 553:063b9f2f393c 5027 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5028 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5029 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5030 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5031 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5032 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5033 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5034 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5035 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5036 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5037
mbed_official 553:063b9f2f393c 5038 /******************** Bit definition for RCC_PLLCFGR register ***************/
mbed_official 553:063b9f2f393c 5039 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
mbed_official 553:063b9f2f393c 5040 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5041 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5042 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5043 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5044 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5045 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5046
mbed_official 553:063b9f2f393c 5047 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
mbed_official 553:063b9f2f393c 5048 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5049 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5050 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5051 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5052 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5053 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5054 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5055 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5056 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5057
mbed_official 553:063b9f2f393c 5058 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
mbed_official 553:063b9f2f393c 5059 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5060 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5061
mbed_official 553:063b9f2f393c 5062 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5063 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5064 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
mbed_official 553:063b9f2f393c 5065
mbed_official 553:063b9f2f393c 5066 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
mbed_official 553:063b9f2f393c 5067 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5068 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5069 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5070 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5071
mbed_official 553:063b9f2f393c 5072 #define RCC_PLLCFGR_PLLR ((uint32_t)0x70000000)
mbed_official 553:063b9f2f393c 5073 #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5074 #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5075 #define RCC_PLLCFGR_PLLR_2 ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5076
mbed_official 553:063b9f2f393c 5077
mbed_official 553:063b9f2f393c 5078 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 553:063b9f2f393c 5079 /*!< SW configuration */
mbed_official 553:063b9f2f393c 5080 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 553:063b9f2f393c 5081 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 5082 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 5083
mbed_official 553:063b9f2f393c 5084 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 553:063b9f2f393c 5085 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 553:063b9f2f393c 5086 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL/PLLP selected as system clock */
mbed_official 553:063b9f2f393c 5087 #define RCC_CFGR_SW_PLLR ((uint32_t)0x00000003) /*!< PLL/PLLR selected as system clock */
mbed_official 553:063b9f2f393c 5088
mbed_official 553:063b9f2f393c 5089 /*!< SWS configuration */
mbed_official 553:063b9f2f393c 5090 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 553:063b9f2f393c 5091 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 5092 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 5093
mbed_official 553:063b9f2f393c 5094 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 553:063b9f2f393c 5095 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 553:063b9f2f393c 5096 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL/PLLP used as system clock */
mbed_official 553:063b9f2f393c 5097 #define RCC_CFGR_SWS_PLLR ((uint32_t)0x0000000C) /*!< PLL/PLLR used as system clock */
mbed_official 553:063b9f2f393c 5098
mbed_official 553:063b9f2f393c 5099 /*!< HPRE configuration */
mbed_official 553:063b9f2f393c 5100 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 553:063b9f2f393c 5101 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 5102 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 5103 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 5104 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 553:063b9f2f393c 5105
mbed_official 553:063b9f2f393c 5106 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 553:063b9f2f393c 5107 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 553:063b9f2f393c 5108 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 553:063b9f2f393c 5109 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 553:063b9f2f393c 5110 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 553:063b9f2f393c 5111 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 553:063b9f2f393c 5112 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 553:063b9f2f393c 5113 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 553:063b9f2f393c 5114 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 553:063b9f2f393c 5115
mbed_official 553:063b9f2f393c 5116 /*!< PPRE1 configuration */
mbed_official 553:063b9f2f393c 5117 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 553:063b9f2f393c 5118 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 5119 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 5120 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 5121
mbed_official 553:063b9f2f393c 5122 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 553:063b9f2f393c 5123 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
mbed_official 553:063b9f2f393c 5124 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
mbed_official 553:063b9f2f393c 5125 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
mbed_official 553:063b9f2f393c 5126 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
mbed_official 553:063b9f2f393c 5127
mbed_official 553:063b9f2f393c 5128 /*!< PPRE2 configuration */
mbed_official 553:063b9f2f393c 5129 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 553:063b9f2f393c 5130 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 5131 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 5132 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 553:063b9f2f393c 5133
mbed_official 553:063b9f2f393c 5134 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 553:063b9f2f393c 5135 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
mbed_official 553:063b9f2f393c 5136 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
mbed_official 553:063b9f2f393c 5137 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
mbed_official 553:063b9f2f393c 5138 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
mbed_official 553:063b9f2f393c 5139
mbed_official 553:063b9f2f393c 5140 /*!< RTCPRE configuration */
mbed_official 553:063b9f2f393c 5141 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
mbed_official 553:063b9f2f393c 5142 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5143 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5144 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5145 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5146 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5147
mbed_official 553:063b9f2f393c 5148 /*!< MCO1 configuration */
mbed_official 553:063b9f2f393c 5149 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
mbed_official 553:063b9f2f393c 5150 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5151 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5152
mbed_official 553:063b9f2f393c 5153 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5154
mbed_official 553:063b9f2f393c 5155 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
mbed_official 553:063b9f2f393c 5156 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5157 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5158 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5159
mbed_official 553:063b9f2f393c 5160 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
mbed_official 553:063b9f2f393c 5161 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5162 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5163 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5164
mbed_official 553:063b9f2f393c 5165 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
mbed_official 553:063b9f2f393c 5166 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5167 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 5168
mbed_official 553:063b9f2f393c 5169 /******************** Bit definition for RCC_CIR register *******************/
mbed_official 553:063b9f2f393c 5170 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5171 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5172 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5173 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5174 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5175 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5176 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5177 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5178 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5179 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5180 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5181 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5182 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5183 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5184 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5185 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5186 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5187 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5188 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5189 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5190 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5191 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5192 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5193
mbed_official 553:063b9f2f393c 5194 /******************** Bit definition for RCC_AHB1RSTR register **************/
mbed_official 553:063b9f2f393c 5195 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5196 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5197 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5198 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5199 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5200 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5201 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5202 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5203 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5204 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5205 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5206 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5207
mbed_official 553:063b9f2f393c 5208 /******************** Bit definition for RCC_AHB2RSTR register **************/
mbed_official 553:063b9f2f393c 5209 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5210 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5211
mbed_official 553:063b9f2f393c 5212 /******************** Bit definition for RCC_AHB3RSTR register **************/
mbed_official 553:063b9f2f393c 5213 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5214 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5215
mbed_official 553:063b9f2f393c 5216 /******************** Bit definition for RCC_APB1RSTR register **************/
mbed_official 553:063b9f2f393c 5217 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5218 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5219 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5220 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5221 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5222 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5223 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5224 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5225 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5226 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5227 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5228 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5229 #define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5230 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5231 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5232 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5233 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5234 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5235 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5236 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5237 #define RCC_APB1RSTR_FMPI2C1RST ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5238 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5239 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5240 #define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5241 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5242 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5243
mbed_official 553:063b9f2f393c 5244 /******************** Bit definition for RCC_APB2RSTR register **************/
mbed_official 553:063b9f2f393c 5245 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5246 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5247 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5248 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5249 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5250 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5251 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5252 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5253 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5254 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5255 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5256 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5257 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5258 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5259
mbed_official 553:063b9f2f393c 5260 /* Old SPI1RST bit definition, maintained for legacy purpose */
mbed_official 553:063b9f2f393c 5261 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
mbed_official 553:063b9f2f393c 5262
mbed_official 553:063b9f2f393c 5263 /******************** Bit definition for RCC_AHB1ENR register ***************/
mbed_official 553:063b9f2f393c 5264 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5265 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5266 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5267 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5268 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5269 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5270 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5271 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5272
mbed_official 553:063b9f2f393c 5273 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5274 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5275 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5276 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5277
mbed_official 553:063b9f2f393c 5278 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5279 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5280
mbed_official 553:063b9f2f393c 5281 /******************** Bit definition for RCC_AHB2ENR register ***************/
mbed_official 553:063b9f2f393c 5282 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5283 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5284
mbed_official 553:063b9f2f393c 5285 /******************** Bit definition for RCC_AHB3ENR register ***************/
mbed_official 553:063b9f2f393c 5286 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5287 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5288
mbed_official 553:063b9f2f393c 5289 /******************** Bit definition for RCC_APB1ENR register ***************/
mbed_official 553:063b9f2f393c 5290 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5291 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5292 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5293 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5294 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5295 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5296 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5297 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5298 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5299 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5300 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5301 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5302 #define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5303 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5304 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5305 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5306 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5307 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5308 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5309 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5310 #define RCC_APB1ENR_FMPI2C1EN ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5311 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5312 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5313 #define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5314 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5315 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5316
mbed_official 553:063b9f2f393c 5317 /******************** Bit definition for RCC_APB2ENR register ***************/
mbed_official 553:063b9f2f393c 5318 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5319 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5320 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5321 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5322 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5323 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5324 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5325 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5326 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5327 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5328 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5329 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5330 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5331 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5332 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5333 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5334
mbed_official 553:063b9f2f393c 5335 /******************** Bit definition for RCC_AHB1LPENR register *************/
mbed_official 553:063b9f2f393c 5336 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5337 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5338 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5339 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5340 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5341 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5342 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5343 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5344 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5345 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5346 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5347
mbed_official 553:063b9f2f393c 5348 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5349 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5350 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5351 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5352 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5353 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5354 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5355
mbed_official 553:063b9f2f393c 5356 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5357 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5358
mbed_official 553:063b9f2f393c 5359 /******************** Bit definition for RCC_AHB2LPENR register *************/
mbed_official 553:063b9f2f393c 5360 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5361 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5362
mbed_official 553:063b9f2f393c 5363 /******************** Bit definition for RCC_AHB3LPENR register *************/
mbed_official 553:063b9f2f393c 5364 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5365 #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5366
mbed_official 553:063b9f2f393c 5367 /******************** Bit definition for RCC_APB1LPENR register *************/
mbed_official 553:063b9f2f393c 5368 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5369 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5370 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5371 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5372 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5373 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5374 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5375 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5376 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5377 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5378 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5379 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5380 #define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5381 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5382 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5383 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5384 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5385 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5386 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5387 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5388 #define RCC_APB1LPENR_FMPI2C1LPEN ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5389 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5390 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5391 #define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5392 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5393 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5394
mbed_official 553:063b9f2f393c 5395 /******************** Bit definition for RCC_APB2LPENR register *************/
mbed_official 553:063b9f2f393c 5396 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5397 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5398 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5399 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5400 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5401 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5402 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5403 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5404 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5405 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5406 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5407 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5408 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5409 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5410 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5411 #define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5412
mbed_official 553:063b9f2f393c 5413 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 553:063b9f2f393c 5414 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5415 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5416 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5417 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5418
mbed_official 553:063b9f2f393c 5419 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
mbed_official 553:063b9f2f393c 5420 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5421 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5422
mbed_official 553:063b9f2f393c 5423 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5424 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5425
mbed_official 553:063b9f2f393c 5426 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 553:063b9f2f393c 5427 #define RCC_CSR_LSION ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5428 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5429 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5430 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5431 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5432 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5433 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5434 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5435 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5436 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 5437
mbed_official 553:063b9f2f393c 5438 /******************** Bit definition for RCC_SSCGR register *****************/
mbed_official 553:063b9f2f393c 5439 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
mbed_official 553:063b9f2f393c 5440 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
mbed_official 553:063b9f2f393c 5441 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5442 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 5443
mbed_official 553:063b9f2f393c 5444 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
mbed_official 553:063b9f2f393c 5445 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
mbed_official 553:063b9f2f393c 5446 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5447 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5448 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5449 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5450 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5451 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5452
mbed_official 553:063b9f2f393c 5453 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
mbed_official 553:063b9f2f393c 5454 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5455 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5456 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5457 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5458 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5459 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5460 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5461 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5462 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5463
mbed_official 553:063b9f2f393c 5464 #define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
mbed_official 553:063b9f2f393c 5465 #define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5466 #define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5467
mbed_official 553:063b9f2f393c 5468 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
mbed_official 553:063b9f2f393c 5469 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5470 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5471 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5472 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5473
mbed_official 553:063b9f2f393c 5474 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
mbed_official 553:063b9f2f393c 5475 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5476 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5477 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5478
mbed_official 553:063b9f2f393c 5479
mbed_official 553:063b9f2f393c 5480 /******************** Bit definition for RCC_PLLSAICFGR register ************/
mbed_official 553:063b9f2f393c 5481 #define RCC_PLLSAICFGR_PLLSAIM ((uint32_t)0x0000003F)
mbed_official 553:063b9f2f393c 5482 #define RCC_PLLSAICFGR_PLLSAIM_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5483 #define RCC_PLLSAICFGR_PLLSAIM_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5484 #define RCC_PLLSAICFGR_PLLSAIM_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5485 #define RCC_PLLSAICFGR_PLLSAIM_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5486 #define RCC_PLLSAICFGR_PLLSAIM_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5487 #define RCC_PLLSAICFGR_PLLSAIM_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5488
mbed_official 553:063b9f2f393c 5489 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
mbed_official 553:063b9f2f393c 5490 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5491 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5492 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5493 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5494 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5495 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5496 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5497 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5498 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5499
mbed_official 553:063b9f2f393c 5500 #define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
mbed_official 553:063b9f2f393c 5501 #define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5502 #define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5503
mbed_official 553:063b9f2f393c 5504 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
mbed_official 553:063b9f2f393c 5505 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5506 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5507 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5508 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5509
mbed_official 553:063b9f2f393c 5510 /******************** Bit definition for RCC_DCKCFGR register ***************/
mbed_official 553:063b9f2f393c 5511 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
mbed_official 553:063b9f2f393c 5512 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
mbed_official 553:063b9f2f393c 5513 #define RCC_DCKCFGR_SAI1SRC ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 5514 #define RCC_DCKCFGR_SAI1SRC_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5515 #define RCC_DCKCFGR_SAI1SRC_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5516 #define RCC_DCKCFGR_SAI2SRC ((uint32_t)0x00C00000)
mbed_official 553:063b9f2f393c 5517 #define RCC_DCKCFGR_SAI2SRC_0 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5518 #define RCC_DCKCFGR_SAI2SRC_1 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5519 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5520 #define RCC_DCKCFGR_I2S1SRC ((uint32_t)0x06000000)
mbed_official 553:063b9f2f393c 5521 #define RCC_DCKCFGR_I2S1SRC_0 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5522 #define RCC_DCKCFGR_I2S1SRC_1 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5523 #define RCC_DCKCFGR_I2S2SRC ((uint32_t)0x18000000)
mbed_official 553:063b9f2f393c 5524 #define RCC_DCKCFGR_I2S2SRC_0 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5525 #define RCC_DCKCFGR_I2S2SRC_1 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5526
mbed_official 553:063b9f2f393c 5527 /******************** Bit definition for RCC_CKGATENR register ***************/
mbed_official 553:063b9f2f393c 5528 #define RCC_CKGATENR_AHB2APB1_CKEN ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5529 #define RCC_CKGATENR_AHB2APB2_CKEN ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5530 #define RCC_CKGATENR_CM4DBG_CKEN ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5531 #define RCC_CKGATENR_SPARE_CKEN ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5532 #define RCC_CKGATENR_SRAM_CKEN ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5533 #define RCC_CKGATENR_FLITF_CKEN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5534 #define RCC_CKGATENR_RCC_CKEN ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5535
mbed_official 553:063b9f2f393c 5536 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
mbed_official 553:063b9f2f393c 5537 #define RCC_DCKCFGR2_FMPI2C1SEL ((uint32_t)0x00C00000)
mbed_official 553:063b9f2f393c 5538 #define RCC_DCKCFGR2_FMPI2C1SEL_0 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5539 #define RCC_DCKCFGR2_FMPI2C1SEL_1 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5540 #define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5541 #define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5542 #define RCC_DCKCFGR2_SDIOSEL ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5543 #define RCC_DCKCFGR2_SPDIFRXSEL ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5544
mbed_official 553:063b9f2f393c 5545 /******************************************************************************/
mbed_official 553:063b9f2f393c 5546 /* */
mbed_official 553:063b9f2f393c 5547 /* Real-Time Clock (RTC) */
mbed_official 553:063b9f2f393c 5548 /* */
mbed_official 553:063b9f2f393c 5549 /******************************************************************************/
mbed_official 553:063b9f2f393c 5550 /******************** Bits definition for RTC_TR register *******************/
mbed_official 553:063b9f2f393c 5551 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5552 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 5553 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5554 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5555 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 553:063b9f2f393c 5556 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5557 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5558 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5559 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5560 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 553:063b9f2f393c 5561 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5562 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5563 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5564 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 553:063b9f2f393c 5565 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5566 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5567 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5568 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5569 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 553:063b9f2f393c 5570 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5571 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5572 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5573 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 5574 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5575 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5576 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5577 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5578
mbed_official 553:063b9f2f393c 5579 /******************** Bits definition for RTC_DR register *******************/
mbed_official 553:063b9f2f393c 5580 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 553:063b9f2f393c 5581 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5582 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5583 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5584 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5585 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 553:063b9f2f393c 5586 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5587 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5588 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5589 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5590 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 553:063b9f2f393c 5591 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5592 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5593 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5594 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5595 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 553:063b9f2f393c 5596 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5597 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5598 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5599 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5600 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 553:063b9f2f393c 5601 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5602 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5603 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 5604 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5605 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5606 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5607 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5608
mbed_official 553:063b9f2f393c 5609 /******************** Bits definition for RTC_CR register *******************/
mbed_official 553:063b9f2f393c 5610 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5611 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 553:063b9f2f393c 5612 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5613 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5614 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5615 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5616 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5617 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5618 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5619 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5620 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5621 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5622 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5623 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5624 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5625 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5626 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5627 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5628 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5629 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5630 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5631 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5632 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 553:063b9f2f393c 5633 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5634 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5635 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5636
mbed_official 553:063b9f2f393c 5637 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 553:063b9f2f393c 5638 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5639 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5640 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5641 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5642 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5643 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5644 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5645 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5646 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5647 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5648 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5649 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5650 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5651 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5652 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5653 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5654
mbed_official 553:063b9f2f393c 5655 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 553:063b9f2f393c 5656 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 553:063b9f2f393c 5657 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
mbed_official 553:063b9f2f393c 5658
mbed_official 553:063b9f2f393c 5659 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 553:063b9f2f393c 5660 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 553:063b9f2f393c 5661
mbed_official 553:063b9f2f393c 5662 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 553:063b9f2f393c 5663 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5664 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 553:063b9f2f393c 5665
mbed_official 553:063b9f2f393c 5666 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 553:063b9f2f393c 5667 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 5668 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5669 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 553:063b9f2f393c 5670 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5671 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5672 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 553:063b9f2f393c 5673 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5674 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5675 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5676 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5677 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5678 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5679 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 5680 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5681 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5682 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 553:063b9f2f393c 5683 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5684 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5685 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5686 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5687 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5688 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 553:063b9f2f393c 5689 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5690 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5691 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5692 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 553:063b9f2f393c 5693 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5694 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5695 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5696 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5697 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5698 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 553:063b9f2f393c 5699 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5700 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5701 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5702 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 5703 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5704 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5705 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5706 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5707
mbed_official 553:063b9f2f393c 5708 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 553:063b9f2f393c 5709 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 5710 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 553:063b9f2f393c 5711 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 553:063b9f2f393c 5712 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 553:063b9f2f393c 5713 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 553:063b9f2f393c 5714 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 553:063b9f2f393c 5715 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5716 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5717 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5718 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5719 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 5720 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5721 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 5722 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5723 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5724 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 553:063b9f2f393c 5725 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5726 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5727 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5728 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5729 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5730 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 553:063b9f2f393c 5731 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5732 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5733 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5734 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 553:063b9f2f393c 5735 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5736 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5737 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5738 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5739 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5740 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 553:063b9f2f393c 5741 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5742 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5743 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5744 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 5745 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5746 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5747 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5748 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5749
mbed_official 553:063b9f2f393c 5750 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 553:063b9f2f393c 5751 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 553:063b9f2f393c 5752
mbed_official 553:063b9f2f393c 5753 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 553:063b9f2f393c 5754 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 553:063b9f2f393c 5755
mbed_official 553:063b9f2f393c 5756 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 553:063b9f2f393c 5757 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 553:063b9f2f393c 5758 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 553:063b9f2f393c 5759
mbed_official 553:063b9f2f393c 5760 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 553:063b9f2f393c 5761 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 5762 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 553:063b9f2f393c 5763 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 553:063b9f2f393c 5764 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 5765 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 553:063b9f2f393c 5766 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5767 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5768 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5769 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 553:063b9f2f393c 5770 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 553:063b9f2f393c 5771 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5772 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5773 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5774 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 553:063b9f2f393c 5775 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5776 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5777 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5778 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5779 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 553:063b9f2f393c 5780 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5781 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5782 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5783 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 5784 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5785 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5786 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5787 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5788
mbed_official 553:063b9f2f393c 5789 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 553:063b9f2f393c 5790 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 553:063b9f2f393c 5791 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5792 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5793 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5794 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5795 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 553:063b9f2f393c 5796 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5797 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5798 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5799 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5800 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 553:063b9f2f393c 5801 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5802 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5803 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 553:063b9f2f393c 5804 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5805 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5806 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5807 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5808
mbed_official 553:063b9f2f393c 5809 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 553:063b9f2f393c 5810 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 553:063b9f2f393c 5811
mbed_official 553:063b9f2f393c 5812 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 553:063b9f2f393c 5813 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5814 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5815 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5816 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 553:063b9f2f393c 5817 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5818 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5819 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5820 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5821 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5822 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 5823 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 5824 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5825 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5826
mbed_official 553:063b9f2f393c 5827 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 553:063b9f2f393c 5828 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 5829 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 5830 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 5831 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 553:063b9f2f393c 5832 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 553:063b9f2f393c 5833 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 553:063b9f2f393c 5834 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 553:063b9f2f393c 5835 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 553:063b9f2f393c 5836 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 5837 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 5838 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 553:063b9f2f393c 5839 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 5840 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 553:063b9f2f393c 5841 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 5842 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 5843 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 5844 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 5845 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 5846 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 5847 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 5848
mbed_official 553:063b9f2f393c 5849 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 553:063b9f2f393c 5850 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 553:063b9f2f393c 5851 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5852 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5853 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5854 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5855 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 553:063b9f2f393c 5856
mbed_official 553:063b9f2f393c 5857 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 553:063b9f2f393c 5858 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 553:063b9f2f393c 5859 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 553:063b9f2f393c 5860 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 5861 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 5862 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 553:063b9f2f393c 5863 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 553:063b9f2f393c 5864
mbed_official 553:063b9f2f393c 5865 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 553:063b9f2f393c 5866 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5867
mbed_official 553:063b9f2f393c 5868 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 553:063b9f2f393c 5869 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5870
mbed_official 553:063b9f2f393c 5871 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 553:063b9f2f393c 5872 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5873
mbed_official 553:063b9f2f393c 5874 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 553:063b9f2f393c 5875 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5876
mbed_official 553:063b9f2f393c 5877 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 553:063b9f2f393c 5878 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5879
mbed_official 553:063b9f2f393c 5880 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 553:063b9f2f393c 5881 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5882
mbed_official 553:063b9f2f393c 5883 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 553:063b9f2f393c 5884 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5885
mbed_official 553:063b9f2f393c 5886 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 553:063b9f2f393c 5887 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5888
mbed_official 553:063b9f2f393c 5889 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 553:063b9f2f393c 5890 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5891
mbed_official 553:063b9f2f393c 5892 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 553:063b9f2f393c 5893 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5894
mbed_official 553:063b9f2f393c 5895 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 553:063b9f2f393c 5896 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5897
mbed_official 553:063b9f2f393c 5898 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 553:063b9f2f393c 5899 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5900
mbed_official 553:063b9f2f393c 5901 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 553:063b9f2f393c 5902 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5903
mbed_official 553:063b9f2f393c 5904 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 553:063b9f2f393c 5905 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5906
mbed_official 553:063b9f2f393c 5907 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 553:063b9f2f393c 5908 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5909
mbed_official 553:063b9f2f393c 5910 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 553:063b9f2f393c 5911 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5912
mbed_official 553:063b9f2f393c 5913 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 553:063b9f2f393c 5914 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5915
mbed_official 553:063b9f2f393c 5916 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 553:063b9f2f393c 5917 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5918
mbed_official 553:063b9f2f393c 5919 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 553:063b9f2f393c 5920 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5921
mbed_official 553:063b9f2f393c 5922 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 553:063b9f2f393c 5923 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 5924
mbed_official 553:063b9f2f393c 5925 /******************************************************************************/
mbed_official 553:063b9f2f393c 5926 /* */
mbed_official 553:063b9f2f393c 5927 /* Serial Audio Interface */
mbed_official 553:063b9f2f393c 5928 /* */
mbed_official 553:063b9f2f393c 5929 /******************************************************************************/
mbed_official 553:063b9f2f393c 5930 /******************** Bit definition for SAI_GCR register *******************/
mbed_official 553:063b9f2f393c 5931 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
mbed_official 553:063b9f2f393c 5932 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5933 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5934
mbed_official 553:063b9f2f393c 5935 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
mbed_official 553:063b9f2f393c 5936 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5937 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5938
mbed_official 553:063b9f2f393c 5939 /******************* Bit definition for SAI_xCR1 register *******************/
mbed_official 553:063b9f2f393c 5940 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
mbed_official 553:063b9f2f393c 5941 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5942 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5943
mbed_official 553:063b9f2f393c 5944 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
mbed_official 553:063b9f2f393c 5945 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5946 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5947
mbed_official 553:063b9f2f393c 5948 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
mbed_official 553:063b9f2f393c 5949 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5950 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5951 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 5952
mbed_official 553:063b9f2f393c 5953 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
mbed_official 553:063b9f2f393c 5954 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
mbed_official 553:063b9f2f393c 5955
mbed_official 553:063b9f2f393c 5956 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
mbed_official 553:063b9f2f393c 5957 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5958 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5959
mbed_official 553:063b9f2f393c 5960 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
mbed_official 553:063b9f2f393c 5961 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
mbed_official 553:063b9f2f393c 5962 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
mbed_official 553:063b9f2f393c 5963 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
mbed_official 553:063b9f2f393c 5964 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
mbed_official 553:063b9f2f393c 5965
mbed_official 553:063b9f2f393c 5966 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
mbed_official 553:063b9f2f393c 5967 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5968 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5969 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 5970 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 5971
mbed_official 553:063b9f2f393c 5972 /******************* Bit definition for SAI_xCR2 register *******************/
mbed_official 553:063b9f2f393c 5973 #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
mbed_official 553:063b9f2f393c 5974 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5975 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5976 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 5977
mbed_official 553:063b9f2f393c 5978 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
mbed_official 553:063b9f2f393c 5979 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
mbed_official 553:063b9f2f393c 5980 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
mbed_official 553:063b9f2f393c 5981 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
mbed_official 553:063b9f2f393c 5982
mbed_official 553:063b9f2f393c 5983 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
mbed_official 553:063b9f2f393c 5984 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5985 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5986 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 5987 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 5988 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 5989 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 5990
mbed_official 553:063b9f2f393c 5991 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
mbed_official 553:063b9f2f393c 5992
mbed_official 553:063b9f2f393c 5993 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
mbed_official 553:063b9f2f393c 5994 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 5995 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 5996
mbed_official 553:063b9f2f393c 5997 /****************** Bit definition for SAI_xFRCR register *******************/
mbed_official 553:063b9f2f393c 5998 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
mbed_official 553:063b9f2f393c 5999 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6000 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6001 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6002 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6003 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 6004 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 6005 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 6006 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 6007
mbed_official 553:063b9f2f393c 6008 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
mbed_official 553:063b9f2f393c 6009 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6010 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6011 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6012 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6013 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 6014 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 6015 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 6016
mbed_official 553:063b9f2f393c 6017 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
mbed_official 553:063b9f2f393c 6018 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
mbed_official 553:063b9f2f393c 6019 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
mbed_official 553:063b9f2f393c 6020
mbed_official 553:063b9f2f393c 6021 /****************** Bit definition for SAI_xSLOTR register *******************/
mbed_official 553:063b9f2f393c 6022 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
mbed_official 553:063b9f2f393c 6023 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6024 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6025 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6026 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6027 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 6028
mbed_official 553:063b9f2f393c 6029 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
mbed_official 553:063b9f2f393c 6030 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6031 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6032
mbed_official 553:063b9f2f393c 6033 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
mbed_official 553:063b9f2f393c 6034 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6035 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6036 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6037 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6038
mbed_official 553:063b9f2f393c 6039 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
mbed_official 553:063b9f2f393c 6040
mbed_official 553:063b9f2f393c 6041 /******************* Bit definition for SAI_xIMR register *******************/
mbed_official 553:063b9f2f393c 6042 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
mbed_official 553:063b9f2f393c 6043 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
mbed_official 553:063b9f2f393c 6044 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
mbed_official 553:063b9f2f393c 6045 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
mbed_official 553:063b9f2f393c 6046 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
mbed_official 553:063b9f2f393c 6047 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
mbed_official 553:063b9f2f393c 6048 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
mbed_official 553:063b9f2f393c 6049
mbed_official 553:063b9f2f393c 6050 /******************** Bit definition for SAI_xSR register *******************/
mbed_official 553:063b9f2f393c 6051 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
mbed_official 553:063b9f2f393c 6052 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
mbed_official 553:063b9f2f393c 6053 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
mbed_official 553:063b9f2f393c 6054 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
mbed_official 553:063b9f2f393c 6055 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
mbed_official 553:063b9f2f393c 6056 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
mbed_official 553:063b9f2f393c 6057 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
mbed_official 553:063b9f2f393c 6058
mbed_official 553:063b9f2f393c 6059 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
mbed_official 553:063b9f2f393c 6060 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6061 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6062 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6063
mbed_official 553:063b9f2f393c 6064 /****************** Bit definition for SAI_xCLRFR register ******************/
mbed_official 553:063b9f2f393c 6065 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
mbed_official 553:063b9f2f393c 6066 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
mbed_official 553:063b9f2f393c 6067 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
mbed_official 553:063b9f2f393c 6068 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
mbed_official 553:063b9f2f393c 6069 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
mbed_official 553:063b9f2f393c 6070 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
mbed_official 553:063b9f2f393c 6071 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
mbed_official 553:063b9f2f393c 6072
mbed_official 553:063b9f2f393c 6073 /****************** Bit definition for SAI_xDR register ******************/
mbed_official 553:063b9f2f393c 6074 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
mbed_official 553:063b9f2f393c 6075
mbed_official 553:063b9f2f393c 6076 /******************************************************************************/
mbed_official 553:063b9f2f393c 6077 /* */
mbed_official 553:063b9f2f393c 6078 /* SPDIF-RX Interface */
mbed_official 553:063b9f2f393c 6079 /* */
mbed_official 553:063b9f2f393c 6080 /******************************************************************************/
mbed_official 553:063b9f2f393c 6081 /******************** Bit definition for SPDIFRX_CR register *******************/
mbed_official 553:063b9f2f393c 6082 #define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
mbed_official 553:063b9f2f393c 6083 #define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
mbed_official 553:063b9f2f393c 6084 #define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
mbed_official 553:063b9f2f393c 6085 #define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
mbed_official 553:063b9f2f393c 6086 #define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
mbed_official 553:063b9f2f393c 6087 #define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
mbed_official 553:063b9f2f393c 6088 #define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
mbed_official 553:063b9f2f393c 6089 #define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
mbed_official 553:063b9f2f393c 6090 #define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
mbed_official 553:063b9f2f393c 6091 #define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
mbed_official 553:063b9f2f393c 6092 #define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
mbed_official 553:063b9f2f393c 6093 #define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
mbed_official 553:063b9f2f393c 6094 #define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIFRX input selection */
mbed_official 553:063b9f2f393c 6095
mbed_official 553:063b9f2f393c 6096 /******************* Bit definition for SPDIFRX_IMR register *******************/
mbed_official 553:063b9f2f393c 6097 #define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
mbed_official 553:063b9f2f393c 6098 #define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
mbed_official 553:063b9f2f393c 6099 #define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
mbed_official 553:063b9f2f393c 6100 #define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
mbed_official 553:063b9f2f393c 6101 #define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
mbed_official 553:063b9f2f393c 6102 #define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
mbed_official 553:063b9f2f393c 6103 #define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
mbed_official 553:063b9f2f393c 6104
mbed_official 553:063b9f2f393c 6105 /******************* Bit definition for SPDIFRX_SR register *******************/
mbed_official 553:063b9f2f393c 6106 #define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
mbed_official 553:063b9f2f393c 6107 #define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
mbed_official 553:063b9f2f393c 6108 #define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
mbed_official 553:063b9f2f393c 6109 #define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
mbed_official 553:063b9f2f393c 6110 #define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
mbed_official 553:063b9f2f393c 6111 #define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
mbed_official 553:063b9f2f393c 6112 #define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
mbed_official 553:063b9f2f393c 6113 #define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
mbed_official 553:063b9f2f393c 6114 #define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
mbed_official 553:063b9f2f393c 6115 #define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with SPDIFRX_clk */
mbed_official 553:063b9f2f393c 6116
mbed_official 553:063b9f2f393c 6117 /******************* Bit definition for SPDIFRX_IFCR register *******************/
mbed_official 553:063b9f2f393c 6118 #define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
mbed_official 553:063b9f2f393c 6119 #define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
mbed_official 553:063b9f2f393c 6120 #define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
mbed_official 553:063b9f2f393c 6121 #define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
mbed_official 553:063b9f2f393c 6122
mbed_official 553:063b9f2f393c 6123 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
mbed_official 553:063b9f2f393c 6124 #define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
mbed_official 553:063b9f2f393c 6125 #define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
mbed_official 553:063b9f2f393c 6126 #define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
mbed_official 553:063b9f2f393c 6127 #define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
mbed_official 553:063b9f2f393c 6128 #define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
mbed_official 553:063b9f2f393c 6129 #define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
mbed_official 553:063b9f2f393c 6130
mbed_official 553:063b9f2f393c 6131 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
mbed_official 553:063b9f2f393c 6132 #define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
mbed_official 553:063b9f2f393c 6133 #define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
mbed_official 553:063b9f2f393c 6134 #define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
mbed_official 553:063b9f2f393c 6135 #define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
mbed_official 553:063b9f2f393c 6136 #define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
mbed_official 553:063b9f2f393c 6137 #define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
mbed_official 553:063b9f2f393c 6138
mbed_official 553:063b9f2f393c 6139 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
mbed_official 553:063b9f2f393c 6140 #define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
mbed_official 553:063b9f2f393c 6141 #define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
mbed_official 553:063b9f2f393c 6142
mbed_official 553:063b9f2f393c 6143 /******************* Bit definition for SPDIFRX_CSR register *******************/
mbed_official 553:063b9f2f393c 6144 #define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
mbed_official 553:063b9f2f393c 6145 #define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
mbed_official 553:063b9f2f393c 6146 #define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
mbed_official 553:063b9f2f393c 6147
mbed_official 553:063b9f2f393c 6148 /******************* Bit definition for SPDIFRX_DIR register *******************/
mbed_official 553:063b9f2f393c 6149 #define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
mbed_official 553:063b9f2f393c 6150 #define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
mbed_official 553:063b9f2f393c 6151
mbed_official 553:063b9f2f393c 6152
mbed_official 553:063b9f2f393c 6153 /******************************************************************************/
mbed_official 553:063b9f2f393c 6154 /* */
mbed_official 553:063b9f2f393c 6155 /* SD host Interface */
mbed_official 553:063b9f2f393c 6156 /* */
mbed_official 553:063b9f2f393c 6157 /******************************************************************************/
mbed_official 553:063b9f2f393c 6158 /****************** Bit definition for SDIO_POWER register ******************/
mbed_official 553:063b9f2f393c 6159 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
mbed_official 553:063b9f2f393c 6160 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6161 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6162
mbed_official 553:063b9f2f393c 6163 /****************** Bit definition for SDIO_CLKCR register ******************/
mbed_official 553:063b9f2f393c 6164 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
mbed_official 553:063b9f2f393c 6165 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
mbed_official 553:063b9f2f393c 6166 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
mbed_official 553:063b9f2f393c 6167 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
mbed_official 553:063b9f2f393c 6168
mbed_official 553:063b9f2f393c 6169 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
mbed_official 553:063b9f2f393c 6170 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6171 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6172
mbed_official 553:063b9f2f393c 6173 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
mbed_official 553:063b9f2f393c 6174 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
mbed_official 553:063b9f2f393c 6175
mbed_official 553:063b9f2f393c 6176 /******************* Bit definition for SDIO_ARG register *******************/
mbed_official 553:063b9f2f393c 6177 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
mbed_official 553:063b9f2f393c 6178
mbed_official 553:063b9f2f393c 6179 /******************* Bit definition for SDIO_CMD register *******************/
mbed_official 553:063b9f2f393c 6180 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
mbed_official 553:063b9f2f393c 6181
mbed_official 553:063b9f2f393c 6182 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
mbed_official 553:063b9f2f393c 6183 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
mbed_official 553:063b9f2f393c 6184 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
mbed_official 553:063b9f2f393c 6185
mbed_official 553:063b9f2f393c 6186 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
mbed_official 553:063b9f2f393c 6187 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
mbed_official 553:063b9f2f393c 6188 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
mbed_official 553:063b9f2f393c 6189 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
mbed_official 553:063b9f2f393c 6190
mbed_official 553:063b9f2f393c 6191 /***************** Bit definition for SDIO_RESPCMD register *****************/
mbed_official 553:063b9f2f393c 6192 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
mbed_official 553:063b9f2f393c 6193
mbed_official 553:063b9f2f393c 6194 /****************** Bit definition for SDIO_RESP0 register ******************/
mbed_official 553:063b9f2f393c 6195 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 553:063b9f2f393c 6196
mbed_official 553:063b9f2f393c 6197 /****************** Bit definition for SDIO_RESP1 register ******************/
mbed_official 553:063b9f2f393c 6198 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 553:063b9f2f393c 6199
mbed_official 553:063b9f2f393c 6200 /****************** Bit definition for SDIO_RESP2 register ******************/
mbed_official 553:063b9f2f393c 6201 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 553:063b9f2f393c 6202
mbed_official 553:063b9f2f393c 6203 /****************** Bit definition for SDIO_RESP3 register ******************/
mbed_official 553:063b9f2f393c 6204 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 553:063b9f2f393c 6205
mbed_official 553:063b9f2f393c 6206 /****************** Bit definition for SDIO_RESP4 register ******************/
mbed_official 553:063b9f2f393c 6207 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 553:063b9f2f393c 6208
mbed_official 553:063b9f2f393c 6209 /****************** Bit definition for SDIO_DTIMER register *****************/
mbed_official 553:063b9f2f393c 6210 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
mbed_official 553:063b9f2f393c 6211
mbed_official 553:063b9f2f393c 6212 /****************** Bit definition for SDIO_DLEN register *******************/
mbed_official 553:063b9f2f393c 6213 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
mbed_official 553:063b9f2f393c 6214
mbed_official 553:063b9f2f393c 6215 /****************** Bit definition for SDIO_DCTRL register ******************/
mbed_official 553:063b9f2f393c 6216 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
mbed_official 553:063b9f2f393c 6217 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
mbed_official 553:063b9f2f393c 6218 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
mbed_official 553:063b9f2f393c 6219 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
mbed_official 553:063b9f2f393c 6220
mbed_official 553:063b9f2f393c 6221 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
mbed_official 553:063b9f2f393c 6222 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6223 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6224 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6225 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6226
mbed_official 553:063b9f2f393c 6227 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
mbed_official 553:063b9f2f393c 6228 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
mbed_official 553:063b9f2f393c 6229 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
mbed_official 553:063b9f2f393c 6230 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
mbed_official 553:063b9f2f393c 6231
mbed_official 553:063b9f2f393c 6232 /****************** Bit definition for SDIO_DCOUNT register *****************/
mbed_official 553:063b9f2f393c 6233 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
mbed_official 553:063b9f2f393c 6234
mbed_official 553:063b9f2f393c 6235 /****************** Bit definition for SDIO_STA register ********************/
mbed_official 553:063b9f2f393c 6236 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
mbed_official 553:063b9f2f393c 6237 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
mbed_official 553:063b9f2f393c 6238 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
mbed_official 553:063b9f2f393c 6239 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
mbed_official 553:063b9f2f393c 6240 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
mbed_official 553:063b9f2f393c 6241 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
mbed_official 553:063b9f2f393c 6242 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
mbed_official 553:063b9f2f393c 6243 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
mbed_official 553:063b9f2f393c 6244 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
mbed_official 553:063b9f2f393c 6245 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
mbed_official 553:063b9f2f393c 6246 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
mbed_official 553:063b9f2f393c 6247 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
mbed_official 553:063b9f2f393c 6248 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
mbed_official 553:063b9f2f393c 6249 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
mbed_official 553:063b9f2f393c 6250 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
mbed_official 553:063b9f2f393c 6251 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
mbed_official 553:063b9f2f393c 6252 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
mbed_official 553:063b9f2f393c 6253 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
mbed_official 553:063b9f2f393c 6254 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
mbed_official 553:063b9f2f393c 6255 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
mbed_official 553:063b9f2f393c 6256 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
mbed_official 553:063b9f2f393c 6257 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
mbed_official 553:063b9f2f393c 6258
mbed_official 553:063b9f2f393c 6259 /******************* Bit definition for SDIO_ICR register *******************/
mbed_official 553:063b9f2f393c 6260 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
mbed_official 553:063b9f2f393c 6261 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
mbed_official 553:063b9f2f393c 6262 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
mbed_official 553:063b9f2f393c 6263 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
mbed_official 553:063b9f2f393c 6264 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
mbed_official 553:063b9f2f393c 6265 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
mbed_official 553:063b9f2f393c 6266 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
mbed_official 553:063b9f2f393c 6267 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
mbed_official 553:063b9f2f393c 6268 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
mbed_official 553:063b9f2f393c 6269 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
mbed_official 553:063b9f2f393c 6270 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
mbed_official 553:063b9f2f393c 6271
mbed_official 553:063b9f2f393c 6272 /****************** Bit definition for SDIO_MASK register *******************/
mbed_official 553:063b9f2f393c 6273 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
mbed_official 553:063b9f2f393c 6274 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
mbed_official 553:063b9f2f393c 6275 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
mbed_official 553:063b9f2f393c 6276 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
mbed_official 553:063b9f2f393c 6277 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
mbed_official 553:063b9f2f393c 6278 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
mbed_official 553:063b9f2f393c 6279 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
mbed_official 553:063b9f2f393c 6280 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
mbed_official 553:063b9f2f393c 6281 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
mbed_official 553:063b9f2f393c 6282 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
mbed_official 553:063b9f2f393c 6283 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
mbed_official 553:063b9f2f393c 6284 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
mbed_official 553:063b9f2f393c 6285 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
mbed_official 553:063b9f2f393c 6286 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
mbed_official 553:063b9f2f393c 6287 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
mbed_official 553:063b9f2f393c 6288 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
mbed_official 553:063b9f2f393c 6289 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
mbed_official 553:063b9f2f393c 6290 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
mbed_official 553:063b9f2f393c 6291 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
mbed_official 553:063b9f2f393c 6292 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
mbed_official 553:063b9f2f393c 6293 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
mbed_official 553:063b9f2f393c 6294 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
mbed_official 553:063b9f2f393c 6295
mbed_official 553:063b9f2f393c 6296 /***************** Bit definition for SDIO_FIFOCNT register *****************/
mbed_official 553:063b9f2f393c 6297 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
mbed_official 553:063b9f2f393c 6298
mbed_official 553:063b9f2f393c 6299 /****************** Bit definition for SDIO_FIFO register *******************/
mbed_official 553:063b9f2f393c 6300 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
mbed_official 553:063b9f2f393c 6301
mbed_official 553:063b9f2f393c 6302 /******************************************************************************/
mbed_official 553:063b9f2f393c 6303 /* */
mbed_official 553:063b9f2f393c 6304 /* Serial Peripheral Interface */
mbed_official 553:063b9f2f393c 6305 /* */
mbed_official 553:063b9f2f393c 6306 /******************************************************************************/
mbed_official 553:063b9f2f393c 6307 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 553:063b9f2f393c 6308 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
mbed_official 553:063b9f2f393c 6309 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
mbed_official 553:063b9f2f393c 6310 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
mbed_official 553:063b9f2f393c 6311
mbed_official 553:063b9f2f393c 6312 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
mbed_official 553:063b9f2f393c 6313 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6314 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6315 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6316
mbed_official 553:063b9f2f393c 6317 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
mbed_official 553:063b9f2f393c 6318 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
mbed_official 553:063b9f2f393c 6319 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
mbed_official 553:063b9f2f393c 6320 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
mbed_official 553:063b9f2f393c 6321 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
mbed_official 553:063b9f2f393c 6322 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
mbed_official 553:063b9f2f393c 6323 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
mbed_official 553:063b9f2f393c 6324 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
mbed_official 553:063b9f2f393c 6325 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
mbed_official 553:063b9f2f393c 6326 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
mbed_official 553:063b9f2f393c 6327
mbed_official 553:063b9f2f393c 6328 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 553:063b9f2f393c 6329 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
mbed_official 553:063b9f2f393c 6330 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
mbed_official 553:063b9f2f393c 6331 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
mbed_official 553:063b9f2f393c 6332 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
mbed_official 553:063b9f2f393c 6333 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
mbed_official 553:063b9f2f393c 6334 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
mbed_official 553:063b9f2f393c 6335 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
mbed_official 553:063b9f2f393c 6336
mbed_official 553:063b9f2f393c 6337 /******************** Bit definition for SPI_SR register ********************/
mbed_official 553:063b9f2f393c 6338 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
mbed_official 553:063b9f2f393c 6339 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
mbed_official 553:063b9f2f393c 6340 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
mbed_official 553:063b9f2f393c 6341 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
mbed_official 553:063b9f2f393c 6342 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
mbed_official 553:063b9f2f393c 6343 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
mbed_official 553:063b9f2f393c 6344 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
mbed_official 553:063b9f2f393c 6345 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
mbed_official 553:063b9f2f393c 6346 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 553:063b9f2f393c 6347
mbed_official 553:063b9f2f393c 6348 /******************** Bit definition for SPI_DR register ********************/
mbed_official 553:063b9f2f393c 6349 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
mbed_official 553:063b9f2f393c 6350
mbed_official 553:063b9f2f393c 6351 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 553:063b9f2f393c 6352 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
mbed_official 553:063b9f2f393c 6353
mbed_official 553:063b9f2f393c 6354 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 553:063b9f2f393c 6355 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
mbed_official 553:063b9f2f393c 6356
mbed_official 553:063b9f2f393c 6357 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 553:063b9f2f393c 6358 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
mbed_official 553:063b9f2f393c 6359
mbed_official 553:063b9f2f393c 6360 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 553:063b9f2f393c 6361 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 553:063b9f2f393c 6362
mbed_official 553:063b9f2f393c 6363 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 553:063b9f2f393c 6364 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6365 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6366
mbed_official 553:063b9f2f393c 6367 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 553:063b9f2f393c 6368
mbed_official 553:063b9f2f393c 6369 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 553:063b9f2f393c 6370 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6371 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6372
mbed_official 553:063b9f2f393c 6373 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 553:063b9f2f393c 6374
mbed_official 553:063b9f2f393c 6375 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 553:063b9f2f393c 6376 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6377 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6378
mbed_official 553:063b9f2f393c 6379 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 553:063b9f2f393c 6380 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 553:063b9f2f393c 6381 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
mbed_official 553:063b9f2f393c 6382
mbed_official 553:063b9f2f393c 6383 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 553:063b9f2f393c 6384 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 553:063b9f2f393c 6385 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 553:063b9f2f393c 6386 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 553:063b9f2f393c 6387
mbed_official 553:063b9f2f393c 6388 /******************************************************************************/
mbed_official 553:063b9f2f393c 6389 /* */
mbed_official 553:063b9f2f393c 6390 /* SYSCFG */
mbed_official 553:063b9f2f393c 6391 /* */
mbed_official 553:063b9f2f393c 6392 /******************************************************************************/
mbed_official 553:063b9f2f393c 6393 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
mbed_official 553:063b9f2f393c 6394 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
mbed_official 553:063b9f2f393c 6395 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 6396 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 6397 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 6398
mbed_official 553:063b9f2f393c 6399 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
mbed_official 553:063b9f2f393c 6400 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
mbed_official 553:063b9f2f393c 6401
mbed_official 553:063b9f2f393c 6402 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 553:063b9f2f393c 6403 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 553:063b9f2f393c 6404 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 553:063b9f2f393c 6405 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 553:063b9f2f393c 6406 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 553:063b9f2f393c 6407
mbed_official 553:063b9f2f393c 6408 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 553:063b9f2f393c 6409 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
mbed_official 553:063b9f2f393c 6410 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
mbed_official 553:063b9f2f393c 6411 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
mbed_official 553:063b9f2f393c 6412 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
mbed_official 553:063b9f2f393c 6413 /**
mbed_official 553:063b9f2f393c 6414 * @brief EXTI0 configuration
mbed_official 553:063b9f2f393c 6415 */
mbed_official 553:063b9f2f393c 6416 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
mbed_official 553:063b9f2f393c 6417 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
mbed_official 553:063b9f2f393c 6418 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
mbed_official 553:063b9f2f393c 6419 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
mbed_official 553:063b9f2f393c 6420 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
mbed_official 553:063b9f2f393c 6421 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
mbed_official 553:063b9f2f393c 6422 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
mbed_official 553:063b9f2f393c 6423 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
mbed_official 553:063b9f2f393c 6424 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
mbed_official 553:063b9f2f393c 6425 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
mbed_official 553:063b9f2f393c 6426 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
mbed_official 553:063b9f2f393c 6427
mbed_official 553:063b9f2f393c 6428 /**
mbed_official 553:063b9f2f393c 6429 * @brief EXTI1 configuration
mbed_official 553:063b9f2f393c 6430 */
mbed_official 553:063b9f2f393c 6431 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
mbed_official 553:063b9f2f393c 6432 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
mbed_official 553:063b9f2f393c 6433 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
mbed_official 553:063b9f2f393c 6434 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
mbed_official 553:063b9f2f393c 6435 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
mbed_official 553:063b9f2f393c 6436 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
mbed_official 553:063b9f2f393c 6437 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
mbed_official 553:063b9f2f393c 6438 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
mbed_official 553:063b9f2f393c 6439 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
mbed_official 553:063b9f2f393c 6440 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
mbed_official 553:063b9f2f393c 6441 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
mbed_official 553:063b9f2f393c 6442
mbed_official 553:063b9f2f393c 6443
mbed_official 553:063b9f2f393c 6444 /**
mbed_official 553:063b9f2f393c 6445 * @brief EXTI2 configuration
mbed_official 553:063b9f2f393c 6446 */
mbed_official 553:063b9f2f393c 6447 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
mbed_official 553:063b9f2f393c 6448 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
mbed_official 553:063b9f2f393c 6449 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
mbed_official 553:063b9f2f393c 6450 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
mbed_official 553:063b9f2f393c 6451 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
mbed_official 553:063b9f2f393c 6452 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
mbed_official 553:063b9f2f393c 6453 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
mbed_official 553:063b9f2f393c 6454 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
mbed_official 553:063b9f2f393c 6455 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
mbed_official 553:063b9f2f393c 6456 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
mbed_official 553:063b9f2f393c 6457 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
mbed_official 553:063b9f2f393c 6458
mbed_official 553:063b9f2f393c 6459
mbed_official 553:063b9f2f393c 6460 /**
mbed_official 553:063b9f2f393c 6461 * @brief EXTI3 configuration
mbed_official 553:063b9f2f393c 6462 */
mbed_official 553:063b9f2f393c 6463 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
mbed_official 553:063b9f2f393c 6464 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
mbed_official 553:063b9f2f393c 6465 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
mbed_official 553:063b9f2f393c 6466 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
mbed_official 553:063b9f2f393c 6467 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
mbed_official 553:063b9f2f393c 6468 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
mbed_official 553:063b9f2f393c 6469 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
mbed_official 553:063b9f2f393c 6470 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
mbed_official 553:063b9f2f393c 6471 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
mbed_official 553:063b9f2f393c 6472 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
mbed_official 553:063b9f2f393c 6473 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
mbed_official 553:063b9f2f393c 6474
mbed_official 553:063b9f2f393c 6475
mbed_official 553:063b9f2f393c 6476 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 553:063b9f2f393c 6477 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
mbed_official 553:063b9f2f393c 6478 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
mbed_official 553:063b9f2f393c 6479 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
mbed_official 553:063b9f2f393c 6480 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
mbed_official 553:063b9f2f393c 6481 /**
mbed_official 553:063b9f2f393c 6482 * @brief EXTI4 configuration
mbed_official 553:063b9f2f393c 6483 */
mbed_official 553:063b9f2f393c 6484 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
mbed_official 553:063b9f2f393c 6485 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
mbed_official 553:063b9f2f393c 6486 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
mbed_official 553:063b9f2f393c 6487 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
mbed_official 553:063b9f2f393c 6488 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
mbed_official 553:063b9f2f393c 6489 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
mbed_official 553:063b9f2f393c 6490 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
mbed_official 553:063b9f2f393c 6491 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
mbed_official 553:063b9f2f393c 6492 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
mbed_official 553:063b9f2f393c 6493 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
mbed_official 553:063b9f2f393c 6494 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
mbed_official 553:063b9f2f393c 6495
mbed_official 553:063b9f2f393c 6496 /**
mbed_official 553:063b9f2f393c 6497 * @brief EXTI5 configuration
mbed_official 553:063b9f2f393c 6498 */
mbed_official 553:063b9f2f393c 6499 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
mbed_official 553:063b9f2f393c 6500 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
mbed_official 553:063b9f2f393c 6501 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
mbed_official 553:063b9f2f393c 6502 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
mbed_official 553:063b9f2f393c 6503 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
mbed_official 553:063b9f2f393c 6504 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
mbed_official 553:063b9f2f393c 6505 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
mbed_official 553:063b9f2f393c 6506 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
mbed_official 553:063b9f2f393c 6507 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
mbed_official 553:063b9f2f393c 6508 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
mbed_official 553:063b9f2f393c 6509 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
mbed_official 553:063b9f2f393c 6510
mbed_official 553:063b9f2f393c 6511 /**
mbed_official 553:063b9f2f393c 6512 * @brief EXTI6 configuration
mbed_official 553:063b9f2f393c 6513 */
mbed_official 553:063b9f2f393c 6514 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
mbed_official 553:063b9f2f393c 6515 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
mbed_official 553:063b9f2f393c 6516 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
mbed_official 553:063b9f2f393c 6517 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
mbed_official 553:063b9f2f393c 6518 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
mbed_official 553:063b9f2f393c 6519 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
mbed_official 553:063b9f2f393c 6520 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
mbed_official 553:063b9f2f393c 6521 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
mbed_official 553:063b9f2f393c 6522 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
mbed_official 553:063b9f2f393c 6523 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
mbed_official 553:063b9f2f393c 6524 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
mbed_official 553:063b9f2f393c 6525
mbed_official 553:063b9f2f393c 6526
mbed_official 553:063b9f2f393c 6527 /**
mbed_official 553:063b9f2f393c 6528 * @brief EXTI7 configuration
mbed_official 553:063b9f2f393c 6529 */
mbed_official 553:063b9f2f393c 6530 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
mbed_official 553:063b9f2f393c 6531 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
mbed_official 553:063b9f2f393c 6532 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
mbed_official 553:063b9f2f393c 6533 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
mbed_official 553:063b9f2f393c 6534 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
mbed_official 553:063b9f2f393c 6535 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
mbed_official 553:063b9f2f393c 6536 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
mbed_official 553:063b9f2f393c 6537 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
mbed_official 553:063b9f2f393c 6538 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
mbed_official 553:063b9f2f393c 6539 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
mbed_official 553:063b9f2f393c 6540 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
mbed_official 553:063b9f2f393c 6541
mbed_official 553:063b9f2f393c 6542 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 553:063b9f2f393c 6543 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
mbed_official 553:063b9f2f393c 6544 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
mbed_official 553:063b9f2f393c 6545 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
mbed_official 553:063b9f2f393c 6546 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
mbed_official 553:063b9f2f393c 6547
mbed_official 553:063b9f2f393c 6548 /**
mbed_official 553:063b9f2f393c 6549 * @brief EXTI8 configuration
mbed_official 553:063b9f2f393c 6550 */
mbed_official 553:063b9f2f393c 6551 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
mbed_official 553:063b9f2f393c 6552 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
mbed_official 553:063b9f2f393c 6553 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
mbed_official 553:063b9f2f393c 6554 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
mbed_official 553:063b9f2f393c 6555 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
mbed_official 553:063b9f2f393c 6556 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
mbed_official 553:063b9f2f393c 6557 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
mbed_official 553:063b9f2f393c 6558 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
mbed_official 553:063b9f2f393c 6559 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
mbed_official 553:063b9f2f393c 6560 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
mbed_official 553:063b9f2f393c 6561
mbed_official 553:063b9f2f393c 6562 /**
mbed_official 553:063b9f2f393c 6563 * @brief EXTI9 configuration
mbed_official 553:063b9f2f393c 6564 */
mbed_official 553:063b9f2f393c 6565 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
mbed_official 553:063b9f2f393c 6566 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
mbed_official 553:063b9f2f393c 6567 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
mbed_official 553:063b9f2f393c 6568 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
mbed_official 553:063b9f2f393c 6569 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
mbed_official 553:063b9f2f393c 6570 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
mbed_official 553:063b9f2f393c 6571 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
mbed_official 553:063b9f2f393c 6572 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
mbed_official 553:063b9f2f393c 6573 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
mbed_official 553:063b9f2f393c 6574 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
mbed_official 553:063b9f2f393c 6575
mbed_official 553:063b9f2f393c 6576
mbed_official 553:063b9f2f393c 6577 /**
mbed_official 553:063b9f2f393c 6578 * @brief EXTI10 configuration
mbed_official 553:063b9f2f393c 6579 */
mbed_official 553:063b9f2f393c 6580 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
mbed_official 553:063b9f2f393c 6581 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
mbed_official 553:063b9f2f393c 6582 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
mbed_official 553:063b9f2f393c 6583 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
mbed_official 553:063b9f2f393c 6584 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
mbed_official 553:063b9f2f393c 6585 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
mbed_official 553:063b9f2f393c 6586 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
mbed_official 553:063b9f2f393c 6587 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
mbed_official 553:063b9f2f393c 6588 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
mbed_official 553:063b9f2f393c 6589 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
mbed_official 553:063b9f2f393c 6590
mbed_official 553:063b9f2f393c 6591
mbed_official 553:063b9f2f393c 6592 /**
mbed_official 553:063b9f2f393c 6593 * @brief EXTI11 configuration
mbed_official 553:063b9f2f393c 6594 */
mbed_official 553:063b9f2f393c 6595 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
mbed_official 553:063b9f2f393c 6596 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
mbed_official 553:063b9f2f393c 6597 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
mbed_official 553:063b9f2f393c 6598 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
mbed_official 553:063b9f2f393c 6599 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
mbed_official 553:063b9f2f393c 6600 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
mbed_official 553:063b9f2f393c 6601 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
mbed_official 553:063b9f2f393c 6602 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
mbed_official 553:063b9f2f393c 6603 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
mbed_official 553:063b9f2f393c 6604 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
mbed_official 553:063b9f2f393c 6605
mbed_official 553:063b9f2f393c 6606
mbed_official 553:063b9f2f393c 6607 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official 553:063b9f2f393c 6608 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
mbed_official 553:063b9f2f393c 6609 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
mbed_official 553:063b9f2f393c 6610 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
mbed_official 553:063b9f2f393c 6611 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
mbed_official 553:063b9f2f393c 6612 /**
mbed_official 553:063b9f2f393c 6613 * @brief EXTI12 configuration
mbed_official 553:063b9f2f393c 6614 */
mbed_official 553:063b9f2f393c 6615 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
mbed_official 553:063b9f2f393c 6616 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
mbed_official 553:063b9f2f393c 6617 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
mbed_official 553:063b9f2f393c 6618 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
mbed_official 553:063b9f2f393c 6619 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
mbed_official 553:063b9f2f393c 6620 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
mbed_official 553:063b9f2f393c 6621 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
mbed_official 553:063b9f2f393c 6622 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
mbed_official 553:063b9f2f393c 6623 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
mbed_official 553:063b9f2f393c 6624 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
mbed_official 553:063b9f2f393c 6625
mbed_official 553:063b9f2f393c 6626
mbed_official 553:063b9f2f393c 6627 /**
mbed_official 553:063b9f2f393c 6628 * @brief EXTI13 configuration
mbed_official 553:063b9f2f393c 6629 */
mbed_official 553:063b9f2f393c 6630 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
mbed_official 553:063b9f2f393c 6631 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
mbed_official 553:063b9f2f393c 6632 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
mbed_official 553:063b9f2f393c 6633 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
mbed_official 553:063b9f2f393c 6634 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
mbed_official 553:063b9f2f393c 6635 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
mbed_official 553:063b9f2f393c 6636 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
mbed_official 553:063b9f2f393c 6637 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
mbed_official 553:063b9f2f393c 6638 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
mbed_official 553:063b9f2f393c 6639 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
mbed_official 553:063b9f2f393c 6640
mbed_official 553:063b9f2f393c 6641
mbed_official 553:063b9f2f393c 6642 /**
mbed_official 553:063b9f2f393c 6643 * @brief EXTI14 configuration
mbed_official 553:063b9f2f393c 6644 */
mbed_official 553:063b9f2f393c 6645 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
mbed_official 553:063b9f2f393c 6646 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
mbed_official 553:063b9f2f393c 6647 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
mbed_official 553:063b9f2f393c 6648 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
mbed_official 553:063b9f2f393c 6649 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
mbed_official 553:063b9f2f393c 6650 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
mbed_official 553:063b9f2f393c 6651 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
mbed_official 553:063b9f2f393c 6652 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
mbed_official 553:063b9f2f393c 6653 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
mbed_official 553:063b9f2f393c 6654 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
mbed_official 553:063b9f2f393c 6655
mbed_official 553:063b9f2f393c 6656
mbed_official 553:063b9f2f393c 6657 /**
mbed_official 553:063b9f2f393c 6658 * @brief EXTI15 configuration
mbed_official 553:063b9f2f393c 6659 */
mbed_official 553:063b9f2f393c 6660 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
mbed_official 553:063b9f2f393c 6661 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
mbed_official 553:063b9f2f393c 6662 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
mbed_official 553:063b9f2f393c 6663 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
mbed_official 553:063b9f2f393c 6664 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
mbed_official 553:063b9f2f393c 6665 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
mbed_official 553:063b9f2f393c 6666 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
mbed_official 553:063b9f2f393c 6667 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
mbed_official 553:063b9f2f393c 6668 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
mbed_official 553:063b9f2f393c 6669 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
mbed_official 553:063b9f2f393c 6670
mbed_official 553:063b9f2f393c 6671 /****************** Bit definition for SYSCFG_CMPCR register ****************/
mbed_official 553:063b9f2f393c 6672 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
mbed_official 553:063b9f2f393c 6673 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
mbed_official 553:063b9f2f393c 6674
mbed_official 553:063b9f2f393c 6675 /****************** Bit definition for SYSCFG_CFGR register ****************/
mbed_official 553:063b9f2f393c 6676 #define SYSCFG_CFGR_FMPI2C1_SCL ((uint32_t)0x00000001) /*!<FM+ drive capability for FMPI2C1_SCL pin */
mbed_official 553:063b9f2f393c 6677 #define SYSCFG_CFGR_FMPI2C1_SDA ((uint32_t)0x00000002) /*!<FM+ drive capability for FMPI2C1_SDA pin */
mbed_official 553:063b9f2f393c 6678
mbed_official 553:063b9f2f393c 6679 /******************************************************************************/
mbed_official 553:063b9f2f393c 6680 /* */
mbed_official 553:063b9f2f393c 6681 /* TIM */
mbed_official 553:063b9f2f393c 6682 /* */
mbed_official 553:063b9f2f393c 6683 /******************************************************************************/
mbed_official 553:063b9f2f393c 6684 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 553:063b9f2f393c 6685 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
mbed_official 553:063b9f2f393c 6686 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
mbed_official 553:063b9f2f393c 6687 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
mbed_official 553:063b9f2f393c 6688 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
mbed_official 553:063b9f2f393c 6689 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
mbed_official 553:063b9f2f393c 6690
mbed_official 553:063b9f2f393c 6691 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 553:063b9f2f393c 6692 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6693 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6694
mbed_official 553:063b9f2f393c 6695 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 553:063b9f2f393c 6696
mbed_official 553:063b9f2f393c 6697 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 553:063b9f2f393c 6698 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6699 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6700
mbed_official 553:063b9f2f393c 6701 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 553:063b9f2f393c 6702 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 553:063b9f2f393c 6703 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 553:063b9f2f393c 6704 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 553:063b9f2f393c 6705
mbed_official 553:063b9f2f393c 6706 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 553:063b9f2f393c 6707 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6708 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6709 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6710
mbed_official 553:063b9f2f393c 6711 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
mbed_official 553:063b9f2f393c 6712 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 553:063b9f2f393c 6713 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 553:063b9f2f393c 6714 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 553:063b9f2f393c 6715 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 553:063b9f2f393c 6716 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 553:063b9f2f393c 6717 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 553:063b9f2f393c 6718 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 553:063b9f2f393c 6719
mbed_official 553:063b9f2f393c 6720 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 553:063b9f2f393c 6721 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 553:063b9f2f393c 6722 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6723 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6724 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6725
mbed_official 553:063b9f2f393c 6726 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 553:063b9f2f393c 6727 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6728 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6729 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6730
mbed_official 553:063b9f2f393c 6731 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
mbed_official 553:063b9f2f393c 6732
mbed_official 553:063b9f2f393c 6733 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 553:063b9f2f393c 6734 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6735 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6736 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6737 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6738
mbed_official 553:063b9f2f393c 6739 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 553:063b9f2f393c 6740 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6741 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6742
mbed_official 553:063b9f2f393c 6743 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
mbed_official 553:063b9f2f393c 6744 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
mbed_official 553:063b9f2f393c 6745
mbed_official 553:063b9f2f393c 6746 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 553:063b9f2f393c 6747 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
mbed_official 553:063b9f2f393c 6748 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 553:063b9f2f393c 6749 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 553:063b9f2f393c 6750 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 553:063b9f2f393c 6751 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 553:063b9f2f393c 6752 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
mbed_official 553:063b9f2f393c 6753 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 553:063b9f2f393c 6754 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
mbed_official 553:063b9f2f393c 6755 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
mbed_official 553:063b9f2f393c 6756 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 553:063b9f2f393c 6757 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 553:063b9f2f393c 6758 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 553:063b9f2f393c 6759 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 553:063b9f2f393c 6760 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
mbed_official 553:063b9f2f393c 6761 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 553:063b9f2f393c 6762
mbed_official 553:063b9f2f393c 6763 /******************** Bit definition for TIM_SR register ********************/
mbed_official 553:063b9f2f393c 6764 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
mbed_official 553:063b9f2f393c 6765 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 553:063b9f2f393c 6766 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 553:063b9f2f393c 6767 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 553:063b9f2f393c 6768 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 553:063b9f2f393c 6769 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
mbed_official 553:063b9f2f393c 6770 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 553:063b9f2f393c 6771 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
mbed_official 553:063b9f2f393c 6772 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 553:063b9f2f393c 6773 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 553:063b9f2f393c 6774 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 553:063b9f2f393c 6775 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 553:063b9f2f393c 6776
mbed_official 553:063b9f2f393c 6777 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 553:063b9f2f393c 6778 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
mbed_official 553:063b9f2f393c 6779 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 553:063b9f2f393c 6780 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 553:063b9f2f393c 6781 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 553:063b9f2f393c 6782 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 553:063b9f2f393c 6783 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 553:063b9f2f393c 6784 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
mbed_official 553:063b9f2f393c 6785 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
mbed_official 553:063b9f2f393c 6786
mbed_official 553:063b9f2f393c 6787 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 553:063b9f2f393c 6788 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 553:063b9f2f393c 6789 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6790 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6791
mbed_official 553:063b9f2f393c 6792 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 553:063b9f2f393c 6793 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 553:063b9f2f393c 6794
mbed_official 553:063b9f2f393c 6795 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 553:063b9f2f393c 6796 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6797 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6798 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6799
mbed_official 553:063b9f2f393c 6800 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 553:063b9f2f393c 6801
mbed_official 553:063b9f2f393c 6802 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 553:063b9f2f393c 6803 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6804 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6805
mbed_official 553:063b9f2f393c 6806 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 553:063b9f2f393c 6807 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 553:063b9f2f393c 6808
mbed_official 553:063b9f2f393c 6809 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 553:063b9f2f393c 6810 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6811 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6812 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6813
mbed_official 553:063b9f2f393c 6814 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 553:063b9f2f393c 6815
mbed_official 553:063b9f2f393c 6816 /*----------------------------------------------------------------------------*/
mbed_official 553:063b9f2f393c 6817
mbed_official 553:063b9f2f393c 6818 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 553:063b9f2f393c 6819 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6820 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6821
mbed_official 553:063b9f2f393c 6822 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 553:063b9f2f393c 6823 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6824 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6825 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6826 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6827
mbed_official 553:063b9f2f393c 6828 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 553:063b9f2f393c 6829 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6830 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6831
mbed_official 553:063b9f2f393c 6832 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 553:063b9f2f393c 6833 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6834 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6835 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6836 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6837
mbed_official 553:063b9f2f393c 6838 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 553:063b9f2f393c 6839 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 553:063b9f2f393c 6840 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6841 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6842
mbed_official 553:063b9f2f393c 6843 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 553:063b9f2f393c 6844 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 553:063b9f2f393c 6845
mbed_official 553:063b9f2f393c 6846 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 553:063b9f2f393c 6847 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6848 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6849 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6850
mbed_official 553:063b9f2f393c 6851 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 553:063b9f2f393c 6852
mbed_official 553:063b9f2f393c 6853 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 553:063b9f2f393c 6854 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6855 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6856
mbed_official 553:063b9f2f393c 6857 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 553:063b9f2f393c 6858 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 553:063b9f2f393c 6859
mbed_official 553:063b9f2f393c 6860 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 553:063b9f2f393c 6861 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6862 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6863 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6864
mbed_official 553:063b9f2f393c 6865 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 553:063b9f2f393c 6866
mbed_official 553:063b9f2f393c 6867 /*----------------------------------------------------------------------------*/
mbed_official 553:063b9f2f393c 6868
mbed_official 553:063b9f2f393c 6869 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 553:063b9f2f393c 6870 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6871 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6872
mbed_official 553:063b9f2f393c 6873 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 553:063b9f2f393c 6874 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6875 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6876 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6877 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6878
mbed_official 553:063b9f2f393c 6879 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 553:063b9f2f393c 6880 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6881 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6882
mbed_official 553:063b9f2f393c 6883 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 553:063b9f2f393c 6884 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6885 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6886 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6887 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6888
mbed_official 553:063b9f2f393c 6889 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 553:063b9f2f393c 6890 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 553:063b9f2f393c 6891 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 553:063b9f2f393c 6892 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 553:063b9f2f393c 6893 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 553:063b9f2f393c 6894 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 553:063b9f2f393c 6895 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 553:063b9f2f393c 6896 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 553:063b9f2f393c 6897 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 553:063b9f2f393c 6898 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 553:063b9f2f393c 6899 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 553:063b9f2f393c 6900 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 553:063b9f2f393c 6901 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 553:063b9f2f393c 6902 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 553:063b9f2f393c 6903 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 553:063b9f2f393c 6904 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 553:063b9f2f393c 6905
mbed_official 553:063b9f2f393c 6906 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 553:063b9f2f393c 6907 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
mbed_official 553:063b9f2f393c 6908
mbed_official 553:063b9f2f393c 6909 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 553:063b9f2f393c 6910 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
mbed_official 553:063b9f2f393c 6911
mbed_official 553:063b9f2f393c 6912 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 553:063b9f2f393c 6913 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 553:063b9f2f393c 6914
mbed_official 553:063b9f2f393c 6915 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 553:063b9f2f393c 6916 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
mbed_official 553:063b9f2f393c 6917
mbed_official 553:063b9f2f393c 6918 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 553:063b9f2f393c 6919 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 553:063b9f2f393c 6920
mbed_official 553:063b9f2f393c 6921 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 553:063b9f2f393c 6922 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 553:063b9f2f393c 6923
mbed_official 553:063b9f2f393c 6924 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 553:063b9f2f393c 6925 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 553:063b9f2f393c 6926
mbed_official 553:063b9f2f393c 6927 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 553:063b9f2f393c 6928 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 553:063b9f2f393c 6929
mbed_official 553:063b9f2f393c 6930 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 553:063b9f2f393c 6931 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 553:063b9f2f393c 6932 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6933 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6934 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6935 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6936 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 6937 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 6938 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 6939 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 6940
mbed_official 553:063b9f2f393c 6941 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 553:063b9f2f393c 6942 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6943 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6944
mbed_official 553:063b9f2f393c 6945 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 553:063b9f2f393c 6946 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 553:063b9f2f393c 6947 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
mbed_official 553:063b9f2f393c 6948 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
mbed_official 553:063b9f2f393c 6949 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
mbed_official 553:063b9f2f393c 6950 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
mbed_official 553:063b9f2f393c 6951
mbed_official 553:063b9f2f393c 6952 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 553:063b9f2f393c 6953 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 553:063b9f2f393c 6954 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6955 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6956 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6957 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6958 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 6959
mbed_official 553:063b9f2f393c 6960 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 553:063b9f2f393c 6961 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6962 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6963 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 6964 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 6965 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 6966
mbed_official 553:063b9f2f393c 6967 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 553:063b9f2f393c 6968 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 553:063b9f2f393c 6969
mbed_official 553:063b9f2f393c 6970 /******************* Bit definition for TIM_OR register *********************/
mbed_official 553:063b9f2f393c 6971 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
mbed_official 553:063b9f2f393c 6972 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6973 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6974 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
mbed_official 553:063b9f2f393c 6975 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 6976 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 6977
mbed_official 553:063b9f2f393c 6978
mbed_official 553:063b9f2f393c 6979 /******************************************************************************/
mbed_official 553:063b9f2f393c 6980 /* */
mbed_official 553:063b9f2f393c 6981 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 553:063b9f2f393c 6982 /* */
mbed_official 553:063b9f2f393c 6983 /******************************************************************************/
mbed_official 553:063b9f2f393c 6984 /******************* Bit definition for USART_SR register *******************/
mbed_official 553:063b9f2f393c 6985 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
mbed_official 553:063b9f2f393c 6986 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
mbed_official 553:063b9f2f393c 6987 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
mbed_official 553:063b9f2f393c 6988 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
mbed_official 553:063b9f2f393c 6989 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
mbed_official 553:063b9f2f393c 6990 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
mbed_official 553:063b9f2f393c 6991 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
mbed_official 553:063b9f2f393c 6992 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
mbed_official 553:063b9f2f393c 6993 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
mbed_official 553:063b9f2f393c 6994 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
mbed_official 553:063b9f2f393c 6995
mbed_official 553:063b9f2f393c 6996 /******************* Bit definition for USART_DR register *******************/
mbed_official 553:063b9f2f393c 6997 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
mbed_official 553:063b9f2f393c 6998
mbed_official 553:063b9f2f393c 6999 /****************** Bit definition for USART_BRR register *******************/
mbed_official 553:063b9f2f393c 7000 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
mbed_official 553:063b9f2f393c 7001 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
mbed_official 553:063b9f2f393c 7002
mbed_official 553:063b9f2f393c 7003 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 553:063b9f2f393c 7004 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
mbed_official 553:063b9f2f393c 7005 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
mbed_official 553:063b9f2f393c 7006 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
mbed_official 553:063b9f2f393c 7007 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
mbed_official 553:063b9f2f393c 7008 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
mbed_official 553:063b9f2f393c 7009 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
mbed_official 553:063b9f2f393c 7010 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
mbed_official 553:063b9f2f393c 7011 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
mbed_official 553:063b9f2f393c 7012 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
mbed_official 553:063b9f2f393c 7013 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
mbed_official 553:063b9f2f393c 7014 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
mbed_official 553:063b9f2f393c 7015 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
mbed_official 553:063b9f2f393c 7016 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
mbed_official 553:063b9f2f393c 7017 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
mbed_official 553:063b9f2f393c 7018 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
mbed_official 553:063b9f2f393c 7019
mbed_official 553:063b9f2f393c 7020 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 553:063b9f2f393c 7021 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
mbed_official 553:063b9f2f393c 7022 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
mbed_official 553:063b9f2f393c 7023 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
mbed_official 553:063b9f2f393c 7024 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
mbed_official 553:063b9f2f393c 7025 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
mbed_official 553:063b9f2f393c 7026 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
mbed_official 553:063b9f2f393c 7027 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
mbed_official 553:063b9f2f393c 7028
mbed_official 553:063b9f2f393c 7029 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
mbed_official 553:063b9f2f393c 7030 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7031 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7032
mbed_official 553:063b9f2f393c 7033 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
mbed_official 553:063b9f2f393c 7034
mbed_official 553:063b9f2f393c 7035 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 553:063b9f2f393c 7036 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
mbed_official 553:063b9f2f393c 7037 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
mbed_official 553:063b9f2f393c 7038 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
mbed_official 553:063b9f2f393c 7039 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
mbed_official 553:063b9f2f393c 7040 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
mbed_official 553:063b9f2f393c 7041 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
mbed_official 553:063b9f2f393c 7042 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
mbed_official 553:063b9f2f393c 7043 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
mbed_official 553:063b9f2f393c 7044 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
mbed_official 553:063b9f2f393c 7045 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
mbed_official 553:063b9f2f393c 7046 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
mbed_official 553:063b9f2f393c 7047 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
mbed_official 553:063b9f2f393c 7048
mbed_official 553:063b9f2f393c 7049 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 553:063b9f2f393c 7050 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
mbed_official 553:063b9f2f393c 7051 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7052 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7053 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7054 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7055 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7056 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7057 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7058 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 7059
mbed_official 553:063b9f2f393c 7060 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
mbed_official 553:063b9f2f393c 7061
mbed_official 553:063b9f2f393c 7062 /******************************************************************************/
mbed_official 553:063b9f2f393c 7063 /* */
mbed_official 553:063b9f2f393c 7064 /* Window WATCHDOG */
mbed_official 553:063b9f2f393c 7065 /* */
mbed_official 553:063b9f2f393c 7066 /******************************************************************************/
mbed_official 553:063b9f2f393c 7067 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 553:063b9f2f393c 7068 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 553:063b9f2f393c 7069 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7070 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7071 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7072 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7073 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7074 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7075 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7076
mbed_official 553:063b9f2f393c 7077 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 553:063b9f2f393c 7078
mbed_official 553:063b9f2f393c 7079 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 553:063b9f2f393c 7080 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 553:063b9f2f393c 7081 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7082 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7083 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7084 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7085 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7086 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7087 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7088
mbed_official 553:063b9f2f393c 7089 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 553:063b9f2f393c 7090 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7091 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7092
mbed_official 553:063b9f2f393c 7093 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 553:063b9f2f393c 7094
mbed_official 553:063b9f2f393c 7095 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 553:063b9f2f393c 7096 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 553:063b9f2f393c 7097
mbed_official 553:063b9f2f393c 7098
mbed_official 553:063b9f2f393c 7099 /******************************************************************************/
mbed_official 553:063b9f2f393c 7100 /* */
mbed_official 553:063b9f2f393c 7101 /* DBG */
mbed_official 553:063b9f2f393c 7102 /* */
mbed_official 553:063b9f2f393c 7103 /******************************************************************************/
mbed_official 553:063b9f2f393c 7104 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 553:063b9f2f393c 7105 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 553:063b9f2f393c 7106 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 553:063b9f2f393c 7107
mbed_official 553:063b9f2f393c 7108 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 553:063b9f2f393c 7109 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 7110 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 7111 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 7112 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 7113
mbed_official 553:063b9f2f393c 7114 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 553:063b9f2f393c 7115 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 553:063b9f2f393c 7116 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 553:063b9f2f393c 7117
mbed_official 553:063b9f2f393c 7118 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 553:063b9f2f393c 7119 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 7120 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 7121 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 553:063b9f2f393c 7122 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
mbed_official 553:063b9f2f393c 7123 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 553:063b9f2f393c 7124 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 553:063b9f2f393c 7125 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
mbed_official 553:063b9f2f393c 7126 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
mbed_official 553:063b9f2f393c 7127 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
mbed_official 553:063b9f2f393c 7128 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 553:063b9f2f393c 7129 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 553:063b9f2f393c 7130 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 553:063b9f2f393c 7131 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 553:063b9f2f393c 7132 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 553:063b9f2f393c 7133 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
mbed_official 553:063b9f2f393c 7134 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 553:063b9f2f393c 7135 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
mbed_official 553:063b9f2f393c 7136 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
mbed_official 553:063b9f2f393c 7137 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
mbed_official 553:063b9f2f393c 7138
mbed_official 553:063b9f2f393c 7139 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 553:063b9f2f393c 7140 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 553:063b9f2f393c 7141 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 553:063b9f2f393c 7142 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
mbed_official 553:063b9f2f393c 7143 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
mbed_official 553:063b9f2f393c 7144 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
mbed_official 553:063b9f2f393c 7145
mbed_official 553:063b9f2f393c 7146
mbed_official 553:063b9f2f393c 7147 /******************************************************************************/
mbed_official 553:063b9f2f393c 7148 /* */
mbed_official 553:063b9f2f393c 7149 /* USB_OTG */
mbed_official 553:063b9f2f393c 7150 /* */
mbed_official 553:063b9f2f393c 7151 /******************************************************************************/
mbed_official 553:063b9f2f393c 7152 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
mbed_official 553:063b9f2f393c 7153 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
mbed_official 553:063b9f2f393c 7154 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
mbed_official 553:063b9f2f393c 7155 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
mbed_official 553:063b9f2f393c 7156 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
mbed_official 553:063b9f2f393c 7157 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
mbed_official 553:063b9f2f393c 7158 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
mbed_official 553:063b9f2f393c 7159 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
mbed_official 553:063b9f2f393c 7160 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
mbed_official 553:063b9f2f393c 7161 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
mbed_official 553:063b9f2f393c 7162 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
mbed_official 553:063b9f2f393c 7163 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
mbed_official 553:063b9f2f393c 7164 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
mbed_official 553:063b9f2f393c 7165 #define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
mbed_official 553:063b9f2f393c 7166 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
mbed_official 553:063b9f2f393c 7167 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
mbed_official 553:063b9f2f393c 7168 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
mbed_official 553:063b9f2f393c 7169 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
mbed_official 553:063b9f2f393c 7170 #define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
mbed_official 553:063b9f2f393c 7171
mbed_official 553:063b9f2f393c 7172 /******************** Bit definition forUSB_OTG_HCFG register ********************/
mbed_official 553:063b9f2f393c 7173
mbed_official 553:063b9f2f393c 7174 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
mbed_official 553:063b9f2f393c 7175 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7176 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7177 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
mbed_official 553:063b9f2f393c 7178
mbed_official 553:063b9f2f393c 7179 /******************** Bit definition forUSB_OTG_DCFG register ********************/
mbed_official 553:063b9f2f393c 7180
mbed_official 553:063b9f2f393c 7181 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
mbed_official 553:063b9f2f393c 7182 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7183 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7184 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
mbed_official 553:063b9f2f393c 7185
mbed_official 553:063b9f2f393c 7186 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
mbed_official 553:063b9f2f393c 7187 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7188 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7189 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7190 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7191 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7192 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7193 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7194
mbed_official 553:063b9f2f393c 7195 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
mbed_official 553:063b9f2f393c 7196 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7197 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7198
mbed_official 553:063b9f2f393c 7199 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
mbed_official 553:063b9f2f393c 7200 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7201 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7202
mbed_official 553:063b9f2f393c 7203 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
mbed_official 553:063b9f2f393c 7204 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
mbed_official 553:063b9f2f393c 7205 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
mbed_official 553:063b9f2f393c 7206 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
mbed_official 553:063b9f2f393c 7207
mbed_official 553:063b9f2f393c 7208 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
mbed_official 553:063b9f2f393c 7209 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
mbed_official 553:063b9f2f393c 7210 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
mbed_official 553:063b9f2f393c 7211 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
mbed_official 553:063b9f2f393c 7212 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
mbed_official 553:063b9f2f393c 7213 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
mbed_official 553:063b9f2f393c 7214 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
mbed_official 553:063b9f2f393c 7215 #define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
mbed_official 553:063b9f2f393c 7216
mbed_official 553:063b9f2f393c 7217 /******************** Bit definition forUSB_OTG_DCTL register ********************/
mbed_official 553:063b9f2f393c 7218 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
mbed_official 553:063b9f2f393c 7219 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
mbed_official 553:063b9f2f393c 7220 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
mbed_official 553:063b9f2f393c 7221 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
mbed_official 553:063b9f2f393c 7222
mbed_official 553:063b9f2f393c 7223 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
mbed_official 553:063b9f2f393c 7224 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7225 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7226 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7227 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
mbed_official 553:063b9f2f393c 7228 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
mbed_official 553:063b9f2f393c 7229 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
mbed_official 553:063b9f2f393c 7230 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
mbed_official 553:063b9f2f393c 7231 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
mbed_official 553:063b9f2f393c 7232
mbed_official 553:063b9f2f393c 7233 /******************** Bit definition forUSB_OTG_HFIR register ********************/
mbed_official 553:063b9f2f393c 7234 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
mbed_official 553:063b9f2f393c 7235
mbed_official 553:063b9f2f393c 7236 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
mbed_official 553:063b9f2f393c 7237 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
mbed_official 553:063b9f2f393c 7238 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
mbed_official 553:063b9f2f393c 7239
mbed_official 553:063b9f2f393c 7240 /******************** Bit definition forUSB_OTG_DSTS register ********************/
mbed_official 553:063b9f2f393c 7241 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
mbed_official 553:063b9f2f393c 7242
mbed_official 553:063b9f2f393c 7243 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
mbed_official 553:063b9f2f393c 7244 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7245 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7246 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
mbed_official 553:063b9f2f393c 7247 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
mbed_official 553:063b9f2f393c 7248
mbed_official 553:063b9f2f393c 7249 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
mbed_official 553:063b9f2f393c 7250 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
mbed_official 553:063b9f2f393c 7251 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
mbed_official 553:063b9f2f393c 7252 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7253 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7254 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7255 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7256 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
mbed_official 553:063b9f2f393c 7257 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
mbed_official 553:063b9f2f393c 7258 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
mbed_official 553:063b9f2f393c 7259
mbed_official 553:063b9f2f393c 7260 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
mbed_official 553:063b9f2f393c 7261
mbed_official 553:063b9f2f393c 7262 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
mbed_official 553:063b9f2f393c 7263 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7264 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7265 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7266 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
mbed_official 553:063b9f2f393c 7267 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
mbed_official 553:063b9f2f393c 7268 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
mbed_official 553:063b9f2f393c 7269 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
mbed_official 553:063b9f2f393c 7270 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7271 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7272 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7273 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7274 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
mbed_official 553:063b9f2f393c 7275 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
mbed_official 553:063b9f2f393c 7276 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
mbed_official 553:063b9f2f393c 7277 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
mbed_official 553:063b9f2f393c 7278 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
mbed_official 553:063b9f2f393c 7279 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
mbed_official 553:063b9f2f393c 7280 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
mbed_official 553:063b9f2f393c 7281 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
mbed_official 553:063b9f2f393c 7282 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
mbed_official 553:063b9f2f393c 7283 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
mbed_official 553:063b9f2f393c 7284 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
mbed_official 553:063b9f2f393c 7285 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
mbed_official 553:063b9f2f393c 7286 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
mbed_official 553:063b9f2f393c 7287
mbed_official 553:063b9f2f393c 7288 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
mbed_official 553:063b9f2f393c 7289 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
mbed_official 553:063b9f2f393c 7290 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
mbed_official 553:063b9f2f393c 7291 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
mbed_official 553:063b9f2f393c 7292 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
mbed_official 553:063b9f2f393c 7293 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
mbed_official 553:063b9f2f393c 7294 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
mbed_official 553:063b9f2f393c 7295 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7296 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7297 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7298 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7299 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7300 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
mbed_official 553:063b9f2f393c 7301 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
mbed_official 553:063b9f2f393c 7302
mbed_official 553:063b9f2f393c 7303 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
mbed_official 553:063b9f2f393c 7304 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 553:063b9f2f393c 7305 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 553:063b9f2f393c 7306 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 553:063b9f2f393c 7307 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 553:063b9f2f393c 7308 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 553:063b9f2f393c 7309 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 553:063b9f2f393c 7310 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 553:063b9f2f393c 7311 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 553:063b9f2f393c 7312
mbed_official 553:063b9f2f393c 7313 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
mbed_official 553:063b9f2f393c 7314 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
mbed_official 553:063b9f2f393c 7315 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
mbed_official 553:063b9f2f393c 7316 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7317 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7318 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7319 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7320 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7321 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7322 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7323 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 7324
mbed_official 553:063b9f2f393c 7325 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
mbed_official 553:063b9f2f393c 7326 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7327 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7328 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7329 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7330 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7331 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7332 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7333 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 7334
mbed_official 553:063b9f2f393c 7335 /******************** Bit definition forUSB_OTG_HAINT register ********************/
mbed_official 553:063b9f2f393c 7336 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
mbed_official 553:063b9f2f393c 7337
mbed_official 553:063b9f2f393c 7338 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
mbed_official 553:063b9f2f393c 7339 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 553:063b9f2f393c 7340 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 553:063b9f2f393c 7341 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
mbed_official 553:063b9f2f393c 7342 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
mbed_official 553:063b9f2f393c 7343 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
mbed_official 553:063b9f2f393c 7344 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 553:063b9f2f393c 7345 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 553:063b9f2f393c 7346
mbed_official 553:063b9f2f393c 7347 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
mbed_official 553:063b9f2f393c 7348 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
mbed_official 553:063b9f2f393c 7349 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
mbed_official 553:063b9f2f393c 7350 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
mbed_official 553:063b9f2f393c 7351 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
mbed_official 553:063b9f2f393c 7352 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
mbed_official 553:063b9f2f393c 7353 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
mbed_official 553:063b9f2f393c 7354 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
mbed_official 553:063b9f2f393c 7355 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
mbed_official 553:063b9f2f393c 7356 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
mbed_official 553:063b9f2f393c 7357 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
mbed_official 553:063b9f2f393c 7358 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
mbed_official 553:063b9f2f393c 7359 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
mbed_official 553:063b9f2f393c 7360 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
mbed_official 553:063b9f2f393c 7361 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
mbed_official 553:063b9f2f393c 7362 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
mbed_official 553:063b9f2f393c 7363 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
mbed_official 553:063b9f2f393c 7364 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
mbed_official 553:063b9f2f393c 7365 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
mbed_official 553:063b9f2f393c 7366 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
mbed_official 553:063b9f2f393c 7367 #define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
mbed_official 553:063b9f2f393c 7368 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
mbed_official 553:063b9f2f393c 7369 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
mbed_official 553:063b9f2f393c 7370 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
mbed_official 553:063b9f2f393c 7371 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
mbed_official 553:063b9f2f393c 7372 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
mbed_official 553:063b9f2f393c 7373 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
mbed_official 553:063b9f2f393c 7374 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
mbed_official 553:063b9f2f393c 7375 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
mbed_official 553:063b9f2f393c 7376
mbed_official 553:063b9f2f393c 7377 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
mbed_official 553:063b9f2f393c 7378 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
mbed_official 553:063b9f2f393c 7379 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
mbed_official 553:063b9f2f393c 7380 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
mbed_official 553:063b9f2f393c 7381 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
mbed_official 553:063b9f2f393c 7382 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
mbed_official 553:063b9f2f393c 7383 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
mbed_official 553:063b9f2f393c 7384 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
mbed_official 553:063b9f2f393c 7385 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
mbed_official 553:063b9f2f393c 7386 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
mbed_official 553:063b9f2f393c 7387 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
mbed_official 553:063b9f2f393c 7388 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
mbed_official 553:063b9f2f393c 7389 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
mbed_official 553:063b9f2f393c 7390 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
mbed_official 553:063b9f2f393c 7391 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
mbed_official 553:063b9f2f393c 7392 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
mbed_official 553:063b9f2f393c 7393 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
mbed_official 553:063b9f2f393c 7394 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
mbed_official 553:063b9f2f393c 7395 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
mbed_official 553:063b9f2f393c 7396 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
mbed_official 553:063b9f2f393c 7397 #define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
mbed_official 553:063b9f2f393c 7398 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
mbed_official 553:063b9f2f393c 7399 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
mbed_official 553:063b9f2f393c 7400 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
mbed_official 553:063b9f2f393c 7401 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
mbed_official 553:063b9f2f393c 7402 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
mbed_official 553:063b9f2f393c 7403 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
mbed_official 553:063b9f2f393c 7404 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
mbed_official 553:063b9f2f393c 7405 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
mbed_official 553:063b9f2f393c 7406
mbed_official 553:063b9f2f393c 7407 /******************** Bit definition forUSB_OTG_DAINT register ********************/
mbed_official 553:063b9f2f393c 7408 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
mbed_official 553:063b9f2f393c 7409 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
mbed_official 553:063b9f2f393c 7410
mbed_official 553:063b9f2f393c 7411 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
mbed_official 553:063b9f2f393c 7412 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
mbed_official 553:063b9f2f393c 7413
mbed_official 553:063b9f2f393c 7414 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
mbed_official 553:063b9f2f393c 7415 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
mbed_official 553:063b9f2f393c 7416 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
mbed_official 553:063b9f2f393c 7417 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
mbed_official 553:063b9f2f393c 7418 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
mbed_official 553:063b9f2f393c 7419
mbed_official 553:063b9f2f393c 7420 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
mbed_official 553:063b9f2f393c 7421 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
mbed_official 553:063b9f2f393c 7422 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
mbed_official 553:063b9f2f393c 7423
mbed_official 553:063b9f2f393c 7424 /******************** Bit definition for OTG register ********************/
mbed_official 553:063b9f2f393c 7425
mbed_official 553:063b9f2f393c 7426 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 553:063b9f2f393c 7427 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7428 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7429 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7430 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7431 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 553:063b9f2f393c 7432
mbed_official 553:063b9f2f393c 7433 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 553:063b9f2f393c 7434 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7435 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7436
mbed_official 553:063b9f2f393c 7437 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 553:063b9f2f393c 7438 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7439 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7440 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7441 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7442
mbed_official 553:063b9f2f393c 7443 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 553:063b9f2f393c 7444 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7445 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7446 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7447 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7448
mbed_official 553:063b9f2f393c 7449 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 553:063b9f2f393c 7450 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7451 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7452 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7453 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7454
mbed_official 553:063b9f2f393c 7455 /******************** Bit definition for OTG register ********************/
mbed_official 553:063b9f2f393c 7456
mbed_official 553:063b9f2f393c 7457 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 553:063b9f2f393c 7458 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7459 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7460 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7461 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7462 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 553:063b9f2f393c 7463
mbed_official 553:063b9f2f393c 7464 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 553:063b9f2f393c 7465 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7466 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7467
mbed_official 553:063b9f2f393c 7468 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 553:063b9f2f393c 7469 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7470 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7471 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7472 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7473
mbed_official 553:063b9f2f393c 7474 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 553:063b9f2f393c 7475 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7476 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7477 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7478 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7479
mbed_official 553:063b9f2f393c 7480 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 553:063b9f2f393c 7481 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7482 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7483 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7484 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7485
mbed_official 553:063b9f2f393c 7486 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
mbed_official 553:063b9f2f393c 7487 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
mbed_official 553:063b9f2f393c 7488
mbed_official 553:063b9f2f393c 7489 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
mbed_official 553:063b9f2f393c 7490 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
mbed_official 553:063b9f2f393c 7491
mbed_official 553:063b9f2f393c 7492 /******************** Bit definition for OTG register ********************/
mbed_official 553:063b9f2f393c 7493 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
mbed_official 553:063b9f2f393c 7494 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
mbed_official 553:063b9f2f393c 7495 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
mbed_official 553:063b9f2f393c 7496 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
mbed_official 553:063b9f2f393c 7497
mbed_official 553:063b9f2f393c 7498 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
mbed_official 553:063b9f2f393c 7499 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
mbed_official 553:063b9f2f393c 7500
mbed_official 553:063b9f2f393c 7501 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
mbed_official 553:063b9f2f393c 7502 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
mbed_official 553:063b9f2f393c 7503
mbed_official 553:063b9f2f393c 7504 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
mbed_official 553:063b9f2f393c 7505 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7506 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7507 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7508 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7509 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7510 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7511 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7512 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 7513
mbed_official 553:063b9f2f393c 7514 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
mbed_official 553:063b9f2f393c 7515 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7516 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7517 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7518 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7519 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7520 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7521 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7522
mbed_official 553:063b9f2f393c 7523 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
mbed_official 553:063b9f2f393c 7524 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
mbed_official 553:063b9f2f393c 7525 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
mbed_official 553:063b9f2f393c 7526
mbed_official 553:063b9f2f393c 7527 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
mbed_official 553:063b9f2f393c 7528 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7529 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7530 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7531 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7532 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7533 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7534 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7535 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 7536 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
mbed_official 553:063b9f2f393c 7537 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
mbed_official 553:063b9f2f393c 7538
mbed_official 553:063b9f2f393c 7539 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
mbed_official 553:063b9f2f393c 7540 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7541 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7542 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7543 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7544 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7545 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7546 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7547 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
mbed_official 553:063b9f2f393c 7548 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
mbed_official 553:063b9f2f393c 7549 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
mbed_official 553:063b9f2f393c 7550
mbed_official 553:063b9f2f393c 7551 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
mbed_official 553:063b9f2f393c 7552 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
mbed_official 553:063b9f2f393c 7553
mbed_official 553:063b9f2f393c 7554 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
mbed_official 553:063b9f2f393c 7555 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
mbed_official 553:063b9f2f393c 7556 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
mbed_official 553:063b9f2f393c 7557
mbed_official 553:063b9f2f393c 7558 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
mbed_official 553:063b9f2f393c 7559 #define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /*!< Data contact detection (DCD) status */
mbed_official 553:063b9f2f393c 7560 #define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /*!< Primary detection (PD) status */
mbed_official 553:063b9f2f393c 7561 #define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /*!< Secondary detection (SD) status */
mbed_official 553:063b9f2f393c 7562 #define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /*!< DM pull-up detection status */
mbed_official 553:063b9f2f393c 7563 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
mbed_official 553:063b9f2f393c 7564 #define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /*!< Battery charging detector (BCD) enable */
mbed_official 553:063b9f2f393c 7565 #define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /*!< Data contact detection (DCD) mode enable*/
mbed_official 553:063b9f2f393c 7566 #define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /*!< Primary detection (PD) mode enable*/
mbed_official 553:063b9f2f393c 7567 #define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /*!< Secondary detection (SD) mode enable */
mbed_official 553:063b9f2f393c 7568 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
mbed_official 553:063b9f2f393c 7569
mbed_official 553:063b9f2f393c 7570 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
mbed_official 553:063b9f2f393c 7571 #define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
mbed_official 553:063b9f2f393c 7572 #define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
mbed_official 553:063b9f2f393c 7573
mbed_official 553:063b9f2f393c 7574 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
mbed_official 553:063b9f2f393c 7575 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
mbed_official 553:063b9f2f393c 7576 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
mbed_official 553:063b9f2f393c 7577
mbed_official 553:063b9f2f393c 7578 /******************** Bit definition forUSB_OTG_CID register ********************/
mbed_official 553:063b9f2f393c 7579 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
mbed_official 553:063b9f2f393c 7580
mbed_official 553:063b9f2f393c 7581 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
mbed_official 553:063b9f2f393c 7582 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
mbed_official 553:063b9f2f393c 7583 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
mbed_official 553:063b9f2f393c 7584 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
mbed_official 553:063b9f2f393c 7585 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
mbed_official 553:063b9f2f393c 7586 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
mbed_official 553:063b9f2f393c 7587 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
mbed_official 553:063b9f2f393c 7588 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
mbed_official 553:063b9f2f393c 7589 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
mbed_official 553:063b9f2f393c 7590 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
mbed_official 553:063b9f2f393c 7591 #define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
mbed_official 553:063b9f2f393c 7592 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
mbed_official 553:063b9f2f393c 7593 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
mbed_official 553:063b9f2f393c 7594 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
mbed_official 553:063b9f2f393c 7595 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
mbed_official 553:063b9f2f393c 7596 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
mbed_official 553:063b9f2f393c 7597
mbed_official 553:063b9f2f393c 7598 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
mbed_official 553:063b9f2f393c 7599 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 553:063b9f2f393c 7600 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 553:063b9f2f393c 7601 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 553:063b9f2f393c 7602 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 553:063b9f2f393c 7603 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 553:063b9f2f393c 7604 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 553:063b9f2f393c 7605 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 553:063b9f2f393c 7606 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 553:063b9f2f393c 7607 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 553:063b9f2f393c 7608
mbed_official 553:063b9f2f393c 7609 /******************** Bit definition forUSB_OTG_HPRT register ********************/
mbed_official 553:063b9f2f393c 7610 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
mbed_official 553:063b9f2f393c 7611 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
mbed_official 553:063b9f2f393c 7612 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
mbed_official 553:063b9f2f393c 7613 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
mbed_official 553:063b9f2f393c 7614 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
mbed_official 553:063b9f2f393c 7615 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
mbed_official 553:063b9f2f393c 7616 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
mbed_official 553:063b9f2f393c 7617 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
mbed_official 553:063b9f2f393c 7618 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
mbed_official 553:063b9f2f393c 7619
mbed_official 553:063b9f2f393c 7620 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
mbed_official 553:063b9f2f393c 7621 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7622 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7623 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
mbed_official 553:063b9f2f393c 7624
mbed_official 553:063b9f2f393c 7625 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
mbed_official 553:063b9f2f393c 7626 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7627 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7628 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7629 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7630
mbed_official 553:063b9f2f393c 7631 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
mbed_official 553:063b9f2f393c 7632 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7633 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7634
mbed_official 553:063b9f2f393c 7635 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
mbed_official 553:063b9f2f393c 7636 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 553:063b9f2f393c 7637 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 553:063b9f2f393c 7638 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
mbed_official 553:063b9f2f393c 7639 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 553:063b9f2f393c 7640 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 553:063b9f2f393c 7641 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 553:063b9f2f393c 7642 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 553:063b9f2f393c 7643 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 553:063b9f2f393c 7644 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
mbed_official 553:063b9f2f393c 7645 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 553:063b9f2f393c 7646 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
mbed_official 553:063b9f2f393c 7647
mbed_official 553:063b9f2f393c 7648 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
mbed_official 553:063b9f2f393c 7649 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
mbed_official 553:063b9f2f393c 7650 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
mbed_official 553:063b9f2f393c 7651
mbed_official 553:063b9f2f393c 7652 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
mbed_official 553:063b9f2f393c 7653 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 553:063b9f2f393c 7654 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 553:063b9f2f393c 7655 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
mbed_official 553:063b9f2f393c 7656 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 553:063b9f2f393c 7657
mbed_official 553:063b9f2f393c 7658 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 553:063b9f2f393c 7659 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7660 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7661 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 553:063b9f2f393c 7662
mbed_official 553:063b9f2f393c 7663 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
mbed_official 553:063b9f2f393c 7664 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7665 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7666 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7667 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7668 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 553:063b9f2f393c 7669 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 553:063b9f2f393c 7670 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 553:063b9f2f393c 7671 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 553:063b9f2f393c 7672 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 553:063b9f2f393c 7673 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 553:063b9f2f393c 7674
mbed_official 553:063b9f2f393c 7675 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
mbed_official 553:063b9f2f393c 7676 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 553:063b9f2f393c 7677
mbed_official 553:063b9f2f393c 7678 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
mbed_official 553:063b9f2f393c 7679 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7680 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7681 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7682 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7683 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
mbed_official 553:063b9f2f393c 7684 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
mbed_official 553:063b9f2f393c 7685
mbed_official 553:063b9f2f393c 7686 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 553:063b9f2f393c 7687 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7688 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7689
mbed_official 553:063b9f2f393c 7690 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
mbed_official 553:063b9f2f393c 7691 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7692 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7693
mbed_official 553:063b9f2f393c 7694 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
mbed_official 553:063b9f2f393c 7695 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7696 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7697 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7698 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7699 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7700 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7701 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7702 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
mbed_official 553:063b9f2f393c 7703 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
mbed_official 553:063b9f2f393c 7704 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
mbed_official 553:063b9f2f393c 7705
mbed_official 553:063b9f2f393c 7706 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
mbed_official 553:063b9f2f393c 7707
mbed_official 553:063b9f2f393c 7708 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
mbed_official 553:063b9f2f393c 7709 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7710 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7711 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7712 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7713 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7714 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7715 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7716
mbed_official 553:063b9f2f393c 7717 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
mbed_official 553:063b9f2f393c 7718 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7719 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7720 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 553:063b9f2f393c 7721 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 553:063b9f2f393c 7722 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 553:063b9f2f393c 7723 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 553:063b9f2f393c 7724 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
mbed_official 553:063b9f2f393c 7725
mbed_official 553:063b9f2f393c 7726 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
mbed_official 553:063b9f2f393c 7727 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7728 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7729 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
mbed_official 553:063b9f2f393c 7730 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
mbed_official 553:063b9f2f393c 7731
mbed_official 553:063b9f2f393c 7732 /******************** Bit definition forUSB_OTG_HCINT register ********************/
mbed_official 553:063b9f2f393c 7733 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
mbed_official 553:063b9f2f393c 7734 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
mbed_official 553:063b9f2f393c 7735 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 553:063b9f2f393c 7736 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
mbed_official 553:063b9f2f393c 7737 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
mbed_official 553:063b9f2f393c 7738 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
mbed_official 553:063b9f2f393c 7739 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
mbed_official 553:063b9f2f393c 7740 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
mbed_official 553:063b9f2f393c 7741 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
mbed_official 553:063b9f2f393c 7742 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
mbed_official 553:063b9f2f393c 7743 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
mbed_official 553:063b9f2f393c 7744
mbed_official 553:063b9f2f393c 7745 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
mbed_official 553:063b9f2f393c 7746 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 553:063b9f2f393c 7747 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 553:063b9f2f393c 7748 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
mbed_official 553:063b9f2f393c 7749 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
mbed_official 553:063b9f2f393c 7750 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
mbed_official 553:063b9f2f393c 7751 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
mbed_official 553:063b9f2f393c 7752 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
mbed_official 553:063b9f2f393c 7753 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
mbed_official 553:063b9f2f393c 7754 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
mbed_official 553:063b9f2f393c 7755 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
mbed_official 553:063b9f2f393c 7756 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
mbed_official 553:063b9f2f393c 7757
mbed_official 553:063b9f2f393c 7758 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
mbed_official 553:063b9f2f393c 7759 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
mbed_official 553:063b9f2f393c 7760 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
mbed_official 553:063b9f2f393c 7761 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 553:063b9f2f393c 7762 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
mbed_official 553:063b9f2f393c 7763 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
mbed_official 553:063b9f2f393c 7764 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
mbed_official 553:063b9f2f393c 7765 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
mbed_official 553:063b9f2f393c 7766 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
mbed_official 553:063b9f2f393c 7767 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
mbed_official 553:063b9f2f393c 7768 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
mbed_official 553:063b9f2f393c 7769 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
mbed_official 553:063b9f2f393c 7770
mbed_official 553:063b9f2f393c 7771 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
mbed_official 553:063b9f2f393c 7772
mbed_official 553:063b9f2f393c 7773 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 553:063b9f2f393c 7774 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 553:063b9f2f393c 7775 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
mbed_official 553:063b9f2f393c 7776 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
mbed_official 553:063b9f2f393c 7777 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 553:063b9f2f393c 7778 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 553:063b9f2f393c 7779 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
mbed_official 553:063b9f2f393c 7780 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
mbed_official 553:063b9f2f393c 7781 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7782 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7783
mbed_official 553:063b9f2f393c 7784 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
mbed_official 553:063b9f2f393c 7785 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 553:063b9f2f393c 7786
mbed_official 553:063b9f2f393c 7787 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
mbed_official 553:063b9f2f393c 7788 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 553:063b9f2f393c 7789
mbed_official 553:063b9f2f393c 7790 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
mbed_official 553:063b9f2f393c 7791 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
mbed_official 553:063b9f2f393c 7792
mbed_official 553:063b9f2f393c 7793 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
mbed_official 553:063b9f2f393c 7794 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
mbed_official 553:063b9f2f393c 7795 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
mbed_official 553:063b9f2f393c 7796
mbed_official 553:063b9f2f393c 7797 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
mbed_official 553:063b9f2f393c 7798
mbed_official 553:063b9f2f393c 7799 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7800 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 553:063b9f2f393c 7801 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 553:063b9f2f393c 7802 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 553:063b9f2f393c 7803 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 553:063b9f2f393c 7804 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 553:063b9f2f393c 7805 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7806 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7807 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
mbed_official 553:063b9f2f393c 7808 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 553:063b9f2f393c 7809 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 553:063b9f2f393c 7810 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 553:063b9f2f393c 7811 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 553:063b9f2f393c 7812 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 553:063b9f2f393c 7813
mbed_official 553:063b9f2f393c 7814 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
mbed_official 553:063b9f2f393c 7815 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 553:063b9f2f393c 7816 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 553:063b9f2f393c 7817 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
mbed_official 553:063b9f2f393c 7818 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
mbed_official 553:063b9f2f393c 7819 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
mbed_official 553:063b9f2f393c 7820 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
mbed_official 553:063b9f2f393c 7821
mbed_official 553:063b9f2f393c 7822 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
mbed_official 553:063b9f2f393c 7823
mbed_official 553:063b9f2f393c 7824 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 553:063b9f2f393c 7825 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 553:063b9f2f393c 7826
mbed_official 553:063b9f2f393c 7827 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
mbed_official 553:063b9f2f393c 7828 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7829 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7830
mbed_official 553:063b9f2f393c 7831 /******************** Bit definition for PCGCCTL register ********************/
mbed_official 553:063b9f2f393c 7832 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
mbed_official 553:063b9f2f393c 7833 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 553:063b9f2f393c 7834 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 553:063b9f2f393c 7835
mbed_official 553:063b9f2f393c 7836
mbed_official 553:063b9f2f393c 7837 /**
mbed_official 553:063b9f2f393c 7838 * @}
mbed_official 553:063b9f2f393c 7839 */
mbed_official 553:063b9f2f393c 7840
mbed_official 553:063b9f2f393c 7841 /**
mbed_official 553:063b9f2f393c 7842 * @}
mbed_official 553:063b9f2f393c 7843 */
mbed_official 553:063b9f2f393c 7844
mbed_official 553:063b9f2f393c 7845 /** @addtogroup Exported_macros
mbed_official 553:063b9f2f393c 7846 * @{
mbed_official 553:063b9f2f393c 7847 */
mbed_official 553:063b9f2f393c 7848
mbed_official 553:063b9f2f393c 7849 /******************************* ADC Instances ********************************/
mbed_official 553:063b9f2f393c 7850 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 553:063b9f2f393c 7851 ((INSTANCE) == ADC2) || \
mbed_official 553:063b9f2f393c 7852 ((INSTANCE) == ADC3))
mbed_official 553:063b9f2f393c 7853
mbed_official 553:063b9f2f393c 7854 /******************************* CAN Instances ********************************/
mbed_official 553:063b9f2f393c 7855 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
mbed_official 553:063b9f2f393c 7856 ((INSTANCE) == CAN2))
mbed_official 553:063b9f2f393c 7857
mbed_official 553:063b9f2f393c 7858 /******************************* CRC Instances ********************************/
mbed_official 553:063b9f2f393c 7859 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 553:063b9f2f393c 7860
mbed_official 553:063b9f2f393c 7861 /******************************* DAC Instances ********************************/
mbed_official 553:063b9f2f393c 7862 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 553:063b9f2f393c 7863
mbed_official 553:063b9f2f393c 7864 /******************************* DCMI Instances *******************************/
mbed_official 553:063b9f2f393c 7865 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
mbed_official 553:063b9f2f393c 7866
mbed_official 553:063b9f2f393c 7867 /******************************** DMA Instances *******************************/
mbed_official 553:063b9f2f393c 7868 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
mbed_official 553:063b9f2f393c 7869 ((INSTANCE) == DMA1_Stream1) || \
mbed_official 553:063b9f2f393c 7870 ((INSTANCE) == DMA1_Stream2) || \
mbed_official 553:063b9f2f393c 7871 ((INSTANCE) == DMA1_Stream3) || \
mbed_official 553:063b9f2f393c 7872 ((INSTANCE) == DMA1_Stream4) || \
mbed_official 553:063b9f2f393c 7873 ((INSTANCE) == DMA1_Stream5) || \
mbed_official 553:063b9f2f393c 7874 ((INSTANCE) == DMA1_Stream6) || \
mbed_official 553:063b9f2f393c 7875 ((INSTANCE) == DMA1_Stream7) || \
mbed_official 553:063b9f2f393c 7876 ((INSTANCE) == DMA2_Stream0) || \
mbed_official 553:063b9f2f393c 7877 ((INSTANCE) == DMA2_Stream1) || \
mbed_official 553:063b9f2f393c 7878 ((INSTANCE) == DMA2_Stream2) || \
mbed_official 553:063b9f2f393c 7879 ((INSTANCE) == DMA2_Stream3) || \
mbed_official 553:063b9f2f393c 7880 ((INSTANCE) == DMA2_Stream4) || \
mbed_official 553:063b9f2f393c 7881 ((INSTANCE) == DMA2_Stream5) || \
mbed_official 553:063b9f2f393c 7882 ((INSTANCE) == DMA2_Stream6) || \
mbed_official 553:063b9f2f393c 7883 ((INSTANCE) == DMA2_Stream7))
mbed_official 553:063b9f2f393c 7884
mbed_official 553:063b9f2f393c 7885 /******************************* GPIO Instances *******************************/
mbed_official 553:063b9f2f393c 7886 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 553:063b9f2f393c 7887 ((INSTANCE) == GPIOB) || \
mbed_official 553:063b9f2f393c 7888 ((INSTANCE) == GPIOC) || \
mbed_official 553:063b9f2f393c 7889 ((INSTANCE) == GPIOD) || \
mbed_official 553:063b9f2f393c 7890 ((INSTANCE) == GPIOE) || \
mbed_official 553:063b9f2f393c 7891 ((INSTANCE) == GPIOF) || \
mbed_official 553:063b9f2f393c 7892 ((INSTANCE) == GPIOG) || \
mbed_official 553:063b9f2f393c 7893 ((INSTANCE) == GPIOH))
mbed_official 553:063b9f2f393c 7894
mbed_official 553:063b9f2f393c 7895 /******************************** I2C Instances *******************************/
mbed_official 553:063b9f2f393c 7896 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 553:063b9f2f393c 7897 ((INSTANCE) == I2C2) || \
mbed_official 553:063b9f2f393c 7898 ((INSTANCE) == I2C3))
mbed_official 553:063b9f2f393c 7899
mbed_official 553:063b9f2f393c 7900 /******************************** I2S Instances *******************************/
mbed_official 553:063b9f2f393c 7901 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 553:063b9f2f393c 7902 ((INSTANCE) == SPI2) || \
mbed_official 553:063b9f2f393c 7903 ((INSTANCE) == SPI3))
mbed_official 553:063b9f2f393c 7904
mbed_official 553:063b9f2f393c 7905 /****************************** RTC Instances *********************************/
mbed_official 553:063b9f2f393c 7906 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 553:063b9f2f393c 7907
mbed_official 553:063b9f2f393c 7908 /******************************* SAI Instances ********************************/
mbed_official 553:063b9f2f393c 7909 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
mbed_official 553:063b9f2f393c 7910 ((PERIPH) == SAI1_Block_B) || \
mbed_official 553:063b9f2f393c 7911 ((PERIPH) == SAI2_Block_A) || \
mbed_official 553:063b9f2f393c 7912 ((PERIPH) == SAI2_Block_B))
mbed_official 553:063b9f2f393c 7913
mbed_official 553:063b9f2f393c 7914 /******************************** SPI Instances *******************************/
mbed_official 553:063b9f2f393c 7915 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 553:063b9f2f393c 7916 ((INSTANCE) == SPI2) || \
mbed_official 553:063b9f2f393c 7917 ((INSTANCE) == SPI3) || \
mbed_official 553:063b9f2f393c 7918 ((INSTANCE) == SPI4))
mbed_official 553:063b9f2f393c 7919
mbed_official 553:063b9f2f393c 7920 /****************** TIM Instances : All supported instances *******************/
mbed_official 553:063b9f2f393c 7921 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7922 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 7923 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 7924 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 7925 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 7926 ((INSTANCE) == TIM6) || \
mbed_official 553:063b9f2f393c 7927 ((INSTANCE) == TIM7) || \
mbed_official 553:063b9f2f393c 7928 ((INSTANCE) == TIM8) || \
mbed_official 553:063b9f2f393c 7929 ((INSTANCE) == TIM9) || \
mbed_official 553:063b9f2f393c 7930 ((INSTANCE) == TIM10) || \
mbed_official 553:063b9f2f393c 7931 ((INSTANCE) == TIM11) || \
mbed_official 553:063b9f2f393c 7932 ((INSTANCE) == TIM12) || \
mbed_official 553:063b9f2f393c 7933 ((INSTANCE) == TIM13) || \
mbed_official 553:063b9f2f393c 7934 ((INSTANCE) == TIM14))
mbed_official 553:063b9f2f393c 7935
mbed_official 553:063b9f2f393c 7936 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 553:063b9f2f393c 7937 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7938 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 7939 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 7940 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 7941 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 7942 ((INSTANCE) == TIM8) || \
mbed_official 553:063b9f2f393c 7943 ((INSTANCE) == TIM9) || \
mbed_official 553:063b9f2f393c 7944 ((INSTANCE) == TIM10) || \
mbed_official 553:063b9f2f393c 7945 ((INSTANCE) == TIM11) || \
mbed_official 553:063b9f2f393c 7946 ((INSTANCE) == TIM12) || \
mbed_official 553:063b9f2f393c 7947 ((INSTANCE) == TIM13) || \
mbed_official 553:063b9f2f393c 7948 ((INSTANCE) == TIM14))
mbed_official 553:063b9f2f393c 7949
mbed_official 553:063b9f2f393c 7950 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 553:063b9f2f393c 7951 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7952 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 7953 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 7954 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 7955 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 7956 ((INSTANCE) == TIM8) || \
mbed_official 553:063b9f2f393c 7957 ((INSTANCE) == TIM9) || \
mbed_official 553:063b9f2f393c 7958 ((INSTANCE) == TIM12))
mbed_official 553:063b9f2f393c 7959
mbed_official 553:063b9f2f393c 7960 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 553:063b9f2f393c 7961 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7962 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 7963 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 7964 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 7965 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 7966 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 7967
mbed_official 553:063b9f2f393c 7968 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 553:063b9f2f393c 7969 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7970 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 7971 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 7972 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 7973 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 7974 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 7975
mbed_official 553:063b9f2f393c 7976 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 553:063b9f2f393c 7977 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7978 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 7979
mbed_official 553:063b9f2f393c 7980 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 553:063b9f2f393c 7981 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7982 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 7983 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 7984 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 7985 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 7986 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 7987
mbed_official 553:063b9f2f393c 7988 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 553:063b9f2f393c 7989 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 7990 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 7991 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 7992 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 7993 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 7994 ((INSTANCE) == TIM6) || \
mbed_official 553:063b9f2f393c 7995 ((INSTANCE) == TIM7) || \
mbed_official 553:063b9f2f393c 7996 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 7997
mbed_official 553:063b9f2f393c 7998 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 553:063b9f2f393c 7999 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 8000 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8001 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 8002 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 8003 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 8004 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 8005
mbed_official 553:063b9f2f393c 8006 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 553:063b9f2f393c 8007 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 8008 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8009 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 8010 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 8011 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 8012 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 8013
mbed_official 553:063b9f2f393c 8014 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 553:063b9f2f393c 8015 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 8016 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8017 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 8018 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 8019 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 8020 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 8021
mbed_official 553:063b9f2f393c 8022 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 553:063b9f2f393c 8023 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 8024 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8025 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 8026 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 8027 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 8028 ((INSTANCE) == TIM6) || \
mbed_official 553:063b9f2f393c 8029 ((INSTANCE) == TIM7) || \
mbed_official 553:063b9f2f393c 8030 ((INSTANCE) == TIM8) || \
mbed_official 553:063b9f2f393c 8031 ((INSTANCE) == TIM9) || \
mbed_official 553:063b9f2f393c 8032 ((INSTANCE) == TIM12))
mbed_official 553:063b9f2f393c 8033
mbed_official 553:063b9f2f393c 8034 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 553:063b9f2f393c 8035 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 8036 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8037 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 8038 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 8039 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 8040 ((INSTANCE) == TIM8) || \
mbed_official 553:063b9f2f393c 8041 ((INSTANCE) == TIM9) || \
mbed_official 553:063b9f2f393c 8042 ((INSTANCE) == TIM12))
mbed_official 553:063b9f2f393c 8043
mbed_official 553:063b9f2f393c 8044 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 553:063b9f2f393c 8045 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8046 ((INSTANCE) == TIM5))
mbed_official 553:063b9f2f393c 8047
mbed_official 553:063b9f2f393c 8048 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 553:063b9f2f393c 8049 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 553:063b9f2f393c 8050 ((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8051 ((INSTANCE) == TIM3) || \
mbed_official 553:063b9f2f393c 8052 ((INSTANCE) == TIM4) || \
mbed_official 553:063b9f2f393c 8053 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 8054 ((INSTANCE) == TIM8))
mbed_official 553:063b9f2f393c 8055
mbed_official 553:063b9f2f393c 8056 /****************** TIM Instances : remapping capability **********************/
mbed_official 553:063b9f2f393c 8057 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 553:063b9f2f393c 8058 ((INSTANCE) == TIM5) || \
mbed_official 553:063b9f2f393c 8059 ((INSTANCE) == TIM11))
mbed_official 553:063b9f2f393c 8060
mbed_official 553:063b9f2f393c 8061 /******************* TIM Instances : output(s) available **********************/
mbed_official 553:063b9f2f393c 8062 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 553:063b9f2f393c 8063 ((((INSTANCE) == TIM1) && \
mbed_official 553:063b9f2f393c 8064 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8065 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8066 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 553:063b9f2f393c 8067 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 553:063b9f2f393c 8068 || \
mbed_official 553:063b9f2f393c 8069 (((INSTANCE) == TIM2) && \
mbed_official 553:063b9f2f393c 8070 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8071 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8072 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 553:063b9f2f393c 8073 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 553:063b9f2f393c 8074 || \
mbed_official 553:063b9f2f393c 8075 (((INSTANCE) == TIM3) && \
mbed_official 553:063b9f2f393c 8076 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8077 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8078 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 553:063b9f2f393c 8079 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 553:063b9f2f393c 8080 || \
mbed_official 553:063b9f2f393c 8081 (((INSTANCE) == TIM4) && \
mbed_official 553:063b9f2f393c 8082 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8083 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8084 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 553:063b9f2f393c 8085 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 553:063b9f2f393c 8086 || \
mbed_official 553:063b9f2f393c 8087 (((INSTANCE) == TIM5) && \
mbed_official 553:063b9f2f393c 8088 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8089 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8090 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 553:063b9f2f393c 8091 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 553:063b9f2f393c 8092 || \
mbed_official 553:063b9f2f393c 8093 (((INSTANCE) == TIM8) && \
mbed_official 553:063b9f2f393c 8094 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8095 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8096 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 553:063b9f2f393c 8097 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 553:063b9f2f393c 8098 || \
mbed_official 553:063b9f2f393c 8099 (((INSTANCE) == TIM9) && \
mbed_official 553:063b9f2f393c 8100 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8101 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 553:063b9f2f393c 8102 || \
mbed_official 553:063b9f2f393c 8103 (((INSTANCE) == TIM10) && \
mbed_official 553:063b9f2f393c 8104 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 553:063b9f2f393c 8105 || \
mbed_official 553:063b9f2f393c 8106 (((INSTANCE) == TIM11) && \
mbed_official 553:063b9f2f393c 8107 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 553:063b9f2f393c 8108 || \
mbed_official 553:063b9f2f393c 8109 (((INSTANCE) == TIM12) && \
mbed_official 553:063b9f2f393c 8110 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8111 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 553:063b9f2f393c 8112 || \
mbed_official 553:063b9f2f393c 8113 (((INSTANCE) == TIM13) && \
mbed_official 553:063b9f2f393c 8114 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 553:063b9f2f393c 8115 || \
mbed_official 553:063b9f2f393c 8116 (((INSTANCE) == TIM14) && \
mbed_official 553:063b9f2f393c 8117 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 553:063b9f2f393c 8118
mbed_official 553:063b9f2f393c 8119 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 553:063b9f2f393c 8120 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 553:063b9f2f393c 8121 ((((INSTANCE) == TIM1) && \
mbed_official 553:063b9f2f393c 8122 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8123 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8124 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 553:063b9f2f393c 8125 || \
mbed_official 553:063b9f2f393c 8126 (((INSTANCE) == TIM8) && \
mbed_official 553:063b9f2f393c 8127 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 553:063b9f2f393c 8128 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 553:063b9f2f393c 8129 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 553:063b9f2f393c 8130
mbed_official 553:063b9f2f393c 8131 /******************** USART Instances : Synchronous mode **********************/
mbed_official 553:063b9f2f393c 8132 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 553:063b9f2f393c 8133 ((INSTANCE) == USART2) || \
mbed_official 553:063b9f2f393c 8134 ((INSTANCE) == USART3) || \
mbed_official 553:063b9f2f393c 8135 ((INSTANCE) == USART6))
mbed_official 553:063b9f2f393c 8136
mbed_official 553:063b9f2f393c 8137 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 553:063b9f2f393c 8138 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 553:063b9f2f393c 8139 ((INSTANCE) == USART2) || \
mbed_official 553:063b9f2f393c 8140 ((INSTANCE) == USART3) || \
mbed_official 553:063b9f2f393c 8141 ((INSTANCE) == UART4) || \
mbed_official 553:063b9f2f393c 8142 ((INSTANCE) == UART5) || \
mbed_official 553:063b9f2f393c 8143 ((INSTANCE) == USART6))
mbed_official 553:063b9f2f393c 8144
mbed_official 553:063b9f2f393c 8145 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 553:063b9f2f393c 8146 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 553:063b9f2f393c 8147 ((INSTANCE) == USART2) || \
mbed_official 553:063b9f2f393c 8148 ((INSTANCE) == USART3) || \
mbed_official 553:063b9f2f393c 8149 ((INSTANCE) == USART6))
mbed_official 553:063b9f2f393c 8150
mbed_official 553:063b9f2f393c 8151 /********************* UART Instances : Smard card mode ***********************/
mbed_official 553:063b9f2f393c 8152 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 553:063b9f2f393c 8153 ((INSTANCE) == USART2) || \
mbed_official 553:063b9f2f393c 8154 ((INSTANCE) == USART3) || \
mbed_official 553:063b9f2f393c 8155 ((INSTANCE) == USART6))
mbed_official 553:063b9f2f393c 8156
mbed_official 553:063b9f2f393c 8157 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 553:063b9f2f393c 8158 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 553:063b9f2f393c 8159 ((INSTANCE) == USART2) || \
mbed_official 553:063b9f2f393c 8160 ((INSTANCE) == USART3) || \
mbed_official 553:063b9f2f393c 8161 ((INSTANCE) == UART4) || \
mbed_official 553:063b9f2f393c 8162 ((INSTANCE) == UART5) || \
mbed_official 553:063b9f2f393c 8163 ((INSTANCE) == USART6))
mbed_official 553:063b9f2f393c 8164
mbed_official 553:063b9f2f393c 8165 /****************************** SDIO Instances ********************************/
mbed_official 553:063b9f2f393c 8166 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
mbed_official 553:063b9f2f393c 8167
mbed_official 553:063b9f2f393c 8168 /****************************** IWDG Instances ********************************/
mbed_official 553:063b9f2f393c 8169 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 553:063b9f2f393c 8170
mbed_official 553:063b9f2f393c 8171 /****************************** WWDG Instances ********************************/
mbed_official 553:063b9f2f393c 8172 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 553:063b9f2f393c 8173
mbed_official 553:063b9f2f393c 8174 /****************************** QSPI Instances ********************************/
mbed_official 553:063b9f2f393c 8175 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
mbed_official 553:063b9f2f393c 8176
mbed_official 553:063b9f2f393c 8177 /******************************* CEC Instances ********************************/
mbed_official 553:063b9f2f393c 8178 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
mbed_official 553:063b9f2f393c 8179
mbed_official 553:063b9f2f393c 8180 /***************************** FMPI2C Instances *******************************/
mbed_official 553:063b9f2f393c 8181 #define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
mbed_official 553:063b9f2f393c 8182
mbed_official 553:063b9f2f393c 8183 /******************************* SPDIFRX Instances ********************************/
mbed_official 553:063b9f2f393c 8184 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
mbed_official 553:063b9f2f393c 8185
mbed_official 553:063b9f2f393c 8186 /****************************** USB Exported Constants ************************/
mbed_official 553:063b9f2f393c 8187 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
mbed_official 553:063b9f2f393c 8188 #define USB_OTG_FS_MAX_IN_ENDPOINTS 5 /* Including EP0 */
mbed_official 553:063b9f2f393c 8189 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 5 /* Including EP0 */
mbed_official 553:063b9f2f393c 8190 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
mbed_official 553:063b9f2f393c 8191
mbed_official 553:063b9f2f393c 8192 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16
mbed_official 553:063b9f2f393c 8193 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
mbed_official 553:063b9f2f393c 8194 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8 /* Including EP0 */
mbed_official 553:063b9f2f393c 8195 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
mbed_official 553:063b9f2f393c 8196
mbed_official 553:063b9f2f393c 8197 /**
mbed_official 553:063b9f2f393c 8198 * @}
mbed_official 553:063b9f2f393c 8199 */
mbed_official 553:063b9f2f393c 8200
mbed_official 553:063b9f2f393c 8201 /**
mbed_official 553:063b9f2f393c 8202 * @}
mbed_official 553:063b9f2f393c 8203 */
mbed_official 553:063b9f2f393c 8204
mbed_official 553:063b9f2f393c 8205 /**
mbed_official 553:063b9f2f393c 8206 * @}
mbed_official 553:063b9f2f393c 8207 */
mbed_official 553:063b9f2f393c 8208
mbed_official 553:063b9f2f393c 8209 #ifdef __cplusplus
mbed_official 553:063b9f2f393c 8210 }
mbed_official 553:063b9f2f393c 8211 #endif /* __cplusplus */
mbed_official 553:063b9f2f393c 8212
mbed_official 553:063b9f2f393c 8213 #endif /* __STM32F446xx_H */
mbed_official 553:063b9f2f393c 8214
mbed_official 553:063b9f2f393c 8215
mbed_official 553:063b9f2f393c 8216
mbed_official 553:063b9f2f393c 8217 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/