CMSIS DSP library
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arm_shift_q15.c
00001 /* ---------------------------------------------------------------------- 00002 * Copyright (C) 2010-2014 ARM Limited. All rights reserved. 00003 * 00004 * $Date: 19. March 2015 00005 * $Revision: V.1.4.5 00006 * 00007 * Project: CMSIS DSP Library 00008 * Title: arm_shift_q15.c 00009 * 00010 * Description: Shifts the elements of a Q15 vector by a specified number of bits. 00011 * 00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 00013 * 00014 * Redistribution and use in source and binary forms, with or without 00015 * modification, are permitted provided that the following conditions 00016 * are met: 00017 * - Redistributions of source code must retain the above copyright 00018 * notice, this list of conditions and the following disclaimer. 00019 * - Redistributions in binary form must reproduce the above copyright 00020 * notice, this list of conditions and the following disclaimer in 00021 * the documentation and/or other materials provided with the 00022 * distribution. 00023 * - Neither the name of ARM LIMITED nor the names of its contributors 00024 * may be used to endorse or promote products derived from this 00025 * software without specific prior written permission. 00026 * 00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00038 * POSSIBILITY OF SUCH DAMAGE. 00039 * -------------------------------------------------------------------- */ 00040 00041 #include "arm_math.h" 00042 00043 /** 00044 * @ingroup groupMath 00045 */ 00046 00047 /** 00048 * @addtogroup shift 00049 * @{ 00050 */ 00051 00052 /** 00053 * @brief Shifts the elements of a Q15 vector a specified number of bits. 00054 * @param[in] *pSrc points to the input vector 00055 * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. 00056 * @param[out] *pDst points to the output vector 00057 * @param[in] blockSize number of samples in the vector 00058 * @return none. 00059 * 00060 * <b>Scaling and Overflow Behavior:</b> 00061 * \par 00062 * The function uses saturating arithmetic. 00063 * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. 00064 */ 00065 00066 void arm_shift_q15( 00067 q15_t * pSrc, 00068 int8_t shiftBits, 00069 q15_t * pDst, 00070 uint32_t blockSize) 00071 { 00072 uint32_t blkCnt; /* loop counter */ 00073 uint8_t sign; /* Sign of shiftBits */ 00074 00075 #ifndef ARM_MATH_CM0_FAMILY 00076 00077 /* Run the below code for Cortex-M4 and Cortex-M3 */ 00078 00079 q15_t in1, in2; /* Temporary variables */ 00080 00081 00082 /*loop Unrolling */ 00083 blkCnt = blockSize >> 2u; 00084 00085 /* Getting the sign of shiftBits */ 00086 sign = (shiftBits & 0x80); 00087 00088 /* If the shift value is positive then do right shift else left shift */ 00089 if(sign == 0u) 00090 { 00091 /* First part of the processing with loop unrolling. Compute 4 outputs at a time. 00092 ** a second loop below computes the remaining 1 to 3 samples. */ 00093 while(blkCnt > 0u) 00094 { 00095 /* Read 2 inputs */ 00096 in1 = *pSrc++; 00097 in2 = *pSrc++; 00098 /* C = A << shiftBits */ 00099 /* Shift the inputs and then store the results in the destination buffer. */ 00100 #ifndef ARM_MATH_BIG_ENDIAN 00101 00102 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), 00103 __SSAT((in2 << shiftBits), 16), 16); 00104 00105 #else 00106 00107 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), 00108 __SSAT((in1 << shiftBits), 16), 16); 00109 00110 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */ 00111 00112 in1 = *pSrc++; 00113 in2 = *pSrc++; 00114 00115 #ifndef ARM_MATH_BIG_ENDIAN 00116 00117 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), 00118 __SSAT((in2 << shiftBits), 16), 16); 00119 00120 #else 00121 00122 *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), 00123 __SSAT((in1 << shiftBits), 16), 16); 00124 00125 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */ 00126 00127 /* Decrement the loop counter */ 00128 blkCnt--; 00129 } 00130 00131 /* If the blockSize is not a multiple of 4, compute any remaining output samples here. 00132 ** No loop unrolling is used. */ 00133 blkCnt = blockSize % 0x4u; 00134 00135 while(blkCnt > 0u) 00136 { 00137 /* C = A << shiftBits */ 00138 /* Shift and then store the results in the destination buffer. */ 00139 *pDst++ = __SSAT((*pSrc++ << shiftBits), 16); 00140 00141 /* Decrement the loop counter */ 00142 blkCnt--; 00143 } 00144 } 00145 else 00146 { 00147 /* First part of the processing with loop unrolling. Compute 4 outputs at a time. 00148 ** a second loop below computes the remaining 1 to 3 samples. */ 00149 while(blkCnt > 0u) 00150 { 00151 /* Read 2 inputs */ 00152 in1 = *pSrc++; 00153 in2 = *pSrc++; 00154 00155 /* C = A >> shiftBits */ 00156 /* Shift the inputs and then store the results in the destination buffer. */ 00157 #ifndef ARM_MATH_BIG_ENDIAN 00158 00159 *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), 00160 (in2 >> -shiftBits), 16); 00161 00162 #else 00163 00164 *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), 00165 (in1 >> -shiftBits), 16); 00166 00167 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */ 00168 00169 in1 = *pSrc++; 00170 in2 = *pSrc++; 00171 00172 #ifndef ARM_MATH_BIG_ENDIAN 00173 00174 *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), 00175 (in2 >> -shiftBits), 16); 00176 00177 #else 00178 00179 *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), 00180 (in1 >> -shiftBits), 16); 00181 00182 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */ 00183 00184 /* Decrement the loop counter */ 00185 blkCnt--; 00186 } 00187 00188 /* If the blockSize is not a multiple of 4, compute any remaining output samples here. 00189 ** No loop unrolling is used. */ 00190 blkCnt = blockSize % 0x4u; 00191 00192 while(blkCnt > 0u) 00193 { 00194 /* C = A >> shiftBits */ 00195 /* Shift the inputs and then store the results in the destination buffer. */ 00196 *pDst++ = (*pSrc++ >> -shiftBits); 00197 00198 /* Decrement the loop counter */ 00199 blkCnt--; 00200 } 00201 } 00202 00203 #else 00204 00205 /* Run the below code for Cortex-M0 */ 00206 00207 /* Getting the sign of shiftBits */ 00208 sign = (shiftBits & 0x80); 00209 00210 /* If the shift value is positive then do right shift else left shift */ 00211 if(sign == 0u) 00212 { 00213 /* Initialize blkCnt with number of samples */ 00214 blkCnt = blockSize; 00215 00216 while(blkCnt > 0u) 00217 { 00218 /* C = A << shiftBits */ 00219 /* Shift and then store the results in the destination buffer. */ 00220 *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16); 00221 00222 /* Decrement the loop counter */ 00223 blkCnt--; 00224 } 00225 } 00226 else 00227 { 00228 /* Initialize blkCnt with number of samples */ 00229 blkCnt = blockSize; 00230 00231 while(blkCnt > 0u) 00232 { 00233 /* C = A >> shiftBits */ 00234 /* Shift the inputs and then store the results in the destination buffer. */ 00235 *pDst++ = (*pSrc++ >> -shiftBits); 00236 00237 /* Decrement the loop counter */ 00238 blkCnt--; 00239 } 00240 } 00241 00242 #endif /* #ifndef ARM_MATH_CM0_FAMILY */ 00243 00244 } 00245 00246 /** 00247 * @} end of shift group 00248 */
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