arm_q15_to_q31.c

00001 /* ----------------------------------------------------------------------------    
00002 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
00003 *    
00004 * $Date:        19. March 2015
00005 * $Revision:    V.1.4.5  
00006 *    
00007 * Project:      CMSIS DSP Library    
00008 * Title:        arm_q15_to_q31.c    
00009 *    
00010 * Description:  Converts the elements of the Q15 vector to Q31 vector.  
00011 *    
00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
00013 *  
00014 * Redistribution and use in source and binary forms, with or without 
00015 * modification, are permitted provided that the following conditions
00016 * are met:
00017 *   - Redistributions of source code must retain the above copyright
00018 *     notice, this list of conditions and the following disclaimer.
00019 *   - Redistributions in binary form must reproduce the above copyright
00020 *     notice, this list of conditions and the following disclaimer in
00021 *     the documentation and/or other materials provided with the 
00022 *     distribution.
00023 *   - Neither the name of ARM LIMITED nor the names of its contributors
00024 *     may be used to endorse or promote products derived from this
00025 *     software without specific prior written permission.
00026 *
00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00038 * POSSIBILITY OF SUCH DAMAGE.     
00039 * ---------------------------------------------------------------------------- */
00040 
00041 #include "arm_math.h"
00042 
00043 /**    
00044  * @ingroup groupSupport    
00045  */
00046 
00047 /**    
00048  * @addtogroup q15_to_x    
00049  * @{    
00050  */
00051 
00052 /**    
00053  * @brief Converts the elements of the Q15 vector to Q31 vector.     
00054  * @param[in]       *pSrc points to the Q15 input vector    
00055  * @param[out]      *pDst points to the Q31 output vector   
00056  * @param[in]       blockSize length of the input vector    
00057  * @return none.    
00058  *    
00059  * \par Description:    
00060  *    
00061  * The equation used for the conversion process is:   
00062  *   
00063  * <pre>    
00064  *  pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    
00065  * </pre>    
00066  *   
00067  */
00068 
00069 
00070 void arm_q15_to_q31(
00071   q15_t * pSrc,
00072   q31_t * pDst,
00073   uint32_t blockSize)
00074 {
00075   q15_t *pIn = pSrc;                             /* Src pointer */
00076   uint32_t blkCnt;                               /* loop counter */
00077 
00078 #ifndef ARM_MATH_CM0_FAMILY
00079 
00080   /* Run the below code for Cortex-M4 and Cortex-M3 */
00081   q31_t in1, in2;
00082   q31_t out1, out2, out3, out4;
00083 
00084   /*loop Unrolling */
00085   blkCnt = blockSize >> 2u;
00086 
00087   /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
00088    ** a second loop below computes the remaining 1 to 3 samples. */
00089   while(blkCnt > 0u)
00090   {
00091     /* C = (q31_t)A << 16 */
00092     /* convert from q15 to q31 and then store the results in the destination buffer */
00093     in1 = *__SIMD32(pIn)++;
00094     in2 = *__SIMD32(pIn)++;
00095 
00096 #ifndef ARM_MATH_BIG_ENDIAN
00097 
00098     /* extract lower 16 bits to 32 bit result */
00099     out1 = in1 << 16u;
00100     /* extract upper 16 bits to 32 bit result */
00101     out2 = in1 & 0xFFFF0000;
00102     /* extract lower 16 bits to 32 bit result */
00103     out3 = in2 << 16u;
00104     /* extract upper 16 bits to 32 bit result */
00105     out4 = in2 & 0xFFFF0000;
00106 
00107 #else
00108 
00109     /* extract upper 16 bits to 32 bit result */
00110     out1 = in1 & 0xFFFF0000;
00111     /* extract lower 16 bits to 32 bit result */
00112     out2 = in1 << 16u;
00113     /* extract upper 16 bits to 32 bit result */
00114     out3 = in2 & 0xFFFF0000;
00115     /* extract lower 16 bits to 32 bit result */
00116     out4 = in2 << 16u;
00117 
00118 #endif //      #ifndef ARM_MATH_BIG_ENDIAN
00119 
00120     *pDst++ = out1;
00121     *pDst++ = out2;
00122     *pDst++ = out3;
00123     *pDst++ = out4;
00124 
00125     /* Decrement the loop counter */
00126     blkCnt--;
00127   }
00128 
00129   /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
00130    ** No loop unrolling is used. */
00131   blkCnt = blockSize % 0x4u;
00132 
00133 #else
00134 
00135   /* Run the below code for Cortex-M0 */
00136 
00137   /* Loop over blockSize number of values */
00138   blkCnt = blockSize;
00139 
00140 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
00141 
00142   while(blkCnt > 0u)
00143   {
00144     /* C = (q31_t)A << 16 */
00145     /* convert from q15 to q31 and then store the results in the destination buffer */
00146     *pDst++ = (q31_t) * pIn++ << 16;
00147 
00148     /* Decrement the loop counter */
00149     blkCnt--;
00150   }
00151 
00152 }
00153 
00154 /**    
00155  * @} end of q15_to_x group    
00156  */