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CMSIS DSP library

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cmsis_dsp/BasicMathFunctions/arm_shift_q7.c@2:da51fb522205, 2013-05-30 (annotated)

Committer:
emilmont
Date:
Thu May 30 17:10:11 2013 +0100
Revision:
2:da51fb522205
Parent:
1:fdd22bb7aa52
Child:
3:7a284390b0ce
Keep "cmsis-dsp" module in synch with its source

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
emilmont 1:fdd22bb7aa52 2 * Copyright (C) 2010 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
emilmont 1:fdd22bb7aa52 4 * $Date: 15. February 2012
emilmont 2:da51fb522205 5 * $Revision: V1.1.0
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_shift_q7.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Processing function for the Q7 Shifting
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
emilmont 1:fdd22bb7aa52 14 * Version 1.1.0 2012/02/15
emilmont 1:fdd22bb7aa52 15 * Updated with more optimizations, bug fixes and minor API changes.
emilmont 1:fdd22bb7aa52 16 *
emilmont 1:fdd22bb7aa52 17 * Version 1.0.10 2011/7/15
emilmont 1:fdd22bb7aa52 18 * Big Endian support added and Merged M0 and M3/M4 Source code.
emilmont 1:fdd22bb7aa52 19 *
emilmont 1:fdd22bb7aa52 20 * Version 1.0.3 2010/11/29
emilmont 1:fdd22bb7aa52 21 * Re-organized the CMSIS folders and updated documentation.
emilmont 1:fdd22bb7aa52 22 *
emilmont 1:fdd22bb7aa52 23 * Version 1.0.2 2010/11/11
emilmont 1:fdd22bb7aa52 24 * Documentation updated.
emilmont 1:fdd22bb7aa52 25 *
emilmont 1:fdd22bb7aa52 26 * Version 1.0.1 2010/10/05
emilmont 1:fdd22bb7aa52 27 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 28 *
emilmont 1:fdd22bb7aa52 29 * Version 1.0.0 2010/09/20
emilmont 1:fdd22bb7aa52 30 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 31 *
emilmont 1:fdd22bb7aa52 32 * Version 0.0.7 2010/06/10
emilmont 1:fdd22bb7aa52 33 * Misra-C changes done
emilmont 1:fdd22bb7aa52 34 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 35
emilmont 1:fdd22bb7aa52 36 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 37
emilmont 1:fdd22bb7aa52 38 /**
emilmont 1:fdd22bb7aa52 39 * @ingroup groupMath
emilmont 1:fdd22bb7aa52 40 */
emilmont 1:fdd22bb7aa52 41
emilmont 1:fdd22bb7aa52 42 /**
emilmont 1:fdd22bb7aa52 43 * @addtogroup shift
emilmont 1:fdd22bb7aa52 44 * @{
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47
emilmont 1:fdd22bb7aa52 48 /**
emilmont 1:fdd22bb7aa52 49 * @brief Shifts the elements of a Q7 vector a specified number of bits.
emilmont 1:fdd22bb7aa52 50 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 51 * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
emilmont 1:fdd22bb7aa52 52 * @param[out] *pDst points to the output vector
emilmont 1:fdd22bb7aa52 53 * @param[in] blockSize number of samples in the vector
emilmont 1:fdd22bb7aa52 54 * @return none.
emilmont 1:fdd22bb7aa52 55 *
emilmont 1:fdd22bb7aa52 56 * \par Conditions for optimum performance
emilmont 1:fdd22bb7aa52 57 * Input and output buffers should be aligned by 32-bit
emilmont 1:fdd22bb7aa52 58 *
emilmont 1:fdd22bb7aa52 59 *
emilmont 1:fdd22bb7aa52 60 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 61 * \par
emilmont 1:fdd22bb7aa52 62 * The function uses saturating arithmetic.
emilmont 1:fdd22bb7aa52 63 * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
emilmont 1:fdd22bb7aa52 64 */
emilmont 1:fdd22bb7aa52 65
emilmont 1:fdd22bb7aa52 66 void arm_shift_q7(
emilmont 1:fdd22bb7aa52 67 q7_t * pSrc,
emilmont 1:fdd22bb7aa52 68 int8_t shiftBits,
emilmont 1:fdd22bb7aa52 69 q7_t * pDst,
emilmont 1:fdd22bb7aa52 70 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 71 {
emilmont 1:fdd22bb7aa52 72 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 73 uint8_t sign; /* Sign of shiftBits */
emilmont 1:fdd22bb7aa52 74
emilmont 1:fdd22bb7aa52 75 #ifndef ARM_MATH_CM0
emilmont 1:fdd22bb7aa52 76
emilmont 1:fdd22bb7aa52 77 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 78 q7_t in1; /* Input value1 */
emilmont 1:fdd22bb7aa52 79 q7_t in2; /* Input value2 */
emilmont 1:fdd22bb7aa52 80 q7_t in3; /* Input value3 */
emilmont 1:fdd22bb7aa52 81 q7_t in4; /* Input value4 */
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83
emilmont 1:fdd22bb7aa52 84 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 85 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 86
emilmont 1:fdd22bb7aa52 87 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 88 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 89
emilmont 1:fdd22bb7aa52 90 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 91 if(sign == 0u)
emilmont 1:fdd22bb7aa52 92 {
emilmont 1:fdd22bb7aa52 93 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 94 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 95 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 96 {
emilmont 1:fdd22bb7aa52 97 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 98 /* Read 4 inputs */
emilmont 1:fdd22bb7aa52 99 in1 = *pSrc;
emilmont 1:fdd22bb7aa52 100 in2 = *(pSrc + 1);
emilmont 1:fdd22bb7aa52 101 in3 = *(pSrc + 2);
emilmont 1:fdd22bb7aa52 102 in4 = *(pSrc + 3);
emilmont 1:fdd22bb7aa52 103
emilmont 1:fdd22bb7aa52 104 /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
emilmont 1:fdd22bb7aa52 105 *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
emilmont 1:fdd22bb7aa52 106 __SSAT((in2 << shiftBits), 8),
emilmont 1:fdd22bb7aa52 107 __SSAT((in3 << shiftBits), 8),
emilmont 1:fdd22bb7aa52 108 __SSAT((in4 << shiftBits), 8));
emilmont 1:fdd22bb7aa52 109 /* Update source pointer to process next sampels */
emilmont 1:fdd22bb7aa52 110 pSrc += 4u;
emilmont 1:fdd22bb7aa52 111
emilmont 1:fdd22bb7aa52 112 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 113 blkCnt--;
emilmont 1:fdd22bb7aa52 114 }
emilmont 1:fdd22bb7aa52 115
emilmont 1:fdd22bb7aa52 116 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 117 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 118 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 119
emilmont 1:fdd22bb7aa52 120 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 121 {
emilmont 1:fdd22bb7aa52 122 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 123 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 124 *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
emilmont 1:fdd22bb7aa52 125
emilmont 1:fdd22bb7aa52 126 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 127 blkCnt--;
emilmont 1:fdd22bb7aa52 128 }
emilmont 1:fdd22bb7aa52 129 }
emilmont 1:fdd22bb7aa52 130 else
emilmont 1:fdd22bb7aa52 131 {
emilmont 1:fdd22bb7aa52 132 shiftBits = -shiftBits;
emilmont 1:fdd22bb7aa52 133 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 134 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 135 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 136 {
emilmont 1:fdd22bb7aa52 137 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 138 /* Read 4 inputs */
emilmont 1:fdd22bb7aa52 139 in1 = *pSrc;
emilmont 1:fdd22bb7aa52 140 in2 = *(pSrc + 1);
emilmont 1:fdd22bb7aa52 141 in3 = *(pSrc + 2);
emilmont 1:fdd22bb7aa52 142 in4 = *(pSrc + 3);
emilmont 1:fdd22bb7aa52 143
emilmont 1:fdd22bb7aa52 144 /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
emilmont 1:fdd22bb7aa52 145 *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
emilmont 1:fdd22bb7aa52 146 (in3 >> shiftBits), (in4 >> shiftBits));
emilmont 1:fdd22bb7aa52 147
emilmont 1:fdd22bb7aa52 148
emilmont 1:fdd22bb7aa52 149 pSrc += 4u;
emilmont 1:fdd22bb7aa52 150
emilmont 1:fdd22bb7aa52 151 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 152 blkCnt--;
emilmont 1:fdd22bb7aa52 153 }
emilmont 1:fdd22bb7aa52 154
emilmont 1:fdd22bb7aa52 155 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 156 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 157 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 158
emilmont 1:fdd22bb7aa52 159 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 160 {
emilmont 1:fdd22bb7aa52 161 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 162 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 163 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 164 *pDst++ = (in1 >> shiftBits);
emilmont 1:fdd22bb7aa52 165
emilmont 1:fdd22bb7aa52 166 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 167 blkCnt--;
emilmont 1:fdd22bb7aa52 168 }
emilmont 1:fdd22bb7aa52 169 }
emilmont 1:fdd22bb7aa52 170
emilmont 1:fdd22bb7aa52 171 #else
emilmont 1:fdd22bb7aa52 172
emilmont 1:fdd22bb7aa52 173 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 174
emilmont 1:fdd22bb7aa52 175 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 176 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 177
emilmont 1:fdd22bb7aa52 178 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 179 if(sign == 0u)
emilmont 1:fdd22bb7aa52 180 {
emilmont 1:fdd22bb7aa52 181 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 182 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 183
emilmont 1:fdd22bb7aa52 184 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 185 {
emilmont 1:fdd22bb7aa52 186 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 187 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 188 *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
emilmont 1:fdd22bb7aa52 189
emilmont 1:fdd22bb7aa52 190 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 191 blkCnt--;
emilmont 1:fdd22bb7aa52 192 }
emilmont 1:fdd22bb7aa52 193 }
emilmont 1:fdd22bb7aa52 194 else
emilmont 1:fdd22bb7aa52 195 {
emilmont 1:fdd22bb7aa52 196 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 197 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 198
emilmont 1:fdd22bb7aa52 199 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 200 {
emilmont 1:fdd22bb7aa52 201 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 202 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 203 *pDst++ = (*pSrc++ >> -shiftBits);
emilmont 1:fdd22bb7aa52 204
emilmont 1:fdd22bb7aa52 205 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 206 blkCnt--;
emilmont 1:fdd22bb7aa52 207 }
emilmont 1:fdd22bb7aa52 208 }
emilmont 1:fdd22bb7aa52 209
emilmont 1:fdd22bb7aa52 210 #endif /* #ifndef ARM_MATH_CM0 */
emilmont 1:fdd22bb7aa52 211 }
emilmont 1:fdd22bb7aa52 212
emilmont 1:fdd22bb7aa52 213 /**
emilmont 1:fdd22bb7aa52 214 * @} end of shift group
emilmont 1:fdd22bb7aa52 215 */