mbed official / mbed-dsp

CMSIS DSP library

Dependents:   performance_timer Surfboard_ gps2rtty Capstone ... more

Legacy Warning

This is an mbed 2 library. To learn more about mbed OS 5, visit the docs.

cmsis_dsp/TransformFunctions/arm_rfft_q15.c@3:7a284390b0ce, 2013-11-08 (annotated)

Committer:
mbed_official
Date:
Fri Nov 08 13:45:10 2013 +0000
Revision:
3:7a284390b0ce
Parent:
2:da51fb522205
Child:
5:3762170b6d4d
Synchronized with git revision e69956aba2f68a2a26ac26b051f8d349deaa1ce8

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 3:7a284390b0ce 2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 3:7a284390b0ce 4 * $Date: 17. January 2013
mbed_official 3:7a284390b0ce 5 * $Revision: V1.4.1
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_rfft_q15.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: RFFT & RIFFT Q15 process function
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 *
emilmont 1:fdd22bb7aa52 13 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 14 *
mbed_official 3:7a284390b0ce 15 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 16 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 17 * are met:
mbed_official 3:7a284390b0ce 18 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 19 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 20 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 21 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 22 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 23 * distribution.
mbed_official 3:7a284390b0ce 24 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 25 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 26 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 27 *
mbed_official 3:7a284390b0ce 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 31 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 32 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 34 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 35 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 39 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 40 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 41
emilmont 1:fdd22bb7aa52 42 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 43
mbed_official 3:7a284390b0ce 44 void arm_radix4_butterfly_q15(
mbed_official 3:7a284390b0ce 45 q15_t * pSrc16,
mbed_official 3:7a284390b0ce 46 uint32_t fftLen,
mbed_official 3:7a284390b0ce 47 q15_t * pCoef16,
mbed_official 3:7a284390b0ce 48 uint32_t twidCoefModifier);
mbed_official 3:7a284390b0ce 49
mbed_official 3:7a284390b0ce 50 void arm_radix4_butterfly_inverse_q15(
mbed_official 3:7a284390b0ce 51 q15_t * pSrc16,
mbed_official 3:7a284390b0ce 52 uint32_t fftLen,
mbed_official 3:7a284390b0ce 53 q15_t * pCoef16,
mbed_official 3:7a284390b0ce 54 uint32_t twidCoefModifier);
mbed_official 3:7a284390b0ce 55
mbed_official 3:7a284390b0ce 56 void arm_bitreversal_q15(
mbed_official 3:7a284390b0ce 57 q15_t * pSrc,
mbed_official 3:7a284390b0ce 58 uint32_t fftLen,
mbed_official 3:7a284390b0ce 59 uint16_t bitRevFactor,
mbed_official 3:7a284390b0ce 60 uint16_t * pBitRevTab);
mbed_official 3:7a284390b0ce 61
mbed_official 3:7a284390b0ce 62 /*--------------------------------------------------------------------
emilmont 2:da51fb522205 63 * Internal functions prototypes
emilmont 1:fdd22bb7aa52 64 --------------------------------------------------------------------*/
emilmont 1:fdd22bb7aa52 65
emilmont 1:fdd22bb7aa52 66 void arm_split_rfft_q15(
emilmont 1:fdd22bb7aa52 67 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 68 uint32_t fftLen,
emilmont 1:fdd22bb7aa52 69 q15_t * pATable,
emilmont 1:fdd22bb7aa52 70 q15_t * pBTable,
emilmont 1:fdd22bb7aa52 71 q15_t * pDst,
emilmont 1:fdd22bb7aa52 72 uint32_t modifier);
emilmont 1:fdd22bb7aa52 73
emilmont 1:fdd22bb7aa52 74 void arm_split_rifft_q15(
emilmont 1:fdd22bb7aa52 75 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 76 uint32_t fftLen,
emilmont 1:fdd22bb7aa52 77 q15_t * pATable,
emilmont 1:fdd22bb7aa52 78 q15_t * pBTable,
emilmont 1:fdd22bb7aa52 79 q15_t * pDst,
emilmont 1:fdd22bb7aa52 80 uint32_t modifier);
emilmont 1:fdd22bb7aa52 81
emilmont 1:fdd22bb7aa52 82 /**
mbed_official 3:7a284390b0ce 83 * @addtogroup RealFFT
emilmont 1:fdd22bb7aa52 84 * @{
emilmont 1:fdd22bb7aa52 85 */
emilmont 1:fdd22bb7aa52 86
emilmont 1:fdd22bb7aa52 87 /**
emilmont 1:fdd22bb7aa52 88 * @brief Processing function for the Q15 RFFT/RIFFT.
emilmont 1:fdd22bb7aa52 89 * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
emilmont 1:fdd22bb7aa52 90 * @param[in] *pSrc points to the input buffer.
emilmont 1:fdd22bb7aa52 91 * @param[out] *pDst points to the output buffer.
emilmont 1:fdd22bb7aa52 92 * @return none.
emilmont 1:fdd22bb7aa52 93 *
emilmont 1:fdd22bb7aa52 94 * \par Input an output formats:
emilmont 1:fdd22bb7aa52 95 * \par
emilmont 1:fdd22bb7aa52 96 * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
emilmont 1:fdd22bb7aa52 97 * Hence the output format is different for different RFFT sizes.
emilmont 1:fdd22bb7aa52 98 * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
emilmont 1:fdd22bb7aa52 99 * \par
emilmont 1:fdd22bb7aa52 100 * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"
emilmont 1:fdd22bb7aa52 101 * \par
emilmont 1:fdd22bb7aa52 102 * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"
emilmont 1:fdd22bb7aa52 103 */
emilmont 1:fdd22bb7aa52 104
emilmont 1:fdd22bb7aa52 105 void arm_rfft_q15(
emilmont 1:fdd22bb7aa52 106 const arm_rfft_instance_q15 * S,
emilmont 1:fdd22bb7aa52 107 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 108 q15_t * pDst)
emilmont 1:fdd22bb7aa52 109 {
emilmont 1:fdd22bb7aa52 110 const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
emilmont 1:fdd22bb7aa52 111
emilmont 1:fdd22bb7aa52 112 /* Calculation of RIFFT of input */
emilmont 1:fdd22bb7aa52 113 if(S->ifftFlagR == 1u)
emilmont 1:fdd22bb7aa52 114 {
emilmont 1:fdd22bb7aa52 115 /* Real IFFT core process */
emilmont 1:fdd22bb7aa52 116 arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
emilmont 1:fdd22bb7aa52 117 S->pTwiddleBReal, pDst, S->twidCoefRModifier);
emilmont 1:fdd22bb7aa52 118
emilmont 1:fdd22bb7aa52 119 /* Complex readix-4 IFFT process */
emilmont 1:fdd22bb7aa52 120 arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
emilmont 1:fdd22bb7aa52 121 S_CFFT->pTwiddle,
emilmont 1:fdd22bb7aa52 122 S_CFFT->twidCoefModifier);
emilmont 1:fdd22bb7aa52 123
emilmont 1:fdd22bb7aa52 124 /* Bit reversal process */
emilmont 1:fdd22bb7aa52 125 if(S->bitReverseFlagR == 1u)
emilmont 1:fdd22bb7aa52 126 {
emilmont 1:fdd22bb7aa52 127 arm_bitreversal_q15(pDst, S_CFFT->fftLen,
emilmont 1:fdd22bb7aa52 128 S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
emilmont 1:fdd22bb7aa52 129 }
emilmont 1:fdd22bb7aa52 130 }
emilmont 1:fdd22bb7aa52 131 else
emilmont 1:fdd22bb7aa52 132 {
emilmont 1:fdd22bb7aa52 133 /* Calculation of RFFT of input */
emilmont 1:fdd22bb7aa52 134
emilmont 1:fdd22bb7aa52 135 /* Complex readix-4 FFT process */
emilmont 1:fdd22bb7aa52 136 arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
emilmont 1:fdd22bb7aa52 137 S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
emilmont 1:fdd22bb7aa52 138
emilmont 1:fdd22bb7aa52 139 /* Bit reversal process */
emilmont 1:fdd22bb7aa52 140 if(S->bitReverseFlagR == 1u)
emilmont 1:fdd22bb7aa52 141 {
emilmont 1:fdd22bb7aa52 142 arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
emilmont 1:fdd22bb7aa52 143 S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
emilmont 1:fdd22bb7aa52 144 }
emilmont 1:fdd22bb7aa52 145
emilmont 1:fdd22bb7aa52 146 arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
emilmont 1:fdd22bb7aa52 147 S->pTwiddleBReal, pDst, S->twidCoefRModifier);
emilmont 1:fdd22bb7aa52 148 }
emilmont 1:fdd22bb7aa52 149
emilmont 1:fdd22bb7aa52 150 }
emilmont 1:fdd22bb7aa52 151
emilmont 1:fdd22bb7aa52 152 /**
mbed_official 3:7a284390b0ce 153 * @} end of RealFFT group
emilmont 1:fdd22bb7aa52 154 */
emilmont 1:fdd22bb7aa52 155
emilmont 1:fdd22bb7aa52 156 /**
emilmont 1:fdd22bb7aa52 157 * @brief Core Real FFT process
emilmont 2:da51fb522205 158 * @param *pSrc points to the input buffer.
emilmont 2:da51fb522205 159 * @param fftLen length of FFT.
emilmont 2:da51fb522205 160 * @param *pATable points to the A twiddle Coef buffer.
emilmont 2:da51fb522205 161 * @param *pBTable points to the B twiddle Coef buffer.
emilmont 2:da51fb522205 162 * @param *pDst points to the output buffer.
emilmont 2:da51fb522205 163 * @param modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
emilmont 1:fdd22bb7aa52 164 * @return none.
emilmont 1:fdd22bb7aa52 165 * The function implements a Real FFT
emilmont 1:fdd22bb7aa52 166 */
emilmont 1:fdd22bb7aa52 167
emilmont 1:fdd22bb7aa52 168 void arm_split_rfft_q15(
emilmont 1:fdd22bb7aa52 169 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 170 uint32_t fftLen,
emilmont 1:fdd22bb7aa52 171 q15_t * pATable,
emilmont 1:fdd22bb7aa52 172 q15_t * pBTable,
emilmont 1:fdd22bb7aa52 173 q15_t * pDst,
emilmont 1:fdd22bb7aa52 174 uint32_t modifier)
emilmont 1:fdd22bb7aa52 175 {
emilmont 1:fdd22bb7aa52 176 uint32_t i; /* Loop Counter */
emilmont 1:fdd22bb7aa52 177 q31_t outR, outI; /* Temporary variables for output */
emilmont 1:fdd22bb7aa52 178 q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
emilmont 1:fdd22bb7aa52 179 q15_t *pSrc1, *pSrc2;
emilmont 1:fdd22bb7aa52 180
emilmont 1:fdd22bb7aa52 181
emilmont 1:fdd22bb7aa52 182 // pSrc[2u * fftLen] = pSrc[0];
emilmont 1:fdd22bb7aa52 183 // pSrc[(2u * fftLen) + 1u] = pSrc[1];
emilmont 1:fdd22bb7aa52 184
emilmont 1:fdd22bb7aa52 185 pCoefA = &pATable[modifier * 2u];
emilmont 1:fdd22bb7aa52 186 pCoefB = &pBTable[modifier * 2u];
emilmont 1:fdd22bb7aa52 187
emilmont 1:fdd22bb7aa52 188 pSrc1 = &pSrc[2];
emilmont 1:fdd22bb7aa52 189 pSrc2 = &pSrc[(2u * fftLen) - 2u];
emilmont 1:fdd22bb7aa52 190
mbed_official 3:7a284390b0ce 191 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 192
emilmont 1:fdd22bb7aa52 193 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 194
emilmont 1:fdd22bb7aa52 195 i = 1u;
emilmont 1:fdd22bb7aa52 196
emilmont 1:fdd22bb7aa52 197 while(i < fftLen)
emilmont 1:fdd22bb7aa52 198 {
emilmont 1:fdd22bb7aa52 199 /*
emilmont 1:fdd22bb7aa52 200 outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
emilmont 1:fdd22bb7aa52 201 + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
emilmont 1:fdd22bb7aa52 202 pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
emilmont 1:fdd22bb7aa52 203 */
emilmont 1:fdd22bb7aa52 204
emilmont 1:fdd22bb7aa52 205 /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
emilmont 1:fdd22bb7aa52 206 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
emilmont 1:fdd22bb7aa52 207 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
emilmont 1:fdd22bb7aa52 208
emilmont 1:fdd22bb7aa52 209
emilmont 1:fdd22bb7aa52 210 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 211
emilmont 1:fdd22bb7aa52 212 /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
emilmont 1:fdd22bb7aa52 213 outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
emilmont 1:fdd22bb7aa52 214
emilmont 1:fdd22bb7aa52 215 #else
emilmont 1:fdd22bb7aa52 216
emilmont 1:fdd22bb7aa52 217 /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
emilmont 1:fdd22bb7aa52 218 outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
emilmont 1:fdd22bb7aa52 219
emilmont 1:fdd22bb7aa52 220 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 221
emilmont 1:fdd22bb7aa52 222 /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +
emilmont 1:fdd22bb7aa52 223 pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
emilmont 1:fdd22bb7aa52 224 outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
emilmont 1:fdd22bb7aa52 225
emilmont 1:fdd22bb7aa52 226 /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
emilmont 1:fdd22bb7aa52 227 pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
emilmont 1:fdd22bb7aa52 228
emilmont 1:fdd22bb7aa52 229 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 230
emilmont 1:fdd22bb7aa52 231 outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
emilmont 1:fdd22bb7aa52 232
emilmont 1:fdd22bb7aa52 233 #else
emilmont 1:fdd22bb7aa52 234
emilmont 1:fdd22bb7aa52 235 outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
emilmont 1:fdd22bb7aa52 236
emilmont 1:fdd22bb7aa52 237 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 238
emilmont 1:fdd22bb7aa52 239 /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
emilmont 1:fdd22bb7aa52 240 outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
emilmont 1:fdd22bb7aa52 241
emilmont 1:fdd22bb7aa52 242 /* write output */
emilmont 1:fdd22bb7aa52 243 pDst[2u * i] = (q15_t) outR;
emilmont 1:fdd22bb7aa52 244 pDst[(2u * i) + 1u] = outI >> 15u;
emilmont 1:fdd22bb7aa52 245
emilmont 1:fdd22bb7aa52 246 /* write complex conjugate output */
emilmont 1:fdd22bb7aa52 247 pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
emilmont 1:fdd22bb7aa52 248 pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
emilmont 1:fdd22bb7aa52 249
emilmont 1:fdd22bb7aa52 250 /* update coefficient pointer */
emilmont 1:fdd22bb7aa52 251 pCoefB = pCoefB + (2u * modifier);
emilmont 1:fdd22bb7aa52 252 pCoefA = pCoefA + (2u * modifier);
emilmont 1:fdd22bb7aa52 253
emilmont 1:fdd22bb7aa52 254 i++;
emilmont 1:fdd22bb7aa52 255
emilmont 1:fdd22bb7aa52 256 }
emilmont 1:fdd22bb7aa52 257
emilmont 1:fdd22bb7aa52 258 pDst[2u * fftLen] = pSrc[0] - pSrc[1];
emilmont 1:fdd22bb7aa52 259 pDst[(2u * fftLen) + 1u] = 0;
emilmont 1:fdd22bb7aa52 260
emilmont 1:fdd22bb7aa52 261 pDst[0] = pSrc[0] + pSrc[1];
emilmont 1:fdd22bb7aa52 262 pDst[1] = 0;
emilmont 1:fdd22bb7aa52 263
emilmont 1:fdd22bb7aa52 264
emilmont 1:fdd22bb7aa52 265 #else
emilmont 1:fdd22bb7aa52 266
emilmont 1:fdd22bb7aa52 267 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 268
emilmont 1:fdd22bb7aa52 269 i = 1u;
emilmont 1:fdd22bb7aa52 270
emilmont 1:fdd22bb7aa52 271 while(i < fftLen)
emilmont 1:fdd22bb7aa52 272 {
emilmont 1:fdd22bb7aa52 273 /*
emilmont 1:fdd22bb7aa52 274 outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
emilmont 1:fdd22bb7aa52 275 + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
emilmont 1:fdd22bb7aa52 276 pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
emilmont 1:fdd22bb7aa52 277 */
emilmont 1:fdd22bb7aa52 278
emilmont 1:fdd22bb7aa52 279 outR = *pSrc1 * *pCoefA;
emilmont 1:fdd22bb7aa52 280 outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
emilmont 1:fdd22bb7aa52 281 outR = outR + (*pSrc2 * *pCoefB);
emilmont 1:fdd22bb7aa52 282 outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
emilmont 1:fdd22bb7aa52 283
emilmont 1:fdd22bb7aa52 284
emilmont 1:fdd22bb7aa52 285 /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
emilmont 1:fdd22bb7aa52 286 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
emilmont 1:fdd22bb7aa52 287 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
emilmont 1:fdd22bb7aa52 288 */
emilmont 1:fdd22bb7aa52 289
emilmont 1:fdd22bb7aa52 290 outI = *pSrc2 * *(pCoefB + 1);
emilmont 1:fdd22bb7aa52 291 outI = outI - (*(pSrc2 + 1) * *pCoefB);
emilmont 1:fdd22bb7aa52 292 outI = outI + (*(pSrc1 + 1) * *pCoefA);
emilmont 1:fdd22bb7aa52 293 outI = outI + (*pSrc1 * *(pCoefA + 1));
emilmont 1:fdd22bb7aa52 294
emilmont 1:fdd22bb7aa52 295 /* update input pointers */
emilmont 1:fdd22bb7aa52 296 pSrc1 += 2u;
emilmont 1:fdd22bb7aa52 297 pSrc2 -= 2u;
emilmont 1:fdd22bb7aa52 298
emilmont 1:fdd22bb7aa52 299 /* write output */
emilmont 1:fdd22bb7aa52 300 pDst[2u * i] = (q15_t) outR;
emilmont 1:fdd22bb7aa52 301 pDst[(2u * i) + 1u] = outI >> 15u;
emilmont 1:fdd22bb7aa52 302
emilmont 1:fdd22bb7aa52 303 /* write complex conjugate output */
emilmont 1:fdd22bb7aa52 304 pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
emilmont 1:fdd22bb7aa52 305 pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
emilmont 1:fdd22bb7aa52 306
emilmont 1:fdd22bb7aa52 307 /* update coefficient pointer */
emilmont 1:fdd22bb7aa52 308 pCoefB = pCoefB + (2u * modifier);
emilmont 1:fdd22bb7aa52 309 pCoefA = pCoefA + (2u * modifier);
emilmont 1:fdd22bb7aa52 310
emilmont 1:fdd22bb7aa52 311 i++;
emilmont 1:fdd22bb7aa52 312
emilmont 1:fdd22bb7aa52 313 }
emilmont 1:fdd22bb7aa52 314
emilmont 1:fdd22bb7aa52 315 pDst[2u * fftLen] = pSrc[0] - pSrc[1];
emilmont 1:fdd22bb7aa52 316 pDst[(2u * fftLen) + 1u] = 0;
emilmont 1:fdd22bb7aa52 317
emilmont 1:fdd22bb7aa52 318 pDst[0] = pSrc[0] + pSrc[1];
emilmont 1:fdd22bb7aa52 319 pDst[1] = 0;
emilmont 1:fdd22bb7aa52 320
mbed_official 3:7a284390b0ce 321 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 322
emilmont 1:fdd22bb7aa52 323 }
emilmont 1:fdd22bb7aa52 324
emilmont 1:fdd22bb7aa52 325
emilmont 1:fdd22bb7aa52 326 /**
emilmont 1:fdd22bb7aa52 327 * @brief Core Real IFFT process
emilmont 2:da51fb522205 328 * @param[in] *pSrc points to the input buffer.
emilmont 2:da51fb522205 329 * @param[in] fftLen length of FFT.
emilmont 2:da51fb522205 330 * @param[in] *pATable points to the twiddle Coef A buffer.
emilmont 2:da51fb522205 331 * @param[in] *pBTable points to the twiddle Coef B buffer.
emilmont 2:da51fb522205 332 * @param[out] *pDst points to the output buffer.
emilmont 2:da51fb522205 333 * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
emilmont 1:fdd22bb7aa52 334 * @return none.
emilmont 1:fdd22bb7aa52 335 * The function implements a Real IFFT
emilmont 1:fdd22bb7aa52 336 */
emilmont 1:fdd22bb7aa52 337 void arm_split_rifft_q15(
emilmont 1:fdd22bb7aa52 338 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 339 uint32_t fftLen,
emilmont 1:fdd22bb7aa52 340 q15_t * pATable,
emilmont 1:fdd22bb7aa52 341 q15_t * pBTable,
emilmont 1:fdd22bb7aa52 342 q15_t * pDst,
emilmont 1:fdd22bb7aa52 343 uint32_t modifier)
emilmont 1:fdd22bb7aa52 344 {
emilmont 1:fdd22bb7aa52 345 uint32_t i; /* Loop Counter */
emilmont 1:fdd22bb7aa52 346 q31_t outR, outI; /* Temporary variables for output */
emilmont 1:fdd22bb7aa52 347 q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
emilmont 1:fdd22bb7aa52 348 q15_t *pSrc1, *pSrc2;
emilmont 1:fdd22bb7aa52 349 q15_t *pDst1 = &pDst[0];
emilmont 1:fdd22bb7aa52 350
emilmont 1:fdd22bb7aa52 351 pCoefA = &pATable[0];
emilmont 1:fdd22bb7aa52 352 pCoefB = &pBTable[0];
emilmont 1:fdd22bb7aa52 353
emilmont 1:fdd22bb7aa52 354 pSrc1 = &pSrc[0];
emilmont 1:fdd22bb7aa52 355 pSrc2 = &pSrc[2u * fftLen];
emilmont 1:fdd22bb7aa52 356
mbed_official 3:7a284390b0ce 357 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 358
emilmont 1:fdd22bb7aa52 359 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 360
emilmont 1:fdd22bb7aa52 361 i = fftLen;
emilmont 1:fdd22bb7aa52 362
emilmont 1:fdd22bb7aa52 363 while(i > 0u)
emilmont 1:fdd22bb7aa52 364 {
emilmont 1:fdd22bb7aa52 365
emilmont 1:fdd22bb7aa52 366 /*
emilmont 1:fdd22bb7aa52 367 outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
emilmont 1:fdd22bb7aa52 368 pIn[2 * n - 2 * i] * pBTable[2 * i] -
emilmont 1:fdd22bb7aa52 369 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
emilmont 1:fdd22bb7aa52 370
emilmont 1:fdd22bb7aa52 371 outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
emilmont 1:fdd22bb7aa52 372 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
emilmont 1:fdd22bb7aa52 373 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
emilmont 1:fdd22bb7aa52 374
emilmont 1:fdd22bb7aa52 375 */
emilmont 1:fdd22bb7aa52 376
emilmont 1:fdd22bb7aa52 377
emilmont 1:fdd22bb7aa52 378 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 379
emilmont 1:fdd22bb7aa52 380 /* pIn[2 * n - 2 * i] * pBTable[2 * i] -
emilmont 1:fdd22bb7aa52 381 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
emilmont 1:fdd22bb7aa52 382 outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
emilmont 1:fdd22bb7aa52 383
emilmont 1:fdd22bb7aa52 384 #else
emilmont 1:fdd22bb7aa52 385
emilmont 1:fdd22bb7aa52 386 /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +
emilmont 1:fdd22bb7aa52 387 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
emilmont 1:fdd22bb7aa52 388 outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
emilmont 1:fdd22bb7aa52 389
emilmont 1:fdd22bb7aa52 390 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 391
emilmont 1:fdd22bb7aa52 392 /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
emilmont 1:fdd22bb7aa52 393 pIn[2 * n - 2 * i] * pBTable[2 * i] */
emilmont 1:fdd22bb7aa52 394 outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
emilmont 1:fdd22bb7aa52 395
emilmont 1:fdd22bb7aa52 396 /*
emilmont 1:fdd22bb7aa52 397 -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +
emilmont 1:fdd22bb7aa52 398 pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
emilmont 1:fdd22bb7aa52 399 outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
emilmont 1:fdd22bb7aa52 400
emilmont 1:fdd22bb7aa52 401 /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
emilmont 1:fdd22bb7aa52 402
emilmont 1:fdd22bb7aa52 403 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 404
emilmont 1:fdd22bb7aa52 405 outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
emilmont 1:fdd22bb7aa52 406
emilmont 1:fdd22bb7aa52 407 #else
emilmont 1:fdd22bb7aa52 408
emilmont 1:fdd22bb7aa52 409 outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
emilmont 1:fdd22bb7aa52 410
emilmont 1:fdd22bb7aa52 411 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 412 /* write output */
emilmont 1:fdd22bb7aa52 413
emilmont 1:fdd22bb7aa52 414 #ifndef ARM_MATH_BIG_ENDIAN
emilmont 1:fdd22bb7aa52 415
emilmont 1:fdd22bb7aa52 416 *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
emilmont 1:fdd22bb7aa52 417
emilmont 1:fdd22bb7aa52 418 #else
emilmont 1:fdd22bb7aa52 419
emilmont 1:fdd22bb7aa52 420 *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
emilmont 1:fdd22bb7aa52 421
emilmont 1:fdd22bb7aa52 422 #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
emilmont 1:fdd22bb7aa52 423
emilmont 1:fdd22bb7aa52 424 /* update coefficient pointer */
emilmont 1:fdd22bb7aa52 425 pCoefB = pCoefB + (2u * modifier);
emilmont 1:fdd22bb7aa52 426 pCoefA = pCoefA + (2u * modifier);
emilmont 1:fdd22bb7aa52 427
emilmont 1:fdd22bb7aa52 428 i--;
emilmont 1:fdd22bb7aa52 429
emilmont 1:fdd22bb7aa52 430 }
emilmont 1:fdd22bb7aa52 431
emilmont 1:fdd22bb7aa52 432
emilmont 1:fdd22bb7aa52 433 #else
emilmont 1:fdd22bb7aa52 434
emilmont 1:fdd22bb7aa52 435 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 436
emilmont 1:fdd22bb7aa52 437 i = fftLen;
emilmont 1:fdd22bb7aa52 438
emilmont 1:fdd22bb7aa52 439 while(i > 0u)
emilmont 1:fdd22bb7aa52 440 {
emilmont 1:fdd22bb7aa52 441
emilmont 1:fdd22bb7aa52 442 /*
emilmont 1:fdd22bb7aa52 443 outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
emilmont 1:fdd22bb7aa52 444 pIn[2 * n - 2 * i] * pBTable[2 * i] -
emilmont 1:fdd22bb7aa52 445 pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
emilmont 1:fdd22bb7aa52 446 */
emilmont 1:fdd22bb7aa52 447
emilmont 1:fdd22bb7aa52 448 outR = *pSrc2 * *pCoefB;
emilmont 1:fdd22bb7aa52 449 outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
emilmont 1:fdd22bb7aa52 450 outR = outR + (*pSrc1 * *pCoefA);
emilmont 1:fdd22bb7aa52 451 outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
emilmont 1:fdd22bb7aa52 452
emilmont 1:fdd22bb7aa52 453 /*
emilmont 1:fdd22bb7aa52 454 outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
emilmont 1:fdd22bb7aa52 455 pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
emilmont 1:fdd22bb7aa52 456 pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
emilmont 1:fdd22bb7aa52 457 */
emilmont 1:fdd22bb7aa52 458
emilmont 1:fdd22bb7aa52 459 outI = *(pSrc1 + 1) * *pCoefA;
emilmont 1:fdd22bb7aa52 460 outI = outI - (*pSrc1 * *(pCoefA + 1));
emilmont 1:fdd22bb7aa52 461 outI = outI - (*pSrc2 * *(pCoefB + 1));
emilmont 1:fdd22bb7aa52 462 outI = outI - (*(pSrc2 + 1) * *(pCoefB));
emilmont 1:fdd22bb7aa52 463
emilmont 1:fdd22bb7aa52 464 /* update input pointers */
emilmont 1:fdd22bb7aa52 465 pSrc1 += 2u;
emilmont 1:fdd22bb7aa52 466 pSrc2 -= 2u;
emilmont 1:fdd22bb7aa52 467
emilmont 1:fdd22bb7aa52 468 /* write output */
emilmont 1:fdd22bb7aa52 469 *pDst1++ = (q15_t) outR;
emilmont 1:fdd22bb7aa52 470 *pDst1++ = (q15_t) (outI >> 15);
emilmont 1:fdd22bb7aa52 471
emilmont 1:fdd22bb7aa52 472 /* update coefficient pointer */
emilmont 1:fdd22bb7aa52 473 pCoefB = pCoefB + (2u * modifier);
emilmont 1:fdd22bb7aa52 474 pCoefA = pCoefA + (2u * modifier);
emilmont 1:fdd22bb7aa52 475
emilmont 1:fdd22bb7aa52 476 i--;
emilmont 1:fdd22bb7aa52 477
emilmont 1:fdd22bb7aa52 478 }
emilmont 1:fdd22bb7aa52 479
mbed_official 3:7a284390b0ce 480 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 481
emilmont 1:fdd22bb7aa52 482 }