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CMSIS DSP library

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cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c@5:3762170b6d4d, 2015-11-20 (annotated)

Committer:
mbed_official
Date:
Fri Nov 20 08:45:18 2015 +0000
Revision:
5:3762170b6d4d
Parent:
3:7a284390b0ce 
Synchronized with git revision 2eb940b9a73af188d3004a2575fdfbb05febe62b



Full URL: https://github.com/mbedmicro/mbed/commit/2eb940b9a73af188d3004a2575fdfbb05febe62b/



Added option to build rpc library. closes #1426

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 5:3762170b6d4d 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 5:3762170b6d4d 4 * $Date: 19. March 2015
mbed_official 5:3762170b6d4d 5 * $Revision: V.1.4.5
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_biquad_cascade_df1_f32.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Processing function for the
emilmont 1:fdd22bb7aa52 11 * floating-point Biquad cascade DirectFormI(DF1) filter.
emilmont 1:fdd22bb7aa52 12 *
emilmont 1:fdd22bb7aa52 13 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 14 *
mbed_official 3:7a284390b0ce 15 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 16 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 17 * are met:
mbed_official 3:7a284390b0ce 18 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 19 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 20 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 21 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 22 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 23 * distribution.
mbed_official 3:7a284390b0ce 24 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 25 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 26 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 27 *
mbed_official 3:7a284390b0ce 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 31 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 32 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 34 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 35 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 39 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 40 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 41
emilmont 1:fdd22bb7aa52 42 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 43
emilmont 1:fdd22bb7aa52 44 /**
emilmont 1:fdd22bb7aa52 45 * @ingroup groupFilters
emilmont 1:fdd22bb7aa52 46 */
emilmont 1:fdd22bb7aa52 47
emilmont 1:fdd22bb7aa52 48 /**
emilmont 1:fdd22bb7aa52 49 * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
emilmont 1:fdd22bb7aa52 50 *
emilmont 1:fdd22bb7aa52 51 * This set of functions implements arbitrary order recursive (IIR) filters.
emilmont 1:fdd22bb7aa52 52 * The filters are implemented as a cascade of second order Biquad sections.
emilmont 1:fdd22bb7aa52 53 * The functions support Q15, Q31 and floating-point data types.
emilmont 1:fdd22bb7aa52 54 * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
emilmont 1:fdd22bb7aa52 55 *
emilmont 1:fdd22bb7aa52 56 * The functions operate on blocks of input and output data and each call to the function
emilmont 1:fdd22bb7aa52 57 * processes <code>blockSize</code> samples through the filter.
emilmont 1:fdd22bb7aa52 58 * <code>pSrc</code> points to the array of input data and
emilmont 1:fdd22bb7aa52 59 * <code>pDst</code> points to the array of output data.
emilmont 1:fdd22bb7aa52 60 * Both arrays contain <code>blockSize</code> values.
emilmont 1:fdd22bb7aa52 61 *
emilmont 1:fdd22bb7aa52 62 * \par Algorithm
emilmont 1:fdd22bb7aa52 63 * Each Biquad stage implements a second order filter using the difference equation:
emilmont 1:fdd22bb7aa52 64 * <pre>
emilmont 1:fdd22bb7aa52 65 * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
emilmont 1:fdd22bb7aa52 66 * </pre>
emilmont 1:fdd22bb7aa52 67 * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
emilmont 1:fdd22bb7aa52 68 * \image html Biquad.gif "Single Biquad filter stage"
emilmont 1:fdd22bb7aa52 69 * Coefficients <code>b0, b1 and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
emilmont 1:fdd22bb7aa52 70 * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
emilmont 1:fdd22bb7aa52 71 * Pay careful attention to the sign of the feedback coefficients.
emilmont 1:fdd22bb7aa52 72 * Some design tools use the difference equation
emilmont 1:fdd22bb7aa52 73 * <pre>
emilmont 1:fdd22bb7aa52 74 * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
emilmont 1:fdd22bb7aa52 75 * </pre>
emilmont 1:fdd22bb7aa52 76 * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
emilmont 1:fdd22bb7aa52 77 *
emilmont 1:fdd22bb7aa52 78 * \par
emilmont 1:fdd22bb7aa52 79 * Higher order filters are realized as a cascade of second order sections.
emilmont 1:fdd22bb7aa52 80 * <code>numStages</code> refers to the number of second order stages used.
emilmont 1:fdd22bb7aa52 81 * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
emilmont 1:fdd22bb7aa52 82 * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
emilmont 1:fdd22bb7aa52 83 * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
emilmont 1:fdd22bb7aa52 84 *
emilmont 1:fdd22bb7aa52 85 * \par
emilmont 1:fdd22bb7aa52 86 * The <code>pState</code> points to state variables array.
emilmont 1:fdd22bb7aa52 87 * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
emilmont 1:fdd22bb7aa52 88 * The state variables are arranged in the <code>pState</code> array as:
emilmont 1:fdd22bb7aa52 89 * <pre>
emilmont 1:fdd22bb7aa52 90 * {x[n-1], x[n-2], y[n-1], y[n-2]}
emilmont 1:fdd22bb7aa52 91 * </pre>
emilmont 1:fdd22bb7aa52 92 *
emilmont 1:fdd22bb7aa52 93 * \par
emilmont 1:fdd22bb7aa52 94 * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
emilmont 1:fdd22bb7aa52 95 * The state array has a total length of <code>4*numStages</code> values.
emilmont 1:fdd22bb7aa52 96 * The state variables are updated after each block of data is processed, the coefficients are untouched.
emilmont 1:fdd22bb7aa52 97 *
emilmont 1:fdd22bb7aa52 98 * \par Instance Structure
emilmont 1:fdd22bb7aa52 99 * The coefficients and state variables for a filter are stored together in an instance data structure.
emilmont 1:fdd22bb7aa52 100 * A separate instance structure must be defined for each filter.
emilmont 1:fdd22bb7aa52 101 * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
emilmont 1:fdd22bb7aa52 102 * There are separate instance structure declarations for each of the 3 supported data types.
emilmont 1:fdd22bb7aa52 103 *
emilmont 1:fdd22bb7aa52 104 * \par Init Functions
emilmont 1:fdd22bb7aa52 105 * There is also an associated initialization function for each data type.
emilmont 1:fdd22bb7aa52 106 * The initialization function performs following operations:
emilmont 1:fdd22bb7aa52 107 * - Sets the values of the internal structure fields.
emilmont 1:fdd22bb7aa52 108 * - Zeros out the values in the state buffer.
mbed_official 3:7a284390b0ce 109 * To do this manually without calling the init function, assign the follow subfields of the instance structure:
mbed_official 3:7a284390b0ce 110 * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
emilmont 1:fdd22bb7aa52 111 *
emilmont 1:fdd22bb7aa52 112 * \par
emilmont 1:fdd22bb7aa52 113 * Use of the initialization function is optional.
emilmont 1:fdd22bb7aa52 114 * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
emilmont 1:fdd22bb7aa52 115 * To place an instance structure into a const data section, the instance structure must be manually initialized.
emilmont 1:fdd22bb7aa52 116 * Set the values in the state buffer to zeros before static initialization.
emilmont 1:fdd22bb7aa52 117 * The code below statically initializes each of the 3 different data type filter instance structures
emilmont 1:fdd22bb7aa52 118 * <pre>
emilmont 1:fdd22bb7aa52 119 * arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
emilmont 1:fdd22bb7aa52 120 * arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
emilmont 1:fdd22bb7aa52 121 * arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
emilmont 1:fdd22bb7aa52 122 * </pre>
emilmont 1:fdd22bb7aa52 123 * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;
emilmont 1:fdd22bb7aa52 124 * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied.
emilmont 1:fdd22bb7aa52 125 *
emilmont 1:fdd22bb7aa52 126 * \par Fixed-Point Behavior
emilmont 1:fdd22bb7aa52 127 * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
emilmont 1:fdd22bb7aa52 128 * Following issues must be considered:
emilmont 1:fdd22bb7aa52 129 * - Scaling of coefficients
emilmont 1:fdd22bb7aa52 130 * - Filter gain
emilmont 1:fdd22bb7aa52 131 * - Overflow and saturation
emilmont 1:fdd22bb7aa52 132 *
emilmont 1:fdd22bb7aa52 133 * \par
emilmont 1:fdd22bb7aa52 134 * <b>Scaling of coefficients: </b>
emilmont 1:fdd22bb7aa52 135 * Filter coefficients are represented as fractional values and
emilmont 1:fdd22bb7aa52 136 * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
emilmont 1:fdd22bb7aa52 137 * The fixed-point functions have an additional scaling parameter <code>postShift</code>
emilmont 1:fdd22bb7aa52 138 * which allow the filter coefficients to exceed the range <code>[+1 -1)</code>.
emilmont 1:fdd22bb7aa52 139 * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
emilmont 1:fdd22bb7aa52 140 * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
emilmont 1:fdd22bb7aa52 141 * This essentially scales the filter coefficients by <code>2^postShift</code>.
emilmont 1:fdd22bb7aa52 142 * For example, to realize the coefficients
emilmont 1:fdd22bb7aa52 143 * <pre>
emilmont 1:fdd22bb7aa52 144 * {1.5, -0.8, 1.2, 1.6, -0.9}
emilmont 1:fdd22bb7aa52 145 * </pre>
emilmont 1:fdd22bb7aa52 146 * set the pCoeffs array to:
emilmont 1:fdd22bb7aa52 147 * <pre>
emilmont 1:fdd22bb7aa52 148 * {0.75, -0.4, 0.6, 0.8, -0.45}
emilmont 1:fdd22bb7aa52 149 * </pre>
emilmont 1:fdd22bb7aa52 150 * and set <code>postShift=1</code>
emilmont 1:fdd22bb7aa52 151 *
emilmont 1:fdd22bb7aa52 152 * \par
emilmont 1:fdd22bb7aa52 153 * <b>Filter gain: </b>
emilmont 1:fdd22bb7aa52 154 * The frequency response of a Biquad filter is a function of its coefficients.
emilmont 1:fdd22bb7aa52 155 * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
emilmont 1:fdd22bb7aa52 156 * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
emilmont 1:fdd22bb7aa52 157 * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
emilmont 1:fdd22bb7aa52 158 *
emilmont 1:fdd22bb7aa52 159 * \par
emilmont 1:fdd22bb7aa52 160 * <b>Overflow and saturation: </b>
emilmont 1:fdd22bb7aa52 161 * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
emilmont 1:fdd22bb7aa52 162 */
emilmont 1:fdd22bb7aa52 163
emilmont 1:fdd22bb7aa52 164 /**
emilmont 1:fdd22bb7aa52 165 * @addtogroup BiquadCascadeDF1
emilmont 1:fdd22bb7aa52 166 * @{
emilmont 1:fdd22bb7aa52 167 */
emilmont 1:fdd22bb7aa52 168
emilmont 1:fdd22bb7aa52 169 /**
emilmont 1:fdd22bb7aa52 170 * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
emilmont 1:fdd22bb7aa52 171 * @param[in] *pSrc points to the block of input data.
emilmont 1:fdd22bb7aa52 172 * @param[out] *pDst points to the block of output data.
emilmont 1:fdd22bb7aa52 173 * @param[in] blockSize number of samples to process per call.
emilmont 1:fdd22bb7aa52 174 * @return none.
emilmont 1:fdd22bb7aa52 175 *
emilmont 1:fdd22bb7aa52 176 */
emilmont 1:fdd22bb7aa52 177
emilmont 1:fdd22bb7aa52 178 void arm_biquad_cascade_df1_f32(
emilmont 1:fdd22bb7aa52 179 const arm_biquad_casd_df1_inst_f32 * S,
emilmont 1:fdd22bb7aa52 180 float32_t * pSrc,
emilmont 1:fdd22bb7aa52 181 float32_t * pDst,
emilmont 1:fdd22bb7aa52 182 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 183 {
emilmont 1:fdd22bb7aa52 184 float32_t *pIn = pSrc; /* source pointer */
emilmont 1:fdd22bb7aa52 185 float32_t *pOut = pDst; /* destination pointer */
emilmont 1:fdd22bb7aa52 186 float32_t *pState = S->pState; /* pState pointer */
emilmont 1:fdd22bb7aa52 187 float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
emilmont 1:fdd22bb7aa52 188 float32_t acc; /* Simulates the accumulator */
emilmont 1:fdd22bb7aa52 189 float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
emilmont 1:fdd22bb7aa52 190 float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
emilmont 1:fdd22bb7aa52 191 float32_t Xn; /* temporary input */
emilmont 1:fdd22bb7aa52 192 uint32_t sample, stage = S->numStages; /* loop counters */
emilmont 1:fdd22bb7aa52 193
emilmont 1:fdd22bb7aa52 194
mbed_official 3:7a284390b0ce 195 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 196
emilmont 1:fdd22bb7aa52 197 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 198
emilmont 1:fdd22bb7aa52 199 do
emilmont 1:fdd22bb7aa52 200 {
emilmont 1:fdd22bb7aa52 201 /* Reading the coefficients */
emilmont 1:fdd22bb7aa52 202 b0 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 203 b1 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 204 b2 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 205 a1 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 206 a2 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 207
emilmont 1:fdd22bb7aa52 208 /* Reading the pState values */
emilmont 1:fdd22bb7aa52 209 Xn1 = pState[0];
emilmont 1:fdd22bb7aa52 210 Xn2 = pState[1];
emilmont 1:fdd22bb7aa52 211 Yn1 = pState[2];
emilmont 1:fdd22bb7aa52 212 Yn2 = pState[3];
emilmont 1:fdd22bb7aa52 213
emilmont 1:fdd22bb7aa52 214 /* Apply loop unrolling and compute 4 output values simultaneously. */
emilmont 1:fdd22bb7aa52 215 /* The variable acc hold output values that are being computed:
emilmont 1:fdd22bb7aa52 216 *
emilmont 1:fdd22bb7aa52 217 * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
emilmont 1:fdd22bb7aa52 218 * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
emilmont 1:fdd22bb7aa52 219 * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
emilmont 1:fdd22bb7aa52 220 * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
emilmont 1:fdd22bb7aa52 221 */
emilmont 1:fdd22bb7aa52 222
emilmont 1:fdd22bb7aa52 223 sample = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 224
emilmont 1:fdd22bb7aa52 225 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 226 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 227 while(sample > 0u)
emilmont 1:fdd22bb7aa52 228 {
emilmont 1:fdd22bb7aa52 229 /* Read the first input */
emilmont 1:fdd22bb7aa52 230 Xn = *pIn++;
emilmont 1:fdd22bb7aa52 231
emilmont 1:fdd22bb7aa52 232 /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
emilmont 1:fdd22bb7aa52 233 Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
emilmont 1:fdd22bb7aa52 234
emilmont 1:fdd22bb7aa52 235 /* Store the result in the accumulator in the destination buffer. */
emilmont 1:fdd22bb7aa52 236 *pOut++ = Yn2;
emilmont 1:fdd22bb7aa52 237
emilmont 1:fdd22bb7aa52 238 /* Every time after the output is computed state should be updated. */
emilmont 1:fdd22bb7aa52 239 /* The states should be updated as: */
emilmont 1:fdd22bb7aa52 240 /* Xn2 = Xn1 */
emilmont 1:fdd22bb7aa52 241 /* Xn1 = Xn */
emilmont 1:fdd22bb7aa52 242 /* Yn2 = Yn1 */
emilmont 1:fdd22bb7aa52 243 /* Yn1 = acc */
emilmont 1:fdd22bb7aa52 244
emilmont 1:fdd22bb7aa52 245 /* Read the second input */
emilmont 1:fdd22bb7aa52 246 Xn2 = *pIn++;
emilmont 1:fdd22bb7aa52 247
emilmont 1:fdd22bb7aa52 248 /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
emilmont 1:fdd22bb7aa52 249 Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
emilmont 1:fdd22bb7aa52 250
emilmont 1:fdd22bb7aa52 251 /* Store the result in the accumulator in the destination buffer. */
emilmont 1:fdd22bb7aa52 252 *pOut++ = Yn1;
emilmont 1:fdd22bb7aa52 253
emilmont 1:fdd22bb7aa52 254 /* Every time after the output is computed state should be updated. */
emilmont 1:fdd22bb7aa52 255 /* The states should be updated as: */
emilmont 1:fdd22bb7aa52 256 /* Xn2 = Xn1 */
emilmont 1:fdd22bb7aa52 257 /* Xn1 = Xn */
emilmont 1:fdd22bb7aa52 258 /* Yn2 = Yn1 */
emilmont 1:fdd22bb7aa52 259 /* Yn1 = acc */
emilmont 1:fdd22bb7aa52 260
emilmont 1:fdd22bb7aa52 261 /* Read the third input */
emilmont 1:fdd22bb7aa52 262 Xn1 = *pIn++;
emilmont 1:fdd22bb7aa52 263
emilmont 1:fdd22bb7aa52 264 /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
emilmont 1:fdd22bb7aa52 265 Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
emilmont 1:fdd22bb7aa52 266
emilmont 1:fdd22bb7aa52 267 /* Store the result in the accumulator in the destination buffer. */
emilmont 1:fdd22bb7aa52 268 *pOut++ = Yn2;
emilmont 1:fdd22bb7aa52 269
emilmont 1:fdd22bb7aa52 270 /* Every time after the output is computed state should be updated. */
emilmont 1:fdd22bb7aa52 271 /* The states should be updated as: */
emilmont 1:fdd22bb7aa52 272 /* Xn2 = Xn1 */
emilmont 1:fdd22bb7aa52 273 /* Xn1 = Xn */
emilmont 1:fdd22bb7aa52 274 /* Yn2 = Yn1 */
emilmont 1:fdd22bb7aa52 275 /* Yn1 = acc */
emilmont 1:fdd22bb7aa52 276
emilmont 1:fdd22bb7aa52 277 /* Read the forth input */
emilmont 1:fdd22bb7aa52 278 Xn = *pIn++;
emilmont 1:fdd22bb7aa52 279
emilmont 1:fdd22bb7aa52 280 /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
emilmont 1:fdd22bb7aa52 281 Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
emilmont 1:fdd22bb7aa52 282
emilmont 1:fdd22bb7aa52 283 /* Store the result in the accumulator in the destination buffer. */
emilmont 1:fdd22bb7aa52 284 *pOut++ = Yn1;
emilmont 1:fdd22bb7aa52 285
emilmont 1:fdd22bb7aa52 286 /* Every time after the output is computed state should be updated. */
emilmont 1:fdd22bb7aa52 287 /* The states should be updated as: */
emilmont 1:fdd22bb7aa52 288 /* Xn2 = Xn1 */
emilmont 1:fdd22bb7aa52 289 /* Xn1 = Xn */
emilmont 1:fdd22bb7aa52 290 /* Yn2 = Yn1 */
emilmont 1:fdd22bb7aa52 291 /* Yn1 = acc */
emilmont 1:fdd22bb7aa52 292 Xn2 = Xn1;
emilmont 1:fdd22bb7aa52 293 Xn1 = Xn;
emilmont 1:fdd22bb7aa52 294
emilmont 1:fdd22bb7aa52 295 /* decrement the loop counter */
emilmont 1:fdd22bb7aa52 296 sample--;
emilmont 1:fdd22bb7aa52 297
emilmont 1:fdd22bb7aa52 298 }
emilmont 1:fdd22bb7aa52 299
emilmont 1:fdd22bb7aa52 300 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 301 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 302 sample = blockSize & 0x3u;
emilmont 1:fdd22bb7aa52 303
emilmont 1:fdd22bb7aa52 304 while(sample > 0u)
emilmont 1:fdd22bb7aa52 305 {
emilmont 1:fdd22bb7aa52 306 /* Read the input */
emilmont 1:fdd22bb7aa52 307 Xn = *pIn++;
emilmont 1:fdd22bb7aa52 308
emilmont 1:fdd22bb7aa52 309 /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
emilmont 1:fdd22bb7aa52 310 acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
emilmont 1:fdd22bb7aa52 311
emilmont 1:fdd22bb7aa52 312 /* Store the result in the accumulator in the destination buffer. */
emilmont 1:fdd22bb7aa52 313 *pOut++ = acc;
emilmont 1:fdd22bb7aa52 314
emilmont 1:fdd22bb7aa52 315 /* Every time after the output is computed state should be updated. */
emilmont 1:fdd22bb7aa52 316 /* The states should be updated as: */
emilmont 1:fdd22bb7aa52 317 /* Xn2 = Xn1 */
emilmont 1:fdd22bb7aa52 318 /* Xn1 = Xn */
emilmont 1:fdd22bb7aa52 319 /* Yn2 = Yn1 */
emilmont 1:fdd22bb7aa52 320 /* Yn1 = acc */
emilmont 1:fdd22bb7aa52 321 Xn2 = Xn1;
emilmont 1:fdd22bb7aa52 322 Xn1 = Xn;
emilmont 1:fdd22bb7aa52 323 Yn2 = Yn1;
emilmont 1:fdd22bb7aa52 324 Yn1 = acc;
emilmont 1:fdd22bb7aa52 325
emilmont 1:fdd22bb7aa52 326 /* decrement the loop counter */
emilmont 1:fdd22bb7aa52 327 sample--;
emilmont 1:fdd22bb7aa52 328
emilmont 1:fdd22bb7aa52 329 }
emilmont 1:fdd22bb7aa52 330
emilmont 1:fdd22bb7aa52 331 /* Store the updated state variables back into the pState array */
emilmont 1:fdd22bb7aa52 332 *pState++ = Xn1;
emilmont 1:fdd22bb7aa52 333 *pState++ = Xn2;
emilmont 1:fdd22bb7aa52 334 *pState++ = Yn1;
emilmont 1:fdd22bb7aa52 335 *pState++ = Yn2;
emilmont 1:fdd22bb7aa52 336
emilmont 1:fdd22bb7aa52 337 /* The first stage goes from the input buffer to the output buffer. */
emilmont 1:fdd22bb7aa52 338 /* Subsequent numStages occur in-place in the output buffer */
emilmont 1:fdd22bb7aa52 339 pIn = pDst;
emilmont 1:fdd22bb7aa52 340
emilmont 1:fdd22bb7aa52 341 /* Reset the output pointer */
emilmont 1:fdd22bb7aa52 342 pOut = pDst;
emilmont 1:fdd22bb7aa52 343
emilmont 1:fdd22bb7aa52 344 /* decrement the loop counter */
emilmont 1:fdd22bb7aa52 345 stage--;
emilmont 1:fdd22bb7aa52 346
emilmont 1:fdd22bb7aa52 347 } while(stage > 0u);
emilmont 1:fdd22bb7aa52 348
emilmont 1:fdd22bb7aa52 349 #else
emilmont 1:fdd22bb7aa52 350
emilmont 1:fdd22bb7aa52 351 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 352
emilmont 1:fdd22bb7aa52 353 do
emilmont 1:fdd22bb7aa52 354 {
emilmont 1:fdd22bb7aa52 355 /* Reading the coefficients */
emilmont 1:fdd22bb7aa52 356 b0 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 357 b1 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 358 b2 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 359 a1 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 360 a2 = *pCoeffs++;
emilmont 1:fdd22bb7aa52 361
emilmont 1:fdd22bb7aa52 362 /* Reading the pState values */
emilmont 1:fdd22bb7aa52 363 Xn1 = pState[0];
emilmont 1:fdd22bb7aa52 364 Xn2 = pState[1];
emilmont 1:fdd22bb7aa52 365 Yn1 = pState[2];
emilmont 1:fdd22bb7aa52 366 Yn2 = pState[3];
emilmont 1:fdd22bb7aa52 367
emilmont 1:fdd22bb7aa52 368 /* The variables acc holds the output value that is computed:
emilmont 1:fdd22bb7aa52 369 * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
emilmont 1:fdd22bb7aa52 370 */
emilmont 1:fdd22bb7aa52 371
emilmont 1:fdd22bb7aa52 372 sample = blockSize;
emilmont 1:fdd22bb7aa52 373
emilmont 1:fdd22bb7aa52 374 while(sample > 0u)
emilmont 1:fdd22bb7aa52 375 {
emilmont 1:fdd22bb7aa52 376 /* Read the input */
emilmont 1:fdd22bb7aa52 377 Xn = *pIn++;
emilmont 1:fdd22bb7aa52 378
emilmont 1:fdd22bb7aa52 379 /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
emilmont 1:fdd22bb7aa52 380 acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
emilmont 1:fdd22bb7aa52 381
emilmont 1:fdd22bb7aa52 382 /* Store the result in the accumulator in the destination buffer. */
emilmont 1:fdd22bb7aa52 383 *pOut++ = acc;
emilmont 1:fdd22bb7aa52 384
emilmont 1:fdd22bb7aa52 385 /* Every time after the output is computed state should be updated. */
emilmont 1:fdd22bb7aa52 386 /* The states should be updated as: */
emilmont 1:fdd22bb7aa52 387 /* Xn2 = Xn1 */
emilmont 1:fdd22bb7aa52 388 /* Xn1 = Xn */
emilmont 1:fdd22bb7aa52 389 /* Yn2 = Yn1 */
emilmont 1:fdd22bb7aa52 390 /* Yn1 = acc */
emilmont 1:fdd22bb7aa52 391 Xn2 = Xn1;
emilmont 1:fdd22bb7aa52 392 Xn1 = Xn;
emilmont 1:fdd22bb7aa52 393 Yn2 = Yn1;
emilmont 1:fdd22bb7aa52 394 Yn1 = acc;
emilmont 1:fdd22bb7aa52 395
emilmont 1:fdd22bb7aa52 396 /* decrement the loop counter */
emilmont 1:fdd22bb7aa52 397 sample--;
emilmont 1:fdd22bb7aa52 398 }
emilmont 1:fdd22bb7aa52 399
emilmont 1:fdd22bb7aa52 400 /* Store the updated state variables back into the pState array */
emilmont 1:fdd22bb7aa52 401 *pState++ = Xn1;
emilmont 1:fdd22bb7aa52 402 *pState++ = Xn2;
emilmont 1:fdd22bb7aa52 403 *pState++ = Yn1;
emilmont 1:fdd22bb7aa52 404 *pState++ = Yn2;
emilmont 1:fdd22bb7aa52 405
emilmont 1:fdd22bb7aa52 406 /* The first stage goes from the input buffer to the output buffer. */
emilmont 1:fdd22bb7aa52 407 /* Subsequent numStages occur in-place in the output buffer */
emilmont 1:fdd22bb7aa52 408 pIn = pDst;
emilmont 1:fdd22bb7aa52 409
emilmont 1:fdd22bb7aa52 410 /* Reset the output pointer */
emilmont 1:fdd22bb7aa52 411 pOut = pDst;
emilmont 1:fdd22bb7aa52 412
emilmont 1:fdd22bb7aa52 413 /* decrement the loop counter */
emilmont 1:fdd22bb7aa52 414 stage--;
emilmont 1:fdd22bb7aa52 415
emilmont 1:fdd22bb7aa52 416 } while(stage > 0u);
emilmont 1:fdd22bb7aa52 417
mbed_official 3:7a284390b0ce 418 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 419
emilmont 1:fdd22bb7aa52 420 }
emilmont 1:fdd22bb7aa52 421
emilmont 1:fdd22bb7aa52 422
emilmont 1:fdd22bb7aa52 423 /**
emilmont 1:fdd22bb7aa52 424 * @} end of BiquadCascadeDF1 group
emilmont 1:fdd22bb7aa52 425 */