Kevin Braun / lwip-eth-patch

Patch for EthernetInterface library using the K64F

arch/TARGET_NXP/lpc17xx_emac.h@0:87a63595da37, 2014-06-30 (annotated)

Committer:
loopsva
Date:
Mon Jun 30 17:27:46 2014 +0000
Revision:
0:87a63595da37
Patch for EthernetInterface using the K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
loopsva 0:87a63595da37 1 /**********************************************************************
loopsva 0:87a63595da37 2 * $Id$ lpc17xx_emac.h 2010-05-21
loopsva 0:87a63595da37 3 *//**
loopsva 0:87a63595da37 4 * @file lpc17xx_emac.h
loopsva 0:87a63595da37 5 * @brief Contains all macro definitions and function prototypes
loopsva 0:87a63595da37 6 * support for Ethernet MAC firmware library on LPC17xx
loopsva 0:87a63595da37 7 * @version 2.0
loopsva 0:87a63595da37 8 * @date 21. May. 2010
loopsva 0:87a63595da37 9 * @author NXP MCU SW Application Team
loopsva 0:87a63595da37 10 *
loopsva 0:87a63595da37 11 * Copyright(C) 2010, NXP Semiconductor
loopsva 0:87a63595da37 12 * All rights reserved.
loopsva 0:87a63595da37 13 *
loopsva 0:87a63595da37 14 ***********************************************************************
loopsva 0:87a63595da37 15 * Software that is described herein is for illustrative purposes only
loopsva 0:87a63595da37 16 * which provides customers with programming information regarding the
loopsva 0:87a63595da37 17 * products. This software is supplied "AS IS" without any warranties.
loopsva 0:87a63595da37 18 * NXP Semiconductors assumes no responsibility or liability for the
loopsva 0:87a63595da37 19 * use of the software, conveys no license or title under any patent,
loopsva 0:87a63595da37 20 * copyright, or mask work right to the product. NXP Semiconductors
loopsva 0:87a63595da37 21 * reserves the right to make changes in the software without
loopsva 0:87a63595da37 22 * notification. NXP Semiconductors also make no representation or
loopsva 0:87a63595da37 23 * warranty that such application will be suitable for the specified
loopsva 0:87a63595da37 24 * use without further testing or modification.
loopsva 0:87a63595da37 25 **********************************************************************/
loopsva 0:87a63595da37 26
loopsva 0:87a63595da37 27 /* Peripheral group ----------------------------------------------------------- */
loopsva 0:87a63595da37 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
loopsva 0:87a63595da37 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
loopsva 0:87a63595da37 30 * @{
loopsva 0:87a63595da37 31 */
loopsva 0:87a63595da37 32
loopsva 0:87a63595da37 33 #ifndef LPC17XX_EMAC_H_
loopsva 0:87a63595da37 34 #define LPC17XX_EMAC_H_
loopsva 0:87a63595da37 35
loopsva 0:87a63595da37 36 /* Includes ------------------------------------------------------------------- */
loopsva 0:87a63595da37 37 #include "cmsis.h"
loopsva 0:87a63595da37 38
loopsva 0:87a63595da37 39 #ifdef __cplusplus
loopsva 0:87a63595da37 40 extern "C"
loopsva 0:87a63595da37 41 {
loopsva 0:87a63595da37 42 #endif
loopsva 0:87a63595da37 43
loopsva 0:87a63595da37 44 #define MCB_LPC_1768
loopsva 0:87a63595da37 45 //#define IAR_LPC_1768
loopsva 0:87a63595da37 46
loopsva 0:87a63595da37 47 /* Public Macros -------------------------------------------------------------- */
loopsva 0:87a63595da37 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
loopsva 0:87a63595da37 49 * @{
loopsva 0:87a63595da37 50 */
loopsva 0:87a63595da37 51
loopsva 0:87a63595da37 52
loopsva 0:87a63595da37 53 /* EMAC PHY status type definitions */
loopsva 0:87a63595da37 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
loopsva 0:87a63595da37 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
loopsva 0:87a63595da37 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
loopsva 0:87a63595da37 57
loopsva 0:87a63595da37 58 /* EMAC PHY device Speed definitions */
loopsva 0:87a63595da37 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
loopsva 0:87a63595da37 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
loopsva 0:87a63595da37 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
loopsva 0:87a63595da37 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
loopsva 0:87a63595da37 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
loopsva 0:87a63595da37 64
loopsva 0:87a63595da37 65 /**
loopsva 0:87a63595da37 66 * @}
loopsva 0:87a63595da37 67 */
loopsva 0:87a63595da37 68 /* Private Macros ------------------------------------------------------------- */
loopsva 0:87a63595da37 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
loopsva 0:87a63595da37 70 * @{
loopsva 0:87a63595da37 71 */
loopsva 0:87a63595da37 72
loopsva 0:87a63595da37 73
loopsva 0:87a63595da37 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
loopsva 0:87a63595da37 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
loopsva 0:87a63595da37 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
loopsva 0:87a63595da37 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
loopsva 0:87a63595da37 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
loopsva 0:87a63595da37 79
loopsva 0:87a63595da37 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
loopsva 0:87a63595da37 81 /*********************************************************************//**
loopsva 0:87a63595da37 82 * Macro defines for MAC Configuration Register 1
loopsva 0:87a63595da37 83 **********************************************************************/
loopsva 0:87a63595da37 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
loopsva 0:87a63595da37 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
loopsva 0:87a63595da37 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
loopsva 0:87a63595da37 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
loopsva 0:87a63595da37 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
loopsva 0:87a63595da37 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
loopsva 0:87a63595da37 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
loopsva 0:87a63595da37 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
loopsva 0:87a63595da37 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
loopsva 0:87a63595da37 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
loopsva 0:87a63595da37 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
loopsva 0:87a63595da37 95
loopsva 0:87a63595da37 96 /*********************************************************************//**
loopsva 0:87a63595da37 97 * Macro defines for MAC Configuration Register 2
loopsva 0:87a63595da37 98 **********************************************************************/
loopsva 0:87a63595da37 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
loopsva 0:87a63595da37 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
loopsva 0:87a63595da37 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
loopsva 0:87a63595da37 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
loopsva 0:87a63595da37 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
loopsva 0:87a63595da37 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
loopsva 0:87a63595da37 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
loopsva 0:87a63595da37 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
loopsva 0:87a63595da37 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
loopsva 0:87a63595da37 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
loopsva 0:87a63595da37 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
loopsva 0:87a63595da37 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
loopsva 0:87a63595da37 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
loopsva 0:87a63595da37 112
loopsva 0:87a63595da37 113 /*********************************************************************//**
loopsva 0:87a63595da37 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
loopsva 0:87a63595da37 115 **********************************************************************/
loopsva 0:87a63595da37 116 /** Programmable field representing the nibble time offset of the minimum possible period
loopsva 0:87a63595da37 117 * between the end of any transmitted packet to the beginning of the next */
loopsva 0:87a63595da37 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
loopsva 0:87a63595da37 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
loopsva 0:87a63595da37 120 * offset of the minimum possible period between the end of any transmitted packet to the
loopsva 0:87a63595da37 121 * beginning of the next */
loopsva 0:87a63595da37 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
loopsva 0:87a63595da37 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
loopsva 0:87a63595da37 124 * offset of the minimum possible period between the end of any transmitted packet to the
loopsva 0:87a63595da37 125 * beginning of the next */
loopsva 0:87a63595da37 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
loopsva 0:87a63595da37 127
loopsva 0:87a63595da37 128 /*********************************************************************//**
loopsva 0:87a63595da37 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
loopsva 0:87a63595da37 130 **********************************************************************/
loopsva 0:87a63595da37 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
loopsva 0:87a63595da37 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
loopsva 0:87a63595da37 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
loopsva 0:87a63595da37 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
loopsva 0:87a63595da37 135 /** Programmable field representing the optional carrierSense window referenced in
loopsva 0:87a63595da37 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
loopsva 0:87a63595da37 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
loopsva 0:87a63595da37 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
loopsva 0:87a63595da37 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
loopsva 0:87a63595da37 140
loopsva 0:87a63595da37 141 /*********************************************************************//**
loopsva 0:87a63595da37 142 * Macro defines for Collision Window/Retry Register
loopsva 0:87a63595da37 143 **********************************************************************/
loopsva 0:87a63595da37 144 /** Programmable field specifying the number of retransmission attempts following a collision before
loopsva 0:87a63595da37 145 * aborting the packet due to excessive collisions */
loopsva 0:87a63595da37 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
loopsva 0:87a63595da37 147 /** Programmable field representing the slot time or collision window during which collisions occur
loopsva 0:87a63595da37 148 * in properly configured networks */
loopsva 0:87a63595da37 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
loopsva 0:87a63595da37 150 /** Default value for Collision Window / Retry register */
loopsva 0:87a63595da37 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
loopsva 0:87a63595da37 152
loopsva 0:87a63595da37 153 /*********************************************************************//**
loopsva 0:87a63595da37 154 * Macro defines for Maximum Frame Register
loopsva 0:87a63595da37 155 **********************************************************************/
loopsva 0:87a63595da37 156 /** Represents a maximum receive frame of 1536 octets */
loopsva 0:87a63595da37 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
loopsva 0:87a63595da37 158
loopsva 0:87a63595da37 159 /*********************************************************************//**
loopsva 0:87a63595da37 160 * Macro defines for PHY Support Register
loopsva 0:87a63595da37 161 **********************************************************************/
loopsva 0:87a63595da37 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
loopsva 0:87a63595da37 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
loopsva 0:87a63595da37 164
loopsva 0:87a63595da37 165 /*********************************************************************//**
loopsva 0:87a63595da37 166 * Macro defines for Test Register
loopsva 0:87a63595da37 167 **********************************************************************/
loopsva 0:87a63595da37 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
loopsva 0:87a63595da37 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
loopsva 0:87a63595da37 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
loopsva 0:87a63595da37 171
loopsva 0:87a63595da37 172 /*********************************************************************//**
loopsva 0:87a63595da37 173 * Macro defines for MII Management Configuration Register
loopsva 0:87a63595da37 174 **********************************************************************/
loopsva 0:87a63595da37 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
loopsva 0:87a63595da37 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
loopsva 0:87a63595da37 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
loopsva 0:87a63595da37 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
loopsva 0:87a63595da37 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
loopsva 0:87a63595da37 180
loopsva 0:87a63595da37 181 /*********************************************************************//**
loopsva 0:87a63595da37 182 * Macro defines for MII Management Command Register
loopsva 0:87a63595da37 183 **********************************************************************/
loopsva 0:87a63595da37 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
loopsva 0:87a63595da37 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
loopsva 0:87a63595da37 186
loopsva 0:87a63595da37 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
loopsva 0:87a63595da37 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
loopsva 0:87a63595da37 189
loopsva 0:87a63595da37 190 /*********************************************************************//**
loopsva 0:87a63595da37 191 * Macro defines for MII Management Address Register
loopsva 0:87a63595da37 192 **********************************************************************/
loopsva 0:87a63595da37 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
loopsva 0:87a63595da37 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
loopsva 0:87a63595da37 195
loopsva 0:87a63595da37 196 /*********************************************************************//**
loopsva 0:87a63595da37 197 * Macro defines for MII Management Write Data Register
loopsva 0:87a63595da37 198 **********************************************************************/
loopsva 0:87a63595da37 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
loopsva 0:87a63595da37 200
loopsva 0:87a63595da37 201 /*********************************************************************//**
loopsva 0:87a63595da37 202 * Macro defines for MII Management Read Data Register
loopsva 0:87a63595da37 203 **********************************************************************/
loopsva 0:87a63595da37 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
loopsva 0:87a63595da37 205
loopsva 0:87a63595da37 206 /*********************************************************************//**
loopsva 0:87a63595da37 207 * Macro defines for MII Management Indicators Register
loopsva 0:87a63595da37 208 **********************************************************************/
loopsva 0:87a63595da37 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
loopsva 0:87a63595da37 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
loopsva 0:87a63595da37 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
loopsva 0:87a63595da37 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
loopsva 0:87a63595da37 213
loopsva 0:87a63595da37 214 /* Station Address 0 Register */
loopsva 0:87a63595da37 215 /* Station Address 1 Register */
loopsva 0:87a63595da37 216 /* Station Address 2 Register */
loopsva 0:87a63595da37 217
loopsva 0:87a63595da37 218
loopsva 0:87a63595da37 219 /* Control register definitions --------------------------------------------------------------------------- */
loopsva 0:87a63595da37 220 /*********************************************************************//**
loopsva 0:87a63595da37 221 * Macro defines for Command Register
loopsva 0:87a63595da37 222 **********************************************************************/
loopsva 0:87a63595da37 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
loopsva 0:87a63595da37 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
loopsva 0:87a63595da37 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
loopsva 0:87a63595da37 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
loopsva 0:87a63595da37 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
loopsva 0:87a63595da37 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
loopsva 0:87a63595da37 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
loopsva 0:87a63595da37 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
loopsva 0:87a63595da37 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
loopsva 0:87a63595da37 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
loopsva 0:87a63595da37 233
loopsva 0:87a63595da37 234 /*********************************************************************//**
loopsva 0:87a63595da37 235 * Macro defines for Status Register
loopsva 0:87a63595da37 236 **********************************************************************/
loopsva 0:87a63595da37 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
loopsva 0:87a63595da37 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
loopsva 0:87a63595da37 239
loopsva 0:87a63595da37 240 /*********************************************************************//**
loopsva 0:87a63595da37 241 * Macro defines for Transmit Status Vector 0 Register
loopsva 0:87a63595da37 242 **********************************************************************/
loopsva 0:87a63595da37 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
loopsva 0:87a63595da37 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
loopsva 0:87a63595da37 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
loopsva 0:87a63595da37 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
loopsva 0:87a63595da37 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
loopsva 0:87a63595da37 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
loopsva 0:87a63595da37 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
loopsva 0:87a63595da37 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
loopsva 0:87a63595da37 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
loopsva 0:87a63595da37 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
loopsva 0:87a63595da37 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
loopsva 0:87a63595da37 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
loopsva 0:87a63595da37 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
loopsva 0:87a63595da37 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
loopsva 0:87a63595da37 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
loopsva 0:87a63595da37 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
loopsva 0:87a63595da37 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
loopsva 0:87a63595da37 260
loopsva 0:87a63595da37 261 /*********************************************************************//**
loopsva 0:87a63595da37 262 * Macro defines for Transmit Status Vector 1 Register
loopsva 0:87a63595da37 263 **********************************************************************/
loopsva 0:87a63595da37 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
loopsva 0:87a63595da37 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
loopsva 0:87a63595da37 266
loopsva 0:87a63595da37 267 /*********************************************************************//**
loopsva 0:87a63595da37 268 * Macro defines for Receive Status Vector Register
loopsva 0:87a63595da37 269 **********************************************************************/
loopsva 0:87a63595da37 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
loopsva 0:87a63595da37 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
loopsva 0:87a63595da37 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
loopsva 0:87a63595da37 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
loopsva 0:87a63595da37 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
loopsva 0:87a63595da37 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
loopsva 0:87a63595da37 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
loopsva 0:87a63595da37 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
loopsva 0:87a63595da37 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
loopsva 0:87a63595da37 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
loopsva 0:87a63595da37 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
loopsva 0:87a63595da37 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
loopsva 0:87a63595da37 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
loopsva 0:87a63595da37 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
loopsva 0:87a63595da37 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
loopsva 0:87a63595da37 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
loopsva 0:87a63595da37 286
loopsva 0:87a63595da37 287 /*********************************************************************//**
loopsva 0:87a63595da37 288 * Macro defines for Flow Control Counter Register
loopsva 0:87a63595da37 289 **********************************************************************/
loopsva 0:87a63595da37 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
loopsva 0:87a63595da37 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
loopsva 0:87a63595da37 292
loopsva 0:87a63595da37 293 /*********************************************************************//**
loopsva 0:87a63595da37 294 * Macro defines for Flow Control Status Register
loopsva 0:87a63595da37 295 **********************************************************************/
loopsva 0:87a63595da37 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
loopsva 0:87a63595da37 297
loopsva 0:87a63595da37 298
loopsva 0:87a63595da37 299 /* Receive filter register definitions -------------------------------------------------------- */
loopsva 0:87a63595da37 300 /*********************************************************************//**
loopsva 0:87a63595da37 301 * Macro defines for Receive Filter Control Register
loopsva 0:87a63595da37 302 **********************************************************************/
loopsva 0:87a63595da37 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
loopsva 0:87a63595da37 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
loopsva 0:87a63595da37 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
loopsva 0:87a63595da37 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
loopsva 0:87a63595da37 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
loopsva 0:87a63595da37 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
loopsva 0:87a63595da37 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
loopsva 0:87a63595da37 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
loopsva 0:87a63595da37 311
loopsva 0:87a63595da37 312 /*********************************************************************//**
loopsva 0:87a63595da37 313 * Macro defines for Receive Filter WoL Status/Clear Registers
loopsva 0:87a63595da37 314 **********************************************************************/
loopsva 0:87a63595da37 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
loopsva 0:87a63595da37 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
loopsva 0:87a63595da37 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
loopsva 0:87a63595da37 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
loopsva 0:87a63595da37 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
loopsva 0:87a63595da37 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
loopsva 0:87a63595da37 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
loopsva 0:87a63595da37 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
loopsva 0:87a63595da37 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
loopsva 0:87a63595da37 324
loopsva 0:87a63595da37 325
loopsva 0:87a63595da37 326 /* Module control register definitions ---------------------------------------------------- */
loopsva 0:87a63595da37 327 /*********************************************************************//**
loopsva 0:87a63595da37 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
loopsva 0:87a63595da37 329 **********************************************************************/
loopsva 0:87a63595da37 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
loopsva 0:87a63595da37 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
loopsva 0:87a63595da37 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
loopsva 0:87a63595da37 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
loopsva 0:87a63595da37 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
loopsva 0:87a63595da37 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
loopsva 0:87a63595da37 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
loopsva 0:87a63595da37 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
loopsva 0:87a63595da37 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
loopsva 0:87a63595da37 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
loopsva 0:87a63595da37 340
loopsva 0:87a63595da37 341 /*********************************************************************//**
loopsva 0:87a63595da37 342 * Macro defines for Power Down Register
loopsva 0:87a63595da37 343 **********************************************************************/
loopsva 0:87a63595da37 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
loopsva 0:87a63595da37 345
loopsva 0:87a63595da37 346 /* Descriptor and status formats ---------------------------------------------------- */
loopsva 0:87a63595da37 347 /*********************************************************************//**
loopsva 0:87a63595da37 348 * Macro defines for RX Descriptor Control Word
loopsva 0:87a63595da37 349 **********************************************************************/
loopsva 0:87a63595da37 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
loopsva 0:87a63595da37 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
loopsva 0:87a63595da37 352
loopsva 0:87a63595da37 353 /*********************************************************************//**
loopsva 0:87a63595da37 354 * Macro defines for RX Status Hash CRC Word
loopsva 0:87a63595da37 355 **********************************************************************/
loopsva 0:87a63595da37 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
loopsva 0:87a63595da37 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
loopsva 0:87a63595da37 358
loopsva 0:87a63595da37 359 /*********************************************************************//**
loopsva 0:87a63595da37 360 * Macro defines for RX Status Information Word
loopsva 0:87a63595da37 361 **********************************************************************/
loopsva 0:87a63595da37 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
loopsva 0:87a63595da37 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
loopsva 0:87a63595da37 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
loopsva 0:87a63595da37 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
loopsva 0:87a63595da37 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
loopsva 0:87a63595da37 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
loopsva 0:87a63595da37 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
loopsva 0:87a63595da37 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
loopsva 0:87a63595da37 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
loopsva 0:87a63595da37 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
loopsva 0:87a63595da37 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
loopsva 0:87a63595da37 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
loopsva 0:87a63595da37 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
loopsva 0:87a63595da37 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
loopsva 0:87a63595da37 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
loopsva 0:87a63595da37 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
loopsva 0:87a63595da37 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
loopsva 0:87a63595da37 379
loopsva 0:87a63595da37 380 /*********************************************************************//**
loopsva 0:87a63595da37 381 * Macro defines for TX Descriptor Control Word
loopsva 0:87a63595da37 382 **********************************************************************/
loopsva 0:87a63595da37 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
loopsva 0:87a63595da37 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
loopsva 0:87a63595da37 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
loopsva 0:87a63595da37 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
loopsva 0:87a63595da37 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
loopsva 0:87a63595da37 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
loopsva 0:87a63595da37 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
loopsva 0:87a63595da37 390
loopsva 0:87a63595da37 391 /*********************************************************************//**
loopsva 0:87a63595da37 392 * Macro defines for TX Status Information Word
loopsva 0:87a63595da37 393 **********************************************************************/
loopsva 0:87a63595da37 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
loopsva 0:87a63595da37 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
loopsva 0:87a63595da37 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
loopsva 0:87a63595da37 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
loopsva 0:87a63595da37 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
loopsva 0:87a63595da37 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
loopsva 0:87a63595da37 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
loopsva 0:87a63595da37 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
loopsva 0:87a63595da37 402
loopsva 0:87a63595da37 403 #ifdef MCB_LPC_1768
loopsva 0:87a63595da37 404 /* DP83848C PHY definition ------------------------------------------------------------ */
loopsva 0:87a63595da37 405
loopsva 0:87a63595da37 406 /** PHY device reset time out definition */
loopsva 0:87a63595da37 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
loopsva 0:87a63595da37 408
loopsva 0:87a63595da37 409 /* ENET Device Revision ID */
loopsva 0:87a63595da37 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
loopsva 0:87a63595da37 411
loopsva 0:87a63595da37 412 /*********************************************************************//**
loopsva 0:87a63595da37 413 * Macro defines for DP83848C PHY Registers
loopsva 0:87a63595da37 414 **********************************************************************/
loopsva 0:87a63595da37 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
loopsva 0:87a63595da37 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
loopsva 0:87a63595da37 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
loopsva 0:87a63595da37 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
loopsva 0:87a63595da37 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
loopsva 0:87a63595da37 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
loopsva 0:87a63595da37 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
loopsva 0:87a63595da37 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
loopsva 0:87a63595da37 423 #define EMAC_PHY_REG_LPNPA 0x08
loopsva 0:87a63595da37 424
loopsva 0:87a63595da37 425 /*********************************************************************//**
loopsva 0:87a63595da37 426 * Macro defines for PHY Extended Registers
loopsva 0:87a63595da37 427 **********************************************************************/
loopsva 0:87a63595da37 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
loopsva 0:87a63595da37 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
loopsva 0:87a63595da37 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
loopsva 0:87a63595da37 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
loopsva 0:87a63595da37 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
loopsva 0:87a63595da37 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
loopsva 0:87a63595da37 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
loopsva 0:87a63595da37 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
loopsva 0:87a63595da37 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
loopsva 0:87a63595da37 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
loopsva 0:87a63595da37 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
loopsva 0:87a63595da37 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
loopsva 0:87a63595da37 440
loopsva 0:87a63595da37 441 /*********************************************************************//**
loopsva 0:87a63595da37 442 * Macro defines for PHY Basic Mode Control Register
loopsva 0:87a63595da37 443 **********************************************************************/
loopsva 0:87a63595da37 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
loopsva 0:87a63595da37 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
loopsva 0:87a63595da37 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
loopsva 0:87a63595da37 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
loopsva 0:87a63595da37 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
loopsva 0:87a63595da37 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
loopsva 0:87a63595da37 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
loopsva 0:87a63595da37 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
loopsva 0:87a63595da37 452
loopsva 0:87a63595da37 453 /*********************************************************************//**
loopsva 0:87a63595da37 454 * Macro defines for PHY Basic Mode Status Status Register
loopsva 0:87a63595da37 455 **********************************************************************/
loopsva 0:87a63595da37 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
loopsva 0:87a63595da37 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
loopsva 0:87a63595da37 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
loopsva 0:87a63595da37 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
loopsva 0:87a63595da37 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
loopsva 0:87a63595da37 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
loopsva 0:87a63595da37 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
loopsva 0:87a63595da37 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
loopsva 0:87a63595da37 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
loopsva 0:87a63595da37 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
loopsva 0:87a63595da37 466
loopsva 0:87a63595da37 467 /*********************************************************************//**
loopsva 0:87a63595da37 468 * Macro defines for PHY Status Register
loopsva 0:87a63595da37 469 **********************************************************************/
loopsva 0:87a63595da37 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
loopsva 0:87a63595da37 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
loopsva 0:87a63595da37 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
loopsva 0:87a63595da37 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
loopsva 0:87a63595da37 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
loopsva 0:87a63595da37 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
loopsva 0:87a63595da37 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
loopsva 0:87a63595da37 477
loopsva 0:87a63595da37 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
loopsva 0:87a63595da37 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
loopsva 0:87a63595da37 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
loopsva 0:87a63595da37 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
loopsva 0:87a63595da37 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
loopsva 0:87a63595da37 483
loopsva 0:87a63595da37 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
loopsva 0:87a63595da37 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
loopsva 0:87a63595da37 486
loopsva 0:87a63595da37 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
loopsva 0:87a63595da37 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
loopsva 0:87a63595da37 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
loopsva 0:87a63595da37 490
loopsva 0:87a63595da37 491 #elif defined(IAR_LPC_1768)
loopsva 0:87a63595da37 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
loopsva 0:87a63595da37 493 /** PHY device reset time out definition */
loopsva 0:87a63595da37 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
loopsva 0:87a63595da37 495
loopsva 0:87a63595da37 496 /* ENET Device Revision ID */
loopsva 0:87a63595da37 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
loopsva 0:87a63595da37 498
loopsva 0:87a63595da37 499 /*********************************************************************//**
loopsva 0:87a63595da37 500 * Macro defines for KSZ8721BL PHY Registers
loopsva 0:87a63595da37 501 **********************************************************************/
loopsva 0:87a63595da37 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
loopsva 0:87a63595da37 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
loopsva 0:87a63595da37 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
loopsva 0:87a63595da37 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
loopsva 0:87a63595da37 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
loopsva 0:87a63595da37 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
loopsva 0:87a63595da37 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
loopsva 0:87a63595da37 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
loopsva 0:87a63595da37 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
loopsva 0:87a63595da37 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
loopsva 0:87a63595da37 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
loopsva 0:87a63595da37 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
loopsva 0:87a63595da37 514
loopsva 0:87a63595da37 515 /*********************************************************************//**
loopsva 0:87a63595da37 516 * Macro defines for PHY Basic Mode Control Register
loopsva 0:87a63595da37 517 **********************************************************************/
loopsva 0:87a63595da37 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
loopsva 0:87a63595da37 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
loopsva 0:87a63595da37 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
loopsva 0:87a63595da37 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
loopsva 0:87a63595da37 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
loopsva 0:87a63595da37 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
loopsva 0:87a63595da37 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
loopsva 0:87a63595da37 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
loopsva 0:87a63595da37 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
loopsva 0:87a63595da37 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
loopsva 0:87a63595da37 528
loopsva 0:87a63595da37 529 /*********************************************************************//**
loopsva 0:87a63595da37 530 * Macro defines for PHY Basic Mode Status Register
loopsva 0:87a63595da37 531 **********************************************************************/
loopsva 0:87a63595da37 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
loopsva 0:87a63595da37 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
loopsva 0:87a63595da37 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
loopsva 0:87a63595da37 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
loopsva 0:87a63595da37 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
loopsva 0:87a63595da37 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
loopsva 0:87a63595da37 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
loopsva 0:87a63595da37 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
loopsva 0:87a63595da37 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
loopsva 0:87a63595da37 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
loopsva 0:87a63595da37 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
loopsva 0:87a63595da37 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
loopsva 0:87a63595da37 544
loopsva 0:87a63595da37 545 /*********************************************************************//**
loopsva 0:87a63595da37 546 * Macro defines for PHY Identifier
loopsva 0:87a63595da37 547 **********************************************************************/
loopsva 0:87a63595da37 548 /* PHY Identifier 1 bitmap definitions */
loopsva 0:87a63595da37 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
loopsva 0:87a63595da37 550
loopsva 0:87a63595da37 551 /* PHY Identifier 2 bitmap definitions */
loopsva 0:87a63595da37 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
loopsva 0:87a63595da37 553
loopsva 0:87a63595da37 554 /*********************************************************************//**
loopsva 0:87a63595da37 555 * Macro defines for Auto-Negotiation Advertisement
loopsva 0:87a63595da37 556 **********************************************************************/
loopsva 0:87a63595da37 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
loopsva 0:87a63595da37 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
loopsva 0:87a63595da37 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
loopsva 0:87a63595da37 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
loopsva 0:87a63595da37 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
loopsva 0:87a63595da37 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
loopsva 0:87a63595da37 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
loopsva 0:87a63595da37 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
loopsva 0:87a63595da37 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
loopsva 0:87a63595da37 566
loopsva 0:87a63595da37 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
loopsva 0:87a63595da37 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
loopsva 0:87a63595da37 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
loopsva 0:87a63595da37 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
loopsva 0:87a63595da37 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
loopsva 0:87a63595da37 572
loopsva 0:87a63595da37 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
loopsva 0:87a63595da37 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
loopsva 0:87a63595da37 575
loopsva 0:87a63595da37 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
loopsva 0:87a63595da37 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
loopsva 0:87a63595da37 578 #endif
loopsva 0:87a63595da37 579
loopsva 0:87a63595da37 580 /**
loopsva 0:87a63595da37 581 * @}
loopsva 0:87a63595da37 582 */
loopsva 0:87a63595da37 583
loopsva 0:87a63595da37 584
loopsva 0:87a63595da37 585 /* Public Types --------------------------------------------------------------- */
loopsva 0:87a63595da37 586 /** @defgroup EMAC_Public_Types EMAC Public Types
loopsva 0:87a63595da37 587 * @{
loopsva 0:87a63595da37 588 */
loopsva 0:87a63595da37 589
loopsva 0:87a63595da37 590 /* Descriptor and status formats ---------------------------------------------- */
loopsva 0:87a63595da37 591
loopsva 0:87a63595da37 592 /**
loopsva 0:87a63595da37 593 * @brief RX Descriptor structure type definition
loopsva 0:87a63595da37 594 */
loopsva 0:87a63595da37 595 typedef struct {
loopsva 0:87a63595da37 596 uint32_t Packet; /**< Receive Packet Descriptor */
loopsva 0:87a63595da37 597 uint32_t Ctrl; /**< Receive Control Descriptor */
loopsva 0:87a63595da37 598 } RX_Desc;
loopsva 0:87a63595da37 599
loopsva 0:87a63595da37 600 /**
loopsva 0:87a63595da37 601 * @brief RX Status structure type definition
loopsva 0:87a63595da37 602 */
loopsva 0:87a63595da37 603 typedef struct {
loopsva 0:87a63595da37 604 uint32_t Info; /**< Receive Information Status */
loopsva 0:87a63595da37 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
loopsva 0:87a63595da37 606 } RX_Stat;
loopsva 0:87a63595da37 607
loopsva 0:87a63595da37 608 /**
loopsva 0:87a63595da37 609 * @brief TX Descriptor structure type definition
loopsva 0:87a63595da37 610 */
loopsva 0:87a63595da37 611 typedef struct {
loopsva 0:87a63595da37 612 uint32_t Packet; /**< Transmit Packet Descriptor */
loopsva 0:87a63595da37 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
loopsva 0:87a63595da37 614 } TX_Desc;
loopsva 0:87a63595da37 615
loopsva 0:87a63595da37 616 /**
loopsva 0:87a63595da37 617 * @brief TX Status structure type definition
loopsva 0:87a63595da37 618 */
loopsva 0:87a63595da37 619 typedef struct {
loopsva 0:87a63595da37 620 uint32_t Info; /**< Transmit Information Status */
loopsva 0:87a63595da37 621 } TX_Stat;
loopsva 0:87a63595da37 622
loopsva 0:87a63595da37 623
loopsva 0:87a63595da37 624 /**
loopsva 0:87a63595da37 625 * @brief TX Data Buffer structure definition
loopsva 0:87a63595da37 626 */
loopsva 0:87a63595da37 627 typedef struct {
loopsva 0:87a63595da37 628 uint32_t ulDataLen; /**< Data length */
loopsva 0:87a63595da37 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
loopsva 0:87a63595da37 630 } EMAC_PACKETBUF_Type;
loopsva 0:87a63595da37 631
loopsva 0:87a63595da37 632 /**
loopsva 0:87a63595da37 633 * @brief EMAC configuration structure definition
loopsva 0:87a63595da37 634 */
loopsva 0:87a63595da37 635 typedef struct {
loopsva 0:87a63595da37 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
loopsva 0:87a63595da37 637 - EMAC_MODE_AUTO
loopsva 0:87a63595da37 638 - EMAC_MODE_10M_FULL
loopsva 0:87a63595da37 639 - EMAC_MODE_10M_HALF
loopsva 0:87a63595da37 640 - EMAC_MODE_100M_FULL
loopsva 0:87a63595da37 641 - EMAC_MODE_100M_HALF
loopsva 0:87a63595da37 642 */
loopsva 0:87a63595da37 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
loopsva 0:87a63595da37 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
loopsva 0:87a63595da37 645 */
loopsva 0:87a63595da37 646 } EMAC_CFG_Type;
loopsva 0:87a63595da37 647
loopsva 0:87a63595da37 648 /** Ethernet block power/clock control bit*/
loopsva 0:87a63595da37 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
loopsva 0:87a63595da37 650
loopsva 0:87a63595da37 651 #ifdef __cplusplus
loopsva 0:87a63595da37 652 }
loopsva 0:87a63595da37 653 #endif
loopsva 0:87a63595da37 654
loopsva 0:87a63595da37 655 #endif /* LPC17XX_EMAC_H_ */
loopsva 0:87a63595da37 656
loopsva 0:87a63595da37 657 /**
loopsva 0:87a63595da37 658 * @}
loopsva 0:87a63595da37 659 */
loopsva 0:87a63595da37 660
loopsva 0:87a63595da37 661 /* --------------------------------- End Of File ------------------------------ */