Kenji Arai / Frq_cuntr_full

Frequency counter library only for NucleoF411RE

Dependents:   Frequency_Counter_w_GPS_1PPS

frq_cuntr_full.cpp@4:9d3b3f0a3882, 2015-01-01 (annotated)

Committer:
kenjiArai
Date:
Thu Jan 01 05:04:20 2015 +0000
Revision:
4:9d3b3f0a3882
Parent:
3:339307e1dc0d 
Modified comments

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 0:bfdc6ed58a06 1 /*
kenjiArai 1:102230f2879d 2 * mbed Library / Frequency Counter with GPS 1PPS Compensation
kenjiArai 0:bfdc6ed58a06 3 * Frequency Counter Hardware relataed program
kenjiArai 1:102230f2879d 4 * Only for ST Nucleo F411RE
kenjiArai 0:bfdc6ed58a06 5 *
kenjiArai 0:bfdc6ed58a06 6 * Copyright (c) 2014 Kenji Arai / JH1PJL
kenjiArai 0:bfdc6ed58a06 7 * http://www.page.sannet.ne.jp/kenjia/index.html
kenjiArai 0:bfdc6ed58a06 8 * http://mbed.org/users/kenjiArai/
kenjiArai 0:bfdc6ed58a06 9 * Additional functions and modification
kenjiArai 0:bfdc6ed58a06 10 * started: October 18th, 2014
kenjiArai 4:9d3b3f0a3882 11 * Revised: January 1st, 2015
kenjiArai 0:bfdc6ed58a06 12 *
kenjiArai 0:bfdc6ed58a06 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
kenjiArai 0:bfdc6ed58a06 14 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
kenjiArai 0:bfdc6ed58a06 15 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
kenjiArai 0:bfdc6ed58a06 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
kenjiArai 0:bfdc6ed58a06 17 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
kenjiArai 0:bfdc6ed58a06 18 */
kenjiArai 0:bfdc6ed58a06 19
kenjiArai 4:9d3b3f0a3882 20 #if defined(TARGET_NUCLEO_F411RE)
kenjiArai 4:9d3b3f0a3882 21
kenjiArai 0:bfdc6ed58a06 22 #include "frq_cuntr_full.h"
kenjiArai 0:bfdc6ed58a06 23
kenjiArai 0:bfdc6ed58a06 24 #ifdef DEBUG
kenjiArai 0:bfdc6ed58a06 25 Serial pcm(USBTX, USBRX);
kenjiArai 0:bfdc6ed58a06 26 DigitalOut debug_led(LED1);
kenjiArai 0:bfdc6ed58a06 27 #endif
kenjiArai 0:bfdc6ed58a06 28
kenjiArai 0:bfdc6ed58a06 29 #ifdef DEBUG
kenjiArai 0:bfdc6ed58a06 30 #define BAUD(x) pcm.baud(x)
kenjiArai 0:bfdc6ed58a06 31 #define PRINTF(...) pcm.printf(__VA_ARGS__)
kenjiArai 0:bfdc6ed58a06 32 #else
kenjiArai 0:bfdc6ed58a06 33 #define BAUD(x) {;}
kenjiArai 0:bfdc6ed58a06 34 #define PRINTF(...) {;}
kenjiArai 0:bfdc6ed58a06 35 #endif
kenjiArai 0:bfdc6ed58a06 36
kenjiArai 0:bfdc6ed58a06 37 namespace Frequency_counter
kenjiArai 0:bfdc6ed58a06 38 {
kenjiArai 1:102230f2879d 39 // TIM2 OC
kenjiArai 2:194f82ad3041 40 static uint32_t oc_set_time0;
kenjiArai 2:194f82ad3041 41 static uint32_t oc_set_time1;
kenjiArai 2:194f82ad3041 42 static uint8_t new_gt_value;
kenjiArai 2:194f82ad3041 43 static uint32_t oc_hi_time;
kenjiArai 2:194f82ad3041 44 static uint32_t oc_lo_time;
kenjiArai 1:102230f2879d 45 // TIM2 IC
kenjiArai 1:102230f2879d 46 static uint8_t tim2_ready_flg;
kenjiArai 1:102230f2879d 47 static uint32_t tim2_cnt_data;
kenjiArai 1:102230f2879d 48 static uint32_t tim2_old_cnt_data;
kenjiArai 1:102230f2879d 49 // TIM3+4 IC
kenjiArai 1:102230f2879d 50 static uint8_t tim3p4_ready_flg;
kenjiArai 1:102230f2879d 51 static uint32_t tim3p4_cnt_data;
kenjiArai 1:102230f2879d 52
kenjiArai 1:102230f2879d 53 //-------------------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 54 // Interrupt Handlers
kenjiArai 1:102230f2879d 55 //-------------------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 56 // TIM2 IC2 Interrupt control
kenjiArai 1:102230f2879d 57 void irq_ic2_TIM2(void)
kenjiArai 1:102230f2879d 58 {
kenjiArai 1:102230f2879d 59 uint16_t reg;
kenjiArai 1:102230f2879d 60 reg = TIM2->SR;
kenjiArai 1:102230f2879d 61 if (reg & TIM_SR_CC2IF) {
kenjiArai 1:102230f2879d 62 TIM2->SR &= ~TIM_SR_CC2IF; // clear IC flag
kenjiArai 1:102230f2879d 63 tim2_old_cnt_data = tim2_cnt_data;
kenjiArai 1:102230f2879d 64 tim2_cnt_data = TIM2->CCR2;
kenjiArai 1:102230f2879d 65 tim2_ready_flg = 1;
kenjiArai 2:194f82ad3041 66 #if defined(DEBUG)
kenjiArai 2:194f82ad3041 67 debug_led = !debug_led;
kenjiArai 4:9d3b3f0a3882 68 #endif // defined(DEBUG)
kenjiArai 2:194f82ad3041 69 } else if (reg & TIM_SR_CC3IF) { // Output Compare
kenjiArai 1:102230f2879d 70 TIM2->SR &= ~TIM_SR_CC3IF; // clear IC flag
kenjiArai 2:194f82ad3041 71 if (GPIOB->IDR & 0x0400) { // Check PB10 status
kenjiArai 1:102230f2879d 72 TIM2->CCR3 = TIM2->CCR3 + oc_hi_time;
kenjiArai 1:102230f2879d 73 } else {
kenjiArai 1:102230f2879d 74 TIM2->CCR3 = TIM2->CCR3 + oc_lo_time;
kenjiArai 1:102230f2879d 75 if (new_gt_value) {
kenjiArai 1:102230f2879d 76 new_gt_value = 0;
kenjiArai 1:102230f2879d 77 oc_hi_time = oc_set_time0;
kenjiArai 1:102230f2879d 78 oc_lo_time = oc_set_time1;
kenjiArai 1:102230f2879d 79 }
kenjiArai 0:bfdc6ed58a06 80 }
kenjiArai 0:bfdc6ed58a06 81 #if defined(DEBUG)
kenjiArai 3:339307e1dc0d 82 debug_led = !debug_led;
kenjiArai 4:9d3b3f0a3882 83 #endif // defined(DEBUG)
kenjiArai 0:bfdc6ed58a06 84 }
kenjiArai 1:102230f2879d 85 }
kenjiArai 1:102230f2879d 86
kenjiArai 1:102230f2879d 87 // TIM3 IC2 Interrupt control (same signal connected to TIM4 IC1)
kenjiArai 1:102230f2879d 88 void irq_ic2_TIM3P4(void)
kenjiArai 1:102230f2879d 89 {
kenjiArai 1:102230f2879d 90 TIM3->SR &= ~TIM_SR_CC2IF; // clear IC flag
kenjiArai 1:102230f2879d 91 TIM4->SR &= ~TIM_SR_CC1IF;
kenjiArai 1:102230f2879d 92 tim3p4_cnt_data = (TIM4->CCR1 << 16) + TIM3->CCR2;
kenjiArai 1:102230f2879d 93 tim3p4_ready_flg = 1;
kenjiArai 0:bfdc6ed58a06 94 #if defined(DEBUG)
kenjiArai 3:339307e1dc0d 95 debug_led = !debug_led;
kenjiArai 4:9d3b3f0a3882 96 #endif // defined(DEBUG)
kenjiArai 1:102230f2879d 97 }
kenjiArai 1:102230f2879d 98
kenjiArai 1:102230f2879d 99 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 100 // Frequency Counter
kenjiArai 1:102230f2879d 101 //---------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 102 FRQ_CUNTR::FRQ_CUNTR(PinName f_in, double gt, double ex_clock): _pin(f_in)
kenjiArai 1:102230f2879d 103 {
kenjiArai 2:194f82ad3041 104 // Don't change calling sequence!!
kenjiArai 2:194f82ad3041 105 set_external_clock(ex_clock); // 1st
kenjiArai 2:194f82ad3041 106 set_gate_time(gt); // 2nd
kenjiArai 2:194f82ad3041 107 initialize_Freq_counter(); // 3rd
kenjiArai 1:102230f2879d 108 }
kenjiArai 1:102230f2879d 109
kenjiArai 1:102230f2879d 110 // Set gate time
kenjiArai 1:102230f2879d 111 double FRQ_CUNTR::set_gate_time(double gt)
kenjiArai 1:102230f2879d 112 {
kenjiArai 1:102230f2879d 113 if (gt < 0.05) {
kenjiArai 1:102230f2879d 114 gate_time = 0.05;
kenjiArai 1:102230f2879d 115 } else if (gt > 60.0) {
kenjiArai 1:102230f2879d 116 gate_time = 60.0;
kenjiArai 1:102230f2879d 117 } else {
kenjiArai 1:102230f2879d 118 gate_time = gt;
kenjiArai 0:bfdc6ed58a06 119 }
kenjiArai 2:194f82ad3041 120 oc_set_time0 = clk_hi_const;
kenjiArai 2:194f82ad3041 121 double gt_tmp0 = ex_clk_base * gate_time;
kenjiArai 1:102230f2879d 122 uint32_t gt_tmp1 = (uint32_t)gt_tmp0;
kenjiArai 1:102230f2879d 123 if ((gt_tmp0 - (double)gt_tmp1) >= 0.5) {
kenjiArai 1:102230f2879d 124 ++gt_tmp1;
kenjiArai 0:bfdc6ed58a06 125 }
kenjiArai 2:194f82ad3041 126 oc_set_time1 = gt_tmp1 - clk_hi_const;
kenjiArai 1:102230f2879d 127 new_gt_value = 1;
kenjiArai 1:102230f2879d 128 return gate_time;
kenjiArai 1:102230f2879d 129 }
kenjiArai 1:102230f2879d 130
kenjiArai 2:194f82ad3041 131 // Read gate time
kenjiArai 2:194f82ad3041 132 double FRQ_CUNTR::read_gate_time(void)
kenjiArai 2:194f82ad3041 133 {
kenjiArai 2:194f82ad3041 134 return gate_time;
kenjiArai 2:194f82ad3041 135 }
kenjiArai 2:194f82ad3041 136
kenjiArai 2:194f82ad3041 137 // Set External Clock Frequency
kenjiArai 2:194f82ad3041 138 void FRQ_CUNTR::set_external_clock(double ex_clock)
kenjiArai 2:194f82ad3041 139 {
kenjiArai 2:194f82ad3041 140 #if defined(BASE_EXTERNAL_CLOCK)
kenjiArai 2:194f82ad3041 141 ex_clock_freq = ex_clock;
kenjiArai 2:194f82ad3041 142 ex_clk_base = (uint32_t)(ex_clock_freq * 1000000); // MHz->Hz
kenjiArai 2:194f82ad3041 143 clk_hi_const = (uint32_t)(ex_clock_freq * 1000000 * 0.04); // 40mS
kenjiArai 3:339307e1dc0d 144 uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.00001); // 10ppm error range
kenjiArai 2:194f82ad3041 145 clk_upper_limit = ex_clk_base + err;
kenjiArai 2:194f82ad3041 146 clk_lower_limit = ex_clk_base - err;
kenjiArai 3:339307e1dc0d 147 PRINTF("EXTERNAL Clock mode\r\n");
kenjiArai 4:9d3b3f0a3882 148 #else // defined(BASE_EXTERNAL_CLOCK)
kenjiArai 3:339307e1dc0d 149 ex_clock_freq = 100; // Internal 100MHz
kenjiArai 2:194f82ad3041 150 ex_clk_base = 100000000; // MHz->Hz
kenjiArai 2:194f82ad3041 151 clk_hi_const = 4000000; // 40mS
kenjiArai 3:339307e1dc0d 152 uint32_t err = 10000; // error range
kenjiArai 2:194f82ad3041 153 clk_upper_limit = ex_clk_base + err;
kenjiArai 2:194f82ad3041 154 clk_lower_limit = ex_clk_base - err;
kenjiArai 3:339307e1dc0d 155 PRINTF("INTERNAL Clock mode\r\n");
kenjiArai 4:9d3b3f0a3882 156 #endif // defined(BASE_EXTERNAL_CLOCK)
kenjiArai 2:194f82ad3041 157 }
kenjiArai 2:194f82ad3041 158
kenjiArai 1:102230f2879d 159 // Read new frequency data
kenjiArai 2:194f82ad3041 160 double FRQ_CUNTR::read_freq_data(void)
kenjiArai 1:102230f2879d 161 {
kenjiArai 1:102230f2879d 162 old_cntr_tim3p4 = counter_tim3p4;
kenjiArai 1:102230f2879d 163 counter_tim3p4 = read_ic2_counter_TIM3P4();
kenjiArai 2:194f82ad3041 164 double freq0 = (double)(counter_tim3p4 - old_cntr_tim3p4);
kenjiArai 2:194f82ad3041 165 newest_frequency = freq0 / gate_time;
kenjiArai 2:194f82ad3041 166 return newest_frequency;
kenjiArai 1:102230f2879d 167 }
kenjiArai 1:102230f2879d 168
kenjiArai 1:102230f2879d 169 // Read status (new frequency data is available or not)
kenjiArai 1:102230f2879d 170 uint32_t FRQ_CUNTR::status_freq_update(void)
kenjiArai 1:102230f2879d 171 {
kenjiArai 1:102230f2879d 172 return check_ic2_status_TIM3P4();
kenjiArai 1:102230f2879d 173 }
kenjiArai 1:102230f2879d 174
kenjiArai 1:102230f2879d 175 // Read status (new 1PPS data is available or not)
kenjiArai 1:102230f2879d 176 uint32_t FRQ_CUNTR::status_1pps(void)
kenjiArai 1:102230f2879d 177 {
kenjiArai 1:102230f2879d 178 return check_ic2_status_TIM2();
kenjiArai 1:102230f2879d 179 }
kenjiArai 1:102230f2879d 180
kenjiArai 1:102230f2879d 181 // Read GPS 1PPS counter value
kenjiArai 1:102230f2879d 182 uint32_t FRQ_CUNTR::set_1PPS_data(void)
kenjiArai 1:102230f2879d 183 {
kenjiArai 1:102230f2879d 184 uint32_t diff = tim2_cnt_data - tim2_old_cnt_data;
kenjiArai 2:194f82ad3041 185 if ((diff > clk_upper_limit) || (diff < clk_lower_limit)) {
kenjiArai 3:339307e1dc0d 186 PRINTF("IC0 %d %d %d \r\n", diff, clk_upper_limit, clk_lower_limit);
kenjiArai 2:194f82ad3041 187 gps_ready = 0;
kenjiArai 1:102230f2879d 188 return 0;
kenjiArai 1:102230f2879d 189 } else {
kenjiArai 2:194f82ad3041 190 gps_ready = 1;
kenjiArai 1:102230f2879d 191 onepps_cnt[onepps_num] = diff;
kenjiArai 1:102230f2879d 192 if (++onepps_num >= CNT_BF_SIZE) {
kenjiArai 1:102230f2879d 193 onepps_num = 0;
kenjiArai 1:102230f2879d 194 onepps_buf_full = 1;
kenjiArai 0:bfdc6ed58a06 195 }
kenjiArai 1:102230f2879d 196 onepps_newest = diff;
kenjiArai 1:102230f2879d 197 return diff;
kenjiArai 0:bfdc6ed58a06 198 }
kenjiArai 1:102230f2879d 199 }
kenjiArai 1:102230f2879d 200
kenjiArai 4:9d3b3f0a3882 201 // Avarage measued data GPS 1PPS by 25MHz External Clock
kenjiArai 1:102230f2879d 202 uint32_t FRQ_CUNTR::read_avarage_1pps(void)
kenjiArai 1:102230f2879d 203 {
kenjiArai 1:102230f2879d 204 uint64_t total = 0;
kenjiArai 1:102230f2879d 205 if (onepps_buf_full == 1) {
kenjiArai 1:102230f2879d 206 for (uint32_t i = 0; i < CNT_BF_SIZE; i++) {
kenjiArai 1:102230f2879d 207 total += (uint64_t)onepps_cnt[i];
kenjiArai 0:bfdc6ed58a06 208 }
kenjiArai 1:102230f2879d 209 onepps_cnt_avarage = total / CNT_BF_SIZE;
kenjiArai 3:339307e1dc0d 210 PRINTF("buf");
kenjiArai 1:102230f2879d 211 } else {
kenjiArai 1:102230f2879d 212 for (uint32_t i = 0; i < onepps_num; i++) {
kenjiArai 1:102230f2879d 213 total += (uint64_t)onepps_cnt[i];
kenjiArai 0:bfdc6ed58a06 214 }
kenjiArai 1:102230f2879d 215 onepps_cnt_avarage = total / onepps_num;
kenjiArai 3:339307e1dc0d 216 PRINTF("not");
kenjiArai 0:bfdc6ed58a06 217 }
kenjiArai 3:339307e1dc0d 218 PRINTF(" full, num= %3d , 1PPS/new= %9d\r\n", onepps_num, onepps_newest);
kenjiArai 1:102230f2879d 219 return onepps_cnt_avarage;
kenjiArai 4:9d3b3f0a3882 220 }
kenjiArai 4:9d3b3f0a3882 221
kenjiArai 4:9d3b3f0a3882 222 // Newest measued data GPS 1PPS
kenjiArai 4:9d3b3f0a3882 223 uint32_t FRQ_CUNTR::read_newest_1pps(void)
kenjiArai 4:9d3b3f0a3882 224 {
kenjiArai 2:194f82ad3041 225 return onepps_newest;
kenjiArai 2:194f82ad3041 226 }
kenjiArai 2:194f82ad3041 227
kenjiArai 2:194f82ad3041 228 // Check GPS condition
kenjiArai 3:339307e1dc0d 229 uint8_t FRQ_CUNTR::status_gps(void)
kenjiArai 2:194f82ad3041 230 {
kenjiArai 2:194f82ad3041 231 return gps_ready;
kenjiArai 1:102230f2879d 232 }
kenjiArai 1:102230f2879d 233
kenjiArai 1:102230f2879d 234 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 235 // TIM2 (32bit Counter + IC + OC)
kenjiArai 1:102230f2879d 236 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 237 // Read TIM2 captured counter value
kenjiArai 1:102230f2879d 238 uint32_t FRQ_CUNTR::read_ic2_counter_TIM2(void)
kenjiArai 1:102230f2879d 239 {
kenjiArai 1:102230f2879d 240 return tim2_cnt_data; // return TIM2->CCR2;
kenjiArai 1:102230f2879d 241 }
kenjiArai 1:102230f2879d 242
kenjiArai 1:102230f2879d 243 // Check TIM2 IC2 status
kenjiArai 1:102230f2879d 244 uint32_t FRQ_CUNTR::check_ic2_status_TIM2(void)
kenjiArai 1:102230f2879d 245 {
kenjiArai 1:102230f2879d 246 if (tim2_ready_flg == 0) {
kenjiArai 1:102230f2879d 247 return 0;
kenjiArai 1:102230f2879d 248 } else {
kenjiArai 1:102230f2879d 249 tim2_ready_flg = 0;
kenjiArai 1:102230f2879d 250 set_1PPS_data();
kenjiArai 1:102230f2879d 251 return 1;
kenjiArai 0:bfdc6ed58a06 252 }
kenjiArai 1:102230f2879d 253 }
kenjiArai 1:102230f2879d 254
kenjiArai 1:102230f2879d 255 // Check OC port status
kenjiArai 1:102230f2879d 256 uint8_t FRQ_CUNTR::read_oc_port_status(void)
kenjiArai 1:102230f2879d 257 {
kenjiArai 1:102230f2879d 258 uint32_t p = GPIOB->IDR;
kenjiArai 1:102230f2879d 259 if (p & 0x0400) { // Check PB10 status
kenjiArai 1:102230f2879d 260 return 1;
kenjiArai 1:102230f2879d 261 } else {
kenjiArai 1:102230f2879d 262 return 0;
kenjiArai 0:bfdc6ed58a06 263 }
kenjiArai 1:102230f2879d 264 }
kenjiArai 1:102230f2879d 265
kenjiArai 1:102230f2879d 266 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 267 // TIM3+TIM4 (32bit Counter + IC)
kenjiArai 1:102230f2879d 268 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 269 // Read TIM3+4(as 32bit) captured counter value
kenjiArai 1:102230f2879d 270 uint32_t FRQ_CUNTR::read_ic2_counter_TIM3P4(void)
kenjiArai 1:102230f2879d 271 {
kenjiArai 1:102230f2879d 272 return tim3p4_cnt_data;
kenjiArai 1:102230f2879d 273 }
kenjiArai 1:102230f2879d 274
kenjiArai 1:102230f2879d 275 // Check TIM3 IC2 & TIM4 IC1 status
kenjiArai 1:102230f2879d 276 uint32_t FRQ_CUNTR::check_ic2_status_TIM3P4(void)
kenjiArai 1:102230f2879d 277 {
kenjiArai 1:102230f2879d 278 if (tim3p4_ready_flg == 0) {
kenjiArai 1:102230f2879d 279 return 0;
kenjiArai 1:102230f2879d 280 } else {
kenjiArai 1:102230f2879d 281 tim3p4_ready_flg = 0;
kenjiArai 1:102230f2879d 282 return 1;
kenjiArai 0:bfdc6ed58a06 283 }
kenjiArai 1:102230f2879d 284 }
kenjiArai 1:102230f2879d 285
kenjiArai 1:102230f2879d 286 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 287 // Frequency check for test purpose
kenjiArai 1:102230f2879d 288 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 289 // Read TIM2 Clock frequency
kenjiArai 1:102230f2879d 290 uint32_t FRQ_CUNTR::read_frequency_TIM2(float gate_time)
kenjiArai 1:102230f2879d 291 {
kenjiArai 1:102230f2879d 292 uint32_t freq = 0;
kenjiArai 1:102230f2879d 293 TIM2->CNT = 0;
kenjiArai 1:102230f2879d 294 wait(gate_time); // Gate time for count
kenjiArai 1:102230f2879d 295 freq = TIM2->CNT; // read counter
kenjiArai 3:339307e1dc0d 296 PRINTF("Clock freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq, gate_time);
kenjiArai 1:102230f2879d 297 return freq; // return counter data
kenjiArai 1:102230f2879d 298 }
kenjiArai 1:102230f2879d 299
kenjiArai 1:102230f2879d 300 // Read TIM3(+TIM4) Input frequency
kenjiArai 1:102230f2879d 301 uint32_t FRQ_CUNTR::read_frequency_TIM3P4(float gate_time)
kenjiArai 1:102230f2879d 302 {
kenjiArai 1:102230f2879d 303 uint32_t freq0 = 0;
kenjiArai 1:102230f2879d 304 uint32_t freq1 = 0;
kenjiArai 1:102230f2879d 305 TIM3->CNT = 0;
kenjiArai 1:102230f2879d 306 TIM4->CNT = 0;
kenjiArai 1:102230f2879d 307 TIM3->CNT = 0;
kenjiArai 1:102230f2879d 308 wait(gate_time); // Gate time for count
kenjiArai 1:102230f2879d 309 freq0 = TIM3->CNT;
kenjiArai 1:102230f2879d 310 freq1 = TIM4->CNT;
kenjiArai 1:102230f2879d 311 freq0 = (freq1 << 16) + freq0;
kenjiArai 3:339307e1dc0d 312 PRINTF("Input freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq0, gate_time);
kenjiArai 1:102230f2879d 313 return freq0; // read counter
kenjiArai 1:102230f2879d 314 }
kenjiArai 1:102230f2879d 315
kenjiArai 1:102230f2879d 316 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 317 // Clock output for test purpose
kenjiArai 1:102230f2879d 318 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 319 // Output internal clock
kenjiArai 1:102230f2879d 320 void FRQ_CUNTR::port_mco1_mco2_set(uint8_t select)
kenjiArai 1:102230f2879d 321 {
kenjiArai 1:102230f2879d 322 // PA8 -> MCO_1
kenjiArai 1:102230f2879d 323 GPIOA->AFR[1] &= 0xfffffff0;
kenjiArai 1:102230f2879d 324 GPIOA->AFR[1] |= GPIO_AF0_MCO << 0;
kenjiArai 1:102230f2879d 325 GPIOA->MODER &= ~(GPIO_MODER_MODER8); // AF
kenjiArai 1:102230f2879d 326 GPIOA->MODER |= GPIO_MODER_MODER8_1;
kenjiArai 1:102230f2879d 327 GPIOA->OTYPER &= ~(GPIO_OTYPER_OT_8); // Output Push-Pull=0
kenjiArai 1:102230f2879d 328 GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8;// Speed full=11
kenjiArai 1:102230f2879d 329 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR8); // Pull-up=01
kenjiArai 1:102230f2879d 330 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR8_0;
kenjiArai 1:102230f2879d 331 // PC9 -> MCO_2
kenjiArai 1:102230f2879d 332 GPIOC->AFR[1] &= 0xffffff0f;
kenjiArai 1:102230f2879d 333 GPIOC->AFR[1] |= GPIO_AF0_MCO << 4;
kenjiArai 1:102230f2879d 334 GPIOC->MODER &= ~(GPIO_MODER_MODER9); // AF
kenjiArai 1:102230f2879d 335 GPIOC->MODER |= GPIO_MODER_MODER9_1;
kenjiArai 1:102230f2879d 336 GPIOC->OTYPER &= ~(GPIO_OTYPER_OT_9); // Output Push-Pull=0
kenjiArai 1:102230f2879d 337 GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9;// Speed full=11
kenjiArai 1:102230f2879d 338 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR9); // Pull-up=01
kenjiArai 1:102230f2879d 339 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR9_0;
kenjiArai 1:102230f2879d 340 // Select output clock source
kenjiArai 1:102230f2879d 341 RCC->CFGR &= 0x009fffff;
kenjiArai 1:102230f2879d 342 if (select == 1) {
kenjiArai 1:102230f2879d 343 // MC01 output HSE 1/1, MCO2 output SYSCLK 1/1
kenjiArai 1:102230f2879d 344 // MCO2 MCO2PRE MCO1PRE MCO1
kenjiArai 1:102230f2879d 345 RCC->CFGR |= (0x0 << 30) + (0x0 << 27) + (0x0 << 24) + (0x2 << 21);
kenjiArai 3:339307e1dc0d 346 PRINTF("Set MCO1(PA8):HSE/1, MCO2(PC9):SYSCLK/1\r\n");
kenjiArai 1:102230f2879d 347 } else if (select == 2) {
kenjiArai 1:102230f2879d 348 // MC01 output HSE 1/2, MCO2 output SYSCLK 1/2
kenjiArai 1:102230f2879d 349 // MCO2 MCO2PRE MCO1PRE MCO1
kenjiArai 1:102230f2879d 350 RCC->CFGR |= (0x0 << 30) + (0x4 << 27) + (0x4 << 24) + (0x2 << 21);
kenjiArai 3:339307e1dc0d 351 PRINTF("Set MCO1(PA8):HSE/2, MCO2(PC9):SYSCLK/2\r\n");
kenjiArai 1:102230f2879d 352 } else { // select = 4 and other wrong order
kenjiArai 1:102230f2879d 353 // MC01 output HSE 1/4, MCO2 output SYSCLK 1/4
kenjiArai 1:102230f2879d 354 // MCO2 MCO2PRE MCO1PRE MCO1
kenjiArai 1:102230f2879d 355 RCC->CFGR |= (0x0 << 30) + (0x6 << 27) + (0x6 << 24) + (0x2 << 21);
kenjiArai 3:339307e1dc0d 356 PRINTF("Set MCO1(PA8):HSE/4, MCO2(PC9):SYSCLK/4\r\n");
kenjiArai 0:bfdc6ed58a06 357 }
kenjiArai 1:102230f2879d 358 }
kenjiArai 1:102230f2879d 359
kenjiArai 1:102230f2879d 360 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 361 // Initialize TIM2 and TIM3+4
kenjiArai 1:102230f2879d 362 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 363 void FRQ_CUNTR::initialize_Freq_counter(void)
kenjiArai 1:102230f2879d 364 {
kenjiArai 1:102230f2879d 365 initialize_TIM2();
kenjiArai 1:102230f2879d 366 initialize_TIM3P4();
kenjiArai 1:102230f2879d 367 }
kenjiArai 1:102230f2879d 368
kenjiArai 1:102230f2879d 369 // Initialize TIM2
kenjiArai 1:102230f2879d 370 // Internal clock (100MHz) or External clock(?MHz) and IC2 for GPS 1pps signal measurement
kenjiArai 1:102230f2879d 371 void FRQ_CUNTR::initialize_TIM2(void)
kenjiArai 1:102230f2879d 372 {
kenjiArai 1:102230f2879d 373 #if defined(BASE_EXTERNAL_CLOCK)
kenjiArai 3:339307e1dc0d 374 // PA0 -> Counter frequency input pin as Timer2 CH1/ETR
kenjiArai 1:102230f2879d 375 RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN);
kenjiArai 1:102230f2879d 376 GPIOA->AFR[0] &= 0xfffffff0;
kenjiArai 1:102230f2879d 377 GPIOA->AFR[0] |= GPIO_AF1_TIM2;
kenjiArai 1:102230f2879d 378 GPIOA->MODER &= ~(GPIO_MODER_MODER0); // AF
kenjiArai 1:102230f2879d 379 GPIOA->MODER |= GPIO_MODER_MODER0_1;
kenjiArai 1:102230f2879d 380 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR0); // PU
kenjiArai 1:102230f2879d 381 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_0;
kenjiArai 1:102230f2879d 382 // Initialize Timer2(32bit) for an external up counter mode
kenjiArai 1:102230f2879d 383 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
kenjiArai 1:102230f2879d 384 TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
kenjiArai 1:102230f2879d 385 TIM2->CR1 |= TIM_CR1_URS;
kenjiArai 1:102230f2879d 386 TIM2->ARR = 0xffffffff;
kenjiArai 1:102230f2879d 387 TIM2->PSC = 0x0000;
kenjiArai 1:102230f2879d 388 TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1
kenjiArai 1:102230f2879d 389 TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S); // input filter + input select
kenjiArai 1:102230f2879d 390 TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
kenjiArai 1:102230f2879d 391 TIM2->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP); // positive edge
kenjiArai 3:339307e1dc0d 392 TIM2->SMCR = (uint16_t)(TIM_SMCR_ECE| TIM_SMCR_ETPS_0 | TIM_SMCR_TS); // clock/2 !!
kenjiArai 1:102230f2879d 393 TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 4:9d3b3f0a3882 394 #else // defined(BASE_EXTERNAL_CLOCK)
kenjiArai 2:194f82ad3041 395 // Initialize Timer2(32bit) for an internal up counter mode
kenjiArai 1:102230f2879d 396 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
kenjiArai 1:102230f2879d 397 TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD)); // count_up + div by 1
kenjiArai 1:102230f2879d 398 TIM2->CR1 |= TIM_CR1_URS;
kenjiArai 1:102230f2879d 399 TIM2->ARR = 0xffffffff;
kenjiArai 1:102230f2879d 400 TIM2->PSC = 0x0000;
kenjiArai 1:102230f2879d 401 TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1
kenjiArai 1:102230f2879d 402 TIM2->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);
kenjiArai 1:102230f2879d 403 TIM2->SMCR |= (uint16_t)0; // Internal clock = 100MHz
kenjiArai 1:102230f2879d 404 TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 4:9d3b3f0a3882 405 #endif // defined(BASE_EXTERNAL_CLOCK)
kenjiArai 1:102230f2879d 406 // PA1 -> Input Capture pin as Timer2 IC2
kenjiArai 1:102230f2879d 407 GPIOA->AFR[0] &= 0xffffff0f;
kenjiArai 1:102230f2879d 408 GPIOA->AFR[0] |= GPIO_AF1_TIM2 << 4;
kenjiArai 1:102230f2879d 409 GPIOA->MODER &= ~(GPIO_MODER_MODER1); // AF
kenjiArai 1:102230f2879d 410 GPIOA->MODER |= GPIO_MODER_MODER1_1;
kenjiArai 1:102230f2879d 411 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR1);
kenjiArai 1:102230f2879d 412 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_0; // PU
kenjiArai 1:102230f2879d 413 // Initialize Timer2 I.C.2
kenjiArai 1:102230f2879d 414 TIM2->CCER &= (uint16_t)~TIM_CCER_CC2E; // Disable the CC2
kenjiArai 1:102230f2879d 415 TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select
kenjiArai 1:102230f2879d 416 TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0;
kenjiArai 1:102230f2879d 417 TIM2->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge
kenjiArai 1:102230f2879d 418 TIM2->CCER |= (uint16_t)TIM_CCER_CC2E; // enable capture
kenjiArai 1:102230f2879d 419 // PB10 -> Output Compare pin as Timer2 CH3/OC3
kenjiArai 1:102230f2879d 420 GPIOB->AFR[1] &= 0xfffff0ff;
kenjiArai 1:102230f2879d 421 GPIOB->AFR[1] |= GPIO_AF1_TIM2 << 8;
kenjiArai 1:102230f2879d 422 GPIOB->MODER &= ~(GPIO_MODER_MODER10); // AF
kenjiArai 1:102230f2879d 423 GPIOB->MODER |= GPIO_MODER_MODER10_1;
kenjiArai 1:102230f2879d 424 GPIOB->OTYPER &= ~(GPIO_OTYPER_OT_10);// Output Push-Pull=0
kenjiArai 1:102230f2879d 425 GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10;// Speed full=11
kenjiArai 1:102230f2879d 426 GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR10); // Pull-up=01
kenjiArai 1:102230f2879d 427 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR10_0;
kenjiArai 1:102230f2879d 428 // Initialize Timer2 O.C.3
kenjiArai 1:102230f2879d 429 TIM2->CCER &= (uint16_t)~TIM_CCER_CC3E; // Reset the CC3E Bit
kenjiArai 1:102230f2879d 430 TIM2->CCMR2 &= (uint16_t)~(TIM_CCMR2_OC3M | TIM_CCMR2_CC3S |
kenjiArai 1:102230f2879d 431 TIM_CCMR2_OC3PE | TIM_CCMR2_OC3CE | TIM_CCMR2_OC3FE);
kenjiArai 1:102230f2879d 432 TIM2->CCMR2 |= (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1);
kenjiArai 1:102230f2879d 433 TIM2->CCER &= (uint16_t)~TIM_CCER_CC3P;// Reset the Output Polarity level
kenjiArai 1:102230f2879d 434 TIM2->CCER |= (uint16_t)TIM_CCER_CC3E; // Set the CC3E Bit
kenjiArai 1:102230f2879d 435 new_gt_value = 0;
kenjiArai 1:102230f2879d 436 oc_hi_time = oc_set_time0;
kenjiArai 1:102230f2879d 437 oc_lo_time = oc_set_time1;
kenjiArai 1:102230f2879d 438 TIM2->CCR3 = TIM2->CNT + oc_hi_time;// Set the Capture Compare Register value
kenjiArai 1:102230f2879d 439 // Only for Debug purpose
kenjiArai 1:102230f2879d 440 BAUD(9600);
kenjiArai 1:102230f2879d 441 // PA
kenjiArai 1:102230f2879d 442 PRINTF("\r\n// Timer2(32bit) for an internal up counter mode\r\n");
kenjiArai 1:102230f2879d 443 PRINTF("// PA1 -> Input Capture pin as Timer2 CH2/TI2\r\n");
kenjiArai 1:102230f2879d 444 PRINTF("GPIOA->AFR[0]0x%08x:0x%08x\r\n",&GPIOA->AFR[0], GPIOA->AFR[0]);
kenjiArai 1:102230f2879d 445 PRINTF("GPIOA->AFR[1]0x%08x:0x%08x\r\n",&GPIOA->AFR[1], GPIOA->AFR[1]);
kenjiArai 1:102230f2879d 446 PRINTF("GPIOA->MODER 0x%08x:0x%08x\r\n",&GPIOA->MODER, GPIOA->MODER);
kenjiArai 1:102230f2879d 447 PRINTF("GPIOA->PUPDR 0x%08x:0x%08x\r\n",&GPIOA->PUPDR, GPIOA->PUPDR);
kenjiArai 1:102230f2879d 448 // PB
kenjiArai 1:102230f2879d 449 PRINTF("// PB10 -> Output Compare pin as Timer2 CH3/TI3\r\n");
kenjiArai 1:102230f2879d 450 PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
kenjiArai 1:102230f2879d 451 PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
kenjiArai 1:102230f2879d 452 PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
kenjiArai 1:102230f2879d 453 PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
kenjiArai 1:102230f2879d 454 // TIM2
kenjiArai 1:102230f2879d 455 PRINTF("// PA1 -> Timer2 IC2\r\n");
kenjiArai 1:102230f2879d 456 PRINTF("// PB10-> Timer2 OC3\r\n");
kenjiArai 1:102230f2879d 457 PRINTF("TIM2->CR1 0x%08x:0x%08x\r\n",&TIM2->CR1, TIM2->CR1);
kenjiArai 1:102230f2879d 458 PRINTF("TIM2->ARR 0x%08x:0x%08x\r\n",&TIM2->ARR, TIM2->ARR);
kenjiArai 1:102230f2879d 459 PRINTF("TIM2->PSC 0x%08x:0x%08x\r\n",&TIM2->PSC, TIM2->PSC);
kenjiArai 1:102230f2879d 460 PRINTF("TIM2->CCMR1 0x%08x:0x%08x\r\n",&TIM2->CCMR1, TIM2->CCMR1);
kenjiArai 1:102230f2879d 461 PRINTF("TIM2->CCMR2 0x%08x:0x%08x\r\n",&TIM2->CCMR2, TIM2->CCMR2);
kenjiArai 1:102230f2879d 462 PRINTF("TIM2->CCER 0x%08x:0x%08x\r\n",&TIM2->CCER, TIM2->CCER);
kenjiArai 1:102230f2879d 463 PRINTF("TIM2->SMCR 0x%08x:0x%08x\r\n",&TIM2->SMCR, TIM2->SMCR);
kenjiArai 1:102230f2879d 464 PRINTF("TIM2->CCR3 0x%08x:0x%08x\r\n\r\n",&TIM2->CCR3, TIM2->CCR3);
kenjiArai 1:102230f2879d 465 // Interrupt Timer2 IC2
kenjiArai 1:102230f2879d 466 for (uint32_t i = 0; i < CNT_BF_SIZE; i++) {
kenjiArai 1:102230f2879d 467 onepps_cnt[i] = 0;
kenjiArai 0:bfdc6ed58a06 468 }
kenjiArai 1:102230f2879d 469 onepps_num = 0;
kenjiArai 1:102230f2879d 470 onepps_ready_flg = 0;
kenjiArai 1:102230f2879d 471 onepps_buf_full = 0;
kenjiArai 1:102230f2879d 472 onepps_cnt_avarage = 0;
kenjiArai 1:102230f2879d 473 tim2_ready_flg = 0;
kenjiArai 1:102230f2879d 474 tim2_cnt_data = 0;
kenjiArai 1:102230f2879d 475 tim2_old_cnt_data = 0;
kenjiArai 1:102230f2879d 476 TIM2->SR &= ~(TIM_SR_CC2IF + TIM_SR_CC3IF); // clear IC flag
kenjiArai 1:102230f2879d 477 TIM2->DIER |= TIM_DIER_CC2IE + TIM_DIER_CC3IE;
kenjiArai 1:102230f2879d 478 NVIC_SetVector(TIM2_IRQn, (uint32_t)irq_ic2_TIM2);
kenjiArai 1:102230f2879d 479 NVIC_ClearPendingIRQ(TIM2_IRQn);
kenjiArai 1:102230f2879d 480 NVIC_EnableIRQ(TIM2_IRQn);
kenjiArai 1:102230f2879d 481 }
kenjiArai 1:102230f2879d 482
kenjiArai 1:102230f2879d 483 // Initialize TIM3 and TIM4 as 32bit counter (TIM3(16bit) + TIM4(16bit))
kenjiArai 1:102230f2879d 484 // TIM3 clock input is unkown freq.(measuring freq.) and TIM4 is slave counter
kenjiArai 1:102230f2879d 485 // 1sec gate signal connected both TIM3 IC2 and TIM4 IC1
kenjiArai 1:102230f2879d 486 void FRQ_CUNTR::initialize_TIM3P4(void)
kenjiArai 1:102230f2879d 487 {
kenjiArai 1:102230f2879d 488 // PC6 -> Unkown frequency input pin as Timer3 CH1/TI1
kenjiArai 1:102230f2879d 489 RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN);
kenjiArai 1:102230f2879d 490 GPIOC->AFR[0] &= 0xf0ffffff;
kenjiArai 1:102230f2879d 491 GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 24;
kenjiArai 1:102230f2879d 492 GPIOC->MODER &= ~(GPIO_MODER_MODER6); // AF
kenjiArai 1:102230f2879d 493 GPIOC->MODER |= GPIO_MODER_MODER6_1;
kenjiArai 1:102230f2879d 494 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR6);
kenjiArai 1:102230f2879d 495 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR6_0; // PU
kenjiArai 1:102230f2879d 496 // Initialize Timer3(16bit) for an external up counter mode
kenjiArai 1:102230f2879d 497 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
kenjiArai 1:102230f2879d 498 TIM3->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
kenjiArai 1:102230f2879d 499 TIM3->CR1 |= (uint16_t)TIM_CR1_URS;
kenjiArai 1:102230f2879d 500 TIM3->ARR = 0xffff;
kenjiArai 1:102230f2879d 501 TIM3->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1
kenjiArai 1:102230f2879d 502 TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S); // input filter + input select
kenjiArai 1:102230f2879d 503 TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
kenjiArai 1:102230f2879d 504 TIM3->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP);// positive edge
kenjiArai 1:102230f2879d 505 TIM3->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1
kenjiArai 1:102230f2879d 506 TIM3->SMCR |= (uint16_t)( TIM_TS_TI1FP1 | TIM_SLAVEMODE_EXTERNAL1); // ECE must be ZERO!!!!
kenjiArai 1:102230f2879d 507 TIM3->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
kenjiArai 1:102230f2879d 508 TIM3->CR2 |= (uint16_t)TIM_CR2_MMS_1; // TRGO update
kenjiArai 1:102230f2879d 509 TIM3->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 1:102230f2879d 510 // Initialize Timer4(16bit) for an slave up counter of TIM3
kenjiArai 1:102230f2879d 511 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
kenjiArai 1:102230f2879d 512 TIM4->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
kenjiArai 1:102230f2879d 513 TIM4->CR1 |= (uint16_t)TIM_CR1_URS;
kenjiArai 1:102230f2879d 514 TIM4->ARR = 0xffff;
kenjiArai 1:102230f2879d 515 TIM4->CCER &= (uint16_t)TIM_CCER_CC1E; // Capture enable
kenjiArai 1:102230f2879d 516 TIM4->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1
kenjiArai 1:102230f2879d 517 TIM4->SMCR |= (uint16_t)( TIM_TS_ITR2 | TIM_SLAVEMODE_EXTERNAL1);// ECE must be ZERO!!!!
kenjiArai 1:102230f2879d 518 TIM4->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
kenjiArai 1:102230f2879d 519 TIM4->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 1:102230f2879d 520 // PC7 -> Input Capture pin as Timer3 IC2
kenjiArai 1:102230f2879d 521 GPIOC->AFR[0] &= 0x0fffffff;
kenjiArai 1:102230f2879d 522 GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 28;
kenjiArai 1:102230f2879d 523 GPIOC->MODER &= ~(GPIO_MODER_MODER7); // AF
kenjiArai 1:102230f2879d 524 GPIOC->MODER |= GPIO_MODER_MODER7_1;
kenjiArai 1:102230f2879d 525 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR7);
kenjiArai 1:102230f2879d 526 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_0; // PU
kenjiArai 1:102230f2879d 527 // Initialize Timer3 IC2
kenjiArai 1:102230f2879d 528 TIM3->CCER &= (uint16_t)~TIM_CCER_CC2E; // Disable the CC2
kenjiArai 1:102230f2879d 529 TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select
kenjiArai 1:102230f2879d 530 TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0;
kenjiArai 1:102230f2879d 531 TIM3->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge
kenjiArai 1:102230f2879d 532 TIM3->CCER |= (uint16_t)TIM_CCER_CC2E; // enable capture
kenjiArai 1:102230f2879d 533 // PB6 -> Input Capture pin as Timer4 IC1
kenjiArai 1:102230f2879d 534 GPIOB->AFR[0] &= 0xf0ffffff;
kenjiArai 1:102230f2879d 535 GPIOB->AFR[0] |= GPIO_AF2_TIM4 << 24;
kenjiArai 1:102230f2879d 536 GPIOB->MODER &= ~(GPIO_MODER_MODER6); // AF
kenjiArai 1:102230f2879d 537 GPIOB->MODER |= GPIO_MODER_MODER6_1;
kenjiArai 1:102230f2879d 538 GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR6);
kenjiArai 1:102230f2879d 539 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_0; // Pull-up=01
kenjiArai 1:102230f2879d 540 // Initialize Timer4 IC1
kenjiArai 1:102230f2879d 541 TIM4->CCER &= (uint16_t)~TIM_CCER_CC1E;
kenjiArai 1:102230f2879d 542 TIM4->CCMR1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
kenjiArai 1:102230f2879d 543 TIM4->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
kenjiArai 1:102230f2879d 544 TIM4->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); // positive edge
kenjiArai 1:102230f2879d 545 TIM4->CCER |= (uint16_t)TIM_CCER_CC1E; // enable capture
kenjiArai 1:102230f2879d 546 // Only for Debug purpose
kenjiArai 1:102230f2879d 547 // PB
kenjiArai 1:102230f2879d 548 PRINTF("// PB6 -> Input Capture pin as Timer4 CH1/TI1\r\n");
kenjiArai 1:102230f2879d 549 PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
kenjiArai 1:102230f2879d 550 PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
kenjiArai 1:102230f2879d 551 PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
kenjiArai 1:102230f2879d 552 PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
kenjiArai 1:102230f2879d 553 PRINTF("GPIOB->OTYPER 0x%08x:0x%08x\r\n",&GPIOB->OTYPER, GPIOB->OTYPER);
kenjiArai 1:102230f2879d 554 PRINTF("GPIOB->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOB->OSPEEDR, GPIOB->OSPEEDR);
kenjiArai 1:102230f2879d 555 // PC
kenjiArai 1:102230f2879d 556 PRINTF("// PC6 -> unkown frequency input pin as Timer3 CH1/TI1\r\n");
kenjiArai 1:102230f2879d 557 PRINTF("// PC7 -> Input Capture pin as Timer3 CH2/TI2\r\n");
kenjiArai 1:102230f2879d 558 PRINTF("GPIOC->AFR[0]0x%08x:0x%08x\r\n",&GPIOC->AFR[0], GPIOC->AFR[0]);
kenjiArai 1:102230f2879d 559 PRINTF("GPIOC->AFR[1]0x%08x:0x%08x\r\n",&GPIOC->AFR[1], GPIOC->AFR[1]);
kenjiArai 1:102230f2879d 560 PRINTF("GPIOC->MODER 0x%08x:0x%08x\r\n",&GPIOC->MODER, GPIOC->MODER);
kenjiArai 1:102230f2879d 561 PRINTF("GPIOC->PUPDR 0x%08x:0x%08x\r\n",&GPIOC->PUPDR, GPIOC->PUPDR);
kenjiArai 1:102230f2879d 562 PRINTF("GPIOC->OTYPER 0x%08x:0x%08x\r\n",&GPIOC->OTYPER, GPIOC->OTYPER);
kenjiArai 1:102230f2879d 563 PRINTF("GPIOC->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOC->OSPEEDR, GPIOC->OSPEEDR);
kenjiArai 1:102230f2879d 564 // TIM3
kenjiArai 1:102230f2879d 565 PRINTF("// PC6 -> Timer3(16bit) for an external up counter mode\r\n");
kenjiArai 1:102230f2879d 566 PRINTF("// PC7 -> Timer3 IC2\r\n");
kenjiArai 1:102230f2879d 567 PRINTF("TIM3->CR1 0x%08x:0x%08x\r\n",&TIM3->CR1, TIM3->CR1);
kenjiArai 1:102230f2879d 568 PRINTF("TIM3->ARR 0x%08x:0x%08x\r\n",&TIM3->ARR, TIM3->ARR);
kenjiArai 1:102230f2879d 569 PRINTF("TIM3->PSC 0x%08x:0x%08x\r\n",&TIM3->PSC, TIM3->PSC);
kenjiArai 1:102230f2879d 570 PRINTF("TIM3->CCMR1 0x%08x:0x%08x\r\n",&TIM3->CCMR1, TIM3->CCMR1);
kenjiArai 1:102230f2879d 571 PRINTF("TIM3->CCMR2 0x%08x:0x%08x\r\n",&TIM3->CCMR2, TIM3->CCMR2);
kenjiArai 1:102230f2879d 572 PRINTF("TIM3->CCER 0x%08x:0x%08x\r\n",&TIM3->CCER, TIM3->CCER);
kenjiArai 1:102230f2879d 573 PRINTF("TIM3->SMCR 0x%08x:0x%08x\r\n",&TIM3->SMCR, TIM3->SMCR);
kenjiArai 1:102230f2879d 574 // TIM4
kenjiArai 1:102230f2879d 575 PRINTF("// none-> Timer4(16bit) for an slave counter\r\n");
kenjiArai 1:102230f2879d 576 PRINTF("// PB6 -> Timer4 IC1\r\n");
kenjiArai 1:102230f2879d 577 PRINTF("TIM4->CR1 0x%08x:0x%08x\r\n",&TIM4->CR1, TIM4->CR1);
kenjiArai 1:102230f2879d 578 PRINTF("TIM4->ARR 0x%08x:0x%08x\r\n",&TIM4->ARR, TIM4->ARR);
kenjiArai 1:102230f2879d 579 PRINTF("TIM4->PSC 0x%08x:0x%08x\r\n",&TIM4->PSC, TIM4->PSC);
kenjiArai 1:102230f2879d 580 PRINTF("TIM4->CCMR1 0x%08x:0x%08x\r\n",&TIM4->CCMR1, TIM4->CCMR1);
kenjiArai 1:102230f2879d 581 PRINTF("TIM4->CCMR2 0x%08x:0x%08x\r\n",&TIM4->CCMR2, TIM4->CCMR2);
kenjiArai 1:102230f2879d 582 PRINTF("TIM4->CCER 0x%08x:0x%08x\r\n",&TIM4->CCER, TIM4->CCER);
kenjiArai 1:102230f2879d 583 PRINTF("TIM4->SMCR 0x%08x:0x%08x\r\n\r\n",&TIM4->SMCR, TIM4->SMCR);
kenjiArai 1:102230f2879d 584 PRINTF("RCC->APB1ENR 0x%08x:0x%08x\r\n\r\n",&RCC->APB1ENR, RCC->APB1ENR);
kenjiArai 1:102230f2879d 585 // Interrupt Timer3 IC2
kenjiArai 1:102230f2879d 586 tim3p4_ready_flg = 0;
kenjiArai 1:102230f2879d 587 tim3p4_cnt_data = 0;
kenjiArai 1:102230f2879d 588 TIM3->SR &= ~TIM_SR_CC2IF; // clear IC flag
kenjiArai 1:102230f2879d 589 TIM4->SR &= ~TIM_SR_CC1IF;
kenjiArai 1:102230f2879d 590 TIM3->DIER |= TIM_DIER_CC2IE;
kenjiArai 1:102230f2879d 591 NVIC_SetVector(TIM3_IRQn, (uint32_t)irq_ic2_TIM3P4);
kenjiArai 1:102230f2879d 592 NVIC_ClearPendingIRQ(TIM3_IRQn);
kenjiArai 1:102230f2879d 593 NVIC_EnableIRQ(TIM3_IRQn);
kenjiArai 1:102230f2879d 594 }
kenjiArai 0:bfdc6ed58a06 595
kenjiArai 2:194f82ad3041 596 //---------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 597 // Only for Debug purpose
kenjiArai 2:194f82ad3041 598 //---------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 599 void FRQ_CUNTR::debug_printf_internal_data(void)
kenjiArai 2:194f82ad3041 600 {
kenjiArai 2:194f82ad3041 601 PRINTF("Debug information\r\n");
kenjiArai 2:194f82ad3041 602 PRINTF("gate_time %f\r\n", gate_time);
kenjiArai 2:194f82ad3041 603 PRINTF("ex_clock_freq %f\r\n", ex_clock_freq);
kenjiArai 2:194f82ad3041 604 PRINTF("ex_clk_base %9d\r\n", ex_clk_base);
kenjiArai 2:194f82ad3041 605 PRINTF("clk_hi_const %9d\r\n", clk_hi_const);
kenjiArai 2:194f82ad3041 606 PRINTF("clk_upper_limit %9d\r\n", clk_upper_limit);
kenjiArai 2:194f82ad3041 607 PRINTF("clk_lower_limit %9d\r\n", clk_lower_limit);
kenjiArai 2:194f82ad3041 608 PRINTF("\r\n");
kenjiArai 2:194f82ad3041 609 }
kenjiArai 2:194f82ad3041 610
kenjiArai 0:bfdc6ed58a06 611 } // Frequency_counter
kenjiArai 4:9d3b3f0a3882 612
kenjiArai 4:9d3b3f0a3882 613 #endif // #if defined(TARGET_NUCLEO_F411RE)