Kenji Arai / Frq_cuntr_full

Frequency counter library only for NucleoF411RE

Dependents:   Frequency_Counter_w_GPS_1PPS

frq_cuntr_full.cpp@3:339307e1dc0d, 2014-12-23 (annotated)

Committer:
kenjiArai
Date:
Tue Dec 23 23:26:49 2014 +0000
Revision:
3:339307e1dc0d
Parent:
2:194f82ad3041
Child:
4:9d3b3f0a3882
change clock input PA0, CH1 to ETR, change debug functions, add new functions

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 0:bfdc6ed58a06 1 /*
kenjiArai 1:102230f2879d 2 * mbed Library / Frequency Counter with GPS 1PPS Compensation
kenjiArai 0:bfdc6ed58a06 3 * Frequency Counter Hardware relataed program
kenjiArai 1:102230f2879d 4 * Only for ST Nucleo F411RE
kenjiArai 0:bfdc6ed58a06 5 *
kenjiArai 0:bfdc6ed58a06 6 * Copyright (c) 2014 Kenji Arai / JH1PJL
kenjiArai 0:bfdc6ed58a06 7 * http://www.page.sannet.ne.jp/kenjia/index.html
kenjiArai 0:bfdc6ed58a06 8 * http://mbed.org/users/kenjiArai/
kenjiArai 0:bfdc6ed58a06 9 * Additional functions and modification
kenjiArai 0:bfdc6ed58a06 10 * started: October 18th, 2014
kenjiArai 3:339307e1dc0d 11 * Revised: December 24th, 2014
kenjiArai 0:bfdc6ed58a06 12 *
kenjiArai 0:bfdc6ed58a06 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
kenjiArai 0:bfdc6ed58a06 14 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
kenjiArai 0:bfdc6ed58a06 15 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
kenjiArai 0:bfdc6ed58a06 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
kenjiArai 0:bfdc6ed58a06 17 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
kenjiArai 0:bfdc6ed58a06 18 */
kenjiArai 0:bfdc6ed58a06 19
kenjiArai 0:bfdc6ed58a06 20 #include "frq_cuntr_full.h"
kenjiArai 0:bfdc6ed58a06 21
kenjiArai 0:bfdc6ed58a06 22 #ifdef DEBUG
kenjiArai 0:bfdc6ed58a06 23 Serial pcm(USBTX, USBRX);
kenjiArai 0:bfdc6ed58a06 24 DigitalOut debug_led(LED1);
kenjiArai 0:bfdc6ed58a06 25 #endif
kenjiArai 0:bfdc6ed58a06 26
kenjiArai 0:bfdc6ed58a06 27 #ifdef DEBUG
kenjiArai 0:bfdc6ed58a06 28 #define BAUD(x) pcm.baud(x)
kenjiArai 0:bfdc6ed58a06 29 #define GETC(x) pcm.getc(x)
kenjiArai 0:bfdc6ed58a06 30 #define PUTC(x) pcm.putc(x)
kenjiArai 0:bfdc6ed58a06 31 #define PRINTF(...) pcm.printf(__VA_ARGS__)
kenjiArai 0:bfdc6ed58a06 32 #define READABLE(x) pcm.readable(x)
kenjiArai 0:bfdc6ed58a06 33 #else
kenjiArai 0:bfdc6ed58a06 34 #define BAUD(x) {;}
kenjiArai 0:bfdc6ed58a06 35 #define GETC(x) {;}
kenjiArai 0:bfdc6ed58a06 36 #define PUTC(x) {;}
kenjiArai 0:bfdc6ed58a06 37 #define PRINTF(...) {;}
kenjiArai 0:bfdc6ed58a06 38 #define READABLE(x) {;}
kenjiArai 0:bfdc6ed58a06 39 #endif
kenjiArai 0:bfdc6ed58a06 40
kenjiArai 0:bfdc6ed58a06 41 namespace Frequency_counter
kenjiArai 0:bfdc6ed58a06 42 {
kenjiArai 1:102230f2879d 43 // TIM2 OC
kenjiArai 2:194f82ad3041 44 static uint32_t oc_set_time0;
kenjiArai 2:194f82ad3041 45 static uint32_t oc_set_time1;
kenjiArai 2:194f82ad3041 46 static uint8_t new_gt_value;
kenjiArai 2:194f82ad3041 47 static uint32_t oc_hi_time;
kenjiArai 2:194f82ad3041 48 static uint32_t oc_lo_time;
kenjiArai 1:102230f2879d 49 // TIM2 IC
kenjiArai 1:102230f2879d 50 static uint8_t tim2_ready_flg;
kenjiArai 1:102230f2879d 51 static uint32_t tim2_cnt_data;
kenjiArai 1:102230f2879d 52 static uint32_t tim2_old_cnt_data;
kenjiArai 1:102230f2879d 53 // TIM3+4 IC
kenjiArai 1:102230f2879d 54 static uint8_t tim3p4_ready_flg;
kenjiArai 1:102230f2879d 55 static uint32_t tim3p4_cnt_data;
kenjiArai 1:102230f2879d 56
kenjiArai 1:102230f2879d 57 //-------------------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 58 // Interrupt Handlers
kenjiArai 1:102230f2879d 59 //-------------------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 60 // TIM2 IC2 Interrupt control
kenjiArai 1:102230f2879d 61 void irq_ic2_TIM2(void)
kenjiArai 1:102230f2879d 62 {
kenjiArai 1:102230f2879d 63 uint16_t reg;
kenjiArai 1:102230f2879d 64 reg = TIM2->SR;
kenjiArai 1:102230f2879d 65 if (reg & TIM_SR_CC2IF) {
kenjiArai 1:102230f2879d 66 TIM2->SR &= ~TIM_SR_CC2IF; // clear IC flag
kenjiArai 1:102230f2879d 67 tim2_old_cnt_data = tim2_cnt_data;
kenjiArai 1:102230f2879d 68 tim2_cnt_data = TIM2->CCR2;
kenjiArai 1:102230f2879d 69 tim2_ready_flg = 1;
kenjiArai 2:194f82ad3041 70 #if defined(DEBUG)
kenjiArai 2:194f82ad3041 71 debug_led = !debug_led;
kenjiArai 2:194f82ad3041 72 #endif
kenjiArai 2:194f82ad3041 73 } else if (reg & TIM_SR_CC3IF) { // Output Compare
kenjiArai 1:102230f2879d 74 TIM2->SR &= ~TIM_SR_CC3IF; // clear IC flag
kenjiArai 2:194f82ad3041 75 if (GPIOB->IDR & 0x0400) { // Check PB10 status
kenjiArai 1:102230f2879d 76 TIM2->CCR3 = TIM2->CCR3 + oc_hi_time;
kenjiArai 1:102230f2879d 77 } else {
kenjiArai 1:102230f2879d 78 TIM2->CCR3 = TIM2->CCR3 + oc_lo_time;
kenjiArai 1:102230f2879d 79 if (new_gt_value) {
kenjiArai 1:102230f2879d 80 new_gt_value = 0;
kenjiArai 1:102230f2879d 81 oc_hi_time = oc_set_time0;
kenjiArai 1:102230f2879d 82 oc_lo_time = oc_set_time1;
kenjiArai 1:102230f2879d 83 }
kenjiArai 0:bfdc6ed58a06 84 }
kenjiArai 0:bfdc6ed58a06 85 #if defined(DEBUG)
kenjiArai 3:339307e1dc0d 86 debug_led = !debug_led;
kenjiArai 0:bfdc6ed58a06 87 #endif
kenjiArai 0:bfdc6ed58a06 88 }
kenjiArai 1:102230f2879d 89 }
kenjiArai 1:102230f2879d 90
kenjiArai 1:102230f2879d 91 // TIM3 IC2 Interrupt control (same signal connected to TIM4 IC1)
kenjiArai 1:102230f2879d 92 void irq_ic2_TIM3P4(void)
kenjiArai 1:102230f2879d 93 {
kenjiArai 1:102230f2879d 94 TIM3->SR &= ~TIM_SR_CC2IF; // clear IC flag
kenjiArai 1:102230f2879d 95 TIM4->SR &= ~TIM_SR_CC1IF;
kenjiArai 1:102230f2879d 96 tim3p4_cnt_data = (TIM4->CCR1 << 16) + TIM3->CCR2;
kenjiArai 1:102230f2879d 97 tim3p4_ready_flg = 1;
kenjiArai 0:bfdc6ed58a06 98 #if defined(DEBUG)
kenjiArai 3:339307e1dc0d 99 debug_led = !debug_led;
kenjiArai 0:bfdc6ed58a06 100 #endif
kenjiArai 1:102230f2879d 101 }
kenjiArai 1:102230f2879d 102
kenjiArai 1:102230f2879d 103 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 104 // Frequency Counter
kenjiArai 1:102230f2879d 105 //---------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 106 FRQ_CUNTR::FRQ_CUNTR(PinName f_in, double gt, double ex_clock): _pin(f_in)
kenjiArai 1:102230f2879d 107 {
kenjiArai 2:194f82ad3041 108 // Don't change calling sequence!!
kenjiArai 2:194f82ad3041 109 set_external_clock(ex_clock); // 1st
kenjiArai 2:194f82ad3041 110 set_gate_time(gt); // 2nd
kenjiArai 2:194f82ad3041 111 initialize_Freq_counter(); // 3rd
kenjiArai 1:102230f2879d 112 }
kenjiArai 1:102230f2879d 113
kenjiArai 1:102230f2879d 114 // Set gate time
kenjiArai 1:102230f2879d 115 double FRQ_CUNTR::set_gate_time(double gt)
kenjiArai 1:102230f2879d 116 {
kenjiArai 1:102230f2879d 117 if (gt < 0.05) {
kenjiArai 1:102230f2879d 118 gate_time = 0.05;
kenjiArai 1:102230f2879d 119 } else if (gt > 60.0) {
kenjiArai 1:102230f2879d 120 gate_time = 60.0;
kenjiArai 1:102230f2879d 121 } else {
kenjiArai 1:102230f2879d 122 gate_time = gt;
kenjiArai 0:bfdc6ed58a06 123 }
kenjiArai 2:194f82ad3041 124 oc_set_time0 = clk_hi_const;
kenjiArai 2:194f82ad3041 125 double gt_tmp0 = ex_clk_base * gate_time;
kenjiArai 1:102230f2879d 126 uint32_t gt_tmp1 = (uint32_t)gt_tmp0;
kenjiArai 1:102230f2879d 127 if ((gt_tmp0 - (double)gt_tmp1) >= 0.5) {
kenjiArai 1:102230f2879d 128 ++gt_tmp1;
kenjiArai 0:bfdc6ed58a06 129 }
kenjiArai 2:194f82ad3041 130 oc_set_time1 = gt_tmp1 - clk_hi_const;
kenjiArai 1:102230f2879d 131 new_gt_value = 1;
kenjiArai 1:102230f2879d 132 return gate_time;
kenjiArai 1:102230f2879d 133 }
kenjiArai 1:102230f2879d 134
kenjiArai 2:194f82ad3041 135 // Read gate time
kenjiArai 2:194f82ad3041 136 double FRQ_CUNTR::read_gate_time(void)
kenjiArai 2:194f82ad3041 137 {
kenjiArai 2:194f82ad3041 138 return gate_time;
kenjiArai 2:194f82ad3041 139 }
kenjiArai 2:194f82ad3041 140
kenjiArai 2:194f82ad3041 141 // Set External Clock Frequency
kenjiArai 2:194f82ad3041 142 void FRQ_CUNTR::set_external_clock(double ex_clock)
kenjiArai 2:194f82ad3041 143 {
kenjiArai 2:194f82ad3041 144 #if defined(BASE_EXTERNAL_CLOCK)
kenjiArai 2:194f82ad3041 145 ex_clock_freq = ex_clock;
kenjiArai 2:194f82ad3041 146 ex_clk_base = (uint32_t)(ex_clock_freq * 1000000); // MHz->Hz
kenjiArai 2:194f82ad3041 147 clk_hi_const = (uint32_t)(ex_clock_freq * 1000000 * 0.04); // 40mS
kenjiArai 3:339307e1dc0d 148 #if defined(CLOCK_DIVIDED_BY_2)
kenjiArai 3:339307e1dc0d 149 uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.00001); // 10ppm error range
kenjiArai 3:339307e1dc0d 150 #else
kenjiArai 3:339307e1dc0d 151 uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.1); // error range
kenjiArai 3:339307e1dc0d 152 #endif
kenjiArai 2:194f82ad3041 153 clk_upper_limit = ex_clk_base + err;
kenjiArai 2:194f82ad3041 154 clk_lower_limit = ex_clk_base - err;
kenjiArai 3:339307e1dc0d 155 PRINTF("EXTERNAL Clock mode\r\n");
kenjiArai 2:194f82ad3041 156 #else
kenjiArai 3:339307e1dc0d 157 ex_clock_freq = 100; // Internal 100MHz
kenjiArai 2:194f82ad3041 158 ex_clk_base = 100000000; // MHz->Hz
kenjiArai 2:194f82ad3041 159 clk_hi_const = 4000000; // 40mS
kenjiArai 3:339307e1dc0d 160 uint32_t err = 10000; // error range
kenjiArai 2:194f82ad3041 161 clk_upper_limit = ex_clk_base + err;
kenjiArai 2:194f82ad3041 162 clk_lower_limit = ex_clk_base - err;
kenjiArai 3:339307e1dc0d 163 PRINTF("INTERNAL Clock mode\r\n");
kenjiArai 2:194f82ad3041 164 #endif
kenjiArai 2:194f82ad3041 165 }
kenjiArai 2:194f82ad3041 166
kenjiArai 1:102230f2879d 167 // Read new frequency data
kenjiArai 2:194f82ad3041 168 double FRQ_CUNTR::read_freq_data(void)
kenjiArai 1:102230f2879d 169 {
kenjiArai 1:102230f2879d 170 old_cntr_tim3p4 = counter_tim3p4;
kenjiArai 1:102230f2879d 171 counter_tim3p4 = read_ic2_counter_TIM3P4();
kenjiArai 2:194f82ad3041 172 double freq0 = (double)(counter_tim3p4 - old_cntr_tim3p4);
kenjiArai 2:194f82ad3041 173 newest_frequency = freq0 / gate_time;
kenjiArai 2:194f82ad3041 174 return newest_frequency;
kenjiArai 1:102230f2879d 175 }
kenjiArai 1:102230f2879d 176
kenjiArai 1:102230f2879d 177 // Read status (new frequency data is available or not)
kenjiArai 1:102230f2879d 178 uint32_t FRQ_CUNTR::status_freq_update(void)
kenjiArai 1:102230f2879d 179 {
kenjiArai 1:102230f2879d 180 return check_ic2_status_TIM3P4();
kenjiArai 1:102230f2879d 181 }
kenjiArai 1:102230f2879d 182
kenjiArai 1:102230f2879d 183 // Read status (new 1PPS data is available or not)
kenjiArai 1:102230f2879d 184 uint32_t FRQ_CUNTR::status_1pps(void)
kenjiArai 1:102230f2879d 185 {
kenjiArai 1:102230f2879d 186 return check_ic2_status_TIM2();
kenjiArai 1:102230f2879d 187 }
kenjiArai 1:102230f2879d 188
kenjiArai 1:102230f2879d 189 // Read GPS 1PPS counter value
kenjiArai 1:102230f2879d 190 uint32_t FRQ_CUNTR::set_1PPS_data(void)
kenjiArai 1:102230f2879d 191 {
kenjiArai 1:102230f2879d 192 uint32_t diff = tim2_cnt_data - tim2_old_cnt_data;
kenjiArai 2:194f82ad3041 193 if ((diff > clk_upper_limit) || (diff < clk_lower_limit)) {
kenjiArai 3:339307e1dc0d 194 PRINTF("IC0 %d %d %d \r\n", diff, clk_upper_limit, clk_lower_limit);
kenjiArai 2:194f82ad3041 195 gps_ready = 0;
kenjiArai 1:102230f2879d 196 return 0;
kenjiArai 1:102230f2879d 197 } else {
kenjiArai 2:194f82ad3041 198 gps_ready = 1;
kenjiArai 1:102230f2879d 199 onepps_cnt[onepps_num] = diff;
kenjiArai 1:102230f2879d 200 if (++onepps_num >= CNT_BF_SIZE) {
kenjiArai 1:102230f2879d 201 onepps_num = 0;
kenjiArai 1:102230f2879d 202 onepps_buf_full = 1;
kenjiArai 0:bfdc6ed58a06 203 }
kenjiArai 1:102230f2879d 204 onepps_newest = diff;
kenjiArai 1:102230f2879d 205 return diff;
kenjiArai 0:bfdc6ed58a06 206 }
kenjiArai 1:102230f2879d 207 }
kenjiArai 1:102230f2879d 208
kenjiArai 1:102230f2879d 209 // Avarage measued data GPS 1PPS by 50MHz Internal Clock
kenjiArai 1:102230f2879d 210 uint32_t FRQ_CUNTR::read_avarage_1pps(void)
kenjiArai 1:102230f2879d 211 {
kenjiArai 1:102230f2879d 212 uint64_t total = 0;
kenjiArai 1:102230f2879d 213 if (onepps_buf_full == 1) {
kenjiArai 1:102230f2879d 214 for (uint32_t i = 0; i < CNT_BF_SIZE; i++) {
kenjiArai 1:102230f2879d 215 total += (uint64_t)onepps_cnt[i];
kenjiArai 0:bfdc6ed58a06 216 }
kenjiArai 1:102230f2879d 217 onepps_cnt_avarage = total / CNT_BF_SIZE;
kenjiArai 3:339307e1dc0d 218 PRINTF("buf");
kenjiArai 1:102230f2879d 219 } else {
kenjiArai 1:102230f2879d 220 for (uint32_t i = 0; i < onepps_num; i++) {
kenjiArai 1:102230f2879d 221 total += (uint64_t)onepps_cnt[i];
kenjiArai 0:bfdc6ed58a06 222 }
kenjiArai 1:102230f2879d 223 onepps_cnt_avarage = total / onepps_num;
kenjiArai 3:339307e1dc0d 224 PRINTF("not");
kenjiArai 0:bfdc6ed58a06 225 }
kenjiArai 3:339307e1dc0d 226 PRINTF(" full, num= %3d , 1PPS/new= %9d\r\n", onepps_num, onepps_newest);
kenjiArai 3:339307e1dc0d 227 #if defined(BASE_EXTERNAL_CLOCK)
kenjiArai 2:194f82ad3041 228 #if defined(ONEPPS_AVE)
kenjiArai 1:102230f2879d 229 return onepps_cnt_avarage;
kenjiArai 2:194f82ad3041 230 #else
kenjiArai 2:194f82ad3041 231 return onepps_newest;
kenjiArai 2:194f82ad3041 232 #endif
kenjiArai 3:339307e1dc0d 233 #else
kenjiArai 3:339307e1dc0d 234 return onepps_newest;
kenjiArai 3:339307e1dc0d 235 #endif
kenjiArai 2:194f82ad3041 236 }
kenjiArai 2:194f82ad3041 237
kenjiArai 2:194f82ad3041 238 // Check GPS condition
kenjiArai 3:339307e1dc0d 239 uint8_t FRQ_CUNTR::status_gps(void)
kenjiArai 2:194f82ad3041 240 {
kenjiArai 2:194f82ad3041 241 return gps_ready;
kenjiArai 1:102230f2879d 242 }
kenjiArai 1:102230f2879d 243
kenjiArai 1:102230f2879d 244 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 245 // TIM2 (32bit Counter + IC + OC)
kenjiArai 1:102230f2879d 246 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 247 // Read TIM2 captured counter value
kenjiArai 1:102230f2879d 248 uint32_t FRQ_CUNTR::read_ic2_counter_TIM2(void)
kenjiArai 1:102230f2879d 249 {
kenjiArai 1:102230f2879d 250 return tim2_cnt_data; // return TIM2->CCR2;
kenjiArai 1:102230f2879d 251 }
kenjiArai 1:102230f2879d 252
kenjiArai 1:102230f2879d 253 // Check TIM2 IC2 status
kenjiArai 1:102230f2879d 254 uint32_t FRQ_CUNTR::check_ic2_status_TIM2(void)
kenjiArai 1:102230f2879d 255 {
kenjiArai 1:102230f2879d 256 if (tim2_ready_flg == 0) {
kenjiArai 1:102230f2879d 257 return 0;
kenjiArai 1:102230f2879d 258 } else {
kenjiArai 1:102230f2879d 259 tim2_ready_flg = 0;
kenjiArai 1:102230f2879d 260 set_1PPS_data();
kenjiArai 1:102230f2879d 261 return 1;
kenjiArai 0:bfdc6ed58a06 262 }
kenjiArai 1:102230f2879d 263 }
kenjiArai 1:102230f2879d 264
kenjiArai 1:102230f2879d 265 // Check OC port status
kenjiArai 1:102230f2879d 266 uint8_t FRQ_CUNTR::read_oc_port_status(void)
kenjiArai 1:102230f2879d 267 {
kenjiArai 1:102230f2879d 268 uint32_t p = GPIOB->IDR;
kenjiArai 1:102230f2879d 269 if (p & 0x0400) { // Check PB10 status
kenjiArai 1:102230f2879d 270 return 1;
kenjiArai 1:102230f2879d 271 } else {
kenjiArai 1:102230f2879d 272 return 0;
kenjiArai 0:bfdc6ed58a06 273 }
kenjiArai 1:102230f2879d 274 }
kenjiArai 1:102230f2879d 275
kenjiArai 1:102230f2879d 276 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 277 // TIM3+TIM4 (32bit Counter + IC)
kenjiArai 1:102230f2879d 278 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 279 // Read TIM3+4(as 32bit) captured counter value
kenjiArai 1:102230f2879d 280 uint32_t FRQ_CUNTR::read_ic2_counter_TIM3P4(void)
kenjiArai 1:102230f2879d 281 {
kenjiArai 1:102230f2879d 282 return tim3p4_cnt_data;
kenjiArai 1:102230f2879d 283 }
kenjiArai 1:102230f2879d 284
kenjiArai 1:102230f2879d 285 // Check TIM3 IC2 & TIM4 IC1 status
kenjiArai 1:102230f2879d 286 uint32_t FRQ_CUNTR::check_ic2_status_TIM3P4(void)
kenjiArai 1:102230f2879d 287 {
kenjiArai 1:102230f2879d 288 if (tim3p4_ready_flg == 0) {
kenjiArai 1:102230f2879d 289 return 0;
kenjiArai 1:102230f2879d 290 } else {
kenjiArai 1:102230f2879d 291 tim3p4_ready_flg = 0;
kenjiArai 1:102230f2879d 292 return 1;
kenjiArai 0:bfdc6ed58a06 293 }
kenjiArai 1:102230f2879d 294 }
kenjiArai 1:102230f2879d 295
kenjiArai 1:102230f2879d 296 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 297 // Frequency check for test purpose
kenjiArai 1:102230f2879d 298 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 299 // Read TIM2 Clock frequency
kenjiArai 1:102230f2879d 300 uint32_t FRQ_CUNTR::read_frequency_TIM2(float gate_time)
kenjiArai 1:102230f2879d 301 {
kenjiArai 1:102230f2879d 302 uint32_t freq = 0;
kenjiArai 1:102230f2879d 303 TIM2->CNT = 0;
kenjiArai 1:102230f2879d 304 wait(gate_time); // Gate time for count
kenjiArai 1:102230f2879d 305 freq = TIM2->CNT; // read counter
kenjiArai 3:339307e1dc0d 306 PRINTF("Clock freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq, gate_time);
kenjiArai 1:102230f2879d 307 return freq; // return counter data
kenjiArai 1:102230f2879d 308 }
kenjiArai 1:102230f2879d 309
kenjiArai 1:102230f2879d 310 // Read TIM3(+TIM4) Input frequency
kenjiArai 1:102230f2879d 311 uint32_t FRQ_CUNTR::read_frequency_TIM3P4(float gate_time)
kenjiArai 1:102230f2879d 312 {
kenjiArai 1:102230f2879d 313 uint32_t freq0 = 0;
kenjiArai 1:102230f2879d 314 uint32_t freq1 = 0;
kenjiArai 1:102230f2879d 315 TIM3->CNT = 0;
kenjiArai 1:102230f2879d 316 TIM4->CNT = 0;
kenjiArai 1:102230f2879d 317 TIM3->CNT = 0;
kenjiArai 1:102230f2879d 318 wait(gate_time); // Gate time for count
kenjiArai 1:102230f2879d 319 freq0 = TIM3->CNT;
kenjiArai 1:102230f2879d 320 freq1 = TIM4->CNT;
kenjiArai 1:102230f2879d 321 freq0 = (freq1 << 16) + freq0;
kenjiArai 3:339307e1dc0d 322 PRINTF("Input freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq0, gate_time);
kenjiArai 1:102230f2879d 323 return freq0; // read counter
kenjiArai 1:102230f2879d 324 }
kenjiArai 1:102230f2879d 325
kenjiArai 1:102230f2879d 326 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 327 // Clock output for test purpose
kenjiArai 1:102230f2879d 328 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 329 // Output internal clock
kenjiArai 1:102230f2879d 330 void FRQ_CUNTR::port_mco1_mco2_set(uint8_t select)
kenjiArai 1:102230f2879d 331 {
kenjiArai 1:102230f2879d 332 // PA8 -> MCO_1
kenjiArai 1:102230f2879d 333 GPIOA->AFR[1] &= 0xfffffff0;
kenjiArai 1:102230f2879d 334 GPIOA->AFR[1] |= GPIO_AF0_MCO << 0;
kenjiArai 1:102230f2879d 335 GPIOA->MODER &= ~(GPIO_MODER_MODER8); // AF
kenjiArai 1:102230f2879d 336 GPIOA->MODER |= GPIO_MODER_MODER8_1;
kenjiArai 1:102230f2879d 337 GPIOA->OTYPER &= ~(GPIO_OTYPER_OT_8); // Output Push-Pull=0
kenjiArai 1:102230f2879d 338 GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8;// Speed full=11
kenjiArai 1:102230f2879d 339 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR8); // Pull-up=01
kenjiArai 1:102230f2879d 340 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR8_0;
kenjiArai 1:102230f2879d 341 // PC9 -> MCO_2
kenjiArai 1:102230f2879d 342 GPIOC->AFR[1] &= 0xffffff0f;
kenjiArai 1:102230f2879d 343 GPIOC->AFR[1] |= GPIO_AF0_MCO << 4;
kenjiArai 1:102230f2879d 344 GPIOC->MODER &= ~(GPIO_MODER_MODER9); // AF
kenjiArai 1:102230f2879d 345 GPIOC->MODER |= GPIO_MODER_MODER9_1;
kenjiArai 1:102230f2879d 346 GPIOC->OTYPER &= ~(GPIO_OTYPER_OT_9); // Output Push-Pull=0
kenjiArai 1:102230f2879d 347 GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9;// Speed full=11
kenjiArai 1:102230f2879d 348 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR9); // Pull-up=01
kenjiArai 1:102230f2879d 349 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR9_0;
kenjiArai 1:102230f2879d 350 // Select output clock source
kenjiArai 1:102230f2879d 351 RCC->CFGR &= 0x009fffff;
kenjiArai 1:102230f2879d 352 if (select == 1) {
kenjiArai 1:102230f2879d 353 // MC01 output HSE 1/1, MCO2 output SYSCLK 1/1
kenjiArai 1:102230f2879d 354 // MCO2 MCO2PRE MCO1PRE MCO1
kenjiArai 1:102230f2879d 355 RCC->CFGR |= (0x0 << 30) + (0x0 << 27) + (0x0 << 24) + (0x2 << 21);
kenjiArai 3:339307e1dc0d 356 PRINTF("Set MCO1(PA8):HSE/1, MCO2(PC9):SYSCLK/1\r\n");
kenjiArai 1:102230f2879d 357 } else if (select == 2) {
kenjiArai 1:102230f2879d 358 // MC01 output HSE 1/2, MCO2 output SYSCLK 1/2
kenjiArai 1:102230f2879d 359 // MCO2 MCO2PRE MCO1PRE MCO1
kenjiArai 1:102230f2879d 360 RCC->CFGR |= (0x0 << 30) + (0x4 << 27) + (0x4 << 24) + (0x2 << 21);
kenjiArai 3:339307e1dc0d 361 PRINTF("Set MCO1(PA8):HSE/2, MCO2(PC9):SYSCLK/2\r\n");
kenjiArai 1:102230f2879d 362 } else { // select = 4 and other wrong order
kenjiArai 1:102230f2879d 363 // MC01 output HSE 1/4, MCO2 output SYSCLK 1/4
kenjiArai 1:102230f2879d 364 // MCO2 MCO2PRE MCO1PRE MCO1
kenjiArai 1:102230f2879d 365 RCC->CFGR |= (0x0 << 30) + (0x6 << 27) + (0x6 << 24) + (0x2 << 21);
kenjiArai 3:339307e1dc0d 366 PRINTF("Set MCO1(PA8):HSE/4, MCO2(PC9):SYSCLK/4\r\n");
kenjiArai 0:bfdc6ed58a06 367 }
kenjiArai 1:102230f2879d 368 }
kenjiArai 1:102230f2879d 369
kenjiArai 1:102230f2879d 370 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 371 // Initialize TIM2 and TIM3+4
kenjiArai 1:102230f2879d 372 //---------------------------------------------------------------------------------------
kenjiArai 1:102230f2879d 373 void FRQ_CUNTR::initialize_Freq_counter(void)
kenjiArai 1:102230f2879d 374 {
kenjiArai 1:102230f2879d 375 initialize_TIM2();
kenjiArai 1:102230f2879d 376 initialize_TIM3P4();
kenjiArai 1:102230f2879d 377 }
kenjiArai 1:102230f2879d 378
kenjiArai 1:102230f2879d 379 // Initialize TIM2
kenjiArai 1:102230f2879d 380 // Internal clock (100MHz) or External clock(?MHz) and IC2 for GPS 1pps signal measurement
kenjiArai 1:102230f2879d 381 void FRQ_CUNTR::initialize_TIM2(void)
kenjiArai 1:102230f2879d 382 {
kenjiArai 1:102230f2879d 383 #if defined(BASE_EXTERNAL_CLOCK)
kenjiArai 3:339307e1dc0d 384 // PA0 -> Counter frequency input pin as Timer2 CH1/ETR
kenjiArai 1:102230f2879d 385 RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN);
kenjiArai 1:102230f2879d 386 GPIOA->AFR[0] &= 0xfffffff0;
kenjiArai 1:102230f2879d 387 GPIOA->AFR[0] |= GPIO_AF1_TIM2;
kenjiArai 1:102230f2879d 388 GPIOA->MODER &= ~(GPIO_MODER_MODER0); // AF
kenjiArai 1:102230f2879d 389 GPIOA->MODER |= GPIO_MODER_MODER0_1;
kenjiArai 1:102230f2879d 390 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR0); // PU
kenjiArai 1:102230f2879d 391 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_0;
kenjiArai 1:102230f2879d 392 // Initialize Timer2(32bit) for an external up counter mode
kenjiArai 1:102230f2879d 393 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
kenjiArai 1:102230f2879d 394 TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
kenjiArai 1:102230f2879d 395 TIM2->CR1 |= TIM_CR1_URS;
kenjiArai 1:102230f2879d 396 TIM2->ARR = 0xffffffff;
kenjiArai 1:102230f2879d 397 TIM2->PSC = 0x0000;
kenjiArai 1:102230f2879d 398 TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1
kenjiArai 1:102230f2879d 399 TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S); // input filter + input select
kenjiArai 1:102230f2879d 400 TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
kenjiArai 1:102230f2879d 401 TIM2->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP); // positive edge
kenjiArai 3:339307e1dc0d 402 #if defined(CLOCK_DIVIDED_BY_2)
kenjiArai 3:339307e1dc0d 403 TIM2->SMCR = (uint16_t)(TIM_SMCR_ECE| TIM_SMCR_ETPS_0 | TIM_SMCR_TS); // clock/2 !!
kenjiArai 3:339307e1dc0d 404 #else
kenjiArai 3:339307e1dc0d 405 TIM2->SMCR = (uint16_t)(TIM_SMCR_ECE| TIM_SMCR_TS); // clock/1 !!
kenjiArai 3:339307e1dc0d 406 #endif
kenjiArai 1:102230f2879d 407 TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 1:102230f2879d 408 #else
kenjiArai 2:194f82ad3041 409 // Initialize Timer2(32bit) for an internal up counter mode
kenjiArai 1:102230f2879d 410 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
kenjiArai 1:102230f2879d 411 TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD)); // count_up + div by 1
kenjiArai 1:102230f2879d 412 TIM2->CR1 |= TIM_CR1_URS;
kenjiArai 1:102230f2879d 413 TIM2->ARR = 0xffffffff;
kenjiArai 1:102230f2879d 414 TIM2->PSC = 0x0000;
kenjiArai 1:102230f2879d 415 TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1
kenjiArai 1:102230f2879d 416 TIM2->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);
kenjiArai 1:102230f2879d 417 TIM2->SMCR |= (uint16_t)0; // Internal clock = 100MHz
kenjiArai 1:102230f2879d 418 TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 1:102230f2879d 419 #endif
kenjiArai 1:102230f2879d 420 // PA1 -> Input Capture pin as Timer2 IC2
kenjiArai 1:102230f2879d 421 GPIOA->AFR[0] &= 0xffffff0f;
kenjiArai 1:102230f2879d 422 GPIOA->AFR[0] |= GPIO_AF1_TIM2 << 4;
kenjiArai 1:102230f2879d 423 GPIOA->MODER &= ~(GPIO_MODER_MODER1); // AF
kenjiArai 1:102230f2879d 424 GPIOA->MODER |= GPIO_MODER_MODER1_1;
kenjiArai 1:102230f2879d 425 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR1);
kenjiArai 1:102230f2879d 426 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_0; // PU
kenjiArai 1:102230f2879d 427 // Initialize Timer2 I.C.2
kenjiArai 1:102230f2879d 428 TIM2->CCER &= (uint16_t)~TIM_CCER_CC2E; // Disable the CC2
kenjiArai 1:102230f2879d 429 TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select
kenjiArai 1:102230f2879d 430 TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0;
kenjiArai 1:102230f2879d 431 TIM2->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge
kenjiArai 1:102230f2879d 432 TIM2->CCER |= (uint16_t)TIM_CCER_CC2E; // enable capture
kenjiArai 1:102230f2879d 433 // PB10 -> Output Compare pin as Timer2 CH3/OC3
kenjiArai 1:102230f2879d 434 GPIOB->AFR[1] &= 0xfffff0ff;
kenjiArai 1:102230f2879d 435 GPIOB->AFR[1] |= GPIO_AF1_TIM2 << 8;
kenjiArai 1:102230f2879d 436 GPIOB->MODER &= ~(GPIO_MODER_MODER10); // AF
kenjiArai 1:102230f2879d 437 GPIOB->MODER |= GPIO_MODER_MODER10_1;
kenjiArai 1:102230f2879d 438 GPIOB->OTYPER &= ~(GPIO_OTYPER_OT_10);// Output Push-Pull=0
kenjiArai 1:102230f2879d 439 GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10;// Speed full=11
kenjiArai 1:102230f2879d 440 GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR10); // Pull-up=01
kenjiArai 1:102230f2879d 441 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR10_0;
kenjiArai 1:102230f2879d 442 // Initialize Timer2 O.C.3
kenjiArai 1:102230f2879d 443 TIM2->CCER &= (uint16_t)~TIM_CCER_CC3E; // Reset the CC3E Bit
kenjiArai 1:102230f2879d 444 TIM2->CCMR2 &= (uint16_t)~(TIM_CCMR2_OC3M | TIM_CCMR2_CC3S |
kenjiArai 1:102230f2879d 445 TIM_CCMR2_OC3PE | TIM_CCMR2_OC3CE | TIM_CCMR2_OC3FE);
kenjiArai 1:102230f2879d 446 TIM2->CCMR2 |= (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1);
kenjiArai 1:102230f2879d 447 TIM2->CCER &= (uint16_t)~TIM_CCER_CC3P;// Reset the Output Polarity level
kenjiArai 1:102230f2879d 448 TIM2->CCER |= (uint16_t)TIM_CCER_CC3E; // Set the CC3E Bit
kenjiArai 1:102230f2879d 449 new_gt_value = 0;
kenjiArai 1:102230f2879d 450 oc_hi_time = oc_set_time0;
kenjiArai 1:102230f2879d 451 oc_lo_time = oc_set_time1;
kenjiArai 1:102230f2879d 452 TIM2->CCR3 = TIM2->CNT + oc_hi_time;// Set the Capture Compare Register value
kenjiArai 3:339307e1dc0d 453 #if 1
kenjiArai 1:102230f2879d 454 // Only for Debug purpose
kenjiArai 1:102230f2879d 455 BAUD(9600);
kenjiArai 1:102230f2879d 456 // PA
kenjiArai 1:102230f2879d 457 PRINTF("\r\n// Timer2(32bit) for an internal up counter mode\r\n");
kenjiArai 1:102230f2879d 458 PRINTF("// PA1 -> Input Capture pin as Timer2 CH2/TI2\r\n");
kenjiArai 1:102230f2879d 459 PRINTF("GPIOA->AFR[0]0x%08x:0x%08x\r\n",&GPIOA->AFR[0], GPIOA->AFR[0]);
kenjiArai 1:102230f2879d 460 PRINTF("GPIOA->AFR[1]0x%08x:0x%08x\r\n",&GPIOA->AFR[1], GPIOA->AFR[1]);
kenjiArai 1:102230f2879d 461 PRINTF("GPIOA->MODER 0x%08x:0x%08x\r\n",&GPIOA->MODER, GPIOA->MODER);
kenjiArai 1:102230f2879d 462 PRINTF("GPIOA->PUPDR 0x%08x:0x%08x\r\n",&GPIOA->PUPDR, GPIOA->PUPDR);
kenjiArai 1:102230f2879d 463 // PB
kenjiArai 1:102230f2879d 464 PRINTF("// PB10 -> Output Compare pin as Timer2 CH3/TI3\r\n");
kenjiArai 1:102230f2879d 465 PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
kenjiArai 1:102230f2879d 466 PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
kenjiArai 1:102230f2879d 467 PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
kenjiArai 1:102230f2879d 468 PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
kenjiArai 1:102230f2879d 469 // TIM2
kenjiArai 1:102230f2879d 470 PRINTF("// PA1 -> Timer2 IC2\r\n");
kenjiArai 1:102230f2879d 471 PRINTF("// PB10-> Timer2 OC3\r\n");
kenjiArai 1:102230f2879d 472 PRINTF("TIM2->CR1 0x%08x:0x%08x\r\n",&TIM2->CR1, TIM2->CR1);
kenjiArai 1:102230f2879d 473 PRINTF("TIM2->ARR 0x%08x:0x%08x\r\n",&TIM2->ARR, TIM2->ARR);
kenjiArai 1:102230f2879d 474 PRINTF("TIM2->PSC 0x%08x:0x%08x\r\n",&TIM2->PSC, TIM2->PSC);
kenjiArai 1:102230f2879d 475 PRINTF("TIM2->CCMR1 0x%08x:0x%08x\r\n",&TIM2->CCMR1, TIM2->CCMR1);
kenjiArai 1:102230f2879d 476 PRINTF("TIM2->CCMR2 0x%08x:0x%08x\r\n",&TIM2->CCMR2, TIM2->CCMR2);
kenjiArai 1:102230f2879d 477 PRINTF("TIM2->CCER 0x%08x:0x%08x\r\n",&TIM2->CCER, TIM2->CCER);
kenjiArai 1:102230f2879d 478 PRINTF("TIM2->SMCR 0x%08x:0x%08x\r\n",&TIM2->SMCR, TIM2->SMCR);
kenjiArai 1:102230f2879d 479 PRINTF("TIM2->CCR3 0x%08x:0x%08x\r\n\r\n",&TIM2->CCR3, TIM2->CCR3);
kenjiArai 2:194f82ad3041 480 #endif
kenjiArai 1:102230f2879d 481 // Interrupt Timer2 IC2
kenjiArai 1:102230f2879d 482 for (uint32_t i = 0; i < CNT_BF_SIZE; i++) {
kenjiArai 1:102230f2879d 483 onepps_cnt[i] = 0;
kenjiArai 0:bfdc6ed58a06 484 }
kenjiArai 1:102230f2879d 485 onepps_num = 0;
kenjiArai 1:102230f2879d 486 onepps_ready_flg = 0;
kenjiArai 1:102230f2879d 487 onepps_buf_full = 0;
kenjiArai 1:102230f2879d 488 onepps_cnt_avarage = 0;
kenjiArai 1:102230f2879d 489 tim2_ready_flg = 0;
kenjiArai 1:102230f2879d 490 tim2_cnt_data = 0;
kenjiArai 1:102230f2879d 491 tim2_old_cnt_data = 0;
kenjiArai 1:102230f2879d 492 TIM2->SR &= ~(TIM_SR_CC2IF + TIM_SR_CC3IF); // clear IC flag
kenjiArai 1:102230f2879d 493 TIM2->DIER |= TIM_DIER_CC2IE + TIM_DIER_CC3IE;
kenjiArai 1:102230f2879d 494 NVIC_SetVector(TIM2_IRQn, (uint32_t)irq_ic2_TIM2);
kenjiArai 1:102230f2879d 495 NVIC_ClearPendingIRQ(TIM2_IRQn);
kenjiArai 1:102230f2879d 496 NVIC_EnableIRQ(TIM2_IRQn);
kenjiArai 1:102230f2879d 497 }
kenjiArai 1:102230f2879d 498
kenjiArai 1:102230f2879d 499 // Initialize TIM3 and TIM4 as 32bit counter (TIM3(16bit) + TIM4(16bit))
kenjiArai 1:102230f2879d 500 // TIM3 clock input is unkown freq.(measuring freq.) and TIM4 is slave counter
kenjiArai 1:102230f2879d 501 // 1sec gate signal connected both TIM3 IC2 and TIM4 IC1
kenjiArai 1:102230f2879d 502 void FRQ_CUNTR::initialize_TIM3P4(void)
kenjiArai 1:102230f2879d 503 {
kenjiArai 1:102230f2879d 504 // PC6 -> Unkown frequency input pin as Timer3 CH1/TI1
kenjiArai 1:102230f2879d 505 RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN);
kenjiArai 1:102230f2879d 506 GPIOC->AFR[0] &= 0xf0ffffff;
kenjiArai 1:102230f2879d 507 GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 24;
kenjiArai 1:102230f2879d 508 GPIOC->MODER &= ~(GPIO_MODER_MODER6); // AF
kenjiArai 1:102230f2879d 509 GPIOC->MODER |= GPIO_MODER_MODER6_1;
kenjiArai 1:102230f2879d 510 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR6);
kenjiArai 1:102230f2879d 511 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR6_0; // PU
kenjiArai 1:102230f2879d 512 // Initialize Timer3(16bit) for an external up counter mode
kenjiArai 1:102230f2879d 513 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
kenjiArai 1:102230f2879d 514 TIM3->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
kenjiArai 1:102230f2879d 515 TIM3->CR1 |= (uint16_t)TIM_CR1_URS;
kenjiArai 1:102230f2879d 516 TIM3->ARR = 0xffff;
kenjiArai 1:102230f2879d 517 TIM3->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1
kenjiArai 1:102230f2879d 518 TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S); // input filter + input select
kenjiArai 1:102230f2879d 519 TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
kenjiArai 1:102230f2879d 520 TIM3->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP);// positive edge
kenjiArai 1:102230f2879d 521 TIM3->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1
kenjiArai 1:102230f2879d 522 TIM3->SMCR |= (uint16_t)( TIM_TS_TI1FP1 | TIM_SLAVEMODE_EXTERNAL1); // ECE must be ZERO!!!!
kenjiArai 1:102230f2879d 523 TIM3->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
kenjiArai 1:102230f2879d 524 TIM3->CR2 |= (uint16_t)TIM_CR2_MMS_1; // TRGO update
kenjiArai 1:102230f2879d 525 TIM3->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 1:102230f2879d 526 // Initialize Timer4(16bit) for an slave up counter of TIM3
kenjiArai 1:102230f2879d 527 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
kenjiArai 1:102230f2879d 528 TIM4->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1
kenjiArai 1:102230f2879d 529 TIM4->CR1 |= (uint16_t)TIM_CR1_URS;
kenjiArai 1:102230f2879d 530 TIM4->ARR = 0xffff;
kenjiArai 1:102230f2879d 531 TIM4->CCER &= (uint16_t)TIM_CCER_CC1E; // Capture enable
kenjiArai 1:102230f2879d 532 TIM4->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1
kenjiArai 1:102230f2879d 533 TIM4->SMCR |= (uint16_t)( TIM_TS_ITR2 | TIM_SLAVEMODE_EXTERNAL1);// ECE must be ZERO!!!!
kenjiArai 1:102230f2879d 534 TIM4->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
kenjiArai 1:102230f2879d 535 TIM4->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 1:102230f2879d 536 // PC7 -> Input Capture pin as Timer3 IC2
kenjiArai 1:102230f2879d 537 GPIOC->AFR[0] &= 0x0fffffff;
kenjiArai 1:102230f2879d 538 GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 28;
kenjiArai 1:102230f2879d 539 GPIOC->MODER &= ~(GPIO_MODER_MODER7); // AF
kenjiArai 1:102230f2879d 540 GPIOC->MODER |= GPIO_MODER_MODER7_1;
kenjiArai 1:102230f2879d 541 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR7);
kenjiArai 1:102230f2879d 542 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_0; // PU
kenjiArai 1:102230f2879d 543 // Initialize Timer3 IC2
kenjiArai 1:102230f2879d 544 TIM3->CCER &= (uint16_t)~TIM_CCER_CC2E; // Disable the CC2
kenjiArai 1:102230f2879d 545 TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select
kenjiArai 1:102230f2879d 546 TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0;
kenjiArai 1:102230f2879d 547 TIM3->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge
kenjiArai 1:102230f2879d 548 TIM3->CCER |= (uint16_t)TIM_CCER_CC2E; // enable capture
kenjiArai 1:102230f2879d 549 // PB6 -> Input Capture pin as Timer4 IC1
kenjiArai 1:102230f2879d 550 GPIOB->AFR[0] &= 0xf0ffffff;
kenjiArai 1:102230f2879d 551 GPIOB->AFR[0] |= GPIO_AF2_TIM4 << 24;
kenjiArai 1:102230f2879d 552 GPIOB->MODER &= ~(GPIO_MODER_MODER6); // AF
kenjiArai 1:102230f2879d 553 GPIOB->MODER |= GPIO_MODER_MODER6_1;
kenjiArai 1:102230f2879d 554 GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR6);
kenjiArai 1:102230f2879d 555 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_0; // Pull-up=01
kenjiArai 1:102230f2879d 556 // Initialize Timer4 IC1
kenjiArai 1:102230f2879d 557 TIM4->CCER &= (uint16_t)~TIM_CCER_CC1E;
kenjiArai 1:102230f2879d 558 TIM4->CCMR1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
kenjiArai 1:102230f2879d 559 TIM4->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0;
kenjiArai 1:102230f2879d 560 TIM4->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); // positive edge
kenjiArai 1:102230f2879d 561 TIM4->CCER |= (uint16_t)TIM_CCER_CC1E; // enable capture
kenjiArai 3:339307e1dc0d 562 #if 1
kenjiArai 1:102230f2879d 563 // Only for Debug purpose
kenjiArai 1:102230f2879d 564 // PB
kenjiArai 1:102230f2879d 565 PRINTF("// PB6 -> Input Capture pin as Timer4 CH1/TI1\r\n");
kenjiArai 1:102230f2879d 566 PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
kenjiArai 1:102230f2879d 567 PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
kenjiArai 1:102230f2879d 568 PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
kenjiArai 1:102230f2879d 569 PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
kenjiArai 1:102230f2879d 570 PRINTF("GPIOB->OTYPER 0x%08x:0x%08x\r\n",&GPIOB->OTYPER, GPIOB->OTYPER);
kenjiArai 1:102230f2879d 571 PRINTF("GPIOB->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOB->OSPEEDR, GPIOB->OSPEEDR);
kenjiArai 1:102230f2879d 572 // PC
kenjiArai 1:102230f2879d 573 PRINTF("// PC6 -> unkown frequency input pin as Timer3 CH1/TI1\r\n");
kenjiArai 1:102230f2879d 574 PRINTF("// PC7 -> Input Capture pin as Timer3 CH2/TI2\r\n");
kenjiArai 1:102230f2879d 575 PRINTF("GPIOC->AFR[0]0x%08x:0x%08x\r\n",&GPIOC->AFR[0], GPIOC->AFR[0]);
kenjiArai 1:102230f2879d 576 PRINTF("GPIOC->AFR[1]0x%08x:0x%08x\r\n",&GPIOC->AFR[1], GPIOC->AFR[1]);
kenjiArai 1:102230f2879d 577 PRINTF("GPIOC->MODER 0x%08x:0x%08x\r\n",&GPIOC->MODER, GPIOC->MODER);
kenjiArai 1:102230f2879d 578 PRINTF("GPIOC->PUPDR 0x%08x:0x%08x\r\n",&GPIOC->PUPDR, GPIOC->PUPDR);
kenjiArai 1:102230f2879d 579 PRINTF("GPIOC->OTYPER 0x%08x:0x%08x\r\n",&GPIOC->OTYPER, GPIOC->OTYPER);
kenjiArai 1:102230f2879d 580 PRINTF("GPIOC->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOC->OSPEEDR, GPIOC->OSPEEDR);
kenjiArai 1:102230f2879d 581 // TIM3
kenjiArai 1:102230f2879d 582 PRINTF("// PC6 -> Timer3(16bit) for an external up counter mode\r\n");
kenjiArai 1:102230f2879d 583 PRINTF("// PC7 -> Timer3 IC2\r\n");
kenjiArai 1:102230f2879d 584 PRINTF("TIM3->CR1 0x%08x:0x%08x\r\n",&TIM3->CR1, TIM3->CR1);
kenjiArai 1:102230f2879d 585 PRINTF("TIM3->ARR 0x%08x:0x%08x\r\n",&TIM3->ARR, TIM3->ARR);
kenjiArai 1:102230f2879d 586 PRINTF("TIM3->PSC 0x%08x:0x%08x\r\n",&TIM3->PSC, TIM3->PSC);
kenjiArai 1:102230f2879d 587 PRINTF("TIM3->CCMR1 0x%08x:0x%08x\r\n",&TIM3->CCMR1, TIM3->CCMR1);
kenjiArai 1:102230f2879d 588 PRINTF("TIM3->CCMR2 0x%08x:0x%08x\r\n",&TIM3->CCMR2, TIM3->CCMR2);
kenjiArai 1:102230f2879d 589 PRINTF("TIM3->CCER 0x%08x:0x%08x\r\n",&TIM3->CCER, TIM3->CCER);
kenjiArai 1:102230f2879d 590 PRINTF("TIM3->SMCR 0x%08x:0x%08x\r\n",&TIM3->SMCR, TIM3->SMCR);
kenjiArai 1:102230f2879d 591 // TIM4
kenjiArai 1:102230f2879d 592 PRINTF("// none-> Timer4(16bit) for an slave counter\r\n");
kenjiArai 1:102230f2879d 593 PRINTF("// PB6 -> Timer4 IC1\r\n");
kenjiArai 1:102230f2879d 594 PRINTF("TIM4->CR1 0x%08x:0x%08x\r\n",&TIM4->CR1, TIM4->CR1);
kenjiArai 1:102230f2879d 595 PRINTF("TIM4->ARR 0x%08x:0x%08x\r\n",&TIM4->ARR, TIM4->ARR);
kenjiArai 1:102230f2879d 596 PRINTF("TIM4->PSC 0x%08x:0x%08x\r\n",&TIM4->PSC, TIM4->PSC);
kenjiArai 1:102230f2879d 597 PRINTF("TIM4->CCMR1 0x%08x:0x%08x\r\n",&TIM4->CCMR1, TIM4->CCMR1);
kenjiArai 1:102230f2879d 598 PRINTF("TIM4->CCMR2 0x%08x:0x%08x\r\n",&TIM4->CCMR2, TIM4->CCMR2);
kenjiArai 1:102230f2879d 599 PRINTF("TIM4->CCER 0x%08x:0x%08x\r\n",&TIM4->CCER, TIM4->CCER);
kenjiArai 1:102230f2879d 600 PRINTF("TIM4->SMCR 0x%08x:0x%08x\r\n\r\n",&TIM4->SMCR, TIM4->SMCR);
kenjiArai 1:102230f2879d 601 PRINTF("RCC->APB1ENR 0x%08x:0x%08x\r\n\r\n",&RCC->APB1ENR, RCC->APB1ENR);
kenjiArai 2:194f82ad3041 602 #endif
kenjiArai 1:102230f2879d 603 // Interrupt Timer3 IC2
kenjiArai 1:102230f2879d 604 tim3p4_ready_flg = 0;
kenjiArai 1:102230f2879d 605 tim3p4_cnt_data = 0;
kenjiArai 1:102230f2879d 606 TIM3->SR &= ~TIM_SR_CC2IF; // clear IC flag
kenjiArai 1:102230f2879d 607 TIM4->SR &= ~TIM_SR_CC1IF;
kenjiArai 1:102230f2879d 608 TIM3->DIER |= TIM_DIER_CC2IE;
kenjiArai 1:102230f2879d 609 NVIC_SetVector(TIM3_IRQn, (uint32_t)irq_ic2_TIM3P4);
kenjiArai 1:102230f2879d 610 NVIC_ClearPendingIRQ(TIM3_IRQn);
kenjiArai 1:102230f2879d 611 NVIC_EnableIRQ(TIM3_IRQn);
kenjiArai 1:102230f2879d 612 }
kenjiArai 0:bfdc6ed58a06 613
kenjiArai 2:194f82ad3041 614 //---------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 615 // Only for Debug purpose
kenjiArai 2:194f82ad3041 616 //---------------------------------------------------------------------------------------
kenjiArai 2:194f82ad3041 617 void FRQ_CUNTR::debug_printf_internal_data(void)
kenjiArai 2:194f82ad3041 618 {
kenjiArai 3:339307e1dc0d 619 #if 1
kenjiArai 2:194f82ad3041 620 PRINTF("Debug information\r\n");
kenjiArai 2:194f82ad3041 621 PRINTF("gate_time %f\r\n", gate_time);
kenjiArai 2:194f82ad3041 622 PRINTF("ex_clock_freq %f\r\n", ex_clock_freq);
kenjiArai 2:194f82ad3041 623 PRINTF("ex_clk_base %9d\r\n", ex_clk_base);
kenjiArai 2:194f82ad3041 624 PRINTF("clk_hi_const %9d\r\n", clk_hi_const);
kenjiArai 2:194f82ad3041 625 PRINTF("clk_upper_limit %9d\r\n", clk_upper_limit);
kenjiArai 2:194f82ad3041 626 PRINTF("clk_lower_limit %9d\r\n", clk_lower_limit);
kenjiArai 2:194f82ad3041 627 PRINTF("\r\n");
kenjiArai 2:194f82ad3041 628 #endif
kenjiArai 2:194f82ad3041 629 }
kenjiArai 2:194f82ad3041 630
kenjiArai 0:bfdc6ed58a06 631 } // Frequency_counter