Frequency counter library using GPS 1PPS signal and temperature controlled 50MHz Base clock. Ported from F411 Frequency Counter.
Dependents: Frequency_Cntr_1PPS_F746ZG
Fork of Frq_cuntr_full by
Please refer following.
/users/kenjiArai/notebook/frequency-counters/
frq_cuntr_full.cpp@0:bfdc6ed58a06, 2014-11-22 (annotated)
- Committer:
- kenjiArai
- Date:
- Sat Nov 22 04:01:41 2014 +0000
- Revision:
- 0:bfdc6ed58a06
- Child:
- 1:102230f2879d
Frequency Counter program using GPS 1PPS signal compensation. Only for ST Nucleo F411RE.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kenjiArai | 0:bfdc6ed58a06 | 1 | /* |
kenjiArai | 0:bfdc6ed58a06 | 2 | * mbed Application program / Frequency Counter with GPS 1PPS Compensation |
kenjiArai | 0:bfdc6ed58a06 | 3 | * Frequency Counter Hardware relataed program |
kenjiArai | 0:bfdc6ed58a06 | 4 | * |
kenjiArai | 0:bfdc6ed58a06 | 5 | * Copyright (c) 2014 Kenji Arai / JH1PJL |
kenjiArai | 0:bfdc6ed58a06 | 6 | * http://www.page.sannet.ne.jp/kenjia/index.html |
kenjiArai | 0:bfdc6ed58a06 | 7 | * http://mbed.org/users/kenjiArai/ |
kenjiArai | 0:bfdc6ed58a06 | 8 | * Additional functions and modification |
kenjiArai | 0:bfdc6ed58a06 | 9 | * started: October 18th, 2014 |
kenjiArai | 0:bfdc6ed58a06 | 10 | * Revised: Nobember 22nd, 2014 |
kenjiArai | 0:bfdc6ed58a06 | 11 | * |
kenjiArai | 0:bfdc6ed58a06 | 12 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, |
kenjiArai | 0:bfdc6ed58a06 | 13 | * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
kenjiArai | 0:bfdc6ed58a06 | 14 | * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, |
kenjiArai | 0:bfdc6ed58a06 | 15 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
kenjiArai | 0:bfdc6ed58a06 | 16 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
kenjiArai | 0:bfdc6ed58a06 | 17 | */ |
kenjiArai | 0:bfdc6ed58a06 | 18 | |
kenjiArai | 0:bfdc6ed58a06 | 19 | #include "frq_cuntr_full.h" |
kenjiArai | 0:bfdc6ed58a06 | 20 | |
kenjiArai | 0:bfdc6ed58a06 | 21 | #ifdef DEBUG |
kenjiArai | 0:bfdc6ed58a06 | 22 | Serial pcm(USBTX, USBRX); |
kenjiArai | 0:bfdc6ed58a06 | 23 | DigitalOut debug_led(LED1); |
kenjiArai | 0:bfdc6ed58a06 | 24 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 25 | |
kenjiArai | 0:bfdc6ed58a06 | 26 | #ifdef DEBUG |
kenjiArai | 0:bfdc6ed58a06 | 27 | #define BAUD(x) pcm.baud(x) |
kenjiArai | 0:bfdc6ed58a06 | 28 | #define GETC(x) pcm.getc(x) |
kenjiArai | 0:bfdc6ed58a06 | 29 | #define PUTC(x) pcm.putc(x) |
kenjiArai | 0:bfdc6ed58a06 | 30 | #define PRINTF(...) pcm.printf(__VA_ARGS__) |
kenjiArai | 0:bfdc6ed58a06 | 31 | #define READABLE(x) pcm.readable(x) |
kenjiArai | 0:bfdc6ed58a06 | 32 | #else |
kenjiArai | 0:bfdc6ed58a06 | 33 | #define BAUD(x) {;} |
kenjiArai | 0:bfdc6ed58a06 | 34 | #define GETC(x) {;} |
kenjiArai | 0:bfdc6ed58a06 | 35 | #define PUTC(x) {;} |
kenjiArai | 0:bfdc6ed58a06 | 36 | #define PRINTF(...) {;} |
kenjiArai | 0:bfdc6ed58a06 | 37 | #define READABLE(x) {;} |
kenjiArai | 0:bfdc6ed58a06 | 38 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 39 | |
kenjiArai | 0:bfdc6ed58a06 | 40 | namespace Frequency_counter |
kenjiArai | 0:bfdc6ed58a06 | 41 | { |
kenjiArai | 0:bfdc6ed58a06 | 42 | #if defined(IRQ_DRIVE) |
kenjiArai | 0:bfdc6ed58a06 | 43 | // TIM2 |
kenjiArai | 0:bfdc6ed58a06 | 44 | uint8_t tim2_ready_flg; |
kenjiArai | 0:bfdc6ed58a06 | 45 | uint32_t tim2_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 46 | uint32_t tim2_old_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 47 | // TIM3+4 |
kenjiArai | 0:bfdc6ed58a06 | 48 | uint8_t tim3p4_ready_flg; |
kenjiArai | 0:bfdc6ed58a06 | 49 | uint32_t tim3p4_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 50 | uint32_t tim3p4_old_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 51 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 52 | |
kenjiArai | 0:bfdc6ed58a06 | 53 | //------------------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 54 | // Control Program |
kenjiArai | 0:bfdc6ed58a06 | 55 | //------------------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 56 | // TIM2 IC2 Interrupt control |
kenjiArai | 0:bfdc6ed58a06 | 57 | void irq_ic2_TIM2(void) |
kenjiArai | 0:bfdc6ed58a06 | 58 | { |
kenjiArai | 0:bfdc6ed58a06 | 59 | uint16_t reg; |
kenjiArai | 0:bfdc6ed58a06 | 60 | |
kenjiArai | 0:bfdc6ed58a06 | 61 | reg = TIM2->SR; |
kenjiArai | 0:bfdc6ed58a06 | 62 | if (reg & TIM_SR_CC2IF){ |
kenjiArai | 0:bfdc6ed58a06 | 63 | TIM2->SR &= ~TIM_SR_CC2IF; // clear IC flag |
kenjiArai | 0:bfdc6ed58a06 | 64 | tim2_old_cnt_data = tim2_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 65 | tim2_cnt_data = TIM2->CCR2; |
kenjiArai | 0:bfdc6ed58a06 | 66 | tim2_ready_flg = 1; |
kenjiArai | 0:bfdc6ed58a06 | 67 | } else if (reg & TIM_SR_CC3IF){ |
kenjiArai | 0:bfdc6ed58a06 | 68 | TIM2->SR &= ~TIM_SR_CC3IF; // clear IC flag |
kenjiArai | 0:bfdc6ed58a06 | 69 | TIM2->CCR3 = TIM2->CCR3 + ONE_SECOND_COUNT; |
kenjiArai | 0:bfdc6ed58a06 | 70 | } |
kenjiArai | 0:bfdc6ed58a06 | 71 | #if defined(DEBUG) |
kenjiArai | 0:bfdc6ed58a06 | 72 | debug_led = !debug_led; |
kenjiArai | 0:bfdc6ed58a06 | 73 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 74 | } |
kenjiArai | 0:bfdc6ed58a06 | 75 | |
kenjiArai | 0:bfdc6ed58a06 | 76 | // TIM3 IC2 Interrupt control (same signal connected to TIM4 IC1) |
kenjiArai | 0:bfdc6ed58a06 | 77 | void irq_ic2_TIM3P4(void) |
kenjiArai | 0:bfdc6ed58a06 | 78 | { |
kenjiArai | 0:bfdc6ed58a06 | 79 | TIM3->SR &= ~TIM_SR_CC2IF; // clear IC flag |
kenjiArai | 0:bfdc6ed58a06 | 80 | TIM4->SR &= ~TIM_SR_CC1IF; |
kenjiArai | 0:bfdc6ed58a06 | 81 | tim3p4_old_cnt_data = tim3p4_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 82 | tim3p4_cnt_data = (TIM4->CCR1 << 16) + TIM3->CCR2; |
kenjiArai | 0:bfdc6ed58a06 | 83 | tim3p4_ready_flg = 1; |
kenjiArai | 0:bfdc6ed58a06 | 84 | #if defined(DEBUG) |
kenjiArai | 0:bfdc6ed58a06 | 85 | debug_led = !debug_led; |
kenjiArai | 0:bfdc6ed58a06 | 86 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 87 | } |
kenjiArai | 0:bfdc6ed58a06 | 88 | |
kenjiArai | 0:bfdc6ed58a06 | 89 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 90 | // Frequency Counter |
kenjiArai | 0:bfdc6ed58a06 | 91 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 92 | FRQ_CUNTR::FRQ_CUNTR(PinName f_in): _pin(f_in) |
kenjiArai | 0:bfdc6ed58a06 | 93 | { |
kenjiArai | 0:bfdc6ed58a06 | 94 | ; |
kenjiArai | 0:bfdc6ed58a06 | 95 | } |
kenjiArai | 0:bfdc6ed58a06 | 96 | |
kenjiArai | 0:bfdc6ed58a06 | 97 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 98 | // TIM2 (32bit Counter + IC + OC) |
kenjiArai | 0:bfdc6ed58a06 | 99 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 100 | // Read TIM2 captured counter value |
kenjiArai | 0:bfdc6ed58a06 | 101 | uint32_t FRQ_CUNTR::read_ic2_counter_TIM2(void) |
kenjiArai | 0:bfdc6ed58a06 | 102 | { |
kenjiArai | 0:bfdc6ed58a06 | 103 | #if !defined(IRQ_DRIVE) |
kenjiArai | 0:bfdc6ed58a06 | 104 | uint32_t count = 0 |
kenjiArai | 0:bfdc6ed58a06 | 105 | |
kenjiArai | 0:bfdc6ed58a06 | 106 | count = TIM2->CCR2; |
kenjiArai | 0:bfdc6ed58a06 | 107 | TIM2->SR &= ~TIM_SR_CC2IF; // clear IC flag |
kenjiArai | 0:bfdc6ed58a06 | 108 | PRINTF("T2:0x%08x\r\n", count); |
kenjiArai | 0:bfdc6ed58a06 | 109 | return count; |
kenjiArai | 0:bfdc6ed58a06 | 110 | #else |
kenjiArai | 0:bfdc6ed58a06 | 111 | // return TIM2->CCR2; |
kenjiArai | 0:bfdc6ed58a06 | 112 | return tim2_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 113 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 114 | } |
kenjiArai | 0:bfdc6ed58a06 | 115 | |
kenjiArai | 0:bfdc6ed58a06 | 116 | // Check TIM2 IC2 status |
kenjiArai | 0:bfdc6ed58a06 | 117 | uint32_t FRQ_CUNTR::check_ic2_status_TIM2(void) |
kenjiArai | 0:bfdc6ed58a06 | 118 | { |
kenjiArai | 0:bfdc6ed58a06 | 119 | #if !defined(IRQ_DRIVE) |
kenjiArai | 0:bfdc6ed58a06 | 120 | uint32_t status = 0; |
kenjiArai | 0:bfdc6ed58a06 | 121 | |
kenjiArai | 0:bfdc6ed58a06 | 122 | status = (TIM2->SR & TIM_SR_CC2IF) >> 2; |
kenjiArai | 0:bfdc6ed58a06 | 123 | PRINTF("Status:0x%08x,", status); |
kenjiArai | 0:bfdc6ed58a06 | 124 | return status; |
kenjiArai | 0:bfdc6ed58a06 | 125 | #else |
kenjiArai | 0:bfdc6ed58a06 | 126 | if (tim2_ready_flg == 0) { |
kenjiArai | 0:bfdc6ed58a06 | 127 | return 0; |
kenjiArai | 0:bfdc6ed58a06 | 128 | } else { |
kenjiArai | 0:bfdc6ed58a06 | 129 | tim2_ready_flg = 0; |
kenjiArai | 0:bfdc6ed58a06 | 130 | avarage_1pps(); |
kenjiArai | 0:bfdc6ed58a06 | 131 | return 0xff; |
kenjiArai | 0:bfdc6ed58a06 | 132 | } |
kenjiArai | 0:bfdc6ed58a06 | 133 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 134 | } |
kenjiArai | 0:bfdc6ed58a06 | 135 | |
kenjiArai | 0:bfdc6ed58a06 | 136 | // Avarage measued data GPS 1PPS by 50MHz Internal Clock |
kenjiArai | 0:bfdc6ed58a06 | 137 | void FRQ_CUNTR::avarage_1pps(void) |
kenjiArai | 0:bfdc6ed58a06 | 138 | { |
kenjiArai | 0:bfdc6ed58a06 | 139 | uint8_t status = 0; |
kenjiArai | 0:bfdc6ed58a06 | 140 | |
kenjiArai | 0:bfdc6ed58a06 | 141 | uint32_t diff = tim2_cnt_data - tim2_old_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 142 | onepps_cnt[onepps_num] = diff; |
kenjiArai | 0:bfdc6ed58a06 | 143 | if ((onepps_cnt[onepps_num] > CNT_UPPER) || (onepps_cnt[onepps_num] < CNT_LOWER)) { |
kenjiArai | 0:bfdc6ed58a06 | 144 | ; |
kenjiArai | 0:bfdc6ed58a06 | 145 | } else { |
kenjiArai | 0:bfdc6ed58a06 | 146 | status = 0; |
kenjiArai | 0:bfdc6ed58a06 | 147 | if (++onepps_num >= CNT_BF_SIZE) { |
kenjiArai | 0:bfdc6ed58a06 | 148 | onepps_num = 0; |
kenjiArai | 0:bfdc6ed58a06 | 149 | onepps_buf_full = 1; |
kenjiArai | 0:bfdc6ed58a06 | 150 | } |
kenjiArai | 0:bfdc6ed58a06 | 151 | } |
kenjiArai | 0:bfdc6ed58a06 | 152 | uint64_t total = 0; |
kenjiArai | 0:bfdc6ed58a06 | 153 | if (onepps_buf_full == 1) { |
kenjiArai | 0:bfdc6ed58a06 | 154 | for (uint32_t i = 0; i < CNT_BF_SIZE; i++) { |
kenjiArai | 0:bfdc6ed58a06 | 155 | total += (uint64_t)onepps_cnt[i]; |
kenjiArai | 0:bfdc6ed58a06 | 156 | } |
kenjiArai | 0:bfdc6ed58a06 | 157 | onepps_cnt_avarage = total / CNT_BF_SIZE; |
kenjiArai | 0:bfdc6ed58a06 | 158 | status = 2; |
kenjiArai | 0:bfdc6ed58a06 | 159 | } else { |
kenjiArai | 0:bfdc6ed58a06 | 160 | for (uint32_t i = 0; i < onepps_num; i++) { |
kenjiArai | 0:bfdc6ed58a06 | 161 | total += (uint64_t)onepps_cnt[i]; |
kenjiArai | 0:bfdc6ed58a06 | 162 | } |
kenjiArai | 0:bfdc6ed58a06 | 163 | onepps_cnt_avarage = total / onepps_num; |
kenjiArai | 0:bfdc6ed58a06 | 164 | status = 1; |
kenjiArai | 0:bfdc6ed58a06 | 165 | } |
kenjiArai | 0:bfdc6ed58a06 | 166 | // PRINTF("num= %3d , status= %1d , 1PPS= %9d , 1PPS/Ave= %9d , ", onepps_num, status, diff, onepps_cnt_avarage); |
kenjiArai | 0:bfdc6ed58a06 | 167 | PRINTF("num= %3d , status= %1d , 1PPS= %9d , 1PPS/Ave= %9d , ", onepps_num, status, diff, 0); |
kenjiArai | 0:bfdc6ed58a06 | 168 | } |
kenjiArai | 0:bfdc6ed58a06 | 169 | |
kenjiArai | 0:bfdc6ed58a06 | 170 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 171 | // TIM3+TIM4 (32bit Counter + IC) |
kenjiArai | 0:bfdc6ed58a06 | 172 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 173 | // Read TIM3+4(as 32bit) captured counter value |
kenjiArai | 0:bfdc6ed58a06 | 174 | uint32_t FRQ_CUNTR::read_ic2_counter_TIM3P4(void) |
kenjiArai | 0:bfdc6ed58a06 | 175 | { |
kenjiArai | 0:bfdc6ed58a06 | 176 | #if !defined(IRQ_DRIVE) |
kenjiArai | 0:bfdc6ed58a06 | 177 | uint32_t count0 = 0, count1 = 0; |
kenjiArai | 0:bfdc6ed58a06 | 178 | |
kenjiArai | 0:bfdc6ed58a06 | 179 | count0 = TIM3->CCR2; |
kenjiArai | 0:bfdc6ed58a06 | 180 | count1 = TIM4->CCR1; |
kenjiArai | 0:bfdc6ed58a06 | 181 | TIM3->SR &= ~TIM_SR_CC2IF; // clear IC flag |
kenjiArai | 0:bfdc6ed58a06 | 182 | TIM4->SR &= ~TIM_SR_CC1IF; |
kenjiArai | 0:bfdc6ed58a06 | 183 | PRINTF("T4:0x%08x,T3:0x%08x\r\n", count1, count0); |
kenjiArai | 0:bfdc6ed58a06 | 184 | count0 = (count1 << 16) + count0; |
kenjiArai | 0:bfdc6ed58a06 | 185 | return count0; |
kenjiArai | 0:bfdc6ed58a06 | 186 | #else |
kenjiArai | 0:bfdc6ed58a06 | 187 | return tim3p4_cnt_data; |
kenjiArai | 0:bfdc6ed58a06 | 188 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 189 | } |
kenjiArai | 0:bfdc6ed58a06 | 190 | |
kenjiArai | 0:bfdc6ed58a06 | 191 | // Check TIM3 IC2 & TIM4 IC1 status |
kenjiArai | 0:bfdc6ed58a06 | 192 | uint32_t FRQ_CUNTR::check_ic2_status_TIM3P4(void) |
kenjiArai | 0:bfdc6ed58a06 | 193 | { |
kenjiArai | 0:bfdc6ed58a06 | 194 | #if !defined(IRQ_DRIVE) |
kenjiArai | 0:bfdc6ed58a06 | 195 | uint32_t status0 = 0, status1 = 0; |
kenjiArai | 0:bfdc6ed58a06 | 196 | |
kenjiArai | 0:bfdc6ed58a06 | 197 | status0 = (TIM3->SR & TIM_SR_CC2IF) >> 2; |
kenjiArai | 0:bfdc6ed58a06 | 198 | status1 = (TIM4->SR & TIM_SR_CC1IF) >> 1; |
kenjiArai | 0:bfdc6ed58a06 | 199 | status0 = (status1 << 16) + status0; |
kenjiArai | 0:bfdc6ed58a06 | 200 | PRINTF("Status:0x%08x,", status0); |
kenjiArai | 0:bfdc6ed58a06 | 201 | return status0; |
kenjiArai | 0:bfdc6ed58a06 | 202 | #else |
kenjiArai | 0:bfdc6ed58a06 | 203 | if (tim3p4_ready_flg == 0) { |
kenjiArai | 0:bfdc6ed58a06 | 204 | return 0; |
kenjiArai | 0:bfdc6ed58a06 | 205 | } else { |
kenjiArai | 0:bfdc6ed58a06 | 206 | tim3p4_ready_flg = 0; |
kenjiArai | 0:bfdc6ed58a06 | 207 | return 0xff; |
kenjiArai | 0:bfdc6ed58a06 | 208 | } |
kenjiArai | 0:bfdc6ed58a06 | 209 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 210 | } |
kenjiArai | 0:bfdc6ed58a06 | 211 | |
kenjiArai | 0:bfdc6ed58a06 | 212 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 213 | // Frequency check for test purpose |
kenjiArai | 0:bfdc6ed58a06 | 214 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 215 | // Read TIM2 Clock frequency |
kenjiArai | 0:bfdc6ed58a06 | 216 | uint32_t FRQ_CUNTR::read_frequency_TIM2(float gate_time) |
kenjiArai | 0:bfdc6ed58a06 | 217 | { |
kenjiArai | 0:bfdc6ed58a06 | 218 | uint32_t freq = 0; |
kenjiArai | 0:bfdc6ed58a06 | 219 | |
kenjiArai | 0:bfdc6ed58a06 | 220 | TIM2->CNT = 0; |
kenjiArai | 0:bfdc6ed58a06 | 221 | wait(gate_time); // Gate time for count |
kenjiArai | 0:bfdc6ed58a06 | 222 | freq = TIM2->CNT; // read counter |
kenjiArai | 0:bfdc6ed58a06 | 223 | PRINTF("Clock freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq, gate_time); |
kenjiArai | 0:bfdc6ed58a06 | 224 | return freq; // return counter data |
kenjiArai | 0:bfdc6ed58a06 | 225 | } |
kenjiArai | 0:bfdc6ed58a06 | 226 | |
kenjiArai | 0:bfdc6ed58a06 | 227 | // Read TIM3(+TIM4) Input frequency |
kenjiArai | 0:bfdc6ed58a06 | 228 | uint32_t FRQ_CUNTR::read_frequency_TIM3P4(float gate_time) |
kenjiArai | 0:bfdc6ed58a06 | 229 | { |
kenjiArai | 0:bfdc6ed58a06 | 230 | uint32_t freq0 = 0, freq1 = 0; |
kenjiArai | 0:bfdc6ed58a06 | 231 | |
kenjiArai | 0:bfdc6ed58a06 | 232 | TIM3->CNT = 0; |
kenjiArai | 0:bfdc6ed58a06 | 233 | TIM4->CNT = 0; |
kenjiArai | 0:bfdc6ed58a06 | 234 | TIM3->CNT = 0; |
kenjiArai | 0:bfdc6ed58a06 | 235 | wait(gate_time); // Gate time for count |
kenjiArai | 0:bfdc6ed58a06 | 236 | freq0 = TIM3->CNT; |
kenjiArai | 0:bfdc6ed58a06 | 237 | freq1 = TIM4->CNT; |
kenjiArai | 0:bfdc6ed58a06 | 238 | freq0 = (freq1 << 16) + freq0; |
kenjiArai | 0:bfdc6ed58a06 | 239 | PRINTF("Input freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq0, gate_time); |
kenjiArai | 0:bfdc6ed58a06 | 240 | return freq0; // read counter |
kenjiArai | 0:bfdc6ed58a06 | 241 | } |
kenjiArai | 0:bfdc6ed58a06 | 242 | |
kenjiArai | 0:bfdc6ed58a06 | 243 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 244 | // Clock output for test purpose |
kenjiArai | 0:bfdc6ed58a06 | 245 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 246 | // Output internal clock |
kenjiArai | 0:bfdc6ed58a06 | 247 | void FRQ_CUNTR::port_mco1_mco2_set(uint8_t select) |
kenjiArai | 0:bfdc6ed58a06 | 248 | { |
kenjiArai | 0:bfdc6ed58a06 | 249 | // PA8 -> MCO_1 |
kenjiArai | 0:bfdc6ed58a06 | 250 | GPIOA->AFR[1] &= 0xfffffff0; |
kenjiArai | 0:bfdc6ed58a06 | 251 | GPIOA->AFR[1] |= GPIO_AF0_MCO << 0; |
kenjiArai | 0:bfdc6ed58a06 | 252 | GPIOA->MODER &= ~(GPIO_MODER_MODER8); // AF |
kenjiArai | 0:bfdc6ed58a06 | 253 | GPIOA->MODER |= GPIO_MODER_MODER8_1; |
kenjiArai | 0:bfdc6ed58a06 | 254 | GPIOA->OTYPER &= ~(GPIO_OTYPER_OT_8); // Output Push-Pull=0 |
kenjiArai | 0:bfdc6ed58a06 | 255 | GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8;// Speed full=11 |
kenjiArai | 0:bfdc6ed58a06 | 256 | GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR8); // Pull-up=01 |
kenjiArai | 0:bfdc6ed58a06 | 257 | GPIOA->PUPDR |= GPIO_PUPDR_PUPDR8_0; |
kenjiArai | 0:bfdc6ed58a06 | 258 | // PC9 -> MCO_2 |
kenjiArai | 0:bfdc6ed58a06 | 259 | GPIOC->AFR[1] &= 0xffffff0f; |
kenjiArai | 0:bfdc6ed58a06 | 260 | GPIOC->AFR[1] |= GPIO_AF0_MCO << 4; |
kenjiArai | 0:bfdc6ed58a06 | 261 | GPIOC->MODER &= ~(GPIO_MODER_MODER9); // AF |
kenjiArai | 0:bfdc6ed58a06 | 262 | GPIOC->MODER |= GPIO_MODER_MODER9_1; |
kenjiArai | 0:bfdc6ed58a06 | 263 | GPIOC->OTYPER &= ~(GPIO_OTYPER_OT_9); // Output Push-Pull=0 |
kenjiArai | 0:bfdc6ed58a06 | 264 | GPIOC->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9;// Speed full=11 |
kenjiArai | 0:bfdc6ed58a06 | 265 | GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR9); // Pull-up=01 |
kenjiArai | 0:bfdc6ed58a06 | 266 | GPIOC->PUPDR |= GPIO_PUPDR_PUPDR9_0; |
kenjiArai | 0:bfdc6ed58a06 | 267 | // Select output clock source |
kenjiArai | 0:bfdc6ed58a06 | 268 | RCC->CFGR &= 0x009fffff; |
kenjiArai | 0:bfdc6ed58a06 | 269 | if (select == 1){ |
kenjiArai | 0:bfdc6ed58a06 | 270 | // MC01 output HSE 1/1, MCO2 output SYSCLK 1/1 |
kenjiArai | 0:bfdc6ed58a06 | 271 | // MCO2 MCO2PRE MCO1PRE MCO1 |
kenjiArai | 0:bfdc6ed58a06 | 272 | RCC->CFGR |= (0x0 << 30) + (0x0 << 27) + (0x0 << 24) + (0x2 << 21); |
kenjiArai | 0:bfdc6ed58a06 | 273 | PRINTF("Set MCO1(PA8):HSE/1, MCO2(PC9):SYSCLK/1\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 274 | } else if (select == 2){ |
kenjiArai | 0:bfdc6ed58a06 | 275 | // MC01 output HSE 1/2, MCO2 output SYSCLK 1/2 |
kenjiArai | 0:bfdc6ed58a06 | 276 | // MCO2 MCO2PRE MCO1PRE MCO1 |
kenjiArai | 0:bfdc6ed58a06 | 277 | RCC->CFGR |= (0x0 << 30) + (0x4 << 27) + (0x4 << 24) + (0x2 << 21); |
kenjiArai | 0:bfdc6ed58a06 | 278 | PRINTF("Set MCO1(PA8):HSE/2, MCO2(PC9):SYSCLK/2\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 279 | } else { // select = 4 and other wrong order |
kenjiArai | 0:bfdc6ed58a06 | 280 | // MC01 output HSE 1/4, MCO2 output SYSCLK 1/4 |
kenjiArai | 0:bfdc6ed58a06 | 281 | // MCO2 MCO2PRE MCO1PRE MCO1 |
kenjiArai | 0:bfdc6ed58a06 | 282 | RCC->CFGR |= (0x0 << 30) + (0x6 << 27) + (0x6 << 24) + (0x2 << 21); |
kenjiArai | 0:bfdc6ed58a06 | 283 | PRINTF("Set MCO1(PA8):HSE/4, MCO2(PC9):SYSCLK/4\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 284 | } |
kenjiArai | 0:bfdc6ed58a06 | 285 | } |
kenjiArai | 0:bfdc6ed58a06 | 286 | |
kenjiArai | 0:bfdc6ed58a06 | 287 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 288 | // Initialize TIM2 and TIM3+4 |
kenjiArai | 0:bfdc6ed58a06 | 289 | //--------------------------------------------------------------------------------------- |
kenjiArai | 0:bfdc6ed58a06 | 290 | void FRQ_CUNTR::initialize_Freq_counter(void) |
kenjiArai | 0:bfdc6ed58a06 | 291 | { |
kenjiArai | 0:bfdc6ed58a06 | 292 | initialize_TIM2(); |
kenjiArai | 0:bfdc6ed58a06 | 293 | initialize_TIM3P4(); |
kenjiArai | 0:bfdc6ed58a06 | 294 | } |
kenjiArai | 0:bfdc6ed58a06 | 295 | |
kenjiArai | 0:bfdc6ed58a06 | 296 | // Initialize TIM2 |
kenjiArai | 0:bfdc6ed58a06 | 297 | // Internal clock (50MHz) and IC2 for GPS 1pps signal measurement |
kenjiArai | 0:bfdc6ed58a06 | 298 | void FRQ_CUNTR::initialize_TIM2(void) |
kenjiArai | 0:bfdc6ed58a06 | 299 | { |
kenjiArai | 0:bfdc6ed58a06 | 300 | #if defined(BASE_EXTERNAL_CLOCK) |
kenjiArai | 0:bfdc6ed58a06 | 301 | // PA0 -> Counter frequency input pin as Timer2 CH1/TI1 |
kenjiArai | 0:bfdc6ed58a06 | 302 | RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN); |
kenjiArai | 0:bfdc6ed58a06 | 303 | GPIOA->AFR[0] &= 0xfffffff0; |
kenjiArai | 0:bfdc6ed58a06 | 304 | GPIOA->AFR[0] |= GPIO_AF1_TIM2; |
kenjiArai | 0:bfdc6ed58a06 | 305 | GPIOA->MODER &= ~(GPIO_MODER_MODER0); // AF |
kenjiArai | 0:bfdc6ed58a06 | 306 | GPIOA->MODER |= GPIO_MODER_MODER0_1; |
kenjiArai | 0:bfdc6ed58a06 | 307 | GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR0); // PU |
kenjiArai | 0:bfdc6ed58a06 | 308 | GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_0; |
kenjiArai | 0:bfdc6ed58a06 | 309 | // Initialize Timer2(32bit) for an external up counter mode |
kenjiArai | 0:bfdc6ed58a06 | 310 | RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; |
kenjiArai | 0:bfdc6ed58a06 | 311 | TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD)); // count_up + div by 1 |
kenjiArai | 0:bfdc6ed58a06 | 312 | TIM2->CR1 |= TIM_CR1_URS; |
kenjiArai | 0:bfdc6ed58a06 | 313 | TIM2->ARR = 0xffffffff; |
kenjiArai | 0:bfdc6ed58a06 | 314 | TIM2->PSC = 0x0000; |
kenjiArai | 0:bfdc6ed58a06 | 315 | TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1 |
kenjiArai | 0:bfdc6ed58a06 | 316 | TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S); // input filter + input select |
kenjiArai | 0:bfdc6ed58a06 | 317 | TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0; |
kenjiArai | 0:bfdc6ed58a06 | 318 | TIM2->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP); // positive edge |
kenjiArai | 0:bfdc6ed58a06 | 319 | TIM2->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS); // external mode 1 |
kenjiArai | 0:bfdc6ed58a06 | 320 | TIM2->SMCR |= (uint16_t)( TIM_TS_TI1FP1 | TIM_SLAVEMODE_EXTERNAL1); // ECE must be ZERO!!!! |
kenjiArai | 0:bfdc6ed58a06 | 321 | TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter |
kenjiArai | 0:bfdc6ed58a06 | 322 | #else |
kenjiArai | 0:bfdc6ed58a06 | 323 | // Initialize Timer2(32bit) for an external up counter mode |
kenjiArai | 0:bfdc6ed58a06 | 324 | RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; |
kenjiArai | 0:bfdc6ed58a06 | 325 | TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD)); // count_up + div by 1 |
kenjiArai | 0:bfdc6ed58a06 | 326 | TIM2->CR1 |= TIM_CR1_URS; |
kenjiArai | 0:bfdc6ed58a06 | 327 | TIM2->ARR = 0xffffffff; |
kenjiArai | 0:bfdc6ed58a06 | 328 | TIM2->PSC = 0x0000; |
kenjiArai | 0:bfdc6ed58a06 | 329 | TIM2->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1 |
kenjiArai | 0:bfdc6ed58a06 | 330 | TIM2->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS); |
kenjiArai | 0:bfdc6ed58a06 | 331 | TIM2->SMCR |= (uint16_t)0; // Internal clock = 100MHz |
kenjiArai | 0:bfdc6ed58a06 | 332 | TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter |
kenjiArai | 0:bfdc6ed58a06 | 333 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 334 | // PA1 -> Input Capture pin as Timer2 IC2 |
kenjiArai | 0:bfdc6ed58a06 | 335 | GPIOA->AFR[0] &= 0xffffff0f; |
kenjiArai | 0:bfdc6ed58a06 | 336 | GPIOA->AFR[0] |= GPIO_AF1_TIM2 << 4; |
kenjiArai | 0:bfdc6ed58a06 | 337 | GPIOA->MODER &= ~(GPIO_MODER_MODER1); // AF |
kenjiArai | 0:bfdc6ed58a06 | 338 | GPIOA->MODER |= GPIO_MODER_MODER1_1; |
kenjiArai | 0:bfdc6ed58a06 | 339 | GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR1); |
kenjiArai | 0:bfdc6ed58a06 | 340 | GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_0; // PU |
kenjiArai | 0:bfdc6ed58a06 | 341 | // Initialize Timer2 I.C.2 |
kenjiArai | 0:bfdc6ed58a06 | 342 | TIM2->CCER &= (uint16_t)~TIM_CCER_CC2E; // Disable the CC2 |
kenjiArai | 0:bfdc6ed58a06 | 343 | TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select |
kenjiArai | 0:bfdc6ed58a06 | 344 | TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0; |
kenjiArai | 0:bfdc6ed58a06 | 345 | TIM2->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge |
kenjiArai | 0:bfdc6ed58a06 | 346 | TIM2->CCER |= (uint16_t)TIM_CCER_CC2E; // enable capture |
kenjiArai | 0:bfdc6ed58a06 | 347 | // PB10 -> Output Compare pin as Timer2 CH3/OC3 |
kenjiArai | 0:bfdc6ed58a06 | 348 | GPIOB->AFR[1] &= 0xfffff0ff; |
kenjiArai | 0:bfdc6ed58a06 | 349 | GPIOB->AFR[1] |= GPIO_AF1_TIM2 << 8; |
kenjiArai | 0:bfdc6ed58a06 | 350 | GPIOB->MODER &= ~(GPIO_MODER_MODER10); // AF |
kenjiArai | 0:bfdc6ed58a06 | 351 | GPIOB->MODER |= GPIO_MODER_MODER10_1; |
kenjiArai | 0:bfdc6ed58a06 | 352 | GPIOB->OTYPER &= ~(GPIO_OTYPER_OT_10);// Output Push-Pull=0 |
kenjiArai | 0:bfdc6ed58a06 | 353 | GPIOB->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10;// Speed full=11 |
kenjiArai | 0:bfdc6ed58a06 | 354 | GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR10); // Pull-up=01 |
kenjiArai | 0:bfdc6ed58a06 | 355 | GPIOB->PUPDR |= GPIO_PUPDR_PUPDR10_0; |
kenjiArai | 0:bfdc6ed58a06 | 356 | // Initialize Timer2 O.C.3 |
kenjiArai | 0:bfdc6ed58a06 | 357 | TIM2->CCER &= (uint16_t)~TIM_CCER_CC3E; // Reset the CC3E Bit |
kenjiArai | 0:bfdc6ed58a06 | 358 | TIM2->CCMR2 &= (uint16_t)~(TIM_CCMR2_OC3M | TIM_CCMR2_CC3S | |
kenjiArai | 0:bfdc6ed58a06 | 359 | TIM_CCMR2_OC3PE | TIM_CCMR2_OC3CE | TIM_CCMR2_OC3FE); |
kenjiArai | 0:bfdc6ed58a06 | 360 | TIM2->CCMR2 |= (TIM_CCMR2_OC3M_0 | TIM_CCMR2_OC3M_1); |
kenjiArai | 0:bfdc6ed58a06 | 361 | TIM2->CCER &= (uint16_t)~TIM_CCER_CC3P;// Reset the Output Polarity level |
kenjiArai | 0:bfdc6ed58a06 | 362 | TIM2->CCER |= (uint16_t)TIM_CCER_CC3E; // Set the CC3E Bit |
kenjiArai | 0:bfdc6ed58a06 | 363 | TIM2->CCR3 = TIM2->CNT + ONE_SECOND_COUNT;// Set the Capture Compare Register value |
kenjiArai | 0:bfdc6ed58a06 | 364 | // Only for Debug purpose |
kenjiArai | 0:bfdc6ed58a06 | 365 | BAUD(9600); |
kenjiArai | 0:bfdc6ed58a06 | 366 | // PA |
kenjiArai | 0:bfdc6ed58a06 | 367 | PRINTF("// Timer2(32bit) for an internal up counter mode\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 368 | PRINTF("// PA1 -> Input Capture pin as Timer2 CH2/TI2\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 369 | PRINTF("GPIOA->AFR[0]0x%08x:0x%08x\r\n",&GPIOA->AFR[0], GPIOA->AFR[0]); |
kenjiArai | 0:bfdc6ed58a06 | 370 | PRINTF("GPIOA->AFR[1]0x%08x:0x%08x\r\n",&GPIOA->AFR[1], GPIOA->AFR[1]); |
kenjiArai | 0:bfdc6ed58a06 | 371 | PRINTF("GPIOA->MODER 0x%08x:0x%08x\r\n",&GPIOA->MODER, GPIOA->MODER); |
kenjiArai | 0:bfdc6ed58a06 | 372 | PRINTF("GPIOA->PUPDR 0x%08x:0x%08x\r\n",&GPIOA->PUPDR, GPIOA->PUPDR); |
kenjiArai | 0:bfdc6ed58a06 | 373 | // PB |
kenjiArai | 0:bfdc6ed58a06 | 374 | PRINTF("// PB10 -> Output Compare pin as Timer2 CH3/TI3\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 375 | PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]); |
kenjiArai | 0:bfdc6ed58a06 | 376 | PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]); |
kenjiArai | 0:bfdc6ed58a06 | 377 | PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER); |
kenjiArai | 0:bfdc6ed58a06 | 378 | PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR); |
kenjiArai | 0:bfdc6ed58a06 | 379 | // TIM2 |
kenjiArai | 0:bfdc6ed58a06 | 380 | PRINTF("// PA1 -> Timer2 IC2\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 381 | PRINTF("// PB10-> Timer2 OC3\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 382 | PRINTF("TIM2->CR1 0x%08x:0x%08x\r\n",&TIM2->CR1, TIM2->CR1); |
kenjiArai | 0:bfdc6ed58a06 | 383 | PRINTF("TIM2->ARR 0x%08x:0x%08x\r\n",&TIM2->ARR, TIM2->ARR); |
kenjiArai | 0:bfdc6ed58a06 | 384 | PRINTF("TIM2->PSC 0x%08x:0x%08x\r\n",&TIM2->PSC, TIM2->PSC); |
kenjiArai | 0:bfdc6ed58a06 | 385 | PRINTF("TIM2->CCMR1 0x%08x:0x%08x\r\n",&TIM2->CCMR1, TIM2->CCMR1); |
kenjiArai | 0:bfdc6ed58a06 | 386 | PRINTF("TIM2->CCMR2 0x%08x:0x%08x\r\n",&TIM2->CCMR2, TIM2->CCMR2); |
kenjiArai | 0:bfdc6ed58a06 | 387 | PRINTF("TIM2->CCER 0x%08x:0x%08x\r\n",&TIM2->CCER, TIM2->CCER); |
kenjiArai | 0:bfdc6ed58a06 | 388 | PRINTF("TIM2->SMCR 0x%08x:0x%08x\r\n",&TIM2->SMCR, TIM2->SMCR); |
kenjiArai | 0:bfdc6ed58a06 | 389 | PRINTF("TIM2->CCR3 0x%08x:0x%08x\r\n\r\n",&TIM2->CCR3, TIM2->CCR3); |
kenjiArai | 0:bfdc6ed58a06 | 390 | #if defined(IRQ_DRIVE) |
kenjiArai | 0:bfdc6ed58a06 | 391 | // Interrupt Timer2 IC2 |
kenjiArai | 0:bfdc6ed58a06 | 392 | for (uint32_t i = 0; i < CNT_BF_SIZE; i++) { |
kenjiArai | 0:bfdc6ed58a06 | 393 | onepps_cnt[i] = 0; |
kenjiArai | 0:bfdc6ed58a06 | 394 | } |
kenjiArai | 0:bfdc6ed58a06 | 395 | onepps_num = 0; |
kenjiArai | 0:bfdc6ed58a06 | 396 | onepps_ready_flg = 0; |
kenjiArai | 0:bfdc6ed58a06 | 397 | onepps_buf_full = 0; |
kenjiArai | 0:bfdc6ed58a06 | 398 | onepps_cnt_avarage = 0; |
kenjiArai | 0:bfdc6ed58a06 | 399 | tim2_ready_flg = 0; |
kenjiArai | 0:bfdc6ed58a06 | 400 | tim2_cnt_data = 0; |
kenjiArai | 0:bfdc6ed58a06 | 401 | tim2_old_cnt_data = 0; |
kenjiArai | 0:bfdc6ed58a06 | 402 | TIM2->SR &= ~(TIM_SR_CC2IF + TIM_SR_CC3IF); // clear IC flag |
kenjiArai | 0:bfdc6ed58a06 | 403 | TIM2->DIER |= TIM_DIER_CC2IE + TIM_DIER_CC3IE; |
kenjiArai | 0:bfdc6ed58a06 | 404 | // void (FRQ_CUNTER::*Func)() = &FRQ_CUNTER::irq_ic2_TIM2; |
kenjiArai | 0:bfdc6ed58a06 | 405 | NVIC_SetVector(TIM2_IRQn, (uint32_t)irq_ic2_TIM2); |
kenjiArai | 0:bfdc6ed58a06 | 406 | // NVIC_SetVector(TIM2_IRQn, (uint32_t)Func); |
kenjiArai | 0:bfdc6ed58a06 | 407 | NVIC_ClearPendingIRQ(TIM2_IRQn); |
kenjiArai | 0:bfdc6ed58a06 | 408 | NVIC_EnableIRQ(TIM2_IRQn); |
kenjiArai | 0:bfdc6ed58a06 | 409 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 410 | } |
kenjiArai | 0:bfdc6ed58a06 | 411 | |
kenjiArai | 0:bfdc6ed58a06 | 412 | // Initialize TIM3 and TIM4 as 32bit counter (TIM3(16bit) + TIM4(16bit)) |
kenjiArai | 0:bfdc6ed58a06 | 413 | // TIM3 clock input is unkown freq.(measuring freq.) and TIM4 is slave counter |
kenjiArai | 0:bfdc6ed58a06 | 414 | // 1sec gate signal connected both TIM3 IC2 and TIM4 IC1 |
kenjiArai | 0:bfdc6ed58a06 | 415 | void FRQ_CUNTR::initialize_TIM3P4(void) |
kenjiArai | 0:bfdc6ed58a06 | 416 | { |
kenjiArai | 0:bfdc6ed58a06 | 417 | // PC6 -> Unkown frequency input pin as Timer3 CH1/TI1 |
kenjiArai | 0:bfdc6ed58a06 | 418 | RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN); |
kenjiArai | 0:bfdc6ed58a06 | 419 | GPIOC->AFR[0] &= 0xf0ffffff; |
kenjiArai | 0:bfdc6ed58a06 | 420 | GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 24; |
kenjiArai | 0:bfdc6ed58a06 | 421 | GPIOC->MODER &= ~(GPIO_MODER_MODER6); // AF |
kenjiArai | 0:bfdc6ed58a06 | 422 | GPIOC->MODER |= GPIO_MODER_MODER6_1; |
kenjiArai | 0:bfdc6ed58a06 | 423 | GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR6); |
kenjiArai | 0:bfdc6ed58a06 | 424 | GPIOC->PUPDR |= GPIO_PUPDR_PUPDR6_0; // PU |
kenjiArai | 0:bfdc6ed58a06 | 425 | // Initialize Timer3(16bit) for an external up counter mode |
kenjiArai | 0:bfdc6ed58a06 | 426 | RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; |
kenjiArai | 0:bfdc6ed58a06 | 427 | TIM3->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1 |
kenjiArai | 0:bfdc6ed58a06 | 428 | TIM3->CR1 |= (uint16_t)TIM_CR1_URS; |
kenjiArai | 0:bfdc6ed58a06 | 429 | TIM3->ARR = 0xffff; |
kenjiArai | 0:bfdc6ed58a06 | 430 | TIM3->CCER &= (uint16_t)~TIM_CCER_CC1E; // Disable the CC1 |
kenjiArai | 0:bfdc6ed58a06 | 431 | TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S); // input filter + input select |
kenjiArai | 0:bfdc6ed58a06 | 432 | TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0; |
kenjiArai | 0:bfdc6ed58a06 | 433 | TIM3->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP);// positive edge |
kenjiArai | 0:bfdc6ed58a06 | 434 | TIM3->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1 |
kenjiArai | 0:bfdc6ed58a06 | 435 | TIM3->SMCR |= (uint16_t)( TIM_TS_TI1FP1 | TIM_SLAVEMODE_EXTERNAL1); // ECE must be ZERO!!!! |
kenjiArai | 0:bfdc6ed58a06 | 436 | TIM3->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS); |
kenjiArai | 0:bfdc6ed58a06 | 437 | TIM3->CR2 |= (uint16_t)TIM_CR2_MMS_1; // TRGO update |
kenjiArai | 0:bfdc6ed58a06 | 438 | TIM3->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter |
kenjiArai | 0:bfdc6ed58a06 | 439 | // Initialize Timer4(16bit) for an slave up counter of TIM3 |
kenjiArai | 0:bfdc6ed58a06 | 440 | RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; |
kenjiArai | 0:bfdc6ed58a06 | 441 | TIM4->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));// count_up + div by 1 |
kenjiArai | 0:bfdc6ed58a06 | 442 | TIM4->CR1 |= (uint16_t)TIM_CR1_URS; |
kenjiArai | 0:bfdc6ed58a06 | 443 | TIM4->ARR = 0xffff; |
kenjiArai | 0:bfdc6ed58a06 | 444 | TIM4->CCER &= (uint16_t)TIM_CCER_CC1E; // Capture enable |
kenjiArai | 0:bfdc6ed58a06 | 445 | TIM4->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);// external mode 1 |
kenjiArai | 0:bfdc6ed58a06 | 446 | TIM4->SMCR |= (uint16_t)( TIM_TS_ITR2 | TIM_SLAVEMODE_EXTERNAL1);// ECE must be ZERO!!!! |
kenjiArai | 0:bfdc6ed58a06 | 447 | TIM4->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS); |
kenjiArai | 0:bfdc6ed58a06 | 448 | TIM4->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter |
kenjiArai | 0:bfdc6ed58a06 | 449 | // PC7 -> Input Capture pin as Timer3 IC2 |
kenjiArai | 0:bfdc6ed58a06 | 450 | GPIOC->AFR[0] &= 0x0fffffff; |
kenjiArai | 0:bfdc6ed58a06 | 451 | GPIOC->AFR[0] |= GPIO_AF2_TIM3 << 28; |
kenjiArai | 0:bfdc6ed58a06 | 452 | GPIOC->MODER &= ~(GPIO_MODER_MODER7); // AF |
kenjiArai | 0:bfdc6ed58a06 | 453 | GPIOC->MODER |= GPIO_MODER_MODER7_1; |
kenjiArai | 0:bfdc6ed58a06 | 454 | GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR7); |
kenjiArai | 0:bfdc6ed58a06 | 455 | GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_0; // PU |
kenjiArai | 0:bfdc6ed58a06 | 456 | // Initialize Timer3 IC2 |
kenjiArai | 0:bfdc6ed58a06 | 457 | TIM3->CCER &= (uint16_t)~TIM_CCER_CC2E; // Disable the CC2 |
kenjiArai | 0:bfdc6ed58a06 | 458 | TIM3->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);// input filter + input select |
kenjiArai | 0:bfdc6ed58a06 | 459 | TIM3->CCMR1 |= (uint16_t)TIM_CCMR1_CC2S_0; |
kenjiArai | 0:bfdc6ed58a06 | 460 | TIM3->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); // positive edge |
kenjiArai | 0:bfdc6ed58a06 | 461 | TIM3->CCER |= (uint16_t)TIM_CCER_CC2E; // enable capture |
kenjiArai | 0:bfdc6ed58a06 | 462 | // PB6 -> Input Capture pin as Timer4 IC1 |
kenjiArai | 0:bfdc6ed58a06 | 463 | GPIOB->AFR[0] &= 0xf0ffffff; |
kenjiArai | 0:bfdc6ed58a06 | 464 | GPIOB->AFR[0] |= GPIO_AF2_TIM4 << 24; |
kenjiArai | 0:bfdc6ed58a06 | 465 | GPIOB->MODER &= ~(GPIO_MODER_MODER6); // AF |
kenjiArai | 0:bfdc6ed58a06 | 466 | GPIOB->MODER |= GPIO_MODER_MODER6_1; |
kenjiArai | 0:bfdc6ed58a06 | 467 | GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR6); |
kenjiArai | 0:bfdc6ed58a06 | 468 | GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_0; // Pull-up=01 |
kenjiArai | 0:bfdc6ed58a06 | 469 | // Initialize Timer4 IC1 |
kenjiArai | 0:bfdc6ed58a06 | 470 | TIM4->CCER &= (uint16_t)~TIM_CCER_CC1E; |
kenjiArai | 0:bfdc6ed58a06 | 471 | TIM4->CCMR1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); |
kenjiArai | 0:bfdc6ed58a06 | 472 | TIM4->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0; |
kenjiArai | 0:bfdc6ed58a06 | 473 | TIM4->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); // positive edge |
kenjiArai | 0:bfdc6ed58a06 | 474 | TIM4->CCER |= (uint16_t)TIM_CCER_CC1E; // enable capture |
kenjiArai | 0:bfdc6ed58a06 | 475 | // Only for Debug purpose |
kenjiArai | 0:bfdc6ed58a06 | 476 | // PB |
kenjiArai | 0:bfdc6ed58a06 | 477 | PRINTF("// PB6 -> Input Capture pin as Timer4 CH1/TI1\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 478 | PRINTF("GPIOB->AFR[0]0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]); |
kenjiArai | 0:bfdc6ed58a06 | 479 | PRINTF("GPIOB->AFR[1]0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]); |
kenjiArai | 0:bfdc6ed58a06 | 480 | PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER); |
kenjiArai | 0:bfdc6ed58a06 | 481 | PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR); |
kenjiArai | 0:bfdc6ed58a06 | 482 | PRINTF("GPIOB->OTYPER 0x%08x:0x%08x\r\n",&GPIOB->OTYPER, GPIOB->OTYPER); |
kenjiArai | 0:bfdc6ed58a06 | 483 | PRINTF("GPIOB->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOB->OSPEEDR, GPIOB->OSPEEDR); |
kenjiArai | 0:bfdc6ed58a06 | 484 | // PC |
kenjiArai | 0:bfdc6ed58a06 | 485 | PRINTF("// PC6 -> unkown frequency input pin as Timer3 CH1/TI1\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 486 | PRINTF("// PC7 -> Input Capture pin as Timer3 CH2/TI2\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 487 | PRINTF("GPIOC->AFR[0]0x%08x:0x%08x\r\n",&GPIOC->AFR[0], GPIOC->AFR[0]); |
kenjiArai | 0:bfdc6ed58a06 | 488 | PRINTF("GPIOC->AFR[1]0x%08x:0x%08x\r\n",&GPIOC->AFR[1], GPIOC->AFR[1]); |
kenjiArai | 0:bfdc6ed58a06 | 489 | PRINTF("GPIOC->MODER 0x%08x:0x%08x\r\n",&GPIOC->MODER, GPIOC->MODER); |
kenjiArai | 0:bfdc6ed58a06 | 490 | PRINTF("GPIOC->PUPDR 0x%08x:0x%08x\r\n",&GPIOC->PUPDR, GPIOC->PUPDR); |
kenjiArai | 0:bfdc6ed58a06 | 491 | PRINTF("GPIOC->OTYPER 0x%08x:0x%08x\r\n",&GPIOC->OTYPER, GPIOC->OTYPER); |
kenjiArai | 0:bfdc6ed58a06 | 492 | PRINTF("GPIOC->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOC->OSPEEDR, GPIOC->OSPEEDR); |
kenjiArai | 0:bfdc6ed58a06 | 493 | // TIM3 |
kenjiArai | 0:bfdc6ed58a06 | 494 | PRINTF("// PC6 -> Timer3(16bit) for an external up counter mode\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 495 | PRINTF("// PC7 -> Timer3 IC2\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 496 | PRINTF("TIM3->CR1 0x%08x:0x%08x\r\n",&TIM3->CR1, TIM3->CR1); |
kenjiArai | 0:bfdc6ed58a06 | 497 | PRINTF("TIM3->ARR 0x%08x:0x%08x\r\n",&TIM3->ARR, TIM3->ARR); |
kenjiArai | 0:bfdc6ed58a06 | 498 | PRINTF("TIM3->PSC 0x%08x:0x%08x\r\n",&TIM3->PSC, TIM3->PSC); |
kenjiArai | 0:bfdc6ed58a06 | 499 | PRINTF("TIM3->CCMR1 0x%08x:0x%08x\r\n",&TIM3->CCMR1, TIM3->CCMR1); |
kenjiArai | 0:bfdc6ed58a06 | 500 | PRINTF("TIM3->CCMR2 0x%08x:0x%08x\r\n",&TIM3->CCMR2, TIM3->CCMR2); |
kenjiArai | 0:bfdc6ed58a06 | 501 | PRINTF("TIM3->CCER 0x%08x:0x%08x\r\n",&TIM3->CCER, TIM3->CCER); |
kenjiArai | 0:bfdc6ed58a06 | 502 | PRINTF("TIM3->SMCR 0x%08x:0x%08x\r\n",&TIM3->SMCR, TIM3->SMCR); |
kenjiArai | 0:bfdc6ed58a06 | 503 | // TIM4 |
kenjiArai | 0:bfdc6ed58a06 | 504 | PRINTF("// none-> Timer4(16bit) for an slave counter\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 505 | PRINTF("// PB6 -> Timer4 IC1\r\n"); |
kenjiArai | 0:bfdc6ed58a06 | 506 | PRINTF("TIM4->CR1 0x%08x:0x%08x\r\n",&TIM4->CR1, TIM4->CR1); |
kenjiArai | 0:bfdc6ed58a06 | 507 | PRINTF("TIM4->ARR 0x%08x:0x%08x\r\n",&TIM4->ARR, TIM4->ARR); |
kenjiArai | 0:bfdc6ed58a06 | 508 | PRINTF("TIM4->PSC 0x%08x:0x%08x\r\n",&TIM4->PSC, TIM4->PSC); |
kenjiArai | 0:bfdc6ed58a06 | 509 | PRINTF("TIM4->CCMR1 0x%08x:0x%08x\r\n",&TIM4->CCMR1, TIM4->CCMR1); |
kenjiArai | 0:bfdc6ed58a06 | 510 | PRINTF("TIM4->CCMR2 0x%08x:0x%08x\r\n",&TIM4->CCMR2, TIM4->CCMR2); |
kenjiArai | 0:bfdc6ed58a06 | 511 | PRINTF("TIM4->CCER 0x%08x:0x%08x\r\n",&TIM4->CCER, TIM4->CCER); |
kenjiArai | 0:bfdc6ed58a06 | 512 | PRINTF("TIM4->SMCR 0x%08x:0x%08x\r\n\r\n",&TIM4->SMCR, TIM4->SMCR); |
kenjiArai | 0:bfdc6ed58a06 | 513 | PRINTF("RCC->APB1ENR 0x%08x:0x%08x\r\n\r\n",&RCC->APB1ENR, RCC->APB1ENR); |
kenjiArai | 0:bfdc6ed58a06 | 514 | #if defined(IRQ_DRIVE) |
kenjiArai | 0:bfdc6ed58a06 | 515 | // Interrupt Timer3 IC2 |
kenjiArai | 0:bfdc6ed58a06 | 516 | tim3p4_ready_flg = 0; |
kenjiArai | 0:bfdc6ed58a06 | 517 | tim3p4_cnt_data = 0; |
kenjiArai | 0:bfdc6ed58a06 | 518 | tim3p4_old_cnt_data = 0; |
kenjiArai | 0:bfdc6ed58a06 | 519 | TIM3->SR &= ~TIM_SR_CC2IF; // clear IC flag |
kenjiArai | 0:bfdc6ed58a06 | 520 | TIM4->SR &= ~TIM_SR_CC1IF; |
kenjiArai | 0:bfdc6ed58a06 | 521 | TIM3->DIER |= TIM_DIER_CC2IE; |
kenjiArai | 0:bfdc6ed58a06 | 522 | NVIC_SetVector(TIM3_IRQn, (uint32_t)irq_ic2_TIM3P4); |
kenjiArai | 0:bfdc6ed58a06 | 523 | NVIC_ClearPendingIRQ(TIM3_IRQn); |
kenjiArai | 0:bfdc6ed58a06 | 524 | NVIC_EnableIRQ(TIM3_IRQn); |
kenjiArai | 0:bfdc6ed58a06 | 525 | #endif |
kenjiArai | 0:bfdc6ed58a06 | 526 | } |
kenjiArai | 0:bfdc6ed58a06 | 527 | |
kenjiArai | 0:bfdc6ed58a06 | 528 | } // Frequency_counter |