Diff: INIT_HW/INIT_HW.cpp

Revision:

23:59218d4a256d

Parent:

21:e5f1a43ea6f9

--- a/INIT_HW/INIT_HW.cpp	Mon Sep 09 10:41:16 2019 +0000
+++ b/INIT_HW/INIT_HW.cpp	Tue Sep 10 09:38:26 2019 +0000
@@ -47,7 +47,7 @@
     //PWM Setup
 
     TIM4->PSC = 0x0;                                            // no prescaler, timer counts up in sync with the peripheral clock
-    TIM4->ARR = PWM_ARR;                                          // set auto reload, 40 khz
+    TIM4->ARR = PWM_ARR;                                          // set auto reload
     TIM4->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
     TIM4->CR1 |= TIM_CR1_CEN;                                   // enable TIM4
     
@@ -67,28 +67,28 @@
     TIM3->RCR |= 0x001;                                         // update event once per up/down count of TIM3 
     TIM3->EGR |= TIM_EGR_UG;
 
-    TIM3->PSC = 0x0;                                            // no prescaler, timer counts up in sync with the peripheral clock
+    TIM3->PSC = 0x00;                                            // no prescaler, timer counts up in sync with the peripheral clock
     TIM3->ARR = TMR3_COUNT;                                          // set auto reload, 5 khz
     TIM3->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
     TIM3->CR1 |= TIM_CR1_CEN;                                   // enable TIM4
 }
 
-void Init_TMR5(){
-    RCC->APB1ENR |= RCC_APB1ENR_TIM5EN;                         // enable TIM5 clock
+void Init_TMR2(){
+    RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;                         // enable TIM5 clock
     
      //ISR Setup     
     
-    NVIC_EnableIRQ(TIM5_IRQn);                         //Enable TIM5 IRQ
+    NVIC_EnableIRQ(TIM2_IRQn);                         //Enable TIM5 IRQ
 
-    TIM5->DIER |= TIM_DIER_UIE;                                 // enable update interrupt
-    TIM5->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
-    TIM5->CR1 |= TIM_CR1_UDIS;
-    TIM5->CR1 |= TIM_CR1_ARPE;                                  // autoreload on, 
-    TIM5->RCR |= 0x001;                                         // update event once per up/down count of TIM5
-    TIM5->EGR |= TIM_EGR_UG;
+    TIM2->DIER |= TIM_DIER_UIE;                                 // enable update interrupt
+    TIM2->CR1 = 0x40;                                           // CMS = 10, interrupt only when counting up // Center-aligned mode
+    TIM2->CR1 |= TIM_CR1_UDIS;
+    TIM2->CR1 |= TIM_CR1_ARPE;                                  // autoreload on, 
+    TIM2->RCR |= 0x001;                                         // update event once per up/down count of TIM5
+    TIM2->EGR |= TIM_EGR_UG;
 
-    TIM5->PSC = 0x0;                                            // no prescaler, timer counts up in sync with the peripheral clock
-    TIM5->ARR = TMR5_COUNT;                                          // set auto reload, 5 khz
-    TIM5->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
-    TIM5->CR1 |= TIM_CR1_CEN;                                   // enable TIM5
+    TIM2->PSC = 0x12;                                            // no prescaler, timer counts up in sync with the peripheral clock
+    TIM2->ARR = TMR2_COUNT;                                          // set auto reload, 5 khz
+    TIM2->CCER |= ~(TIM_CCER_CC1NP);                            // Interupt when low side is on.
+    TIM2->CR1 |= TIM_CR1_CEN;                                   // enable TIM5
 }
\ No newline at end of file