Joaquin Verastegui / jro

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Dependents:   JRO_CR2 frdm_test

Fork of jro by Miguel Urco

dds.h@1:7c424a3e12ea, 2014-12-04 (annotated)

Committer:
miguelcordero191
Date:
Thu Dec 04 14:35:52 2014 +0000
Revision:
1:7c424a3e12ea
Parent:
0:b444ea725ba7 
First release: write and read process working very well

Who changed what in which revision?

UserRevisionLine numberNew contents of line
miguelcordero191 0:b444ea725ba7 1 #include "mbed.h"
miguelcordero191 0:b444ea725ba7 2
miguelcordero191 0:b444ea725ba7 3 #define SPI_BITS 8
miguelcordero191 0:b444ea725ba7 4 #define SPI_MODE 0
miguelcordero191 0:b444ea725ba7 5 #define SPI_FREQ 10000
miguelcordero191 0:b444ea725ba7 6
miguelcordero191 0:b444ea725ba7 7 class DDS{
miguelcordero191 0:b444ea725ba7 8 private:
miguelcordero191 0:b444ea725ba7 9 float frequency; // Work frequency in MHz
miguelcordero191 1:7c424a3e12ea 10 char cr_multiplier; // Multiplier 4- 20
miguelcordero191 1:7c424a3e12ea 11 char cr_mode; // Single, FSK, Ramped FSK, Chirp, BPSK
miguelcordero191 1:7c424a3e12ea 12 bool cr_qdac_pwdn; // Q DAC power down enable: 0 -> disable
miguelcordero191 0:b444ea725ba7 13 bool cr_ioupdclk; // IO Update clock enable: 0 -> input
miguelcordero191 0:b444ea725ba7 14 bool cr_inv_sinc; // Inverse sinc filter enable: 0 -> enable
miguelcordero191 0:b444ea725ba7 15 bool cr_osk_en; // Enable AM: 0 -> disabled
miguelcordero191 0:b444ea725ba7 16 bool cr_osk_int; // ext/int output shaped control: 0 -> external
miguelcordero191 0:b444ea725ba7 17 bool cr_msb_lsb; // msb/lsb bit first: 0 -> MSB
miguelcordero191 0:b444ea725ba7 18 bool cr_sdo; // SDO pin active: 0 -> inactive
miguelcordero191 0:b444ea725ba7 19
miguelcordero191 0:b444ea725ba7 20 SPI *spi_device;
miguelcordero191 0:b444ea725ba7 21 //DDS I/O
miguelcordero191 0:b444ea725ba7 22 DigitalOut *dds_mreset;
miguelcordero191 1:7c424a3e12ea 23 DigitalOut *dds_outramp;
miguelcordero191 0:b444ea725ba7 24 DigitalOut *dds_sp_mode;
miguelcordero191 0:b444ea725ba7 25 DigitalOut *dds_cs;
miguelcordero191 0:b444ea725ba7 26 DigitalOut *dds_io_reset;
miguelcordero191 0:b444ea725ba7 27 DigitalInOut *dds_updclk;
miguelcordero191 1:7c424a3e12ea 28
miguelcordero191 1:7c424a3e12ea 29 char frequency1[6];
miguelcordero191 1:7c424a3e12ea 30 char frequency2[6];
miguelcordero191 1:7c424a3e12ea 31 char phase1[2];
miguelcordero191 1:7c424a3e12ea 32 char phase2[2];
miguelcordero191 1:7c424a3e12ea 33 char amplitudeI[2];
miguelcordero191 1:7c424a3e12ea 34 char amplitudeQ[2];
miguelcordero191 1:7c424a3e12ea 35 bool rf_enabled;
miguelcordero191 1:7c424a3e12ea 36
miguelcordero191 1:7c424a3e12ea 37 char* cmd_answer;
miguelcordero191 1:7c424a3e12ea 38 unsigned long cmd_answer_len;
miguelcordero191 1:7c424a3e12ea 39
miguelcordero191 1:7c424a3e12ea 40 int __writeData(char addr, char ndata, const char* data);
miguelcordero191 1:7c424a3e12ea 41 char* __readData(char addr, char ndata);
miguelcordero191 1:7c424a3e12ea 42 int __writeDataAndVerify(char addr, char ndata, const char* wr_spi_data);
miguelcordero191 1:7c424a3e12ea 43 char* __getControlRegister();
miguelcordero191 0:b444ea725ba7 44 int __writeControlRegister();
miguelcordero191 0:b444ea725ba7 45
miguelcordero191 0:b444ea725ba7 46 public:
miguelcordero191 0:b444ea725ba7 47 bool isConfig;
miguelcordero191 0:b444ea725ba7 48
miguelcordero191 1:7c424a3e12ea 49 DDS(SPI *spi_dev, DigitalOut *mreset, DigitalOut *outramp, DigitalOut *spmode, DigitalOut *cs, DigitalOut *ioreset, DigitalInOut *updclk);
miguelcordero191 0:b444ea725ba7 50 int init();
miguelcordero191 0:b444ea725ba7 51 int reset();
miguelcordero191 0:b444ea725ba7 52 int scanIOUpdate();
miguelcordero191 0:b444ea725ba7 53 int find();
miguelcordero191 1:7c424a3e12ea 54 char* rdMode();
miguelcordero191 1:7c424a3e12ea 55 char* rdMultiplier();
miguelcordero191 1:7c424a3e12ea 56 char* rdPhase1();
miguelcordero191 1:7c424a3e12ea 57 char* rdPhase2();
miguelcordero191 1:7c424a3e12ea 58 char* rdFrequency1();
miguelcordero191 1:7c424a3e12ea 59 char* rdFrequency2();
miguelcordero191 1:7c424a3e12ea 60 char* rdAmplitudeI();
miguelcordero191 1:7c424a3e12ea 61 char* rdAmplitudeQ();
miguelcordero191 1:7c424a3e12ea 62 int wrMode(char mode);
miguelcordero191 1:7c424a3e12ea 63 int wrMultiplier(char multiplier, float clock);
miguelcordero191 1:7c424a3e12ea 64 int wrPhase1(char* phase);
miguelcordero191 1:7c424a3e12ea 65 int wrPhase2(char* phase);
miguelcordero191 1:7c424a3e12ea 66 int wrFrequency1(char* freq);
miguelcordero191 1:7c424a3e12ea 67 int wrFrequency2(char* freq);
miguelcordero191 1:7c424a3e12ea 68 int wrAmplitudeI(char* amplitude);
miguelcordero191 1:7c424a3e12ea 69 int wrAmplitudeQ(char* amplitude);
miguelcordero191 1:7c424a3e12ea 70 int enableRF();
miguelcordero191 1:7c424a3e12ea 71 int disableRF();
miguelcordero191 1:7c424a3e12ea 72 int defaultSettings();
miguelcordero191 1:7c424a3e12ea 73 char* newCommand(unsigned short cmd, char* payload, unsigned long payload_len);
miguelcordero191 1:7c424a3e12ea 74 char* getCmdAnswer();
miguelcordero191 1:7c424a3e12ea 75 unsigned long getCmdAnswerLen();
miguelcordero191 0:b444ea725ba7 76
miguelcordero191 0:b444ea725ba7 77 };