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John Mitchell / DMSupport

Subdirectory provided by Embedded Artists

Dependencies: DM_FATFileSystem DM_HttpServer DM_USBHost EthernetInterface USBDevice mbed-rpc mbed-rtos mbed-src

Dependents: lpc4088_displaymodule_hello_world_Sept_2018

Fork of DMSupport by Embedded Artists

FileSystems/MCIFileSystem.cpp@9:a33326afd686, 2014-12-11 (annotated)

Committer:: embeddedartists
Date:: Thu Dec 11 18:23:07 2014 +0000
Revision:: 9:a33326afd686
Parent:: 0:6b68dac0d986
Child:: 31:d47cffcb0a3e

Updated documentation

Who changed what in which revision?

User	Revision	Line number	New contents of line
embeddedartists	0:6b68dac0d986	1	/*
embeddedartists	9:a33326afd686	2	* Copyright 2014 Embedded Artists AB
embeddedartists	0:6b68dac0d986	3	*
embeddedartists	0:6b68dac0d986	4	* Licensed under the Apache License, Version 2.0 (the "License");
embeddedartists	0:6b68dac0d986	5	* you may not use this file except in compliance with the License.
embeddedartists	0:6b68dac0d986	6	* You may obtain a copy of the License at
embeddedartists	0:6b68dac0d986	7	*
embeddedartists	0:6b68dac0d986	8	* http://www.apache.org/licenses/LICENSE-2.0
embeddedartists	0:6b68dac0d986	9	*
embeddedartists	0:6b68dac0d986	10	* Unless required by applicable law or agreed to in writing, software
embeddedartists	0:6b68dac0d986	11	* distributed under the License is distributed on an "AS IS" BASIS,
embeddedartists	0:6b68dac0d986	12	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
embeddedartists	0:6b68dac0d986	13	* See the License for the specific language governing permissions and
embeddedartists	0:6b68dac0d986	14	* limitations under the License.
embeddedartists	0:6b68dac0d986	15	*/
embeddedartists	0:6b68dac0d986	16
embeddedartists	0:6b68dac0d986	17	/******************************************************************************
embeddedartists	0:6b68dac0d986	18	* Includes
embeddedartists	0:6b68dac0d986	19	*****************************************************************************/
embeddedartists	0:6b68dac0d986	20
embeddedartists	0:6b68dac0d986	21	#include "MCIFileSystem.h"
embeddedartists	0:6b68dac0d986	22	#include "mbed_debug.h"
embeddedartists	0:6b68dac0d986	23
embeddedartists	0:6b68dac0d986	24	#include "diskio.h" //STA_* defines
embeddedartists	0:6b68dac0d986	25	#include "gpdma.h"
embeddedartists	0:6b68dac0d986	26
embeddedartists	0:6b68dac0d986	27	/******************************************************************************
embeddedartists	0:6b68dac0d986	28	* Defines and typedefs
embeddedartists	0:6b68dac0d986	29	*****************************************************************************/
embeddedartists	0:6b68dac0d986	30
embeddedartists	0:6b68dac0d986	31	#define MCI_DBG 0
embeddedartists	0:6b68dac0d986	32
embeddedartists	0:6b68dac0d986	33	#define CMD_TIMEOUT (0x10000)
embeddedartists	0:6b68dac0d986	34
embeddedartists	0:6b68dac0d986	35	#define DATA_TIMER_VALUE_R (SDC_TRAN_CLOCK_RATE / 4) // 250ms
embeddedartists	0:6b68dac0d986	36	#define DATA_TIMER_VALUE_W (SDC_TRAN_CLOCK_RATE) // 1000ms
embeddedartists	0:6b68dac0d986	37	#define ACQUIRE_DELAY (0.100f) /!< inter-command acquire oper condition delay in seconds /
embeddedartists	0:6b68dac0d986	38
embeddedartists	0:6b68dac0d986	39	#define SYSCTL_CLOCK_SDC (1<<28)
embeddedartists	0:6b68dac0d986	40
embeddedartists	0:6b68dac0d986	41	/**
embeddedartists	0:6b68dac0d986	42	* @brief SDC Clear Register bit definitions
embeddedartists	0:6b68dac0d986	43	*/
embeddedartists	0:6b68dac0d986	44	/** Clear all status flag*/
embeddedartists	0:6b68dac0d986	45	#define SDC_CLEAR_ALL ((uint32_t) 0x7FF)
embeddedartists	0:6b68dac0d986	46
embeddedartists	0:6b68dac0d986	47	/*
embeddedartists	0:6b68dac0d986	48	* SDMMC Card bus clock rate definitions
embeddedartists	0:6b68dac0d986	49	*/
embeddedartists	0:6b68dac0d986	50	/** Card bus clock in Card Identification Mode */
embeddedartists	0:6b68dac0d986	51	#define SDC_IDENT_CLOCK_RATE (400000) /* 400KHz */
embeddedartists	0:6b68dac0d986	52	/** Card bus clock in Data Transfer Mode */
embeddedartists	0:6b68dac0d986	53	#define SDC_TRAN_CLOCK_RATE (20000000) /* 20MHz */
embeddedartists	0:6b68dac0d986	54
embeddedartists	0:6b68dac0d986	55	/**
embeddedartists	0:6b68dac0d986	56	* @brief SDC Power Control Register bit definitions
embeddedartists	0:6b68dac0d986	57	*/
embeddedartists	0:6b68dac0d986	58	/** SD_CMD Output Control */
embeddedartists	0:6b68dac0d986	59	#define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
embeddedartists	0:6b68dac0d986	60
embeddedartists	0:6b68dac0d986	61	/**
embeddedartists	0:6b68dac0d986	62	* @brief SDC Command Register bit definitions
embeddedartists	0:6b68dac0d986	63	*/
embeddedartists	0:6b68dac0d986	64	/** SDC Command Register Bitmask */
embeddedartists	0:6b68dac0d986	65	#define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
embeddedartists	0:6b68dac0d986	66	/** SDC Command Index Bitmask */
embeddedartists	0:6b68dac0d986	67	#define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
embeddedartists	0:6b68dac0d986	68	/** Set SDC Command Index */
embeddedartists	0:6b68dac0d986	69	#define SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
embeddedartists	0:6b68dac0d986	70	/** No response is expected */
embeddedartists	0:6b68dac0d986	71	#define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
embeddedartists	0:6b68dac0d986	72	/** Short response is expected */
embeddedartists	0:6b68dac0d986	73	#define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
embeddedartists	0:6b68dac0d986	74	/** Long response is expected */
embeddedartists	0:6b68dac0d986	75	#define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
embeddedartists	0:6b68dac0d986	76	/** Response bit mask */
embeddedartists	0:6b68dac0d986	77	#define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
embeddedartists	0:6b68dac0d986	78	/** Mark that command timer is disabled and CPSM waits for interrupt request */
embeddedartists	0:6b68dac0d986	79	#define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
embeddedartists	0:6b68dac0d986	80	/** Mark that CPSM waits for CmdPend before starting sending a command*/
embeddedartists	0:6b68dac0d986	81	#define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
embeddedartists	0:6b68dac0d986	82	/** Enable CPSM */
embeddedartists	0:6b68dac0d986	83	#define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
embeddedartists	0:6b68dac0d986	84
embeddedartists	0:6b68dac0d986	85	/**
embeddedartists	0:6b68dac0d986	86	* @brief SDC Command Response Register bit definitions
embeddedartists	0:6b68dac0d986	87	*/
embeddedartists	0:6b68dac0d986	88	/** SDC Command Response value */
embeddedartists	0:6b68dac0d986	89	#define SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
embeddedartists	0:6b68dac0d986	90
embeddedartists	0:6b68dac0d986	91	/*
embeddedartists	0:6b68dac0d986	92	* SD/MMC Response type definitions
embeddedartists	0:6b68dac0d986	93	*/
embeddedartists	0:6b68dac0d986	94	#define CMDRESP_NONE_TYPE (SDC_COMMAND_NO_RSP)
embeddedartists	0:6b68dac0d986	95	#define CMDRESP_R1_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:6b68dac0d986	96	#define CMDRESP_R1b_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:6b68dac0d986	97	#define CMDRESP_R2_TYPE (SDC_COMMAND_LONG_RSP)
embeddedartists	0:6b68dac0d986	98	#define CMDRESP_R3_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:6b68dac0d986	99	#define CMDRESP_R6_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:6b68dac0d986	100	#define CMDRESP_R7_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:6b68dac0d986	101
embeddedartists	0:6b68dac0d986	102	/*
embeddedartists	0:6b68dac0d986	103	* SD command values (Command Index, Response)
embeddedartists	0:6b68dac0d986	104	*/
embeddedartists	0:6b68dac0d986	105	#define SD_GO_IDLE_STATE (SDC_COMMAND_INDEX(MMC_GO_IDLE_STATE) \| CMDRESP_NONE_TYPE \| SDC_COMMAND_INTERRUPT) /!< GO_IDLE_STATE(MMC) or RESET(SD) /
embeddedartists	0:6b68dac0d986	106	#define SD_CMD1_SEND_OP_COND (SDC_COMMAND_INDEX(MMC_SEND_OP_COND) \| CMDRESP_R3_TYPE \| 0) /!< SEND_OP_COND(MMC) or ACMD41(SD) /
embeddedartists	0:6b68dac0d986	107	#define SD_CMD2_ALL_SEND_CID (SDC_COMMAND_INDEX(MMC_ALL_SEND_CID) \| CMDRESP_R2_TYPE \| 0) /!< ALL_SEND_CID /
embeddedartists	0:6b68dac0d986	108	#define SD_CMD3_SET_RELATIVE_ADDR (SDC_COMMAND_INDEX(MMC_SET_RELATIVE_ADDR) \| CMDRESP_R1_TYPE \| 0) /!< SET_RELATE_ADDR /
embeddedartists	0:6b68dac0d986	109	#define SD_CMD3_SEND_RELATIVE_ADDR (SDC_COMMAND_INDEX(SD_SEND_RELATIVE_ADDR) \| CMDRESP_R6_TYPE \| 0) /!< SEND_RELATE_ADDR /
embeddedartists	0:6b68dac0d986	110	#define SD_CMD7_SELECT_CARD (SDC_COMMAND_INDEX(MMC_SELECT_CARD) \| CMDRESP_R1b_TYPE \| 0) /!< SELECT/DESELECT_CARD /
embeddedartists	0:6b68dac0d986	111	#define SD_CMD8_SEND_IF_COND (SDC_COMMAND_INDEX(SD_CMD8) \| CMDRESP_R7_TYPE \| 0) /!< SEND_IF_COND /
embeddedartists	0:6b68dac0d986	112	#define SD_CMD9_SEND_CSD (SDC_COMMAND_INDEX(MMC_SEND_CSD) \| CMDRESP_R2_TYPE \| 0) /!< SEND_CSD /
embeddedartists	0:6b68dac0d986	113	#define SD_CMD12_STOP_TRANSMISSION (SDC_COMMAND_INDEX(MMC_STOP_TRANSMISSION) \| CMDRESP_R1_TYPE \| 0) /!< STOP_TRANSMISSION /
embeddedartists	0:6b68dac0d986	114	#define SD_CMD13_SEND_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) \| CMDRESP_R1_TYPE \| 0) /!< SEND_STATUS /
embeddedartists	0:6b68dac0d986	115
embeddedartists	0:6b68dac0d986	116	/* Block-Oriented Read Commands (class 2) */
embeddedartists	0:6b68dac0d986	117	#define SD_CMD16_SET_BLOCKLEN (SDC_COMMAND_INDEX(MMC_SET_BLOCKLEN) \| CMDRESP_R1_TYPE \| 0) /!< SET_BLOCK_LEN /
embeddedartists	0:6b68dac0d986	118	#define SD_CMD17_READ_SINGLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_SINGLE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< READ_SINGLE_BLOCK /
embeddedartists	0:6b68dac0d986	119	#define SD_CMD18_READ_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_MULTIPLE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< READ_MULTIPLE_BLOCK /
embeddedartists	0:6b68dac0d986	120
embeddedartists	0:6b68dac0d986	121	/* Block-Oriented Write Commands (class 4) */
embeddedartists	0:6b68dac0d986	122	#define SD_CMD24_WRITE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< WRITE_BLOCK /
embeddedartists	0:6b68dac0d986	123	#define SD_CMD25_WRITE_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_MULTIPLE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< WRITE_MULTIPLE_BLOCK /
embeddedartists	0:6b68dac0d986	124
embeddedartists	0:6b68dac0d986	125	/* Erase Commands (class 5) */
embeddedartists	0:6b68dac0d986	126	#define SD_CMD32_ERASE_WR_BLK_START (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_START) \| CMDRESP_R1_TYPE \| 0) /!< ERASE_WR_BLK_START /
embeddedartists	0:6b68dac0d986	127	#define SD_CMD33_ERASE_WR_BLK_END (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_END) \| CMDRESP_R1_TYPE \| 0) /!< ERASE_WR_BLK_END /
embeddedartists	0:6b68dac0d986	128	#define SD_CMD38_ERASE (SDC_COMMAND_INDEX(SD_ERASE) \| CMDRESP_R1b_TYPE \| 0) /!< ERASE /
embeddedartists	0:6b68dac0d986	129
embeddedartists	0:6b68dac0d986	130	/* Application-Specific Commands (class 8) */
embeddedartists	0:6b68dac0d986	131	#define SD_CMD55_APP_CMD (SDC_COMMAND_INDEX(MMC_APP_CMD) \| CMDRESP_R1_TYPE \| 0) /!< APP_CMD /
embeddedartists	0:6b68dac0d986	132	#define SD_ACMD6_SET_BUS_WIDTH (SDC_COMMAND_INDEX(SD_APP_SET_BUS_WIDTH) \| CMDRESP_R1_TYPE \| 0) /!< SET_BUS_WIDTH /
embeddedartists	0:6b68dac0d986	133	#define SD_ACMD13_SEND_SD_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) \| CMDRESP_R1_TYPE \| 0) /!< SEND_SD_STATUS /
embeddedartists	0:6b68dac0d986	134	#define SD_ACMD41_SD_SEND_OP_COND (SDC_COMMAND_INDEX(SD_APP_OP_COND) \| CMDRESP_R3_TYPE \| 0) /!< SD_SEND_OP_COND /
embeddedartists	0:6b68dac0d986	135
embeddedartists	0:6b68dac0d986	136	/**
embeddedartists	0:6b68dac0d986	137	* @brief SDC Interrupt Mask Register bit definitions
embeddedartists	0:6b68dac0d986	138	*/
embeddedartists	0:6b68dac0d986	139	/** Mask CmdCrcFail flag.*/
embeddedartists	0:6b68dac0d986	140	#define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
embeddedartists	0:6b68dac0d986	141	/** Mask DataCrcFail flag. */
embeddedartists	0:6b68dac0d986	142	#define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
embeddedartists	0:6b68dac0d986	143	/** Mask CmdTimeOut flag. */
embeddedartists	0:6b68dac0d986	144	#define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
embeddedartists	0:6b68dac0d986	145	/** Mask DataTimeOut flag. */
embeddedartists	0:6b68dac0d986	146	#define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
embeddedartists	0:6b68dac0d986	147	/** Mask TxUnderrun flag. */
embeddedartists	0:6b68dac0d986	148	#define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
embeddedartists	0:6b68dac0d986	149	/** Mask RxOverrun flag. */
embeddedartists	0:6b68dac0d986	150	#define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
embeddedartists	0:6b68dac0d986	151	/** Mask CmdRespEnd flag. */
embeddedartists	0:6b68dac0d986	152	#define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
embeddedartists	0:6b68dac0d986	153	/** Mask CmdSent flag.*/
embeddedartists	0:6b68dac0d986	154	#define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
embeddedartists	0:6b68dac0d986	155	/** Mask DataEnd flag.*/
embeddedartists	0:6b68dac0d986	156	#define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
embeddedartists	0:6b68dac0d986	157	/** Mask StartBitErr flag.*/
embeddedartists	0:6b68dac0d986	158	#define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
embeddedartists	0:6b68dac0d986	159	/** Mask DataBlockEnd flag.*/
embeddedartists	0:6b68dac0d986	160	#define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
embeddedartists	0:6b68dac0d986	161	/** Mask CmdActive flag.*/
embeddedartists	0:6b68dac0d986	162	#define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
embeddedartists	0:6b68dac0d986	163	/** Mask TxActive flag.*/
embeddedartists	0:6b68dac0d986	164	#define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
embeddedartists	0:6b68dac0d986	165	/** Mask RxActive flag.*/
embeddedartists	0:6b68dac0d986	166	#define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
embeddedartists	0:6b68dac0d986	167	/** Mask TxFifoHalfEmpty flag.*/
embeddedartists	0:6b68dac0d986	168	#define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
embeddedartists	0:6b68dac0d986	169	/** Mask RxFifoHalfFull flag.*/
embeddedartists	0:6b68dac0d986	170	#define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
embeddedartists	0:6b68dac0d986	171	/** Mask TxFifoFull flag.*/
embeddedartists	0:6b68dac0d986	172	#define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
embeddedartists	0:6b68dac0d986	173	/** Mask RxFifoFull flag.*/
embeddedartists	0:6b68dac0d986	174	#define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
embeddedartists	0:6b68dac0d986	175	/** Mask TxFifoEmpty flag.*/
embeddedartists	0:6b68dac0d986	176	#define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
embeddedartists	0:6b68dac0d986	177	/** Mask RxFifoEmpty flag.*/
embeddedartists	0:6b68dac0d986	178	#define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
embeddedartists	0:6b68dac0d986	179	/** Mask TxDataAvlbl flag.*/
embeddedartists	0:6b68dac0d986	180	#define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
embeddedartists	0:6b68dac0d986	181	/** Mask RxDataAvlbl flag.*/
embeddedartists	0:6b68dac0d986	182	#define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
embeddedartists	0:6b68dac0d986	183	/** CMD error interrupt mask */
embeddedartists	0:6b68dac0d986	184	#define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL \| SDC_MASK0_CMDTIMEOUT \| SDC_MASK0_STARTBITERR)
embeddedartists	0:6b68dac0d986	185	/** Data Transmit Error interrupt mask */
embeddedartists	0:6b68dac0d986	186	#define SDC_MASK0_TXDATAERR (SDC_MASK0_DATACRCFAIL \| SDC_MASK0_DATATIMEOUT \| SDC_MASK0_TXUNDERRUN \| SDC_MASK0_STARTBITERR)
embeddedartists	0:6b68dac0d986	187	/** Data Receive Error interrupt mask */
embeddedartists	0:6b68dac0d986	188	#define SDC_MASK0_RXDATAERR (SDC_MASK0_DATACRCFAIL \| SDC_MASK0_DATATIMEOUT \| SDC_MASK0_RXOVERRUN \| SDC_MASK0_STARTBITERR)
embeddedartists	0:6b68dac0d986	189	/** Data Transfer interrupt mask*/
embeddedartists	0:6b68dac0d986	190	#define SDC_MASK0_DATA (SDC_MASK0_DATAEND \| SDC_MASK0_DATABLOCKEND )
embeddedartists	0:6b68dac0d986	191
embeddedartists	0:6b68dac0d986	192	/**
embeddedartists	0:6b68dac0d986	193	* @brief SDC Clock Control Register bit definitions
embeddedartists	0:6b68dac0d986	194	*/
embeddedartists	0:6b68dac0d986	195	/** SDC Clock Control Register Bitmask */
embeddedartists	0:6b68dac0d986	196	#define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
embeddedartists	0:6b68dac0d986	197	/** SDC Clock Divider Bitmask */
embeddedartists	0:6b68dac0d986	198	#define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
embeddedartists	0:6b68dac0d986	199	/** Set SDC Clock Divide value */
embeddedartists	0:6b68dac0d986	200	#define SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
embeddedartists	0:6b68dac0d986	201
embeddedartists	0:6b68dac0d986	202	/**
embeddedartists	0:6b68dac0d986	203	* @brief SDC Status Register bit definitions
embeddedartists	0:6b68dac0d986	204	*/
embeddedartists	0:6b68dac0d986	205	/** Command Response received (CRC check failed) */
embeddedartists	0:6b68dac0d986	206	#define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
embeddedartists	0:6b68dac0d986	207	/** Data block sent/received (CRC check failed). */
embeddedartists	0:6b68dac0d986	208	#define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
embeddedartists	0:6b68dac0d986	209	/** Command response timeout.. */
embeddedartists	0:6b68dac0d986	210	#define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
embeddedartists	0:6b68dac0d986	211	/** Data timeout. */
embeddedartists	0:6b68dac0d986	212	#define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
embeddedartists	0:6b68dac0d986	213	/** Transmit FIFO underrun error. */
embeddedartists	0:6b68dac0d986	214	#define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
embeddedartists	0:6b68dac0d986	215	/** Receive FIFO overrun error. */
embeddedartists	0:6b68dac0d986	216	#define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
embeddedartists	0:6b68dac0d986	217	/** Command response received (CRC check passed). */
embeddedartists	0:6b68dac0d986	218	#define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
embeddedartists	0:6b68dac0d986	219	/** Command sent (no response required).*/
embeddedartists	0:6b68dac0d986	220	#define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
embeddedartists	0:6b68dac0d986	221	/** Data end (data counter is zero).*/
embeddedartists	0:6b68dac0d986	222	#define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
embeddedartists	0:6b68dac0d986	223	/** Start bit not detected on all data signals in wide bus mode..*/
embeddedartists	0:6b68dac0d986	224	#define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
embeddedartists	0:6b68dac0d986	225	/** Data block sent/received (CRC check passed).*/
embeddedartists	0:6b68dac0d986	226	#define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
embeddedartists	0:6b68dac0d986	227	/** Command transfer in progress.*/
embeddedartists	0:6b68dac0d986	228	#define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
embeddedartists	0:6b68dac0d986	229	/** Data transmit in progress.*/
embeddedartists	0:6b68dac0d986	230	#define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
embeddedartists	0:6b68dac0d986	231	/** Data receive in progress.*/
embeddedartists	0:6b68dac0d986	232	#define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
embeddedartists	0:6b68dac0d986	233	/** Transmit FIFO half empty.*/
embeddedartists	0:6b68dac0d986	234	#define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
embeddedartists	0:6b68dac0d986	235	/** Receive FIFO half full.*/
embeddedartists	0:6b68dac0d986	236	#define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
embeddedartists	0:6b68dac0d986	237	/** Transmit FIFO full.*/
embeddedartists	0:6b68dac0d986	238	#define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
embeddedartists	0:6b68dac0d986	239	/** Receive FIFO full.*/
embeddedartists	0:6b68dac0d986	240	#define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
embeddedartists	0:6b68dac0d986	241	/** Transmit FIFO empty.*/
embeddedartists	0:6b68dac0d986	242	#define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
embeddedartists	0:6b68dac0d986	243	/** Receive FIFO empty.*/
embeddedartists	0:6b68dac0d986	244	#define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
embeddedartists	0:6b68dac0d986	245	/** Data available in transmit FIFO.*/
embeddedartists	0:6b68dac0d986	246	#define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
embeddedartists	0:6b68dac0d986	247	/** Data available in receive FIFO.*/
embeddedartists	0:6b68dac0d986	248	#define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
embeddedartists	0:6b68dac0d986	249	/** Command Error Status */
embeddedartists	0:6b68dac0d986	250	#define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL \| SDC_STATUS_CMDTIMEOUT \| SDC_STATUS_STARTBITERR)
embeddedartists	0:6b68dac0d986	251	/** Data Error Status */
embeddedartists	0:6b68dac0d986	252	#define SDC_STATUS_DATAERR (SDC_STATUS_DATACRCFAIL \| SDC_STATUS_DATATIMEOUT \| SDC_STATUS_TXUNDERRUN \
embeddedartists	0:6b68dac0d986	253	\| SDC_STATUS_RXOVERRUN \| SDC_STATUS_STARTBITERR)
embeddedartists	0:6b68dac0d986	254	/** FIFO Status*/
embeddedartists	0:6b68dac0d986	255	#define SDC_STATUS_FIFO (SDC_STATUS_TXFIFOHALFEMPTY \| SDC_STATUS_RXFIFOHALFFULL \
embeddedartists	0:6b68dac0d986	256	\| SDC_STATUS_TXFIFOFULL \| SDC_STATUS_RXFIFOFULL \
embeddedartists	0:6b68dac0d986	257	\| SDC_STATUS_TXFIFOEMPTY \| SDC_STATUS_RXFIFOEMPTY \
embeddedartists	0:6b68dac0d986	258	\| SDC_STATUS_DATABLOCKEND)
embeddedartists	0:6b68dac0d986	259
embeddedartists	0:6b68dac0d986	260	/** Data Transfer Status*/
embeddedartists	0:6b68dac0d986	261	#define SDC_STATUS_DATA (SDC_STATUS_DATAEND )
embeddedartists	0:6b68dac0d986	262
embeddedartists	0:6b68dac0d986	263	/**
embeddedartists	0:6b68dac0d986	264	* @brief SDC Data Control Register bit definitions
embeddedartists	0:6b68dac0d986	265	*/
embeddedartists	0:6b68dac0d986	266	/** SDC Data Control Register Bitmask */
embeddedartists	0:6b68dac0d986	267	#define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
embeddedartists	0:6b68dac0d986	268	/** Enable Data Transfer */
embeddedartists	0:6b68dac0d986	269	#define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
embeddedartists	0:6b68dac0d986	270	/** Mark that Data is transfer from card to controller */
embeddedartists	0:6b68dac0d986	271	#define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
embeddedartists	0:6b68dac0d986	272	/** Mark that Data is transfer from controller to card */
embeddedartists	0:6b68dac0d986	273	#define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
embeddedartists	0:6b68dac0d986	274	/** Mark that the transfer mode is Stream Data Transfer */
embeddedartists	0:6b68dac0d986	275	#define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
embeddedartists	0:6b68dac0d986	276	/** Mark that the transfer mode is Block Data Transfer */
embeddedartists	0:6b68dac0d986	277	#define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
embeddedartists	0:6b68dac0d986	278	/** Enable DMA */
embeddedartists	0:6b68dac0d986	279	#define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
embeddedartists	0:6b68dac0d986	280	/** Set Data Block size */
embeddedartists	0:6b68dac0d986	281	#define SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
embeddedartists	0:6b68dac0d986	282	/** Get Data Block size value */
embeddedartists	0:6b68dac0d986	283	#define SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
embeddedartists	0:6b68dac0d986	284
embeddedartists	0:6b68dac0d986	285	/**
embeddedartists	0:6b68dac0d986	286	* @brief OCR Register definitions
embeddedartists	0:6b68dac0d986	287	*/
embeddedartists	0:6b68dac0d986	288	/** Support voltage range 2.7-3.6 */
embeddedartists	0:6b68dac0d986	289	#define SDC_OCR_27_36 ((uint32_t) 0x00FF8000)
embeddedartists	0:6b68dac0d986	290	/** Card power up status bit */
embeddedartists	0:6b68dac0d986	291	#define SDC_OCR_IDLE (((uint32_t) 1) << 31)
embeddedartists	0:6b68dac0d986	292	#define SDC_OCR_BUSY (((uint32_t) 0) << 31)
embeddedartists	0:6b68dac0d986	293
embeddedartists	0:6b68dac0d986	294
embeddedartists	0:6b68dac0d986	295	/* SD/MMC commands - this matrix shows the command, response types, and
embeddedartists	0:6b68dac0d986	296	supported card type for that command.
embeddedartists	0:6b68dac0d986	297	Command Number Resp SD MMC
embeddedartists	0:6b68dac0d986	298	----------------------- ------ ----- --- ---
embeddedartists	0:6b68dac0d986	299	Reset (go idle) CMD0 NA x x
embeddedartists	0:6b68dac0d986	300	Send op condition CMD1 R3 x
embeddedartists	0:6b68dac0d986	301	All send CID CMD2 R2 x x
embeddedartists	0:6b68dac0d986	302	Send relative address CMD3 R1 x
embeddedartists	0:6b68dac0d986	303	Send relative address CMD3 R6 x
embeddedartists	0:6b68dac0d986	304	Program DSR CMD4 NA x
embeddedartists	0:6b68dac0d986	305	Select/deselect card CMD7 R1b x
embeddedartists	0:6b68dac0d986	306	Select/deselect card CMD7 R1 x
embeddedartists	0:6b68dac0d986	307	Send CSD CMD9 R2 x x
embeddedartists	0:6b68dac0d986	308	Send CID CMD10 R2 x x
embeddedartists	0:6b68dac0d986	309	Read data until stop CMD11 R1 x x
embeddedartists	0:6b68dac0d986	310	Stop transmission CMD12 R1/b x x
embeddedartists	0:6b68dac0d986	311	Send status CMD13 R1 x x
embeddedartists	0:6b68dac0d986	312	Go inactive state CMD15 NA x x
embeddedartists	0:6b68dac0d986	313	Set block length CMD16 R1 x x
embeddedartists	0:6b68dac0d986	314	Read single block CMD17 R1 x x
embeddedartists	0:6b68dac0d986	315	Read multiple blocks CMD18 R1 x x
embeddedartists	0:6b68dac0d986	316	Write data until stop CMD20 R1 x
embeddedartists	0:6b68dac0d986	317	Setblock count CMD23 R1 x
embeddedartists	0:6b68dac0d986	318	Write single block CMD24 R1 x x
embeddedartists	0:6b68dac0d986	319	Write multiple blocks CMD25 R1 x x
embeddedartists	0:6b68dac0d986	320	Program CID CMD26 R1 x
embeddedartists	0:6b68dac0d986	321	Program CSD CMD27 R1 x x
embeddedartists	0:6b68dac0d986	322	Set write protection CMD28 R1b x x
embeddedartists	0:6b68dac0d986	323	Clear write protection CMD29 R1b x x
embeddedartists	0:6b68dac0d986	324	Send write protection CMD30 R1 x x
embeddedartists	0:6b68dac0d986	325	Erase block start CMD32 R1 x
embeddedartists	0:6b68dac0d986	326	Erase block end CMD33 R1 x
embeddedartists	0:6b68dac0d986	327	Erase block start CMD35 R1 x
embeddedartists	0:6b68dac0d986	328	Erase block end CMD36 R1 x
embeddedartists	0:6b68dac0d986	329	Erase blocks CMD38 R1b x
embeddedartists	0:6b68dac0d986	330	Fast IO CMD39 R4 x
embeddedartists	0:6b68dac0d986	331	Go IRQ state CMD40 R5 x
embeddedartists	0:6b68dac0d986	332	Lock/unlock CMD42 R1b x
embeddedartists	0:6b68dac0d986	333	Application command CMD55 R1 x
embeddedartists	0:6b68dac0d986	334	General command CMD56 R1b x
embeddedartists	0:6b68dac0d986	335
embeddedartists	0:6b68dac0d986	336	* SD card application commands - these must be preceded with *
embeddedartists	0:6b68dac0d986	337	* MMC CMD55 application specific command first *
embeddedartists	0:6b68dac0d986	338	Set bus width ACMD6 R1 x
embeddedartists	0:6b68dac0d986	339	Send SD status ACMD13 R1 x
embeddedartists	0:6b68dac0d986	340	Send number WR blocks ACMD22 R1 x
embeddedartists	0:6b68dac0d986	341	Set WR block erase cnt ACMD23 R1 x
embeddedartists	0:6b68dac0d986	342	Send op condition ACMD41 R3 x
embeddedartists	0:6b68dac0d986	343	Set clear card detect ACMD42 R1 x
embeddedartists	0:6b68dac0d986	344	Send CSR ACMD51 R1 x */
embeddedartists	0:6b68dac0d986	345
embeddedartists	0:6b68dac0d986	346	/**
embeddedartists	0:6b68dac0d986	347	* @brief Possible SDMMC card state types
embeddedartists	0:6b68dac0d986	348	*/
embeddedartists	0:6b68dac0d986	349	typedef enum {
embeddedartists	0:6b68dac0d986	350	SDMMC_IDLE_ST = 0, /!< Idle state /
embeddedartists	0:6b68dac0d986	351	SDMMC_READY_ST, /!< Ready state /
embeddedartists	0:6b68dac0d986	352	SDMMC_IDENT_ST, /!< Identification State /
embeddedartists	0:6b68dac0d986	353	SDMMC_STBY_ST, /!< standby state /
embeddedartists	0:6b68dac0d986	354	SDMMC_TRAN_ST, /!< transfer state /
embeddedartists	0:6b68dac0d986	355	SDMMC_DATA_ST, /!< Sending-data State /
embeddedartists	0:6b68dac0d986	356	SDMMC_RCV_ST, /!< Receive-data State /
embeddedartists	0:6b68dac0d986	357	SDMMC_PRG_ST, /!< Programming State /
embeddedartists	0:6b68dac0d986	358	SDMMC_DIS_ST /!< Disconnect State /
embeddedartists	0:6b68dac0d986	359	} SDMMC_STATE_T;
embeddedartists	0:6b68dac0d986	360
embeddedartists	0:6b68dac0d986	361
embeddedartists	0:6b68dac0d986	362	/**
embeddedartists	0:6b68dac0d986	363	* @brief SD/MMC commands, arguments and responses
embeddedartists	0:6b68dac0d986	364	* Standard SD/MMC commands (3.1) type argument response
embeddedartists	0:6b68dac0d986	365	*/
embeddedartists	0:6b68dac0d986	366	/* class 1 */
embeddedartists	0:6b68dac0d986	367	#define MMC_GO_IDLE_STATE 0 /* bc */
embeddedartists	0:6b68dac0d986	368	#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
embeddedartists	0:6b68dac0d986	369	#define MMC_ALL_SEND_CID 2 /* bcr R2 */
embeddedartists	0:6b68dac0d986	370	#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
embeddedartists	0:6b68dac0d986	371	#define MMC_SET_DSR 4 /* bc [31:16] RCA */
embeddedartists	0:6b68dac0d986	372	#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
embeddedartists	0:6b68dac0d986	373	#define MMC_SEND_EXT_CSD 8 /* bc R1 */
embeddedartists	0:6b68dac0d986	374	#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
embeddedartists	0:6b68dac0d986	375	#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
embeddedartists	0:6b68dac0d986	376	#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
embeddedartists	0:6b68dac0d986	377	#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
embeddedartists	0:6b68dac0d986	378	#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
embeddedartists	0:6b68dac0d986	379
embeddedartists	0:6b68dac0d986	380	/* class 2 */
embeddedartists	0:6b68dac0d986	381	#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
embeddedartists	0:6b68dac0d986	382	#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	383	#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	384
embeddedartists	0:6b68dac0d986	385	/* class 3 */
embeddedartists	0:6b68dac0d986	386	#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	387
embeddedartists	0:6b68dac0d986	388	/* class 4 */
embeddedartists	0:6b68dac0d986	389	#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	390	#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	391	#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
embeddedartists	0:6b68dac0d986	392	#define MMC_PROGRAM_CID 26 /* adtc R1 */
embeddedartists	0:6b68dac0d986	393	#define MMC_PROGRAM_CSD 27 /* adtc R1 */
embeddedartists	0:6b68dac0d986	394
embeddedartists	0:6b68dac0d986	395	/* class 6 */
embeddedartists	0:6b68dac0d986	396	#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
embeddedartists	0:6b68dac0d986	397	#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
embeddedartists	0:6b68dac0d986	398	#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
embeddedartists	0:6b68dac0d986	399
embeddedartists	0:6b68dac0d986	400	/* class 5 */
embeddedartists	0:6b68dac0d986	401	#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	402	#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	403	#define MMC_ERASE 37 /* ac R1b */
embeddedartists	0:6b68dac0d986	404	#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	405	#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
embeddedartists	0:6b68dac0d986	406	#define SD_ERASE 38 /* ac R1b */
embeddedartists	0:6b68dac0d986	407
embeddedartists	0:6b68dac0d986	408	/* class 9 */
embeddedartists	0:6b68dac0d986	409	#define MMC_FAST_IO 39 /* ac <Complex> R4 */
embeddedartists	0:6b68dac0d986	410	#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
embeddedartists	0:6b68dac0d986	411
embeddedartists	0:6b68dac0d986	412	/* class 7 */
embeddedartists	0:6b68dac0d986	413	#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
embeddedartists	0:6b68dac0d986	414
embeddedartists	0:6b68dac0d986	415	/* class 8 */
embeddedartists	0:6b68dac0d986	416	#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
embeddedartists	0:6b68dac0d986	417	#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
embeddedartists	0:6b68dac0d986	418
embeddedartists	0:6b68dac0d986	419	/* SD commands type argument response */
embeddedartists	0:6b68dac0d986	420	/* class 8 */
embeddedartists	0:6b68dac0d986	421	/* This is basically the same command as for MMC with some quirks. */
embeddedartists	0:6b68dac0d986	422	#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */
embeddedartists	0:6b68dac0d986	423	#define SD_CMD8 8 /* bcr [31:0] OCR R3 */
embeddedartists	0:6b68dac0d986	424
embeddedartists	0:6b68dac0d986	425	/* Application commands */
embeddedartists	0:6b68dac0d986	426	#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
embeddedartists	0:6b68dac0d986	427	#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R1 (R4) */
embeddedartists	0:6b68dac0d986	428	#define SD_APP_SEND_SCR 51 /* adtc R1 */
embeddedartists	0:6b68dac0d986	429
embeddedartists	0:6b68dac0d986	430
embeddedartists	0:6b68dac0d986	431	/**
embeddedartists	0:6b68dac0d986	432	* @brief MMC status in R1<br>
embeddedartists	0:6b68dac0d986	433	* Type<br>
embeddedartists	0:6b68dac0d986	434	* e : error bit<br>
embeddedartists	0:6b68dac0d986	435	* s : status bit<br>
embeddedartists	0:6b68dac0d986	436	* r : detected and set for the actual command response<br>
embeddedartists	0:6b68dac0d986	437	* x : detected and set during command execution. the host must poll
embeddedartists	0:6b68dac0d986	438	* the card by sending status command in order to read these bits.
embeddedartists	0:6b68dac0d986	439	* Clear condition<br>
embeddedartists	0:6b68dac0d986	440	* a : according to the card state<br>
embeddedartists	0:6b68dac0d986	441	* b : always related to the previous command. Reception of
embeddedartists	0:6b68dac0d986	442	* a valid command will clear it (with a delay of one command)<br>
embeddedartists	0:6b68dac0d986	443	* c : clear by read<br>
embeddedartists	0:6b68dac0d986	444	*/
embeddedartists	0:6b68dac0d986	445
embeddedartists	0:6b68dac0d986	446	#define R1_OUT_OF_RANGE (1UL << 31) /* er, c */
embeddedartists	0:6b68dac0d986	447	#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
embeddedartists	0:6b68dac0d986	448	#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
embeddedartists	0:6b68dac0d986	449	#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
embeddedartists	0:6b68dac0d986	450	#define R1_ERASE_PARAM (1 << 27) /* ex, c */
embeddedartists	0:6b68dac0d986	451	#define R1_WP_VIOLATION (1 << 26) /* erx, c */
embeddedartists	0:6b68dac0d986	452	#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
embeddedartists	0:6b68dac0d986	453	#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
embeddedartists	0:6b68dac0d986	454	#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
embeddedartists	0:6b68dac0d986	455	#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
embeddedartists	0:6b68dac0d986	456	#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
embeddedartists	0:6b68dac0d986	457	#define R1_CC_ERROR (1 << 20) /* erx, c */
embeddedartists	0:6b68dac0d986	458	#define R1_ERROR (1 << 19) /* erx, c */
embeddedartists	0:6b68dac0d986	459	#define R1_UNDERRUN (1 << 18) /* ex, c */
embeddedartists	0:6b68dac0d986	460	#define R1_OVERRUN (1 << 17) /* ex, c */
embeddedartists	0:6b68dac0d986	461	#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
embeddedartists	0:6b68dac0d986	462	#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
embeddedartists	0:6b68dac0d986	463	#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
embeddedartists	0:6b68dac0d986	464	#define R1_ERASE_RESET (1 << 13) /* sr, c */
embeddedartists	0:6b68dac0d986	465	#define R1_STATUS(x) (x & 0xFFFFE000)
embeddedartists	0:6b68dac0d986	466	#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
embeddedartists	0:6b68dac0d986	467	#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
embeddedartists	0:6b68dac0d986	468	#define R1_APP_CMD (1 << 5) /* sr, c */
embeddedartists	0:6b68dac0d986	469
embeddedartists	0:6b68dac0d986	470
embeddedartists	0:6b68dac0d986	471	/**
embeddedartists	0:6b68dac0d986	472	* @brief SD/MMC card OCR register bits
embeddedartists	0:6b68dac0d986	473	*/
embeddedartists	0:6b68dac0d986	474	#define OCR_ALL_READY (1UL << 31) /* Card Power up status bit */
embeddedartists	0:6b68dac0d986	475	#define OCR_HC_CCS (1 << 30) /* High capacity card */
embeddedartists	0:6b68dac0d986	476	#define OCR_VOLTAGE_RANGE_MSK (0x00FF8000)
embeddedartists	0:6b68dac0d986	477
embeddedartists	0:6b68dac0d986	478	#define SD_SEND_IF_ARG 0x000001AA
embeddedartists	0:6b68dac0d986	479	#define SD_SEND_IF_ECHO_MSK 0x000000FF
embeddedartists	0:6b68dac0d986	480	#define SD_SEND_IF_RESP 0x000000AA
embeddedartists	0:6b68dac0d986	481
embeddedartists	0:6b68dac0d986	482	/**
embeddedartists	0:6b68dac0d986	483	* @brief R3 response definitions
embeddedartists	0:6b68dac0d986	484	*/
embeddedartists	0:6b68dac0d986	485	#define CMDRESP_R3_OCR_VAL(n) (((uint32_t) n) & 0xFFFFFF)
embeddedartists	0:6b68dac0d986	486	#define CMDRESP_R3_S18A (((uint32_t) 1 ) << 24)
embeddedartists	0:6b68dac0d986	487	#define CMDRESP_R3_HC_CCS (((uint32_t) 1 ) << 30)
embeddedartists	0:6b68dac0d986	488	#define CMDRESP_R3_INIT_COMPLETE (((uint32_t) 1 ) << 31)
embeddedartists	0:6b68dac0d986	489
embeddedartists	0:6b68dac0d986	490	/**
embeddedartists	0:6b68dac0d986	491	* @brief R6 response definitions
embeddedartists	0:6b68dac0d986	492	*/
embeddedartists	0:6b68dac0d986	493	#define CMDRESP_R6_RCA_VAL(n) (((uint32_t) (n >> 16)) & 0xFFFF)
embeddedartists	0:6b68dac0d986	494	#define CMDRESP_R6_CARD_STATUS(n) (((uint32_t) (n & 0x1FFF)) \| \
embeddedartists	0:6b68dac0d986	495	((n & (1 << 13)) ? (1 << 19) : 0) \| \
embeddedartists	0:6b68dac0d986	496	((n & (1 << 14)) ? (1 << 22) : 0) \| \
embeddedartists	0:6b68dac0d986	497	((n & (1 << 15)) ? (1 << 23) : 0))
embeddedartists	0:6b68dac0d986	498
embeddedartists	0:6b68dac0d986	499	/**
embeddedartists	0:6b68dac0d986	500	* @brief R7 response definitions
embeddedartists	0:6b68dac0d986	501	*/
embeddedartists	0:6b68dac0d986	502	/** Echo-back of check-pattern */
embeddedartists	0:6b68dac0d986	503	#define CMDRESP_R7_CHECK_PATTERN(n) (((uint32_t) n ) & 0xFF)
embeddedartists	0:6b68dac0d986	504	/** Voltage accepted */
embeddedartists	0:6b68dac0d986	505	#define CMDRESP_R7_VOLTAGE_ACCEPTED (((uint32_t) 1 ) << 8)
embeddedartists	0:6b68dac0d986	506
embeddedartists	0:6b68dac0d986	507	/**
embeddedartists	0:6b68dac0d986	508	* @brief CMD3 command definitions
embeddedartists	0:6b68dac0d986	509	*/
embeddedartists	0:6b68dac0d986	510	/** Card Address */
embeddedartists	0:6b68dac0d986	511	#define CMD3_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:6b68dac0d986	512
embeddedartists	0:6b68dac0d986	513	/**
embeddedartists	0:6b68dac0d986	514	* @brief CMD7 command definitions
embeddedartists	0:6b68dac0d986	515	*/
embeddedartists	0:6b68dac0d986	516	/** Card Address */
embeddedartists	0:6b68dac0d986	517	#define CMD7_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:6b68dac0d986	518
embeddedartists	0:6b68dac0d986	519	/**
embeddedartists	0:6b68dac0d986	520	* @brief CMD8 command definitions
embeddedartists	0:6b68dac0d986	521	*/
embeddedartists	0:6b68dac0d986	522	/** Check pattern */
embeddedartists	0:6b68dac0d986	523	#define CMD8_CHECKPATTERN(n) (((uint32_t) (n & 0xFF) ) << 0)
embeddedartists	0:6b68dac0d986	524	/** Recommended pattern */
embeddedartists	0:6b68dac0d986	525	#define CMD8_DEF_PATTERN (0xAA)
embeddedartists	0:6b68dac0d986	526	/** Voltage supplied.*/
embeddedartists	0:6b68dac0d986	527	#define CMD8_VOLTAGESUPPLIED_27_36 (((uint32_t) 1 ) << 8)
embeddedartists	0:6b68dac0d986	528
embeddedartists	0:6b68dac0d986	529	/**
embeddedartists	0:6b68dac0d986	530	* @brief CMD9 command definitions
embeddedartists	0:6b68dac0d986	531	*/
embeddedartists	0:6b68dac0d986	532	#define CMD9_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:6b68dac0d986	533
embeddedartists	0:6b68dac0d986	534	/**
embeddedartists	0:6b68dac0d986	535	* @brief CMD13 command definitions
embeddedartists	0:6b68dac0d986	536	*/
embeddedartists	0:6b68dac0d986	537	#define CMD13_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:6b68dac0d986	538
embeddedartists	0:6b68dac0d986	539	/**
embeddedartists	0:6b68dac0d986	540	* @brief APP_CMD command definitions
embeddedartists	0:6b68dac0d986	541	*/
embeddedartists	0:6b68dac0d986	542	#define CMD55_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:6b68dac0d986	543
embeddedartists	0:6b68dac0d986	544	/**
embeddedartists	0:6b68dac0d986	545	* @brief ACMD41 command definitions
embeddedartists	0:6b68dac0d986	546	*/
embeddedartists	0:6b68dac0d986	547	#define ACMD41_OCR(n) (((uint32_t) n) & 0xFFFFFF)
embeddedartists	0:6b68dac0d986	548	#define ACMD41_S18R (((uint32_t) 1 ) << 24)
embeddedartists	0:6b68dac0d986	549	#define ACMD41_XPC (((uint32_t) 1 ) << 28)
embeddedartists	0:6b68dac0d986	550	#define ACMD41_HCS (((uint32_t) 1 ) << 30)
embeddedartists	0:6b68dac0d986	551
embeddedartists	0:6b68dac0d986	552	/**
embeddedartists	0:6b68dac0d986	553	* @brief ACMD6 command definitions
embeddedartists	0:6b68dac0d986	554	*/
embeddedartists	0:6b68dac0d986	555	#define ACMD6_BUS_WIDTH(n) ((uint32_t) n & 0x03)
embeddedartists	0:6b68dac0d986	556	#define ACMD6_BUS_WIDTH_1 (0)
embeddedartists	0:6b68dac0d986	557	#define ACMD6_BUS_WIDTH_4 (2)
embeddedartists	0:6b68dac0d986	558
embeddedartists	0:6b68dac0d986	559	/** @brief Card type defines
embeddedartists	0:6b68dac0d986	560	*/
embeddedartists	0:6b68dac0d986	561	#define CARD_TYPE_SD (1 << 0)
embeddedartists	0:6b68dac0d986	562	#define CARD_TYPE_4BIT (1 << 1)
embeddedartists	0:6b68dac0d986	563	#define CARD_TYPE_8BIT (1 << 2)
embeddedartists	0:6b68dac0d986	564	#define CARD_TYPE_HC (OCR_HC_CCS)/!< high capacity card > 2GB /
embeddedartists	0:6b68dac0d986	565
embeddedartists	0:6b68dac0d986	566	/**
embeddedartists	0:6b68dac0d986	567	* @brief SD/MMC sector size in bytes
embeddedartists	0:6b68dac0d986	568	*/
embeddedartists	0:6b68dac0d986	569	#define MMC_SECTOR_SIZE 512
embeddedartists	0:6b68dac0d986	570
embeddedartists	0:6b68dac0d986	571	/******************************************************************************
embeddedartists	0:6b68dac0d986	572	* External global variables
embeddedartists	0:6b68dac0d986	573	*****************************************************************************/
embeddedartists	0:6b68dac0d986	574
embeddedartists	0:6b68dac0d986	575	/******************************************************************************
embeddedartists	0:6b68dac0d986	576	* Local variables
embeddedartists	0:6b68dac0d986	577	*****************************************************************************/
embeddedartists	0:6b68dac0d986	578
embeddedartists	0:6b68dac0d986	579	static MCIFileSystem* pUglyForIRQ = NULL;
embeddedartists	0:6b68dac0d986	580
embeddedartists	0:6b68dac0d986	581	/******************************************************************************
embeddedartists	0:6b68dac0d986	582	* Local Functions
embeddedartists	0:6b68dac0d986	583	*****************************************************************************/
embeddedartists	0:6b68dac0d986	584
embeddedartists	0:6b68dac0d986	585	static void mymciirq()
embeddedartists	0:6b68dac0d986	586	{
embeddedartists	0:6b68dac0d986	587	pUglyForIRQ->mci_MCIIRQHandler();
embeddedartists	0:6b68dac0d986	588	}
embeddedartists	0:6b68dac0d986	589
embeddedartists	0:6b68dac0d986	590	static void mydmairq()
embeddedartists	0:6b68dac0d986	591	{
embeddedartists	0:6b68dac0d986	592	pUglyForIRQ->mci_DMAIRQHandler();
embeddedartists	0:6b68dac0d986	593	}
embeddedartists	0:6b68dac0d986	594
embeddedartists	0:6b68dac0d986	595	/******************************************************************************
embeddedartists	0:6b68dac0d986	596	* Public Functions
embeddedartists	0:6b68dac0d986	597	*****************************************************************************/
embeddedartists	0:6b68dac0d986	598
embeddedartists	0:6b68dac0d986	599	MCIFileSystem::MCIFileSystem(const char* name, PinName cd) :
embeddedartists	0:6b68dac0d986	600	FATFileSystem(name)
embeddedartists	0:6b68dac0d986	601	{
embeddedartists	0:6b68dac0d986	602	pUglyForIRQ = this;
embeddedartists	0:6b68dac0d986	603
embeddedartists	0:6b68dac0d986	604	_Stat = STA_NOINIT;
embeddedartists	0:6b68dac0d986	605	memset(&_sdCardInfo, 0, sizeof(SDMMC_CARD_T));
embeddedartists	0:6b68dac0d986	606	_eventReceived = false;
embeddedartists	0:6b68dac0d986	607	_eventSuccess = false;
embeddedartists	0:6b68dac0d986	608
embeddedartists	0:6b68dac0d986	609	initMCI();
embeddedartists	0:6b68dac0d986	610
embeddedartists	0:6b68dac0d986	611	if (cd == NC)
embeddedartists	0:6b68dac0d986	612	{
embeddedartists	0:6b68dac0d986	613	_cardDetect = NULL;
embeddedartists	0:6b68dac0d986	614	}
embeddedartists	0:6b68dac0d986	615	else
embeddedartists	0:6b68dac0d986	616	{
embeddedartists	0:6b68dac0d986	617	_cardDetect = new DigitalIn(cd);
embeddedartists	0:6b68dac0d986	618	_cardDetect->mode(PullUp);
embeddedartists	0:6b68dac0d986	619	}
embeddedartists	0:6b68dac0d986	620	}
embeddedartists	0:6b68dac0d986	621
embeddedartists	0:6b68dac0d986	622	MCIFileSystem::~MCIFileSystem()
embeddedartists	0:6b68dac0d986	623	{
embeddedartists	0:6b68dac0d986	624	if (_cardDetect != NULL)
embeddedartists	0:6b68dac0d986	625	{
embeddedartists	0:6b68dac0d986	626	delete _cardDetect;
embeddedartists	0:6b68dac0d986	627	}
embeddedartists	0:6b68dac0d986	628	}
embeddedartists	0:6b68dac0d986	629	void MCIFileSystem::initMCI()
embeddedartists	0:6b68dac0d986	630	{
embeddedartists	0:6b68dac0d986	631	// Pinsel for MCI
embeddedartists	0:6b68dac0d986	632	LPC_IOCON->P1_2 = 2; /* SD_CLK @ P1.2 */
embeddedartists	0:6b68dac0d986	633	LPC_IOCON->P1_3 = 2; /* SD_CMD @ P1.3 */
embeddedartists	0:6b68dac0d986	634	LPC_IOCON->P1_5 = 2 \| (1<<7); /* SD_PWR @ P1.5 - digital mode */
embeddedartists	0:6b68dac0d986	635	LPC_IOCON->P1_6 = 2 \| (1<<7); /* SD_DAT[0] @ P1.6 - digital mode */
embeddedartists	0:6b68dac0d986	636	LPC_IOCON->P1_7 = 2 \| (1<<7); /* SD_DAT[1] @ P1.7 - digital mode */
embeddedartists	0:6b68dac0d986	637	LPC_IOCON->P1_11 = 2; /* SD_DAT[2] @ P1.11 */
embeddedartists	0:6b68dac0d986	638	LPC_IOCON->P1_12 = 2; /* SD_DAT[3] @ P1.12 */
embeddedartists	0:6b68dac0d986	639
embeddedartists	0:6b68dac0d986	640	LPC_SC->PCONP \|= SYSCTL_CLOCK_SDC;
embeddedartists	0:6b68dac0d986	641	LPC_SC->RSTCON0 = (1<<28);
embeddedartists	0:6b68dac0d986	642	LPC_SC->RSTCON0 &= ~(1<<28);
embeddedartists	0:6b68dac0d986	643
embeddedartists	0:6b68dac0d986	644	/* Initialize GPDMA controller */
embeddedartists	0:6b68dac0d986	645	gpdma_init();
embeddedartists	0:6b68dac0d986	646
embeddedartists	0:6b68dac0d986	647	/* Initialize SDC peripheral */
embeddedartists	0:6b68dac0d986	648	LPC_SC->PCONP \|= SYSCTL_CLOCK_SDC;
embeddedartists	0:6b68dac0d986	649
embeddedartists	0:6b68dac0d986	650	/* Disable SD_CLK */
embeddedartists	0:6b68dac0d986	651	mci_ClockControl(SDC_CLOCK_ENABLE, false);
embeddedartists	0:6b68dac0d986	652
embeddedartists	0:6b68dac0d986	653	/* Power-off */
embeddedartists	0:6b68dac0d986	654	mci_PowerControl(PowerOff, 0);
embeddedartists	0:6b68dac0d986	655	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	656
embeddedartists	0:6b68dac0d986	657	/* Disable all interrupts */
embeddedartists	0:6b68dac0d986	658	LPC_MCI->MASK0 = 0;
embeddedartists	0:6b68dac0d986	659
embeddedartists	0:6b68dac0d986	660	/Setting for timeout problem /
embeddedartists	0:6b68dac0d986	661	LPC_MCI->DATATMR = 0x1FFFFFFF;
embeddedartists	0:6b68dac0d986	662
embeddedartists	0:6b68dac0d986	663	LPC_MCI->COMMAND = 0;
embeddedartists	0:6b68dac0d986	664	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	665
embeddedartists	0:6b68dac0d986	666	LPC_MCI->DATACTRL = 0;
embeddedartists	0:6b68dac0d986	667	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	668
embeddedartists	0:6b68dac0d986	669	/* clear all pending interrupts */
embeddedartists	0:6b68dac0d986	670	LPC_MCI->CLEAR = SDC_CLEAR_ALL;
embeddedartists	0:6b68dac0d986	671
embeddedartists	0:6b68dac0d986	672	/* Power-up SDC Peripheral */
embeddedartists	0:6b68dac0d986	673	mci_PowerControl(PowerUp, 0);
embeddedartists	0:6b68dac0d986	674
embeddedartists	0:6b68dac0d986	675	/* delays for the supply output is stable*/
embeddedartists	0:6b68dac0d986	676	for (uint32_t i = 0; i < 0x80000; i++ ) {}
embeddedartists	0:6b68dac0d986	677
embeddedartists	0:6b68dac0d986	678	mci_SetClock(SDC_IDENT_CLOCK_RATE);
embeddedartists	0:6b68dac0d986	679	mci_ClockControl(SDC_CLOCK_ENABLE, true);
embeddedartists	0:6b68dac0d986	680
embeddedartists	0:6b68dac0d986	681	/* Power-on SDC Interface */
embeddedartists	0:6b68dac0d986	682	mci_PowerControl(PowerOn, 0);
embeddedartists	0:6b68dac0d986	683
embeddedartists	0:6b68dac0d986	684	NVIC_SetVector(MCI_IRQn, (uint32_t) mymciirq);
embeddedartists	0:6b68dac0d986	685	NVIC_EnableIRQ(MCI_IRQn);
embeddedartists	0:6b68dac0d986	686
embeddedartists	0:6b68dac0d986	687	NVIC_SetVector(DMA_IRQn, (uint32_t) mydmairq);
embeddedartists	0:6b68dac0d986	688	NVIC_EnableIRQ(DMA_IRQn);
embeddedartists	0:6b68dac0d986	689	}
embeddedartists	0:6b68dac0d986	690
embeddedartists	0:6b68dac0d986	691	int MCIFileSystem::disk_initialize() {
embeddedartists	0:6b68dac0d986	692
embeddedartists	0:6b68dac0d986	693	debug_if(MCI_DBG, "mcifs:disk_initialize(), _Stat = %#x\n", _Stat);
embeddedartists	0:6b68dac0d986	694
embeddedartists	0:6b68dac0d986	695	if (!cardInserted()) {
embeddedartists	0:6b68dac0d986	696	/* No card in the socket */
embeddedartists	0:6b68dac0d986	697	_Stat = STA_NODISK \| STA_NOINIT;
embeddedartists	0:6b68dac0d986	698	}
embeddedartists	0:6b68dac0d986	699
embeddedartists	0:6b68dac0d986	700	if (_Stat != STA_NOINIT) {
embeddedartists	0:6b68dac0d986	701	return _Stat; /* card is already enumerated */
embeddedartists	0:6b68dac0d986	702	}
embeddedartists	0:6b68dac0d986	703
embeddedartists	0:6b68dac0d986	704	//rtc_init();
embeddedartists	0:6b68dac0d986	705
embeddedartists	0:6b68dac0d986	706	/* Initialize the Card Data Strucutre */
embeddedartists	0:6b68dac0d986	707	memset(&_sdCardInfo, 0, sizeof(SDMMC_CARD_T));
embeddedartists	0:6b68dac0d986	708
embeddedartists	0:6b68dac0d986	709	/* Reset */
embeddedartists	0:6b68dac0d986	710	_Stat = STA_NOINIT;
embeddedartists	0:6b68dac0d986	711
embeddedartists	0:6b68dac0d986	712	/* Enumerate the card once detected. Note this function may block for a little while. */
embeddedartists	0:6b68dac0d986	713	int ret = mci_Acquire();
embeddedartists	0:6b68dac0d986	714	if (ret != 1) {
embeddedartists	0:6b68dac0d986	715	debug("Card Acquire failed... got %d, but expected 1\r\n", ret);
embeddedartists	0:6b68dac0d986	716	return 1;//Stat;
embeddedartists	0:6b68dac0d986	717	}
embeddedartists	0:6b68dac0d986	718
embeddedartists	0:6b68dac0d986	719	_Stat &= ~STA_NOINIT;
embeddedartists	0:6b68dac0d986	720	return _Stat;
embeddedartists	0:6b68dac0d986	721	}
embeddedartists	0:6b68dac0d986	722
embeddedartists	0:6b68dac0d986	723	int MCIFileSystem::disk_write(const uint8_t *buffer, uint64_t block_number, uint8_t count) {
embeddedartists	0:6b68dac0d986	724	debug_if(MCI_DBG, "mcifs:disk_write(%#x, %llu, %u), _Stat = %#x\n", (uint32_t)buffer, block_number, count, _Stat);
embeddedartists	0:6b68dac0d986	725	if (_Stat & STA_NOINIT) {
embeddedartists	0:6b68dac0d986	726	// not ready
embeddedartists	0:6b68dac0d986	727	return 1;
embeddedartists	0:6b68dac0d986	728	}
embeddedartists	0:6b68dac0d986	729	if (mci_WriteBlocks((void*)buffer, block_number, count) == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	730	return 0;
embeddedartists	0:6b68dac0d986	731	}
embeddedartists	0:6b68dac0d986	732
embeddedartists	0:6b68dac0d986	733	return 1;
embeddedartists	0:6b68dac0d986	734	}
embeddedartists	0:6b68dac0d986	735
embeddedartists	0:6b68dac0d986	736	int MCIFileSystem::disk_read(uint8_t *buffer, uint64_t block_number, uint8_t count) {
embeddedartists	0:6b68dac0d986	737	debug_if(MCI_DBG, "mcifs:disk_read(%#x, %llu, %u), _Stat = %#x\n", (uint32_t)buffer, block_number, count, _Stat);
embeddedartists	0:6b68dac0d986	738	if (_Stat & STA_NOINIT) {
embeddedartists	0:6b68dac0d986	739	// not ready
embeddedartists	0:6b68dac0d986	740	return _Stat;
embeddedartists	0:6b68dac0d986	741	}
embeddedartists	0:6b68dac0d986	742	if (mci_ReadBlocks(buffer, block_number, count) == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	743	return 0;
embeddedartists	0:6b68dac0d986	744	}
embeddedartists	0:6b68dac0d986	745
embeddedartists	0:6b68dac0d986	746	return 1;
embeddedartists	0:6b68dac0d986	747	}
embeddedartists	0:6b68dac0d986	748
embeddedartists	0:6b68dac0d986	749	int MCIFileSystem::disk_status()
embeddedartists	0:6b68dac0d986	750	{
embeddedartists	0:6b68dac0d986	751	debug_if(MCI_DBG, "mcifs:disk_status(), _Stat = %#x\n", _Stat);
embeddedartists	0:6b68dac0d986	752	return _Stat;
embeddedartists	0:6b68dac0d986	753	}
embeddedartists	0:6b68dac0d986	754
embeddedartists	0:6b68dac0d986	755	int MCIFileSystem::disk_sync()
embeddedartists	0:6b68dac0d986	756	{
embeddedartists	0:6b68dac0d986	757	debug_if(MCI_DBG, "mcifs:disk_sync(), _Stat = %#x\n", _Stat);
embeddedartists	0:6b68dac0d986	758	uint32_t end = us_ticker_read() + 50*1000; // 50ms
embeddedartists	0:6b68dac0d986	759	while (us_ticker_read() < end)
embeddedartists	0:6b68dac0d986	760	{
embeddedartists	0:6b68dac0d986	761	if (mci_GetCardStatus() & R1_READY_FOR_DATA)
embeddedartists	0:6b68dac0d986	762	{
embeddedartists	0:6b68dac0d986	763	// card is ready
embeddedartists	0:6b68dac0d986	764	return 0;
embeddedartists	0:6b68dac0d986	765	}
embeddedartists	0:6b68dac0d986	766	}
embeddedartists	0:6b68dac0d986	767	// timeout while waiting for card to get ready
embeddedartists	0:6b68dac0d986	768	return 1;
embeddedartists	0:6b68dac0d986	769	}
embeddedartists	0:6b68dac0d986	770
embeddedartists	0:6b68dac0d986	771	uint64_t MCIFileSystem::disk_sectors()
embeddedartists	0:6b68dac0d986	772	{
embeddedartists	0:6b68dac0d986	773	debug_if(MCI_DBG, "mcifs:disk_sectors(), _Stat = %#x, returning %llu\n", _Stat, _sdCardInfo.blocknr);
embeddedartists	0:6b68dac0d986	774	return _sdCardInfo.blocknr;
embeddedartists	0:6b68dac0d986	775	}
embeddedartists	0:6b68dac0d986	776
embeddedartists	0:6b68dac0d986	777	void MCIFileSystem::mci_MCIIRQHandler()
embeddedartists	0:6b68dac0d986	778	{
embeddedartists	0:6b68dac0d986	779	int32_t Ret;
embeddedartists	0:6b68dac0d986	780
embeddedartists	0:6b68dac0d986	781	Ret = mci_IRQHandler(NULL, 0, NULL, 0);
embeddedartists	0:6b68dac0d986	782	if(Ret < 0) {
embeddedartists	0:6b68dac0d986	783	_eventSuccess = false;
embeddedartists	0:6b68dac0d986	784	_eventReceived = true;
embeddedartists	0:6b68dac0d986	785	}
embeddedartists	0:6b68dac0d986	786	}
embeddedartists	0:6b68dac0d986	787
embeddedartists	0:6b68dac0d986	788	void MCIFileSystem::mci_DMAIRQHandler()
embeddedartists	0:6b68dac0d986	789	{
embeddedartists	0:6b68dac0d986	790	_eventSuccess = gpdma_interrupt(_eventDmaChannel);
embeddedartists	0:6b68dac0d986	791	_eventReceived = true;
embeddedartists	0:6b68dac0d986	792	NVIC_DisableIRQ(DMA_IRQn);
embeddedartists	0:6b68dac0d986	793	}
embeddedartists	0:6b68dac0d986	794
embeddedartists	0:6b68dac0d986	795	/******************************************************************************
embeddedartists	0:6b68dac0d986	796	* Private Functions
embeddedartists	0:6b68dac0d986	797	*****************************************************************************/
embeddedartists	0:6b68dac0d986	798
embeddedartists	0:6b68dac0d986	799	bool MCIFileSystem::cardInserted() const
embeddedartists	0:6b68dac0d986	800	{
embeddedartists	0:6b68dac0d986	801	// If no card detect pin is given, then assume that a card is inserted.
embeddedartists	0:6b68dac0d986	802	// If a pin is specified then use that to determing the presence of a card.
embeddedartists	0:6b68dac0d986	803	return ((_cardDetect == NULL) \|\| (_cardDetect->read() == 0));
embeddedartists	0:6b68dac0d986	804	}
embeddedartists	0:6b68dac0d986	805
embeddedartists	0:6b68dac0d986	806
embeddedartists	0:6b68dac0d986	807
embeddedartists	0:6b68dac0d986	808	int32_t MCIFileSystem::mci_Acquire()
embeddedartists	0:6b68dac0d986	809	{
embeddedartists	0:6b68dac0d986	810	int32_t Ret;
embeddedartists	0:6b68dac0d986	811
embeddedartists	0:6b68dac0d986	812	/* Initialize card info */
embeddedartists	0:6b68dac0d986	813	_sdCardInfo.speed = SDC_TRAN_CLOCK_RATE;
embeddedartists	0:6b68dac0d986	814	_sdCardInfo.card_type = 0;
embeddedartists	0:6b68dac0d986	815
embeddedartists	0:6b68dac0d986	816	/* During identification phase, the clock should be less than
embeddedartists	0:6b68dac0d986	817	400Khz. Once we pass this phase, the normal clock can be set up
embeddedartists	0:6b68dac0d986	818	to 25Mhz on SD card and 20Mhz on MMC card. */
embeddedartists	0:6b68dac0d986	819	mci_SetClock(SDC_IDENT_CLOCK_RATE);
embeddedartists	0:6b68dac0d986	820
embeddedartists	0:6b68dac0d986	821	/* Clear Open Drain output control for SD */
embeddedartists	0:6b68dac0d986	822	mci_PowerControl(PowerOn, 0);
embeddedartists	0:6b68dac0d986	823
embeddedartists	0:6b68dac0d986	824	/* Card Reset */
embeddedartists	0:6b68dac0d986	825	Ret = mci_ExecuteCmd(SD_GO_IDLE_STATE, 0, NULL);
embeddedartists	0:6b68dac0d986	826	if (Ret != 0) {
embeddedartists	0:6b68dac0d986	827	return Ret;
embeddedartists	0:6b68dac0d986	828	}
embeddedartists	0:6b68dac0d986	829
embeddedartists	0:6b68dac0d986	830	wait(ACQUIRE_DELAY);
embeddedartists	0:6b68dac0d986	831
embeddedartists	0:6b68dac0d986	832	/* Send interface operation condiftion */
embeddedartists	0:6b68dac0d986	833	Ret = mci_SendIfCond();
embeddedartists	0:6b68dac0d986	834	if (Ret == SDC_RET_BAD_PARAMETERS) {
embeddedartists	0:6b68dac0d986	835	return Ret; /* Non-compatible voltage range or check pattern is not correct */
embeddedartists	0:6b68dac0d986	836
embeddedartists	0:6b68dac0d986	837	}
embeddedartists	0:6b68dac0d986	838	/* Get Card Type */
embeddedartists	0:6b68dac0d986	839	if (Ret == SDC_RET_OK) {/* Ver2.00 or later SD Memory Card*/
embeddedartists	0:6b68dac0d986	840	bool CCS;
embeddedartists	0:6b68dac0d986	841	uint32_t OCR = SDC_OCR_27_36;
embeddedartists	0:6b68dac0d986	842	_sdCardInfo.card_type \|= CARD_TYPE_SD;
embeddedartists	0:6b68dac0d986	843	Ret = mci_SendAppOpCond(0, true, &OCR, &CCS);
embeddedartists	0:6b68dac0d986	844	if (CCS) { /* High Capacity or Extended Capacity SD Memory Card */
embeddedartists	0:6b68dac0d986	845	_sdCardInfo.card_type \|= CARD_TYPE_HC;
embeddedartists	0:6b68dac0d986	846	}
embeddedartists	0:6b68dac0d986	847	}
embeddedartists	0:6b68dac0d986	848	else { /*Ver2.00 or later SD Memory Card(voltage mismatch) or Ver1.X SD Memory Card
embeddedartists	0:6b68dac0d986	849	or not SD Memory Card*/
embeddedartists	0:6b68dac0d986	850	bool CCS;
embeddedartists	0:6b68dac0d986	851	uint32_t OCR = SDC_OCR_27_36;
embeddedartists	0:6b68dac0d986	852	Ret = mci_SendAppOpCond(0, false, &OCR, &CCS);
embeddedartists	0:6b68dac0d986	853	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	854	_sdCardInfo.card_type \|= CARD_TYPE_SD;
embeddedartists	0:6b68dac0d986	855	}
embeddedartists	0:6b68dac0d986	856	else if (Ret == SDC_RET_BAD_PARAMETERS) {
embeddedartists	0:6b68dac0d986	857	return Ret;
embeddedartists	0:6b68dac0d986	858	}
embeddedartists	0:6b68dac0d986	859	else { /* MMC Card setup */
embeddedartists	0:6b68dac0d986	860	uint32_t OCR;
embeddedartists	0:6b68dac0d986	861	/* Enter to Open Drain mode */
embeddedartists	0:6b68dac0d986	862	mci_PowerControl(PowerOn, SDC_PWR_OPENDRAIN);
embeddedartists	0:6b68dac0d986	863	wait(ACQUIRE_DELAY);
embeddedartists	0:6b68dac0d986	864	Ret = mci_SendOpCond(&OCR);
embeddedartists	0:6b68dac0d986	865	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	866	return Ret;
embeddedartists	0:6b68dac0d986	867	}
embeddedartists	0:6b68dac0d986	868
embeddedartists	0:6b68dac0d986	869	}
embeddedartists	0:6b68dac0d986	870	}
embeddedartists	0:6b68dac0d986	871
embeddedartists	0:6b68dac0d986	872	/* Read CID */
embeddedartists	0:6b68dac0d986	873	mci_GetCID(_sdCardInfo.cid);
embeddedartists	0:6b68dac0d986	874
embeddedartists	0:6b68dac0d986	875	/* RCA send, for SD get RCA */
embeddedartists	0:6b68dac0d986	876	if (_sdCardInfo.card_type & CARD_TYPE_SD) {
embeddedartists	0:6b68dac0d986	877	mci_GetAddr(&_sdCardInfo.rca);
embeddedartists	0:6b68dac0d986	878	}
embeddedartists	0:6b68dac0d986	879	else {
embeddedartists	0:6b68dac0d986	880	_sdCardInfo.rca = 1;
embeddedartists	0:6b68dac0d986	881	mci_SetAddr(_sdCardInfo.rca);
embeddedartists	0:6b68dac0d986	882	mci_PowerControl(PowerOn, 0); /* enter to push-pull mode */
embeddedartists	0:6b68dac0d986	883	}
embeddedartists	0:6b68dac0d986	884
embeddedartists	0:6b68dac0d986	885	/* Get CSD */
embeddedartists	0:6b68dac0d986	886	mci_GetCSD(_sdCardInfo.rca, _sdCardInfo.csd);
embeddedartists	0:6b68dac0d986	887
embeddedartists	0:6b68dac0d986	888	/* Compute card size, block size and no. of blocks based on CSD response recived. */
embeddedartists	0:6b68dac0d986	889	if (_sdCardInfo.cid[0]) {
embeddedartists	0:6b68dac0d986	890	mci_ProcessCSD();
embeddedartists	0:6b68dac0d986	891
embeddedartists	0:6b68dac0d986	892	if (mci_SetTranState(_sdCardInfo.rca) != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	893	return 0;
embeddedartists	0:6b68dac0d986	894	}
embeddedartists	0:6b68dac0d986	895
embeddedartists	0:6b68dac0d986	896	if (mci_GetCardState() != SDMMC_TRAN_ST) {
embeddedartists	0:6b68dac0d986	897	return 0;
embeddedartists	0:6b68dac0d986	898	}
embeddedartists	0:6b68dac0d986	899
embeddedartists	0:6b68dac0d986	900	if (mci_SetCardParams() != 0) {
embeddedartists	0:6b68dac0d986	901	return 0;
embeddedartists	0:6b68dac0d986	902	}
embeddedartists	0:6b68dac0d986	903	}
embeddedartists	0:6b68dac0d986	904
embeddedartists	0:6b68dac0d986	905	return (_sdCardInfo.cid[0]) ? 1 : 0;
embeddedartists	0:6b68dac0d986	906	}
embeddedartists	0:6b68dac0d986	907
embeddedartists	0:6b68dac0d986	908	uint32_t MCIFileSystem::mci_GetCardStatus() const
embeddedartists	0:6b68dac0d986	909	{
embeddedartists	0:6b68dac0d986	910	uint32_t Status;
embeddedartists	0:6b68dac0d986	911	mci_GetStatus(_sdCardInfo.rca, &Status);
embeddedartists	0:6b68dac0d986	912	return Status;
embeddedartists	0:6b68dac0d986	913	}
embeddedartists	0:6b68dac0d986	914
embeddedartists	0:6b68dac0d986	915	MCIFileSystem::CardState MCIFileSystem::mci_GetCardState() const
embeddedartists	0:6b68dac0d986	916	{
embeddedartists	0:6b68dac0d986	917	uint32_t Status;
embeddedartists	0:6b68dac0d986	918	volatile int32_t Ret;
embeddedartists	0:6b68dac0d986	919
embeddedartists	0:6b68dac0d986	920	/* get current state of the card */
embeddedartists	0:6b68dac0d986	921	Ret = mci_GetStatus(_sdCardInfo.rca, &Status);
embeddedartists	0:6b68dac0d986	922
embeddedartists	0:6b68dac0d986	923	/* check card state in response */
embeddedartists	0:6b68dac0d986	924	return (CardState) R1_CURRENT_STATE(Status);
embeddedartists	0:6b68dac0d986	925	}
embeddedartists	0:6b68dac0d986	926
embeddedartists	0:6b68dac0d986	927	MCIFileSystem::ReturnCode MCIFileSystem::mci_StopTransmission(uint32_t rca) const
embeddedartists	0:6b68dac0d986	928	{
embeddedartists	0:6b68dac0d986	929	uint32_t Status;
embeddedartists	0:6b68dac0d986	930	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	931	response_t Response;
embeddedartists	0:6b68dac0d986	932	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	933
embeddedartists	0:6b68dac0d986	934	Ret = mci_GetStatus(rca, &Status);
embeddedartists	0:6b68dac0d986	935	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	936	return SDC_RET_ERR_STATE;
embeddedartists	0:6b68dac0d986	937	}
embeddedartists	0:6b68dac0d986	938
embeddedartists	0:6b68dac0d986	939	if (R1_CURRENT_STATE(Status) == SDMMC_TRAN_ST) {
embeddedartists	0:6b68dac0d986	940	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	941	}
embeddedartists	0:6b68dac0d986	942
embeddedartists	0:6b68dac0d986	943	if ((R1_CURRENT_STATE(Status) != SDMMC_DATA_ST) &&
embeddedartists	0:6b68dac0d986	944	(R1_CURRENT_STATE(Status) != SDMMC_RCV_ST)) {
embeddedartists	0:6b68dac0d986	945	return SDC_RET_ERR_STATE;
embeddedartists	0:6b68dac0d986	946	}
embeddedartists	0:6b68dac0d986	947
embeddedartists	0:6b68dac0d986	948	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	949	Ret = mci_ExecuteCmd(SD_CMD12_STOP_TRANSMISSION, 0, &Response);
embeddedartists	0:6b68dac0d986	950	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	951	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	952	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	953	return Ret;
embeddedartists	0:6b68dac0d986	954	}
embeddedartists	0:6b68dac0d986	955	Ret = mci_GetStatus(rca, &Status);
embeddedartists	0:6b68dac0d986	956	if ((R1_CURRENT_STATE(Status) == SDMMC_TRAN_ST) \|\| (R1_CURRENT_STATE(Status) == SDMMC_PRG_ST)) {
embeddedartists	0:6b68dac0d986	957	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	958	}
embeddedartists	0:6b68dac0d986	959	return SDC_RET_ERR_STATE;
embeddedartists	0:6b68dac0d986	960	}
embeddedartists	0:6b68dac0d986	961	}
embeddedartists	0:6b68dac0d986	962	RetryCnt--;
embeddedartists	0:6b68dac0d986	963	}
embeddedartists	0:6b68dac0d986	964	return Ret;
embeddedartists	0:6b68dac0d986	965	}
embeddedartists	0:6b68dac0d986	966
embeddedartists	0:6b68dac0d986	967	MCIFileSystem::ReturnCode MCIFileSystem::mci_ReadBlocks(void *buffer, int32_t startBlock, int32_t blockNum)
embeddedartists	0:6b68dac0d986	968	{
embeddedartists	0:6b68dac0d986	969	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	970	uint8_t dmaChannel;
embeddedartists	0:6b68dac0d986	971	int32_t ByteNum = blockNum * MMC_SECTOR_SIZE;
embeddedartists	0:6b68dac0d986	972
embeddedartists	0:6b68dac0d986	973	do
embeddedartists	0:6b68dac0d986	974	{
embeddedartists	0:6b68dac0d986	975	/* if card is not acquired return immediately */
embeddedartists	0:6b68dac0d986	976	if (( startBlock < 0) \|\| ( (startBlock + blockNum) > _sdCardInfo.blocknr) ) {
embeddedartists	0:6b68dac0d986	977	Ret = SDC_RET_NOT_READY;
embeddedartists	0:6b68dac0d986	978	break;
embeddedartists	0:6b68dac0d986	979	}
embeddedartists	0:6b68dac0d986	980
embeddedartists	0:6b68dac0d986	981	/* Put to tran state */
embeddedartists	0:6b68dac0d986	982	Ret = mci_SetTranState(_sdCardInfo.rca);
embeddedartists	0:6b68dac0d986	983	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	984	break;
embeddedartists	0:6b68dac0d986	985	}
embeddedartists	0:6b68dac0d986	986
embeddedartists	0:6b68dac0d986	987	LPC_MCI->MASK0 = SDC_MASK0_DATA \| SDC_MASK0_RXDATAERR;
embeddedartists	0:6b68dac0d986	988
embeddedartists	0:6b68dac0d986	989	/* DMA Setup */
embeddedartists	0:6b68dac0d986	990	gpdma_getFreeChannel(&dmaChannel);
embeddedartists	0:6b68dac0d986	991	gpdma_transfer_from_mci(dmaChannel, (uint32_t)buffer, ByteNum);
embeddedartists	0:6b68dac0d986	992	mci_SetupEventWakeup(dmaChannel);
embeddedartists	0:6b68dac0d986	993
embeddedartists	0:6b68dac0d986	994	/* set transfer information */
embeddedartists	0:6b68dac0d986	995	mci_SetDataTransfer(blockNum, true, DATA_TIMER_VALUE_R);
embeddedartists	0:6b68dac0d986	996
embeddedartists	0:6b68dac0d986	997	Ret = _readBlocks(_sdCardInfo.card_type, startBlock, blockNum);
embeddedartists	0:6b68dac0d986	998	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	999	/* Wait for transfer Finish */
embeddedartists	0:6b68dac0d986	1000	if (mci_WaitForEvent() != 0) {
embeddedartists	0:6b68dac0d986	1001	Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1002	}
embeddedartists	0:6b68dac0d986	1003	} else {
embeddedartists	0:6b68dac0d986	1004	Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1005	}
embeddedartists	0:6b68dac0d986	1006
embeddedartists	0:6b68dac0d986	1007	gpdma_stop(dmaChannel);
embeddedartists	0:6b68dac0d986	1008
embeddedartists	0:6b68dac0d986	1009	if ((blockNum > 1) \|\| (mci_GetCardState() == SDMMC_DATA_ST)) {
embeddedartists	0:6b68dac0d986	1010	/* Send Stop transmission command */
embeddedartists	0:6b68dac0d986	1011	mci_StopTransmission(_sdCardInfo.rca);
embeddedartists	0:6b68dac0d986	1012	}
embeddedartists	0:6b68dac0d986	1013
embeddedartists	0:6b68dac0d986	1014	/* Wait for card to enter tran state */
embeddedartists	0:6b68dac0d986	1015	while (mci_GetCardState() != SDMMC_TRAN_ST) {}
embeddedartists	0:6b68dac0d986	1016
embeddedartists	0:6b68dac0d986	1017	} while(false);
embeddedartists	0:6b68dac0d986	1018
embeddedartists	0:6b68dac0d986	1019	return Ret;
embeddedartists	0:6b68dac0d986	1020	}
embeddedartists	0:6b68dac0d986	1021
embeddedartists	0:6b68dac0d986	1022	MCIFileSystem::ReturnCode MCIFileSystem::mci_WriteBlocks(void *buffer, int32_t startBlock, int32_t blockNum)
embeddedartists	0:6b68dac0d986	1023	{
embeddedartists	0:6b68dac0d986	1024	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1025	uint8_t dmaChannel;
embeddedartists	0:6b68dac0d986	1026
embeddedartists	0:6b68dac0d986	1027	do
embeddedartists	0:6b68dac0d986	1028	{
embeddedartists	0:6b68dac0d986	1029	/* if card is not acquired return immediately */
embeddedartists	0:6b68dac0d986	1030	if (( startBlock < 0) \|\| ( (startBlock + blockNum) > _sdCardInfo.blocknr) ) {
embeddedartists	0:6b68dac0d986	1031	Ret = SDC_RET_NOT_READY;
embeddedartists	0:6b68dac0d986	1032	break;
embeddedartists	0:6b68dac0d986	1033	}
embeddedartists	0:6b68dac0d986	1034
embeddedartists	0:6b68dac0d986	1035	/* Put to tran state */
embeddedartists	0:6b68dac0d986	1036	Ret = mci_SetTranState(_sdCardInfo.rca);
embeddedartists	0:6b68dac0d986	1037	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1038	break;
embeddedartists	0:6b68dac0d986	1039	}
embeddedartists	0:6b68dac0d986	1040
embeddedartists	0:6b68dac0d986	1041	Ret = _writeBlocks(_sdCardInfo.card_type, startBlock, blockNum);
embeddedartists	0:6b68dac0d986	1042	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1043	break;
embeddedartists	0:6b68dac0d986	1044	}
embeddedartists	0:6b68dac0d986	1045
embeddedartists	0:6b68dac0d986	1046	/Wait for card enter to rcv state/
embeddedartists	0:6b68dac0d986	1047	while (mci_GetCardState() != SDMMC_RCV_ST) {}
embeddedartists	0:6b68dac0d986	1048
embeddedartists	0:6b68dac0d986	1049	LPC_MCI->MASK0 = SDC_MASK0_DATA \| SDC_MASK0_TXDATAERR;
embeddedartists	0:6b68dac0d986	1050
embeddedartists	0:6b68dac0d986	1051	/* DMA Setup */
embeddedartists	0:6b68dac0d986	1052	gpdma_getFreeChannel(&dmaChannel);
embeddedartists	0:6b68dac0d986	1053	gpdma_transfer_to_mci(dmaChannel, (uint32_t)buffer, blockNum*MMC_SECTOR_SIZE);
embeddedartists	0:6b68dac0d986	1054	mci_SetupEventWakeup(dmaChannel);
embeddedartists	0:6b68dac0d986	1055
embeddedartists	0:6b68dac0d986	1056	/* set transfer information */
embeddedartists	0:6b68dac0d986	1057	mci_SetDataTransfer(blockNum, false, DATA_TIMER_VALUE_W);
embeddedartists	0:6b68dac0d986	1058
embeddedartists	0:6b68dac0d986	1059	/* Wait for transfer done */
embeddedartists	0:6b68dac0d986	1060	if (mci_WaitForEvent() != 0) {
embeddedartists	0:6b68dac0d986	1061	Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1062	}
embeddedartists	0:6b68dac0d986	1063	gpdma_stop(dmaChannel);
embeddedartists	0:6b68dac0d986	1064
embeddedartists	0:6b68dac0d986	1065	if ((blockNum > 1) \|\| (mci_GetCardState() == SDMMC_RCV_ST)) {
embeddedartists	0:6b68dac0d986	1066	/* Send Stop transmission command */
embeddedartists	0:6b68dac0d986	1067	mci_StopTransmission(_sdCardInfo.rca);
embeddedartists	0:6b68dac0d986	1068	}
embeddedartists	0:6b68dac0d986	1069
embeddedartists	0:6b68dac0d986	1070	/* Wait for card to enter tran state */
embeddedartists	0:6b68dac0d986	1071	while (mci_GetCardState() != SDMMC_TRAN_ST) {}
embeddedartists	0:6b68dac0d986	1072
embeddedartists	0:6b68dac0d986	1073	} while (false);
embeddedartists	0:6b68dac0d986	1074
embeddedartists	0:6b68dac0d986	1075	return Ret;
embeddedartists	0:6b68dac0d986	1076	}
embeddedartists	0:6b68dac0d986	1077
embeddedartists	0:6b68dac0d986	1078	void MCIFileSystem::mci_SetClock(uint32_t freq) const
embeddedartists	0:6b68dac0d986	1079	{
embeddedartists	0:6b68dac0d986	1080	uint32_t PClk;
embeddedartists	0:6b68dac0d986	1081	uint32_t ClkValue = 0;
embeddedartists	0:6b68dac0d986	1082
embeddedartists	0:6b68dac0d986	1083	PClk = PeripheralClock;
embeddedartists	0:6b68dac0d986	1084
embeddedartists	0:6b68dac0d986	1085	ClkValue = (PClk + 2 * freq - 1) / (2 * freq);
embeddedartists	0:6b68dac0d986	1086	if (ClkValue > 0) {
embeddedartists	0:6b68dac0d986	1087	ClkValue -= 1;
embeddedartists	0:6b68dac0d986	1088	}
embeddedartists	0:6b68dac0d986	1089	uint32_t temp;
embeddedartists	0:6b68dac0d986	1090	temp = (LPC_MCI->CLOCK & (~SDC_CLOCK_CLKDIV_BITMASK));
embeddedartists	0:6b68dac0d986	1091	LPC_MCI->CLOCK = temp \| (SDC_CLOCK_CLKDIV(ClkValue));
embeddedartists	0:6b68dac0d986	1092	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	1093	}
embeddedartists	0:6b68dac0d986	1094
embeddedartists	0:6b68dac0d986	1095	void MCIFileSystem::mci_ClockControl(ClockControl ctrlType, bool enable) const
embeddedartists	0:6b68dac0d986	1096	{
embeddedartists	0:6b68dac0d986	1097	if (enable) {
embeddedartists	0:6b68dac0d986	1098	LPC_MCI->CLOCK \|= (1 << ctrlType);
embeddedartists	0:6b68dac0d986	1099	}
embeddedartists	0:6b68dac0d986	1100	else {
embeddedartists	0:6b68dac0d986	1101	LPC_MCI->CLOCK &= (~(1 << ctrlType));
embeddedartists	0:6b68dac0d986	1102	}
embeddedartists	0:6b68dac0d986	1103	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	1104	}
embeddedartists	0:6b68dac0d986	1105
embeddedartists	0:6b68dac0d986	1106	void MCIFileSystem::mci_PowerControl(power_ctrl_t powerMode, uint32_t flag) const
embeddedartists	0:6b68dac0d986	1107	{
embeddedartists	0:6b68dac0d986	1108	LPC_MCI->POWER = (powerMode & 0x3) \| flag;
embeddedartists	0:6b68dac0d986	1109	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	1110	}
embeddedartists	0:6b68dac0d986	1111
embeddedartists	0:6b68dac0d986	1112	MCIFileSystem::ReturnCode MCIFileSystem::mci_ExecuteCmd(uint32_t Command, uint32_t Arg, response_t* pResp) const
embeddedartists	0:6b68dac0d986	1113	{
embeddedartists	0:6b68dac0d986	1114	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1115
embeddedartists	0:6b68dac0d986	1116	/* Send Command to card */
embeddedartists	0:6b68dac0d986	1117	Ret = mci_SendCmd(Command, Arg, CMD_TIMEOUT);
embeddedartists	0:6b68dac0d986	1118	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1119	return Ret;
embeddedartists	0:6b68dac0d986	1120	}
embeddedartists	0:6b68dac0d986	1121
embeddedartists	0:6b68dac0d986	1122	/* Get response (if any) */
embeddedartists	0:6b68dac0d986	1123	if ((Command & SDC_COMMAND_RSP_BITMASK) != SDC_COMMAND_NO_RSP) {
embeddedartists	0:6b68dac0d986	1124
embeddedartists	0:6b68dac0d986	1125	mci_GetResp(pResp);
embeddedartists	0:6b68dac0d986	1126
embeddedartists	0:6b68dac0d986	1127	/* If the response is not R1, in the response field, the Expected Cmd data
embeddedartists	0:6b68dac0d986	1128	won't be the same as the CMD data in SendCmd(). Below four cmds have
embeddedartists	0:6b68dac0d986	1129	R2 or R3 response. We don't need to check if MCI_RESP_CMD is the same
embeddedartists	0:6b68dac0d986	1130	as the Expected or not. */
embeddedartists	0:6b68dac0d986	1131	if ((SDC_COMMAND_INDEX(Command) != MMC_SEND_OP_COND) &&
embeddedartists	0:6b68dac0d986	1132	(SDC_COMMAND_INDEX(Command) != SD_APP_OP_COND) &&
embeddedartists	0:6b68dac0d986	1133	(SDC_COMMAND_INDEX(Command) != MMC_ALL_SEND_CID) &&
embeddedartists	0:6b68dac0d986	1134	(SDC_COMMAND_INDEX(Command) != MMC_SEND_CSD) &&
embeddedartists	0:6b68dac0d986	1135	(pResp->CmdIndex != SDC_COMMAND_INDEX(Command))) {
embeddedartists	0:6b68dac0d986	1136	return SDC_RET_CMD_FAILED;
embeddedartists	0:6b68dac0d986	1137	}
embeddedartists	0:6b68dac0d986	1138	}
embeddedartists	0:6b68dac0d986	1139
embeddedartists	0:6b68dac0d986	1140	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1141	}
embeddedartists	0:6b68dac0d986	1142
embeddedartists	0:6b68dac0d986	1143	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendIfCond() const
embeddedartists	0:6b68dac0d986	1144	{
embeddedartists	0:6b68dac0d986	1145	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1146	response_t Response;
embeddedartists	0:6b68dac0d986	1147	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1148
embeddedartists	0:6b68dac0d986	1149	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1150	Ret = mci_ExecuteCmd(SD_CMD8_SEND_IF_COND, (CMD8_VOLTAGESUPPLIED_27_36 \| CMD8_CHECKPATTERN(
embeddedartists	0:6b68dac0d986	1151	CMD8_DEF_PATTERN)), &Response);
embeddedartists	0:6b68dac0d986	1152	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1153	if ((Response.Data[0] & CMDRESP_R7_VOLTAGE_ACCEPTED) &&
embeddedartists	0:6b68dac0d986	1154	(CMDRESP_R7_CHECK_PATTERN(Response.Data[0]) == CMD8_DEF_PATTERN)) {
embeddedartists	0:6b68dac0d986	1155	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1156	}
embeddedartists	0:6b68dac0d986	1157	return SDC_RET_BAD_PARAMETERS;
embeddedartists	0:6b68dac0d986	1158	}
embeddedartists	0:6b68dac0d986	1159	RetryCnt--;
embeddedartists	0:6b68dac0d986	1160	}
embeddedartists	0:6b68dac0d986	1161	return Ret;
embeddedartists	0:6b68dac0d986	1162	}
embeddedartists	0:6b68dac0d986	1163
embeddedartists	0:6b68dac0d986	1164	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendOpCond(uint32_t *pOCR) const
embeddedartists	0:6b68dac0d986	1165	{
embeddedartists	0:6b68dac0d986	1166	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1167	response_t Response;
embeddedartists	0:6b68dac0d986	1168	uint32_t RetryCnt = 0x200;
embeddedartists	0:6b68dac0d986	1169
embeddedartists	0:6b68dac0d986	1170	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1171	Ret = mci_ExecuteCmd(SD_CMD1_SEND_OP_COND, SDC_OCR_27_36, &Response);
embeddedartists	0:6b68dac0d986	1172	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1173	*pOCR = Response.Data[0];
embeddedartists	0:6b68dac0d986	1174	if (*pOCR & SDC_OCR_IDLE) {
embeddedartists	0:6b68dac0d986	1175	if ((Response.Data[0] & SDC_OCR_27_36) != SDC_OCR_27_36) {
embeddedartists	0:6b68dac0d986	1176	return SDC_RET_BAD_PARAMETERS;
embeddedartists	0:6b68dac0d986	1177	}
embeddedartists	0:6b68dac0d986	1178	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1179	}
embeddedartists	0:6b68dac0d986	1180	}
embeddedartists	0:6b68dac0d986	1181	RetryCnt--;
embeddedartists	0:6b68dac0d986	1182	}
embeddedartists	0:6b68dac0d986	1183	return SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1184	}
embeddedartists	0:6b68dac0d986	1185
embeddedartists	0:6b68dac0d986	1186	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendAppOpCond(uint16_t rca, bool hcs, uint32_t pOcr, bool pCCS) const
embeddedartists	0:6b68dac0d986	1187	{
embeddedartists	0:6b68dac0d986	1188	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1189	response_t Response;
embeddedartists	0:6b68dac0d986	1190	uint32_t Argument;
embeddedartists	0:6b68dac0d986	1191	uint32_t RetryCnt = 0x2000; /* The host repeatedly issues ACMD41 for at least 1 second or
embeddedartists	0:6b68dac0d986	1192	until the busy bit are set to 1 */
embeddedartists	0:6b68dac0d986	1193
embeddedartists	0:6b68dac0d986	1194	Argument = ACMD41_OCR(*pOcr);
embeddedartists	0:6b68dac0d986	1195	if (hcs) {
embeddedartists	0:6b68dac0d986	1196	Argument \|= ACMD41_HCS;
embeddedartists	0:6b68dac0d986	1197	}
embeddedartists	0:6b68dac0d986	1198
embeddedartists	0:6b68dac0d986	1199	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1200	Ret = mci_SendAppCmd(rca);
embeddedartists	0:6b68dac0d986	1201	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1202	Ret = mci_ExecuteCmd(SD_ACMD41_SD_SEND_OP_COND, Argument, &Response);
embeddedartists	0:6b68dac0d986	1203	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1204	if (Response.Data[0] & CMDRESP_R3_INIT_COMPLETE) {
embeddedartists	0:6b68dac0d986	1205	if (*pOcr == 0) {
embeddedartists	0:6b68dac0d986	1206	*pOcr = CMDRESP_R3_OCR_VAL(Response.Data[0]);
embeddedartists	0:6b68dac0d986	1207	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1208	}
embeddedartists	0:6b68dac0d986	1209	if ((CMDRESP_R3_OCR_VAL(Response.Data[0]) & pOcr) != pOcr) {
embeddedartists	0:6b68dac0d986	1210	return SDC_RET_BAD_PARAMETERS;
embeddedartists	0:6b68dac0d986	1211	}
embeddedartists	0:6b68dac0d986	1212	*pCCS = (Response.Data[0] & CMDRESP_R3_HC_CCS) ? true : false;
embeddedartists	0:6b68dac0d986	1213	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1214	}
embeddedartists	0:6b68dac0d986	1215	}
embeddedartists	0:6b68dac0d986	1216	}
embeddedartists	0:6b68dac0d986	1217	else {
embeddedartists	0:6b68dac0d986	1218	//If we abort here then some cards will go undetected, better to keep retrying
embeddedartists	0:6b68dac0d986	1219	//return Ret;
embeddedartists	0:6b68dac0d986	1220	}
embeddedartists	0:6b68dac0d986	1221	RetryCnt--;
embeddedartists	0:6b68dac0d986	1222	}
embeddedartists	0:6b68dac0d986	1223	return SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1224	}
embeddedartists	0:6b68dac0d986	1225
embeddedartists	0:6b68dac0d986	1226	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetCID(uint32_t *pCID) const
embeddedartists	0:6b68dac0d986	1227	{
embeddedartists	0:6b68dac0d986	1228	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1229	response_t Response;
embeddedartists	0:6b68dac0d986	1230	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1231
embeddedartists	0:6b68dac0d986	1232	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1233	Ret = mci_ExecuteCmd(SD_CMD2_ALL_SEND_CID, 0, &Response);
embeddedartists	0:6b68dac0d986	1234	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1235	pCID[3] = Response.Data[0];
embeddedartists	0:6b68dac0d986	1236	pCID[2] = Response.Data[1];
embeddedartists	0:6b68dac0d986	1237	pCID[1] = Response.Data[2];
embeddedartists	0:6b68dac0d986	1238	pCID[0] = Response.Data[3];
embeddedartists	0:6b68dac0d986	1239	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1240	}
embeddedartists	0:6b68dac0d986	1241	RetryCnt--;
embeddedartists	0:6b68dac0d986	1242	}
embeddedartists	0:6b68dac0d986	1243	return Ret;
embeddedartists	0:6b68dac0d986	1244	}
embeddedartists	0:6b68dac0d986	1245
embeddedartists	0:6b68dac0d986	1246	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetAddr(uint16_t addr) const
embeddedartists	0:6b68dac0d986	1247	{
embeddedartists	0:6b68dac0d986	1248	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1249	response_t Response;
embeddedartists	0:6b68dac0d986	1250	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1251
embeddedartists	0:6b68dac0d986	1252	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1253	Ret = mci_ExecuteCmd(SD_CMD3_SET_RELATIVE_ADDR, CMD3_RCA(addr), &Response);
embeddedartists	0:6b68dac0d986	1254	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1255	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	1256	return Ret;
embeddedartists	0:6b68dac0d986	1257	}
embeddedartists	0:6b68dac0d986	1258	}
embeddedartists	0:6b68dac0d986	1259	RetryCnt--;
embeddedartists	0:6b68dac0d986	1260	}
embeddedartists	0:6b68dac0d986	1261	return Ret;
embeddedartists	0:6b68dac0d986	1262	}
embeddedartists	0:6b68dac0d986	1263
embeddedartists	0:6b68dac0d986	1264	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetAddr(uint16_t *pRCA) const
embeddedartists	0:6b68dac0d986	1265	{
embeddedartists	0:6b68dac0d986	1266	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1267	response_t Response;
embeddedartists	0:6b68dac0d986	1268	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1269
embeddedartists	0:6b68dac0d986	1270	*pRCA = 0;
embeddedartists	0:6b68dac0d986	1271	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1272	Ret = mci_ExecuteCmd(SD_CMD3_SEND_RELATIVE_ADDR, 0, &Response);
embeddedartists	0:6b68dac0d986	1273	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1274	if (!(CMDRESP_R6_CARD_STATUS(Response.Data[0]) & R1_READY_FOR_DATA)) {
embeddedartists	0:6b68dac0d986	1275	Ret = SDC_RET_NOT_READY;
embeddedartists	0:6b68dac0d986	1276	}
embeddedartists	0:6b68dac0d986	1277	else if (R1_CURRENT_STATE(CMDRESP_R6_CARD_STATUS(Response.Data[0])) != SDMMC_STBY_ST) {
embeddedartists	0:6b68dac0d986	1278	Ret = SDC_RET_ERR_STATE;
embeddedartists	0:6b68dac0d986	1279	}
embeddedartists	0:6b68dac0d986	1280	else {
embeddedartists	0:6b68dac0d986	1281	*pRCA = CMDRESP_R6_RCA_VAL(Response.Data[0]);
embeddedartists	0:6b68dac0d986	1282	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1283	}
embeddedartists	0:6b68dac0d986	1284	}
embeddedartists	0:6b68dac0d986	1285	RetryCnt--;
embeddedartists	0:6b68dac0d986	1286	}
embeddedartists	0:6b68dac0d986	1287	return Ret;
embeddedartists	0:6b68dac0d986	1288	}
embeddedartists	0:6b68dac0d986	1289
embeddedartists	0:6b68dac0d986	1290	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetCSD(uint16_t rca, uint32_t *pCSD) const
embeddedartists	0:6b68dac0d986	1291	{
embeddedartists	0:6b68dac0d986	1292	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1293	response_t Response;
embeddedartists	0:6b68dac0d986	1294	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1295
embeddedartists	0:6b68dac0d986	1296	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1297	Ret = mci_ExecuteCmd(SD_CMD9_SEND_CSD, CMD9_RCA(rca), &Response);
embeddedartists	0:6b68dac0d986	1298	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1299	pCSD[3] = Response.Data[0];
embeddedartists	0:6b68dac0d986	1300	pCSD[2] = Response.Data[1];
embeddedartists	0:6b68dac0d986	1301	pCSD[1] = Response.Data[2];
embeddedartists	0:6b68dac0d986	1302	pCSD[0] = Response.Data[3];
embeddedartists	0:6b68dac0d986	1303	return Ret;
embeddedartists	0:6b68dac0d986	1304	}
embeddedartists	0:6b68dac0d986	1305	RetryCnt--;
embeddedartists	0:6b68dac0d986	1306	}
embeddedartists	0:6b68dac0d986	1307	return Ret;
embeddedartists	0:6b68dac0d986	1308	}
embeddedartists	0:6b68dac0d986	1309
embeddedartists	0:6b68dac0d986	1310	MCIFileSystem::ReturnCode MCIFileSystem::mci_SelectCard(uint16_t addr) const
embeddedartists	0:6b68dac0d986	1311	{
embeddedartists	0:6b68dac0d986	1312	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1313	response_t Response;
embeddedartists	0:6b68dac0d986	1314	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1315
embeddedartists	0:6b68dac0d986	1316	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1317	Ret = mci_ExecuteCmd(SD_CMD7_SELECT_CARD, CMD7_RCA(addr), &Response);
embeddedartists	0:6b68dac0d986	1318	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1319	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	1320	return Ret;
embeddedartists	0:6b68dac0d986	1321	}
embeddedartists	0:6b68dac0d986	1322	}
embeddedartists	0:6b68dac0d986	1323	RetryCnt--;
embeddedartists	0:6b68dac0d986	1324	}
embeddedartists	0:6b68dac0d986	1325	return Ret;
embeddedartists	0:6b68dac0d986	1326	}
embeddedartists	0:6b68dac0d986	1327
embeddedartists	0:6b68dac0d986	1328	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetStatus(uint16_t rca, uint32_t *pStatus) const
embeddedartists	0:6b68dac0d986	1329	{
embeddedartists	0:6b68dac0d986	1330	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1331	response_t Response;
embeddedartists	0:6b68dac0d986	1332	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1333
embeddedartists	0:6b68dac0d986	1334	*pStatus = (uint32_t) -1;
embeddedartists	0:6b68dac0d986	1335	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1336	Ret = mci_ExecuteCmd(SD_CMD13_SEND_STATUS, CMD13_RCA(rca), &Response);
embeddedartists	0:6b68dac0d986	1337	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1338	mci_CheckR1Response(Response.Data[0], &Ret);
embeddedartists	0:6b68dac0d986	1339	*pStatus = Response.Data[0];
embeddedartists	0:6b68dac0d986	1340	return Ret;
embeddedartists	0:6b68dac0d986	1341	}
embeddedartists	0:6b68dac0d986	1342	RetryCnt--;
embeddedartists	0:6b68dac0d986	1343	}
embeddedartists	0:6b68dac0d986	1344	return Ret;
embeddedartists	0:6b68dac0d986	1345	}
embeddedartists	0:6b68dac0d986	1346
embeddedartists	0:6b68dac0d986	1347	void MCIFileSystem::mci_ProcessCSD()
embeddedartists	0:6b68dac0d986	1348	{
embeddedartists	0:6b68dac0d986	1349	int32_t CSize = 0;
embeddedartists	0:6b68dac0d986	1350	int32_t CSizeMult = 0;
embeddedartists	0:6b68dac0d986	1351	int32_t Mult = 0;
embeddedartists	0:6b68dac0d986	1352
embeddedartists	0:6b68dac0d986	1353	/* compute block length based on CSD response */
embeddedartists	0:6b68dac0d986	1354	_sdCardInfo.block_len = 1 << mci_GetBits(80, 83, _sdCardInfo.csd);
embeddedartists	0:6b68dac0d986	1355
embeddedartists	0:6b68dac0d986	1356	if ((_sdCardInfo.card_type & CARD_TYPE_HC) && (_sdCardInfo.card_type & CARD_TYPE_SD)) {
embeddedartists	0:6b68dac0d986	1357	/* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec an explanation for the calculation of these values */
embeddedartists	0:6b68dac0d986	1358	CSize = mci_GetBits(48, 63, (uint32_t *) _sdCardInfo.csd) + 1;
embeddedartists	0:6b68dac0d986	1359	_sdCardInfo.blocknr = CSize << 10; /* 512 byte blocks */
embeddedartists	0:6b68dac0d986	1360	}
embeddedartists	0:6b68dac0d986	1361	else {
embeddedartists	0:6b68dac0d986	1362	/* See section 5.3 of the 4.1 revision of the MMC specs for an explanation for the calculation of these values */
embeddedartists	0:6b68dac0d986	1363	CSize = mci_GetBits(62, 73, (uint32_t *) _sdCardInfo.csd);
embeddedartists	0:6b68dac0d986	1364	CSizeMult = mci_GetBits(47, 49, (uint32_t *) _sdCardInfo.csd);
embeddedartists	0:6b68dac0d986	1365	Mult = 1 << (CSizeMult + 2);
embeddedartists	0:6b68dac0d986	1366	_sdCardInfo.blocknr = (CSize + 1) * Mult;
embeddedartists	0:6b68dac0d986	1367
embeddedartists	0:6b68dac0d986	1368	/* adjust blocknr to 512/block */
embeddedartists	0:6b68dac0d986	1369	if (_sdCardInfo.block_len > MMC_SECTOR_SIZE) {
embeddedartists	0:6b68dac0d986	1370	_sdCardInfo.blocknr = _sdCardInfo.blocknr * (_sdCardInfo.block_len >> 9);
embeddedartists	0:6b68dac0d986	1371	}
embeddedartists	0:6b68dac0d986	1372	}
embeddedartists	0:6b68dac0d986	1373
embeddedartists	0:6b68dac0d986	1374	_sdCardInfo.device_size = _sdCardInfo.blocknr << 9; /* blocknr * 512 */
embeddedartists	0:6b68dac0d986	1375	}
embeddedartists	0:6b68dac0d986	1376
embeddedartists	0:6b68dac0d986	1377	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetBusWidth(uint16_t rca, uint8_t width) const
embeddedartists	0:6b68dac0d986	1378	{
embeddedartists	0:6b68dac0d986	1379	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1380	response_t Response;
embeddedartists	0:6b68dac0d986	1381	uint8_t RetryCnt = 0x20;
embeddedartists	0:6b68dac0d986	1382
embeddedartists	0:6b68dac0d986	1383	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1384	Ret = mci_SendAppCmd(rca);
embeddedartists	0:6b68dac0d986	1385	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1386	Ret = mci_ExecuteCmd(SD_ACMD6_SET_BUS_WIDTH, ACMD6_BUS_WIDTH(width), &Response);
embeddedartists	0:6b68dac0d986	1387	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1388	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	1389	return Ret;
embeddedartists	0:6b68dac0d986	1390	}
embeddedartists	0:6b68dac0d986	1391	}
embeddedartists	0:6b68dac0d986	1392	}
embeddedartists	0:6b68dac0d986	1393	RetryCnt--;
embeddedartists	0:6b68dac0d986	1394	}
embeddedartists	0:6b68dac0d986	1395	return SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1396	}
embeddedartists	0:6b68dac0d986	1397
embeddedartists	0:6b68dac0d986	1398	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetTranState(uint16_t rca) const
embeddedartists	0:6b68dac0d986	1399	{
embeddedartists	0:6b68dac0d986	1400	ReturnCode Ret = SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1401	uint32_t status = 0;
embeddedartists	0:6b68dac0d986	1402	SDMMC_STATE_T state;
embeddedartists	0:6b68dac0d986	1403
embeddedartists	0:6b68dac0d986	1404	/* get current state of the card */
embeddedartists	0:6b68dac0d986	1405	Ret = mci_GetStatus(rca, &status);
embeddedartists	0:6b68dac0d986	1406	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1407	/* unable to get the card state. So return immediatly. */
embeddedartists	0:6b68dac0d986	1408	return Ret;
embeddedartists	0:6b68dac0d986	1409	}
embeddedartists	0:6b68dac0d986	1410
embeddedartists	0:6b68dac0d986	1411	/* check card state in response */
embeddedartists	0:6b68dac0d986	1412	state = (SDMMC_STATE_T) R1_CURRENT_STATE(status);
embeddedartists	0:6b68dac0d986	1413	switch (state) {
embeddedartists	0:6b68dac0d986	1414	case SDMMC_STBY_ST:
embeddedartists	0:6b68dac0d986	1415	/* put card in 'Trans' state */
embeddedartists	0:6b68dac0d986	1416	Ret = mci_SelectCard(rca);
embeddedartists	0:6b68dac0d986	1417	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1418	/* unable to put the card in Trans state. So return immediatly. */
embeddedartists	0:6b68dac0d986	1419	return Ret;
embeddedartists	0:6b68dac0d986	1420	}
embeddedartists	0:6b68dac0d986	1421	mci_GetStatus(rca, &status);
embeddedartists	0:6b68dac0d986	1422	if (((SDMMC_STATE_T) R1_CURRENT_STATE(status)) != SDMMC_TRAN_ST) {
embeddedartists	0:6b68dac0d986	1423	return SDC_RET_ERR_STATE;
embeddedartists	0:6b68dac0d986	1424	}
embeddedartists	0:6b68dac0d986	1425	break;
embeddedartists	0:6b68dac0d986	1426
embeddedartists	0:6b68dac0d986	1427	case SDMMC_TRAN_ST:
embeddedartists	0:6b68dac0d986	1428	/do nothing /
embeddedartists	0:6b68dac0d986	1429	break;
embeddedartists	0:6b68dac0d986	1430
embeddedartists	0:6b68dac0d986	1431	default:
embeddedartists	0:6b68dac0d986	1432	/* card shouldn't be in other states so return */
embeddedartists	0:6b68dac0d986	1433	return SDC_RET_ERR_STATE;
embeddedartists	0:6b68dac0d986	1434	}
embeddedartists	0:6b68dac0d986	1435
embeddedartists	0:6b68dac0d986	1436	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1437	}
embeddedartists	0:6b68dac0d986	1438
embeddedartists	0:6b68dac0d986	1439	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetBlockLength(uint32_t rca, uint32_t block_len) const
embeddedartists	0:6b68dac0d986	1440	{
embeddedartists	0:6b68dac0d986	1441	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1442	response_t Response;
embeddedartists	0:6b68dac0d986	1443	uint8_t RetryCnt = 0x20;
embeddedartists	0:6b68dac0d986	1444
embeddedartists	0:6b68dac0d986	1445	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1446	Ret = mci_ExecuteCmd(SD_CMD16_SET_BLOCKLEN, block_len, &Response);
embeddedartists	0:6b68dac0d986	1447	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1448	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	1449	return Ret;
embeddedartists	0:6b68dac0d986	1450	}
embeddedartists	0:6b68dac0d986	1451	}
embeddedartists	0:6b68dac0d986	1452	RetryCnt--;
embeddedartists	0:6b68dac0d986	1453	}
embeddedartists	0:6b68dac0d986	1454	return SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1455	}
embeddedartists	0:6b68dac0d986	1456
embeddedartists	0:6b68dac0d986	1457	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetCardParams() const
embeddedartists	0:6b68dac0d986	1458	{
embeddedartists	0:6b68dac0d986	1459	ReturnCode Ret;
embeddedartists	0:6b68dac0d986	1460
embeddedartists	0:6b68dac0d986	1461	mci_SetClock(SDC_TRAN_CLOCK_RATE);
embeddedartists	0:6b68dac0d986	1462	if (_sdCardInfo.card_type & CARD_TYPE_SD) {
embeddedartists	0:6b68dac0d986	1463	mci_ClockControl(SDC_CLOCK_WIDEBUS_MODE, true);
embeddedartists	0:6b68dac0d986	1464	Ret = mci_SetBusWidth(_sdCardInfo.rca, ACMD6_BUS_WIDTH_4);
embeddedartists	0:6b68dac0d986	1465	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1466	return Ret;
embeddedartists	0:6b68dac0d986	1467	}
embeddedartists	0:6b68dac0d986	1468	}
embeddedartists	0:6b68dac0d986	1469	else {
embeddedartists	0:6b68dac0d986	1470	mci_ClockControl(SDC_CLOCK_WIDEBUS_MODE, false);
embeddedartists	0:6b68dac0d986	1471	}
embeddedartists	0:6b68dac0d986	1472
embeddedartists	0:6b68dac0d986	1473	/* set block length */
embeddedartists	0:6b68dac0d986	1474	Ret = mci_SetBlockLength(_sdCardInfo.rca, MMC_SECTOR_SIZE);
embeddedartists	0:6b68dac0d986	1475	return Ret;
embeddedartists	0:6b68dac0d986	1476	}
embeddedartists	0:6b68dac0d986	1477
embeddedartists	0:6b68dac0d986	1478	bool MCIFileSystem::mci_CheckR1Response(uint32_t resp, ReturnCode* pCheckResult) const
embeddedartists	0:6b68dac0d986	1479	{
embeddedartists	0:6b68dac0d986	1480	bool Ret = true;
embeddedartists	0:6b68dac0d986	1481
embeddedartists	0:6b68dac0d986	1482	if (!(resp & R1_READY_FOR_DATA)) {
embeddedartists	0:6b68dac0d986	1483	*pCheckResult = SDC_RET_NOT_READY;
embeddedartists	0:6b68dac0d986	1484	Ret = false;
embeddedartists	0:6b68dac0d986	1485	}
embeddedartists	0:6b68dac0d986	1486	else if (R1_STATUS(resp)) {
embeddedartists	0:6b68dac0d986	1487	*pCheckResult = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1488	}
embeddedartists	0:6b68dac0d986	1489	else {
embeddedartists	0:6b68dac0d986	1490	*pCheckResult = SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1491	}
embeddedartists	0:6b68dac0d986	1492	return Ret;
embeddedartists	0:6b68dac0d986	1493	}
embeddedartists	0:6b68dac0d986	1494
embeddedartists	0:6b68dac0d986	1495	void MCIFileSystem::mci_WriteDelay() const
embeddedartists	0:6b68dac0d986	1496	{
embeddedartists	0:6b68dac0d986	1497	// volatile uint8_t i;
embeddedartists	0:6b68dac0d986	1498	// for ( i = 0; i < 0x10; i++ ) { /* delay 3MCLK + 2PCLK */
embeddedartists	0:6b68dac0d986	1499	// }
embeddedartists	0:6b68dac0d986	1500	wait(0.00001f); /* delay 10 us */
embeddedartists	0:6b68dac0d986	1501	}
embeddedartists	0:6b68dac0d986	1502
embeddedartists	0:6b68dac0d986	1503	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendCmd(uint32_t Command, uint32_t Arg, uint32_t timeout) const
embeddedartists	0:6b68dac0d986	1504	{
embeddedartists	0:6b68dac0d986	1505	ReturnCode ret = SDC_RET_TIMEOUT;
embeddedartists	0:6b68dac0d986	1506	uint32_t Status;
embeddedartists	0:6b68dac0d986	1507
embeddedartists	0:6b68dac0d986	1508	/* Set Command Info */
embeddedartists	0:6b68dac0d986	1509	mci_SetCommand(Command, Arg);
embeddedartists	0:6b68dac0d986	1510
embeddedartists	0:6b68dac0d986	1511	while (timeout) {
embeddedartists	0:6b68dac0d986	1512
embeddedartists	0:6b68dac0d986	1513	Status = LPC_MCI->STATUS;
embeddedartists	0:6b68dac0d986	1514
embeddedartists	0:6b68dac0d986	1515	/* check if command was sent */
embeddedartists	0:6b68dac0d986	1516	if (((Command & SDC_COMMAND_RSP_BITMASK) == SDC_COMMAND_NO_RSP) && (Status & SDC_STATUS_CMDSENT)) {
embeddedartists	0:6b68dac0d986	1517	ret = SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1518	break;
embeddedartists	0:6b68dac0d986	1519	}
embeddedartists	0:6b68dac0d986	1520	/* check if response was received */
embeddedartists	0:6b68dac0d986	1521	if (Status & SDC_STATUS_CMDRESPEND) {
embeddedartists	0:6b68dac0d986	1522	ret = SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1523	break;
embeddedartists	0:6b68dac0d986	1524	}
embeddedartists	0:6b68dac0d986	1525
embeddedartists	0:6b68dac0d986	1526	/* check command sending status */
embeddedartists	0:6b68dac0d986	1527	if (Status & SDC_STATUS_CMDERR) {
embeddedartists	0:6b68dac0d986	1528	if (Status & SDC_STATUS_CMDCRCFAIL) {
embeddedartists	0:6b68dac0d986	1529	if ((SDC_COMMAND_INDEX(Command) == MMC_SEND_OP_COND) \|\|
embeddedartists	0:6b68dac0d986	1530	(SDC_COMMAND_INDEX(Command) == SD_APP_OP_COND) \|\|
embeddedartists	0:6b68dac0d986	1531	(SDC_COMMAND_INDEX(Command) == MMC_STOP_TRANSMISSION)) {
embeddedartists	0:6b68dac0d986	1532	ret = SDC_RET_OK; /* ignore CRC error if it's a resp for SEND_OP_COND or STOP_TRANSMISSION. */
embeddedartists	0:6b68dac0d986	1533	break;
embeddedartists	0:6b68dac0d986	1534	}
embeddedartists	0:6b68dac0d986	1535	}
embeddedartists	0:6b68dac0d986	1536	ret = SDC_RET_CMD_FAILED;
embeddedartists	0:6b68dac0d986	1537	break;
embeddedartists	0:6b68dac0d986	1538	}
embeddedartists	0:6b68dac0d986	1539
embeddedartists	0:6b68dac0d986	1540	timeout--;
embeddedartists	0:6b68dac0d986	1541	}
embeddedartists	0:6b68dac0d986	1542
embeddedartists	0:6b68dac0d986	1543	mci_ResetCommand();
embeddedartists	0:6b68dac0d986	1544
embeddedartists	0:6b68dac0d986	1545	return ret;
embeddedartists	0:6b68dac0d986	1546	}
embeddedartists	0:6b68dac0d986	1547
embeddedartists	0:6b68dac0d986	1548	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendAppCmd(uint16_t rca) const
embeddedartists	0:6b68dac0d986	1549	{
embeddedartists	0:6b68dac0d986	1550	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1551	response_t Response;
embeddedartists	0:6b68dac0d986	1552	uint32_t RetryCnt = 20;
embeddedartists	0:6b68dac0d986	1553
embeddedartists	0:6b68dac0d986	1554	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1555	Ret = mci_ExecuteCmd(SD_CMD55_APP_CMD, CMD55_RCA(rca), &Response);
embeddedartists	0:6b68dac0d986	1556	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1557	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	1558	if (Ret != SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1559	return Ret;
embeddedartists	0:6b68dac0d986	1560	}
embeddedartists	0:6b68dac0d986	1561	if (Response.Data[0] & R1_APP_CMD) {
embeddedartists	0:6b68dac0d986	1562	return SDC_RET_OK;
embeddedartists	0:6b68dac0d986	1563	}
embeddedartists	0:6b68dac0d986	1564	else {
embeddedartists	0:6b68dac0d986	1565	Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1566	}
embeddedartists	0:6b68dac0d986	1567	}
embeddedartists	0:6b68dac0d986	1568	}
embeddedartists	0:6b68dac0d986	1569	RetryCnt--;
embeddedartists	0:6b68dac0d986	1570	}
embeddedartists	0:6b68dac0d986	1571	return SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1572	}
embeddedartists	0:6b68dac0d986	1573
embeddedartists	0:6b68dac0d986	1574	void MCIFileSystem::mci_SetDataTransfer(uint16_t BlockNum, bool DirFromCard, uint32_t Timeout) const
embeddedartists	0:6b68dac0d986	1575	{
embeddedartists	0:6b68dac0d986	1576	uint32_t DataCtrl = 0;
embeddedartists	0:6b68dac0d986	1577	LPC_MCI->DATATMR = Timeout;
embeddedartists	0:6b68dac0d986	1578	LPC_MCI->DATALEN = BlockNum * 512;
embeddedartists	0:6b68dac0d986	1579
embeddedartists	0:6b68dac0d986	1580	DataCtrl = SDC_DATACTRL_ENABLE;
embeddedartists	0:6b68dac0d986	1581	// DataCtrl mode=block, block size=512byte
embeddedartists	0:6b68dac0d986	1582	DataCtrl \|= (0x9 << 4);
embeddedartists	0:6b68dac0d986	1583	if (DirFromCard) {
embeddedartists	0:6b68dac0d986	1584	DataCtrl \|= (0x1 << 1);
embeddedartists	0:6b68dac0d986	1585	}
embeddedartists	0:6b68dac0d986	1586	DataCtrl \|= SDC_DATACTRL_DMA_ENABLE;
embeddedartists	0:6b68dac0d986	1587	LPC_MCI->DATACTRL = DataCtrl;
embeddedartists	0:6b68dac0d986	1588	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	1589	}
embeddedartists	0:6b68dac0d986	1590
embeddedartists	0:6b68dac0d986	1591	void MCIFileSystem::mci_GetResp(response_t* pResp) const
embeddedartists	0:6b68dac0d986	1592	{
embeddedartists	0:6b68dac0d986	1593	pResp->CmdIndex = SDC_RESPCOMMAND_VAL(LPC_MCI->RESP_CMD);
embeddedartists	0:6b68dac0d986	1594	pResp->Data[0] = LPC_MCI->RESP0;
embeddedartists	0:6b68dac0d986	1595	if (CardStatusNumBytes == 4) {
embeddedartists	0:6b68dac0d986	1596	pResp->Data[1] = LPC_MCI->RESP1;
embeddedartists	0:6b68dac0d986	1597	pResp->Data[2] = LPC_MCI->RESP2;
embeddedartists	0:6b68dac0d986	1598	pResp->Data[3] = LPC_MCI->RESP3;
embeddedartists	0:6b68dac0d986	1599	}
embeddedartists	0:6b68dac0d986	1600	}
embeddedartists	0:6b68dac0d986	1601
embeddedartists	0:6b68dac0d986	1602	uint32_t MCIFileSystem::mci_GetBits(int32_t start, int32_t end, uint32_t *data) const
embeddedartists	0:6b68dac0d986	1603	{
embeddedartists	0:6b68dac0d986	1604	uint32_t v;
embeddedartists	0:6b68dac0d986	1605	uint32_t i = end >> 5;
embeddedartists	0:6b68dac0d986	1606	uint32_t j = start & 0x1f;
embeddedartists	0:6b68dac0d986	1607
embeddedartists	0:6b68dac0d986	1608	if (i == (start >> 5)) {
embeddedartists	0:6b68dac0d986	1609	v = (data[i] >> j);
embeddedartists	0:6b68dac0d986	1610	}
embeddedartists	0:6b68dac0d986	1611	else {
embeddedartists	0:6b68dac0d986	1612	v = ((data[i] << (32 - j)) \| (data[start >> 5] >> j));
embeddedartists	0:6b68dac0d986	1613	}
embeddedartists	0:6b68dac0d986	1614
embeddedartists	0:6b68dac0d986	1615	return v & ((1 << (end - start + 1)) - 1);
embeddedartists	0:6b68dac0d986	1616	}
embeddedartists	0:6b68dac0d986	1617
embeddedartists	0:6b68dac0d986	1618	void MCIFileSystem::mci_SetCommand(uint32_t Cmd, uint32_t Arg) const
embeddedartists	0:6b68dac0d986	1619	{
embeddedartists	0:6b68dac0d986	1620	/* Clear status register */
embeddedartists	0:6b68dac0d986	1621	LPC_MCI->CLEAR = SDC_CLEAR_ALL;
embeddedartists	0:6b68dac0d986	1622
embeddedartists	0:6b68dac0d986	1623	/* Set the argument first, finally command */
embeddedartists	0:6b68dac0d986	1624	LPC_MCI->ARGUMENT = Arg;
embeddedartists	0:6b68dac0d986	1625
embeddedartists	0:6b68dac0d986	1626	/* Write command value, enable the command */
embeddedartists	0:6b68dac0d986	1627	LPC_MCI->COMMAND = Cmd \| SDC_COMMAND_ENABLE;
embeddedartists	0:6b68dac0d986	1628
embeddedartists	0:6b68dac0d986	1629	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	1630	}
embeddedartists	0:6b68dac0d986	1631
embeddedartists	0:6b68dac0d986	1632	void MCIFileSystem::mci_ResetCommand() const
embeddedartists	0:6b68dac0d986	1633	{
embeddedartists	0:6b68dac0d986	1634	LPC_MCI->CLEAR = SDC_CLEAR_ALL;
embeddedartists	0:6b68dac0d986	1635
embeddedartists	0:6b68dac0d986	1636	LPC_MCI->ARGUMENT = 0xFFFFFFFF;
embeddedartists	0:6b68dac0d986	1637
embeddedartists	0:6b68dac0d986	1638	LPC_MCI->COMMAND = 0;
embeddedartists	0:6b68dac0d986	1639
embeddedartists	0:6b68dac0d986	1640	mci_WriteDelay();
embeddedartists	0:6b68dac0d986	1641	}
embeddedartists	0:6b68dac0d986	1642
embeddedartists	0:6b68dac0d986	1643	int32_t MCIFileSystem::mci_IRQHandler(uint8_t txBuf, uint32_t txCnt, uint8_t rxBuf, uint32_t rxCnt)
embeddedartists	0:6b68dac0d986	1644	{
embeddedartists	0:6b68dac0d986	1645	uint32_t Status;
embeddedartists	0:6b68dac0d986	1646
embeddedartists	0:6b68dac0d986	1647	Status = LPC_MCI->STATUS;
embeddedartists	0:6b68dac0d986	1648
embeddedartists	0:6b68dac0d986	1649	if ( Status & SDC_STATUS_DATAERR) {
embeddedartists	0:6b68dac0d986	1650	LPC_MCI->CLEAR = SDC_STATUS_DATAERR;
embeddedartists	0:6b68dac0d986	1651	return -1; /* Data transfer error */
embeddedartists	0:6b68dac0d986	1652	}
embeddedartists	0:6b68dac0d986	1653
embeddedartists	0:6b68dac0d986	1654	if ( Status & SDC_STATUS_DATAEND) {
embeddedartists	0:6b68dac0d986	1655	LPC_MCI->CLEAR = SDC_STATUS_DATAEND;
embeddedartists	0:6b68dac0d986	1656	LPC_MCI->MASK0 = 0;
embeddedartists	0:6b68dac0d986	1657	return 0;
embeddedartists	0:6b68dac0d986	1658	}
embeddedartists	0:6b68dac0d986	1659
embeddedartists	0:6b68dac0d986	1660	if ( Status & SDC_STATUS_DATABLOCKEND) {
embeddedartists	0:6b68dac0d986	1661	LPC_MCI->CLEAR = SDC_STATUS_DATABLOCKEND;
embeddedartists	0:6b68dac0d986	1662	return 1;
embeddedartists	0:6b68dac0d986	1663	}
embeddedartists	0:6b68dac0d986	1664
embeddedartists	0:6b68dac0d986	1665	if (Status & SDC_STATUS_FIFO) {
embeddedartists	0:6b68dac0d986	1666	return mci_FIFOIRQHandler(txBuf, txCnt, rxBuf, rxCnt);
embeddedartists	0:6b68dac0d986	1667	}
embeddedartists	0:6b68dac0d986	1668
embeddedartists	0:6b68dac0d986	1669	return 1;
embeddedartists	0:6b68dac0d986	1670	}
embeddedartists	0:6b68dac0d986	1671
embeddedartists	0:6b68dac0d986	1672	int32_t MCIFileSystem::mci_FIFOIRQHandler(uint8_t txBuf, uint32_t txCnt, uint8_t rxBuf, uint32_t rxCnt)
embeddedartists	0:6b68dac0d986	1673	{
embeddedartists	0:6b68dac0d986	1674	uint32_t Status;
embeddedartists	0:6b68dac0d986	1675	Status = LPC_MCI->STATUS;
embeddedartists	0:6b68dac0d986	1676
embeddedartists	0:6b68dac0d986	1677	if (txBuf) {
embeddedartists	0:6b68dac0d986	1678	if (Status & SDC_STATUS_TXFIFOHALFEMPTY) {
embeddedartists	0:6b68dac0d986	1679	if (*txCnt % 64) {
embeddedartists	0:6b68dac0d986	1680	mci_WriteFIFO((uint32_t ) &txBuf[txCnt], false);
embeddedartists	0:6b68dac0d986	1681	}
embeddedartists	0:6b68dac0d986	1682	else {
embeddedartists	0:6b68dac0d986	1683	mci_WriteFIFO((uint32_t ) &txBuf[txCnt], true);
embeddedartists	0:6b68dac0d986	1684	}
embeddedartists	0:6b68dac0d986	1685	*txCnt += 32;
embeddedartists	0:6b68dac0d986	1686	}
embeddedartists	0:6b68dac0d986	1687	}
embeddedartists	0:6b68dac0d986	1688
embeddedartists	0:6b68dac0d986	1689	if (rxBuf) {
embeddedartists	0:6b68dac0d986	1690	if (Status & SDC_STATUS_RXFIFOHALFFULL) {
embeddedartists	0:6b68dac0d986	1691	if (*rxCnt % 64) {
embeddedartists	0:6b68dac0d986	1692	mci_ReadFIFO((uint32_t ) &rxBuf[rxCnt], false);
embeddedartists	0:6b68dac0d986	1693	}
embeddedartists	0:6b68dac0d986	1694	else {
embeddedartists	0:6b68dac0d986	1695	mci_ReadFIFO((uint32_t ) &rxBuf[rxCnt], true);
embeddedartists	0:6b68dac0d986	1696	}
embeddedartists	0:6b68dac0d986	1697	*rxCnt += 32;
embeddedartists	0:6b68dac0d986	1698	}
embeddedartists	0:6b68dac0d986	1699	}
embeddedartists	0:6b68dac0d986	1700
embeddedartists	0:6b68dac0d986	1701	LPC_MCI->CLEAR = SDC_STATUS_FIFO;
embeddedartists	0:6b68dac0d986	1702
embeddedartists	0:6b68dac0d986	1703	return 1;
embeddedartists	0:6b68dac0d986	1704	}
embeddedartists	0:6b68dac0d986	1705
embeddedartists	0:6b68dac0d986	1706	void MCIFileSystem::mci_ReadFIFO(uint32_t *pDst, bool bFirstHalf) const
embeddedartists	0:6b68dac0d986	1707	{
embeddedartists	0:6b68dac0d986	1708	uint8_t start = 0, end = 7;
embeddedartists	0:6b68dac0d986	1709
embeddedartists	0:6b68dac0d986	1710	if (!bFirstHalf) {
embeddedartists	0:6b68dac0d986	1711	start += 8;
embeddedartists	0:6b68dac0d986	1712	end += 8;
embeddedartists	0:6b68dac0d986	1713	}
embeddedartists	0:6b68dac0d986	1714	for (; start <= end; start++) {
embeddedartists	0:6b68dac0d986	1715	*pDst = LPC_MCI->FIFO[start];
embeddedartists	0:6b68dac0d986	1716	pDst++;
embeddedartists	0:6b68dac0d986	1717	}
embeddedartists	0:6b68dac0d986	1718	}
embeddedartists	0:6b68dac0d986	1719
embeddedartists	0:6b68dac0d986	1720	void MCIFileSystem::mci_WriteFIFO(uint32_t *pSrc, bool bFirstHalf) const
embeddedartists	0:6b68dac0d986	1721	{
embeddedartists	0:6b68dac0d986	1722	uint8_t start = 0, end = 7;
embeddedartists	0:6b68dac0d986	1723	if (!bFirstHalf) {
embeddedartists	0:6b68dac0d986	1724	start += 8;
embeddedartists	0:6b68dac0d986	1725	end += 8;
embeddedartists	0:6b68dac0d986	1726	}
embeddedartists	0:6b68dac0d986	1727	for (; start <= end; start++) {
embeddedartists	0:6b68dac0d986	1728	LPC_MCI->FIFO[start] = *pSrc;
embeddedartists	0:6b68dac0d986	1729	pSrc++;
embeddedartists	0:6b68dac0d986	1730	}
embeddedartists	0:6b68dac0d986	1731	}
embeddedartists	0:6b68dac0d986	1732
embeddedartists	0:6b68dac0d986	1733	void MCIFileSystem::mci_SetupEventWakeup(uint8_t dmaChannel)
embeddedartists	0:6b68dac0d986	1734	{
embeddedartists	0:6b68dac0d986	1735	/* Wait for IRQ - for an RTOS, you would pend on an event here with a IRQ based wakeup. */
embeddedartists	0:6b68dac0d986	1736	NVIC_ClearPendingIRQ(DMA_IRQn);
embeddedartists	0:6b68dac0d986	1737
embeddedartists	0:6b68dac0d986	1738	_eventDmaChannel = dmaChannel;
embeddedartists	0:6b68dac0d986	1739	_eventReceived = false;
embeddedartists	0:6b68dac0d986	1740	_eventSuccess = false;
embeddedartists	0:6b68dac0d986	1741
embeddedartists	0:6b68dac0d986	1742	NVIC_EnableIRQ(DMA_IRQn);
embeddedartists	0:6b68dac0d986	1743	}
embeddedartists	0:6b68dac0d986	1744
embeddedartists	0:6b68dac0d986	1745	uint32_t MCIFileSystem::mci_WaitForEvent() const
embeddedartists	0:6b68dac0d986	1746	{
embeddedartists	0:6b68dac0d986	1747	/* Wait for the event (DMA or MCI interrupt) for a maximum of 2 seconds */
embeddedartists	0:6b68dac0d986	1748	uint32_t end = us_ticker_read() + 210001000;
embeddedartists	0:6b68dac0d986	1749	while ((us_ticker_read() < end) && (!_eventReceived))
embeddedartists	0:6b68dac0d986	1750	{
embeddedartists	0:6b68dac0d986	1751	// If the driver is having problems reading the card, adding a delay here
embeddedartists	0:6b68dac0d986	1752	// might help.
embeddedartists	0:6b68dac0d986	1753	//wait(0.01);
embeddedartists	0:6b68dac0d986	1754	}
embeddedartists	0:6b68dac0d986	1755
embeddedartists	0:6b68dac0d986	1756	if (_eventReceived && _eventSuccess) {
embeddedartists	0:6b68dac0d986	1757	return 0;
embeddedartists	0:6b68dac0d986	1758	}
embeddedartists	0:6b68dac0d986	1759
embeddedartists	0:6b68dac0d986	1760	return 1;
embeddedartists	0:6b68dac0d986	1761	}
embeddedartists	0:6b68dac0d986	1762
embeddedartists	0:6b68dac0d986	1763	MCIFileSystem::ReturnCode MCIFileSystem::_readBlocks(uint32_t card_type, uint32_t startBlock, uint32_t blockNum) const
embeddedartists	0:6b68dac0d986	1764	{
embeddedartists	0:6b68dac0d986	1765	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1766	response_t Response;
embeddedartists	0:6b68dac0d986	1767	uint32_t Command, Argument;
embeddedartists	0:6b68dac0d986	1768	uint8_t RetryCnt = 0x20;
embeddedartists	0:6b68dac0d986	1769
embeddedartists	0:6b68dac0d986	1770	if (blockNum == 1) {
embeddedartists	0:6b68dac0d986	1771	Command = SD_CMD17_READ_SINGLE_BLOCK;
embeddedartists	0:6b68dac0d986	1772	}
embeddedartists	0:6b68dac0d986	1773	else {
embeddedartists	0:6b68dac0d986	1774	Command = SD_CMD18_READ_MULTIPLE_BLOCK;
embeddedartists	0:6b68dac0d986	1775	}
embeddedartists	0:6b68dac0d986	1776
embeddedartists	0:6b68dac0d986	1777	/* Select single or multiple read based on number of blocks */
embeddedartists	0:6b68dac0d986	1778	/* if high capacity card use block indexing */
embeddedartists	0:6b68dac0d986	1779	if (card_type & CARD_TYPE_HC) {
embeddedartists	0:6b68dac0d986	1780	Argument = startBlock;
embeddedartists	0:6b68dac0d986	1781	}
embeddedartists	0:6b68dac0d986	1782	else { /fix at 512 bytes/
embeddedartists	0:6b68dac0d986	1783	Argument = startBlock << 9;
embeddedartists	0:6b68dac0d986	1784	}
embeddedartists	0:6b68dac0d986	1785
embeddedartists	0:6b68dac0d986	1786	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1787	Ret = mci_ExecuteCmd(Command, Argument, &Response);
embeddedartists	0:6b68dac0d986	1788	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1789	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	1790	return Ret;
embeddedartists	0:6b68dac0d986	1791	}
embeddedartists	0:6b68dac0d986	1792	}
embeddedartists	0:6b68dac0d986	1793	RetryCnt--;
embeddedartists	0:6b68dac0d986	1794	}
embeddedartists	0:6b68dac0d986	1795	return Ret;
embeddedartists	0:6b68dac0d986	1796	}
embeddedartists	0:6b68dac0d986	1797
embeddedartists	0:6b68dac0d986	1798	MCIFileSystem::ReturnCode MCIFileSystem::_writeBlocks(uint32_t card_type, uint32_t startBlock, uint32_t blockNum) const
embeddedartists	0:6b68dac0d986	1799	{
embeddedartists	0:6b68dac0d986	1800	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:6b68dac0d986	1801	response_t Response;
embeddedartists	0:6b68dac0d986	1802	uint32_t Command, Argument;
embeddedartists	0:6b68dac0d986	1803	uint8_t RetryCnt = 0x20;
embeddedartists	0:6b68dac0d986	1804
embeddedartists	0:6b68dac0d986	1805	if (blockNum == 1) {
embeddedartists	0:6b68dac0d986	1806	Command = SD_CMD24_WRITE_BLOCK;
embeddedartists	0:6b68dac0d986	1807	}
embeddedartists	0:6b68dac0d986	1808	else {
embeddedartists	0:6b68dac0d986	1809	Command = SD_CMD25_WRITE_MULTIPLE_BLOCK;
embeddedartists	0:6b68dac0d986	1810	}
embeddedartists	0:6b68dac0d986	1811
embeddedartists	0:6b68dac0d986	1812	/* if high capacity card use block indexing */
embeddedartists	0:6b68dac0d986	1813	if (card_type & CARD_TYPE_HC) {
embeddedartists	0:6b68dac0d986	1814	Argument = startBlock;
embeddedartists	0:6b68dac0d986	1815	}
embeddedartists	0:6b68dac0d986	1816	else { /fix at 512 bytes/
embeddedartists	0:6b68dac0d986	1817	Argument = startBlock << 9;
embeddedartists	0:6b68dac0d986	1818
embeddedartists	0:6b68dac0d986	1819	}
embeddedartists	0:6b68dac0d986	1820
embeddedartists	0:6b68dac0d986	1821	while (RetryCnt > 0) {
embeddedartists	0:6b68dac0d986	1822	Ret = mci_ExecuteCmd(Command, Argument, &Response);
embeddedartists	0:6b68dac0d986	1823	if (Ret == SDC_RET_OK) {
embeddedartists	0:6b68dac0d986	1824	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:6b68dac0d986	1825	return Ret;
embeddedartists	0:6b68dac0d986	1826	}
embeddedartists	0:6b68dac0d986	1827	}
embeddedartists	0:6b68dac0d986	1828	RetryCnt--;
embeddedartists	0:6b68dac0d986	1829	}
embeddedartists	0:6b68dac0d986	1830	return Ret;
embeddedartists	0:6b68dac0d986	1831	}

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Type:	Program
Created:	04 Oct 2018
Imports:	1
Forks:	0
Commits:	42
Dependents:	1
Dependencies:	8
Followers:	1

FileSystems/MCIFileSystem.cpp@9:a33326afd686, 2014-12-11 (annotated)

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