Revision 0:f8571ffd252a, committed 2013-07-28

Comitter:

jksoft

Date:

Sun Jul 28 08:20:17 2013 +0000

Commit message:

First

Changed in this revision

diff -r 000000000000 -r f8571ffd252a HighSpeedAnalogIn/HighSpeedAnalogIn.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/HighSpeedAnalogIn/HighSpeedAnalogIn.cpp	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,292 @@
+
+#include "HighSpeedAnalogIn.h"
+
+HighSpeedAnalogIn *HighSpeedAnalogIn::instance;
+int HighSpeedAnalogIn::refcnt = 0;
+
+HighSpeedAnalogIn::HighSpeedAnalogIn(PinName pin0, PinName pin1, PinName pin2, PinName pin3, PinName pin4, PinName pin5) {
+
+    refcnt++;
+    if (refcnt > 1) {
+        error("Please do not use over an object.");
+    }
+
+    static const int sample_rate = 200000;
+    static const int cclk_div = 1;
+
+    int adc_clk_freq = CLKS_PER_SAMPLE * sample_rate;
+    int m = (LPC_SC->PLL0CFG & 0xFFFF) + 1;
+    int n = (LPC_SC->PLL0CFG >> 16) + 1;
+    int cclkdiv = LPC_SC->CCLKCFG + 1;
+    int Fcco = (2 * m * XTAL_FREQ) / n;
+    int cclk = Fcco / cclkdiv;
+
+    LPC_SC->PCONP |= (1 << 12);
+    LPC_SC->PCLKSEL0 &= ~(0x3 << 24);
+    switch (cclk_div) {
+        case 1:
+            LPC_SC->PCLKSEL0 |= 0x1 << 24;
+            break;
+        case 2:
+            LPC_SC->PCLKSEL0 |= 0x2 << 24;
+            break;
+        case 4:
+            LPC_SC->PCLKSEL0 |= 0x0 << 24;
+            break;
+        case 8:
+            LPC_SC->PCLKSEL0 |= 0x3 << 24;
+            break;
+        default:
+            fprintf(stderr, "Warning: ADC CCLK clock divider must be 1, 2, 4 or 8. %u supplied.\n", cclk_div);
+            fprintf(stderr, "Defaulting to 1.\n");
+            LPC_SC->PCLKSEL0 |= 0x1 << 24;
+            break;
+    }
+    int pclk = cclk / cclk_div;
+    int clock_div = pclk / adc_clk_freq;
+
+    if (clock_div > 0xFF) {
+        fprintf(stderr, "Warning: Clock division is %u which is above 255 limit. Re-Setting at limit.\n", clock_div);
+        clock_div = 0xFF;
+    }
+    if (clock_div == 0) {
+        fprintf(stderr, "Warning: Clock division is 0. Re-Setting to 1.\n");
+        clock_div = 1;
+    }
+
+    int _adc_clk_freq = pclk / clock_div;
+    if (_adc_clk_freq > MAX_ADC_CLOCK) {
+        fprintf(stderr, "Warning: Actual ADC sample rate of %u which is above %u limit\n", _adc_clk_freq / CLKS_PER_SAMPLE, MAX_ADC_CLOCK / CLKS_PER_SAMPLE);
+        int max_div = 1;
+        while ((pclk / max_div) > MAX_ADC_CLOCK) {
+            max_div++;
+        }
+        fprintf(stderr, "Maximum recommended sample rate is %u\n", (pclk / max_div) / CLKS_PER_SAMPLE);
+    }
+
+    LPC_ADC->ADCR = ((clock_div - 1) << 8) | (1 << 21);
+    LPC_ADC->ADCR &= ~0xFF;
+
+    for (int i = 0; i < 8; i++) {
+        _adc_data[i] = 0;
+    }
+
+    // Attach IRQ
+    instance = this;
+    NVIC_SetVector(ADC_IRQn, (uint32_t)&static_adcisr);
+
+    // Disable global interrupt
+    LPC_ADC->ADINTEN &= ~0x100;
+
+    // Clock frequency.
+    printf("Clock frequency:%d\n", _adc_clk_freq);
+
+    // Actual sampling rate.
+    printf("Actual sampling rate:%d\n", _adc_clk_freq / CLKS_PER_SAMPLE);
+    
+    int tmp = LPC_ADC->ADCR & ~(0x0F << 24);
+    tmp |= ((0x0 & 7) << 24) | ((0x0 & 1) << 27);
+    LPC_ADC->ADCR = tmp;
+    LPC_ADC->ADCR |= (1 << 16);
+
+    if (pin0 != NC) setup(pin0, 1);
+    if (pin1 != NC) setup(pin1, 1);
+    if (pin2 != NC) setup(pin2, 1);
+    if (pin3 != NC) setup(pin3, 1);
+    if (pin4 != NC) setup(pin4, 1);
+    if (pin5 != NC) setup(pin5, 1);
+
+    interrupt_state(pin0, 1);
+}
+
+HighSpeedAnalogIn::~HighSpeedAnalogIn() {
+}
+
+void HighSpeedAnalogIn::static_adcisr(void) {
+    instance->adcisr();
+}
+
+void HighSpeedAnalogIn::adcisr(void) {
+    uint32_t stat = LPC_ADC->ADSTAT;
+    // Scan channels for over-run or done and update array
+    if (stat & 0x0101) _adc_data[0] = LPC_ADC->ADDR0;
+    if (stat & 0x0202) _adc_data[1] = LPC_ADC->ADDR1;
+    if (stat & 0x0404) _adc_data[2] = LPC_ADC->ADDR2;
+    if (stat & 0x0808) _adc_data[3] = LPC_ADC->ADDR3;
+    if (stat & 0x1010) _adc_data[4] = LPC_ADC->ADDR4;
+    if (stat & 0x2020) _adc_data[5] = LPC_ADC->ADDR5;
+    if (stat & 0x4040) _adc_data[6] = LPC_ADC->ADDR6;
+    if (stat & 0x8080) _adc_data[7] = LPC_ADC->ADDR7;
+}
+
+int HighSpeedAnalogIn::get_channel(PinName pin) {
+    int ch;
+    switch (pin) {
+        case p15:// =p0.23 of LPC1768
+            ch = 0;
+            break;
+        case p16:// =p0.24 of LPC1768
+            ch = 1;
+            break;
+        case p17:// =p0.25 of LPC1768
+            ch = 2;
+            break;
+        case p18:// =p0.26 of LPC1768
+            ch = 3;
+            break;
+        case p19:// =p1.30 of LPC1768
+            ch = 4;
+            break;
+        case p20:// =p1.31 of LPC1768
+            ch = 5;
+            break;
+        default:
+            ch = 0;
+            break;
+    }
+    return ch;
+}
+
+uint32_t HighSpeedAnalogIn::get_data(PinName pin) {
+    // If in burst mode and at least one interrupt enabled then
+    // take all values from _adc_data
+    if (LPC_ADC->ADINTEN & 0x3F) {
+        return (_adc_data[get_channel(pin)]);
+    } else {
+        // Return current register value or last value from interrupt
+        switch (pin) {
+            case p15:// =p0.23 of LPC1768
+                return ((LPC_ADC->ADINTEN & 0x01) ? _adc_data[0] : LPC_ADC->ADDR0);
+            case p16:// =p0.24 of LPC1768
+                return ((LPC_ADC->ADINTEN & 0x02) ? _adc_data[1] : LPC_ADC->ADDR1);
+            case p17:// =p0.25 of LPC1768
+                return ((LPC_ADC->ADINTEN & 0x04) ? _adc_data[2] : LPC_ADC->ADDR2);
+            case p18:// =p0.26 of LPC1768:
+                return ((LPC_ADC->ADINTEN & 0x08) ? _adc_data[3] : LPC_ADC->ADDR3);
+            case p19:// =p1.30 of LPC1768
+                return ((LPC_ADC->ADINTEN & 0x10) ? _adc_data[4] : LPC_ADC->ADDR4);
+            case p20:// =p1.31 of LPC1768
+                return ((LPC_ADC->ADINTEN & 0x20) ? _adc_data[5] : LPC_ADC->ADDR5);
+            default:
+                return 0;
+        }
+    }
+}
+
+// Enable or disable an HighSpeedAnalogIn pin
+void HighSpeedAnalogIn::setup(PinName pin, int state) {
+    int ch = get_channel(pin);
+    if ((state & 1) == 1) {
+        switch (pin) {
+            case p15:// =p0.23 of LPC1768
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 14);
+                LPC_PINCON->PINSEL1 |= (unsigned int)0x1 << 14;
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 14);
+                LPC_PINCON->PINMODE1 |= (unsigned int)0x2 << 14;
+                break;
+            case p16:// =p0.24 of LPC1768
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 16);
+                LPC_PINCON->PINSEL1 |= (unsigned int)0x1 << 16;
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 16);
+                LPC_PINCON->PINMODE1 |= (unsigned int)0x2 << 16;
+                break;
+            case p17:// =p0.25 of LPC1768
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 18);
+                LPC_PINCON->PINSEL1 |= (unsigned int)0x1 << 18;
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 18);
+                LPC_PINCON->PINMODE1 |= (unsigned int)0x2 << 18;
+                break;
+            case p18:// =p0.26 of LPC1768:
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 20);
+                LPC_PINCON->PINSEL1 |= (unsigned int)0x1 << 20;
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 20);
+                LPC_PINCON->PINMODE1 |= (unsigned int)0x2 << 20;
+                break;
+            case p19:// =p1.30 of LPC1768
+                LPC_PINCON->PINSEL3 &= ~((unsigned int)0x3 << 28);
+                LPC_PINCON->PINSEL3 |= (unsigned int)0x3 << 28;
+                LPC_PINCON->PINMODE3 &= ~((unsigned int)0x3 << 28);
+                LPC_PINCON->PINMODE3 |= (unsigned int)0x2 << 28;
+                break;
+            case p20:// =p1.31 of LPC1768
+                LPC_PINCON->PINSEL3 &= ~((unsigned int)0x3 << 30);
+                LPC_PINCON->PINSEL3 |= (unsigned int)0x3 << 30;
+                LPC_PINCON->PINMODE3 &= ~((unsigned int)0x3 << 30);
+                LPC_PINCON->PINMODE3 |= (unsigned int)0x2 << 30;
+                break;
+            default:
+                error("Invalid pin.");
+                break;
+        }
+        // Select channel
+        LPC_ADC->ADCR |= (1 << ch);
+    } else {
+        switch (pin) {
+            case p15://=p0.23 of LPC1768
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 14);
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 14);
+                break;
+            case p16://=p0.24 of LPC1768
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 16);
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 16);
+                break;
+            case p17://=p0.25 of LPC1768
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 18);
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 18);
+                break;
+            case p18://=p0.26 of LPC1768:
+                LPC_PINCON->PINSEL1 &= ~((unsigned int)0x3 << 20);
+                LPC_PINCON->PINMODE1 &= ~((unsigned int)0x3 << 20);
+                break;
+            case p19://=p1.30 of LPC1768
+                LPC_PINCON->PINSEL3 &= ~((unsigned int)0x3 << 28);
+                LPC_PINCON->PINMODE3 &= ~((unsigned int)0x3 << 28);
+                break;
+            case p20://=p1.31 of LPC1768
+                LPC_PINCON->PINSEL3 &= ~((unsigned int)0x3 << 30);
+                LPC_PINCON->PINMODE3 &= ~((unsigned int)0x3 << 30);
+                break;
+            default:
+                error("Invalid pin.");
+                break;
+        }
+        LPC_ADC->ADCR &= ~(1 << ch);
+    }
+}
+
+void HighSpeedAnalogIn::interrupt_state(PinName pin, int state) {
+    int ch = get_channel(pin);
+    if (state == 1) {
+        LPC_ADC->ADINTEN &= ~0x100;
+        LPC_ADC->ADINTEN |= 1 << ch;
+        /* Enable the HighSpeedAnalogIn Interrupt */
+        NVIC_EnableIRQ(ADC_IRQn);
+    } else {
+        LPC_ADC->ADINTEN &= ~(1 << ch);
+        //Disable interrrupt if no active pins left
+        if ((LPC_ADC->ADINTEN & 0xFF) == 0)
+            NVIC_DisableIRQ(ADC_IRQn);
+    }
+}
+
+float HighSpeedAnalogIn::read(PinName pin) {
+    /*
+     * Reset DONE and OVERRUN.
+     *
+     * bit 31 : DONE
+     * bit 30 : OVERRUN
+     */
+    _adc_data[get_channel(pin)] &= ~(((uint32_t)0x01 << 31) | ((uint32_t)0x01 << 30));
+    return (float)((get_data(pin) >> 4) & 0xFFF) / (float)0xFFF;
+}
+
+unsigned short HighSpeedAnalogIn::read_u16(PinName pin) {
+    /*
+     * Reset DONE and OVERRUN.
+     *
+     * bit 31 : DONE
+     * bit 30 : OVERRUN
+     */
+    _adc_data[get_channel(pin)] &= ~(((uint32_t)0x01 << 31) | ((uint32_t)0x01 << 30));
+    return ((get_data(pin) >> 4) & 0xFFF);
+}

diff -r 000000000000 -r f8571ffd252a HighSpeedAnalogIn/HighSpeedAnalogIn.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/HighSpeedAnalogIn/HighSpeedAnalogIn.h	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,35 @@
+#ifndef HIGH_SPEED_ANALOG_IN_H
+#define HIGH_SPEED_ANALOG_IN_H
+
+#include "mbed.h"
+
+class HighSpeedAnalogIn {
+public:
+
+    HighSpeedAnalogIn(PinName pin0, PinName pin1 = NC, PinName pin2 = NC, PinName pin3 = NC, PinName pin4 = NC, PinName pin5 = NC);
+    ~HighSpeedAnalogIn();
+    float read(PinName pin);
+    unsigned short read_u16(PinName pin);
+
+private:
+
+    HighSpeedAnalogIn();
+    uint32_t _adc_data[8];
+
+    static const int XTAL_FREQ = 12000000;
+    static const int MAX_ADC_CLOCK = 13000000;
+    static const int CLKS_PER_SAMPLE = 64;
+    
+    static HighSpeedAnalogIn *instance;
+    static int refcnt;
+
+    static void static_adcisr(void);
+
+    int get_channel(PinName pin);
+    uint32_t get_data(PinName pin);
+    void adcisr(void);
+    void setup(PinName pin, int state);
+    void interrupt_state(PinName pin, int state);
+};
+
+#endif

diff -r 000000000000 -r f8571ffd252a PowerControl/EthernetPowerControl.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/PowerControl/EthernetPowerControl.cpp	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,138 @@
+#include "EthernetPowerControl.h"
+
+static void write_PHY (unsigned int PhyReg, unsigned short Value) {
+   /* Write a data 'Value' to PHY register 'PhyReg'. */
+   unsigned int tout;
+   /* Hardware MII Management for LPC176x devices. */
+   LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+   LPC_EMAC->MWTD = Value;
+
+   /* Wait utill operation completed */
+   for (tout = 0; tout < MII_WR_TOUT; tout++) {
+      if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+         break;
+      }
+   }
+}
+
+static unsigned short read_PHY (unsigned int PhyReg) {
+   /* Read a PHY register 'PhyReg'. */
+   unsigned int tout, val;
+
+   LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+   LPC_EMAC->MCMD = MCMD_READ;
+
+   /* Wait until operation completed */
+   for (tout = 0; tout < MII_RD_TOUT; tout++) {
+      if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
+         break;
+      }
+   }
+   LPC_EMAC->MCMD = 0;
+   val = LPC_EMAC->MRDD;
+   
+   return (val);
+}
+
+void EMAC_Init()
+{
+  unsigned int tout,regv;
+  /* Power Up the EMAC controller. */
+  Peripheral_PowerUp(LPC1768_PCONP_PCENET);
+  
+  LPC_PINCON->PINSEL2 = 0x50150105;
+  LPC_PINCON->PINSEL3 &= ~0x0000000F;
+  LPC_PINCON->PINSEL3 |= 0x00000005;
+
+  /* Reset all EMAC internal modules. */
+  LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
+             MAC1_SIM_RES | MAC1_SOFT_RES;
+  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
+
+  /* A short delay after reset. */
+  for (tout = 100; tout; tout--);
+
+  /* Initialize MAC control registers. */
+  LPC_EMAC->MAC1 = MAC1_PASS_ALL;
+  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+  LPC_EMAC->MAXF = ETH_MAX_FLEN;
+  LPC_EMAC->CLRT = CLRT_DEF;
+  LPC_EMAC->IPGR = IPGR_DEF;
+
+  /* Enable Reduced MII interface. */
+  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
+
+  /* Reset Reduced MII Logic. */
+  LPC_EMAC->SUPP = SUPP_RES_RMII;
+  for (tout = 100; tout; tout--);
+  LPC_EMAC->SUPP = 0;
+
+  /* Put the DP83848C in reset mode */
+  write_PHY (PHY_REG_BMCR, 0x8000);
+
+  /* Wait for hardware reset to end. */
+  for (tout = 0; tout < 0x100000; tout++) {
+    regv = read_PHY (PHY_REG_BMCR);
+    if (!(regv & 0x8000)) {
+      /* Reset complete */
+      break;
+    }
+  }
+}
+
+
+void PHY_PowerDown()
+{
+    if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+        EMAC_Init(); //init EMAC if it is not already init'd
+    
+    unsigned int regv;
+    regv = read_PHY(PHY_REG_BMCR);
+    write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
+    regv = read_PHY(PHY_REG_BMCR);
+    
+    //shouldn't need the EMAC now.
+    Peripheral_PowerDown(LPC1768_PCONP_PCENET);
+    
+    //and turn off the PHY OSC
+     LPC_GPIO1->FIODIR |= 0x8000000;
+     LPC_GPIO1->FIOCLR = 0x8000000;
+}
+
+void PHY_PowerUp()
+{   
+    if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+        EMAC_Init(); //init EMAC if it is not already init'd
+        
+    LPC_GPIO1->FIODIR |= 0x8000000;
+    LPC_GPIO1->FIOSET = 0x8000000;
+    
+    //wait for osc to be stable
+    wait_ms(200);
+    
+    unsigned int regv;
+    regv = read_PHY(PHY_REG_BMCR);
+    write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
+    regv = read_PHY(PHY_REG_BMCR);
+}
+
+void PHY_EnergyDetect_Enable()
+{
+    if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+        EMAC_Init(); //init EMAC if it is not already init'd
+        
+    unsigned int regv;
+    regv = read_PHY(PHY_REG_EDCR);
+    write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
+    regv = read_PHY(PHY_REG_EDCR);   
+}
+
+void PHY_EnergyDetect_Disable()
+{
+    if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
+        EMAC_Init(); //init EMAC if it is not already init'd
+    unsigned int regv;
+    regv = read_PHY(PHY_REG_EDCR);
+    write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
+    regv = read_PHY(PHY_REG_EDCR);   
+}
\ No newline at end of file

diff -r 000000000000 -r f8571ffd252a PowerControl/EthernetPowerControl.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/PowerControl/EthernetPowerControl.h	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,299 @@
+/* mbed PowerControl Library
+  * Copyright (c) 2010 Michael Wei
+  */ 
+  
+#ifndef MBED_POWERCONTROL_ETH_H 
+#define MBED_POWERCONTROL_ETH_H 
+
+#include "mbed.h"
+#include "PowerControl.h"
+
+#define PHY_REG_BMCR_POWERDOWN    0xB
+#define PHY_REG_EDCR_ENABLE       0xF
+
+
+void EMAC_Init();
+static unsigned short read_PHY (unsigned int PhyReg);
+static void write_PHY (unsigned int PhyReg, unsigned short Value);
+
+void PHY_PowerDown(void);
+void PHY_PowerUp(void);
+void PHY_EnergyDetect_Enable(void);
+void PHY_EnergyDetect_Disable(void);
+
+//From NXP Sample Code .... Probably from KEIL sample code
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
+#define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
+#define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
+#define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
+
+#define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
+
+/* EMAC variables located in 16K Ethernet SRAM */
+#define RX_DESC_BASE        0x20080000
+#define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
+#define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
+#define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
+#define RX_BUF_BASE         (TX_STAT_BASE + NUM_TX_FRAG*4)
+#define TX_BUF_BASE         (RX_BUF_BASE  + NUM_RX_FRAG*ETH_FRAG_SIZE)
+
+/* RX and TX descriptor and status definitions. */
+#define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))
+#define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
+#define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))
+#define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
+#define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))
+#define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
+#define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))
+#define RX_BUF(i)           (RX_BUF_BASE + ETH_FRAG_SIZE*i)
+#define TX_BUF(i)           (TX_BUF_BASE + ETH_FRAG_SIZE*i)
+
+/* MAC Configuration Register 1 */
+#define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
+#define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
+#define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
+#define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
+#define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
+#define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
+#define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
+#define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
+#define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
+#define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
+#define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
+
+/* MAC Configuration Register 2 */
+#define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
+#define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
+#define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
+#define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
+#define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
+#define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
+#define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
+#define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
+#define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
+#define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
+#define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
+#define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
+#define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
+
+/* Back-to-Back Inter-Packet-Gap Register */
+#define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
+#define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
+
+/* Non Back-to-Back Inter-Packet-Gap Register */
+#define IPGR_DEF            0x00000012  /* Recommended value                 */
+
+/* Collision Window/Retry Register */
+#define CLRT_DEF            0x0000370F  /* Default value                     */
+
+/* PHY Support Register */
+#define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
+#define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
+
+/* Test Register */
+#define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
+#define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
+#define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
+
+/* MII Management Configuration Register */
+#define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
+#define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
+#define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */
+#define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
+
+/* MII Management Command Register */
+#define MCMD_READ           0x00000001  /* MII Read                          */
+#define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
+
+#define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
+#define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
+
+/* MII Management Address Register */
+#define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
+#define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
+
+/* MII Management Indicators Register */
+#define MIND_BUSY           0x00000001  /* MII is Busy                       */
+#define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
+#define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
+#define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
+
+/* Command Register */
+#define CR_RX_EN            0x00000001  /* Enable Receive                    */
+#define CR_TX_EN            0x00000002  /* Enable Transmit                   */
+#define CR_REG_RES          0x00000008  /* Reset Host Registers              */
+#define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
+#define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
+#define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
+#define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
+#define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
+#define CR_RMII             0x00000200  /* Reduced MII Interface             */
+#define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
+
+/* Status Register */
+#define SR_RX_EN            0x00000001  /* Enable Receive                    */
+#define SR_TX_EN            0x00000002  /* Enable Transmit                   */
+
+/* Transmit Status Vector 0 Register */
+#define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
+#define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
+#define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
+#define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
+#define TSV0_MCAST          0x00000010  /* Multicast Destination             */
+#define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
+#define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
+#define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
+#define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
+#define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
+#define TSV0_GIANT          0x00000400  /* Giant Frame                       */
+#define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
+#define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
+#define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
+#define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
+#define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
+#define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
+
+/* Transmit Status Vector 1 Register */
+#define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
+#define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
+
+/* Receive Status Vector Register */
+#define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
+#define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
+#define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
+#define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
+#define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
+#define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
+#define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
+#define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
+#define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
+#define RSV_MCAST           0x01000000  /* Multicast Frame                   */
+#define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
+#define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
+#define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
+#define RSV_PAUSE           0x10000000  /* Pause Frame                       */
+#define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
+#define RSV_VLAN            0x40000000  /* VLAN Frame                        */
+
+/* Flow Control Counter Register */
+#define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
+#define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
+
+/* Flow Control Status Register */
+#define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
+
+/* Receive Filter Control Register */
+#define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
+#define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
+#define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
+#define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
+#define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
+#define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
+#define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
+#define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
+
+/* Receive Filter WoL Status/Clear Registers */
+#define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
+#define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
+#define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
+#define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
+#define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
+#define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
+#define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
+#define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
+
+/* Interrupt Status/Enable/Clear/Set Registers */
+#define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
+#define INT_RX_ERR          0x00000002  /* Receive Error                     */
+#define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
+#define INT_RX_DONE         0x00000008  /* Receive Done                      */
+#define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
+#define INT_TX_ERR          0x00000020  /* Transmit Error                    */
+#define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
+#define INT_TX_DONE         0x00000080  /* Transmit Done                     */
+#define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
+#define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
+
+/* Power Down Register */
+#define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
+
+/* RX Descriptor Control Word */
+#define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
+#define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
+
+/* RX Status Hash CRC Word */
+#define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
+#define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
+
+/* RX Status Information Word */
+#define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
+#define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
+#define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
+#define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
+#define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
+#define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
+#define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
+#define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
+#define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
+#define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
+#define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
+#define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
+#define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
+#define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
+#define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+#define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \
+                            RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
+
+/* TX Descriptor Control Word */
+#define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
+#define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
+#define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
+#define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
+#define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
+#define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
+#define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
+
+/* TX Status Information Word */
+#define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
+#define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
+#define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
+#define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
+#define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
+#define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
+#define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
+#define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
+
+/* DP83848C PHY Registers */
+#define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
+#define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
+#define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
+#define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
+#define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
+#define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
+#define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
+#define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
+
+/* PHY Extended Registers */
+#define PHY_REG_STS         0x10        /* Status Register                   */
+#define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
+#define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
+#define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
+#define PHY_REG_RECR        0x15        /* Receive Error Counter             */
+#define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
+#define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
+#define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
+#define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
+#define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
+#define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
+#define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
+
+#define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
+#define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
+#define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
+#define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
+#define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
+
+#define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
+#define DP83848C_ID         0x20005C90  /* PHY Identifier                    */
+#endif
\ No newline at end of file

diff -r 000000000000 -r f8571ffd252a PowerControl/PowerControl.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/PowerControl/PowerControl.h	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,192 @@
+/* mbed PowerControl Library
+  * Copyright (c) 2010 Michael Wei
+  */ 
+  
+#ifndef MBED_POWERCONTROL_H 
+#define MBED_POWERCONTROL_H 
+
+//shouldn't have to include, but fixes weird problems with defines
+#include "LPC1768/LPC17xx.h"
+
+//System Control Register
+// bit 0: Reserved
+// bit 1: Sleep on Exit
+#define LPC1768_SCR_SLEEPONEXIT     0x2
+// bit 2: Deep Sleep
+#define LPC1768_SCR_SLEEPDEEP       0x4
+// bit 3: Resereved
+// bit 4: Send on Pending
+#define LPC1768_SCR_SEVONPEND        0x10
+// bit 5-31: Reserved
+
+//Power Control Register
+// bit 0: Power mode control bit 0 (power-down mode)
+#define LPC1768_PCON_PM0            0x1
+// bit 1: Power mode control bit 1 (deep power-down mode)
+#define LPC1768_PCON_PM1            0x2
+// bit 2: Brown-out reduced power mode
+#define LPC1768_PCON_BODRPM         0x4
+// bit 3: Brown-out global disable
+#define LPC1768_PCON_BOGD           0x8
+// bit 4: Brown-out reset disable
+#define LPC1768_PCON_BORD           0x10
+// bit 5-7 : Reserved
+// bit 8: Sleep Mode Entry Flag
+#define LPC1768_PCON_SMFLAG         0x100
+// bit 9: Deep Sleep Entry Flag
+#define LPC1768_PCON_DSFLAG         0x200
+// bit 10: Power Down Entry Flag
+#define LPC1768_PCON_PDFLAG         0x400
+// bit 11: Deep Power Down Entry Flag
+#define LPC1768_PCON_DPDFLAG        0x800
+// bit 12-31: Reserved
+
+//"Sleep Mode" (WFI).
+inline void Sleep(void)
+{
+    __WFI();
+}
+
+//"Deep Sleep" Mode
+inline void DeepSleep(void)
+{
+   SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
+   __WFI();
+}
+
+//"Power-Down" Mode
+inline void PowerDown(void)
+{
+   SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
+   LPC_SC->PCON &= ~LPC1768_PCON_PM1;
+   LPC_SC->PCON |= LPC1768_PCON_PM0;
+   __WFI();
+   //reset back to normal
+  LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
+}
+
+//"Deep Power-Down" Mode
+inline void DeepPowerDown(void)
+{
+   SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
+   LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
+   __WFI();
+   //reset back to normal
+  LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
+}
+
+//shut down BOD during power-down/deep sleep
+inline void BrownOut_ReducedPowerMode_Enable(void)
+{
+    LPC_SC->PCON |= LPC1768_PCON_BODRPM;
+}
+
+//turn on BOD during power-down/deep sleep
+inline void BrownOut_ReducedPowerMode_Disable(void)
+{
+    LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
+}
+
+//turn off brown out circutry
+inline void BrownOut_Global_Disable(void)
+{
+    LPC_SC->PCON |= LPC1768_PCON_BOGD;
+}
+
+//turn on brown out circutry
+inline void BrownOut_Global_Enable(void)
+{
+    LPC_SC->PCON &= !LPC1768_PCON_BOGD;
+}
+
+//turn off brown out reset circutry
+inline void BrownOut_Reset_Disable(void)
+{
+    LPC_SC->PCON |= LPC1768_PCON_BORD;
+}
+
+//turn on brown outreset  circutry
+inline void BrownOut_Reset_Enable(void)
+{
+    LPC_SC->PCON &= ~LPC1768_PCON_BORD;
+}
+//Peripheral Control Register
+// bit 0: Reserved
+// bit 1: PCTIM0: Timer/Counter 0 power/clock enable
+#define LPC1768_PCONP_PCTIM0        0x2
+// bit 2: PCTIM1: Timer/Counter 1 power/clock enable
+#define LPC1768_PCONP_PCTIM1        0x4
+// bit 3: PCUART0: UART 0 power/clock enable
+#define LPC1768_PCONP_PCUART0       0x8
+// bit 4: PCUART1: UART 1 power/clock enable
+#define LPC1768_PCONP_PCUART1       0x10
+// bit 5: Reserved
+// bit 6: PCPWM1: PWM 1 power/clock enable
+#define LPC1768_PCONP_PCPWM1        0x40
+// bit 7: PCI2C0: I2C interface 0 power/clock enable
+#define LPC1768_PCONP_PCI2C0        0x80
+// bit 8: PCSPI: SPI interface power/clock enable
+#define LPC1768_PCONP_PCSPI         0x100
+// bit 9: PCRTC: RTC power/clock enable
+#define LPC1768_PCONP_PCRTC         0x200
+// bit 10: PCSSP1: SSP interface 1 power/clock enable
+#define LPC1768_PCONP_PCSSP1        0x400
+// bit 11: Reserved
+// bit 12: PCADC: A/D converter power/clock enable
+#define LPC1768_PCONP_PCADC         0x1000
+// bit 13: PCCAN1: CAN controller 1 power/clock enable
+#define LPC1768_PCONP_PCCAN1        0x2000
+// bit 14: PCCAN2: CAN controller 2 power/clock enable
+#define LPC1768_PCONP_PCCAN2        0x4000
+// bit 15: PCGPIO: GPIOs power/clock enable
+#define LPC1768_PCONP_PCGPIO        0x8000
+// bit 16: PCRIT: Repetitive interrupt timer power/clock enable
+#define LPC1768_PCONP_PCRIT         0x10000
+// bit 17: PCMCPWM: Motor control PWM power/clock enable
+#define LPC1768_PCONP_PCMCPWM       0x20000
+// bit 18: PCQEI: Quadrature encoder interface power/clock enable
+#define LPC1768_PCONP_PCQEI         0x40000
+// bit 19: PCI2C1: I2C interface 1 power/clock enable
+#define LPC1768_PCONP_PCI2C1        0x80000
+// bit 20: Reserved
+// bit 21: PCSSP0: SSP interface 0 power/clock enable
+#define LPC1768_PCONP_PCSSP0        0x200000
+// bit 22: PCTIM2: Timer 2 power/clock enable
+#define LPC1768_PCONP_PCTIM2        0x400000
+// bit 23: PCTIM3: Timer 3 power/clock enable
+#define LPC1768_PCONP_PCQTIM3       0x800000
+// bit 24: PCUART2: UART 2 power/clock enable
+#define LPC1768_PCONP_PCUART2       0x1000000
+// bit 25: PCUART3: UART 3 power/clock enable
+#define LPC1768_PCONP_PCUART3       0x2000000
+// bit 26: PCI2C2: I2C interface 2 power/clock enable
+#define LPC1768_PCONP_PCI2C2        0x4000000
+// bit 27: PCI2S: I2S interface power/clock enable
+#define LPC1768_PCONP_PCI2S         0x8000000
+// bit 28: Reserved
+// bit 29: PCGPDMA: GP DMA function power/clock enable
+#define LPC1768_PCONP_PCGPDMA       0x20000000
+// bit 30: PCENET: Ethernet block power/clock enable
+#define LPC1768_PCONP_PCENET        0x40000000
+// bit 31: PCUSB: USB interface power/clock enable
+#define LPC1768_PCONP_PCUSB         0x80000000
+
+//Powers Up specified Peripheral(s)
+inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
+{
+    return LPC_SC->PCONP |= bitMask;
+}   
+
+//Powers Down specified Peripheral(s) 
+inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
+{
+    return LPC_SC->PCONP &= ~bitMask;
+}
+
+//returns if the peripheral is on or off
+inline bool Peripheral_GetStatus(unsigned int peripheral)
+{
+    return (LPC_SC->PCONP & peripheral) ? true : false;
+}
+
+#endif
\ No newline at end of file

diff -r 000000000000 -r f8571ffd252a TB6612/TB6612.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TB6612/TB6612.cpp	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,71 @@
+/**
+ * Motor Driver TB6612 Control Library
+ *
+ * -- TB6612 is a device of the TOSHIBA. 
+ *
+ * Copyright (C) 2012 Junichi Katsu (JKSOFT) 
+ */
+
+
+#include "TB6612.h"
+
+// TB6612 Class Constructor
+TB6612::TB6612(PinName pwm, PinName fwd, PinName rev):
+        _pwm(pwm), _fwd(fwd), _rev(rev) {
+
+    _fwd = 0;
+    _rev = 0;
+    _pwm = 0.0;
+    _pwm.period(0.001);
+    
+    bspeed = 0.0;
+    timer_flag = false;
+}
+
+// Speed Control
+//  arg
+//   float speed -1.0 - 0.0 - 1.0
+void TB6612::speed(float speed) {
+    
+    if( timer_flag == true )    return;
+    
+    bspeed = speed;
+    
+    if( speed > 0.0 )
+    {
+        _pwm = speed;
+        _fwd = 1;
+        _rev = 0;
+    }
+    else if( speed < 0.0 )
+    {
+        _pwm = -speed;
+        _fwd = 0;
+        _rev = 1;
+    }
+    else
+    {
+        _fwd = 1;
+        _rev = 1;
+    }
+}
+
+
+// Speed Control with time-out
+//  arg
+//   float sspeed:-1.0 - 0.0 - 1.0
+//   float time  :0.0-
+void TB6612::move(float sspeed , float time)
+{
+    speed(sspeed);
+    timer_flag = true;
+    timer.attach(this,&TB6612::timeout,time);
+}
+
+
+void TB6612::timeout()
+{
+    timer_flag = false;
+    speed(bspeed);
+}
+

diff -r 000000000000 -r f8571ffd252a TB6612/TB6612.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TB6612/TB6612.h	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,35 @@
+/**
+ * Motor Driver TB6612 Control Library
+ *
+ * -- TB6612 is a device of the rohm. 
+ *
+ * Copyright (C) 2012 Junichi Katsu (JKSOFT) 
+ */
+
+#ifndef MBED_TB6612_H
+#define MBED_TB6612_H
+
+#include "mbed.h"
+
+class TB6612 {
+public:
+    TB6612(PinName pwm, PinName fwd, PinName rev);
+    void speed(float speed);
+    void move(float speed , float time);
+    void operator= ( float value )
+    {
+        speed(value);
+    }
+    
+protected:
+    PwmOut _pwm;
+    DigitalOut _fwd;
+    DigitalOut _rev;
+    Timeout timer;
+    float    bspeed;
+    bool     timer_flag;
+    void timeout();
+
+};
+
+#endif

diff -r 000000000000 -r f8571ffd252a wallbot.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/wallbot.cpp	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,127 @@
+/* wallbot Library
+ *
+ * wallbot.cpp
+ *
+ * Copyright (c) 2010-2013 jksoft
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mbed.h"
+#include "wallbot.h"
+
+
+wallbot::wallbot() :  _right(p22,p14,p13) , _left(p21,p12,p11) , _ain(p15, p16, p17, p18), _left_sw(p29),_right_sw(p30)  {
+    PHY_PowerDown();
+
+	_right = 0.0;
+    _left = 0.0;
+	
+	_left_sw.mode(PullUp);
+	_right_sw.mode(PullUp);
+	
+	_floorSensorThreshold = SENSOR_THRESHOLD;
+}
+
+void wallbot::left_motor (float speed) {
+    _left = speed;
+}
+
+void wallbot::right_motor (float speed) {
+    _right = speed;
+}
+
+void wallbot::forward (float speed) {
+    _left = speed;
+	_right = speed;
+}
+
+void wallbot::backward (float speed) {
+    _left = -1.0*speed;
+	_right = -1.0*speed;
+}
+
+void wallbot::left (float speed) {
+    _left = -1.0*speed;
+	_right = speed;
+}
+
+void wallbot::right (float speed) {
+    _left = speed;
+	_right = -1.0*speed;
+}
+
+void wallbot::stop (void) {
+    _right = 0.0;
+    _left = 0.0;
+}
+
+
+float wallbot::GetLinePosition(void) {
+    float ret = 0.0;
+    int bit = 0;
+    int value[4];
+    
+    value[0] = _ain.read_u16(p15);
+    value[1] = _ain.read_u16(p16);
+    value[2] = _ain.read_u16(p17);
+    value[3] = _ain.read_u16(p18);
+    
+    if( value[0] > _floorSensorThreshold ) bit |= 0x01;
+    if( value[1] > _floorSensorThreshold ) bit |= 0x02;
+    if( value[2] > _floorSensorThreshold ) bit |= 0x04;
+    if( value[3] > _floorSensorThreshold ) bit |= 0x08;
+    
+    switch(bit)
+    {
+    case 0x01:    ret = 1.0;      break;
+    case 0x03:    ret = 0.66;     break;
+    case 0x02:    ret = 0.33;     break;
+    case 0x04:    ret = -0.33;    break;
+    case 0x0C:    ret = -0.66;    break;
+    case 0x08:    ret = -1.0;     break;
+    default:    ret = 0.0;        break;
+    }
+    
+    return(ret);
+}
+
+void wallbot::GetLinePosition(int *bit) {
+    int value[4];
+    
+    *bit = 0;
+    
+    value[0] = _ain.read_u16(p15);
+    value[1] = _ain.read_u16(p16);
+    value[2] = _ain.read_u16(p17);
+    value[3] = _ain.read_u16(p18);
+    
+    if( value[0] > _floorSensorThreshold ) *bit |= 0x01;
+    if( value[1] > _floorSensorThreshold ) *bit |= 0x02;
+    if( value[2] > _floorSensorThreshold ) *bit |= 0x04;
+    if( value[3] > _floorSensorThreshold ) *bit |= 0x08;
+}
+
+int wallbot::GetLeftSw(void) {
+	return(!_left_sw);
+}
+
+int wallbot::GetRightSw(void) {
+	return(!_right_sw);
+}

diff -r 000000000000 -r f8571ffd252a wallbot.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/wallbot.h	Sun Jul 28 08:20:17 2013 +0000
@@ -0,0 +1,149 @@
+/* mbed wallbot Library
+ *
+ * wallbot.h
+ *
+ * Copyright (c) 2010-2013 jksoft
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef WALLBOT_H
+#define WALLBOT_H
+
+#include "mbed.h"
+#include "HighSpeedAnalogIn.h"
+#include "EthernetPowerControl.h"
+#include "TB6612.h"
+
+#define SENSOR_NOMAL	0
+#define SENSOR_EXT		1
+#define SENSOR_THRESHOLD 2500
+/** wallbot control class
+ *
+ * Example:
+ * @code
+ * // Drive the wwallbot forward, turn left, back, turn right, at half speed for half a second
+
+#include "mbed.h"
+#include "wallbot.h"
+
+wallbot wb;
+ 
+int main() {
+
+	wait(0.5);
+	
+	wb.forward(0.5);
+	wait (0.5);
+	wb.left(0.5);
+	wait (0.5);
+	wb.backward(0.5);
+	wait (0.5);
+	wb.right(0.5);
+	wait (0.5);
+	
+	wb.stop();
+
+ }
+ * @endcode
+ */
+class wallbot  {
+
+    // Public functions
+public:
+
+    /** Create the wallbot object connected to the default pins
+     */
+    wallbot();
+
+    /** Directly control the speed and direction of the left motor
+     *
+     * @param speed A normalised number -1.0 - 1.0 represents the full range.
+     */
+    void left_motor (float speed);
+
+    /** Directly control the speed and direction of the right motor
+     *
+     * @param speed A normalised number -1.0 - 1.0 represents the full range.
+     */
+    void right_motor (float speed);
+
+    /** Drive both motors forward as the same speed
+     *
+     * @param speed A normalised number 0 - 1.0 represents the full range.
+     */
+    void forward (float speed);
+
+    /** Drive both motors backward as the same speed
+     *
+     * @param speed A normalised number 0 - 1.0 represents the full range.
+     */
+    void backward (float speed);
+
+    /** Drive left motor backwards and right motor forwards at the same speed to turn on the spot
+     *
+     * @param speed A normalised number 0 - 1.0 represents the full range.
+     */
+    void left (float speed);
+
+    /** Drive left motor forward and right motor backwards at the same speed to turn on the spot
+     * @param speed A normalised number 0 - 1.0 represents the full range.
+     */
+    void right (float speed);
+
+    /** Stop both motors
+     *
+     */
+    void stop (void);
+	
+    /** Get floorline position.(float value return.)
+     *
+     */	
+	float GetLinePosition(void);
+
+    /** Get floorline position.(bit value return.)
+     *
+     */	
+	void GetLinePosition(int *bit);
+	
+    /** Get left switch .(switch OFF:0 or ON:1 return.)
+     *
+     */	
+	int GetLeftSw(void);
+
+    /** Get GetRightSw switch .(switch OFF:0 or ON:1 return.)
+     *
+     */	
+	int GetRightSw(void);
+	
+	private :
+
+	TB6612 _right;
+	TB6612 _left;
+
+	HighSpeedAnalogIn _ain;
+	
+	DigitalIn _left_sw;
+	DigitalIn _right_sw;
+
+	int _floorSensorThreshold;
+    
+};
+
+#endif
\ No newline at end of file