Diff: FPGA_bus.cpp

Revision:

6:e68defb7b775

Parent:

5:64c677e9995c

Child:

7:c0bef9c1f5d5

Child:

8:65d1b1a7bfcc

diff -r 64c677e9995c -r e68defb7b775 FPGA_bus.cpp
--- a/FPGA_bus.cpp	Thu Apr 18 22:59:26 2019 +0000
+++ b/FPGA_bus.cpp	Wed May 08 16:41:44 2019 +0000
@@ -191,14 +191,14 @@
 void FPGA_bus::set_RC_period(void)
 {
     do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), 1000000, &data, &status);
-    global_FPGA_unit_error_flag = status;;
+    global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus::set_RC_period(uint32_t duty_uS)
 {
     uint32_t nos_20nS_ticks = ((duty_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS);
     do_transaction(WRITE_REGISTER_CMD, (RC_BASE + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status);
-    global_FPGA_unit_error_flag = status;;
+    global_FPGA_unit_error_flag = status;
 }
 
 void FPGA_bus :: set_RC_pulse(uint32_t channel, uint32_t pulse_uS)
@@ -238,4 +238,17 @@
     do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
     global_FPGA_unit_error_flag = status;
     return data;
+}
+
+uint32_t FPGA_bus::get_SYS_data(void)
+{
+    do_transaction(READ_REGISTER_CMD, SYS_DATA_REG_ADDR, NULL, &data, &status);
+    sys_data.major_version          = (data & 0x0000000F);
+    sys_data.minor_version          = (data >> 4) & 0x0000000F;
+    sys_data.number_of_PWM_channels = (data >> 8) & 0x0000000F;
+    sys_data.number_of_QE_channels  = (data >> 8) & 0x0000000F;
+    sys_data.number_of_RC_channels  = (data >> 8) & 0x0000000F;
+    
+    global_FPGA_unit_error_flag = status;
+    return data;
 }
\ No newline at end of file