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Diff: FPGA_bus.cpp
- Revision:
- 1:b819a72b3b5d
- Parent:
- 0:9600ed6fd725
- Child:
- 2:fd5c862b86db
diff -r 9600ed6fd725 -r b819a72b3b5d FPGA_bus.cpp --- a/FPGA_bus.cpp Wed Feb 20 16:42:55 2019 +0000 +++ b/FPGA_bus.cpp Wed Apr 17 14:32:22 2019 +0000 @@ -65,6 +65,8 @@ wait_us(20); async_uP_reset = HIGH; wait_us(20); + + global_FPGA_unit_error_flag = NO_ERROR; } void FPGA_bus::do_start(void) @@ -152,32 +154,60 @@ return 0; } -uint32_t FPGA_bus::set_PWM_period(uint32_t channel, float frequency) +void FPGA_bus::set_PWM_period(uint32_t channel, float frequency) { uint32_t period_value = (uint32_t)(1000000/(20 * frequency)); do_transaction(WRITE_REGISTER_CMD, (channel + PWM_PERIOD) , period_value, &data, &status); sys_data.PWM_period_value[channel] = period_value; - return status; + global_FPGA_unit_error_flag = status; } -uint32_t FPGA_bus::set_PWM_duty(uint32_t channel, float percentage) +void FPGA_bus::set_PWM_duty(uint32_t channel, float percentage) { uint32_t duty_value = (uint32_t)((sys_data.PWM_period_value[channel] * percentage) / 100); do_transaction(WRITE_REGISTER_CMD, (channel + PWM_ON_TIME) , duty_value, &data, &status); sys_data.PWM_duty_value[channel] = duty_value; - return status; + global_FPGA_unit_error_flag = status;; } -uint32_t FPGA_bus::PWM_enable(uint32_t channel) +void FPGA_bus::PWM_enable(uint32_t channel) { do_transaction(WRITE_REGISTER_CMD, (channel + PWM_CONFIG) , 1, &data, &status); // sys_data.PWM_duty_value[channel] = duty_value; - return status; + global_FPGA_unit_error_flag = status;; } -uint32_t FPGA_bus::PWM_config(uint32_t channel, uint32_t config_value) +void FPGA_bus::PWM_config(uint32_t channel, uint32_t config_value) { do_transaction(WRITE_REGISTER_CMD, (channel + PWM_CONFIG) , config_value, &data, &status); sys_data.PWM_duty_value[channel] = config_value; - return status; + global_FPGA_unit_error_flag = status;; +} + +void FPGA_bus::set_RC_duty(void) +{ + do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_PERIOD), 1000000, &data, &status); + global_FPGA_unit_error_flag = status;; +} + +void FPGA_bus::set_RC_duty(uint32_t duty_uS) +{ + uint32_t nos_20nS_ticks = ((duty_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS); + do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status); + global_FPGA_unit_error_flag = status;; +} + +void FPGA_bus :: set_RC_pulse(uint32_t channel, uint32_t pulse_uS) +{ + uint32_t nos_20nS_ticks = ((pulse_uS * nS_IN_uS)/FPGA_CLOCK_PERIOD_nS); + do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_PERIOD), nos_20nS_ticks, &data, &status); + global_FPGA_unit_error_flag = status;; +} + +void FPGA_bus ::enable_RC_channel(uint32_t channel) +{ + do_transaction(READ_REGISTER_CMD, (RC_0 + RC_SERVO_CONFIG), NULL, &data, &status); + int32_t config = data || (0x01 << channel); + do_transaction(WRITE_REGISTER_CMD, (RC_0 + RC_SERVO_CONFIG), config, &data, &status); + global_FPGA_unit_error_flag = status; } \ No newline at end of file