Diff: FPGA_bus.cpp

Revision:

10:56a045a02047

Parent:

9:6fe95fb0c7ea

Child:

12:b9b4ff729fef

diff -r 6fe95fb0c7ea -r 56a045a02047 FPGA_bus.cpp
--- a/FPGA_bus.cpp	Wed May 29 15:08:52 2019 +0000
+++ b/FPGA_bus.cpp	Sat May 02 16:26:32 2020 +0000
@@ -236,11 +236,11 @@
     uint32_t register_base = (QE_BASE + (channel * NOS_QE_REGISTERS));
     do_transaction(WRITE_REGISTER_CMD, (register_base + QE_SIM_PHASE_TIME), phase_time, &data, &status);
     global_FPGA_unit_error_flag = status;
- //   if (status != NO_ERROR) {
- //       return;
- //   }
-//    do_transaction(WRITE_REGISTER_CMD, (register_base + QE_CONFIG), config_value, &data, &status);
-//    global_FPGA_unit_error_flag = status;
+    if (status != NO_ERROR) {
+        return;
+    }
+    do_transaction(WRITE_REGISTER_CMD, (register_base + QE_CONFIG), config_value, &data, &status);
+    global_FPGA_unit_error_flag = status;
 }
 
 uint32_t FPGA_bus::read_speed_measure(uint32_t channel)
@@ -251,6 +251,14 @@
     return data;
 }
 
+uint32_t FPGA_bus::read_count_measure(uint32_t channel)
+{
+    uint32_t register_address = ((QE_BASE + (channel * NOS_QE_REGISTERS)) + QE_COUNT_BUFFER);
+    do_transaction(READ_REGISTER_CMD, register_address, NULL, &data, &status);
+    global_FPGA_unit_error_flag = status;
+    return data;
+}
+
 uint32_t FPGA_bus::get_SYS_data(void)
 {
     do_transaction(READ_REGISTER_CMD, SYS_DATA_REG_ADDR, NULL, &data, &status);