jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

Diff: FPGA_bus.h

Revision:
22:c47d4177d59c
Parent:
21:6b2b7a0e2d9a
Child:
23:4b391cfd4f2d
--- a/FPGA_bus.h	Tue Jun 16 23:06:04 2020 +0000
+++ b/FPGA_bus.h	Tue Jun 23 11:39:07 2020 +0000
@@ -77,6 +77,7 @@
 #define     nS_IN_uS                1000
 #define     FPGA_CLOCK_PERIOD_nS      20
 #define     uS_DELAY_BEFORE_TEST_HANDSHAKE      25
+#define     HANDSHAKE_TIMEOUT_COUNT      10000
 
 //////////////////////////////////////////////////////////////////////////
 // error codes
@@ -84,6 +85,7 @@
 #define     NO_ERROR      0
 #define     BUS_FAIL_1  -30     // handshake_2 initially HIGH but should be LOW
 #define     BUS_FAIL_2  -31     // handshake_2 not transitioned to HIGH
+#define     BUS_FAIL_3  -32     // handshake_2 not transitioned to HIGH
 
 //////////////////////////////////////////////////////////////////////////
 // typedef structures
@@ -184,6 +186,7 @@
      uint32_t read_speed_measure(uint32_t channel);
      uint32_t read_count_measure(uint32_t channel);
      uint32_t get_SYS_data(void);
+     int32_t  soft_check_bus(void);
 //
 // data
 //   
@@ -225,7 +228,7 @@
                         uint32_t register_data);
     void     do_read(received_packet_t   *buffer);
     void     do_reset(void);
-    int32_t  check_bus(void);
+    int32_t  hard_check_bus(void);
     void     update_FPGA_register_pointers(void);
 //
 // Hardware digital I/O lines