Diff: FPGA_bus.h

Revision:

9:6fe95fb0c7ea

Parent:

8:65d1b1a7bfcc

Child:

10:56a045a02047

--- a/FPGA_bus.h	Sun May 12 21:10:50 2019 +0000
+++ b/FPGA_bus.h	Wed May 29 15:08:52 2019 +0000
@@ -20,6 +20,8 @@
 #define ASYNC_UP_ACK_PIN          PB_4
 #define ASYNC_UP_RESET_PIN        PB_5
 
+#define LOG_PIN                   PB_8
+
 //
 // 
 #define PWM_BASE            1
@@ -40,7 +42,24 @@
 
 #define RC_0                RC_BASE
 
-#define NOS_RECEIVED_PACKET_WORDS  2
+//
+// System can be configured to return ONE or TWO 32-bit values from the FPGA.
+//
+//      first value  : 32-bit data value
+//      second value : 32-bit status value
+//
+// In practice, the status word carries little or no information but consumes
+// four 8-bit transactions between the FPGA and the uP.
+//
+// Uncomment following #define to enable status word to be returned.
+
+//#define INCLUDE_32_BIT_STATUS_RETURN
+
+#ifdef INCLUDE_32_BIT_STATUS_RETURN
+    #define NOS_RECEIVED_PACKET_WORDS  2
+#else
+    #define NOS_RECEIVED_PACKET_WORDS  1
+#endif
 
 #define SET_BUS_INPUT             (GPIOC->MODER = (GPIOC->MODER & 0xFFFF0000))
 #define SET_BUS_OUTPUT            (GPIOC->MODER = ((GPIOC->MODER & 0xFFFF0000) | 0x00005555))
@@ -70,8 +89,8 @@
 } FPGA_packet_t;
 
 typedef union {
-    uint32_t word_data[NOS_RECEIVED_PACKET_WORDS];
-    uint8_t  byte_data[NOS_RECEIVED_PACKET_WORDS << 2];
+    uint32_t word_data[2];    // NOS_RECEIVED_PACKET_WORDS];
+    uint8_t  byte_data[8];    // NOS_RECEIVED_PACKET_WORDS << 2];
 } received_packet_t;
 
 enum {READ_REGISTER_CMD=0, WRITE_REGISTER_CMD=1};
@@ -94,6 +113,7 @@
 //
 // constants to define bits in QE config register
 
+#define  QE_CONFIG_DEFAULT    0x00
 enum {QE_SIG_EXT=0x00, QE_SIG_INT_SIM=0x02};
 enum {QE_INT_SIM_DISABLE=0x0, QE_INT_SIM_ENABLE=0x04};
 enum {QE_SIM_DIR_FORWARD=0x0, QE_SIM_DIR_BACKWARD=0x08};
@@ -107,6 +127,10 @@
 //
 enum {RC_SERVO_PERIOD=0, RC_SERVO_CONFIG=1, RC_SERVO_STATUS=2, RC_SERVO_ON_TIME=3};
 
+//
+// constants to define bits in PWM config register
+
+#define  PWM_CONFIG_DEFAULT    0x00
 enum {PWM_OFF=0x0, PWM_ON=0x1};
 enum {INT_H_BRIDGE_OFF=0x0, INT_H_BRIDGE_ON=0x10000};
 enum {EXT_H_BRIDGE_OFF=0x0, EXT_H_BRIDGE_ON=0x20000};
@@ -131,6 +155,7 @@
      
      void     initialise(void); 
      uint32_t do_command(FPGA_packet_t cmd_packet);
+     void write_register(uint32_t register_addr, uint32_t value);
      void set_PWM_period(uint32_t channel, float frequency);
      void set_PWM_duty(uint32_t channel, float percentage);
      void PWM_enable(uint32_t channel);
@@ -140,7 +165,8 @@
      void set_RC_pulse(uint32_t channel, uint32_t pulse_uS);
      void enable_RC_channel(uint32_t channel);
      void disable_RC_channel(uint32_t channel);
-     void enable_speed_measure(uint32_t channel);
+     void QE_config(uint32_t channel, uint32_t config_value);
+     void enable_speed_measure(uint32_t channel, uint32_t config_value, uint32_t phase_time);
      uint32_t read_speed_measure(uint32_t channel);
      
      uint32_t get_SYS_data(void);
@@ -177,6 +203,8 @@
     DigitalIn  uP_ack;
     DigitalIn  uP_handshake_2;
     
+    DigitalOut log_pin;
+    
     struct SYS_data {
         uint8_t major_version;
         uint8_t minor_version;