Preliminary mbed encoder interface IC class

Dependents:   mbed_QUAD_ENCLIB_TEST Axis Axis_20181108 Axis_version2

include the mbed library with this snippet

#include "mbed.h"
#include "LS7366.h"

SPI spi(p5, p6, p7);   
LS7366 enc1(spi, p19);
LS7366 enc2(spi, p20);
Serial pc(USBTX, USBRX); // tx, rx for serial USB interface to pc

//------------------- MAIN --------------------------------
int main()
{    
    while(1){ 
        pc.printf("enc1 = %ld enc2 = %ld\r\n",enc1.read(), enc2.read());
        wait(.02);
    }//while(1)                        
}//main
Committer:
jebradshaw
Date:
Mon Aug 31 17:13:34 2015 +0000
Revision:
1:c627734cf04c
Parent:
0:c2458154721b
removed secondary operator overload

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jebradshaw 0:c2458154721b 1 // LS7366.h Encoder IC Class Library
jebradshaw 0:c2458154721b 2 // J. Bradshaw 20141030
jebradshaw 0:c2458154721b 3 /* Copyright (c) 2014, jbradshaw (http://mbed.org)
jebradshaw 0:c2458154721b 4 *
jebradshaw 0:c2458154721b 5 * Permission is hereby granted, free of charge, to any person obtaining a copy
jebradshaw 0:c2458154721b 6 * of this software and associated documentation files (the "Software"), to deal
jebradshaw 0:c2458154721b 7 * in the Software without restriction, including without limitation the rights
jebradshaw 0:c2458154721b 8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
jebradshaw 0:c2458154721b 9 * copies of the Software, and to permit persons to whom the Software is
jebradshaw 0:c2458154721b 10 * furnished to do so, subject to the following conditions:
jebradshaw 0:c2458154721b 11 *
jebradshaw 0:c2458154721b 12 * The above copyright notice and this permission notice shall be included in
jebradshaw 0:c2458154721b 13 * all copies or substantial portions of the Software.
jebradshaw 0:c2458154721b 14 *
jebradshaw 0:c2458154721b 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
jebradshaw 0:c2458154721b 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
jebradshaw 0:c2458154721b 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
jebradshaw 0:c2458154721b 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
jebradshaw 0:c2458154721b 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
jebradshaw 0:c2458154721b 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
jebradshaw 0:c2458154721b 21 * THE SOFTWARE.
jebradshaw 0:c2458154721b 22 *
jebradshaw 0:c2458154721b 23 */
jebradshaw 0:c2458154721b 24 #include "mbed.h"
jebradshaw 0:c2458154721b 25
jebradshaw 0:c2458154721b 26 #ifndef LS7366_H
jebradshaw 0:c2458154721b 27 #define LS7366_H
jebradshaw 0:c2458154721b 28
jebradshaw 0:c2458154721b 29 //=============================================================================
jebradshaw 0:c2458154721b 30 // Four commands for the Instruction Register (B7,B6) - LS7366
jebradshaw 0:c2458154721b 31 //=============================================================================
jebradshaw 0:c2458154721b 32 #define CLR 0x00 //Clear Instruction
jebradshaw 0:c2458154721b 33 #define RD 0x01 //Read Instruction
jebradshaw 0:c2458154721b 34 #define WR 0x02 //Write Instruction
jebradshaw 0:c2458154721b 35 #define LOAD 0x03 //Load Instruction
jebradshaw 0:c2458154721b 36
jebradshaw 0:c2458154721b 37 //=============================================================================
jebradshaw 0:c2458154721b 38 // Register to Select from the Instruction Register (B5,B4,B3) - LS7366
jebradshaw 0:c2458154721b 39 //=============================================================================
jebradshaw 0:c2458154721b 40 #define NONE 0x00 //No Register Selected
jebradshaw 0:c2458154721b 41 #define MDR0 0x01 //Mode Register 0
jebradshaw 0:c2458154721b 42 #define MDR1 0x02 //Mode Register 1
jebradshaw 0:c2458154721b 43 #define DTR 0x03 //Data Transfer Register
jebradshaw 0:c2458154721b 44 #define CNTR 0x04 //Software Configurable Counter Register
jebradshaw 0:c2458154721b 45 #define OTR 0x05 //Output Transfer Register
jebradshaw 0:c2458154721b 46 #define STR 0x06 //Status Register
jebradshaw 0:c2458154721b 47 #define NONE_REG 0x07 //No Register Selected
jebradshaw 0:c2458154721b 48
jebradshaw 0:c2458154721b 49 /**
jebradshaw 0:c2458154721b 50 * LS7366 Class.
jebradshaw 0:c2458154721b 51 */
jebradshaw 0:c2458154721b 52
jebradshaw 0:c2458154721b 53 class LS7366{
jebradshaw 0:c2458154721b 54 public:
jebradshaw 0:c2458154721b 55 /**
jebradshaw 0:c2458154721b 56 * Constructor.
jebradshaw 0:c2458154721b 57 * @param spi - spi bus
jebradshaw 0:c2458154721b 58 * @param _cs - pin to use for chip select
jebradshaw 0:c2458154721b 59 */
jebradshaw 0:c2458154721b 60 LS7366(SPI& spi, PinName _cs);
jebradshaw 0:c2458154721b 61 void LS7366_cmd(int inst, int reg);
jebradshaw 0:c2458154721b 62 long LS7366_read_counter();
jebradshaw 0:c2458154721b 63 void LS7366_quad_mode_x4();
jebradshaw 0:c2458154721b 64 void LS7366_reset_counter();
jebradshaw 0:c2458154721b 65 void LS7366_write_DTR(long enc_value);
jebradshaw 0:c2458154721b 66 void write(long wcount); //
jebradshaw 0:c2458154721b 67 long read(void);
jebradshaw 0:c2458154721b 68
jebradshaw 0:c2458154721b 69 long count;
jebradshaw 0:c2458154721b 70 LS7366& operator= (long count);
jebradshaw 1:c627734cf04c 71 // LS7366& LS7366::operator= (LS7366& rhs);
jebradshaw 0:c2458154721b 72 operator long();
jebradshaw 0:c2458154721b 73
jebradshaw 0:c2458154721b 74 private:
jebradshaw 0:c2458154721b 75 SPI _spi;
jebradshaw 0:c2458154721b 76 DigitalOut _cs;
jebradshaw 0:c2458154721b 77 void _init();
jebradshaw 0:c2458154721b 78 };
jebradshaw 0:c2458154721b 79
jebradshaw 0:c2458154721b 80 #endif /* LS7366_H */