NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies:   mbed

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I2S_MODEConf_Type Struct Reference

I2S_MODEConf_Type Struct Reference
[I2S_Public_Types]

I2S mode configuration structure definition. More...

#include <lpc17xx_i2s.h>

Data Fields

uint8_t fpin
 Clock source selection, should be:

  • I2S_CLKSEL_0: Select the fractional rate divider clock output
  • I2S_CLKSEL_2: Select the MCLK signal as the clock source.

uint8_t mcena
 Select four pin mode, should be:

  • I2S_4PIN_ENABLE: 4-pin enable
  • I2S_4PIN_DISABLE: 4-pin disable.

uint8_t Reserved
 Select MCLK mode, should be:

  • I2S_MCLK_ENABLE: MCLK enable for output
  • I2S_MCLK_DISABLE: MCLK disable for output.


Detailed Description

I2S mode configuration structure definition.

Definition at line 253 of file lpc17xx_i2s.h.


Field Documentation

uint8_t fpin

Clock source selection, should be:

  • I2S_CLKSEL_0: Select the fractional rate divider clock output
  • I2S_CLKSEL_2: Select the MCLK signal as the clock source.

Definition at line 257 of file lpc17xx_i2s.h.

uint8_t mcena

Select four pin mode, should be:

  • I2S_4PIN_ENABLE: 4-pin enable
  • I2S_4PIN_DISABLE: 4-pin disable.

Definition at line 260 of file lpc17xx_i2s.h.

uint8_t Reserved

Select MCLK mode, should be:

  • I2S_MCLK_ENABLE: MCLK enable for output
  • I2S_MCLK_DISABLE: MCLK disable for output.

Definition at line 263 of file lpc17xx_i2s.h.