NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
lpc17xx_i2s.h
00001 /***********************************************************************//** 00002 * @file : lpc17xx_i2s.h 00003 * @brief : Contains all macro definitions and function prototypes 00004 * support for I2S firmware library on LPC17xx 00005 * @version : 1.0 00006 * @date : 13. May. 2009 00007 * @author : NguyenCao 00008 ************************************************************************** 00009 * Software that is described herein is for illustrative purposes only 00010 * which provides customers with programming information regarding the 00011 * products. This software is supplied "AS IS" without any warranties. 00012 * NXP Semiconductors assumes no responsibility or liability for the 00013 * use of the software, conveys no license or title under any patent, 00014 * copyright, or mask work right to the product. NXP Semiconductors 00015 * reserves the right to make changes in the software without 00016 * notification. NXP Semiconductors also make no representation or 00017 * warranty that such application will be suitable for the specified 00018 * use without further testing or modification. 00019 **************************************************************************/ 00020 00021 /* Peripheral group ----------------------------------------------------------- */ 00022 /** @defgroup I2S 00023 * @ingroup LPC1700CMSIS_FwLib_Drivers 00024 * @{ 00025 */ 00026 00027 #ifndef LPC17XX_I2S_H_ 00028 #define LPC17XX_I2S_H_ 00029 00030 /* Includes ------------------------------------------------------------------- */ 00031 #include "cmsis.h" 00032 #include "lpc_types.h" 00033 00034 00035 #ifdef __cplusplus 00036 extern "C" 00037 { 00038 #endif 00039 00040 00041 /* Private Macros ------------------------------------------------------------- */ 00042 /** @defgroup I2S_Private_Macros 00043 * @{ 00044 */ 00045 00046 /*********************************************************************//** 00047 * Macro defines for DAO-Digital Audio Output register 00048 **********************************************************************/ 00049 /** @defgroup I2S_REGISTER_BIT_DEFINITION 00050 * @{ 00051 */ 00052 00053 /** I2S wordwide - the number of bytes in data*/ 00054 #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ 00055 #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ 00056 #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ 00057 /** I2S control mono or stereo format */ 00058 #define I2S_DAO_MONO ((uint32_t)(1<<2)) 00059 /** I2S control stop mode */ 00060 #define I2S_DAO_STOP ((uint32_t)(1<<3)) 00061 /** I2S control reset mode */ 00062 #define I2S_DAO_RESET ((uint32_t)(1<<4)) 00063 /** I2S control master/slave mode */ 00064 #define I2S_DAO_SLAVE ((uint32_t)(1<<5)) 00065 /** I2S word select half period minus one */ 00066 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6)) 00067 /** I2S control mute mode */ 00068 #define I2S_DAO_MUTE ((uint32_t)(1<<15)) 00069 00070 /*********************************************************************//** 00071 * Macro defines for DAI-Digital Audio Input register 00072 **********************************************************************/ 00073 /** I2S wordwide - the number of bytes in data*/ 00074 #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ 00075 #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ 00076 #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ 00077 /** I2S control mono or stereo format */ 00078 #define I2S_DAI_MONO ((uint32_t)(1<<2)) 00079 /** I2S control stop mode */ 00080 #define I2S_DAI_STOP ((uint32_t)(1<<3)) 00081 /** I2S control reset mode */ 00082 #define I2S_DAI_RESET ((uint32_t)(1<<4)) 00083 /** I2S control master/slave mode */ 00084 #define I2S_DAI_SLAVE ((uint32_t)(1<<5)) 00085 /** I2S word select half period minus one (9 bits)*/ 00086 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6)) 00087 /** I2S control mute mode */ 00088 #define I2S_DAI_MUTE ((uint32_t)(1<<15)) 00089 00090 /*********************************************************************//** 00091 * Macro defines for STAT register (Status Feedback register) 00092 **********************************************************************/ 00093 /** I2S Status Receive or Transmit Interrupt */ 00094 #define I2S_STATE_IRQ ((uint32_t)(1)) 00095 /** I2S Status Receive or Transmit DMA1 */ 00096 #define I2S_STATE_DMA1 ((uint32_t)(1<<1)) 00097 /** I2S Status Receive or Transmit DMA2 */ 00098 #define I2S_STATE_DMA2 ((uint32_t)(1<<2)) 00099 /** I2S Status Current level of the Receive FIFO (5 bits)*/ 00100 #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8)) 00101 /** I2S Status Current level of the Transmit FIFO (5 bits)*/ 00102 #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16)) 00103 00104 /*********************************************************************//** 00105 * Macro defines for DMA1 register (DMA1 Configuration register) 00106 **********************************************************************/ 00107 /** I2S control DMA1 for I2S receive */ 00108 #define I2S_DMA1_RX_ENABLE ((uint32_t)(1)) 00109 /** I2S control DMA1 for I2S transmit */ 00110 #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1)) 00111 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ 00112 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) 00113 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ 00114 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) 00115 00116 /*********************************************************************//** 00117 * Macro defines for DMA2 register (DMA2 Configuration register) 00118 **********************************************************************/ 00119 /** I2S control DMA2 for I2S receive */ 00120 #define I2S_DMA2_RX_ENABLE ((uint32_t)(1)) 00121 /** I2S control DMA1 for I2S transmit */ 00122 #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1)) 00123 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ 00124 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) 00125 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ 00126 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) 00127 00128 /*********************************************************************//** 00129 * Macro defines for IRQ register (Interrupt Request Control register) 00130 **********************************************************************/ 00131 /** I2S control I2S receive interrupt */ 00132 #define I2S_IRQ_RX_ENABLE ((uint32_t)(1)) 00133 /** I2S control I2S transmit interrupt */ 00134 #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1)) 00135 /** I2S set the FIFO level on which to create an irq request */ 00136 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) 00137 /** I2S set the FIFO level on which to create an irq request */ 00138 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) 00139 00140 /********************************************************************************//** 00141 * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register) 00142 *********************************************************************************/ 00143 /** I2S Transmit MCLK rate denominator */ 00144 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) 00145 /** I2S Transmit MCLK rate denominator */ 00146 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) 00147 /** I2S Receive MCLK rate denominator */ 00148 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) 00149 /** I2S Receive MCLK rate denominator */ 00150 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) 00151 00152 /*************************************************************************************//** 00153 * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register) 00154 **************************************************************************************/ 00155 #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F)) 00156 #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F)) 00157 00158 /**********************************************************************************//** 00159 * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register) 00160 ************************************************************************************/ 00161 /** I2S Transmit select clock source (2 bits)*/ 00162 #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) 00163 /** I2S Transmit control 4-pin mode */ 00164 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) 00165 /** I2S Transmit control the TX_MCLK output */ 00166 #define I2S_TXMODE_MCENA ((uint32_t)(1<<3)) 00167 /** I2S Receive select clock source */ 00168 #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) 00169 /** I2S Receive control 4-pin mode */ 00170 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) 00171 /** I2S Receive control the TX_MCLK output */ 00172 #define I2S_RXMODE_MCENA ((uint32_t)(1<<3)) 00173 00174 /** 00175 * @} 00176 */ 00177 00178 /** 00179 * @} 00180 */ 00181 00182 00183 /* Public Types --------------------------------------------------------------- */ 00184 /** @defgroup I2S_Public_Types 00185 * @{ 00186 */ 00187 00188 00189 /** 00190 * @brief I2S configuration structure 00191 */ 00192 typedef struct { 00193 uint8_t CLK_Pin; /**< Clock Pin, should be: 00194 - I2S_SRX_CLK_P0_4: RX_CLK pin is on P0.4 00195 - I2S_SRX_CLK_P0_23: RX_CLK pin is on P0.23 00196 - I2S_STX_CLK_P0_7: TX_CLK pin is on P0.7 00197 - I2S_STX_CLK_P2_11: TX_CLK pin is on P2.11 */ 00198 uint8_t WS_Pin; /**< Word Select, should be: 00199 - I2S_SRX_WS_P0_5: RX_WS pin is on P0.5 00200 - I2S_SRX_WS_P0_24: RX_WS pin is on P0.24 00201 - I2S_STX_WS_P0_8: TX_WS pin is on P0.8 00202 - I2S_STX_WS_P2_12: TX_WS pin is on P2.12 */ 00203 uint8_t SDA_Pin; /**< Data, should be: 00204 - I2S_SRX_SDA_P0_6: RX_SDA pin is on P0.6 00205 - I2S_SRX_SDA_P0_25: RX_SDA pin is on P0.25 00206 - I2S_STX_SDA_P0_9: TX_SDA pin is on P0.8 00207 - I2S_STX_SDA_P2_13: TX_SDA pin is on P2.13 */ 00208 uint8_t MCLK_Pin; /**< Master Clock output, should be: 00209 - I2S_RX_MCLK_P4_28: RX_MCLK pin is on P4.28 00210 - I2S_TX_MCLK_P4_29: TX_MCLK pin is on P4.29*/ 00211 }I2S_PinCFG_Type; 00212 00213 /** 00214 * @brief I2S configuration structure definition 00215 */ 00216 typedef struct { 00217 uint8_t wordwidth; /** the number of bytes in data as follow: 00218 -I2S_WORDWIDTH_8: 8 bit data 00219 -I2S_WORDWIDTH_16: 16 bit data 00220 -I2S_WORDWIDTH_32: 32 bit data */ 00221 uint8_t mono; /** Set mono/stereo mode, should be: 00222 - I2S_STEREO: stereo mode 00223 - I2S_MONO: mono mode */ 00224 uint8_t stop; /** Disables accesses on FIFOs, should be: 00225 - I2S_STOP_ENABLE: enable stop mode 00226 - I2S_STOP_DISABLE: disable stop mode */ 00227 uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be: 00228 - I2S_RESET_ENABLE: enable reset mode 00229 - I2S_RESET_DISABLE: disable reset mode */ 00230 uint8_t ws_sel; /** Set Master/Slave mode, should be: 00231 - I2S_MASTER_MODE: I2S master mode 00232 - I2S_SLAVE_MODE: I2S slave mode */ 00233 uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be: 00234 - I2S_MUTE_ENABLE: enable mute mode 00235 - I2S_MUTE_DISABLE: disable mute mode */ 00236 uint8_t Reserved0[2]; 00237 } I2S_CFG_Type; 00238 00239 /** 00240 * @brief I2S DMA configuration structure definition 00241 */ 00242 typedef struct { 00243 uint8_t DMAIndex; /** Select DMA1 or DMA2, should be: 00244 - I2S_DMA_1: DMA1 00245 - I2S_DMA_2: DMA2 */ 00246 uint8_t depth; /** FIFO level that triggers a DMA request */ 00247 uint8_t Reserved0[2]; 00248 }I2S_DMAConf_Type; 00249 00250 /** 00251 * @brief I2S mode configuration structure definition 00252 */ 00253 typedef struct{ 00254 uint8_t clksel; /** Clock source selection, should be: 00255 - I2S_CLKSEL_0: Select the fractional rate divider clock output 00256 - I2S_CLKSEL_2: Select the MCLK signal as the clock source */ 00257 uint8_t fpin; /** Select four pin mode, should be: 00258 - I2S_4PIN_ENABLE: 4-pin enable 00259 - I2S_4PIN_DISABLE: 4-pin disable */ 00260 uint8_t mcena; /** Select MCLK mode, should be: 00261 - I2S_MCLK_ENABLE: MCLK enable for output 00262 - I2S_MCLK_DISABLE: MCLK disable for output */ 00263 uint8_t Reserved; 00264 }I2S_MODEConf_Type; 00265 00266 /** I2S call-back function type definitions */ 00267 typedef void (fnI2SCbs_Type)(); 00268 00269 /** 00270 * @} 00271 */ 00272 00273 00274 /* Public Macros -------------------------------------------------------------- */ 00275 /** @defgroup I2S_Public_Macros 00276 * @{ 00277 */ 00278 00279 /** Macro to determine if it is valid I2S peripheral */ 00280 #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S)) 00281 00282 /** Macro to check Data to send valid */ 00283 #define PARAM_I2S_DATA(data) ((data <= 0xFFFFFFFF)) 00284 #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000)) 00285 00286 /** SSP0 function pin selection defines */ 00287 #define I2S_SRX_CLK_P0_4 ((uint8_t)(0)) 00288 #define I2S_SRX_WS_P0_5 ((uint8_t)(0)) 00289 #define I2S_SRX_SDA_P0_6 ((uint8_t)(0)) 00290 #define I2S_STX_CLK_P0_7 ((uint8_t)(0)) 00291 #define I2S_STX_WS_P0_8 ((uint8_t)(0)) 00292 #define I2S_STX_SDA_P0_9 ((uint8_t)(0)) 00293 00294 00295 #define I2S_SRX_CLK_P0_23 ((uint8_t)(0)) 00296 #define I2S_SRX_WS_P0_24 ((uint8_t)(0)) 00297 #define I2S_SRX_SDA_P0_25 ((uint8_t)(0)) 00298 00299 #define I2S_STX_CLK_P2_11 ((uint8_t)(2)) 00300 #define I2S_STX_WS_P2_12 ((uint8_t)(2)) 00301 #define I2S_STX_SDA_P2_13 ((uint8_t)(2)) 00302 00303 #define I2S_TX_MCLK_P4_29 ((uint8_t)(4)) 00304 #define I2S_RX_MCLK_P4_28 ((uint8_t)(4)) 00305 00306 /** Macro to check PIN parameter */ 00307 #define PARAM_RX_CLK_PIN(n) ((n==I2S_SRX_CLK_P0_4)||(n==I2S_SRX_CLK_P0_23)) 00308 #define PARAM_TX_CLK_PIN(n) ((n==I2S_STX_CLK_P0_7)||(n==I2S_STX_CLK_P2_11)) 00309 00310 #define PARAM_RX_WS_PIN(n) ((n==I2S_SRX_WS_P0_5)||(n==I2S_SRX_WS_P0_24)) 00311 #define PARAM_TX_WS_PIN(n) ((n==I2S_STX_WS_P0_8)||(n==I2S_STX_WS_P2_12)) 00312 00313 #define PARAM_RX_SDA_PIN(n) ((n==I2S_SRX_SDA_P0_6)||(n==I2S_SRX_SDA_P0_25)) 00314 #define PARAM_TX_SDA_PIN(n) ((n==I2S_STX_SDA_P0_9)||(n==I2S_STX_SDA_P2_13)) 00315 00316 #define PARAM_RX_MCLK_PIN(n) (n==I2S_RX_MCLK_P4_28) 00317 #define PARAM_TX_MCLK_PIN(n) (n==I2S_TX_MCLK_P4_29) 00318 00319 /*********************************************************************//** 00320 * I2S configuration parameter defines 00321 **********************************************************************/ 00322 /** I2S Wordwidth bit */ 00323 #define I2S_WORDWIDTH_8 I2S_DAO_WORDWIDTH_8 00324 #define I2S_WORDWIDTH_16 I2S_DAO_WORDWIDTH_16 00325 #define I2S_WORDWIDTH_32 I2S_DAO_WORDWIDTH_32 00326 #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\ 00327 ||(n==I2S_WORDWIDTH_32)) 00328 00329 /** I2S Channel bit */ 00330 #define I2S_STEREO ((uint32_t)(0)) 00331 #define I2S_MONO ((uint32_t)(1)) 00332 #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO)) 00333 00334 /** I2S Master/Slave mode bit */ 00335 #define I2S_MASTER_MODE ((uint8_t)(0)) 00336 #define I2S_SLAVE_MODE ((uint8_t)(1)) 00337 #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE)) 00338 00339 /** I2S Stop bit */ 00340 #define I2S_STOP_ENABLE ((uint8_t)(1)) 00341 #define I2S_STOP_DISABLE ((uint8_t)(0)) 00342 #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE)) 00343 00344 /** I2S Reset bit */ 00345 #define I2S_RESET_ENABLE ((uint8_t)(1)) 00346 #define I2S_RESET_DISABLE ((uint8_t)(0)) 00347 #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE)) 00348 00349 /** I2S Mute bit */ 00350 #define I2S_MUTE_ENABLE ((uint8_t)(1)) 00351 #define I2S_MUTE_DISABLE ((uint8_t)(0)) 00352 #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE)) 00353 00354 /** I2S Transmit/Receive bit */ 00355 #define I2S_TX_MODE ((uint8_t)(0)) 00356 #define I2S_RX_MODE ((uint8_t)(1)) 00357 #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE)) 00358 00359 /** I2S Clock Select bit */ 00360 #define I2S_CLKSEL_0 ((uint8_t)(0)) 00361 #define I2S_CLKSEL_1 ((uint8_t)(2)) 00362 #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_0)||(n==I2S_CLKSEL_1)) 00363 00364 /** I2S 4-pin Mode bit */ 00365 #define I2S_4PIN_ENABLE ((uint8_t)(1)) 00366 #define I2S_4PIN_DISABLE ((uint8_t)(0)) 00367 #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE)) 00368 00369 /** I2S MCLK Enable bit */ 00370 #define I2S_MCLK_ENABLE ((uint8_t)(1)) 00371 #define I2S_MCLK_DISABLE ((uint8_t)(0)) 00372 #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE)) 00373 00374 /** I2S select DMA bit */ 00375 #define I2S_DMA_1 ((uint8_t)(0)) 00376 #define I2S_DMA_2 ((uint8_t)(1)) 00377 #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2)) 00378 00379 #define PARAM_I2S_DMA_DEPTH(n) ((n<=31)) 00380 #define PARAM_I2S_IRQ_LEVEL(n) ((n<=31)) 00381 00382 #define PARAM_I2S_HALFPERIOD(n) ((n<512)) 00383 00384 #define PARAM_I2S_BITRATE(n) ((n>=1)&&(n<=64)) 00385 00386 /** 00387 * @} 00388 */ 00389 00390 00391 /* Public Functions ----------------------------------------------------------- */ 00392 /** @defgroup I2S_Public_Functions 00393 * @{ 00394 */ 00395 00396 void I2S_Init(LPC_I2S_TypeDef *I2Sx); 00397 void I2S_DeInit(LPC_I2S_TypeDef *I2Sx); 00398 00399 void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct); 00400 Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode); 00401 void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode); 00402 void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode); 00403 00404 void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData); 00405 uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx); 00406 void I2S_Start(LPC_I2S_TypeDef *I2Sx); 00407 void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 00408 void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 00409 void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 00410 00411 void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode); 00412 void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState); 00413 void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level, fnI2SCbs_Type *pfnI2SCbs); 00414 void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState); 00415 void I2S_IntHandler(void); 00416 uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 00417 00418 /** 00419 * @} 00420 */ 00421 00422 00423 #ifdef __cplusplus 00424 } 00425 #endif 00426 00427 00428 #endif /* LPC17XX_SSP_H_ */ 00429 00430 /** 00431 * @} 00432 */ 00433 00434 /* --------------------------------- End Of File ------------------------------ */
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