Fawwaz Nadzmy
mbed library sources. Supersedes mbed-src.
Fork of
mbed-dev
by 
mbed official
Revision 153:9398a535854b, committed 2016-12-22
- Comitter:
- fwndz
- Date:
- Thu Dec 22 05:12:40 2016 +0000
- Parent:
- 152:9a67f0b066fc
- Commit message:
- device target maximize
Changed in this revision
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralNames.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// NOTE: TIMER0_BASE=(APBPERIPH_BASE + 0x10000)
-// TIMER1_BASE=(APBPERIPH_BASE + 0x10020)
-#define NU_MODNAME(MODBASE, SUBINDEX) ((MODBASE) | (SUBINDEX))
-#define NU_MODBASE(MODNAME) ((MODNAME) & 0xFFFFFFE0)
-#define NU_MODSUBINDEX(MODNAME) ((MODNAME) & 0x0000001F)
-
-#if 0
-typedef enum {
- GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0),
- GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 0),
- GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 0),
- GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 0),
- GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 0),
- GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 0)
-} GPIOName;
-#endif
-
-typedef enum {
- ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0),
- ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 1),
- ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 2),
- ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 3),
- ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 4),
- ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 5),
- ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 6),
- ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 7),
- ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 8),
- ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 9),
- ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 10),
- ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 11),
- ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 12),
- ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 13),
- ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 14),
- ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 15)
-} ADCName;
-
-typedef enum {
- UART_0 = (int) NU_MODNAME(UART0_BASE, 0),
- UART_1 = (int) NU_MODNAME(UART1_BASE, 0),
- UART_2 = (int) NU_MODNAME(UART2_BASE, 0),
- UART_3 = (int) NU_MODNAME(UART3_BASE, 0),
- // FIXME: board-specific
- STDIO_UART = UART_3
-} UARTName;
-
-typedef enum {
- SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0),
- SPI_1 = (int) NU_MODNAME(SPI1_BASE, 0),
- SPI_2 = (int) NU_MODNAME(SPI2_BASE, 0)
-} SPIName;
-
-typedef enum {
- I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0),
- I2C_1 = (int) NU_MODNAME(I2C1_BASE, 0)
-} I2CName;
-
-typedef enum {
- PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0),
- PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 1),
- PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 2),
- PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 3),
- PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 4),
- PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 5),
-
- PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 0),
- PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1),
- PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 2),
- PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 3),
- PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 4),
- PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 5)
-} PWMName;
-
-typedef enum {
- TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0),
- TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x20, 0),
- TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 0),
- TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x20, 0),
-} TIMERName;
-
-typedef enum {
- RTC_0 = (int) NU_MODNAME(RTC_BASE, 0)
-} RTCName;
-
-typedef enum {
- DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0)
-} DMAName;
-
-typedef enum {
- CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0)
-} CANName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,377 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-// If you change them, you will have also to modify the corresponding xxx_api.c file
-// for pwmout, analogin, analogout, ...
-// =====
-
-#if 0
-//*** GPIO ***
-const PinMap PinMap_GPIO[] = {
- // GPIO A MFPL
- {PA_0, GPIO_A, SYS_GPA_MFPL_PA0MFP_GPIO},
- {PA_1, GPIO_A, SYS_GPA_MFPL_PA1MFP_GPIO},
- {PA_2, GPIO_A, SYS_GPA_MFPL_PA2MFP_GPIO},
- {PA_3, GPIO_A, SYS_GPA_MFPL_PA3MFP_GPIO},
- {PA_4, GPIO_A, SYS_GPA_MFPL_PA4MFP_GPIO},
- {PA_5, GPIO_A, SYS_GPA_MFPL_PA5MFP_GPIO},
- {PA_6, GPIO_A, SYS_GPA_MFPL_PA6MFP_GPIO},
- {PA_7, GPIO_A, SYS_GPA_MFPL_PA7MFP_GPIO},
- // GPIO A MFPH
- {PA_8, GPIO_A, SYS_GPA_MFPH_PA8MFP_GPIO},
- {PA_9, GPIO_A, SYS_GPA_MFPH_PA9MFP_GPIO},
- {PA_10, GPIO_A, SYS_GPA_MFPH_PA10MFP_GPIO},
- {PA_11, GPIO_A, SYS_GPA_MFPH_PA11MFP_GPIO},
- {PA_12, GPIO_A, SYS_GPA_MFPH_PA12MFP_GPIO},
- {PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO},
- {PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO},
- {PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO},
-
- // GPIO B MFPL
- {PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO},
- {PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO},
- {PB_2, GPIO_B, SYS_GPB_MFPL_PB2MFP_GPIO},
- {PB_3, GPIO_B, SYS_GPB_MFPL_PB3MFP_GPIO},
- {PB_4, GPIO_B, SYS_GPB_MFPL_PB4MFP_GPIO},
- {PB_5, GPIO_B, SYS_GPB_MFPL_PB5MFP_GPIO},
- {PB_6, GPIO_B, SYS_GPB_MFPL_PB6MFP_GPIO},
- {PB_7, GPIO_B, SYS_GPB_MFPL_PB7MFP_GPIO},
- // GPIO B MFPH
- {PB_8, GPIO_B, SYS_GPB_MFPH_PB8MFP_GPIO},
- {PB_9, GPIO_B, SYS_GPB_MFPH_PB9MFP_GPIO},
- {PB_10, GPIO_B, SYS_GPB_MFPH_PB10MFP_GPIO},
- {PB_11, GPIO_B, SYS_GPB_MFPH_PB11MFP_GPIO},
- {PB_12, GPIO_B, SYS_GPB_MFPH_PB12MFP_GPIO},
- {PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO},
- {PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO},
- {PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO},
-
- // GPIO C MFPL
- {PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO},
- {PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO},
- {PC_2, GPIO_C, SYS_GPC_MFPL_PC2MFP_GPIO},
- {PC_3, GPIO_C, SYS_GPC_MFPL_PC3MFP_GPIO},
- {PC_4, GPIO_C, SYS_GPC_MFPL_PC4MFP_GPIO},
- {PC_5, GPIO_C, SYS_GPC_MFPL_PC5MFP_GPIO},
- {PC_6, GPIO_C, SYS_GPC_MFPL_PC6MFP_GPIO},
- {PC_7, GPIO_C, SYS_GPC_MFPL_PC7MFP_GPIO},
- // GPIO C MFPH
- {PC_8, GPIO_C, SYS_GPC_MFPH_PC8MFP_GPIO},
- {PC_9, GPIO_C, SYS_GPC_MFPH_PC9MFP_GPIO},
- {PC_10, GPIO_C, SYS_GPC_MFPH_PC10MFP_GPIO},
- {PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO},
- {PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO},
- {PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO},
- {PC_14, GPIO_C, SYS_GPC_MFPH_PC14MFP_GPIO},
- {PC_15, GPIO_C, SYS_GPC_MFPH_PC15MFP_GPIO},
-
- // GPIO D MFPL
- {PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO},
- {PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO},
- {PD_2, GPIO_D, SYS_GPD_MFPL_PD2MFP_GPIO},
- {PD_3, GPIO_D, SYS_GPD_MFPL_PD3MFP_GPIO},
- {PD_4, GPIO_D, SYS_GPD_MFPL_PD4MFP_GPIO},
- {PD_5, GPIO_D, SYS_GPD_MFPL_PD5MFP_GPIO},
- {PD_6, GPIO_D, SYS_GPD_MFPL_PD6MFP_GPIO},
- {PD_7, GPIO_D, SYS_GPD_MFPL_PD7MFP_GPIO},
- // GPIO D MFPH
- {PD_8, GPIO_D, SYS_GPD_MFPH_PD8MFP_GPIO},
- {PD_9, GPIO_D, SYS_GPD_MFPH_PD9MFP_GPIO},
- {PD_10, GPIO_D, SYS_GPD_MFPH_PD10MFP_GPIO},
- {PD_11, GPIO_D, SYS_GPD_MFPH_PD11MFP_GPIO},
- {PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO},
- {PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO},
- {PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO},
- {PD_15, GPIO_D, SYS_GPD_MFPH_PD15MFP_GPIO},
-
- // GPIO E MFPL
- {PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO},
- {PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO},
- {PE_2, GPIO_E, SYS_GPE_MFPL_PE2MFP_GPIO},
- {PE_3, GPIO_E, SYS_GPE_MFPL_PE3MFP_GPIO},
- {PE_4, GPIO_E, SYS_GPE_MFPL_PE4MFP_GPIO},
- {PE_5, GPIO_E, SYS_GPE_MFPL_PE5MFP_GPIO},
- {PE_6, GPIO_E, SYS_GPE_MFPL_PE6MFP_GPIO},
- {PE_7, GPIO_E, SYS_GPE_MFPL_PE7MFP_GPIO},
- // GPIO E MFPH
- {PE_8, GPIO_E, SYS_GPE_MFPH_PE8MFP_GPIO},
- {PE_9, GPIO_E, SYS_GPE_MFPH_PE9MFP_GPIO},
- {PE_10, GPIO_E, SYS_GPE_MFPH_PE10MFP_GPIO},
- {PE_11, GPIO_E, SYS_GPE_MFPH_PE11MFP_GPIO},
- {PE_12, GPIO_E, SYS_GPE_MFPH_PE12MFP_GPIO},
- {PE_13, GPIO_E, SYS_GPE_MFPH_PE13MFP_GPIO},
- {PE_14, GPIO_E, SYS_GPE_MFPH_PE14MFP_GPIO},
-
- // GPIO F MFPL
- {PF_0, GPIO_F, SYS_GPF_MFPL_PF0MFP_GPIO},
- {PF_1, GPIO_F, SYS_GPF_MFPL_PF1MFP_GPIO},
- {PF_2, GPIO_F, SYS_GPF_MFPL_PF2MFP_GPIO},
- {PF_3, GPIO_F, SYS_GPF_MFPL_PF3MFP_GPIO},
- {PF_4, GPIO_F, SYS_GPF_MFPL_PF4MFP_GPIO},
- {PF_5, GPIO_F, SYS_GPF_MFPL_PF5MFP_GPIO},
- {PF_6, GPIO_F, SYS_GPF_MFPL_PF6MFP_GPIO},
- {PF_7, GPIO_F, SYS_GPF_MFPL_PF7MFP_GPIO},
-};
-#endif
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
- {PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC_CH0},
- {PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC_CH1},
- {PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC_CH2},
- {PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC_CH3},
- {PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC_CH4},
- {PB_5, ADC_0_13, SYS_GPB_MFPL_PB5MFP_EADC_CH13},
- {PB_6, ADC_0_14, SYS_GPB_MFPL_PB6MFP_EADC_CH14},
- {PB_7, ADC_0_15, SYS_GPB_MFPL_PB7MFP_EADC_CH15},
- {PB_8, ADC_0_5, SYS_GPB_MFPH_PB8MFP_EADC_CH5},
- {PB_9, ADC_0_6, SYS_GPB_MFPH_PB9MFP_EADC_CH6},
- {PB_10, ADC_0_7, SYS_GPB_MFPH_PB10MFP_EADC_CH7},
- {PB_11, ADC_0_8, SYS_GPB_MFPH_PB11MFP_EADC_CH8},
- {PB_12, ADC_0_9, SYS_GPB_MFPH_PB12MFP_EADC_CH9},
- {PB_13, ADC_0_10, SYS_GPB_MFPH_PB13MFP_EADC_CH10},
- {PB_14, ADC_0_11, SYS_GPB_MFPH_PB14MFP_EADC_CH11},
- {PB_15, ADC_0_12, SYS_GPB_MFPH_PB15MFP_EADC_CH12},
- {PD_0, ADC_0_6, SYS_GPD_MFPL_PD0MFP_EADC_CH6},
- {PD_1, ADC_0_11, SYS_GPD_MFPL_PD1MFP_EADC_CH11},
- {PD_8, ADC_0_7, SYS_GPD_MFPH_PD8MFP_EADC_CH7},
- {PD_9, ADC_0_10, SYS_GPD_MFPH_PD9MFP_EADC_CH10},
-
- {NC, NC, 0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
- {PA_2, I2C_0, SYS_GPA_MFPL_PA2MFP_I2C0_SDA},
- {PD_4, I2C_0, SYS_GPD_MFPL_PD4MFP_I2C0_SDA},
- {PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA},
- {PE_5, I2C_1, SYS_GPE_MFPL_PE5MFP_I2C1_SDA},
- {PE_9, I2C_1, SYS_GPE_MFPH_PE9MFP_I2C1_SDA},
- {PE_11, I2C_1, SYS_GPE_MFPH_PE11MFP_I2C1_SDA},
- {PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SDA},
- {PF_4, I2C_1, SYS_GPF_MFPL_PF4MFP_I2C1_SDA},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
- {PA_3, I2C_0, SYS_GPA_MFPL_PA3MFP_I2C0_SCL},
- {PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SCL},
- {PD_5, I2C_0, SYS_GPD_MFPL_PD5MFP_I2C0_SCL},
- {PE_4, I2C_1, SYS_GPE_MFPL_PE4MFP_I2C1_SCL},
- {PE_8, I2C_1, SYS_GPE_MFPH_PE8MFP_I2C1_SCL},
- {PE_10, I2C_1, SYS_GPE_MFPH_PE10MFP_I2C1_SCL},
- {PE_12, I2C_0, SYS_GPE_MFPH_PE12MFP_I2C0_SCL},
- {PF_3, I2C_1, SYS_GPF_MFPL_PF3MFP_I2C1_SCL},
-
-
- {NC, NC, 0}
-};
-
-//*** PWM ***
-
-const PinMap PinMap_PWM[] = {
- {PA_0, PWM_1_5, SYS_GPA_MFPL_PA0MFP_PWM1_CH5},
- {PA_1, PWM_1_4, SYS_GPA_MFPL_PA1MFP_PWM1_CH4},
- {PA_2, PWM_1_3, SYS_GPA_MFPL_PA2MFP_PWM1_CH3},
- {PA_3, PWM_1_2, SYS_GPA_MFPL_PA3MFP_PWM1_CH2},
- {PB_8, PWM_0_2, SYS_GPB_MFPH_PB8MFP_PWM0_CH2},
- {PC_0, PWM_0_0, SYS_GPC_MFPL_PC0MFP_PWM0_CH0},
- {PC_1, PWM_0_1, SYS_GPC_MFPL_PC1MFP_PWM0_CH1},
- {PC_2, PWM_0_2, SYS_GPC_MFPL_PC2MFP_PWM0_CH2},
- {PC_3, PWM_0_3, SYS_GPC_MFPL_PC3MFP_PWM0_CH3},
- {PC_4, PWM_0_4, SYS_GPC_MFPL_PC4MFP_PWM0_CH4},
- {PC_5, PWM_0_5, SYS_GPC_MFPL_PC5MFP_PWM0_CH5},
- {PC_6, PWM_1_0, SYS_GPC_MFPL_PC6MFP_PWM1_CH0},
- {PC_7, PWM_1_1, SYS_GPC_MFPL_PC7MFP_PWM1_CH1},
- {PC_9, PWM_1_0, SYS_GPC_MFPH_PC9MFP_PWM1_CH0},
- {PC_10, PWM_1_1, SYS_GPC_MFPH_PC10MFP_PWM1_CH1},
- {PC_11, PWM_1_2, SYS_GPC_MFPH_PC11MFP_PWM1_CH2},
- {PC_12, PWM_1_3, SYS_GPC_MFPH_PC12MFP_PWM1_CH3},
- {PC_13, PWM_1_4, SYS_GPC_MFPH_PC13MFP_PWM1_CH4},
- {PC_14, PWM_1_5, SYS_GPC_MFPH_PC14MFP_PWM1_CH5},
- {PC_15, PWM_1_0, SYS_GPC_MFPH_PC15MFP_PWM1_CH0},
- {PD_6, PWM_0_5, SYS_GPD_MFPL_PD6MFP_PWM0_CH5},
- {PD_7, PWM_0_5, SYS_GPD_MFPL_PD7MFP_PWM0_CH5},
- {PD_12, PWM_1_0, SYS_GPD_MFPH_PD12MFP_PWM1_CH0},
- {PD_13, PWM_1_1, SYS_GPD_MFPH_PD13MFP_PWM1_CH1},
- {PD_14, PWM_1_2, SYS_GPD_MFPH_PD14MFP_PWM1_CH2},
- {PD_15, PWM_1_3, SYS_GPD_MFPH_PD15MFP_PWM1_CH3},
- {PE_0, PWM_0_0, SYS_GPE_MFPL_PE0MFP_PWM0_CH0},
- {PE_1, PWM_0_1, SYS_GPE_MFPL_PE1MFP_PWM0_CH1},
- {PE_2, PWM_1_1, SYS_GPE_MFPL_PE2MFP_PWM1_CH1},
- {PE_3, PWM_0_3, SYS_GPE_MFPL_PE3MFP_PWM0_CH3},
-
- {NC, NC, 0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
- {PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_TXD},
- {PA_2, UART_0, SYS_GPA_MFPL_PA2MFP_UART0_TXD},
- {PA_8, UART_3, SYS_GPA_MFPH_PA8MFP_UART3_TXD},
- {PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD},
- {PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD},
- {PB_3, UART_3, SYS_GPB_MFPL_PB3MFP_UART3_TXD},
- {PB_4, UART_2, SYS_GPB_MFPL_PB4MFP_UART2_TXD},
- {PC_0, UART_3, SYS_GPC_MFPL_PC0MFP_UART3_TXD},
- {PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_TXD},
- {PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_TXD},
- {PD_1, UART_0, SYS_GPD_MFPL_PD1MFP_UART0_TXD},
- {PD_12, UART_3, SYS_GPD_MFPH_PD12MFP_UART3_TXD},
- {PE_8, UART_1, SYS_GPE_MFPH_PE8MFP_UART1_TXD},
- {PE_10, UART_3, SYS_GPE_MFPH_PE10MFP_UART3_TXD},
- {PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_TXD},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_UART_RX[] = {
- {PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_RXD},
- {PA_3, UART_0, SYS_GPA_MFPL_PA3MFP_UART0_RXD},
- {PA_9, UART_3, SYS_GPA_MFPH_PA9MFP_UART3_RXD},
- {PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD},
- {PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD},
- {PB_2, UART_3, SYS_GPB_MFPL_PB2MFP_UART3_RXD},
- {PB_5, UART_2, SYS_GPB_MFPL_PB5MFP_UART2_RXD},
- {PC_1, UART_3, SYS_GPC_MFPL_PC1MFP_UART3_RXD},
- {PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_RXD},
- {PC_7, UART_0, (int) SYS_GPC_MFPL_PC7MFP_UART0_RXD},
- {PD_0, UART_0, SYS_GPD_MFPL_PD0MFP_UART0_RXD},
- {PD_6, UART_0, SYS_GPD_MFPL_PD6MFP_UART0_RXD},
- {PD_13, UART_3, SYS_GPD_MFPH_PD13MFP_UART3_RXD},
- {PE_9, UART_1, SYS_GPE_MFPH_PE9MFP_UART1_RXD},
- {PE_11, UART_3, SYS_GPE_MFPH_PE11MFP_UART3_RXD},
- {PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_RXD},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_UART_RTS[] = {
- {PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nRTS},
- {PA_3, UART_0, SYS_GPA_MFPL_PA3MFP_UART0_nRTS},
- {PA_11, UART_3, SYS_GPA_MFPH_PA11MFP_UART3_nRTS},
- {PA_15, UART_2, SYS_GPA_MFPH_PA15MFP_UART2_nRTS},
- {PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS},
- {PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_nRTS},
- {PD_15, UART_3, SYS_GPD_MFPH_PD15MFP_UART3_nRTS},
- {PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nRTS},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_UART_CTS[] = {
- {PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nCTS},
- {PA_2, UART_0, SYS_GPA_MFPL_PA2MFP_UART0_nCTS},
- {PA_10, UART_3, SYS_GPA_MFPH_PA10MFP_UART3_nCTS},
- {PA_14, UART_2, SYS_GPA_MFPH_PA14MFP_UART2_nCTS},
- {PB_4, UART_1, SYS_GPB_MFPL_PB4MFP_UART1_nCTS},
- {PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_nCTS},
- {PD_14, UART_3, SYS_GPD_MFPH_PD14MFP_UART3_nCTS},
- {PE_10, UART_1, SYS_GPE_MFPH_PE10MFP_UART1_nCTS},
-
- {NC, NC, 0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
- {PA_5, SPI_1, SYS_GPA_MFPL_PA5MFP_SPI1_MOSI},
- {PB_0, SPI_0, SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1},
- {PB_5, SPI_0, SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0},
- {PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MOSI},
- {PC_3, SPI_2, SYS_GPC_MFPL_PC3MFP_SPI2_MOSI},
- {PC_10, SPI_2, SYS_GPC_MFPH_PC10MFP_SPI2_MOSI},
- {PD_13, SPI_2, SYS_GPD_MFPH_PD13MFP_SPI2_MOSI},
- {PE_3, SPI_1, SYS_GPE_MFPL_PE3MFP_SPI1_MOSI},
- {PE_9, SPI_0, SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1},
- {PE_11, SPI_1, SYS_GPE_MFPH_PE11MFP_SPI1_MOSI},
- {PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
- {PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_MISO},
- {PB_1, SPI_0, SYS_GPB_MFPL_PB1MFP_SPI0_MISO1},
- {PB_3, SPI_0, SYS_GPB_MFPL_PB3MFP_SPI0_MISO0},
- {PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_MISO},
- {PB_6, SPI_0, SYS_GPB_MFPL_PB6MFP_SPI0_MISO0},
- {PB_6, SPI_1, SYS_GPB_MFPL_PB6MFP_SPI1_MISO},
- {PC_4, SPI_2, SYS_GPC_MFPL_PC4MFP_SPI2_MISO},
- {PC_11, SPI_2, SYS_GPC_MFPH_PC11MFP_SPI2_MISO},
- {PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_MISO},
- {PD_14, SPI_2, SYS_GPD_MFPH_PD14MFP_SPI2_MISO},
- {PE_8, SPI_0, SYS_GPE_MFPH_PE8MFP_SPI0_MISO1},
- {PE_10, SPI_1, SYS_GPE_MFPH_PE10MFP_SPI1_MISO},
- {PE_10, SPI_0, SYS_GPE_MFPH_PE10MFP_SPI0_MISO0},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
- {PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK},
- {PB_2, SPI_0, SYS_GPB_MFPL_PB2MFP_SPI0_CLK},
- {PB_2, SPI_1, SYS_GPB_MFPL_PB2MFP_SPI1_CLK},
- {PB_7, SPI_0, SYS_GPB_MFPL_PB7MFP_SPI0_CLK},
- {PB_7, SPI_1, SYS_GPB_MFPL_PB7MFP_SPI1_CLK},
- {PC_0, SPI_2, SYS_GPC_MFPL_PC0MFP_SPI2_CLK},
- {PC_12, SPI_2, SYS_GPC_MFPH_PC12MFP_SPI2_CLK},
- {PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_CLK},
- {PD_15, SPI_2, SYS_GPD_MFPH_PD15MFP_SPI2_CLK},
- {PE_0, SPI_2, SYS_GPE_MFPL_PE0MFP_SPI2_CLK},
- {PE_13, SPI_1, SYS_GPE_MFPH_PE13MFP_SPI1_CLK},
- {PE_13, SPI_0, SYS_GPE_MFPH_PE13MFP_SPI0_CLK},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
- {PA_4, SPI_1, SYS_GPA_MFPL_PA4MFP_SPI1_SS},
- {PB_4, SPI_0, SYS_GPB_MFPL_PB4MFP_SPI0_SS},
- {PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_SS},
- {PC_2, SPI_2, SYS_GPC_MFPL_PC2MFP_SPI2_SS},
- {PC_13, SPI_2, SYS_GPC_MFPH_PC13MFP_SPI2_SS},
- {PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_SS},
- {PD_12, SPI_2, SYS_GPD_MFPH_PD12MFP_SPI2_SS},
- {PE_12, SPI_1, SYS_GPE_MFPH_PE12MFP_SPI1_SS},
- {PE_12, SPI_0, SYS_GPE_MFPH_PE12MFP_SPI0_SS},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_CAN_TD[] = {
- {PC_0, CAN_0, SYS_GPC_MFPL_PC0MFP_CAN0_TXD},
- {PA_1, CAN_0, SYS_GPA_MFPL_PA1MFP_CAN0_TXD},
- {PA_12, CAN_0, SYS_GPA_MFPH_PA12MFP_CAN0_TXD},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_CAN_RD[] = {
- {PC_1, CAN_0, SYS_GPC_MFPL_PC1MFP_CAN0_RXD},
- {PA_0, CAN_0, SYS_GPA_MFPL_PA0MFP_CAN0_RXD},
- {PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD},
-
- {NC, NC, 0}
-};
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PeripheralPins.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PERIPHERALPINS_H
-#define MBED_PERIPHERALPINS_H
-
-#include "pinmap.h"
-#include "PeripheralNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//*** GPIO ***
-
-extern const PinMap PinMap_GPIO[];
-
-//*** ADC ***
-
-extern const PinMap PinMap_ADC[];
-
-//*** I2C ***
-
-extern const PinMap PinMap_I2C_SDA[];
-extern const PinMap PinMap_I2C_SCL[];
-
-//*** PWM ***
-
-extern const PinMap PinMap_PWM[];
-
-//*** SERIAL ***
-
-extern const PinMap PinMap_UART_TX[];
-extern const PinMap PinMap_UART_RX[];
-extern const PinMap PinMap_UART_RTS[];
-extern const PinMap PinMap_UART_CTS[];
-
-//*** SPI ***
-
-extern const PinMap PinMap_SPI_MOSI[];
-extern const PinMap PinMap_SPI_MISO[];
-extern const PinMap PinMap_SPI_SCLK[];
-extern const PinMap PinMap_SPI_SSEL[];
-
-//*** SD ***
-
-extern const PinMap PinMap_SD_CD[];
-extern const PinMap PinMap_SD_CMD[];
-extern const PinMap PinMap_SD_CLK[];
-extern const PinMap PinMap_SD_DAT0[];
-extern const PinMap PinMap_SD_DAT1[];
-extern const PinMap PinMap_SD_DAT2[];
-extern const PinMap PinMap_SD_DAT3[];
-
-//*** CAN ***
-
-extern PinMap const PinMap_CAN_TD[];
-extern PinMap const PinMap_CAN_RD[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NU_PORT_SHIFT 12
-#define NU_PINNAME_TO_PORT(name) ((unsigned int)(name) >> NU_PORT_SHIFT)
-#define NU_PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << NU_PORT_SHIFT))
-#define NU_PORT_N_PIN_TO_PINNAME(port, pin) ((((unsigned int) (port)) << (NU_PORT_SHIFT)) | ((unsigned int) (pin)))
-#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
-#define NU_MFP_POS(pin) ((pin % 8) * 4)
-#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
- PullNone = 0,
- PullDown,
- PullUp,
-
- PushPull,
- OpenDrain,
- Quasi,
-
- PullDefault = PullUp,
-} PinMode;
-
-typedef enum {
- // Not connected
- NC = (int)0xFFFFFFFF,
-
- // Generic naming
- PA_0 = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
- PB_0 = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
- PC_0 = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14, PC_15,
- PD_0 = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14, PD_15,
- PE_0 = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14,
- PF_0 = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7,
-
- // Arduino UNO naming
- A0 = PB_0,
- A1 = PB_1,
- A2 = PB_2,
- A3 = PB_3,
- A4 = PB_4,
- A5 = PB_8,
- A6 = PB_9,
- A7 = PB_10,
-
- D0 = PD_6,
- D1 = PD_1,
- D2 = PC_6,
- D3 = PC_7,
- D4 = PC_11,
- D5 = PC_12,
- D6 = PC_13,
- D7 = PC_14,
- D8 = PC_0,
- D9 = PC_1,
- D10 = PC_2,
- D11 = PC_3,
- D12 = PC_4,
- D13 = PC_5,
- D14 = PE_5,
- D15 = PE_4,
-
- // FIXME: other board-specific naming
- // UART naming
- USBTX = PA_8,
- USBRX = PA_9,
- STDIO_UART_TX = USBTX,
- STDIO_UART_RX = USBRX,
- // LED naming
- LED1 = PD_2,
- LED2 = PD_3,
- LED3 = PD_7,
- LED4 = D0, // No real LED. Just for passing ATS.
- LED_RED = LED2,
- LED_GREEN = LED3,
- LED_BLUE = LED1,
- // Button naming
- SW1 = PA_15,
- SW2 = PA_14,
-
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // MBED_PINNAMES_H
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PortNames.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/device.h Thu Dec 15 11:48:27 2016 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 24 - -#include "objects.h" - -#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/mbed_overrides.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,83 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "analogin_api.h"
-
-// NOTE: Ensurce mbed_sdk_init() will get called before C++ global object constructor.
-#if defined(__CC_ARM) || defined(__GNUC__)
-void mbed_sdk_init_forced(void) __attribute__((constructor(101)));
-#elif defined(__ICCARM__)
- // FIXME: How to achieve it in IAR?
-#endif
-
-
-void mbed_sdk_init(void)
-{
- // NOTE: Support singleton semantics to be called from other init functions
- static int inited = 0;
- if (inited) {
- return;
- }
- inited = 1;
-
- /*---------------------------------------------------------------------------------------------------------*/
- /* Init System Clock */
- /*---------------------------------------------------------------------------------------------------------*/
- /* Unlock protected registers */
- SYS_UnlockReg();
-
- /* Enable HIRC clock (Internal RC 22.1184MHz) */
- CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
- /* Enable HXT clock (external XTAL 12MHz) */
- CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
- /* Enable LIRC for lp_ticker */
- CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
- /* Enable LXT for RTC */
- CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
-
- /* Wait for HIRC clock ready */
- CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
- /* Wait for HXT clock ready */
- CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
- /* Wait for LIRC clock ready */
- CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
- /* Wait for LXT clock ready */
- CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
-
- /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
- CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
-
- /* Set core clock as 72000000 from PLL */
- CLK_SetCoreClock(72000000);
-
-#if DEVICE_ANALOGIN
- // FIXME: Check voltage reference for EADC
- /* Vref connect to AVDD */
- //SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
-#endif
-
- /* Update System Core Clock */
- /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
- SystemCoreClockUpdate();
-
- /* Lock protected registers */
- SYS_LockReg();
-}
-
-void mbed_sdk_init_forced(void)
-{
- mbed_sdk_init();
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,136 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-#include "dma_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- //IRQn_Type irq_n;
- //uint32_t irq_index;
- //uint32_t event;
-
- PinName pin;
- uint32_t irq_handler;
- uint32_t irq_id;
-};
-
-struct port_s {
- PortName port;
- uint32_t mask;
- PinDirection direction;
-};
-
-struct analogin_s {
- ADCName adc;
- //PinName pin;
-};
-
-struct serial_s {
- UARTName uart;
- PinName pin_tx;
- PinName pin_rx;
-
- uint32_t baudrate;
- uint32_t databits;
- uint32_t parity;
- uint32_t stopbits;
-
- void (*vec)(void);
- uint32_t irq_handler;
- uint32_t irq_id;
- uint32_t inten_msk;
-
- // Async transfer related fields
- DMAUsage dma_usage_tx;
- DMAUsage dma_usage_rx;
- int dma_chn_id_tx;
- int dma_chn_id_rx;
- uint32_t event;
- void (*irq_handler_tx_async)(void);
- void (*irq_handler_rx_async)(void);
-};
-
-struct spi_s {
- SPIName spi;
- PinName pin_miso;
- PinName pin_mosi;
- PinName pin_sclk;
- PinName pin_ssel;
-
- //void (*vec)(void);
-
- // Async transfer related fields
- DMAUsage dma_usage;
- int dma_chn_id_tx;
- int dma_chn_id_rx;
- uint32_t event;
- //void (*irq_handler_tx_async)(void);
- //void (*irq_handler_rx_async)(void);
-};
-
-struct i2c_s {
- I2CName i2c;
- //void (*vec)(void);
- int slaveaddr_state;
-
- uint32_t tran_ctrl;
- char * tran_beg;
- char * tran_pos;
- char * tran_end;
- int inten;
-
- // Async transfer related fields
- DMAUsage dma_usage;
- uint32_t event;
- int stop;
- uint32_t address;
-};
-
-struct pwmout_s {
- PWMName pwm;
- //PinName pin;
- uint32_t period_us;
- uint32_t pulsewidth_us;
-};
-
-struct sleep_s {
- uint32_t start_us;
- uint32_t end_us;
- uint32_t period_us;
- int powerdown;
-};
-
-struct can_s {
- CANName can;
- char index;
-};
-#ifdef __cplusplus
-}
-#endif
-
-#include "gpio_object.h"
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/analogin_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,160 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-
-struct nu_adc_var {
- uint32_t en_msk;
-};
-
-static struct nu_adc_var adc0_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc1_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc2_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc3_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc4_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc5_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc6_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc7_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc8_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc9_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc10_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc11_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc12_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc13_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc14_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc15_var = {
- .en_msk = 0
-};
-
-static const struct nu_modinit_s adc_modinit_tab[] = {
- {ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc0_var},
- {ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc1_var},
- {ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc2_var},
- {ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc3_var},
- {ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc4_var},
- {ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc5_var},
- {ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc6_var},
- {ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc7_var},
- {ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc8_var},
- {ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc9_var},
- {ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc10_var},
- {ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc11_var},
- {ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc12_var},
- {ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc13_var},
- {ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc14_var},
- {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, ADC00_IRQn, &adc15_var},
-};
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
- obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName) NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->adc);
-
- EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
-
- // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
- if (! ((struct nu_adc_var *) modinit->var)->en_msk) {
- // Reset this module if no channel enabled
- SYS_ResetModule(modinit->rsetidx);
-
- // Select clock source of paired channels
- CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
- // Enable clock of paired channels
- CLK_EnableModuleClock(modinit->clkidx);
-
- // Power on ADC
- //ADC_POWER_ON(ADC);
-
- // Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
- EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
- EADC_SetInternalSampleTime(eadc_base, 6);
- }
-
- uint32_t chn = NU_MODSUBINDEX(obj->adc);
-
- // Wire pinout
- pinmap_pinout(pin, PinMap_ADC);
-
- // Configure the sample module Nmod for analog input channel Nch and software trigger source
- EADC_ConfigSampleModule(EADC, chn, EADC_SOFTWARE_TRIGGER, chn);
-
- ((struct nu_adc_var *) modinit->var)->en_msk |= 1 << chn;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
- EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
- uint32_t chn = NU_MODSUBINDEX(obj->adc);
-
- EADC_START_CONV(eadc_base, 1 << chn);
- while (EADC_GET_PENDING_CONV(eadc_base) & (1 << chn));
- uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
- // Just 12 bits are effective. Convert to 16 bits.
- // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
- // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
- uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8);
-
- return conv_res_16;
-}
-
-float analogin_read(analogin_t *obj)
-{
- uint16_t value = analogin_read_u16(obj);
- return (float) value * (1.0f / (float) 0xFFFF);
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/can_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,303 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- #include "can_api.h"
- #include "m451_gpio.h"
- #include "m451_can.h"
-
- #if DEVICE_CAN
- #include <string.h>
- #include "cmsis.h"
- #include "pinmap.h"
- #include "PeripheralPins.h"
- #include "nu_modutil.h"
- #include "nu_miscutil.h"
- #include "nu_bitutil.h"
- #include "critical.h"
-
- #define NU_CAN_DEBUG 0
- #define CAN_NUM 1
-
- static uint32_t can_irq_ids[CAN_NUM] = {0};
- static can_irq_handler can0_irq_handler;
-
-
- static const struct nu_modinit_s can_modinit_tab[] = {
- {CAN_0, CAN0_MODULE, 0, 0, CAN0_RST, CAN0_IRQn, NULL},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-
- void can_init(can_t *obj, PinName rd, PinName td)
- {
- uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
- uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
- obj->can = (CANName)pinmap_merge(can_td, can_rd);
- MBED_ASSERT((int)obj->can != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->can);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- obj->index = 0;
-
- pinmap_pinout(td, PinMap_CAN_TD);
- pinmap_pinout(rd, PinMap_CAN_RD);
-
- /* For M453 mbed Board Transmitter Setting (RS Pin) */
- GPIO_SetMode(PA, BIT0| BIT1, GPIO_MODE_OUTPUT);
- PA0 = 0x00;
- PA1 = 0x00;
-
- CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE);
-
- can_filter(obj, 0, 0, CANStandard, 0);
- }
-
-
-void can_free(can_t *obj)
-{
-
- const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
-
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->can);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- CLK_DisableModuleClock(modinit->clkidx);
-}
-
-int can_frequency(can_t *obj, int hz)
-{
- CAN_SetBaudRate((CAN_T *)obj->can, hz);
-
- return CAN_GetCANBitRate((CAN_T *)obj->can);
-}
-
-static void can_irq(CANName name, int id)
-{
-
- CAN_T *can = (CAN_T *)NU_MODBASE(name);
- uint32_t u8IIDRstatus;
-
- u8IIDRstatus = can->IIDR;
-
- if(u8IIDRstatus == 0x00008000) { /* Check Status Interrupt Flag (Error status Int and Status change Int) */
- /**************************/
- /* Status Change interrupt*/
- /**************************/
- if(can->STATUS & CAN_STATUS_RXOK_Msk) {
- can->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
- can0_irq_handler(can_irq_ids[id], IRQ_RX);
- }
-
- if(can->STATUS & CAN_STATUS_TXOK_Msk) {
- can->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
- can0_irq_handler(can_irq_ids[id], IRQ_TX);
- }
-
- /**************************/
- /* Error Status interrupt */
- /**************************/
- if(can->STATUS & CAN_STATUS_EWARN_Msk) {
- can0_irq_handler(can_irq_ids[id], IRQ_ERROR);
- }
-
- if(can->STATUS & CAN_STATUS_BOFF_Msk) {
- can0_irq_handler(can_irq_ids[id], IRQ_BUS);
- }
- } else if (u8IIDRstatus!=0) {
-
- can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
-
- CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1)); /* Clear Interrupt Pending */
-
- } else if(can->WU_STATUS == 1) {
-
- can->WU_STATUS = 0; /* Write '0' to clear */
- can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
- }
-}
-
-void CAN0_IRQHandler(void)
-{
- can_irq(CAN_0, 0);
-}
-
-void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
-{
- can0_irq_handler = handler;
- can_irq_ids[obj->index] = id;
-}
-
-void can_irq_free(can_t *obj)
-{
- CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
-
- can_irq_ids[obj->index] = 0;
-
- NVIC_DisableIRQ(CAN0_IRQn);
-}
-
-void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
-{
-
- CAN_EnterInitMode((CAN_T*)obj->can, ((enable != 0 )? CAN_CON_IE_Msk :0) );
-
-
- switch (irq)
- {
- case IRQ_ERROR:
- case IRQ_BUS:
- case IRQ_PASSIVE:
- ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk;
- ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
- break;
-
- case IRQ_RX:
- case IRQ_TX:
- case IRQ_OVERRUN:
- case IRQ_WAKEUP:
- ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
- break;
-
- default:
- break;
-
- }
-
- CAN_LeaveInitMode((CAN_T*)obj->can);
-
- NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
- NVIC_EnableIRQ(CAN0_IRQn);
-
-}
-
-int can_write(can_t *obj, CAN_Message msg, int cc)
-{
- STR_CANMSG_T CMsg;
-
- CMsg.IdType = (uint32_t)msg.format;
- CMsg.FrameType = (uint32_t)!msg.type;
- CMsg.Id = msg.id;
- CMsg.DLC = msg.len;
- memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8);
-
- return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg);
-}
-
-int can_read(can_t *obj, CAN_Message *msg, int handle)
-{
- STR_CANMSG_T CMsg;
-
- if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg))
- return 0;
-
- msg->format = (CANFormat)CMsg.IdType;
- msg->type = (CANType)!CMsg.FrameType;
- msg->id = CMsg.Id;
- msg->len = CMsg.DLC;
- memcpy(&msg->data[0], &CMsg.Data[0], 8);
-
- return 1;
-}
-
-int can_mode(can_t *obj, CanMode mode)
-{
- int success = 0;
- switch (mode)
- {
- case MODE_RESET:
- CAN_LeaveTestMode((CAN_T*)obj->can);
- success = 1;
- break;
-
- case MODE_NORMAL:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk);
- success = 1;
- break;
-
- case MODE_SILENT:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk);
- success = 1;
- break;
-
- case MODE_TEST_LOCAL:
- case MODE_TEST_GLOBAL:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk);
- success = 1;
- break;
-
- case MODE_TEST_SILENT:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
- success = 1;
- break;
-
- default:
- success = 0;
- break;
-
- }
-
-
- return success;
-}
-
-int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
-{
- return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id);
-}
-
-
-void can_reset(can_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
-
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->can);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
-}
-
-unsigned char can_rderror(can_t *obj)
-{
- CAN_T *can = (CAN_T *)(obj->can);
- return ((can->ERR>>8)&0xFF);
-}
-
-unsigned char can_tderror(can_t *obj)
-{
- CAN_T *can = (CAN_T *)(obj->can);
- return ((can->ERR)&0xFF);
-}
-
-void can_monitor(can_t *obj, int silent)
-{
- CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk);
-}
-
-#endif // DEVICE_CAN
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/M451Series.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,17150 +0,0 @@
-/******************************************************************************
- * @file M451Series.h
- * @version V3.10
- * $Revision: 179 $
- * $Date: 15/09/04 3:45p $
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-
-/**
- \mainpage Introduction
- *
- *
- * This user manual describes the usage of M451 Series MCU device driver
- *
- * <b>Disclaimer</b>
- *
- * The Software is furnished "AS IS", without warranty as to performance or results, and
- * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
- * warranties, express, implied or otherwise, with regard to the Software, its use, or
- * operation, including without limitation any and all warranties of merchantability, fitness
- * for a particular purpose, and non-infringement of intellectual property rights.
- *
- * <b>Copyright Notice</b>
- *
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- */
-
-/**
- * \page PG_REV Revision History
- *
- * <b>Revision 3.01.001</b>
- * \li Added Nu-LB-M451, NuEdu and USB device sample code.
- * \li Added a lacking macro SYS_IS_LVR_RST() to SYS driver.
- * \li Added a sample code DAC_PDMA_ScatterGather_PWMTrigger to use PDMA scatter gather mode and trigger DAC by PWM.
- * \li Added counter type constant definitions: PWM_UP_COUNTER, PWM_DOWN_COUNTER, and PWM_UP_DOWN_COUNTER.
- * \li Added DAC_PDMA_PWMTrigger sample code to use PDMA and trigger DAC by PWM.
- * \li Added a sample code EADC_PDMA_PWM_Trigger to trigger EADC with PWM and copy result by PDMA.
- * \li Added a new function to control systick and select systick clock source CLK_EnableSysTick() and CLK_DisableSysTick() in CLK driver.
- * \li Added 'NMIEN' and 'NMISTS' control registers to M451Series.h for NMI control.
- * \li Added PDMA_ScatterGather_PingPongBuffer sample code to create ping-pong buffer with PDMA scatter gather mode.
- * \li Added 'PE_DRVCTL' register of GPIO to M451Series.h for GPIO driving strength control.
- * \li Added a sample code PWM_PDMA_Capture to transfer PWM capture data by PDMA.
- * \li Added SCLIB_ActivateDelay API for initial SC with non-standard H/W design in SC driver
- * \li Fixed the bug of EADC_IS_INT_FLAG_OV() that accesses the incorrect register.
- * \li Fixed the bug of EADC_IS_SAMPLE_MODULE_OV() that accesses the incorrect register.
- * \li Fixed the bug of EADC_SetExtendSampleTime() for position shift error in EADC driver.
- * \li Fixed the bug of EADC_SetTriggerDelayTime() for position shift error in EADC driver.
- * \li Fixed the bug of PWM_ENABLE_OUTPUT_INVERTER () that output inverter function cannot be disabled.
- * \li Fixed the bug of PWM_MASK_OUTPUT() in PWM driver that mask function cannot be disabled.
- * \li Fixed CAN_STATUS_LEC_Msk from 0x03 to 0x07.
- * \li Fixed the bug of CLK_SysTickDelay() that COUNTFLAG may not be cleared in CLK driver.
- * \li Fixed CTL and PINCTL regsiter synchronize issue by waiting synchronized ready flag in SC driver.
- * \li Fixed DAC_SetDelayTime() calculation error in DAC driver because the dac->TCTL only used 10 bits, not 14 bits.
- * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
- * \li Fixed EADC_CMP_ADCMPIE_DISABLE definition error.
- * \li Fixed IAR entry point from __iar_program_start to Reset_Handler
- * \li Fixed PWM_ConfigOutputChannel() return value bug in PWM driver.
- * \li Fixed the bug of PWM_ConfigSyncPhase() that cannot configure synchronized source for channel2~5.
- * \li Fixed SC_SET_STOP_BIT_LEN definition error.
- * \li Fixed SCUART baudrate return error in SCUART_Open and SCUART_SetLineConfig API of SCUART driver.
- * \li Fixed SCUART_PARITY_NONE/SCUART_PARITY_EVEN/SCUART_PARITY_ODD definition bug in SCUART driver.
- * \li Fixed u32DataWidth setting error by sc->UARTCTL in SCUART_SetLineConfig API of SCUART driver.
- * \li Fixed SMBD_Enable constant value definition error in I2C driver.
- * \li Fixed the problem that MSC device detection is aborted due to REQUEST_SENSE command not ready.
- * \li Fixed UART clock setting bug in UART_Open(), UART_SetLine_Config() and UART_SelectIrDAMode() of UART driver.
- * \li Improved compatibility of USBH driver for pen driver.
- * \li Improved EADC_ConfigSampleModule() to support rising and falling trigger at the same time.
- * \li Improved EBI_SRAM sample code to add PDMA data transfer with EBI.
- * \li Improved SC driver to support more than one SC port.
- * \li Improved USBH driver to support composite HID devices
- * \li Improved USBD driver to support more USB device sample code.
- * \li Modified I2C_STOP() from #define to inline and add waiting STO bit clear to 0 . This modified is safe for next START coming soon.
- * \li Removed CRC clock enabled in CRC_Open(). User should enable CRC clock in system initialization before any CRC operation.
- * \li Removed FMC_ReadDID() in FMC driver. This function was no longer supported.
- * \li Removed I2C_CTL_STA_STO_SI and I2C_CTL_STA_STO_SI_AA definitions to avoid STOP and START write to control bit at the same time.
- *
- * <b>Revision 3.00.005</b>
- * \li Fixed EADC_CTL_DMOF_STRAIGHT_BINARY and EADC_CTL_DMOF_TWOS_COMPLEMENT definition error in EADC driver.
- * \li Fixed EADC_FALLING_EDGE_TRIGGER definition error in EADC driver.
- * \li Fixed EADC_RISING_EDGE_TRIGGER definition error in EADC driver.
- * \li Fixed UART transmit data bug in UART_TEST_HANDLE() of UART_TxRxFunction sample code.
- * \li Fixed the data missing bug when BULK IN transfer is end by max packet size packet at last packet in USBD_VCOM sample code.
- * \li Fixed program user configuration area without erase in USBD_MassStorage_DataFlash sample code.
- * \li Fixed the bug of switching HCLK to HIRC before enabling PLL in CLK_SetCoreClock() of CLK driver.
- * \li Fixed isochronous transfer bugs of USB Host library.
- * \li Fixed Clear Modem Status Interrupt flag bug in UART_ClearIntFlag() of UART driver.
- * \li Fixed the time-out flag clear bug in I2C_ClearTimeoutFlag() of I2C driver.
- * \li Replaced PERIOD0~5 with PERIOD[6] in PWM_T, and modified PERIOD bit field constant definition in M451Series.h.
- * \li Replaced CMPDAT0~5 with CMPDAT0[6] in PWM_T, and modified CMPDAT bit field constant definition in M451Series.h.
- * \li Replaced CNT0~5 with CNT[6] in PWM_T, and modified CNT bit field constant definition in M451Series.h.
- * \li Replaced PBUF0~5 with PBUF[6] in PWM_T, and modified PBUF bit field constant definition in M451Series.h.
- * \li Replaced CMPBUF0~5 with CMPBUF[6] in PWM_T, and modified CMPBUF bit field constant definition in M451Series.h.
- * \li Replaced CURSCAT0~CURSCAT11 with CURSCAT[12] in PDMA_T of M451Series.h.
- * \li Modified CLK_WaitClockReady() time-out to about 300 ms in CLK driver.
- * \li Updated USB USBD_MassStorage_DataFlash sample code and USB Driver to pass USB-IF MSC test. (The MassStorage size must be greater than 64 KB; otherwise, Command Set test will fail in MSC test).
- * \li Replaced old HID library file (open source) with Nuvoton HID library in USB Host library.
- * \li Added USBH_Audio_Class and USBH_UAC_HID sample code for USB Host to support UAC + HID device.
- *
- * <b>Revision 3.00.004</b>
- * \li Fixed the time-out from 5 ms to 300 ms in CLK_WaitClockReady() of CLK driver.
- * \li Fixed the bug of UART_ClearIntFlag() in UART driver to only clear one flag at one time.
- * \li Fixed the missing parameter, UART clock source LXT, for CLK_SetModuleClock() in UART driver.
- * \li Fixed the bug of clearing data and CTS wake-up flag to clear one flag at one time in UART1_IRQHandler() of UART_Wakeup sample code.
- * \li Fixed the bug of RS485_HANDLE() in the UART_RS485_Slave sample code to only clear one flag at one time.
- * \li Fixed the bug of clearing auto baud rate detect finished and time-out flag to clear one flag at one time in AutoBaudRate_RxTest() of UART_AutoBaudRate_Slave sample code.
- * \li Fixed NVIC_EnableIRQ() to NVIC_DisableIRQ() after chip wake-up in I2C_Wakeup_Slave sample code.
- * \li Fixed multi-function setting error of SC CD pin in USBD_CCID sample code.
- * \li Fixed PD.7 (Headphone output control pin) output mode configuration in WAU8822_Setup() of USBD_Audio_NAU8822 sample code.
- * \li Fixed wrong CLK_WaitClockReady parameter in I2C_GCMode_Slave sample code.
- * \li Fixed UART data transfer bug of USBD_VCOM sample code.
- * \li Updated CLK driver to avoid HIRC force enabled in CLK_SetHCLK() and CLK_SetCoreClock().
- * \li Updated USBD driver to pass USB-IF MSC test.
- * \li Updated USBD_MassStorage_DataFlash sample code to pass USB-IF MSC test.
- * \li Updated driver of VCOM for win8 certification in USBD_VCOM sample code.
- * \li Added HID Media key supporting in USBD_Audio_HID_NAU8822 sample code.
- * \li Added new sample code USBH_UAC_HID of USB Host to support UAC + HID device.
- * \li Added new sample code USBH_Audio_Class to support USB audio class device (UAC).
- *
- * <b>Revision 3.00.003</b>
- * \li Added USBD_Audio_HID_NAU8822 sample code.
- *
- * <b>Revision 3.00.002</b>
- * \li Fixed serial number code in device descriptor.
- * \li Fixed EBI_Open API did not perform u32CSActiveLevel parameters to set CS pin polar.
- * \li Fixed SMBus bus time-out and Clock Lo time-out API.
- * \li Fixed I2C0,1 IP reset of SYS_IPRST1.
- * \li Fixed include path of CMSIS.
- * \li Fixed SPI_CLR_UNIT_TRANS_INT_FLAG( ) definition.
- * \li Fixed USBD_INT_WAKEUP definition.
- * \li Modified USBD driver to support USB remote wake-up function.
- *
- * <b>Revision 3.00.001</b>
- * \li Initial Release.
-*/
-
-#ifndef __M451SERIES_H__
-#define __M451SERIES_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/******************************************************************************/
-/* Processor and Core Peripherals */
-/******************************************************************************/
-/** @addtogroup CMSIS Device CMSIS Definitions
- Configuration of the Cortex-M4 Processor and Core Peripherals
- @{
-*/
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
- /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
-
- /****** M451 Specific Interrupt Numbers ********************************************************/
-
- BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
- IRC_IRQn = 1, /*!< Internal RC Interrupt */
- PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
- RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
- CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
- RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
- TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
- WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */
- WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */
- EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
- EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
- EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
- EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
- EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
- EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
- GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
- GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
- GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
- GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
- GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
- GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
- SPI0_IRQn = 22, /*!< SPI0 Interrupt */
- SPI1_IRQn = 23, /*!< SPI1 Interrupt */
- BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
- PWM0P0_IRQn = 25, /*!< PWM0P0 Interrupt */
- PWM0P1_IRQn = 26, /*!< PWM0P1 Interrupt */
- PWM0P2_IRQn = 27, /*!< PWM0P2 Interrupt */
- BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
- PWM1P0_IRQn = 29, /*!< PWM1P0 Interrupt */
- PWM1P1_IRQn = 30, /*!< PWM1P1 Interrupt */
- PWM1P2_IRQn = 31, /*!< PWM1P2 Interrupt */
- TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
- TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
- TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
- TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
- UART0_IRQn = 36, /*!< UART 0 Interrupt */
- UART1_IRQn = 37, /*!< UART 1 Interrupt */
- I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
- I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
- PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
- DAC_IRQn = 41, /*!< DAC Interrupt */
- ADC00_IRQn = 42, /*!< ADC0 Source 0 Interrupt */
- ADC01_IRQn = 43, /*!< ADC0 Source 1 Interrupt */
- ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
- ADC02_IRQn = 46, /*!< ADC0 Source 2 Interrupt */
- ADC03_IRQn = 47, /*!< ADC0 Source 3 Interrupt */
- UART2_IRQn = 48, /*!< UART2 Interrupt */
- UART3_IRQn = 49, /*!< UART3 Interrupt */
- SPI2_IRQn = 51, /*!< SPI2 Interrupt */
- USBD_IRQn = 53, /*!< USB device Interrupt */
- USBH_IRQn = 54, /*!< USB host Interrupt */
- USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
- CAN0_IRQn = 56, /*!< CAN0 Interrupt */
- SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
- TK_IRQn = 63 /*!< Touch Key Interrupt */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M# Processor and Core Peripherals */
-#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
-#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-
-/*@}*/ /* end of group CMSIS */
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_M451Series.h" /* M451 System include file */
-#include <stdint.h>
-
-
-
-/******************************************************************************/
-/* Device Specific Peripheral registers structures */
-/******************************************************************************/
-
-/** @addtogroup REGISTER Control Register
-
- @{
-
-*/
-
-
-/*---------------------- Analog Comparator Controller -------------------------*/
-/**
- @addtogroup ACMP Analog Comparator Controller(ACMP)
- Memory Mapped Structure for ACMP Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var ACMP_T::CTL
- * Offset: 0x00 Analog Comparator 0 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ACMPEN |Comparator Enable Bit
- * | | |0 = Comparator 0 Disabled.
- * | | |1 = Comparator 0 Enabled.
- * |[1] |ACMPIE |Comparator Interrupt Enable Bit
- * | | |0 = Comparator 0 interrupt Disabled.
- * | | |1 = Comparator 0 interrupt Enabled.
- * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
- * |[2] |HYSEN |Comparator Hysteresis Enable Bit
- * | | |0 = Comparator 0 hysteresis Disabled.
- * | | |1 = Comparator 0 hysteresis Enabled.
- * |[3] |ACMPOINV |Comparator Output Inverse
- * | | |0 = Comparator 0 output inverse Disabled.
- * | | |1 = Comparator 0 output inverse Enabled.
- * |[5:4] |NEGSEL |Comparator Negative Input Selection
- * | | |00 = ACMP0_N pin.
- * | | |01 = Internal comparator reference voltage (CRV).
- * | | |10 = Band-gap voltage.
- * | | |11 = DAC output.
- * |[7:6] |POSSEL |Comparator Positive Input Selection
- * | | |00 = Input from ACMP0_P0.
- * | | |01 = Input from ACMP0_P1.
- * | | |10 = Input from ACMP0_P2.
- * | | |11 = Input from ACMP0_P3.
- * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
- * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
- * | | |00 = Rising edge or falling edge.
- * | | |01 = Rising edge.
- * | | |10 = Falling edge.
- * | | |11 = Reserved.
- * |[12] |OUTSEL |Comparator Output Select
- * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
- * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output.
- * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
- * | | |000 = Filter function is Disabled.
- * | | |001 = ACMP0 output is sampled 1 consecutive PCLK.
- * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs.
- * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs.
- * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs.
- * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs.
- * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs.
- * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs.
- * |[16] |WKEN |Power Down Wake-Up Enable Bit
- * | | |0 = Wake-up function Disabled.
- * | | |1 = Wake-up function Enabled.
- * ---------------------------------------------------------------------------------------------------
- * Offset: 0x04 Analog Comparator 1 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ACMPEN |Comparator Enable Bit
- * | | |0 = Comparator 1 Disabled.
- * | | |1 = Comparator 1 Enabled.
- * |[1] |ACMPIE |Comparator Interrupt Enable Bit
- * | | |0 = Comparator 1 interrupt Disabled.
- * | | |1 = Comparator 1 interrupt Enabled.
- * | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well.
- * |[2] |HYSEN |Comparator Hysteresis Enable Bit
- * | | |0 = Comparator 1 hysteresis Disabled.
- * | | |1 = Comparator 1 hysteresis Enabled.
- * |[3] |ACMPOINV |Comparator Output Inverse Control
- * | | |0 = Comparator 1 output inverse Disabled.
- * | | |1 = Comparator 1 output inverse Enabled.
- * |[5:4] |NEGSEL |Comparator Negative Input Selection
- * | | |00 = ACMP1_N pin.
- * | | |01 = Internal comparator reference voltage (CRV).
- * | | |10 = Band-gap voltage.
- * | | |11 = DAC output.
- * |[7:6] |POSSEL |Comparator Positive Input Selection
- * | | |00 = Input from ACMP1_P0.
- * | | |01 = Input from ACMP1_P1.
- * | | |10 = Input from ACMP1_P2.
- * | | |11 = Input from ACMP1_P3.
- * |[9:8] |INTPOL |Interrupt Condition Polarity Selection
- * | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected.
- * | | |00 = Rising edge or falling edge.
- * | | |01 = Rising edge.
- * | | |10 = Falling edge.
- * | | |11 = Reserved.
- * |[12] |OUTSEL |Comparator Output Select
- * | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output.
- * | | |1 = Comparator 1 output to ACMP1_O pin is from filter output.
- * |[15:13] |FILTSEL |Comparator Output Filter Count Selection
- * | | |000 = Filter function is Disabled.
- * | | |001 = ACMP1 output is sampled 1 consecutive PCLK.
- * | | |010 = ACMP1 output is sampled 2 consecutive PCLKs.
- * | | |011 = ACMP1 output is sampled 4 consecutive PCLKs.
- * | | |100 = ACMP1 output is sampled 8 consecutive PCLKs.
- * | | |101 = ACMP1 output is sampled 16 consecutive PCLKs.
- * | | |110 = ACMP1 output is sampled 32 consecutive PCLKs.
- * | | |111 = ACMP1 output is sampled 64 consecutive PCLKs.
- * |[16] |WKEN |Power Down Wakeup Enable Bit
- * | | |0 = Wake-up function Disabled.
- * | | |1 = Wake-up function Enabled.
- * @var ACMP_T::STATUS
- * Offset: 0x08 Analog Comparator Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag
- * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output.
- * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag
- * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output.
- * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |ACMPO0 |Comparator 0 Output
- * | | |Synchronized to the PCLK to allow reading by software.
- * | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0.
- * |[5] |ACMPO1 |Comparator 1 Output
- * | | |Synchronized to the PCLK to allow reading by software.
- * | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0.
- * |[8] |WKIF0 |Comparator 0 Power Down Wake-Up Interrupt Flag
- * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
- * | | |0 = No power down wake-up occurred.
- * | | |1 = Power down wake-up occurred.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |WKIF1 |Comparator 1 Power Down Wake-Up Interrupt Flag
- * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
- * | | |0 = No power down wake-up occurred.
- * | | |1 = Power down wake-up occurred.
- * | | |Note: Write 1 to clear this bit to 0.
- * @var ACMP_T::VREF
- * Offset: 0x0C Analog Comparator Reference Voltage Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |CRVCTL |Comparator Reference Voltage Setting
- * | | |CRV = CRV source voltage * (1/6+CRVCTL/24).
- * |[6] |CRVSSEL |CRV Source Voltage Selection
- * | | |0 = VDDA is selected as CRV source voltage.
- * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
- */
-
- __IO uint32_t CTL[2]; /* Offset: 0x00 Analog Comparator Control Register */
- __IO uint32_t STATUS; /* Offset: 0x08 Analog Comparator Status Register */
- __IO uint32_t VREF; /* Offset: 0x0C Analog Comparator Reference Voltage Control Register */
-
-} ACMP_T;
-
-
-
-/**
- @addtogroup ACMP_CONST ACMP Bit Field Definition
- Constant Definitions for ACMP Controller
-@{ */
-
-#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */
-#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */
-
-#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */
-#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */
-
-#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */
-#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */
-
-#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */
-#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */
-
-#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */
-#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */
-
-#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */
-#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */
-
-#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */
-#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */
-
-#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */
-#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */
-
-#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */
-#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */
-
-#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */
-#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */
-
-#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */
-#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */
-
-#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */
-#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */
-
-#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */
-#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */
-
-#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */
-#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */
-
-#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */
-#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */
-
-#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */
-#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */
-
-#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */
-#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */
-
-#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */
-#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */
-
-/**@}*/ /* ACMP_CONST */
-/**@}*/ /* end of ACMP register group */
-
-
-/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
-/**
- @addtogroup Enhanced Analog to Digital Converter(EADC)
- Memory Mapped Structure for EADC Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var EADC_T::DAT
- * Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
- * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
- * |[16] |OV |Overrun Flag
- * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
- * | | |0 = Data in RESULT[11:0] is recent conversion result.
- * | | |1 = Data in RESULT[11:0] is overwrite.
- * | | |Note: It is cleared by hardware after EADC_DAT register is read.
- * |[17] |VALID |Valid Flag
- * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
- * | | |0 = Data in RESULT[11:0] bits is not valid.
- * | | |1 = Data in RESULT[11:0] bits is valid.
- * @var EADC_T::CURDAT
- * Offset: 0x4C EADC PDMA Current Transfer Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register
- * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
- * | | |This is a read only register.
- * @var EADC_T::CTL
- * Offset: 0x50 A/D Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADCEN |A/D Converter Enable Bit
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |Note: Before starting A/D conversion function, this bit should be set to 1.
- * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
- * |[1] |ADCRST |ADC A/D Converter Control Circuits Reset
- * | | |0 = No effect.
- * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
- * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
- * |[2] |ADCIEN0 |Specific Sample Module A/D ADINT0 Interrupt Enable Bit
- * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion.
- * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
- * | | |0 = Specific sample module A/D ADINT0 interrupt function Disabled.
- * | | |1 = Specific sample module A/D ADINT0 interrupt function Enabled.
- * |[3] |ADCIEN1 |Specific Sample Module A/D ADINT1 Interrupt Enable Bit
- * | | |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion.
- * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
- * | | |0 = Specific sample module A/D ADINT1 interrupt function Disabled.
- * | | |1 = Specific sample module A/D ADINT1 interrupt function Enabled.
- * |[4] |ADCIEN2 |Specific Sample Module A/D ADINT2 Interrupt Enable Bit
- * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion.
- * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
- * | | |0 = Specific sample module A/D ADINT2 interrupt function Disabled.
- * | | |1 = Specific sample module A/D ADINT2 interrupt function Enabled.
- * |[5] |ADCIEN3 |Specific Sample Module A/D ADINT3 Interrupt Enable Bit
- * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
- * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
- * | | |0 = Specific sample module A/D ADINT3 interrupt function Disabled.
- * | | |1 = Specific sample module A/D ADINT3 interrupt function Enabled.
- * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit
- * | | |0 = Single-end analog input mode.
- * | | |1 = Differential analog input mode.
- * |[9] |DMOF |ADC Differential Input Mode Output Format
- * | | |0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
- * | | |1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
- * |[11] |PDMAEN |PDMA Transfer Enable Bit
- * | | |When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
- * | | |0 = PDMA data transfer Disabled.
- * | | |1 = PDMA data transfer Enabled.
- * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
- * |[18:16] |SMPTSEL |ADC Internal Sampling Time Selection
- * | | |ADC internal sampling cycle = SMPTSEL + 1.
- * | | |000 = 1 ADC clock sampling time.
- * | | |001 = 2 ADC clock sampling time.
- * | | |010 = 3 ADC clock sampling time.
- * | | |011 = 4 ADC clock sampling time.
- * | | |100 = 5 ADC clock sampling time.
- * | | |101 = 6 ADC clock sampling time.
- * | | |110 = 7 ADC clock sampling time.
- * | | |111 = 8 ADC clock sampling time.
- * @var EADC_T::SWTRG
- * Offset: 0x54 A/D Sample Module Software Start Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[18:0] |SWTRG |A/D Sample Module
- * | | |0~18 Software Force To Start ADC Conversion
- * | | |0 = No effect.
- * | | |1 = Cause an ADC conversion when the priority is given to sample module.
- * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
- * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
- * @var EADC_T::PENDSTS
- * Offset: 0x58 A/D Start of Conversion Pending Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[18:0] |STPF |A/D Sample Module 0~18 Start Of Conversion Pending Flag
- * | | |Read:
- * | | |0 = There is no pending conversion for sample module.
- * | | |1 = Sample module ADC start of conversion is pending.
- * | | |Write:
- * | | |1 = clear pending flag and cancel the conversion for sample module.
- * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
- * @var EADC_T::OVSTS
- * Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[18:0] |SPOVF |A/D SAMPLE0~18 Overrun Flag
- * | | |0 = No sample module event overrun.
- * | | |1 = Indicates a new sample module event is generated while an old one event is pending.
- * | | |Note: This bit is cleared by writing 1 to it.
- * @var EADC_T::SCTL
- * Offset: 0x80-0x8C A/D Sample Module n Control Register, n=0~3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |CHSEL |A/D Sample Module Channel Selection
- * | | |00H = EADC_CH0.
- * | | |01H = EADC_CH1.
- * | | |02H = EADC_CH2.
- * | | |03H = EADC_CH3.
- * | | |04H = EADC_CH4.
- * | | |05H = EADC_CH5.
- * | | |06H = EADC_CH6.
- * | | |07H = EADC_CH7.
- * | | |08H = EADC_CH8.
- * | | |09H = EADC_CH9.
- * | | |0AH = EADC_CH10.
- * | | |0BH = EADC_CH11.
- * | | |0CH = EADC_CH12.
- * | | |0DH = EADC_CH13.
- * | | |0EH = EADC_CH14.
- * | | |0FH = EADC_CH15.
- * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
- * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
- * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
- * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
- * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
- * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
- * |[7:6] |TRGDLYDIV |A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[15:8] |TRGDLYCNT |A/D Sample Module Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
- * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
- * | | |0H = Disable trigger.
- * | | |1H = External trigger from STADC pin input.
- * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
- * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
- * | | |4H = Timer0 overflow pulse trigger.
- * | | |5H = Timer1 overflow pulse trigger.
- * | | |6H = Timer2 overflow pulse trigger.
- * | | |7H = Timer3 overflow pulse trigger.
- * | | |8H = PWM0TG0.
- * | | |9H = PWM0TG1.
- * | | |AH = PWM0TG2.
- * | | |BH = PWM0TG3.
- * | | |CH = PWM0TG4.
- * | | |DH = PWM0TG5.
- * | | |EH = PWM1TG0.
- * | | |FH = PWM1TG1.
- * | | |10H = PWM1TG2.
- * | | |11H = PWM1TG3.
- * | | |12H = PWM1TG4.
- * | | |13H = PWM1TG5.
- * | | |other = Reserved.
- * |[22] |INTPOS |Interrupt Flag Position Select
- * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
- * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
- * |[23] |DBMEN |Double Buffer Mode Enable Bit
- * | | |0 = Sample has one sample result register. (default).
- * | | |1 = Sample has two sample result registers.
- * |[31:24] |EXTSMPT |ADC Sampling Time Extend
- * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
- * | | |The range of start delay time is from 0~255 ADC clock.
- * @var EADC_T::SCTL
- * Offset: 0x90-0xBC A/D Sample Module n Control Register, n=4~15
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |CHSEL |A/D Sample Module Channel Selection
- * | | |00H = EADC_CH0.
- * | | |01H = EADC_CH1.
- * | | |02H = EADC_CH2.
- * | | |03H = EADC_CH3.
- * | | |04H = EADC_CH4.
- * | | |05H = EADC_CH5.
- * | | |06H = EADC_CH6.
- * | | |07H = EADC_CH7.
- * | | |08H = EADC_CH8.
- * | | |09H = EADC_CH9.
- * | | |0AH = EADC_CH10.
- * | | |0BH = EADC_CH11.
- * | | |0CH = EADC_CH12.
- * | | |0DH = EADC_CH13.
- * | | |0EH = EADC_CH14.
- * | | |0FH = EADC_CH15.
- * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit
- * | | |0 = Rising edge Disabled when A/D selects STADC as trigger source.
- * | | |1 = Rising edge Enabled when A/D selects STADC as trigger source.
- * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit
- * | | |0 = Falling edge Disabled when A/D selects STADC as trigger source.
- * | | |1 = Falling edge Enabled when A/D selects STADC as trigger source.
- * |[7:6] |TRGDLYDIV[1:0]|A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[15:8] |TRGDLYCNT[7:0]|A/D Sample Module Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
- * |[20:16] |TRGSEL |A/D Sample Module Start Of Conversion Trigger Source Selection
- * | | |0H = Disable trigger.
- * | | |1H = External trigger from STADC pin input.
- * | | |2H = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |3H = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |4H = Timer0 overflow pulse trigger.
- * | | |5H = Timer1 overflow pulse trigger.
- * | | |6H = Timer2 overflow pulse trigger.
- * | | |7H = Timer3 overflow pulse trigger.
- * | | |8H = PWM0TG0.
- * | | |9H = PWM0TG1.
- * | | |AH = PWM0TG2.
- * | | |BH = PWM0TG3.
- * | | |CH = PWM0TG4.
- * | | |DH = PWM0TG5.
- * | | |EH = PWM1TG0.
- * | | |FH = PWM1TG1.
- * | | |10H = PWM1TG2.
- * | | |11H = PWM1TG3.
- * | | |12H = PWM1TG4.
- * | | |13H = PWM1TG5.
- * | | |other = Reserved.
- * |[22] |INTPOS |Interrupt Flag Position Select
- * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
- * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
- * |[31:24] |EXTSMPT |ADC Sampling Time Extend
- * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
- * | | |The range of start delay time is from 0~255 ADC clock.
- * @var EADC_T::SCTL
- * Offset: 0xC0~0xC8 A/D Sample Module n Control Register, n=16~18
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:24] |EXTSMPT |ADC Sampling Time Extend
- * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
- * | | |The range of start delay time is from 0~255 ADC clock.
- * @var EADC_T::INTSRC
- * Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit
- * | | |0 = Sample Module 0 interrupt Disabled.
- * | | |1 = Sample Module 0 interrupt Enabled.
- * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit
- * | | |0 = Sample Module 1 interrupt Disabled.
- * | | |1 = Sample Module 1 interrupt Enabled.
- * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit
- * | | |0 = Sample Module 2 interrupt Disabled.
- * | | |1 = Sample Module 2 interrupt Enabled.
- * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit
- * | | |0 = Sample Module 3 interrupt Disabled.
- * | | |1 = Sample Module 3 interrupt Enabled.
- * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit
- * | | |0 = Sample Module 4 interrupt Disabled.
- * | | |1 = Sample Module 4 interrupt Enabled.
- * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit
- * | | |0 = Sample Module 5 interrupt Disabled.
- * | | |1 = Sample Module 5 interrupt Enabled.
- * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit
- * | | |0 = Sample Module 6 interrupt Disabled.
- * | | |1 = Sample Module 6 interrupt Enabled.
- * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit
- * | | |0 = Sample Module 7 interrupt Disabled.
- * | | |1 = Sample Module 7 interrupt Enabled.
- * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit
- * | | |0 = Sample Module 8 interrupt Disabled.
- * | | |1 = Sample Module 8 interrupt Enabled.
- * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit
- * | | |0 = Sample Module 9 interrupt Disabled.
- * | | |1 = Sample Module 9 interrupt Enabled.
- * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit
- * | | |0 = Sample Module 10 interrupt Disabled.
- * | | |1 = Sample Module 10 interrupt Enabled.
- * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit
- * | | |0 = Sample Module 11 interrupt Disabled.
- * | | |1 = Sample Module 11 interrupt Enabled.
- * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit
- * | | |0 = Sample Module 12 interrupt Disabled.
- * | | |1 = Sample Module 12 interrupt Enabled.
- * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit
- * | | |0 = Sample Module 13 interrupt Disabled.
- * | | |1 = Sample Module 13 interrupt Enabled.
- * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit
- * | | |0 = Sample Module 14 interrupt Disabled.
- * | | |1 = Sample Module 14 interrupt Enabled.
- * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit
- * | | |0 = Sample Module 15 interrupt Disabled.
- * | | |1 = Sample Module 15 interrupt Enabled.
- * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit
- * | | |0 = Sample Module 16 interrupt Disabled.
- * | | |1 = Sample Module 16 interrupt Enabled.
- * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit
- * | | |0 = Sample Module 17 interrupt Disabled.
- * | | |1 = Sample Module 17 interrupt Enabled.
- * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit
- * | | |0 = Sample Module 18 interrupt Disabled.
- * | | |1 = Sample Module 18 interrupt Enabled.
- * @var EADC_T::CMP
- * Offset: 0xEC A/D Result Compare Register n, n=0~3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADCMPEN |A/D Result Compare Enable Bit
- * | | |0 = Compare Disabled.
- * | | |1 = Compare Enabled.
- * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
- * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Bit
- * | | |0 = Compare function interrupt Disabled.
- * | | |1 = Compare function interrupt Enabled.
- * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
- * |[2] |CMPCOND |Compare Condition
- * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn
- * | | |[27:16]), the internal match counter will increase one.
- * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
- * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
- * |[7:3] |CMPSPL |Compare Sample Module Selection
- * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
- * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
- * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
- * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
- * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
- * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
- * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
- * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
- * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
- * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
- * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
- * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
- * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
- * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
- * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
- * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
- * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
- * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
- * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
- * |[11:8] |CMPMCNT |Compare Match Count
- * | | |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1.
- * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0.
- * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
- * |[15] |CMPWEN |Compare Window Mode Enable Bit
- * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
- * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
- * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
- * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
- * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
- * |[27:16] |CMPDAT |Comparison Data
- * | | |The 12 bits data is used to compare with conversion result of specified sample module.
- * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
- * @var EADC_T::STATUS0
- * Offset: 0xF0 A/D Status Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag
- * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
- * |[31:16] |OV |EADC_DAT0~15 Overrun Flag
- * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
- * @var EADC_T::STATUS1
- * Offset: 0xF4 A/D Status Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag
- * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
- * |[18:16] |OV |EADC_DAT16~18 Overrun Flag
- * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).
- * @var EADC_T::STATUS2
- * Offset: 0xF8 A/D Status Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
- * | | |0 = No ADINT0 interrupt pulse received.
- * | | |1 = ADINT0 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
- * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
- * | | |0 = No ADINT1 interrupt pulse received.
- * | | |1 = ADINT1 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
- * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
- * | | |0 = No ADINT2 interrupt pulse received.
- * | | |1 = ADINT2 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
- * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
- * | | |0 = No ADINT3 interrupt pulse received.
- * | | |1 = ADINT3 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
- * |[4] |ADCMPF0 |ADC Compare 0 Flag
- * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
- * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
- * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[5] |ADCMPF1 |ADC Compare 1 Flag
- * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
- * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
- * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[6] |ADCMPF2 |ADC Compare 2 Flag
- * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
- * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
- * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[7] |ADCMPF3 |ADC Compare 3 Flag
- * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
- * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
- * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[8] |ADOVIF0 |A/D ADINT0 Interrupt Flag Overrun
- * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT0 interrupt flag is overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[9] |ADOVIF1 |A/D ADINT1 Interrupt Flag Overrun
- * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT1 interrupt flag is overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[10] |ADOVIF2 |A/D ADINT2 Interrupt Flag Overrun
- * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT2 interrupt flag is s overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[11] |ADOVIF3 |A/D ADINT3 Interrupt Flag Overrun
- * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT3 interrupt flag is overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[12] |ADCMPO0 |ADC Compare 0 Output Status
- * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
- * | | |User can use it to monitor the external analog input pin voltage status.
- * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
- * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0
- * | | |setting.
- * |[13] |ADCMPO1 |ADC Compare 1 Output Status
- * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
- * | | |User can use it to monitor the external analog input pin voltage status.
- * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
- * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1
- * | | |setting.
- * |[14] |ADCMPO2 |ADC Compare 2 Output Status
- * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
- * | | |User can use it to monitor the external analog input pin voltage status.
- * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
- * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2
- * | | |setting.
- * |[15] |ADCMPO3 |ADC Compare 3 Output Status
- * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
- * | | |User can use it to monitor the external analog input pin voltage status.
- * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
- * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3
- * | | |setting.
- * |[20:16] |CHANNEL |Current Conversion Channel
- * | | |This filed reflects ADC current conversion channel when BUSY=1.
- * | | |It is read only.
- * | | |00H = EADC_CH0.
- * | | |01H = EADC_CH1.
- * | | |02H = EADC_CH2.
- * | | |03H = EADC_CH3.
- * | | |04H = EADC_CH4.
- * | | |05H = EADC_CH5.
- * | | |06H = EADC_CH6.
- * | | |07H = EADC_CH7.
- * | | |08H = EADC_CH8.
- * | | |09H = EADC_CH9.
- * | | |0AH = EADC_CH10.
- * | | |0BH = EADC_CH11.
- * | | |0CH = EADC_CH12.
- * | | |0DH = EADC_CH13.
- * | | |0EH = EADC_CH14.
- * | | |0FH = EADC_CH15.
- * | | |10H = VBG.
- * | | |11H = VTEMP.
- * | | |12H = VBAT.
- * |[23] |BUSY |Busy/Idle
- * | | |0 = EADC is in idle state.
- * | | |1 = EADC is busy at conversion.
- * | | |Note: This bit is read only.
- * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
- * | | |n=0~3.
- * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
- * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
- * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
- * |[25] |STOVF |For All A/D Sample Module Start Of Conversion Overrun Flags Check
- * | | |n=0~18.
- * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
- * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
- * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
- * |[26] |AVALID |For All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
- * | | |n=0~18.
- * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
- * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
- * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
- * |[27] |AOV |For All Sample Module A/D Result Data Register Overrun Flags Check
- * | | |n=0~18.
- * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
- * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
- * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1.
- * @var EADC_T::STATUS3
- * Offset: 0xFC A/D Status Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:0] |CURSPL |ADC Current Sample Module
- * | | |This register show the current ADC is controlled by which sample module control logic modules.
- * | | |If the ADC is Idle, this bit filed will set to 0x1F.
- * | | |This is a read only register.
- * @var EADC_T::DDAT
- * Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RESULT |A/D Conversion Results
- * | | |This field contains 12 bits conversion results.
- * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
- * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
- * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
- * | | |It is cleared by hardware after EADC_DDAT register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
- * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
- * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
- * | | |(n=0~3).
- */
-
- __I uint32_t DAT[19]; /* Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18 */
- __I uint32_t CURDAT; /* Offset: 0x4C EADC PDMA Current Transfer Data Register */
- __IO uint32_t CTL; /* Offset: 0x50 A/D Control Register */
- __O uint32_t SWTRG; /* Offset: 0x54 A/D Sample Module Software Start Register */
- __IO uint32_t PENDSTS; /* Offset: 0x58 A/D Start of Conversion Pending Flag Register */
- __IO uint32_t OVSTS; /* Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register */
- __I uint32_t RESERVE0[8];
- __IO uint32_t SCTL[19]; /* Offset: 0x80-0xC8 A/D Sample Module n Control Register, n=0~3 */
- __I uint32_t RESERVE1[1];
- __IO uint32_t INTSRC[4]; /* Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3 */
- __IO uint32_t CMP[4]; /* Offset: 0xEC A/D Result Compare Register n, n=0~3 */
- __I uint32_t STATUS0; /* Offset: 0xF0 A/D Status Register 0 */
- __I uint32_t STATUS1; /* Offset: 0xF4 A/D Status Register 1 */
- __IO uint32_t STATUS2; /* Offset: 0xF8 A/D Status Register 2 */
- __I uint32_t STATUS3; /* Offset: 0xFC A/D Status Register 3 */
- __I uint32_t DDAT[4]; /* Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3 */
-
-} EADC_T;
-
-
-
-/**
- @addtogroup EADC_CONST EADC Bit Field Definition
- Constant Definitions for EADC Controller
-@{ */
-#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */
-#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */
-
-#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */
-#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */
-
-#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */
-#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */
-
-#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */
-#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */
-
-#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */
-#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */
-
-#define EADC_CTL_ADRST_Pos (1) /*!< EADC_T::CTL: ADRST Position */
-#define EADC_CTL_ADRST_Msk (0x1ul << EADC_CTL_ADRST_Pos) /*!< EADC_T::CTL: ADRST Mask */
-
-#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */
-#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */
-
-#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */
-#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */
-
-#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */
-#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */
-
-#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */
-#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */
-
-#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */
-#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */
-
-#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */
-#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */
-
-#define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */
-#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */
-
-#define EADC_CTL_SMPTSEL_Pos (16) /*!< EADC_T::CTL: SMPTSEL Position */
-#define EADC_CTL_SMPTSEL_Msk (0x7ul << EADC_CTL_SMPTSEL_Pos) /*!< EADC_T::CTL: SMPTSEL Mask */
-
-#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */
-#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */
-
-#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */
-#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */
-
-#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */
-#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */
-
-#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */
-#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */
-
-#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */
-#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */
-
-#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */
-#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */
-
-#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */
-#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */
-
-#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */
-#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */
-
-#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */
-#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */
-
-#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */
-#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */
-
-#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */
-#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */
-
-#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */
-#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */
-
-#define EADC_INTSRC_SPLIE_Pos (0) /*!< EADC_T::INTSRC: SPLIE Position */
-#define EADC_INTSRC_SPLIE_Msk (0x7FFFFul << EADC_INTSRC_SPLIE_Pos) /*!< EADC_T::INTSRC: SPLIE Mask */
-
-#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */
-#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */
-
-#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */
-#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */
-
-#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */
-#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */
-
-#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */
-#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */
-
-#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */
-#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */
-
-#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */
-#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */
-
-#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */
-#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */
-
-#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */
-#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */
-
-#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */
-#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */
-
-#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */
-#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */
-
-#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */
-#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */
-
-#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */
-#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */
-
-#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */
-#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */
-
-#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */
-#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */
-
-#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */
-#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */
-
-#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */
-#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */
-
-#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */
-#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */
-
-#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */
-#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */
-
-#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */
-#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */
-
-#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */
-#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */
-
-#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */
-#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */
-
-#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */
-#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */
-
-#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */
-#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */
-
-#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */
-#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */
-
-#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */
-#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */
-
-#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */
-#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */
-
-#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */
-#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */
-
-#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */
-#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */
-
-#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */
-#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */
-
-#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */
-#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */
-
-#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */
-#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */
-
-#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */
-#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */
-
-#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */
-#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */
-
-#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */
-#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */
-
-#define EADC_DDAT_RESULT_Pos (0) /*!< EADC_T::DDAT: RESULT Position */
-#define EADC_DDAT_RESULT_Msk (0xfffful << EADC_DDAT_RESULT_Pos) /*!< EADC_T::DDAT: RESULT Mask */
-
-#define EADC_DDAT_OV_Pos (16) /*!< EADC_T::DDAT: OV Position */
-#define EADC_DDAT_OV_Msk (0x1ul << EADC_DDAT_OV_Pos) /*!< EADC_T::DDAT: OV Mask */
-
-#define EADC_DDAT_VALID_Pos (17) /*!< EADC_T::DDAT: VALID Position */
-#define EADC_DDAT_VALID_Msk (0x1ul << EADC_DDAT_VALID_Pos) /*!< EADC_T::DDAT: VALID Mask */
-
-
-/**@}*/ /* EADC_CONST */
-/**@}*/ /* end of EADC register group */
-
-
-/*---------------------- Controller Area Network Controller -------------------------*/
-/**
- @addtogroup CAN Controller Area Network Controller(CAN)
- Memory Mapped Structure for CAN Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-/**
- * @var CAN_IF_T::CREQ
- * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |MessageNumber|Message Number
- * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
- * | | |RAM is selected for data transfer.
- * | | |0x00: Not a valid Message Number, interpreted as 0x20.
- * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
- * |[15] |Busy |Busy Flag
- * | | |0 = Read/write action has finished.
- * | | |1 = Writing to the IFn Command Request Register is in progress.
- * | | |This bit can only be read by the software.
- * @var CAN_IF_T::CMASK
- * Offset: 0x24, 0x84 IFn Command Mask Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DAT_B |Access Data Bytes [7:4]
- * | | |Write Operation:
- * | | |0 = Data Bytes [7:4] unchanged.
- * | | |1 = Transfer Data Bytes [7:4] to Message Object.
- * | | |Read Operation:
- * | | |0 = Data Bytes [7:4] unchanged.
- * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
- * |[1] |DAT_A |Access Data Bytes [3:0]
- * | | |Write Operation:
- * | | |0 = Data Bytes [3:0] unchanged.
- * | | |1 = Transfer Data Bytes [3:0] to Message Object.
- * | | |Read Operation:
- * | | |0 = Data Bytes [3:0] unchanged.
- * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
- * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
- * | | |0 = TxRqst bit unchanged.
- * | | |1 = Set TxRqst bit.
- * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
- * | | |Access New Data Bit when Read Operation.
- * | | |0 = NewDat bit remains unchanged.
- * | | |1 = Clear NewDat bit in the Message Object.
- * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
- * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
- * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
- * | | |Write Operation:
- * | | |When writing to a Message Object, this bit is ignored.
- * | | |Read Operation:
- * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
- * | | |1 = Clear IntPnd bit in the Message Object.
- * |[4] |Control |Control Access Control Bits
- * | | |Write Operation:
- * | | |0 = Control Bits unchanged.
- * | | |1 = Transfer Control Bits to Message Object.
- * | | |Read Operation:
- * | | |0 = Control Bits unchanged.
- * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
- * |[5] |Arb |Access Arbitration Bits
- * | | |Write Operation:
- * | | |0 = Arbitration bits unchanged.
- * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
- * | | |Read Operation:
- * | | |0 = Arbitration bits unchanged.
- * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
- * |[6] |Mask |Access Mask Bits
- * | | |Write Operation:
- * | | |0 = Mask bits unchanged.
- * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
- * | | |Read Operation:
- * | | |0 = Mask bits unchanged.
- * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
- * |[7] |WR_RD |Write / Read Mode
- * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
- * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
- * @var CAN_IF_T::MASK1
- * Offset: 0x28, 0x88 IFn Mask 1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |Msk[15:0] |Identifier Mask 15-0
- * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
- * | | |1 = The corresponding identifier bit is used for acceptance filtering.
- * @var CAN_IF_T::MASK2
- * Offset: 0x2C, 0x8C IFn Mask 2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[12:0] |Msk[28:16]|Identifier Mask 28-16
- * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
- * | | |1 = The corresponding identifier bit is used for acceptance filtering.
- * |[14] |MDir |Mask Message Direction
- * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
- * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
- * |[15] |MXtd |Mask Extended Identifier
- * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
- * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
- * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
- * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
- * @var CAN_IF_T::ARB1
- * Offset: 0x30, 0x90 IFn Arbitration 1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |ID[15:0] |Message Identifier 15-0
- * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
- * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
- * @var CAN_IF_T::ARB2
- * Offset: 0x34, 0x94 IFn Arbitration 2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[12:0] |ID[28:16] |Message Identifier 28-16
- * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
- * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
- * |[13] |Dir |Message Direction
- * | | |0 = Direction is receive.
- * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
- * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
- * | | |1 = Direction is transmit.
- * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
- * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
- * |[14] |Xtd |Extended Identifier
- * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
- * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
- * |[15] |MsgVal |Message Valid
- * | | |0 = The Message Object is ignored by the Message Handler.
- * | | |1 = The Message Object is configured and should be considered by the Message Handler.
- * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
- * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
- * @var CAN_IF_T::MCON
- * Offset: 0x38, 0x98 IFn Message Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |DLC |Data Length Code
- * | | |0-8: Data Frame has 0-8 data bytes.
- * | | |9-15: Data Frame has 8 data bytes
- * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
- * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
- * | | |Data 0: 1st data byte of a CAN Data Frame
- * | | |Data 1: 2nd data byte of a CAN Data Frame
- * | | |Data 2: 3rd data byte of a CAN Data Frame
- * | | |Data 3: 4th data byte of a CAN Data Frame
- * | | |Data 4: 5th data byte of a CAN Data Frame
- * | | |Data 5: 6th data byte of a CAN Data Frame
- * | | |Data 6: 7th data byte of a CAN Data Frame
- * | | |Data 7 : 8th data byte of a CAN Data Frame
- * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
- * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
- * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
- * |[7] |EoB |End Of Buffer
- * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
- * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
- * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
- * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
- * |[8] |TxRqst |Transmit Request
- * | | |0 = This Message Object is not waiting for transmission.
- * | | |1 = The transmission of this Message Object is requested and is not yet done.
- * |[9] |RmtEn |Remote Enable Control
- * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
- * | | |1 = At the reception of a Remote Frame, TxRqst is set.
- * |[10] |RxIE |Receive Interrupt Enable Control
- * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
- * | | |1 = IntPnd will be set after a successful reception of a frame.
- * |[11] |TxIE |Transmit Interrupt Enable Control
- * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
- * | | |1 = IntPnd will be set after a successful transmission of a frame.
- * |[12] |UMask |Use Acceptance Mask
- * | | |0 = Mask ignored.
- * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
- * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
- * |[13] |IntPnd |Interrupt Pending
- * | | |0 = This message object is not the source of an interrupt.
- * | | |1 = This message object is the source of an interrupt.
- * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
- * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
- * | | |0 = No message lost since last time this bit was reset by the CPU.
- * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
- * |[15] |NewDat |New Data
- * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
- * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
- * @var CAN_IF_T::DAT_A1
- * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |Data0 |Data Byte 0
- * | | |1st data byte of a CAN Data Frame
- * |[15:8] |Data1 |Data Byte 1
- * | | |2nd data byte of a CAN Data Frame
- * @var CAN_IF_T::DAT_A2
- * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |Data2 |Data Byte 2
- * | | |3rd data byte of CAN Data Frame
- * |[15:8] |Data3 |Data Byte 3
- * | | |4th data byte of CAN Data Frame
- * @var CAN_IF_T::DAT_B1
- * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |Data4 |Data Byte 4
- * | | |5th data byte of CAN Data Frame
- * |[15:8] |Data5 |Data Byte 5
- * | | |6th data byte of CAN Data Frame
- * @var CAN_IF_T::DAT_B2
- * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |Data6 |Data Byte 6
- * | | |7th data byte of CAN Data Frame.
- * |[15:8] |Data7 |Data Byte 7
- * | | |8th data byte of CAN Data Frame.
- */
-
- __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */
- __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */
- __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */
- __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */
- __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */
- __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */
- __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */
- __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */
- __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */
- __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */
- __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */
- __I uint32_t RESERVE0[13];
-
-} CAN_IF_T;
-
-
-
-
-typedef struct
-{
-
-
-
-/**
- * @var CAN_T::CON
- * Offset: 0x00 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |Init |Init Initialization
- * | | |0 = Normal Operation.
- * | | |1 = Initialization is started.
- * |[1] |IE |Module Interrupt Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |SIE |Status Change Interrupt Enable Control
- * | | |0 = Disabled - No Status Change Interrupt will be generated.
- * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
- * |[3] |EIE |Error Interrupt Enable Control
- * | | |0 = Disabled - No Error Status Interrupt will be generated.
- * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
- * |[5] |DAR |Automatic Re-Transmission Disable Control
- * | | |0 = Automatic Retransmission of disturbed messages enabled.
- * | | |1 = Automatic Retransmission disabled.
- * |[6] |CCE |Configuration Change Enable Control
- * | | |0 = No write access to the Bit Timing Register.
- * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
- * |[7] |Test |Test Mode Enable Control
- * | | |0 = Normal Operation.
- * | | |1 = Test Mode.
- * @var CAN_T::STATUS
- * Offset: 0x04 Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
- * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
- * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
- * | | |The unused code '7' may be written by the CPU to check for updates.
- * | | |The following table describes the error code.
- * |[3] |TxOK |Transmitted A Message Successfully
- * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
- * | | |This bit is never reset by the CAN Core.
- * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
- * |[4] |RxOK |Received A Message Successfully
- * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
- * | | |This bit is never reset by the CAN Core.
- * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
- * |[5] |EPass |Error Passive (Read Only)
- * | | |0 = The CAN Core is error active.
- * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
- * |[6] |EWarn |Error Warning Status (Read Only)
- * | | |0 = Both error counters are below the error warning limit of 96.
- * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
- * |[7] |BOff |Bus-Off Status (Read Only)
- * | | |0 = The CAN module is not in bus-off state.
- * | | |1 = The CAN module is in bus-off state.
- * @var CAN_T::ERR
- * Offset: 0x08 Error Counter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TEC |Transmit Error Counter
- * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
- * |[14:8] |REC |Receive Error Counter
- * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
- * |[15] |RP |Receive Error Passive
- * | | |0 = The Receive Error Counter is below the error passive level.
- * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
- * @var CAN_T::BTIME
- * Offset: 0x0C Bit Timing Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |BRP |Baud Rate Prescaler
- * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
- * | | |The bit time is built up from a multiple of this quanta.
- * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
- * |[7:6] |SJW |(Re)Synchronization Jump Width
- * | | |0x0-0x3: Valid programmed values are [0 ... 3].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
- * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
- * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
- * |[14:12] |TSeg2 |Time Segment After Sample Point
- * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
- * @var CAN_T::IIDR
- * Offset: 0x10 Interrupt Identifier Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
- * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
- * | | |An interrupt remains pending until the application software has cleared it.
- * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
- * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
- * | | |The Status Interrupt has the highest priority.
- * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
- * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
- * | | |The Status Interrupt is cleared by reading the Status Register.
- * @var CAN_T::TEST
- * Offset: 0x14 Test Register (Register Map Note 1)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |Res |Reserved
- * | | |There are reserved bits.
- * | | |These bits are always read as '0' and must always be written with '0'.
- * |[2] |Basic |Basic Mode
- * | | |0 = Basic Mode disabled.
- * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
- * |[3] |Silent |Silent Mode
- * | | |0 = Normal operation.
- * | | |1 = The module is in Silent Mode.
- * |[4] |LBack |Loop Back Mode Enable Control
- * | | |0 = Loop Back Mode is disabled.
- * | | |1 = Loop Back Mode is enabled.
- * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
- * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
- * | | |01 = Sample Point can be monitored at CAN_TX pin.
- * | | |10 = CAN_TX pin drives a dominant ('0') value.
- * | | |11 = CAN_TX pin drives a recessive ('1') value.
- * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
- * | | |0 = The CAN bus is dominant (CAN_RX = '0').
- * | | |1 = The CAN bus is recessive (CAN_RX = '1').
- * @var CAN_T::BRPE
- * Offset: 0x18 Baud Rate Prescaler Extension Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension
- * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
- * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
- * @var CAN_T::IF
- * Offset: 0x20~0xFC CAN Interface Registers
- * ---------------------------------------------------------------------------------------------------
- * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
- *
- * @var CAN_T::TXREQ1
- * Offset: 0x100 Transmission Request Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
- * | | |0 = This Message Object is not waiting for transmission.
- * | | |1 = The transmission of this Message Object is requested and is not yet done.
- * | | |These bits are read only.
- * @var CAN_T::TXREQ2
- * Offset: 0x104 Transmission Request Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
- * | | |0 = This Message Object is not waiting for transmission.
- * | | |1 = The transmission of this Message Object is requested and is not yet done.
- * | | |These bits are read only.
- * @var CAN_T::NDAT1
- * Offset: 0x120 New Data Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
- * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
- * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
- * @var CAN_T::NDAT2
- * Offset: 0x124 New Data Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
- * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
- * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
- * @var CAN_T::IPND1
- * Offset: 0x140 Interrupt Pending Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
- * | | |0 = This message object is not the source of an interrupt.
- * | | |1 = This message object is the source of an interrupt.
- * @var CAN_T::IPND2
- * Offset: 0x144 Interrupt Pending Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
- * | | |0 = This message object is not the source of an interrupt.
- * | | |1 = This message object is the source of an interrupt.
- * @var CAN_T::MVLD1
- * Offset: 0x160 Message Valid Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
- * | | |0 = This Message Object is ignored by the Message Handler.
- * | | |1 = This Message Object is configured and should be considered by the Message Handler.
- * | | |Ex.
- * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
- * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
- * @var CAN_T::MVLD2
- * Offset: 0x164 Message Valid Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
- * | | |0 = This Message Object is ignored by the Message Handler.
- * | | |1 = This Message Object is configured and should be considered by the Message Handler.
- * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
- * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
- * @var CAN_T::WU_EN
- * Offset: 0x168 Wake-up Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WAKUP_EN |Wake-Up Enable Control
- * | | |0 = The wake-up function Disabled.
- * | | |1 = The wake-up function Enabled.
- * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
- * @var CAN_T::WU_STATUS
- * Offset: 0x16C Wake-up Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WAKUP_STS |Wake-Up Status
- * | | |0 = No wake-up event occurred.
- * | | |1 = Wake-up event occurred.
- * | | |Note: This bit can be cleared by writing '0'.
- */
-
- __IO uint32_t CON; /* Offset: 0x00 Control Register */
- __IO uint32_t STATUS; /* Offset: 0x04 Status Register */
- __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */
- __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */
- __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */
- __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */
- __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */
- __I uint32_t RESERVE0[1];
- __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */
- __I uint32_t RESERVE1[8];
- __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */
- __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */
- __I uint32_t RESERVE3[6];
- __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */
- __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */
- __I uint32_t RESERVE4[6];
- __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */
- __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */
- __I uint32_t RESERVE5[6];
- __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */
- __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */
- __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */
- __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */
-
-} CAN_T;
-
-
-
-/**
- @addtogroup CAN_CONST CAN Bit Field Definition
- Constant Definitions for CAN Controller
-@{ */
-/* CAN CON Bit Field Definitions */
-#define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */
-#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */
-
-#define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */
-#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */
-
-#define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */
-#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */
-
-#define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */
-#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */
-
-#define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */
-#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */
-
-#define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */
-#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */
-
-#define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */
-#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */
-
-/* CAN STATUS Bit Field Definitions */
-#define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */
-#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */
-
-#define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */
-#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */
-
-#define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */
-#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */
-
-#define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */
-#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */
-
-#define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */
-#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */
-
-#define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */
-#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */
-
-/* CAN ERR Bit Field Definitions */
-#define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */
-#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */
-
-#define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */
-#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */
-
-#define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */
-#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */
-
-/* CAN BTIME Bit Field Definitions */
-#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */
-#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */
-
-#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */
-#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */
-
-#define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */
-#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */
-
-#define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */
-#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */
-
-/* CAN IIDR Bit Field Definitions */
-#define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */
-#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */
-
-/* CAN TEST Bit Field Definitions */
-#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */
-#define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */
-
-#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */
-#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */
-
-#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */
-#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */
-
-#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */
-#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */
-
-#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */
-#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */
-
-/* CAN BPRE Bit Field Definitions */
-#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */
-#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */
-
-/* CAN IFn_CREQ Bit Field Definitions */
-#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */
-#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */
-
-#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */
-#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */
-
-/* CAN IFn_CMASK Bit Field Definitions */
-#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */
-#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */
-
-#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */
-#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */
-
-#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */
-#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */
-
-#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */
-#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */
-
-#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */
-#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
-
-#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
-#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */
-
-#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */
-#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */
-
-#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */
-#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */
-
-/* CAN IFn_MASK1 Bit Field Definitions */
-#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */
-#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */
-
-/* CAN IFn_MASK2 Bit Field Definitions */
-#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */
-#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */
-
-#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */
-#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */
-
-#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */
-#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */
-
-/* CAN IFn_ARB1 Bit Field Definitions */
-#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */
-#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */
-
-/* CAN IFn_ARB2 Bit Field Definitions */
-#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */
-#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */
-
-#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */
-#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */
-
-#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */
-#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */
-
-#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */
-#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */
-
-/* CAN IFn_MCON Bit Field Definitions */
-#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */
-#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */
-
-#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */
-#define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */
-
-#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */
-#define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */
-
-#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */
-#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */
-
-#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */
-#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */
-
-#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */
-#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */
-
-#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */
-#define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */
-
-#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */
-#define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */
-
-#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */
-#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */
-
-#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */
-#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */
-
-/* CAN IFn_DATA_A1 Bit Field Definitions */
-#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */
-#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */
-
-#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */
-#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */
-
-/* CAN IFn_DATA_A2 Bit Field Definitions */
-#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */
-#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */
-
-#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */
-#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */
-
-/* CAN IFn_DATA_B1 Bit Field Definitions */
-#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */
-#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */
-
-#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */
-#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */
-
-/* CAN IFn_DATA_B2 Bit Field Definitions */
-#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */
-#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */
-
-#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */
-#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */
-
-/* CAN IFn_TXRQST1 Bit Field Definitions */
-#define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */
-#define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */
-
-/* CAN IFn_TXRQST2 Bit Field Definitions */
-#define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */
-#define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */
-
-/* CAN IFn_NDAT1 Bit Field Definitions */
-#define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */
-#define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */
-
-/* CAN IFn_NDAT2 Bit Field Definitions */
-#define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */
-#define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */
-
-/* CAN IFn_IPND1 Bit Field Definitions */
-#define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */
-#define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */
-
-/* CAN IFn_IPND2 Bit Field Definitions */
-#define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */
-#define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */
-
-/* CAN IFn_MVLD1 Bit Field Definitions */
-#define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */
-#define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */
-
-/* CAN IFn_MVLD2 Bit Field Definitions */
-#define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */
-#define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */
-
-/* CAN WUEN Bit Field Definitions */
-#define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */
-#define CAN_WUEN_WAKUP_EN_Msk (0x1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */
-
-/* CAN WUSTATUS Bit Field Definitions */
-#define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
-#define CAN_WUSTATUS_WAKUP_STS_Msk (0x1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */
-
-
-/**@}*/ /* CAN_CONST */
-/**@}*/ /* end of CAN register group */
-
-
-/*---------------------- System Clock Controller -------------------------*/
-/**
- @addtogroup CLK System Clock Controller(CLK)
- Memory Mapped Structure for CLK Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var CLK_T::PWRCTL
- * Offset: 0x00 System Power-down Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HXTEN |External 4~24 MHz High-Speed Crystal Enable Bit (Write Protect)
- * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
- * | | |When the default clock source is from external 4~24 MHz high-speed crystal, this bit is set to 1 automatically.
- * | | |0 = External 4 ~ 24 MHz high speed crystal oscillator (HXT) Disabled.
- * | | |1 = External 4 MH~ 24 z high speed crystal oscillator (HXT) Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[1] |LXTEN |External 32.768 KHz Low-Speed Crystal Enable Bit (Write Protect)
- * | | |0 = External 32.768 kHz low-speed crystal oscillator (LXT) Disabled.
- * | | |1 = External 32.768 kHz low-speed crystal oscillator (LXT) Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[2] |HIRCEN |Internal 22.1184 MHz High-Speed Oscillator Enable Bit (Write Protect)
- * | | |0 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Disabled.
- * | | |1 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[3] |LIRCEN |Internal 10 KHz Low-Speed Oscillator Enable Bit (Write Protect)
- * | | |0 = Internal 10 kHz low speed RC oscillator (LIRC) Disabled.
- * | | |1 = Internal 10 kHz low speed RC oscillator (LIRC) Enabled.
- * |[4] |PDWKDLY |Enable The Wake-Up Delay Counter (Write Protect)
- * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
- * | | |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high-speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high-speed oscillator.
- * | | |0 = Clock cycles delay Disabled.
- * | | |1 = Clock cycles delay Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[5] |PDWKIEN |Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
- * | | |0 = Power-down Mode Wake-up Interrupt Disabled.
- * | | |1 = Power-down Mode Wake-up Interrupt Enabled.
- * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
- * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[6] |PDWKIF |Power-Down Mode Wake-Up Interrupt Status
- * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode
- * | | |The flag is set if the EINT0~5, GPIO, USBH, USBD, OTG, UART0~3, WDT, CAN0, ACMP01, BOD, RTC, TMR0~3, I2C0~1 or TK wake-up occurred.
- * | | |Note1: Write 1 to clear the bit to 0.
- * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
- * |[7] |PDEN |System Power-Down Enable (Write Protect)
- * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.
- * | | |(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set.(default)
- * | | |(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
- * | | |When chip wakes up from Power-down mode, this bit is auto cleared.
- * | | |Users need to set this bit again for next Power-down.
- * | | |In Power-down mode, external 4~24 MHz high-speed crystal and the internal 22.1184 MHz high-speed oscillator will be disabled in this mode, but the external 32.768 kHz low-speed crystal and internal 10 kHz low-speed oscillator are not controlled by Power-down mode.
- * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
- * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low-speed crystal or the internal 10 kHz low-speed oscillator.
- * | | |0 = Chip operating normally or chip in idle mode because of WFI command.
- * | | |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[8] |PDWTCPU |This Bit Control The Power-Down Entry Condition (Write Protect)
- * | | |0 = Chip enters Power-down mode when the PDEN bit is set to 1.
- * | | |1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[11:10] |HXTGAIN |4~24 MHz High-Speed Crystal Gain Control Bit
- * | | |(Write Protect)
- * | | |This is a protected register. Please refer to open lock sequence to program it.
- * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
- * | | |If gain control is enabled, crystal will consume more power than gain control off.
- * | | |00 = HXT frequency is lower than from 8 MHz.
- * | | |01 = HXT frequency is from 8 MHz to 12 MHz.
- * | | |10 = HXT frequency is from 12 MHz to 16 MHz.
- * | | |11 = HXT frequency is higher than 16 MHz.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[12] |HXTSELTYP |4~24 MHz High-Speed Crystal Type Select Bit (Write Protect)
- * | | |This is a protected register. Please refer to open lock sequence to program it.
- * | | |0 = Select INV type.
- * | | |1 = Select GM type.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var CLK_T::AHBCLK
- * Offset: 0x04 AHB Devices Clock Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit
- * | | |0 = PDMA peripheral clock Disabled.
- * | | |1 = PDMA peripheral clock Enabled.
- * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
- * | | |0 = Flash ISP peripheral clock Disabled.
- * | | |1 = Flash ISP peripheral clock Enabled.
- * |[3] |EBICKEN |EBI Controller Clock Enable Bit
- * | | |0 = EBI peripheral clock Disabled.
- * | | |1 = EBI peripheral clock Enabled.
- * |[4] |USBHCKEN |USB HOST Controller Clock Enable Bit
- * | | |0 = USB HOST peripheral clock Disabled.
- * | | |1 = USB HOST peripheral clock Enabled.
- * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit
- * | | |0 = CRC peripheral clock Disabled.
- * | | |1 = CRC peripheral clock Enabled.
- * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit In IDLE Mode
- * | | |0 = FMC peripheral clock Disabled when chip operating at IDLE mode.
- * | | |1 = FMC peripheral clock Enabled when chip operating at IDLE mode.
- * @var CLK_T::APBCLK0
- * Offset: 0x08 APB Devices Clock Enable Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect)
- * | | |0 = Watchdog Timer Clock Disabled.
- * | | |1 = Watchdog Timer Clock Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[1] |RTCCKEN |Real-Time-Clock APB Interface Clock Enable Bit
- * | | |This bit is used to control the RTC APB clock only.
- * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]).
- * | | |It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator.
- * | | |0 = RTC Clock Disabled.
- * | | |1 = RTC Clock Enabled.
- * |[2] |TMR0CKEN |Timer0 Clock Enable Bit
- * | | |0 = Timer0 Clock Disabled.
- * | | |1 = Timer0 Clock Enabled.
- * |[3] |TMR1CKEN |Timer1 Clock Enable Bit
- * | | |0 = Timer1 Clock Disabled.
- * | | |1 = Timer1 Clock Enabled.
- * |[4] |TMR2CKEN |Timer2 Clock Enable Bit
- * | | |0 = Timer2 Clock Disabled.
- * | | |1 = Timer2 Clock Enabled.
- * |[5] |TMR3CKEN |Timer3 Clock Enable Bit
- * | | |0 = Timer3 Clock Disabled.
- * | | |1 = Timer3 Clock Enabled.
- * |[6] |CLKOCKEN |CLKO Clock Enable Bit
- * | | |0 = CLKO Clock Disabled.
- * | | |1 = CLKO Clock Enabled.
- * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
- * | | |0 = Analog Comparator 0/1 Clock Disabled.
- * | | |1 = Analog Comparator 0/1 Clock Enabled.
- * |[8] |I2C0CKEN |I2C0 Clock Enable Bit
- * | | |0 = I2C0 Clock Disabled.
- * | | |1 = I2C0 Clock Enabled.
- * |[9] |I2C1CKEN |I2C1 Clock Enable Bit
- * | | |0 = I2C1 Clock Disabled.
- * | | |1 = I2C1 Clock Enabled.
- * |[12] |SPI0CKEN |SPI0 Clock Enable Bit
- * | | |0 = SPI0 Clock Disabled.
- * | | |1 = SPI0 Clock Enabled.
- * |[13] |SPI1CKEN |SPI1 Clock Enable Bit
- * | | |0 = SPI1 Clock Disabled.
- * | | |1 = SPI1 Clock Enabled.
- * |[14] |SPI2CKEN |SPI2 Clock Enable Bit
- * | | |0 = SPI2 Clock Disabled.
- * | | |1 = SPI2 Clock Enabled.
- * |[16] |UART0CKEN |UART0 Clock Enable Bit
- * | | |0 = UART0 clock Disabled.
- * | | |1 = UART0 clock Enabled.
- * |[17] |UART1CKEN |UART1 Clock Enable Bit
- * | | |0 = UART1 clock Disabled.
- * | | |1 = UART1 clock Enabled.
- * |[18] |UART2CKEN |UART2 Clock Enable Bit
- * | | |0 = UART2 clock Disabled.
- * | | |1 = UART2 clock Enabled.
- * |[19] |UART3CKEN |UART3 Clock Enable Bit
- * | | |0 = UART3 clock Disabled.
- * | | |1 = UART3 clock Enabled.
- * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
- * | | |0 = CAN0 clock Disabled.
- * | | |1 = CAN0 clock Enabled.
- * |[26] |OTGCKEN |USB OTG Clock Enable Bit
- * | | |0 = USB OTG clock Disabled.
- * | | |1 = USB OTG clock Enabled.
- * |[27] |USBDCKEN |USB Device Clock Enable Bit
- * | | |0 = USB Device clock Disabled.
- * | | |1 = USB Device clock Enabled.
- * |[28] |EADCCKEN |Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit
- * | | |0 = EADC clock Disabled.
- * | | |1 = EADC clock Enabled.
- * @var CLK_T::APBCLK1
- * Offset: 0x0C APB Devices Clock Enable Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SC0CKEN |SC0 Clock Enable Bit
- * | | |0 = SC0 Clock Disabled.
- * | | |1 = SC0 Clock Enabled.
- * |[12] |DACCKEN |DAC Clock Enable Bit
- * | | |0 = DAC Clock Disabled.
- * | | |1 = DAC Clock Enabled.
- * |[16] |PWM0CKEN |PWM0 Clock Enable Bit
- * | | |0 = PWM0 Clock Disabled.
- * | | |1 = PWM0 Clock Enabled.
- * |[17] |PWM1CKEN |PWM1 Clock Enable Bit
- * | | |0 = PWM1 Clock Disabled.
- * | | |1 = PWM1 Clock Enabled.
- * |[25] |TKCKEN |Touch Key Clock Enable Bit
- * | | |0 = Touch Key Clock Disabled.
- * | | |1 = Touch key Clock Enabled.
- * @var CLK_T::CLKSEL0
- * Offset: 0x10 Clock Source Select Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
- * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
- * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
- * | | |Therefore the default value is either 000b or 111b.
- * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |010 = Clock source from PLL clock.
- * | | |011 = Clock source from internal 10 kHz low-speed oscillator clock.
- * | | |111= Clock source from internal 22.1184 MHz high-speed oscillator clock.
- * | | |Other = Reserved.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect)
- * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
- * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |010 = Clock source from external 4~24 MHz high-speed crystal clock/2.
- * | | |011 = Clock source from HCLK/2.
- * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2.
- * | | |Note: if SysTick clock source is not from HCLK (i.e.
- * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[6] |PCLK0SEL |PCLK0 Clock Source Selection (Write Protect)
- * | | |0 = APB0 BUS clock source from HCLK.
- * | | |1 = APB0 BUS clock source from HCLK/2.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[7] |PCLK1SEL |PCLK1 Clock Source Selection (Write Protect)
- * | | |0 = APB1 BUS clock source from HCLK.
- * | | |1 = APB1 BUS clock source from HCLK/2.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var CLK_T::CLKSEL1
- * Offset: 0x14 Clock Source Select Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
- * | | |00 = Reserved.
- * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |10 = Clock source from PCLK0/2048 clock.
- * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
- * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
- * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |010 = Clock source from PCLK0.
- * | | |011 = Clock source from external clock T0 pin
- * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
- * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
- * | | |Others = Reserved.
- * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection
- * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |010 = Clock source from PCLK0.
- * | | |011 = Clock source from external clock T1 pin
- * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
- * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
- * | | |Others = Reserved.
- * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection
- * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |010 = Clock source from PCLK1.
- * | | |011 = Clock source from external clock T2 pin
- * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
- * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
- * | | |Others = Reserved.
- * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection
- * | | |000 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |001 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |010 = Clock source from PCLK1.
- * | | |011 = Clock source from external clock T3 pin.
- * | | |101 = Clock source from internal 10 kHz low-speed oscillator clock.
- * | | |111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
- * | | |Others = Reserved.
- * |[25:24] |UARTSEL |UART Clock Source Selection
- * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT).
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
- * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC).
- * |[29:28] |CLKOSEL |Clock Divider Clock Source Selection
- * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |01 = Clock source from external 32.768 kHz low-speed crystal clock.
- * | | |10 = Clock source from HCLK.
- * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
- * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection
- * | | |10 = Clock source from PCLK0/2048 clock.
- * | | |11 = Clock source from internal 10 kHz low-speed oscillator clock.
- * | | |Others = Reserved.
- * @var CLK_T::CLKSEL2
- * Offset: 0x18 Clock Source Select Control Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PWM0SEL |PWM0 Clock Source Selection
- * | | |The peripheral clock source of PWM0 is defined by PWM0SEL.
- * | | |0 = Clock source from PLL clock.
- * | | |1 = Clock source from PCLK0.
- * |[1] |PWM1SEL |PWM1 Clock Source Selection
- * | | |The peripheral clock source of PWM1 is defined by PWM1SEL.
- * | | |0 = Clock source from PLL clock.
- * | | |1 = Clock source from PCLK1.
- * |[3:2] |SPI0SEL |SPI0 Clock Source Selection
- * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from PCLK0.
- * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
- * |[5:4] |SPI1SEL |SPI1 Clock Source Selection
- * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from PCLK1.
- * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
- * |[7:6] |SPI2SEL |SPI2 Clock Source Selection
- * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from PCLK0.
- * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
- * @var CLK_T::CLKSEL3
- * Offset: 0x1C Clock Source Select Control Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |SC0SEL |SC0 Clock Source Selection
- * | | |00 = Clock source from external 4~24 MHz high-speed crystal clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from PCLK0.
- * | | |11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
- * |[8] |RTCSEL |RTC Clock Source Selection
- * | | |0 = Clock source from external 32.768 kHz low-speed oscillator.
- * | | |1 = Clock source from internal 10 kHz low speed RC oscillator.
- * @var CLK_T::CLKDIV0
- * Offset: 0x20 Clock Divider Number Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
- * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
- * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock
- * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
- * |[11:8] |UARTDIV |UART Clock Divide Number From UART Clock Source
- * | | |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
- * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source
- * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
- * @var CLK_T::CLKDIV1
- * Offset: 0x24 Clock Divider Number Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
- * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).
- * @var CLK_T::PLLCTL
- * Offset: 0x40 PLL Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8:0] |FBDIV |PLL Feedback Divider Control Pins (Write Protect)
- * | | |Refer to the formulas below the table.
- * |[13:9] |INDIV |PLL Input Divider Control Pins (Write Protect)
- * | | |Refer to the formulas below the table.
- * |[15:14] |OUTDIV |PLL Output Divider Control Pins (Write Protect)
- * | | |Refer to the formulas below the table.
- * |[16] |PD |Power-Down Mode (Write Protect)
- * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
- * | | |0 = PLL is in normal mode.
- * | | |1 = PLL is in Power-down mode (default).
- * |[17] |BP |PLL Bypass Control (Write Protect)
- * | | |0 = PLL is in normal mode (default).
- * | | |1 = PLL clock output is same as PLL input clock FIN.
- * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect)
- * | | |0 = PLL FOUT Enabled.
- * | | |1 = PLL FOUT is fixed low.
- * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect)
- * | | |0 = PLL source clock from external 4~24 MHz high-speed crystal (HXT).
- * | | |1 = PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC).
- * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect)
- * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz).
- * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz).
- * @var CLK_T::STATUS
- * Offset: 0x50 Clock Status Monitor Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HXTSTB |External 4~24 MHz High-Speed Crystal Clock Source Stable Flag (Read Only)
- * | | |0 = External 4~24 MHz high-speed crystal clock is not stable or disabled.
- * | | |1 = External 4~24 MHz high-speed crystal clock is stable and enabled.
- * |[1] |LXTSTB |External 32.768 kHz Low-Speed Crystal Clock Source Stable Flag (Read Only)
- * | | |0 = External 32.768 kHz low-speed crystal clock is not stable or disabled.
- * | | |1 = External 32.768 kHz low-speed crystal clock is stabled and enabled.
- * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
- * | | |0 = Internal PLL clock is not stable or disabled.
- * | | |1 = Internal PLL clock is stable and enabled.
- * |[3] |LIRCSTB |Internal 10 KHz Low-Speed Oscillator Clock Source Stable Flag (Read Only)
- * | | |0 = Internal 10 kHz low-speed oscillator clock is not stable or disabled.
- * | | |1 = Internal 10 kHz low-speed oscillator clock is stable and enabled.
- * |[4] |HIRCSTB |Internal 22.1184 MHz High-Speed Oscillator Clock Source Stable Flag (Read Only)
- * | | |0 = Internal 22.1184 MHz high-speed oscillator clock is not stable or disabled.
- * | | |1 = Internal 22.1184 MHz high-speed oscillator clock is stable and enabled.
- * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only)
- * | | |This bit is updated when software switches system clock source.
- * | | |If switch target clock is stable, this bit will be set to 0.
- * | | |If switch target clock is not stable, this bit will be set to 1.
- * | | |0 = Clock switching success.
- * | | |1 = Clock switching failure.
- * | | |Note: Write 1 to clear the bit to 0.
- * @var CLK_T::CLKOCTL
- * Offset: 0x60 Clock Output Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |FREQSEL |Clock Output Frequency Selection
- * | | |The formula of output frequency is
- * | | |Fout = Fin/2(N+1).
- * | | |Fin is the input clock frequency.
- * | | |Fout is the frequency of divider output clock.
- * | | |N is the 4-bit value of FREQSEL[3:0].
- * |[4] |CLKOEN |Clock Output Enable Bit
- * | | |0 =Clock Output function Disabled.
- * | | |1 = Clock Output function Enabled.
- * |[5] |DIV1EN |Clock Output Divide One Enable Bit
- * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL.
- * | | |1 = Clock Output will output clock with source frequency.
- * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit
- * | | |0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled.
- * | | |1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled.
- * @var CLK_T::CLKDCTL
- * Offset: 0x70 Clock Fail Detector Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit
- * | | |0 = HXT clock Fail detector Disabled.
- * | | |1 = HXT clock Fail detector Enabled.
- * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit
- * | | |0 = HXT clock Fail interrupt Disabled.
- * | | |1 = HXT clock Fail interrupt Enabled.
- * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit
- * | | |0 = LXT clock Fail detector Disabled.
- * | | |1 = LXT clock Fail detector Enabled.
- * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit
- * | | |0 = LXT clock Fail interrupt Disabled.
- * | | |1 = LXT clock Fail interrupt Enabled.
- * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit
- * | | |0 = HXT clock frequency monitor Disabled.
- * | | |1 = HXT clock frequency monitor Enabled.
- * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit
- * | | |0 = HXT clock frequency monitor fail interrupt Disabled.
- * | | |1 = HXT clock frequency monitor fail interrupt Enabled.
- * @var CLK_T::CLKDSTS
- * Offset: 0x74 Clock Fail Detector Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag
- * | | |0 = HXT clock normal.
- * | | |1 = HXT clock stop
- * | | |Note: Write 1 to clear the bit to 0.
- * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag
- * | | |0 = LXT clock normal.
- * | | |1 = LXT stop
- * | | |Note: Write 1 to clear the bit to 0.
- * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag
- * | | |0 = HXT clock normal.
- * | | |1 = HXT clock frequency abnormal
- * | | |Note: Write 1 to clear the bit to 0.
- * @var CLK_T::CDUPB
- * Offset: 0x78 Clock Frequency Detector Upper Boundary Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary
- * | | |The bits define the high value of frequency monitor window.
- * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
- * @var CLK_T::CDLOWB
- * Offset: 0x7C Clock Frequency Detector Low Boundary Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[9:0] |LOWERBD |HXT Clock Frequency Detector Low Boundary
- * | | |The bits define the low value of frequency monitor window.
- * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
- */
-
- __IO uint32_t PWRCTL; /* Offset: 0x00 System Power-down Control Register */
- __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
- __IO uint32_t APBCLK0; /* Offset: 0x08 APB Devices Clock Enable Control Register 0 */
- __IO uint32_t APBCLK1; /* Offset: 0x0C APB Devices Clock Enable Control Register 1 */
- __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
- __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
- __IO uint32_t CLKSEL2; /* Offset: 0x18 Clock Source Select Control Register 2 */
- __IO uint32_t CLKSEL3; /* Offset: 0x1C Clock Source Select Control Register 3 */
- __IO uint32_t CLKDIV0; /* Offset: 0x20 Clock Divider Number Register 0 */
- __IO uint32_t CLKDIV1; /* Offset: 0x24 Clock Divider Number Register 1 */
- __I uint32_t RESERVE0[6];
- __IO uint32_t PLLCTL; /* Offset: 0x40 PLL Control Register */
- __I uint32_t RESERVE1[3];
- __I uint32_t STATUS; /* Offset: 0x50 Clock Status Monitor Register */
- __I uint32_t RESERVE2[3];
- __IO uint32_t CLKOCTL; /* Offset: 0x60 Clock Output Control Register */
- __I uint32_t RESERVE3[3];
- __IO uint32_t CLKDCTL; /* Offset: 0x70 Clock Fail Detector Control Register */
- __IO uint32_t CLKDSTS; /* Offset: 0x74 Clock Fail Detector Status Register */
- __IO uint32_t CDUPB; /* Offset: 0x78 Clock Frequency Detector Upper Boundary Register */
- __IO uint32_t CDLOWB; /* Offset: 0x7C Clock Frequency Detector Low Boundary Register */
-
-} CLK_T;
-
-
-
-/**
- @addtogroup CLK_CONST CLK Bit Field Definition
- Constant Definitions for CLK Controller
-@{ */
-
-#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */
-#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */
-
-#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */
-#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */
-
-#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */
-#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */
-
-#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */
-#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */
-
-#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */
-#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */
-
-#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */
-#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */
-
-#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */
-#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */
-
-#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */
-#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */
-
-#define CLK_PWRCTL_PDWTCPU_Pos (8) /*!< CLK_T::PWRCTL: PDWTCPU Position */
-#define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /*!< CLK_T::PWRCTL: PDWTCPU Mask */
-
-#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */
-#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */
-
-#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */
-#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */
-
-#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */
-#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */
-
-#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */
-#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */
-
-#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */
-#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */
-
-#define CLK_AHBCLK_USBHCKEN_Pos (4) /*!< CLK_T::AHBCLK: USBHCKEN Position */
-#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */
-
-#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */
-#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */
-
-#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */
-#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */
-
-#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */
-#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */
-
-#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */
-#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */
-
-#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */
-#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */
-
-#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */
-#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */
-
-#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */
-#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */
-
-#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */
-#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */
-
-#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */
-#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */
-
-#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */
-#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */
-
-#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */
-#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */
-
-#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */
-#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */
-
-#define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: SPI0CKEN Position */
-#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */
-
-#define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI1CKEN Position */
-#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */
-
-#define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI2CKEN Position */
-#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */
-
-#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */
-#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */
-
-#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */
-#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */
-
-#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */
-#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */
-
-#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */
-#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */
-
-#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
-#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
-
-#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */
-#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */
-
-#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */
-#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */
-
-#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */
-#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */
-
-#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */
-#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */
-
-#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */
-#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */
-
-#define CLK_APBCLK1_PWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: PWM0CKEN Position */
-#define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) /*!< CLK_T::APBCLK1: PWM0CKEN Mask */
-
-#define CLK_APBCLK1_PWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: PWM1CKEN Position */
-#define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) /*!< CLK_T::APBCLK1: PWM1CKEN Mask */
-
-#define CLK_APBCLK1_TKCKEN_Pos (25) /*!< CLK_T::APBCLK1: TKCKEN Position */
-#define CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos) /*!< CLK_T::APBCLK1: TKCKEN Mask */
-
-#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */
-#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */
-
-#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */
-#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */
-
-#define CLK_CLKSEL0_PCLK0SEL_Pos (6) /*!< CLK_T::CLKSEL0: PCLK0SEL Position */
-#define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK0SEL Mask */
-
-#define CLK_CLKSEL0_PCLK1SEL_Pos (7) /*!< CLK_T::CLKSEL0: PCLK1SEL Position */
-#define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) /*!< CLK_T::CLKSEL0: PCLK1SEL Mask */
-
-#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
-#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
-
-#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
-#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
-
-#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */
-#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */
-
-#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */
-#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */
-
-#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */
-#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */
-
-#define CLK_CLKSEL1_UARTSEL_Pos (24) /*!< CLK_T::CLKSEL1: UARTSEL Position */
-#define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /*!< CLK_T::CLKSEL1: UARTSEL Mask */
-
-#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */
-#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */
-
-#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */
-#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */
-
-#define CLK_CLKSEL2_PWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: PWM0SEL Position */
-#define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) /*!< CLK_T::CLKSEL2: PWM0SEL Mask */
-
-#define CLK_CLKSEL2_PWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: PWM1SEL Position */
-#define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) /*!< CLK_T::CLKSEL2: PWM1SEL Mask */
-
-#define CLK_CLKSEL2_SPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: SPI0SEL Position */
-#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */
-
-#define CLK_CLKSEL2_SPI1SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI1SEL Position */
-#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */
-
-#define CLK_CLKSEL2_SPI2SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI2SEL Position */
-#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */
-
-#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
-#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
-
-#define CLK_CLKSEL3_RTCSEL_Pos (8) /*!< CLK_T::CLKSEL3: RTCSEL Position */
-#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) /*!< CLK_T::CLKSEL3: RTCSEL Mask */
-
-#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */
-#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */
-
-#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */
-#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */
-
-#define CLK_CLKDIV0_UARTDIV_Pos (8) /*!< CLK_T::CLKDIV0: UARTDIV Position */
-#define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLK_T::CLKDIV0: UARTDIV Mask */
-
-#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */
-#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */
-
-#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */
-#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */
-
-#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */
-#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */
-
-#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */
-#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */
-
-#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */
-#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */
-
-#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */
-#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */
-
-#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */
-#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */
-
-#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */
-#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */
-
-#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */
-#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */
-
-#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */
-#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */
-
-#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */
-#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */
-
-#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */
-#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */
-
-#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */
-#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */
-
-#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */
-#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */
-
-#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */
-#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */
-
-#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */
-#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */
-
-#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */
-#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */
-
-#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */
-#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */
-
-#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */
-#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */
-
-#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */
-#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */
-
-#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */
-#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */
-
-#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */
-#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */
-
-#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */
-#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */
-
-#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */
-#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */
-
-#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */
-#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */
-
-#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */
-#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */
-
-#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */
-#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */
-
-#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */
-#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */
-
-#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */
-#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */
-
-#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */
-#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */
-
-#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */
-#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */
-
-
-/**@}*/ /* CLK_CONST */
-/**@}*/ /* end of CLK register group */
-
-
-
-/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
-/**
- @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
- Memory Mapped Structure for CRC Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var CRC_T::CTL
- * Offset: 0x00 CRC Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CRCEN |CRC Channel Enable Bit
- * | | |0 = No effect.
- * | | |1 = CRC operation Enabled.
- * |[1] |CRCRST |CRC Engine Reset
- * | | |0 = No effect.
- * | | |1 = Reset the internal CRC state machine and internal buffer.
- * | | |The others contents of CRC_CTL register will not be cleared.
- * | | |Note1: This bit will be cleared automatically.
- * | | |Note2: Setting this bit will reload the initial seed value (CRC_SEED register).
- * |[24] |DATREV |Write Data Bit Order Reverse
- * | | |This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
- * | | |0 = Bit order reversed for CRC write data in Disabled.
- * | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
- * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
- * |[25] |CHKSREV |Checksum Bit Order Reverse
- * | | |This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
- * | | |0 = Bit order reverse for CRC checksum Disabled.
- * | | |1 = Bit order reverse for CRC checksum Enabled.
- * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
- * |[26] |DATFMT |Write Data 1's Complement
- * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
- * | | |0 = 1's complement for CRC writes data in Disabled.
- * | | |1 = 1's complement for CRC writes data in Enabled.
- * |[27] |CHKSFMT |Checksum 1's Complement
- * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
- * | | |0 = 1's complement for CRC checksum Disabled.
- * | | |1 = 1's complement for CRC checksum Enabled.
- * |[29:28] |DATLEN |CPU Write Data Length
- * | | |This field indicates the write data length.
- * | | |00 = Data length is 8-bit mode.
- * | | |01 = Data length is 16-bit mode.
- * | | |1x = Data length is 32-bit mode.
- * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
- * |[31:30] |CRCMODE |CRC Polynomial Mode
- * | | |This field indicates the CRC operation polynomial mode.
- * | | |00 = CRC-CCITT Polynomial mode.
- * | | |01 = CRC-8 Polynomial mode.
- * | | |10 = CRC-16 Polynomial mode.
- * | | |11 = CRC-32 Polynomial mode.
- * @var CRC_T::DAT
- * Offset: 0x04 CRC Write Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |DATA |CRC Write Data Bits
- * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
- * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
- * @var CRC_T::SEED
- * Offset: 0x08 CRC Seed Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |SEED |CRC Seed Value
- * | | |This field indicates the CRC seed value.
- * @var CRC_T::CHECKSUM
- * Offset: 0x0C CRC Checksum Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |CHECKSUM |CRC Checksum Results
- * | | |This field indicates the CRC checksum result.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */
- __IO uint32_t DAT; /* Offset: 0x04 CRC Write Data Register */
- __IO uint32_t SEED; /* Offset: 0x08 CRC Seed Register */
- __I uint32_t CHECKSUM; /* Offset: 0x0C CRC Checksum Register */
-
-} CRC_T;
-
-
-
-/**
- @addtogroup CRC_CONST CRC Bit Field Definition
- Constant Definitions for CRC Controller
-@{ */
-
-#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
-#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
-
-#define CRC_CTL_CRCRST_Pos (1) /*!< CRC_T::CTL: CRCRST Position */
-#define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /*!< CRC_T::CTL: CRCRST Mask */
-
-#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
-#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
-
-#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
-#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
-
-#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
-#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
-
-#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
-#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
-
-#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
-#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
-
-#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
-#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
-
-#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
-#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
-
-#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
-#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
-
-#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
-#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
-
-/**@}*/ /* CRC_CONST */
-/**@}*/ /* end of CRC register group */
-
-
-/*---------------------- Digital to Analog Converter -------------------------*/
-/**
- @addtogroup DAC Digital to Analog Converter(DAC)
- Memory Mapped Structure for DAC Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-/**
- * @var DAC_T::CTL
- * Offset: 0x00 DAC Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DACEN |DAC Enable Bit
- * | | |0 = DAC is Disabled.
- * | | |1 = DAC is Enabled.
- * |[1] |DACIEN |DAC Interrupt Enable Bit
- * | | |0 = Interrupt is Disabled.
- * | | |1 = Interrupt is Enabled.
- * |[2] |DMAEN |DMA Mode Enable Bit
- * | | |0 = DMA mode Disabled.
- * | | |1 = DMA mode Enabled.
- * |[3] |DMAURIEN |DMA Under-Run Interrupt Enable Bit
- * | | |0 = DMA under run interrupt Disabled.
- * | | |1 = DMA under run interrupt Enabled.
- * |[4] |TRGEN |Trigger Mode Enable Bit
- * | | |0 = DAC event trigger mode Disabled.
- * | | |1 = DAC event trigger mode Enabled.
- * |[7:5] |TRGSEL |Trigger Source Selection
- * | | |000 = Software trigger.
- * | | |001 = External pin STDAC trigger.
- * | | |010 = Timer 0 trigger.
- * | | |011 = Timer 1 trigger.
- * | | |100 = Timer 2 trigger.
- * | | |101 = Timer 3 trigger.
- * | | |110 = PWM0 trigger.
- * | | |111 = PWM1 trigger.
- * |[8] |BYPASS |Bypass Buffer Mode
- * | | |0 = Output voltage buffer Enabled.
- * | | |1 = Output voltage buffer Disabled.
- * |[10] |LALIGN |DAC Data Left-Aligned Enabled Control
- * | | |0 = Right alignment.
- * | | |1 = Left alignment.
- * |[13:12] |ETRGSEL |External Pin Trigger Selection
- * | | |00 = Low level trigger.
- * | | |01 = High level trigger.
- * | | |10 = Falling edge trigger.
- * | | |11 = Rising edge trigger.
- * @var DAC_T::SWTRG
- * Offset: 0x04 DAC Software Trigger Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SWTRG |Software Trigger
- * | | |0 = Software trigger Disabled.
- * | | |1 = Software trigger Enabled.
- * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
- * @var DAC_T::DAT
- * Offset: 0x08 DAC Data Holding Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |DAC_DAT |DAC 12-Bit Holding Data
- * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output.
- * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
- * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
- * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
- * @var DAC_T::DATOUT
- * Offset: 0x0C DAC Data Output Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |DATOUT |DAC 12-Bit Output Data
- * | | |These bits are current digital data for DAC output conversion.
- * | | |It is loaded from DAC_DAT register and user cannot write it directly.
- * @var DAC_T::STATUS
- * Offset: 0x10 DAC Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FINISH |DAC Conversion Complete Finish Flag
- * | | |0 = DAC is in conversion state.
- * | | |1 = DAC conversion finish.
- * | | |This bit set to 1 when conversion time counter counts to SETTLET.
- * | | |It is cleared to 0 when DAC starts a new conversion.
- * | | |User writes 1 to clear this bit to 0.
- * |[1] |DMAUDR |DMA Under Run Interrupt Flag
- * | | |0 = No DMA under-run error condition occurred.
- * | | |1 = DMA under-run error condition occurred.
- * | | |User writes 1 to clear this bit.
- * |[8] |BUSY |DAC Busy Flag (Read Only)
- * | | |0 = DAC is ready for next conversion.
- * | | |1 = DAC is busy in conversion.
- * | | |This is read only bit.
- * @var DAC_T::TCTL
- * Offset: 0x14 DAC Timing Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[9:0] |SETTLET |DAC Output Settling Time
- * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
- * | | |For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 DAC Control Register */
- __IO uint32_t SWTRG; /* Offset: 0x04 DAC Software Trigger Control Register */
- __IO uint32_t DAT; /* Offset: 0x08 DAC Data Holding Register */
- __I uint32_t DATOUT; /* Offset: 0x0C DAC Data Output Register */
- __IO uint32_t STATUS; /* Offset: 0x10 DAC Status Register */
- __IO uint32_t TCTL; /* Offset: 0x14 DAC Timing Control Register */
-
-} DAC_T;
-
-
-
-/**
- @addtogroup DAC_CONST DAC Bit Field Definition
- Constant Definitions for DAC Controller
-@{ */
-
-#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
-#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
-
-#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
-#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
-
-#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
-#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
-
-#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
-#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
-
-#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
-#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
-
-#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
-#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
-
-#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
-#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
-
-#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
-#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
-
-#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
-#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
-
-#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
-#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
-
-#define DAC_DAT_DAC_DAT_Pos (0) /*!< DAC_T::DAT: DAC_DAT Position */
-#define DAC_DAT_DAC_DAT_Msk (0xfffful << DAC_DAT_DAC_DAT_Pos) /*!< DAC_T::DAT: DAC_DAT Mask */
-
-#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
-#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
-
-#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
-#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
-
-#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
-#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
-
-#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
-#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
-
-#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
-#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
-
-/**@}*/ /* DAC_CONST */
-/**@}*/ /* end of DAC register group */
-
-
-/*---------------------- External Bus Interface Controller -------------------------*/
-/**
- @addtogroup EBI External Bus Interface Controller(EBI)
- Memory Mapped Structure for EBI Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var EBI_T::CTL0
- * Offset: 0x00 External Bus Interface Bank0 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EN |EBI Enable Bit
- * | | |This bit is the functional enable bit for EBI.
- * | | |0 = EBI function Disabled.
- * | | |1 = EBI function Enabled.
- * |[1] |DW16 |EBI Data Width 16-Bit Select
- * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
- * | | |0 = EBI data width is 8-bit.
- * | | |1 = EBI data width is 16-bit.
- * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
- * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
- * | | |0 = Chip select pin (EBI_nCS) is active low.
- * | | |1 = Chip select pin (EBI_nCS) is active high.
- * |[10:8] |MCLKDIV |External Output Clock Divider
- * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
- * | | |000 = HCLK/1.
- * | | |001 = HCLK/2.
- * | | |010 = HCLK/4.
- * | | |011 = HCLK/8.
- * | | |100 = HCLK/16.
- * | | |101 = HCLK/32.
- * | | |110 = Reserved.
- * | | |111 = Reserved.
- * |[18:16] |TALE |Extend Time Of ALE
- * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
- * | | |tALE = (TALE+1)*EBI_MCLK.
- * | | |Note: This field only available in EBI_CTL0 register
- * |[24] |WBUFEN |EBI Write Buffer Enable Bit
- * | | |0 = EBI write buffer Disabled.
- * | | |1 = EBI write buffer Enabled.
- * | | |Note: This bit only available in EBI_CTL0 register
- * @var EBI_T::TCTL0
- * Offset: 0x04 External Bus Interface Bank0 Timing Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:3] |TACC |EBI Data Access Time
- * | | |TACC define data access time (tACC).
- * | | |tACC = (TACC +1) * EBI_MCLK.
- * |[10:8] |TAHD |EBI Data Access Hold Time
- * | | |TAHD define data access hold time (tAHD).
- * | | |tAHD = (TAHD +1) * EBI_MCLK.
- * |[15:12] |W2X |Idle Cycle After Write
- * | | |This field defines the number of W2X idle cycle.
- * | | |W2X idle cycle = (W2X * EBI_MCLK).
- * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
- * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
- * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
- * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
- * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
- * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
- * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
- * |[27:24] |R2R |Idle Cycle Between Read-To-Read
- * | | |This field defines the number of R2R idle cycle.
- * | | |R2R idle cycle = (R2R * EBI_MCLK).
- * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
- * @var EBI_T::CTL1
- * Offset: 0x10 External Bus Interface Bank1 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EN |EBI Enable Bit
- * | | |This bit is the functional enable bit for EBI.
- * | | |0 = EBI function Disabled.
- * | | |1 = EBI function Enabled.
- * |[1] |DW16 |EBI Data Width 16-Bit Select
- * | | |This bit defines if the EBI data width is 8-bit or 16-bit.
- * | | |0 = EBI data width is 8-bit.
- * | | |1 = EBI data width is 16-bit.
- * |[2] |CSPOLINV |Chip Select Pin Polar Inverse
- * | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
- * | | |0 = Chip select pin (EBI_nCS) is active low.
- * | | |1 = Chip select pin (EBI_nCS) is active high.
- * |[10:8] |MCLKDIV |External Output Clock Divider
- * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
- * | | |000 = HCLK/1.
- * | | |001 = HCLK/2.
- * | | |010 = HCLK/4.
- * | | |011 = HCLK/8.
- * | | |100 = HCLK/16.
- * | | |101 = HCLK/32.
- * | | |110 = Reserved.
- * | | |111 = Reserved.
- * |[18:16] |TALE |Extend Time Of ALE
- * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
- * | | |tALE = (TALE+1)*EBI_MCLK.
- * | | |Note: This field only available in EBI_CTL0 register
- * |[24] |WBUFEN |EBI Write Buffer Enable Bit
- * | | |0 = EBI write buffer Disabled.
- * | | |1 = EBI write buffer Enabled.
- * | | |Note: This bit only available in EBI_CTL0 register
- * @var EBI_T::TCTL1
- * Offset: 0x14 External Bus Interface Bank1 Timing Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:3] |TACC |EBI Data Access Time
- * | | |TACC define data access time (tACC).
- * | | |tACC = (TACC +1) * EBI_MCLK.
- * |[10:8] |TAHD |EBI Data Access Hold Time
- * | | |TAHD define data access hold time (tAHD).
- * | | |tAHD = (TAHD +1) * EBI_MCLK.
- * |[15:12] |W2X |Idle Cycle After Write
- * | | |This field defines the number of W2X idle cycle.
- * | | |W2X idle cycle = (W2X * EBI_MCLK).
- * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
- * |[22] |RAHDOFF |Access Hold Time Disable Control When Read
- * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
- * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
- * |[23] |WAHDOFF |Access Hold Time Disable Control When Write
- * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
- * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
- * |[27:24] |R2R |Idle Cycle Between Read-To-Read
- * | | |This field defines the number of R2R idle cycle.
- * | | |R2R idle cycle = (R2R * EBI_MCLK).
- * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
- */
-
- __IO uint32_t CTL0; /* Offset: 0x00 External Bus Interface Bank0 Control Register */
- __IO uint32_t TCTL0; /* Offset: 0x04 External Bus Interface Bank0 Timing Control Register */
- __I uint32_t RESERVE0[2];
- __IO uint32_t CTL1; /* Offset: 0x10 External Bus Interface Bank1 Control Register */
- __IO uint32_t TCTL1; /* Offset: 0x14 External Bus Interface Bank1 Timing Control Register */
-
-} EBI_T;
-
-
-
-/**
- @addtogroup EBI_CONST EBI Bit Field Definition
- Constant Definitions for EBI Controller
-@{ */
-
-#define EBI_CTL0_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
-#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
-
-#define EBI_CTL0_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
-#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
-
-#define EBI_CTL0_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
-#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
-
-#define EBI_CTL0_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
-#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
-
-#define EBI_CTL0_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
-#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
-
-#define EBI_CTL0_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */
-#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */
-
-#define EBI_TCTL0_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
-#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
-
-#define EBI_TCTL0_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
-#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
-
-#define EBI_TCTL0_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
-#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
-
-#define EBI_TCTL0_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
-#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
-
-#define EBI_TCTL0_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
-#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
-
-#define EBI_TCTL0_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
-#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
-
-#define EBI_CTL1_EN_Pos (0) /*!< EBI_T::CTL1: EN Position */
-#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) /*!< EBI_T::CTL1: EN Mask */
-
-#define EBI_CTL1_DW16_Pos (1) /*!< EBI_T::CTL1: DW16 Position */
-#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) /*!< EBI_T::CTL1: DW16 Mask */
-
-#define EBI_CTL1_CSPOLINV_Pos (2) /*!< EBI_T::CTL1: CSPOLINV Position */
-#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) /*!< EBI_T::CTL1: CSPOLINV Mask */
-
-#define EBI_CTL1_MCLKDIV_Pos (8) /*!< EBI_T::CTL1: MCLKDIV Position */
-#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) /*!< EBI_T::CTL1: MCLKDIV Mask */
-
-#define EBI_CTL1_TALE_Pos (16) /*!< EBI_T::CTL1: TALE Position */
-#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) /*!< EBI_T::CTL1: TALE Mask */
-
-#define EBI_CTL1_WBUFEN_Pos (24) /*!< EBI_T::CTL1: WBUFEN Position */
-#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) /*!< EBI_T::CTL1: WBUFEN Mask */
-
-#define EBI_TCTL1_TACC_Pos (3) /*!< EBI_T::TCTL1: TACC Position */
-#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) /*!< EBI_T::TCTL1: TACC Mask */
-
-#define EBI_TCTL1_TAHD_Pos (8) /*!< EBI_T::TCTL1: TAHD Position */
-#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) /*!< EBI_T::TCTL1: TAHD Mask */
-
-#define EBI_TCTL1_W2X_Pos (12) /*!< EBI_T::TCTL1: W2X Position */
-#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) /*!< EBI_T::TCTL1: W2X Mask */
-
-#define EBI_TCTL1_RAHDOFF_Pos (22) /*!< EBI_T::TCTL1: RAHDOFF Position */
-#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) /*!< EBI_T::TCTL1: RAHDOFF Mask */
-
-#define EBI_TCTL1_WAHDOFF_Pos (23) /*!< EBI_T::TCTL1: WAHDOFF Position */
-#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) /*!< EBI_T::TCTL1: WAHDOFF Mask */
-
-#define EBI_TCTL1_R2R_Pos (24) /*!< EBI_T::TCTL1: R2R Position */
-#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /*!< EBI_T::TCTL1: R2R Mask */
-
-/**@}*/ /* EBI_CONST */
-/**@}*/ /* end of EBI register group */
-
-
-/*---------------------- Flash Memory Controller -------------------------*/
-/**
- @addtogroup FMC Flash Memory Controller(FMC)
- Memory Mapped Structure for FMC Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var FMC_T::ISPCTL
- * Offset: 0x00 ISP Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ISPEN |ISP Enable Bit (Write Protect)
- * | | |ISP function enable bit. Set this bit to enable ISP function.
- * | | |0 = ISP function Disabled.
- * | | |1 = ISP function Enabled.
- * |[1] |BS |Boot Select (Write Protect)
- * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively.
- * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
- * | | |This bit is initiated with the inverted value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
- * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
- * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
- * |[3] |APUEN |APROM Update Enable Bit (Write Protect)
- * | | |0 = APROM cannot be updated when the chip runs in APROM.
- * | | |1 = APROM can be updated when the chip runs in APROM.
- * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect)
- * | | |0 = CONFIG cannot be updated.
- * | | |1 = CONFIG can be updated.
- * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect)
- * | | |LDROM update enable bit.
- * | | |0 = LDROM cannot be updated.
- * | | |1 = LDROM can be updated.
- * |[6] |ISPFF |ISP Fail Flag (Write Protect)
- * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
- * | | |This bit needs to be cleared by writing 1 to it.
- * | | |(1) APROM writes to itself if APUEN is set to 0.
- * | | |(2) LDROM writes to itself if LDUEN is set to 0.
- * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
- * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
- * | | |(5) SPROM is programmed at SPROM secured mode.
- * | | |(6) Page Erase command at LOCK mode with ICE connection
- * | | |(7) Erase or Program command at brown-out detected
- * | | |(8) Destination address is illegal, such as over an available range.
- * | | |(9) Invalid ISP commands
- * |[16] |BL |Boot Loader Booting (Write Protect)
- * | | |This bit is initiated with the inverted value of MBS (CONFIG0[5]).
- * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded.
- * | | |This bit is used to check chip boot from Boot Loader or not.
- * | | |User should keep original value of this bit when updating FMC_ISPCTL register.
- * | | |0 = Booting from APROM or LDROM.
- * | | |1 = Booting from Boot Loader.
- * @var FMC_T::ISPADDR
- * Offset: 0x04 ISP Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |ISPADDR |ISP Address
- * | | |The NuMicro M451 series is equipped with embedded flash.
- * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
- * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
- * | | |For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 Kbytes alignment is necessary for checksum calculation.
- * @var FMC_T::ISPDAT
- * Offset: 0x08 ISP Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |ISPDAT |ISP Data
- * | | |Write data to this register before ISP program operation.
- * | | |Read data from this register after ISP read operation.
- * | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 Kbytes alignment.
- * | | |For ISP Read Checksum command, ISPDAT is the checksum result.
- * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect, or (3) all of data are 0.
- * @var FMC_T::ISPCMD
- * Offset: 0x0C ISP CMD Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[6:0] |CMD |ISP CMD
- * | | |ISP command table is shown below:
- * | | |0x00= FLASH Read.
- * | | |0x04= Read Unique ID.
- * | | |0x0B= Read Company ID.
- * | | |0x0C= Read Device ID.
- * | | |0x0D= Read Checksum.
- * | | |0x21= FLASH 32-bit Program.
- * | | |0x22= FLASH Page Erase.
- * | | |0x27= FLASH Multi-Word Program.
- * | | |0x2D= Run Checksum Calculation.
- * | | |0x2E= Vector Remap.
- * | | |0x61= FLASH 64-bit Program.
- * | | |The other commands are invalid.
- * @var FMC_T::ISPTRG
- * Offset: 0x10 ISP Trigger Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ISPGO |ISP Start Trigger (Write Protect)
- * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
- * | | |0 = ISP operation is finished.
- * | | |1 = ISP is progressed.
- * @var FMC_T::DFBA
- * Offset: 0x14 Data Flash Base Address
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |DFBA |Data Flash Base Address
- * | | |This register indicates Data Flash start address. It is a read only register.
- * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
- * | | |This register is valid when DFEN (CONFIG0[0]) =0 .
- * @var FMC_T::FTCTL
- * Offset: 0x18 Flash Access Time Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[6:4] |FOM |Frequency Optimization Mode (Write Protect)
- * | | |The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.
- * | | |001 = Frequency <= 12MHz.
- * | | |010 = Frequency <= 36MHz.
- * | | |100 = Frequency <= 60MHz.
- * | | |Others = Frequency <= 72MHz.
- * @var FMC_T::ISPSTS
- * Offset: 0x40 ISP Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ISPBUSY |ISP Busy Flag (Read Only)
- * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
- * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
- * | | |0 = ISP operation is finished.
- * | | |1 = ISP is progressed.
- * |[2:1] |CBS |Boot Selection Of CONFIG (Read Only)
- * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
- * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
- * | | |00 = LDROM with IAP mode.
- * | | |01 = LDROM without IAP mode.
- * | | |10 = APROM with IAP mode.
- * | | |11 = APROM without IAP mode.
- * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only)
- * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
- * | | |0 = Booting from Boot Loader.
- * | | |1 = Booting
- * | | |from LDROM/APROM.(see CBS bit setting)
- * |[5] |PGFF |Flash Program With Fast Verification Flag (Read Only)
- * | | |This bit is set if data is mismatched at ISP programming verification.
- * | | |This bit is clear by performing ISP flash erase or ISP read CID operation.
- * | | |0 = Flash Program is success.
- * | | |1 = Flash Program is fail. Program data is different with data in the flash memory
- * |[6] |ISPFF |ISP Fail Flag (Write Protect)
- * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
- * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
- * | | |(1) APROM writes to itself if APUEN is set to 0.
- * | | |(2) LDROM writes to itself if LDUEN is set to 0.
- * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
- * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
- * | | |(5) SPROM is programmed at SPROM secured mode.
- * | | |(6) Page Erase command at LOCK mode with ICE connection
- * | | |(7) Erase or Program command at brown-out detected
- * | | |(8) Destination address is illegal, such as over an available range.
- * | | |(9) Invalid ISP commands
- * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only)
- * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
- * @var FMC_T::MPDAT0
- * Offset: 0x80 ISP Data0 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |ISPDAT0 |ISP Data 0
- * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
- * @var FMC_T::MPDAT1
- * Offset: 0x84 ISP Data1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |ISPDAT1 |ISP Data 1
- * | | |This register is the second 32-bit data for 64-bit/multi-word programming.
- * @var FMC_T::MPDAT2
- * Offset: 0x88 ISP Data2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |ISPDAT2 |ISP Data 2
- * | | |This register is the third 32-bit data for multi-word programming.
- * @var FMC_T::MPDAT3
- * Offset: 0x8C ISP Data3 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |ISPDAT3 |ISP Data 3
- * | | |This register is the fourth 32-bit data for multi-word programming.
- * @var FMC_T::MPSTS
- * Offset: 0xC0 ISP Multi-Program Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |MPBUSY |ISP Multi-Word Program Busy Flag (Read Only)
- * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
- * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
- * | | |0 = ISP Multi-Word program operation is finished.
- * | | |1 = ISP Multi-Word program operation
- * | | |is progressed.
- * |[1] |PPGO |ISP Multi-Program Status (Read Only)
- * | | |0 = ISP multi-word program operation is not active.
- * | | |1 = ISP multi-word program operation is in progress.
- * |[2] |ISPFF |ISP Fail Flag (Read Only)
- * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
- * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
- * | | |(1) APROM writes to itself if APUEN is set to 0.
- * | | |(2) LDROM writes to itself if LDUEN is set to 0.
- * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
- * | | |(4) SPROM is erased/programmed if SPUEN is set to 0
- * | | |(5) SPROM is programmed at SPROM secured mode.
- * | | |(6) Page Erase command at LOCK mode with ICE connection
- * | | |(7) Erase or Program command at brown-out detected
- * | | |(8) Destination address is illegal, such as over an available range.
- * | | |(9) Invalid ISP commands
- * |[4] |D0 |ISP DATA 0 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
- * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
- * |[5] |D1 |ISP DATA 1 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
- * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
- * |[6] |D2 |ISP DATA 2 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
- * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
- * |[7] |D3 |ISP DATA 3 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
- * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
- * @var FMC_T::MPADDR
- * Offset: 0xC4 ISP Multi-Program Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |MPADDR |ISP Multi-Word Program Address
- * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
- * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete.
- */
-
- __IO uint32_t ISPCTL; /* Offset: 0x00 ISP Control Register */
- __IO uint32_t ISPADDR; /* Offset: 0x04 ISP Address Register */
- __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
- __IO uint32_t ISPCMD; /* Offset: 0x0C ISP CMD Register */
- __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Control Register */
- __I uint32_t DFBA; /* Offset: 0x14 Data Flash Base Address */
- __IO uint32_t FTCTL; /* Offset: 0x18 Flash Access Time Control Register */
- __I uint32_t RESERVE0[9];
- __I uint32_t ISPSTS; /* Offset: 0x40 ISP Status Register */
- __I uint32_t RESERVE1[15];
- __IO uint32_t MPDAT0; /* Offset: 0x80 ISP Data0 Register */
- __IO uint32_t MPDAT1; /* Offset: 0x84 ISP Data1 Register */
- __IO uint32_t MPDAT2; /* Offset: 0x88 ISP Data2 Register */
- __IO uint32_t MPDAT3; /* Offset: 0x8C ISP Data3 Register */
- __I uint32_t RESERVE2[12];
- __I uint32_t MPSTS; /* Offset: 0xC0 ISP Multi-Program Status Register */
- __I uint32_t MPADDR; /* Offset: 0xC4 ISP Multi-Program Address Register */
-
-} FMC_T;
-
-
-
-
-/**
- @addtogroup FMC_CONST FMC Bit Field Definition
- Constant Definitions for FMC Controller
-@{ */
-
-#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */
-#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */
-
-#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */
-#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */
-
-#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */
-#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */
-
-#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */
-#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */
-
-#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */
-#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */
-
-#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */
-#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */
-
-#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */
-#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */
-
-#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */
-#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */
-
-#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */
-#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
-
-#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */
-#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */
-
-#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */
-#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
-
-#define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */
-#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */
-
-#define FMC_FTCTL_FOM_Pos (4) /*!< FMC_T::FTCTL: FOM Position */
-#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC_T::FTCTL: FOM Mask */
-
-#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */
-#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */
-
-#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */
-#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */
-
-#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */
-#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */
-
-#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */
-#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */
-
-#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */
-#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */
-
-#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */
-#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */
-
-#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */
-#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */
-
-#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */
-#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */
-
-#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */
-#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */
-
-#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */
-#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */
-
-#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */
-#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */
-
-#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */
-#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */
-
-#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */
-#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */
-
-#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */
-#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */
-
-#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */
-#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */
-
-#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */
-#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */
-
-#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */
-#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */
-
-#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */
-#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */
-
-/**@}*/ /* FMC_CONST */
-/**@}*/ /* end of FMC register group */
-
-
-/*---------------------- General Purpose Input/Output Controller -------------------------*/
-/**
- @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
- Memory Mapped Structure for GPIO Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-/**
- * @var GPIO_T::MODE
- * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control
- * | | |Determine each I/O mode of Px.n pins.
- * | | |00 = Px.n is in Input mode.
- * | | |01 = Px.n is in Push-pull Output mode.
- * | | |10 = Px.n is in Open-drain Output mode.
- * | | |11 = Px.n is in Quasi-bidirectional mode.
- * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
- * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
- * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
- * | | |input mode after chip powered on.
- * | | |Note2:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::DINOFF
- * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Control
- * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
- * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
- * | | |0 = Px.n digital input path Enabled.
- * | | |1 = Px.n digital input path Disabled (digital input tied to low).
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::DOUT
- * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |DOUTn |Port A-F Pin[n] Output Value
- * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
- * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
- * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::DATMSK
- * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |DMASKn |Port A-F Pin[n] Data Output Write Mask
- * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
- * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
- * | | |If the write signal is masked, writing data to the protect bit is ignored.
- * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
- * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
- * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
- * | | |Note2:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::PIN
- * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |PINn |Port A-F Pin[n] Pin Value
- * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
- * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::DBEN
- * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |DBENn |Port A-F Pin[n] Input Signal De-Bounce Enable Bit
- * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
- * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
- * | | |0 = Px.n de-bounce function Disabled.
- * | | |1 = Px.n de-bounce function Enabled.
- * | | |The de-bounce function is valid only for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::INTTYPE
- * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |TYPEn |Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control
- * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
- * | | |0 = Edge trigger interrupt.
- * | | |1 = Level trigger interrupt.
- * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
- * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
- * | | |The de-bounce function is valid only for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::INTEN
- * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
- * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
- * | | |Set bit to 1 also enable the pin wake-up function.
- * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
- * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
- * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
- * | | |0 = Px.n level low or high to low interrupt Disabled.
- * | | |1 = Px.n level low or high to low interrupt Enabled.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::INTSRC
- * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag
- * | | |Write Operation :
- * | | |0 = No action.
- * | | |1 = Clear the corresponding pending interrupt.
- * | | |Read Operation :
- * | | |0 = No interrupt at Px.n.
- * | | |1 = Px.n generates an interrupt.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::SMTEN
- * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |SMTENn |Port A-F Pin[n] Input Schmitt Trigger Enable Bit
- * | | |0 = Px.n input Schmitt trigger function Disabled.
- * | | |1 = Px.n input Schmitt trigger function Enabled.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::SLEWCTL
- * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |HSRENn |Port A-F Pin[n] High Slew Rate Control
- * | | |0 = Px.n output with basic slew rate.
- * | | |1 = Px.n output with higher slew rate.
- * | | |Note:
- * | | |n=0~15 for port A/B/C/D.
- * | | |n=0~14 for port E.
- * | | |n=0~7 for port F.
- * @var GPIO_T::DRVCTL
- * Offset: 0x2C Port E High Drive Strength Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[n] |HDRVENn |Port E Pin[n] Driving Strength Control
- * | | |0 = Px.n output with basic driving strength.
- * | | |1 = Px.n output with high driving strength.
- * | | |Note:
- * | | |n=8,9..13 for port E.
- */
-
- __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control */
- __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control */
- __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value */
- __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask */
- __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value */
- __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register */
- __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control */
- __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register */
- __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag */
- __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register */
- __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register */
- __IO uint32_t DRVCTL; /* Offset: 0x12C Port E High Drive Strength Control Register */
-
-} GPIO_T;
-
-
-
-
-typedef struct
-{
-
-
-
-/**
- * @var GPIO_DBCTL_T::DBCTL
- * Offset: 0x440 Interrupt De-bounce Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
- * | | |0000 = Sample interrupt input once per 1 clocks.
- * | | |0001 = Sample interrupt input once per 2 clocks.
- * | | |0010 = Sample interrupt input once per 4 clocks.
- * | | |0011 = Sample interrupt input once per 8 clocks.
- * | | |0100 = Sample interrupt input once per 16 clocks.
- * | | |0101 = Sample interrupt input once per 32 clocks.
- * | | |0110 = Sample interrupt input once per 64 clocks.
- * | | |0111 = Sample interrupt input once per 128 clocks.
- * | | |1000 = Sample interrupt input once per 256 clocks.
- * | | |1001 = Sample interrupt input once per 2*256 clocks.
- * | | |1010 = Sample interrupt input once per 4*256 clocks.
- * | | |1011 = Sample interrupt input once per 8*256 clocks.
- * | | |1100 = Sample interrupt input once per 16*256 clocks.
- * | | |1101 = Sample interrupt input once per 32*256 clocks.
- * | | |1110 = Sample interrupt input once per 64*256 clocks.
- * | | |1111 = Sample interrupt input once per 128*256 clocks.
- * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
- * | | |0 = De-bounce counter clock source is the HCLK.
- * | | |1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator.
- * |[5] |ICLKON |Interrupt Clock On Mode
- * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
- * | | |1 = All I/O pins edge detection circuit is always active after reset.
- * | | |Note: It is recommended to disable this bit to save system power if no special application concern.
- */
-
- __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
-
-} GPIO_DBCTL_T;
-
-
-
-
-/**
- @addtogroup GPIO_CONST GPIO Bit Field Definition
- Constant Definitions for GPIO Controller
-@{ */
-
-#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */
-#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */
-
-#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */
-#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */
-
-#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */
-#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */
-
-#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */
-#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */
-
-#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */
-#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */
-
-#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */
-#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */
-
-#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */
-#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */
-
-#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */
-#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */
-
-#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */
-#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */
-
-#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */
-#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */
-
-#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */
-#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */
-
-#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */
-#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */
-
-#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */
-#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */
-
-#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */
-#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */
-
-#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */
-#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */
-
-#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */
-#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */
-
-#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */
-#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */
-
-#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */
-#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */
-
-#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */
-#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */
-
-#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */
-#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */
-
-#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */
-#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */
-
-#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */
-#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */
-
-#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */
-#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */
-
-#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */
-#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */
-
-#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */
-#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */
-
-#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */
-#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */
-
-#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */
-#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */
-
-#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */
-#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */
-
-#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */
-#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */
-
-#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */
-#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */
-
-#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */
-#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */
-
-#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */
-#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */
-
-#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */
-#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */
-
-#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */
-#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */
-
-#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */
-#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */
-
-#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */
-#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */
-
-#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */
-#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */
-
-#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */
-#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */
-
-#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */
-#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */
-
-#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */
-#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */
-
-#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */
-#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */
-
-#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */
-#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */
-
-#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */
-#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */
-
-#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */
-#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */
-
-#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */
-#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */
-
-#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */
-#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */
-
-#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */
-#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */
-
-#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */
-#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */
-
-#define GPIO_DATMSK_DMASK0_Pos (0) /*!< GPIO_T::DATMSK: DMASK0 Position */
-#define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos) /*!< GPIO_T::DATMSK: DMASK0 Mask */
-
-#define GPIO_DATMSK_DMASK1_Pos (1) /*!< GPIO_T::DATMSK: DMASK1 Position */
-#define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos) /*!< GPIO_T::DATMSK: DMASK1 Mask */
-
-#define GPIO_DATMSK_DMASK2_Pos (2) /*!< GPIO_T::DATMSK: DMASK2 Position */
-#define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos) /*!< GPIO_T::DATMSK: DMASK2 Mask */
-
-#define GPIO_DATMSK_DMASK3_Pos (3) /*!< GPIO_T::DATMSK: DMASK3 Position */
-#define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos) /*!< GPIO_T::DATMSK: DMASK3 Mask */
-
-#define GPIO_DATMSK_DMASK4_Pos (4) /*!< GPIO_T::DATMSK: DMASK4 Position */
-#define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos) /*!< GPIO_T::DATMSK: DMASK4 Mask */
-
-#define GPIO_DATMSK_DMASK5_Pos (5) /*!< GPIO_T::DATMSK: DMASK5 Position */
-#define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos) /*!< GPIO_T::DATMSK: DMASK5 Mask */
-
-#define GPIO_DATMSK_DMASK6_Pos (6) /*!< GPIO_T::DATMSK: DMASK6 Position */
-#define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos) /*!< GPIO_T::DATMSK: DMASK6 Mask */
-
-#define GPIO_DATMSK_DMASK7_Pos (7) /*!< GPIO_T::DATMSK: DMASK7 Position */
-#define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos) /*!< GPIO_T::DATMSK: DMASK7 Mask */
-
-#define GPIO_DATMSK_DMASK8_Pos (8) /*!< GPIO_T::DATMSK: DMASK8 Position */
-#define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos) /*!< GPIO_T::DATMSK: DMASK8 Mask */
-
-#define GPIO_DATMSK_DMASK9_Pos (9) /*!< GPIO_T::DATMSK: DMASK9 Position */
-#define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos) /*!< GPIO_T::DATMSK: DMASK9 Mask */
-
-#define GPIO_DATMSK_DMASK10_Pos (10) /*!< GPIO_T::DATMSK: DMASK10 Position */
-#define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos) /*!< GPIO_T::DATMSK: DMASK10 Mask */
-
-#define GPIO_DATMSK_DMASK11_Pos (11) /*!< GPIO_T::DATMSK: DMASK11 Position */
-#define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos) /*!< GPIO_T::DATMSK: DMASK11 Mask */
-
-#define GPIO_DATMSK_DMASK12_Pos (12) /*!< GPIO_T::DATMSK: DMASK12 Position */
-#define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos) /*!< GPIO_T::DATMSK: DMASK12 Mask */
-
-#define GPIO_DATMSK_DMASK13_Pos (13) /*!< GPIO_T::DATMSK: DMASK13 Position */
-#define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos) /*!< GPIO_T::DATMSK: DMASK13 Mask */
-
-#define GPIO_DATMSK_DMASK14_Pos (14) /*!< GPIO_T::DATMSK: DMASK14 Position */
-#define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos) /*!< GPIO_T::DATMSK: DMASK14 Mask */
-
-#define GPIO_DATMSK_DMASK15_Pos (15) /*!< GPIO_T::DATMSK: DMASK15 Position */
-#define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos) /*!< GPIO_T::DATMSK: DMASK15 Mask */
-
-#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */
-#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */
-
-#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */
-#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */
-
-#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */
-#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */
-
-#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */
-#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */
-
-#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */
-#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */
-
-#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */
-#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */
-
-#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */
-#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */
-
-#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */
-#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */
-
-#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */
-#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */
-
-#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */
-#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */
-
-#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */
-#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */
-
-#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */
-#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */
-
-#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */
-#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */
-
-#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */
-#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */
-
-#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */
-#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */
-
-#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */
-#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */
-
-#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */
-#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */
-
-#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */
-#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */
-
-#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */
-#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */
-
-#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */
-#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */
-
-#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */
-#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */
-
-#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */
-#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */
-
-#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */
-#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */
-
-#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */
-#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */
-
-#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */
-#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */
-
-#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */
-#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */
-
-#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */
-#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */
-
-#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */
-#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */
-
-#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */
-#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */
-
-#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */
-#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */
-
-#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */
-#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */
-
-#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */
-#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */
-
-#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */
-#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */
-
-#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */
-#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */
-
-#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */
-#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */
-
-#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */
-#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */
-
-#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */
-#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */
-
-#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */
-#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */
-
-#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */
-#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */
-
-#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */
-#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */
-
-#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */
-#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */
-
-#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */
-#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */
-
-#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */
-#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */
-
-#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */
-#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */
-
-#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */
-#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */
-
-#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */
-#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */
-
-#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */
-#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */
-
-#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */
-#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */
-
-#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */
-#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */
-
-#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */
-#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */
-
-#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */
-#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */
-
-#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */
-#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */
-
-#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */
-#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */
-
-#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */
-#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */
-
-#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */
-#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */
-
-#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */
-#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */
-
-#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */
-#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */
-
-#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */
-#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */
-
-#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */
-#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */
-
-#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */
-#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */
-
-#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */
-#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */
-
-#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */
-#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */
-
-#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */
-#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */
-
-#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */
-#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */
-
-#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */
-#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */
-
-#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */
-#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */
-
-#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */
-#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */
-
-#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */
-#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */
-
-#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */
-#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */
-
-#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */
-#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */
-
-#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */
-#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */
-
-#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */
-#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */
-
-#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */
-#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */
-
-#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */
-#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */
-
-#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */
-#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */
-
-#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */
-#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */
-
-#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */
-#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */
-
-#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */
-#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */
-
-#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */
-#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */
-
-#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */
-#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */
-
-#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */
-#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */
-
-#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */
-#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */
-
-#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */
-#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */
-
-#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */
-#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */
-
-#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */
-#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */
-
-#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */
-#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */
-
-#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */
-#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */
-
-#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */
-#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */
-
-#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */
-#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */
-
-#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */
-#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */
-
-#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */
-#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */
-
-#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */
-#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */
-
-#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */
-#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */
-
-#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */
-#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */
-
-#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */
-#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */
-
-#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */
-#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */
-
-#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */
-#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */
-
-#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */
-#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */
-
-#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */
-#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */
-
-#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */
-#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */
-
-#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */
-#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */
-
-#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */
-#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */
-
-#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */
-#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */
-
-#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */
-#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */
-
-#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */
-#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */
-
-#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */
-#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */
-
-#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */
-#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */
-
-#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */
-#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */
-
-#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */
-#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */
-
-#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */
-#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */
-
-#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */
-#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */
-
-#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */
-#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */
-
-#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */
-#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */
-
-#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */
-#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */
-
-#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */
-#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */
-
-#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */
-#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */
-
-#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */
-#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */
-
-#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */
-#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */
-
-#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */
-#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */
-
-#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */
-#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */
-
-#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */
-#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */
-
-#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */
-#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */
-
-#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */
-#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */
-
-#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */
-#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */
-
-#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */
-#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */
-
-#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */
-#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */
-
-#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */
-#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */
-
-#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */
-#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */
-
-#define GPIO_DRVCTL_HDRVEN8_Pos (8) /*!< GPIO_T::DRVCTL: HDRVEN8 Position */
-#define GPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos) /*!< GPIO_T::DRVCTL: HDRVEN8 Mask */
-
-#define GPIO_DRVCTL_HDRVEN9_Pos (9) /*!< GPIO_T::DRVCTL: HDRVEN9 Position */
-#define GPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos) /*!< GPIO_T::DRVCTL: HDRVEN9 Mask */
-
-#define GPIO_DRVCTL_HDRVEN10_Pos (10) /*!< GPIO_T::DRVCTL: HDRVEN10 Position */
-#define GPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos) /*!< GPIO_T::DRVCTL: HDRVEN10 Mask */
-
-#define GPIO_DRVCTL_HDRVEN11_Pos (11) /*!< GPIO_T::DRVCTL: HDRVEN11 Position */
-#define GPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos) /*!< GPIO_T::DRVCTL: HDRVEN11 Mask */
-
-#define GPIO_DRVCTL_HDRVEN12_Pos (12) /*!< GPIO_T::DRVCTL: HDRVEN12 Position */
-#define GPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos) /*!< GPIO_T::DRVCTL: HDRVEN12 Mask */
-
-#define GPIO_DRVCTL_HDRVEN13_Pos (13) /*!< GPIO_T::DRVCTL: HDRVEN13 Position */
-#define GPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos) /*!< GPIO_T::DRVCTL: HDRVEN13 Mask */
-
-#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */
-#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */
-
-#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */
-#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */
-
-#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */
-#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */
-
-
-/**@}*/ /* GPIO_CONST */
-/**@}*/ /* end of GPIO register group */
-
-
-/*---------------------- Inter-IC Bus Controller -------------------------*/
-/**
- @addtogroup I2C Inter-IC Bus Controller(I2C)
- Memory Mapped Structure for I2C Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var I2C_T::CTL
- * Offset: 0x00 I2C Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2] |AA |Assert Acknowledge Control
- * | | |When AA =1 prior to address or data is received,
- * | | |an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when
- * | | |1. A slave is acknowledging the address sent from master.
- * | | |2. The receiver devices are acknowledging the data sent by transmitter.
- * | | |When AA=0 prior to address or data received,
- * | | |a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
- * |[3] |SI |I2C Interrupt Flag
- * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware.
- * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.
- * | | |SI must be cleared by software.
- * | | |Clear SI by writing 1 to this bit.
- * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
- * |[4] |STO |I2C STOP Control
- * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
- * | | |This bit will be cleared by hardware automatically.
- * |[5] |STA |I2C START Control
- * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
- * |[6] |I2CEN |I2C Controller Enable Bit
- * | | |Set to enable I2C serial function controller.
- * | | |When I2CEN=1 the I2C serial function enable.
- * | | |The multi-function pin function must set to SDA, and SCL of I2C function first.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |INTEN |Enable Interrupt
- * | | |0 = I2C interrupt Disabled.
- * | | |1 = I2C interrupt Enabled.
- * @var I2C_T::ADDR0
- * Offset: 0x04 I2C Slave Address Register0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[7:1] |ADDR |I2C Address
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- * @var I2C_T::DAT
- * Offset: 0x08 I2C Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |DAT |I2C Data
- * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
- * @var I2C_T::STATUS
- * Offset: 0x0C I2C Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |STATUS |I2C Status
- * | | |The three least significant bits are always 0.
- * | | |The five most significant bits contain the status code.
- * | | |There are 28 possible status codes.
- * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested.
- * | | |Others I2C_STATUS values correspond to defined I2C states.
- * | | |When each of these states is entered, a status interrupt is requested (SI = 1).
- * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
- * | | |In addition, states 00H stands for a Bus Error.
- * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
- * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
- * | | |Note:
- * | | |1.
- * | | |If the BUSEN and ACKMEN are enabled in slave received mode, there is SI interrupt in the 8th clock.
- * | | |The user can read the I2C_STATUS = 0xf0 for the function condition has done.
- * | | |2.
- * | | |If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed.
- * @var I2C_T::CLKDIV
- * Offset: 0x10 I2C Clock Divided Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |DIVIDER |I2C Clock Divided
- * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
- * | | |Note: The minimum value of I2C_CLKDIV is 4.
- * @var I2C_T::TOCTL
- * Offset: 0x14 I2C Time-out Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TOIF |Time-Out Flag
- * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
- * | | |Note: Software can write 1 to clear this bit.
- * |[1] |TOCDIV4 |Time-Out Counter Input Clock Divided By 4
- * | | |When Enabled, The time-out period is extend 4 times.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |TOCEN |Time-Out Counter Enable Bit
- * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear.
- * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * @var I2C_T::ADDR1
- * Offset: 0x18 I2C Slave Address Register1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[7:1] |ADDR |I2C Address
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- * @var I2C_T::ADDR2
- * Offset: 0x1C I2C Slave Address Register2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[7:1] |ADDR |I2C Address
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- * @var I2C_T::ADDR3
- * Offset: 0x20 I2C Slave Address Register3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[7:1] |ADDR |I2C Address
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- * @var I2C_T::ADDRMSK0
- * Offset: 0x24 I2C Slave Address Mask Register0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:1] |ADDRMSK |I2C Address Mask
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- * @var I2C_T::ADDRMSK1
- * Offset: 0x28 I2C Slave Address Mask Register1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:1] |ADDRMSK |I2C Address Mask
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- * @var I2C_T::ADDRMSK2
- * Offset: 0x2C I2C Slave Address Mask Register2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:1] |ADDRMSK |I2C Address Mask
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- * @var I2C_T::ADDRMSK3
- * Offset: 0x30 I2C Slave Address Mask Register3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:1] |ADDRMSK |I2C Address Mask
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- * @var I2C_T::WKCTL
- * Offset: 0x3C I2C Wake-up Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WKEN |I2C Wake-Up Enable Bit
- * | | |0 = I2C wake-up function Disabled.
- * | | |1= I2C wake-up function Enabled.
- * @var I2C_T::WKSTS
- * Offset: 0x40 I2C Wake-up Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WKIF |I2C Wake-Up Flag
- * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
- * | | |Software can write 1 to clear this bit.
- * @var I2C_T::BUSCTL
- * Offset: 0x44 I2C Bus Management Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ACKMEN |Acknowledge Control By Manual
- * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
- * | | |0 = Slave byte control Disabled.
- * | | |1 = Slave byte control Enabled.
- * | | |The 9th bit can response the ACK or NACK according the received data by user.
- * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
- * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
- * |[1] |PECEN |Packet Error Checking Calculation Enable Bit
- * | | |0 = Packet Error Checking Calculation Disabled.
- * | | |1 = Packet Error Checking Calculation Enabled.
- * |[2] |BMDEN |Bus Management Device Default Address Enable Bit
- * | | |0 = Device default address Disable.
- * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed.
- * | | |1 = Device default address Enabled.
- * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
- * |[3] |BMHEN |Bus Management Host Enable Bit
- * | | |0 = Host function Disabled.
- * | | |1 = Host function Enabled and the SUSCON will be used as CONTROL function.
- * |[4] |ALERTEN |Bus Management Alert Enable Bit
- * | | |Device Mode (BMHEN =0).
- * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
- * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
- * | | |Host Mode (BMHEN =1).
- * | | |0 = BM_ALERT pin not supported.
- * | | |1 = BM_ALERT pin supported.
- * |[5] |SCTLOSTS |Suspend/Control Data Output Status
- * | | |0 = The output of SUSCON pin is low.
- * | | |1 = The output of SUSCON pin is high.
- * |[6] |SCTLOEN |Suspend Or Control Pin Output Enable Bit
- * | | |0 = The SUSCON pin in input.
- * | | |1 = The output enable is active on the SUSCON pin.
- * |[7] |BUSEN |BUS Enable Bit
- * | | |0 = The system management function is Disabled.
- * | | |1 = The system management function is Enable.
- * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
- * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception
- * | | |This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received
- * | | |0 = No PEC transfer.
- * | | |1 = PEC transmission/reception is requested.
- * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
- * |[9] |TIDLE |Timer Check In Idle State
- * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
- * | | |This bit is used to define which condition is enabled.
- * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active.
- * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
- * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
- * |[10] |PECCLR |PEC Clear At Repeat Start
- * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected.
- * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
- * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
- * | | |1 = The PEC calculation is cleared by "Repeat Start" function is Enabled.
- * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt
- * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
- * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
- * @var I2C_T::BUSTCTL
- * Offset: 0x48 I2C Bus Management Timer Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSTOEN |Bus Time Out Enable Bit
- * | | |0 = Indicates the bus clock low time-out detection is Disabled.
- * | | |1 = Indicates the bus clock low time-out detection is Enabled
- * | | |bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1),
- * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit
- * | | |0 = Indicates the cumulative clock low time-out detection is Disabled.
- * | | |1 = Indicates the cumulative clock low time-out detection is Enabled.
- * | | |For Master, it calculates the period from START to ACK
- * | | |For Slave, it calculates the period from START to STOP
- * |[2] |BUSTOIEN |Time-Out Interrupt Enable Bit
- * | | |BUSY =1.
- * | | |0 = Indicates the SCLK low time-out interrupt is Disabled.
- * | | |1 = Indicates the SCLK low time-out interrupt is Enabled.
- * | | |BUSY =0.
- * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled.
- * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled.
- * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit
- * | | |0 = Indicates the time extended interrupt is Disabled.
- * | | |1 = Indicates the time extended interrupt is Enabled.
- * |[4] |TORSTEN |Time Out Reset Enable Bit
- * | | |0 = Indicates the I2C state machine reset is Disable.
- * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
- * |[5] |PECIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit
- * | | |0 = Indicates the byte count done interrupt is Disabled.
- * | | |1 = Indicates the byte count done interrupt is Enabled.
- * | | |Note: This bit is used in PECEN =1.
- * @var I2C_T::BUSSTS
- * Offset: 0x4C I2C Bus Management Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSY |Bus Busy
- * | | |Indicates that a communication is in progress on the bus.
- * | | |It is set by hardware when a START condition is detected.
- * | | |It is cleared by hardware when a STOP condition is detected.
- * | | |0 = The bus is IDLE (both SCLK and SDA High).
- * | | |1 = The bus is busy.
- * |[1] |BCDONE |Byte Count Transmission/Receive Done
- * | | |0 = Indicates the transmission/ receive is not finished when the PECEN is set.
- * | | |1 = Indicates the transmission/ receive is finished when the PECEN is set.
- * | | |Note: Software can write 1 to clear this bit.
- * |[2] |PECERR |PEC Error In Reception
- * | | |0 = Indicates the PEC value equal the received PEC data packet.
- * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet.
- * | | |Note: Software can write 1 to clear this bit.
- * |[3] |ALERT |SMBus Alert Status
- * | | |Device Mode (BMHEN =0).
- * | | |0 = Indicates SMALERT pin state is low.
- * | | |1 = Indicates SMALERT pin state is high
- * | | |Host Mode (BMHEN =1).
- * | | |0 = No SMBALERT event.
- * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
- * | | |Note: 1.
- * | | |The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system.
- * | | |2.
- * | | |Software can write 1 to clear this bit.
- * |[4] |SCTLDIN |Bus Suspend Or Control Signal Input Status
- * | | |0 = The input status of SUSCON pin is 0.
- * | | |1 = The input status of SUSCON pin is 1.
- * |[5] |BUSTO |Bus Time-out Status
- * | | |0 = Indicates that there is no any time-out or external clock time-out.
- * | | |1 = Indicates that a time-out or external clock time-out occurred.
- * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
- * | | |Note: Software can write 1 to clear this bit.
- * |[6] |CLKTO |Clock Low Cumulate Time-out Status
- * | | |0 = Indicates that the cumulative clock low is no any time-out.
- * | | |1 = Indicates that the cumulative clock low time-out occurred.
- * | | |Note: Software can write 1 to clear this bit.
- * @var I2C_T::PKTSIZE
- * Offset: 0x50 I2C Packet Error Checking Byte Number Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |PLDSIZE |Transfer Byte Number
- * | | |The transmission or receive byte number in one transaction when the PECEN is set.
- * | | |The maximum transaction or receive byte is 255 Bytes.
- * @var I2C_T::PKTCRC
- * Offset: 0x54 I2C Packet Error Checking Byte Value Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |PECCRC |Packet Error Checking Byte Value
- * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
- * | | |I t is read only.
- * @var I2C_T::BUSTOUT
- * Offset: 0x58 I2C Bus Management Timer Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |BUSTO |Bus Management Time-out Value
- * | | |Indicate the bus time-out value in bus is IDLE or SCLK low.
- * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
- * @var I2C_T::CLKTOUT
- * Offset: 0x5C I2C Bus Management Clock Low Timer Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CLKTO |Bus Clock Low Timer
- * | | |The field is used to configure the cumulative clock extension time-out.
- * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 I2C Control Register */
- __IO uint32_t ADDR0; /* Offset: 0x04 I2C Slave Address Register0 */
- __IO uint32_t DAT; /* Offset: 0x08 I2C Data Register */
- __I uint32_t STATUS; /* Offset: 0x0C I2C Status Register */
- __IO uint32_t CLKDIV; /* Offset: 0x10 I2C Clock Divided Register */
- __IO uint32_t TOCTL; /* Offset: 0x14 I2C Time-out Control Register */
- __IO uint32_t ADDR1; /* Offset: 0x18 I2C Slave Address Register1 */
- __IO uint32_t ADDR2; /* Offset: 0x1C I2C Slave Address Register2 */
- __IO uint32_t ADDR3; /* Offset: 0x20 I2C Slave Address Register3 */
- __IO uint32_t ADDRMSK0; /* Offset: 0x24 I2C Slave Address Mask Register0 */
- __IO uint32_t ADDRMSK1; /* Offset: 0x28 I2C Slave Address Mask Register1 */
- __IO uint32_t ADDRMSK2; /* Offset: 0x2C I2C Slave Address Mask Register2 */
- __IO uint32_t ADDRMSK3; /* Offset: 0x30 I2C Slave Address Mask Register3 */
- __I uint32_t RESERVE0[2];
- __IO uint32_t WKCTL; /* Offset: 0x3C I2C Wake-up Control Register */
- __IO uint32_t WKSTS; /* Offset: 0x40 I2C Wake-up Status Register */
- __IO uint32_t BUSCTL; /* Offset: 0x44 I2C Bus Management Control Register */
- __IO uint32_t BUSTCTL; /* Offset: 0x48 I2C Bus Management Timer Control Register */
- __IO uint32_t BUSSTS; /* Offset: 0x4C I2C Bus Management Status Register */
- __IO uint32_t PKTSIZE; /* Offset: 0x50 I2C Packet Error Checking Byte Number Register */
- __I uint32_t PKTCRC; /* Offset: 0x54 I2C Packet Error Checking Byte Value Register */
- __IO uint32_t BUSTOUT; /* Offset: 0x58 I2C Bus Management Timer Register */
- __IO uint32_t CLKTOUT; /* Offset: 0x5C I2C Bus Management Clock Low Timer Register */
-
-} I2C_T;
-
-
-
-/**
- @addtogroup I2C_CONST I2C Bit Field Definition
- Constant Definitions for I2C Controller
-@{ */
-
-#define I2C_CTL_AA_Pos (2) /*!< I2C_T::CTL: AA Position */
-#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /*!< I2C_T::CTL: AA Mask */
-
-#define I2C_CTL_SI_Pos (3) /*!< I2C_T::CTL: SI Position */
-#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /*!< I2C_T::CTL: SI Mask */
-
-#define I2C_CTL_STO_Pos (4) /*!< I2C_T::CTL: STO Position */
-#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /*!< I2C_T::CTL: STO Mask */
-
-#define I2C_CTL_STA_Pos (5) /*!< I2C_T::CTL: STA Position */
-#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /*!< I2C_T::CTL: STA Mask */
-
-#define I2C_CTL_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */
-#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */
-
-#define I2C_CTL_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */
-#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */
-
-#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */
-#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */
-
-#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */
-#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */
-
-#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */
-#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */
-
-#define I2C_STATUS_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */
-#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C_T::STATUS: STATUS Mask */
-
-#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */
-#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */
-
-#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */
-#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */
-
-#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */
-#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */
-
-#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */
-#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */
-
-#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */
-#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */
-
-#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */
-#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */
-
-#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */
-#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */
-
-#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */
-#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */
-
-#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */
-#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */
-
-#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */
-#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */
-
-#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */
-#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */
-
-#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */
-#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */
-
-#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */
-#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */
-
-#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */
-#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */
-
-#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */
-#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */
-
-#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */
-#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */
-
-#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */
-#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */
-
-#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */
-#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */
-
-#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */
-#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */
-
-#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */
-#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */
-
-#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */
-#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */
-
-#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */
-#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */
-
-#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */
-#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */
-
-#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */
-#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */
-
-#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */
-#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */
-
-#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */
-#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */
-
-#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */
-#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */
-
-#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */
-#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */
-
-#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */
-#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */
-
-#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */
-#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */
-
-#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */
-#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */
-
-#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */
-#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */
-
-#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */
-#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */
-
-#define I2C_BUSTCTL_PECIEN_Pos (5) /*!< I2C_T::BUSTCTL: PECIEN Position */
-#define I2C_BUSTCTL_PECIEN_Msk (0x1ul << I2C_BUSTCTL_PECIEN_Pos) /*!< I2C_T::BUSTCTL: PECIEN Mask */
-
-#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */
-#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */
-
-#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */
-#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */
-
-#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */
-#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */
-
-#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */
-#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */
-
-#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */
-#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */
-
-#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */
-#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */
-
-#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */
-#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */
-
-#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */
-#define I2C_PKTSIZE_PLDSIZE_Msk (0xfful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */
-
-#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */
-#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */
-
-#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */
-#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */
-
-#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */
-#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */
-
-
-/**@}*/ /* I2C_CONST */
-/**@}*/ /* end of I2C register group */
-
-/*---------------------- USB On-The-Go Controller -------------------------*/
-/**
- @addtogroup OTG USB On-The-Go Controller(OTG)
- Memory Mapped Structure for OTG Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var OTG_T::CTL
- * Offset: 0x00 OTG Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |VBUSDROP |Drop VBUS Control
- * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS.
- * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
- * | | |0 = Not drop the VBUS.
- * | | |1 = Drop the VBUS.
- * |[1] |BUSREQ |OTG Bus Request
- * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection.
- * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power.
- * | | |This bit will be cleared when A-device goes to A_wait_vfall state. A_wait_vfall state is defined in OTG specification.
- * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
- * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol.
- * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues ARP in specified interval, defined in OTG specification).
- * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set IDSTS (OTG_STATUS[1]) changed.
- * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
- * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
- * |[2] |HNPREQEN |OTG HNP Request Enable Bit
- * | | |When USB frame as A-device, set this bit when A-device allows to process Host Negotiation Protocol.
- * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state.
- * | | |When USB frame is as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change.
- * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
- * | | |0 = HNP request Disabled.
- * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
- * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
- * |[4] |OTGEN |OTG Function Enable Bit
- * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device.
- * | | |When USB frame not configured as OTG device, this bit is must be low.
- * | | |0 = OTG function Disabled.
- * | | |1 = OTG function Enabled.
- * |[5] |WKEN |OTG ID Pin Wake-Up Enable Bit
- * | | |0 = OTG ID pin status change wake-up function Disabled.
- * | | |1 = OTG ID pin status change wake-up function Enabled.
- * @var OTG_T::PHYCTL
- * Offset: 0x04 OTG PHY Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OTGPHYEN |OTG PHY Enable
- * | | |When USB frame is configured as OTG-device, user needs to set this bit before using OTG function.
- * | | |If device is not configured as OTG-device, this bit is "don't care".
- * | | |0 = OTG PHY Disabled.
- * | | |1 = OTG PHY Enabled.
- * |[1] |IDDETEN |ID Detection Enable Bit
- * | | |0 = Detect ID pin status Disabled.
- * | | |1 = Detect ID pin status Enabled.
- * |[4] |VBENPOL |Off-Chip USB VBUS Power Switch Enable Polarity
- * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need.
- * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
- * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component.
- * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
- * | | |0 = The off-chip USB VBUS power switch enable is active high.
- * | | |1 = The off-chip USB VBUS power switch enable is active low.
- * |[5] |VBSTSPOL |Off-Chip USB VBUS Power Switch Status Polarity
- * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component.
- * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch.
- * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
- * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high.
- * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low.
- * @var OTG_T::INTEN
- * Offset: 0x08 OTG Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ROLECHGIEN|Role (Host Or Peripheral) Changed Interrupt Enable Bit
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
- * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Going to idle state means going to a_idle or b_idle state.
- * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
- * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit
- * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, a interrupt will be asserted.
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit
- * | | |If this bit is set to 1 and the device is changed as a peripheral, a interrupt will be asserted.
- * | | |0 = This device as a peripheral interrupt Disabled.
- * | | |1 = This device as a peripheral interrupt Enabled.
- * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit
- * | | |If this bit is set to 1 and the device is changed as a host, a interrupt will be asserted.
- * | | |0 = This device as a host interrupt Disabled.
- * | | |1 = This device as a host interrupt Enabled.
- * |[8] |BVLDCHGIEN|B-Device Session Valid Status Changed Interrupt Enable Bit
- * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, a interrupt will be asserted.
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[9] |AVLDCHGIEN|A-Device Session Valid Status Changed Interrupt Enable Bit
- * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, a interrupt will be asserted.
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[10] |VBCHGIEN |VBUSVLD Status Changed
- * | | |Interrupt Enable Bit
- * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, a interrupt will be asserted.
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit
- * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, a interrupt will be asserted.
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * @var OTG_T::INTSTS
- * Offset: 0x0C OTG Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
- * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
- * | | |0 = OTG device role not changed.
- * | | |1 = OTG device role changed.
- * | | |Note: Write 1 to clear this flag.
- * |[1] |VBEIF |VBUS Error Interrupt Status
- * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
- * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
- * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
- * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
- * |[2] |SRPFIF |SRP Fail Interrupt Status
- * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification.
- * | | |This flag is set when the OTG B-device does not get VBUS high after this interval.
- * | | |0 = OTG B-device gets VBUS high before this interval.
- * | | |1 = OTG B-device does not get VBUS high before this interval.
- * | | |Note: Write 1 to clear this flag.
- * |[3] |HNPFIF |HNP Fail Interrupt Status
- * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
- * | | |0 = A-device connects to B-device before specified interval expires.
- * | | |1 = A-device does not connect to B-device before specified interval expires.
- * | | |Note: Write 1 to clear this flag.
- * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status
- * | | |Flag is set if the OTG device transfers from non-idle state to idle state.
- * | | |The OTG device will be neither a host nor a peripheral.
- * | | |0 = OTG device does not go back to idle state (a_idle or b_idle).
- * | | |1 = OTG device goes back to idle state (a_idle or b_idle).
- * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification for the details of a_idle state and b_idle state.
- * | | |Note 2: Write 1 to clear this flag.
- * |[5] |IDCHGIF |ID State Change Interrupt Status
- * | | |0 = IDSTS (OTG_STATUS[1]) not toggled.
- * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
- * | | |Note: Write 1 to clear this flag.
- * |[6] |PDEVIF |Act As Peripheral Interrupt Status
- * | | |0 = This device does not act as a peripheral.
- * | | |1 = This device acts as a peripheral.
- * | | |Note: Write 1 to clear this flag.
- * |[7] |HOSTIF |Act As Host Interrupt Status
- * | | |0 = This device does not act as a host.
- * | | |1 = This device acts as a host.
- * | | |Note: Write 1 to clear this flag.
- * |[8] |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
- * | | |0 = BVLD (OTG_STATUS[3]) is not toggled.
- * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
- * | | |Note: Write 1 to clear this status.
- * |[9] |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
- * | | |0 = AVLD (OTG_STATUS[4]) not toggled.
- * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
- * | | |Note: Write 1 to clear this status.
- * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status
- * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
- * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
- * | | |Note: Write 1 to clear this status.
- * |[11] |SECHGIF |SESSEND State Change Interrupt Status
- * | | |0 = SESSEND (OTG_STATUS[2]) not toggled.
- * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
- * | | |Note: Write 1 to clear this flag.
- * |[13] |SRPDETIF |SRP Detected Interrupt Status
- * | | |0 = SRP not detected.
- * | | |1 = SRP detected.
- * | | |Note: Write 1 to clear this status.
- * @var OTG_T::STATUS
- * Offset: 0x10 OTG Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OVERCUR |Over Current Condition
- * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
- * | | |0 = OTG A-device drives VBUS successfully.
- * | | |1 = OTG A-device cannot drives VBUS high in this interval.
- * |[1] |IDSTS |USB_ID Pin State Of Mini-B/Micro-Plug
- * | | |0 = Mini-A/Micro-A plug is attached.
- * | | |1 = Mini-B/Micro-B plug is attached.
- * |[2] |SESSEND |Session End Status
- * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1.
- * | | |Session end means no meaningful power on VBUS.
- * | | |0 = Session is not end.
- * | | |1 = Session is end.
- * |[3] |BVLD |B-Device Session Valid Status
- * | | |0 = B-device session is not valid.
- * | | |1 = B-device session is valid.
- * |[4] |AVLD |A-Device Session Valid Status
- * | | |0 = A-device session is not valid.
- * | | |1 = A-device session is valid.
- * |[5] |VBUSVLD |VBUS Valid Status
- * | | |When VBUS is larger than 4.7V, this bit will be set to 1.
- * | | |0 = VBUS is not valid.
- * | | |1 = VBUS is valid.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 OTG Control Register */
- __IO uint32_t PHYCTL; /* Offset: 0x04 OTG PHY Control Register */
- __IO uint32_t INTEN; /* Offset: 0x08 OTG Interrupt Enable Register */
- __IO uint32_t INTSTS; /* Offset: 0x0C OTG Interrupt Status Register */
- __I uint32_t STATUS; /* Offset: 0x10 OTG Status Register */
-
-} OTG_T;
-
-
-
-/**
- @addtogroup OTG_CONST OTG Bit Field Definition
- Constant Definitions for OTG Controller
-@{ */
-
-#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */
-#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */
-
-#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */
-#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */
-
-#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */
-#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */
-
-#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */
-#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */
-
-#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */
-#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */
-
-#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */
-#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */
-
-#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */
-#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */
-
-#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */
-#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */
-
-#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */
-#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */
-
-#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */
-#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */
-
-#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */
-#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */
-
-#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */
-#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */
-
-#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */
-#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */
-
-#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */
-#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */
-
-#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */
-#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */
-
-#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */
-#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */
-
-#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */
-#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */
-
-#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */
-#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */
-
-#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */
-#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */
-
-#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */
-#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */
-
-#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */
-#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */
-
-#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */
-#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */
-
-#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */
-#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */
-
-#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */
-#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */
-
-#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */
-#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */
-
-#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */
-#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */
-
-#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */
-#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */
-
-#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */
-#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */
-
-#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */
-#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */
-
-#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */
-#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */
-
-#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */
-#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */
-
-#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */
-#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */
-
-#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */
-#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */
-
-#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */
-#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */
-
-#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */
-#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */
-
-#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */
-#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */
-
-#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */
-#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */
-
-#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */
-#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */
-
-#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */
-#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */
-
-#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */
-#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */
-
-#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */
-#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */
-
-/**@}*/ /* OTG_CONST */
-/**@}*/ /* end of OTG register group */
-
-
-/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
-/**
- @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
- Memory Mapped Structure for PDMA Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var DSCT_T::CTL
- * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |OPMODE |PDMA Operation Mode Selection
- * | | |0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
- * | | |1 = Basic mode: The descriptor table only has one task.
- * | | |When this task is finished, the PDMA_INTSTS[x] will be asserted.
- * | | |2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
- * | | |3 = Reserved.
- * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
- * |[2] |TXTYPE |Transfer Type
- * | | |0 = Burst transfer type.
- * | | |1 = Single transfer type.
- * |[6:4] |BURSIZE |Burst Size
- * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
- * | | |000 = 128 Transfers.
- * | | |001 = 64 Transfers.
- * | | |010 = 32 Transfers.
- * | | |011 = 16 Transfers.
- * | | |100 = 8 Transfers.
- * | | |101 = 4 Transfers.
- * | | |110 = 2 Transfers.
- * | | |111 = 1 Transfers.
- * | | |Note: This field is only useful in burst transfer type.
- * |[7] |TBINTDIS |Table Interrupt Disable
- * | | |This field can be used to decide whether to enable table interrupt or not.
- * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt.
- * | | |0 = Table interrupt Enabled.
- * | | |1 = Table interrupt Disabled.
- * | | |Note: If this bit set to '1', the TEMPTYF will not be set.
- * |[9:8] |SAINC |Source Address Increment
- * | | |This field is used to set the source address increment size.
- * | | |11 = No increment (fixed address).
- * | | |Others = Increment and size is depended on TXWIDTH selection.
- * |[11:10] |DAINC |Destination Address Increment
- * | | |This field is used to set the destination address increment size.
- * | | |11 = No increment (fixed address).
- * | | |Others = Increment and size is depended on TXWIDTH selection.
- * |[13:12] |TXWIDTH |Transfer Width Selection
- * | | |This field is used for transfer width.
- * | | |00 = One byte (8 bit) is transferred for every operation.
- * | | |01= One half-word (16 bit) is transferred for every operation.
- * | | |10 = One word (32-bit) is transferred for every operation.
- * | | |11 = Reserved.
- * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
- * |[29:16] |TXCNT |Transfer Count
- * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
- * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately.
- * @var DSCT_T::SA
- * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |SA |PDMA Transfer Source Address Register
- * | | |This field indicates a 32-bit source address of PDMA controller.
- * @var DSCT_T::DA
- * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |DA |PDMA Transfer Destination Address Register
- * | | |This field indicates a 32-bit destination address of PDMA controller.
- * @var DSCT_T::NEXT
- * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:2] |NEXT |PDMA Next Descriptor Table Offset Address Register
- * | | |This field indicates the offset of next descriptor table address in system memory.
- * | | |The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.
- * | | |Note1: The next descriptor table address must be word boundary.
- * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11 */
- __IO uint32_t SA; /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11 */
- __IO uint32_t DA; /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11 */
- __IO uint32_t NEXT; /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */
-
-} DSCT_T;
-
-
-
-
-typedef struct
-{
-
-
-/**
- * @var PDMA_T::DSCT
- * Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11
- * ---------------------------------------------------------------------------------------------------
- * @var PDMA_T::CURSCAT
- * Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only)
- * | | |This field indicates a 32-bit current external description address of PDMA controller.
- * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
- * @var PDMA_T::CHCTL
- * Offset: 0x400 PDMA Channel Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |CHENn |PDMA Channel Enable Bit
- * | | |Set this bit to 1 to enable PDMAn operation.
- * | | |If each channel is not set as enabled, each channel cannot be active.
- * | | |0 = PDMA channel [n] Disabled.
- * | | |1 = PDMA channel [n] Enabled.
- * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
- * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
- * @var PDMA_T::STOP
- * Offset: 0x404 PDMA Transfer Stop Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |STOPn |PDMA Transfer Stop Control Register (Write Only)
- * | | |User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).
- * | | |By bit field:
- * | | |0 = No effect.
- * | | |1 = Stop PDMA transfer[n].
- * | | |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag.
- * | | |By write 0xFFFF_FFFF to PDMA_STOP:
- * | | |Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the DSCT will not be reset).
- * | | |When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'.
- * | | |Note: User can poll channel enable bit to know if the on-going transfer is finished.
- * @var PDMA_T::SWREQ
- * Offset: 0x408 PDMA Software Request Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |SWREQn |PDMA Software Request Register (Write Only)
- * | | |Set this bit to 1 to generate a software request to PDMA [n].
- * | | |0 = No effect.
- * | | |1 = Generate a software request.
- * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active.
- * | | |Active flag may be triggered by software request or peripheral request.
- * | | |Note2: If user does not enable each PDMA channel, the software request will be ignored.
- * @var PDMA_T::TRGSTS
- * Offset: 0x40C PDMA Channel Request Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |REQSTSn |PDMA Channel Request Status (Read Only)
- * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
- * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
- * | | |0 = PDMA Channel n has no request.
- * | | |1 = PDMA Channel n has a request.
- * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
- * | | |Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
- * @var PDMA_T::PRISET
- * Offset: 0x410 PDMA Fixed Priority Setting Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |FPRISETn |PDMA Fixed Priority Setting Register
- * | | |Set this bit to 1 to enable fixed priority level.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Set PDMA channel [n] to fixed priority channel.
- * | | |Read Operation:
- * | | |0 = Corresponding PDMA channel is round-robin priority.
- * | | |1 = Corresponding PDMA channel is fixed priority.
- * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
- * @var PDMA_T::PRICLR
- * Offset: 0x414 PDMA Fixed Priority Clear Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only)
- * | | |Set this bit to 1 to clear fixed priority level.
- * | | |0 = No effect.
- * | | |1 = Clear PDMA channel [n] fixed priority setting.
- * | | |Note: User can read PDMA_PRISET register to know the channel priority.
- * @var PDMA_T::INTEN
- * Offset: 0x418 PDMA Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |INTENn |PDMA Interrupt Enable Register
- * | | |This field is used for enabling PDMA channel[n] interrupt.
- * | | |0 = PDMA channel n interrupt Disabled.
- * | | |1 = PDMA channel n interrupt Enabled.
- * |[31:12] |Reserved |should be keep 0.
- * @var PDMA_T::INTSTS
- * Offset: 0x41C PDMA Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read-Only)
- * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
- * | | |0 = No AHB bus ERROR response received.
- * | | |1 = AHB bus ERROR response received.
- * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only)
- * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
- * | | |0 = Not finished yet.
- * | | |1 = PDMA channel has finished transmission.
- * |[2] |TEIF |Table Empty Interrupt Flag (Read Only)
- * | | |This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode.
- * | | |User can read TEIF register to indicate which channel finished transfer.
- * | | |0 = PDMA channel transfer is not finished.
- * | | |1 = PDMA channel transfer is finished and the operation is in idle state.
- * |[8:15] |REQTOFn |Request Time-out Flag For Each Channel [N](M45xD/M45xC Only)
- * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
- * | | |0 = No request time-out.
- * | | |1 = Peripheral request time-out.
- * @var PDMA_T::ABTSTS
- * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag
- * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
- * | | |0 = No AHB bus ERROR response received when channel n transfer.
- * | | |1 = AHB bus ERROR response received when channel n transfer.
- * @var PDMA_T::TDSTS
- * Offset: 0x424 PDMA Channel Transfer Done Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |TDIFn |Transfer Done Flag Register
- * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
- * | | |0 = PDMA channel transfer has not finished.
- * | | |1 = PDMA channel has finished transmission.
- * @var PDMA_T::SCATSTS
- * Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |TEMPTYFn |Scatter-Gather Table Empty Flag Register
- * | | |This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn set to high or channel has finished transmission and the operation mode is Stop mode.
- * | | |User can write 1 to clear these bits.
- * | | |0 = PDMA channel scatter-gather table is not empty.
- * | | |1 = PDMA channel scatter-gather table is empty and PDMA SWREQ has be set.
- * @var PDMA_T::TACTSTS
- * Offset: 0x42C PDMA Transfer Active Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |TXACTFn |Transfer On Active Flag Register (Read Only)
- * | | |This bit indicates which PDMA channel is in active.
- * | | |0 = PDMA channel is not finished.
- * | | |1 = PDMA channel is active.
- * @var PDMA_T::TOUTEN
- * Offset: 0x434 PDMA Time-out Enable register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TOUTENn |PDMA Time-Out Enable Bits
- * | | |0 = PDMA Channel n time-out function Disable.
- * | | |1 = PDMA Channel n time-out function Enable.
- * @var PDMA_T::TOUTIEN
- * Offset: 0x438 PDMA Time-out Interrupt Enable register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TOUTIENn |PDMA Time-Out Interrupt Enable Bits
- * | | |0 = PDMA Channel n time-out interrupt Disable.
- * | | |1 = PDMA Channel n time-out interrupt Enable.
- * @var PDMA_T::SCATBA
- * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:16] |SCATBA |PDMA Scatter-Gather Descriptor Table Address Register
- * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
- * | | |The next link address equation is.
- * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
- * | | |Note: Only useful in Scatter-Gather mode.
- * @var PDMA_T::TOC0_1
- * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:16] |TOC1 |Time-Out Counter For Channel 1
- * | | |This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
- * |[15:0] |TOC0 |Time-Out Counter For Channel 0
- * | | |This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
- * @var PDMA_T::TOC2_3
- * Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:16] |TOC3 |Time-Out Counter For Channel 3
- * | | |This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
- * |[15:0] |TOC2 |Time-Out Counter For Channel 2
- * | | |This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
- * @var PDMA_T::TOC4_5
- * Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:16] |TOC5 |Time-Out Counter For Channel 5
- * | | |This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
- * |[15:0] |TOC4 |Time-Out Counter For Channel 4
- * | | |This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
- * @var PDMA_T::TOC6_7
- * Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:16] |TOC7 |Time-Out Counter For Channel 7
- * | | |This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
- * |[15:0] |TOC6 |Time-Out Counter For Channel 6
- * | | |This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
- * @var PDMA_T::REQSEL0_3
- * Offset: 0x480 PDMA Request Source Select Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:0] |REQSRC0 |Channel 0 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 0.
- * | | |User can configure the peripheral by setting REQSRC0.
- * | | |1 = Channel connects to SPI0_TX.
- * | | |2 = Channel connects to SPI1_TX.
- * | | |3 = Channel connects to SPI2_TX.
- * | | |4 = Channel connects to UART0_TX.
- * | | |5 = Channel connects to UART1_TX.
- * | | |6 = Channel connects to UART2_TX.
- * | | |7 = Channel connects to UART3_TX.
- * | | |8 = Channel connects to DAC_TX.
- * | | |9 = Channel connects to ADC_RX.
- * | | |11 = Channel connects to PWM0_P1_RX.
- * | | |12 = Channel connects to PWM0_P2_RX.
- * | | |13 = Channel connects to PWM0_P3_RX.
- * | | |14 = Channel connects to PWM1_P1_RX.
- * | | |15 = Channel connects to PWM1_P2_RX.
- * | | |16 = Channel connects to PWM1_P3_RX.
- * | | |17 = Channel connects to SPI0_RX.
- * | | |18 = Channel connects to SPI1_RX.
- * | | |19 = Channel connects to SPI2_RX.
- * | | |20 = Channel connects to UART0_RX.
- * | | |21 = Channel connects to UART1_RX.
- * | | |22 = Channel connects to UART2_RX.
- * | | |23 = Channel connects to UART3_RX.
- * | | |31 = Disable PDMA.
- * | | |Others = Reserved.
- * | | |Note 1: A peripheral can't assign to two channels at the same time.
- * | | |Note 2: This field is useless when transfer between memory and memory.
- * |[12:8] |REQSRC1 |Channel 1 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 1.
- * | | |User can configure the peripheral setting by REQSRC1.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[20:16] |REQSRC2 |Channel 2 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 2.
- * | | |User can configure the peripheral setting by REQSRC2.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[28:24] |REQSRC3 |Channel 3 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 3.
- * | | |User can configure the peripheral setting by REQSRC3.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * @var PDMA_T::REQSEL4_7
- * Offset: 0x484 PDMA Request Source Select Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:0] |REQSRC4 |Channel 4 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 4.
- * | | |User can configure the peripheral setting by REQSRC4.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[12:8] |REQSRC5 |Channel 5 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 5.
- * | | |User can configure the peripheral setting by REQSRC5.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[20:16] |REQSRC6 |Channel 6 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 6.
- * | | |User can configure the peripheral setting by REQSRC6.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[28:24] |REQSRC7 |Channel 7 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 7.
- * | | |User can configure the peripheral setting by REQSRC7.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * @var PDMA_T::REQSEL8_11
- * Offset: 0x488 PDMA Request Source Select Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:0] |REQSRC8 |Channel 8 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 8.
- * | | |User can configure the peripheral setting by REQSRC8.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[12:8] |REQSRC9 |Channel 9 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 9.
- * | | |User can configure the peripheral setting by REQSRC9.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[20:16] |REQSRC10 |Channel 10 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 10.
- * | | |User can configure the peripheral setting by REQSRC10.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[28:24] |REQSRC11 |Channel 11 Request Source Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 11.
- * | | |User can configure the peripheral setting by REQSRC11.
- * | | |Note: The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- */
-
- DSCT_T DSCT[12]; /* Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11 */
- __I uint32_t CURSCAT[12];
- __I uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */
- __IO uint32_t CHCTL; /* Offset: 0x400 PDMA Channel Control Register */
- __O uint32_t STOP; /* Offset: 0x404 PDMA Transfer Stop Control Register */
- __O uint32_t SWREQ; /* Offset: 0x408 PDMA Software Request Register */
- __I uint32_t TRGSTS; /* Offset: 0x40C PDMA Channel Request Status Register */
- __IO uint32_t PRISET; /* Offset: 0x410 PDMA Fixed Priority Setting Register */
- __O uint32_t PRICLR; /* Offset: 0x414 PDMA Fixed Priority Clear Register */
- __IO uint32_t INTEN; /* Offset: 0x418 PDMA Interrupt Enable Register */
- __IO uint32_t INTSTS; /* Offset: 0x41C PDMA Interrupt Status Register */
- __IO uint32_t ABTSTS; /* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register */
- __IO uint32_t TDSTS; /* Offset: 0x424 PDMA Channel Transfer Done Flag Register */
- __IO uint32_t SCATSTS; /* Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register */
- __I uint32_t TACTSTS;
- __I uint32_t RESERVE1[1]; /* Offset: 0x42C PDMA Transfer Active Flag Register */
- __IO uint32_t TOUTEN; /* Offset: 0x434 PDMA Time-out Enable register */
- __IO uint32_t TOUTIEN; /* Offset: 0x438 PDMA Time-out Interrupt Enable register */
- __IO uint32_t SCATBA; /* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register */
- __IO uint32_t TOC0_1; /* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register */
- __IO uint32_t TOC2_3; /* Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register */
- __IO uint32_t TOC4_5; /* Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register */
- __IO uint32_t TOC6_7;
- __I uint32_t RESERVE2[12]; /* Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register */
- __IO uint32_t REQSEL0_3; /* Offset: 0x480 PDMA Request Source Select Register 0 */
- __IO uint32_t REQSEL4_7; /* Offset: 0x484 PDMA Request Source Select Register 1 */
- __IO uint32_t REQSEL8_11; /* Offset: 0x484 PDMA Request Source Select Register 2 */
-
-} PDMA_T;
-
-
-
-/**
- @addtogroup PDMA_CONST PDMA Bit Field Definition
- Constant Definitions for PDMA Controller
-@{ */
-
-#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< DSCT_T::CTL: OPMODE Position */
-#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< DSCT_T::CTL: OPMODE Mask */
-
-#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< DSCT_T::CTL: TXTYPE Position */
-#define PDMA_DSCT_CTL_TXTYPE_Msk (1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< DSCT_T::CTL: TXTYPE Mask */
-
-#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< DSCT_T::CTL: BURSIZE Position */
-#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< DSCT_T::CTL: BURSIZE Mask */
-
-#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< DSCT_T::CTL: TBINTDIS Position */
-#define PDMA_DSCT_CTL_TBINTDIS_Msk (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< DSCT_T::CTL: TBINTDIS Mask */
-
-#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< DSCT_T::CTL: SAINC Position */
-#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< DSCT_T::CTL: SAINC Mask */
-
-#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< DSCT_T::CTL: DAINC Position */
-#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< DSCT_T::CTL: DAINC Mask */
-
-#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< DSCT_T::CTL: TXWIDTH Position */
-#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< DSCT_T::CTL: TXWIDTH Mask */
-
-#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< DSCT_T::CTL: TXCNT Position */
-#define PDMA_DSCT_CTL_TXCNT_Msk (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos) /*!< DSCT_T::CTL: TXCNT Mask */
-
-#define PDMA_DSCT_SA_SA_Pos (0) /*!< DSCT_T::SA: SA Position */
-#define PDMA_DSCT_SA_SA_Msk (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos) /*!< DSCT_T::SA: SA Mask */
-
-#define PDMA_DSCT_DA_DA_Pos (0) /*!< DSCT_T::DA: DA Position */
-#define PDMA_DSCT_DA_DA_Msk (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos) /*!< DSCT_T::DA: DA Mask */
-
-#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< DSCT_T::NEXT: NEXT Position */
-#define PDMA_DSCT_NEXT_NEXT_Msk (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos) /*!< DSCT_T::NEXT: NEXT Mask */
-
-#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */
-#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */
-
-#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */
-#define PDMA_CHCTL_CHENn_Msk (0xffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */
-
-#define PDMA_STOP_STOPn_Pos (0) /*!< PDMA_T::STOP: STOPn Position */
-#define PDMA_STOP_STOPn_Msk (0xffful << PDMA_STOP_STOPn_Pos) /*!< PDMA_T::STOP: STOPn Mask */
-
-#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */
-#define PDMA_SWREQ_SWREQn_Msk (0xffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */
-
-#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */
-#define PDMA_TRGSTS_REQSTSn_Msk (0xffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */
-
-#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */
-#define PDMA_PRISET_FPRISETn_Msk (0xffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */
-
-#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */
-#define PDMA_PRICLR_FPRICLRn_Msk (0xffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */
-
-#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */
-#define PDMA_INTEN_INTENn_Msk (0xffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */
-
-#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */
-#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */
-
-#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */
-#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */
-
-#define PDMA_INTSTS_TEIF_Pos (2) /*!< PDMA_T::INTSTS: TEIF Position */
-#define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /*!< PDMA_T::INTSTS: TEIF Mask */
-
-#define PDMA_INTSTS_REQTOFn_Pos (8) /*!< PDMA_T::INTSTS: REQTOFn Position */
-#define PDMA_INTSTS_REQTOFn_Msk (0xfful << PDMA_INTSTS_REQTOFn_Pos) /*!< PDMA_T::INTSTS: REQTOFn Mask */
-
-#define PDMA_ABTSTS_ABTIFn_Pos (0) /*!< PDMA_T::ABTSTS: ABTIFn Position */
-#define PDMA_ABTSTS_ABTIFn_Msk (0xffful << PDMA_ABTSTS_ABTIFn_Pos) /*!< PDMA_T::ABTSTS: ABTIFn Mask */
-
-#define PDMA_TDSTS_TDIFn_Pos (0) /*!< PDMA_T::TDSTS: TDIFn Position */
-#define PDMA_TDSTS_TDIFn_Msk (0xffful << PDMA_TDSTS_TDIFn_Pos) /*!< PDMA_T::TDSTS: TDIFn Mask */
-
-#define PDMA_SCATSTS_TEMPTYFn_Pos (0) /*!< PDMA_T::SCATSTS: TEMPTYFn Position */
-#define PDMA_SCATSTS_TEMPTYFn_Msk (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos) /*!< PDMA_T::SCATSTS: TEMPTYFn Mask */
-
-#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */
-#define PDMA_TACTSTS_TXACTFn_Msk (0xffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */
-
-#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */
-#define PDMA_TOUTEN_TOUTENn_Msk (0xfful << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */
-
-#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */
-#define PDMA_TOUTIEN_TOUTIENn_Msk (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */
-
-#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */
-#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */
-
-#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */
-#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */
-
-#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */
-#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */
-
-#define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA_T::TOC2_3: TOC2 Position */
-#define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA_T::TOC2_3: TOC2 Mask */
-
-#define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA_T::TOC2_3: TOC3 Position */
-#define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA_T::TOC2_3: TOC3 Mask */
-
-#define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA_T::TOC4_5: TOC4 Position */
-#define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA_T::TOC4_5: TOC4 Mask */
-
-#define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA_T::TOC4_5: TOC5 Position */
-#define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA_T::TOC4_5: TOC5 Mask */
-
-#define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA_T::TOC6_7: TOC6 Position */
-#define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA_T::TOC6_7: TOC6 Mask */
-
-#define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA_T::TOC6_7: TOC7 Position */
-#define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA_T::TOC6_7: TOC7 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */
-#define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */
-#define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */
-#define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */
-#define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */
-#define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */
-#define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */
-#define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */
-#define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA_T::REQSEL8_11: REQSRC8 Position */
-#define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC8 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA_T::REQSEL8_11: REQSRC9 Position */
-#define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC9 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA_T::REQSEL8_11: REQSRC10 Position */
-#define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC10 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA_T::REQSEL8_11: REQSRC11 Position */
-#define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA_T::REQSEL8_11: REQSRC11 Mask */
-
-/**@}*/ /* PDMA_CONST */
-/**@}*/ /* end of PDMA register group */
-
-
-/*---------------------- Pulse Width Modulation Controller -------------------------*/
-/**
- @addtogroup PWM Pulse Width Modulation Controller(PWM)
- Memory Mapped Structure for PWM Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var PWM_T::CTL0
- * Offset: 0x00 PWM Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CTRLDn |Center Re-Load
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period.
- * | | |CMPDAT will load to CMPBUF at the center point of a period.
- * |[13:8] |WINLDENn |Window Load Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = PERIOD will load to PBUF at the end point of each period.
- * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
- * | | |1 = PERIOD will load to PBUF at the end point of each period.
- * | | |CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.
- * | | |The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
- * |[21:16] |IMMLDENn |Immediately Load Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = PERIOD will load to PBUF at the end point of each period.
- * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
- * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
- * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
- * |[24] |GROUPEN |Group Function Enable
- * | | |0 = The output waveform of each PWM channel are independent.
- * | | |1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.
- * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
- * | | |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
- * | | |0 = ICE debug mode counter halt disable.
- * | | |1 = ICE debug mode counter halt enable.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
- * | | |0 = ICE debug mode acknowledgement effects PWM output.
- * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
- * | | |1 = ICE debug mode acknowledgement disabled.
- * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::CTL1
- * Offset: 0x04 PWM Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |CNTTYPEn |PWM Counter Behavior Type
- * | | |Each bit n controls corresponding PWM channel n.
- * | | |00 = Up counter type (supports in capture mode).
- * | | |01 = Down count type (supports in capture mode).
- * | | |10 = Up-down counter type.
- * | | |11 = Reserved.
- * |[21:16] |CNTMODEn |PWM Counter Mode
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Auto-reload mode.
- * | | |1 = One-shot mode.
- * |[26:24] |OUTMODEn |PWM Output Mode
- * | | |Each bit n controls the
- * | | |output mode of
- * | | |corresponding PWM channel n.
- * | | |0 = PWM independent mode.
- * | | |1 = PWM complementary mode.
- * | | |Note: When operating in group function, these bits must all set to the same mode.
- * @var PWM_T::SYNC
- * Offset: 0x08 PWM Synchronization Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |PHSENn |SYNC Phase Enable
- * | | |Each bit n controls corresponding PWM channel n.
- * | | |0 = PWM counter disable to load PHS value.
- * | | |1 = PWM counter enable to load PHS value.
- * |[13:8] |SINSRCn |PWM_SYNC_IN Source Selection
- * | | |Each bit n controls corresponding PWM channel n.
- * | | |00 = Synchronize source from SYNC_IN or SWSYNC.
- * | | |01 = Counter equal to 0.
- * | | |10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.
- * | | |11 = SYNC_OUT will not be generated.
- * |[16] |SNFLTEN |PWM_SYNC_IN Noise Filter Enable
- * | | |0 = Noise filter of input pin PWM_SYNC_IN is Disabled.
- * | | |1 = Noise filter of input pin PWM_SYNC_IN is Enabled.
- * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection
- * | | |000 = Filter clock = HCLK.
- * | | |001 = Filter clock = HCLK/2.
- * | | |010 = Filter clock = HCLK/4.
- * | | |011 = Filter clock = HCLK/8.
- * | | |100 = Filter clock = HCLK/16.
- * | | |101 = Filter clock = HCLK/32.
- * | | |110 = Filter clock = HCLK/64.
- * | | |111 = Filter clock = HCLK/128.
- * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count
- * | | |The register bits control the counter number of edge detector.
- * |[23] |SINPINV |SYNC Input Pin Inverse
- * | | |0 = The state of pin SYNC is passed to the negative edge detector.
- * | | |1 = The inverted state of pin SYNC is passed to the negative edge detector.
- * |[26:24] |PHSDIRn |PWM Phase Direction Control
- * | | |Each bit n controls corresponding PWM channel n.
- * | | |0 = Control PWM counter count decrement after synchronizing.
- * | | |1 = Control PWM counter count increment after synchronizing.
- * @var PWM_T::SWSYNC
- * Offset: 0x0C PWM Software Control Synchronization Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |SWSYNCn |Software SYNC Function
- * | | |Each bit n controls corresponding PWM channel n.
- * | | |When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
- * @var PWM_T::CLKSRC
- * Offset: 0x10 PWM Clock Source Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |ECLKSRC0 |PWM_CH01 External Clock Source Select
- * | | |000 = PWMx_CLK, x denotes 0 or 1.
- * | | |001 = TIMER0 overflow.
- * | | |010 = TIMER1 overflow.
- * | | |011 = TIMER2 overflow.
- * | | |100 = TIMER3 overflow.
- * | | |Others = Reserved.
- * |[10:8] |ECLKSRC2 |PWM_CH23 External Clock Source Select
- * | | |000 = PWMx_CLK, x denotes 0 or 1.
- * | | |001 = TIMER0 overflow.
- * | | |010 = TIMER1 overflow.
- * | | |011 = TIMER2 overflow.
- * | | |100 = TIMER3 overflow.
- * | | |Others = Reserved.
- * |[18:16] |ECLKSRC4 |PWM_CH45 External Clock Source Select
- * | | |000 = PWMx_CLK, x denotes 0 or 1.
- * | | |001 = TIMER0 overflow.
- * | | |010 = TIMER1 overflow.
- * | | |011 = TIMER2 overflow.
- * | | |100 = TIMER3 overflow.
- * | | |Others = Reserved.
- * @var PWM_T::CLKPSC0_1
- * Offset: 0x14 PWM Clock Pre-scale Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
- * | | |The clock of PWM counter is decided by clock prescaler.
- * | | |Each PWM pair share one PWM counter clock prescaler.
- * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
- * @var PWM_T::CLKPSC2_3
- * Offset: 0x18 PWM Clock Pre-scale Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
- * | | |The clock of PWM counter is decided by clock prescaler.
- * | | |Each PWM pair share one PWM counter clock prescaler.
- * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
- * @var PWM_T::CLKPSC4_5
- * Offset: 0x1C PWM Clock Pre-scale Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |CLKPSC |PWM Counter Clock Pre-Scale
- * | | |The clock of PWM counter is decided by clock prescaler.
- * | | |Each PWM pair share one PWM counter clock prescaler.
- * | | |The clock of PWM counter is divided by (CLKPSC+ 1).
- * @var PWM_T::CNTEN
- * Offset: 0x20 PWM Counter Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CNTENn |PWM Counter Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = PWM Counter and clock prescaler Stop Running.
- * | | |1 = PWM Counter and clock prescaler Start Running.
- * @var PWM_T::CNTCLR
- * Offset: 0x24 PWM Clear Counter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CNTCLRn |Clear PWM Counter Control Bit
- * | | |It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
- * | | |0 = No effect.
- * | | |1 = Clear 16-bit PWM counter to 0000H.
- * @var PWM_T::LOAD
- * Offset: 0x28 PWM Load Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |LOADn |Re-Load PWM Comparator Register (CMPDAT) Control Bit
- * | | |This bit is software write, hardware clear when current PWM period end.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Set load window of window loading mode.
- * | | |Read Operation:
- * | | |0 = No load window is set.
- * | | |1 = Load window is set.
- * | | |Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.
- * @var PWM_T::PERIOD
- * Offset: 0x30~0x44 PWM Period Register 0~5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |PERIOD |PWM Period Register
- * | | |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
- * | | |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
- * | | |PWM period time = (PERIOD+1) * PWM_CLK period.
- * | | |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
- * | | |PWM period time = 2 * PERIOD * PWM_CLK period.
- * @var PWM_T::CMPDAT
- * Offset: 0x50~0x64 PWM Comparator Register 0~5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |CMP |PWM Comparator Register
- * | | |CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC/DAC.
- * | | |In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
- * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
- * @var PWM_T::DTCTL0_1
- * Offset: 0x70 PWM Dead-Time Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
- * | | |The dead-time can be calculated from the following formula:
- * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
- * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
- * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-time insertion Disabled on the pin pair.
- * | | |1 = Dead-time insertion Enabled on the pin pair.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
- * | | |0 = Dead-time clock source from PWM_CLK.
- * | | |1 = Dead-time clock source from prescaler output.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::DTCTL2_3
- * Offset: 0x74 PWM Dead-Time Control Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
- * | | |The dead-time can be calculated from the following formula:
- * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
- * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
- * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-time insertion Disabled on the pin pair.
- * | | |1 = Dead-time insertion Enabled on the pin pair.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
- * | | |0 = Dead-time clock source from PWM_CLK.
- * | | |1 = Dead-time clock source from prescaler output.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::DTCTL4_5
- * Offset: 0x78 PWM Dead-Time Control Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |DTCNT |Dead-Time Counter (Write Protect)
- * | | |The dead-time can be calculated from the following formula:
- * | | |Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[16] |DTEN |Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
- * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
- * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-time insertion Disabled on the pin pair.
- * | | |1 = Dead-time insertion Enabled on the pin pair.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[24] |DTCKSEL |Dead-Time Clock Select (Write Protect) (M45xD/M45xC Only)
- * | | |0 = Dead-time clock source from PWM_CLK.
- * | | |1 = Dead-time clock source from prescaler output.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::PHS0_1
- * Offset: 0x80 PWM Counter Phase Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |PHS |PWM Synchronous Start Phase Bits
- * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
- * @var PWM_T::PHS2_3
- * Offset: 0x84 PWM Counter Phase Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |PHS |PWM Synchronous Start Phase Bits
- * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
- * @var PWM_T::PHS4_5
- * Offset: 0x88 PWM Counter Phase Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |PHS |PWM Synchronous Start Phase Bits
- * | | |PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
- * @var PWM_T::CNT
- * Offset: 0x90~0xA4 PWM Counter Register 0~5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |CNT |PWM Data Register (Read Only)
- * | | |User can monitor CNTR to know the current value in 16-bit period counter.
- * |[16] |DIRF |PWM Direction Indicator Flag (Read Only)
- * | | |0 = Counter is Down count.
- * | | |1 = Counter is UP count.
- * @var PWM_T::WGCTL0
- * Offset: 0xB0 PWM Generation Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |ZPCTLn |PWM Zero Point Control
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |00 = Do nothing.
- * | | |01 = PWM zero point output Low.
- * | | |10 = PWM zero point output High.
- * | | |11 = PWM zero point output Toggle.
- * | | |PWM can control output level when PWM counter count to zero.
- * |[27:16] |PRDPCTLn |PWM Period (Center) Point Control
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |00 = Do nothing.
- * | | |01 = PWM period (center) point output Low.
- * | | |10 = PWM period (center) point output High.
- * | | |11 = PWM period (center) point output Toggle.
- * | | |PWM can control output level when PWM counter count to (PERIODn+1).
- * | | |Note: This bit is center point control when PWM counter operating in up-down counter type.
- * @var PWM_T::WGCTL1
- * Offset: 0xB4 PWM Generation Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |CMPUCTLn |PWM Compare Up Point Control
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |00 = Do nothing.
- * | | |01 = PWM compare up point output Low.
- * | | |10 = PWM compare up point output High.
- * | | |11 = PWM compare up point output Toggle.
- * | | |PWM can control output level when PWM counter up count to CMPDAT.
- * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
- * |[27:16] |CMPDCTLn |PWM Compare Down Point Control
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |00 = Do nothing.
- * | | |01 = PWM compare down point output Low.
- * | | |10 = PWM compare down point output High.
- * | | |11 = PWM compare down point output Toggle.
- * | | |PWM can control output level when PWM counter down count to CMPDAT.
- * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
- * @var PWM_T::MSKEN
- * Offset: 0xB8 PWM Mask Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |MSKENn |PWM Mask Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |The PWM output signal will be masked when this bit is enabled.
- * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
- * | | |0 = PWM output signal is non-masked.
- * | | |1 = PWM output signal is masked and output MSKDATn data.
- * @var PWM_T::MSK
- * Offset: 0xBC PWM Mask Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |MSKDATn |PWM Mask Data Bit
- * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Output logic low to PWMn.
- * | | |1 = Output logic high to PWMn.
- * @var PWM_T::BNF
- * Offset: 0xC0 PWM Brake Noise Filter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BRK0NFEN |PWM Brake 0 Noise Filter Enable
- * | | |0 = Noise filter of PWM Brake 0 Disabled.
- * | | |1 = Noise filter of PWM Brake 0 Enabled.
- * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
- * | | |000 = Filter clock = HCLK.
- * | | |001 = Filter clock = HCLK/2.
- * | | |010 = Filter clock = HCLK/4.
- * | | |011 = Filter clock = HCLK/8.
- * | | |100 = Filter clock = HCLK/16.
- * | | |101 = Filter clock = HCLK/32.
- * | | |110 = Filter clock = HCLK/64.
- * | | |111 = Filter clock = HCLK/128.
- * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count
- * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
- * |[7] |BRK0PINV |Brake 0 Pin Inverse
- * | | |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.
- * | | |1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.
- * |[8] |BRK1NFEN |PWM Brake 1 Noise Filter Enable
- * | | |0 = Noise filter of PWM Brake 1 Disabled.
- * | | |1 = Noise filter of PWM Brake 1 Enabled.
- * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
- * | | |000 = Filter clock = HCLK.
- * | | |001 = Filter clock = HCLK/2.
- * | | |010 = Filter clock = HCLK/4.
- * | | |011 = Filter clock = HCLK/8.
- * | | |100 = Filter clock = HCLK/16.
- * | | |101 = Filter clock = HCLK/32.
- * | | |110 = Filter clock = HCLK/64.
- * | | |111 = Filter clock = HCLK/128.
- * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count
- * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
- * |[15] |BRK1PINV |Brake 1 Pin Inverse
- * | | |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.
- * | | |1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.
- * |[16] |BK0SRC |Brake 0 Pin Source Select (M45xD/M45xC Only)
- * | | |For PWM0 setting:
- * | | |0 = Brake 0 pin source come from PWM0_BRAKE0.
- * | | |1 = Brake 0 pin source come from PWM1_BRAKE0.
- * | | |For PWM1 setting:
- * | | |0 = Brake 0 pin source come from PWM1_BRAKE0.
- * | | |1 = Brake 0 pin source come from PWM0_BRAKE0.
- * |[24] |BK1SRC |Brake 1 Pin Source Select (M45xD/M45xC Only)
- * | | |For PWM0 setting:
- * | | |0 = Brake 1 pin source come from PWM0_BRAKE1.
- * | | |1 = Brake 1 pin source come from PWM1_BRAKE1.
- * | | |For PWM1 setting:
- * | | |0 = Brake 1 pin source come from PWM1_BRAKE1.
- * | | |1 = Brake 1 pin source come from PWM0_BRAKE1.
- * @var PWM_T::FAILBRK
- * Offset: 0xC4 PWM System Fail Brake Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function 0 Enable
- * | | |0 = Brake Function triggered by CSS detection Disabled.
- * | | |1 = Brake Function triggered by CSS detection Enabled.
- * |[1] |BODBRKEN |Brown-Out Detection Trigger PWM Brake Function 0 Enable
- * | | |0 = Brake Function triggered by BOD Disabled.
- * | | |1 = Brake Function triggered by BOD Enabled.
- * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable
- * | | |0 = Brake Function triggered by SRAM parity error detection Disabled.
- * | | |1 = Brake Function triggered by SRAM parity error detection Enabled.
- * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function 0 Enable
- * | | |0 = Brake Function triggered by Core lockup detection Disabled.
- * | | |1 = Brake Function triggered by Core lockup detection Enabled.
- * @var PWM_T::BRKCTL0_1
- * Offset: 0xC8 PWM Brake Edge Detect Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
- * | | |0 = ACMP0_O as edge-detect brake source Disabled.
- * | | |1 = ACMP0_O as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
- * | | |0 = ACMP1_O as edge-detect brake source Disabled.
- * | | |1 = ACMP1_O as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
- * | | |0 = BKP0 pin as edge-detect brake source Disabled.
- * | | |1 = BKP0 pin as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
- * | | |0 = BKP1 pin as edge-detect brake source Disabled.
- * | | |1 = BKP1 pin as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
- * | | |0 = System Fail condition as edge-detect brake source Disabled.
- * | | |1 = System Fail condition as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
- * | | |0 = ACMP0_O as level-detect brake source Disabled.
- * | | |1 = ACMP0_O as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
- * | | |0 = ACMP1_O as level-detect brake source Disabled.
- * | | |1 = ACMP1_O as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
- * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
- * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
- * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
- * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
- * | | |0 = System Fail condition as level-detect brake source Disabled.
- * | | |1 = System Fail condition as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
- * | | |00 = PWM even channel level-detect brake function not affect channel output.
- * | | |01 = PWM even channel output tri-state when level-detect brake happened.
- * | | |10 = PWM even channel output low level when level-detect brake happened.
- * | | |11 = PWM even channel output high level when level-detect brake happened.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
- * | | |00 = PWM odd channel level-detect brake function not affect channel output.
- * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
- * | | |10 = PWM odd channel output low level when level-detect brake happened.
- * | | |11 = PWM odd channel output high level when level-detect brake happened.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::BRKCTL2_3
- * Offset: 0xCC PWM Brake Edge Detect Control Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
- * | | |0 = ACMP0_O as edge-detect brake source Disabled.
- * | | |1 = ACMP0_O as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
- * | | |0 = ACMP1_O as edge-detect brake source Disabled.
- * | | |1 = ACMP1_O as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
- * | | |0 = BKP0 pin as edge-detect brake source Disabled.
- * | | |1 = BKP0 pin as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
- * | | |0 = BKP1 pin as edge-detect brake source Disabled.
- * | | |1 = BKP1 pin as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
- * | | |0 = System Fail condition as edge-detect brake source Disabled.
- * | | |1 = System Fail condition as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
- * | | |0 = ACMP0_O as level-detect brake source Disabled.
- * | | |1 = ACMP0_O as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
- * | | |0 = ACMP1_O as level-detect brake source Disabled.
- * | | |1 = ACMP1_O as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
- * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
- * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
- * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
- * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
- * | | |0 = System Fail condition as level-detect brake source Disabled.
- * | | |1 = System Fail condition as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
- * | | |00 = PWM even channel level-detect brake function not affect channel output.
- * | | |01 = PWM even channel output tri-state when level-detect brake happened.
- * | | |10 = PWM even channel output low level when level-detect brake happened.
- * | | |11 = PWM even channel output high level when level-detect brake happened.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
- * | | |00 = PWM odd channel level-detect brake function not affect channel output.
- * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
- * | | |10 = PWM odd channel output low level when level-detect brake happened.
- * | | |11 = PWM odd channel output high level when level-detect brake happened.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::BRKCTL4_5
- * Offset: 0xD0 PWM Brake Edge Detect Control Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-Detect Brake Source (Write Protect)
- * | | |0 = ACMP0_O as edge-detect brake source Disabled.
- * | | |1 = ACMP0_O as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-Detect Brake Source (Write Protect)
- * | | |0 = ACMP1_O as edge-detect brake source Disabled.
- * | | |1 = ACMP1_O as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
- * | | |0 = BKP0 pin as edge-detect brake source Disabled.
- * | | |1 = BKP0 pin as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
- * | | |0 = BKP1 pin as edge-detect brake source Disabled.
- * | | |1 = BKP1 pin as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[7] |SYSEBEN |Enable System Fail As Edge-Detect Brake Source (Write Protect)
- * | | |0 = System Fail condition as edge-detect brake source Disabled.
- * | | |1 = System Fail condition as edge-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-Detect Brake Source (Write Protect)
- * | | |0 = ACMP0_O as level-detect brake source Disabled.
- * | | |1 = ACMP0_O as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-Detect Brake Source (Write Protect)
- * | | |0 = ACMP1_O as level-detect brake source Disabled.
- * | | |1 = ACMP1_O as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
- * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
- * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
- * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
- * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[15] |SYSLBEN |Enable System Fail As Level-Detect Brake Source (Write Protect)
- * | | |0 = System Fail condition as level-detect brake source Disabled.
- * | | |1 = System Fail condition as level-detect brake source Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[17:16] |BRKAEVEN |PWM Brake Action Select For Even Channel (Write Protect)
- * | | |00 = PWM even channel level-detect brake function not affect channel output.
- * | | |01 = PWM even channel output tri-state when level-detect brake happened.
- * | | |10 = PWM even channel output low level when level-detect brake happened.
- * | | |11 = PWM even channel output high level when level-detect brake happened.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[19:18] |BRKAODD |PWM Brake Action Select For Odd Channel (Write Protect)
- * | | |00 = PWM odd channel level-detect brake function not affect channel output.
- * | | |01 = PWM odd channel output tri-state when level-detect brake happened.
- * | | |10 = PWM odd channel output low level when level-detect brake happened.
- * | | |11 = PWM odd channel output high level when level-detect brake happened.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::POLCTL
- * Offset: 0xD4 PWM Pin Polar Inverse Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |PINVn |PWM PIN Polar Inverse Control
- * | | |The register controls polarity state of PWM output.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = PWM output polar inverse Disabled.
- * | | |1 = PWM output polar inverse Enabled.
- * @var PWM_T::POEN
- * Offset: 0xD8 PWM Output Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |POENn |PWM Pin Output Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = PWM pin at tri-state.
- * | | |1 = PWM pin in output mode.
- * @var PWM_T::SWBRK
- * Offset: 0xDC PWM Software Brake Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |BRKETRGn |PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only)
- * | | |Each bit n controls the corresponding PWM pair n.
- * | | |Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[10:8] |BRKLTRGn |PWM Level Brake Software Trigger (Write Only) (Write Protect)
- * | | |Each bit n controls the corresponding PWM pair n.
- * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::INTEN0
- * Offset: 0xE0 PWM Interrupt Enable Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |ZIENn |PWM Zero Point Interrupt Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Zero point interrupt Disabled.
- * | | |1 = Zero point interrupt Enabled.
- * | | |Note: Odd channels will read always 0 at complementary mode.
- * |[7] |IFAIEN0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable
- * | | |0 = Interrupt Flag accumulator interrupt Disabled.
- * | | |1 = Interrupt Flag accumulator interrupt Enabled.
- * |[13:8] |PIENn |PWM Period Point Interrupt Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Period point interrupt Disabled.
- * | | |1 = Period point interrupt Enabled.
- * | | |Note1: When up-down counter type period point means center point.
- * | | |Note2: Odd channels will read always 0 at complementary mode.
- * |[15] |IFAIEN2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable
- * | | |0 = Interrupt Flag accumulator interrupt Disabled.
- * | | |1 = Interrupt Flag accumulator interrupt Enabled.
- * |[21:16] |CMPUIENn |PWM Compare Up Count Interrupt Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Compare up count interrupt Disabled.
- * | | |1 = Compare up count interrupt Enabled.
- * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
- * |[23] |IFAIEN4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable
- * | | |0 = Interrupt Flag accumulator interrupt Disabled.
- * | | |1 = Interrupt Flag accumulator interrupt Enabled.
- * |[29:24] |CMPDIENn |PWM Compare Down Count Interrupt Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Compare down count interrupt Disabled.
- * | | |1 = Compare down count interrupt Enabled.
- * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
- * @var PWM_T::INTEN1
- * Offset: 0xE4 PWM Interrupt Enable Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BRKEIEN0_1|PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
- * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
- * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[1] |BRKEIEN2_3|PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
- * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
- * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[2] |BRKEIEN4_5|PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
- * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
- * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[8] |BRKLIEN0_1|PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
- * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled.
- * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[9] |BRKLIEN2_3|PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
- * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled.
- * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[10] |BRKLIEN4_5|PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
- * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled.
- * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * @var PWM_T::INTSTS0
- * Offset: 0xE8 PWM Interrupt Flag Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |ZIFn |PWM Zero Point Interrupt Flag
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
- * |[7] |IFAIF0_1 |PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag
- * | | |Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
- * |[13:8] |PIFn |PWM Period Point Interrupt Flag
- * | | |This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero.
- * | | |Each bit n controls the corresponding PWM channel n.
- * |[15] |IFAIF2_3 |PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag
- * | | |Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
- * |[21:16] |CMPUIFn |PWM Compare Up Count Interrupt Flag
- * | | |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
- * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
- * |[23] |IFAIF4_5 |PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag
- * | | |Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
- * |[29:24] |CMPDIFn |PWM Compare Down Count Interrupt Flag
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
- * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
- * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
- * @var PWM_T::INTSTS1
- * Offset: 0xEC PWM Interrupt Flag Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BRKEIF0 |PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel0 edge-detect brake event do not happened.
- * | | |1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[1] |BRKEIF1 |PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel1 edge-detect brake event do not happened.
- * | | |1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[2] |BRKEIF2 |PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel2 edge-detect brake event do not happened.
- * | | |1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[3] |BRKEIF3 |PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel3 edge-detect brake event do not happened.
- * | | |1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[4] |BRKEIF4 |PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel4 edge-detect brake event do not happened.
- * | | |1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[5] |BRKEIF5 |PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel5 edge-detect brake event do not happened.
- * | | |1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[8] |BRKLIF0 |PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel0 level-detect brake event do not happened.
- * | | |1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[9] |BRKLIF1 |PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel1 level-detect brake event do not happened.
- * | | |1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[10] |BRKLIF2 |PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel2 level-detect brake event do not happened.
- * | | |1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[11] |BRKLIF3 |PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel3 level-detect brake event do not happened.
- * | | |1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[12] |BRKLIF4 |PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel4 level-detect brake event do not happened.
- * | | |1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[13] |BRKLIF5 |PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)
- * | | |0 = PWM channel5 level-detect brake event do not happened.
- * | | |1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
- * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
- * |[16] |BRKESTS0 |PWM Channel0 Edge-Detect Brake Status
- * | | |0 = PWM channel0 edge-detect brake state is released.
- * | | |1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear.
- * |[17] |BRKESTS1 |PWM Channel1 Edge-Detect Brake Status
- * | | |0 = PWM channel1 edge-detect brake state is released.
- * | | |1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear.
- * |[18] |BRKESTS2 |PWM Channel2 Edge-Detect Brake Status
- * | | |0 = PWM channel2 edge-detect brake state is released.
- * | | |1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear.
- * |[19] |BRKESTS3 |PWM Channel3 Edge-Detect Brake Status
- * | | |0 = PWM channel3 edge-detect brake state is released.
- * | | |1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear.
- * |[20] |BRKESTS4 |PWM Channel4 Edge-Detect Brake Status
- * | | |0 = PWM channel4 edge-detect brake state is released.
- * | | |1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear.
- * |[21] |BRKESTS5 |PWM Channel5 Edge-Detect Brake Status
- * | | |0 = PWM channel5 edge-detect brake state is released.
- * | | |1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear.
- * |[24] |BRKLSTS0 |PWM Channel0 Level-Detect Brake Status (Read Only)
- * | | |0 = PWM channel0 level-detect brake state is released.
- * | | |1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state.
- * | | |Note: This bit is read only and auto cleared by hardware.
- * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
- * | | |The PWM waveform will start output from next full PWM period.
- * |[25] |BRKLSTS1 |PWM Channel1 Level-Detect Brake Status (Read Only)
- * | | |0 = PWM channel1 level-detect brake state is released.
- * | | |1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state.
- * | | |Note: This bit is read only and auto cleared by hardware.
- * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
- * | | |The PWM waveform will start output from next full PWM period.
- * |[26] |BRKLSTS2 |PWM Channel2 Level-Detect Brake Status (Read Only)
- * | | |0 = PWM channel2 level-detect brake state is released.
- * | | |1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state.
- * | | |Note: This bit is read only and auto cleared by hardware.
- * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
- * | | |The PWM waveform will start output from next full PWM period.
- * |[27] |BRKLSTS3 |PWM Channel3 Level-Detect Brake Status (Read Only)
- * | | |0 = PWM channel3 level-detect brake state is released.
- * | | |1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state.
- * | | |Note: This bit is read only and auto cleared by hardware.
- * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
- * | | |The PWM waveform will start output from next full PWM period.
- * |[28] |BRKLSTS4 |PWM Channel4 Level-Detect Brake Status (Read Only)
- * | | |0 = PWM channel4 level-detect brake state is released.
- * | | |1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state.
- * | | |Note: This bit is read only and auto cleared by hardware.
- * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
- * | | |The PWM waveform will start output from next full PWM period.
- * |[29] |BRKLSTS5 |PWM Channel5 Level-Detect Brake Status (Read Only)
- * | | |0 = PWM channel5 level-detect brake state is released.
- * | | |1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state.
- * | | |Note: This bit is read only and auto cleared by hardware.
- * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
- * | | |The PWM waveform will start output from next full PWM period.
- * @var PWM_T::IFA
- * Offset: 0xF0 PWM Interrupt Flag Accumulator Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |IFCNT0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Counter
- * | | |The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt.
- * | | |PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period.
- * |[6:4] |IFSEL0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select
- * | | |000 = CNT equal to Zero in channel 0.
- * | | |001 = CNT equal to PERIOD in channel 0.
- * | | |010 = CNT equal to CMPU in channel 0.
- * | | |011 = CNT equal to CMPD in channel 0.
- * | | |100 = CNT equal to Zero in channel 1.
- * | | |101 = CNT equal to PERIOD in channel 1.
- * | | |110 = CNT equal to CMPU in channel 1.
- * | | |111 = CNT equal to CMPD in channel 1.
- * |[7] |IFAEN0_1 |PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable
- * | | |0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable.
- * | | |1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable.
- * |[11:8] |IFCNT2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Counter
- * | | |The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
- * | | |PWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
- * |[14:12] |IFSEL2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select
- * | | |000 = CNT equal to Zero in channel 2.
- * | | |001 = CNT equal to PERIOD in channel 2.
- * | | |010 = CNT equal to CMPU in channel 2.
- * | | |011 = CNT equal to CMPD in channel 2.
- * | | |100 = CNT equal to Zero in channel 3.
- * | | |101 = CNT equal to PERIOD in channel 3.
- * | | |110 = CNT equal to CMPU in channel 3.
- * | | |111 = CNT equal to CMPD in channel 3.
- * |[15] |IFAEN2_3 |PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable
- * | | |0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable.
- * | | |1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable.
- * |[19:16] |IFCNT4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Counter
- * | | |The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt.
- * | | |PWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
- * |[22:20] |IFSEL4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select
- * | | |000 = CNT equal to Zero in channel 4.
- * | | |001 = CNT equal to PERIOD in channel 4.
- * | | |010 = CNT equal to CMPU in channel 4.
- * | | |011 = CNT equal to CMPD in channel 4.
- * | | |100 = CNT equal to Zero in channel 5.
- * | | |101 = CNT equal to PERIOD in channel 5.
- * | | |110 = CNT equal to CMPU in channel 5.
- * | | |111 = CNT equal to CMPD in channel 5.
- * |[23] |IFAEN4_5 |PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable
- * | | |0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable.
- * | | |1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable.
- * @var PWM_T::DACTRGEN
- * Offset: 0xF4 PWM Trigger DAC Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |ZTEn |PWM Zero Point Trigger DAC Enable
- * | | |0 = PWM period point trigger DAC function Disabled.
- * | | |1 = PWM period point trigger DAC function Enabled.
- * | | |PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to 1.
- * | | |Each bit n controls the corresponding PWM channel n.
- * |[13:8] |PTEn |PWM Period Point Trigger DAC Enable
- * | | |0 = PWM period point trigger DAC function Disabled.
- * | | |1 = PWM period point trigger DAC function Enabled.
- * | | |PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to 1.
- * | | |Each bit n controls the corresponding PWM channel n.
- * |[21:16] |CUTRGEn |PWM Compare Up Count Point Trigger DAC Enable
- * | | |0 = PWM Compare Up point trigger DAC function Disabled.
- * | | |1 = PWM Compare Up point trigger DAC function Enabled.
- * | | |PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to 1.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |Note1: This bit should keep at 0 when PWM counter operating in down counter type.
- * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
- * |[29:24] |CDTRGEn |PWM Compare Down Count Point Trigger DAC Enable
- * | | |0 = PWM Compare Down count point trigger DAC function Disabled.
- * | | |1 = PWM Compare Down count point trigger DAC function Enabled.
- * | | |PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to 1.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |Note1: This bit should keep at 0 when PWM counter operating in up counter type.
- * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
- * @var PWM_T::EADCTS0
- * Offset: 0xF8 PWM Trigger EADC Source Select Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |TRGSEL0 |PWM_CH0 Trigger EADC Source Select
- * | | |0000 = PWM_CH0 zero point.
- * | | |0001 = PWM_CH0 period point.
- * | | |0010 = PWM_CH0 zero or period point.
- * | | |0011 = PWM_CH0 up-count CMPDAT point.
- * | | |0100 = PWM_CH0 down-count CMPDAT point.
- * | | |0101 = PWM_CH1 zero point.
- * | | |0110 = PWM_CH1 period point.
- * | | |0111 = PWM_CH1 zero or period point.
- * | | |1000 = PWM_CH1 up-count CMPDAT point.
- * | | |1001 = PWM_CH1 down-count CMPDAT point.
- * | | |1010 = PWM_CH0 up-count free CMPDAT point.
- * | | |1011 = PWM_CH0 down-count free CMPDAT point.
- * | | |1100 = PWM_CH2 up-count free CMPDAT point.
- * | | |1101 = PWM_CH2 down-count free CMPDAT point.
- * | | |1110 = PWM_CH4 up-count free CMPDAT point.
- * | | |1111 = PWM_CH4 down-count free CMPDAT point.
- * |[7] |TRGEN0 |PWM_CH0 Trigger EADC enable bit
- * |[11:8] |TRGSEL1 |PWM_CH1 Trigger EADC Source Select
- * | | |0000 = PWM_CH0 zero point.
- * | | |0001 = PWM_CH0 period point.
- * | | |0010 = PWM_CH0 zero or period point.
- * | | |0011 = PWM_CH0 up-count CMPDAT point.
- * | | |0100 = PWM_CH0 down-count CMPDAT point.
- * | | |0101 = PWM_CH1 zero point.
- * | | |0110 = PWM_CH1 period point.
- * | | |0111 = PWM_CH1 zero or period point.
- * | | |1000 = PWM_CH1 up-count CMPDAT point.
- * | | |1001 = PWM_CH1 down-count CMPDAT point.
- * | | |1010 = PWM_CH0 up-count free CMPDAT point.
- * | | |1011 = PWM_CH0 down-count free CMPDAT point.
- * | | |1100 = PWM_CH2 up-count free CMPDAT point.
- * | | |1101 = PWM_CH2 down-count free CMPDAT point.
- * | | |1110 = PWM_CH4 up-count free CMPDAT point.
- * | | |1111 = PWM_CH4 down-count free CMPDAT point.
- * |[15] |TRGEN1 |PWM_CH1 Trigger EADC enable bit
- * |[19:16] |TRGSEL2 |PWM_CH2 Trigger EADC Source Select
- * | | |0000 = PWM_CH2 zero point.
- * | | |0001 = PWM_CH2 period point.
- * | | |0010 = PWM_CH2 zero or period point.
- * | | |0011 = PWM_CH2 up-count CMPDAT point.
- * | | |0100 = PWM_CH2 down-count CMPDAT point.
- * | | |0101 = PWM_CH3 zero point.
- * | | |0110 = PWM_CH3 period point.
- * | | |0111 = PWM_CH3 zero or period point.
- * | | |1000 = PWM_CH3 up-count CMPDAT point.
- * | | |1001 = PWM_CH3 down-count CMPDAT point.
- * | | |1010 = PWM_CH0 up-count free CMPDAT point.
- * | | |1011 = PWM_CH0 down-count free CMPDAT point.
- * | | |1100 = PWM_CH2 up-count free CMPDAT point.
- * | | |1101 = PWM_CH2 down-count free CMPDAT point.
- * | | |1110 = PWM_CH4 up-count free CMPDAT point.
- * | | |1111 = PWM_CH4 down-count free CMPDAT point.
- * |[23] |TRGEN2 |PWM_CH2 Trigger EADC enable bit
- * |[27:24] |TRGSEL3 |PWM_CH3 Trigger EADC Source Select
- * | | |0000 = PWM_CH2 zero point.
- * | | |0001 = PWM_CH2 period point.
- * | | |0010 = PWM_CH2 zero or period point.
- * | | |0011 = PWM_CH2 up-count CMPDAT point.
- * | | |0100 = PWM_CH2 down-count CMPDAT point.
- * | | |0101 = PWM_CH3 zero point.
- * | | |0110 = PWM_CH3 period point.
- * | | |0111 = PWM_CH3 zero or period point.
- * | | |1000 = PWM_CH3 up-count CMPDAT point.
- * | | |1001 = PWM_CH3 down-count CMPDAT point.
- * | | |1010 = PWM_CH0 up-count free CMPDAT point.
- * | | |1011 = PWM_CH0 down-count free CMPDAT point.
- * | | |1100 = PWM_CH2 up-count free CMPDAT point.
- * | | |1101 = PWM_CH2 down-count free CMPDAT point.
- * | | |1110 = PWM_CH4 up-count free CMPDAT point.
- * | | |1111 = PWM_CH4 down-count free CMPDAT point.
- * |[31] |TRGEN3 |PWM_CH3 Trigger EADC enable bit
- * @var PWM_T::EADCTS1
- * Offset: 0xFC PWM Trigger EADC Source Select Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |TRGSEL4 |PWM_CH4 Trigger EADC Source Select
- * | | |0000 = PWM_CH4 zero point.
- * | | |0001 = PWM_CH4 period point.
- * | | |0010 = PWM_CH4 zero or period point.
- * | | |0011 = PWM_CH4 up-count CMPDAT point.
- * | | |0100 = PWM_CH4 down-count CMPDAT point.
- * | | |0101 = PWM_CH5 zero point.
- * | | |0110 = PWM_CH5 period point.
- * | | |0111 = PWM_CH5 zero or period point.
- * | | |1000 = PWM_CH5 up-count CMPDAT point.
- * | | |1001 = PWM_CH5 down-count CMPDAT point.
- * | | |1010 = PWM_CH0 up-count free CMPDAT point.
- * | | |1011 = PWM_CH0 down-count free CMPDAT point.
- * | | |1100 = PWM_CH2 up-count free CMPDAT point.
- * | | |1101 = PWM_CH2 down-count free CMPDAT point.
- * | | |1110 = PWM_CH4 up-count free CMPDAT point.
- * | | |1111 = PWM_CH4 down-count free CMPDAT point.
- * |[7] |TRGEN4 |PWM_CH4 Trigger EADC enable bit
- * |[11:8] |TRGSEL5 |PWM_CH5 Trigger EADC Source Select
- * | | |0000 = PWM_CH4 zero point.
- * | | |0001 = PWM_CH4 period point.
- * | | |0010 = PWM_CH4 zero or period point.
- * | | |0011 = PWM_CH4 up-count CMPDAT point.
- * | | |0100 = PWM_CH4 down-count CMPDAT point.
- * | | |0101 = PWM_CH5 zero point.
- * | | |0110 = PWM_CH5 period point.
- * | | |0111 = PWM_CH5 zero or period point.
- * | | |1000 = PWM_CH5 up-count CMPDAT point.
- * | | |1001 = PWM_CH5 down-count CMPDAT point.
- * | | |1010 = PWM_CH0 up-count free CMPDAT point.
- * | | |1011 = PWM_CH0 down-count free CMPDAT point.
- * | | |1100 = PWM_CH2 up-count free CMPDAT point.
- * | | |1101 = PWM_CH2 down-count free CMPDAT point.
- * | | |1110 = PWM_CH4 up-count free CMPDAT point.
- * | | |1111 = PWM_CH4 down-count free CMPDAT point.
- * |[15] |TRGEN5 |PWM_CH5 Trigger EADC enable bit
- * @var PWM_T::FTCMPDAT0_1
- * Offset: 0x100 PWM Free Trigger Compare Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FTCMP |PWM Free Trigger Compare Register
- * | | |FTCMP use to compare with even CNTR to trigger EADC.
- * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
- * @var PWM_T::FTCMPDAT2_3
- * Offset: 0x104 PWM Free Trigger Compare Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FTCMP |PWM Free Trigger Compare Register
- * | | |FTCMP use to compare with even CNTR to trigger EADC.
- * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
- * @var PWM_T::FTCMPDAT4_5
- * Offset: 0x108 PWM Free Trigger Compare Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FTCMP |PWM Free Trigger Compare Register
- * | | |FTCMP use to compare with even CNTR to trigger EADC.
- * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
- * @var PWM_T::SSCTL
- * Offset: 0x110 PWM Synchronous Start Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |SSENn |PWM Synchronous Start Function Enable
- * | | |When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = PWM synchronous start function Disabled.
- * | | |1 = PWM synchronous start function Enabled.
- * @var PWM_T::SSTRG
- * Offset: 0x114 PWM Synchronous Start Trigger Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CNTSEN |PWM Counter Synchronous Start Enable (Write Only)
- * | | |PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
- * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
- * | | |Note: This bit only present in PWM0_BA.
- * @var PWM_T::STATUS
- * Offset: 0x120 PWM Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CNTMAXFn |Time-Base Counter Equal To 0xFFFF Latched Flag
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
- * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
- * |[10:8] |SYNCINFn |Input Synchronization Latched Flag
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Indicates no SYNC_IN event has occurred.
- * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
- * |[21:16] |ADCTRGFn |EADC Start Of Conversion Flag
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
- * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
- * |[24] |DACTRGF |DAC Start Of Conversion Flag
- * | | |0 = Indicates no DAC start of conversion trigger event has occurred.
- * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
- * @var PWM_T::CAPINEN
- * Offset: 0x200 PWM Capture Input Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CAPINENn |Capture Input Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = PWM Channel capture input path Disabled.
- * | | |The input of PWM channel capture function is always regarded as 0.
- * | | |1 = PWM Channel capture input path Enabled.
- * | | |The input of PWM channel capture function comes from correlative multifunction pin.
- * @var PWM_T::CAPCTL
- * Offset: 0x204 PWM Capture Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CAPENn |Capture Function Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
- * | | |1 = Capture function Enabled.
- * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
- * |[13:8] |CAPINVn |Capture Inverter Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Capture source inverter Disabled.
- * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
- * |[21:16] |RCRLDENn |Rising Capture Reload Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Rising capture reload counter Disabled.
- * | | |1 = Rising capture reload counter Enabled.
- * |[29:24] |FCRLDENn |Falling Capture Reload Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Falling capture reload counter Disabled.
- * | | |1 = Falling capture reload counter Enabled.
- * @var PWM_T::CAPSTS
- * Offset: 0x208 PWM Capture Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CRLIFOVn |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
- * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
- * |[13:8] |CFLIFOVn |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
- * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
- * @var PWM_T::RCAPDAT0
- * Offset: 0x20C PWM Rising Capture Data Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
- * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::FCAPDAT0
- * Offset: 0x210 PWM Falling Capture Data Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
- * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::RCAPDAT1
- * Offset: 0x214 PWM Rising Capture Data Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
- * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::FCAPDAT1
- * Offset: 0x218 PWM Falling Capture Data Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
- * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::RCAPDAT2
- * Offset: 0x21C PWM Rising Capture Data Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
- * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::FCAPDAT2
- * Offset: 0x220 PWM Falling Capture Data Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
- * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::RCAPDAT3
- * Offset: 0x224 PWM Rising Capture Data Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
- * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::FCAPDAT3
- * Offset: 0x228 PWM Falling Capture Data Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
- * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::RCAPDAT4
- * Offset: 0x22C PWM Rising Capture Data Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
- * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::FCAPDAT4
- * Offset: 0x230 PWM Falling Capture Data Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
- * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::RCAPDAT5
- * Offset: 0x234 PWM Rising Capture Data Register 5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RCAPDAT |PWM Rising Capture Data Register (Read Only)
- * | | |When rising capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::FCAPDAT5
- * Offset: 0x238 PWM Falling Capture Data Register 5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FCAPDAT |PWM Falling Capture Data Register (Read Only)
- * | | |When falling capture condition happened, the PWM counter value will be saved in this register.
- * @var PWM_T::PDMACTL
- * Offset: 0x23C PWM PDMA Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable
- * | | |0 = Channel 0/1 PDMA function Disabled.
- * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
- * |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer
- * | | |00 = Reserved.
- * | | |01 = PWM_RCAPDAT0/1.
- * | | |10 = PWM_FCAPDAT0/1.
- * | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.
- * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
- * | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.
- * | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory.
- * | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory.
- * |[4] |CHSEL0_1 |Select Channel 0/1 To Do PDMA Transfer
- * | | |0 = Channel0.
- * | | |1 = Channel1.
- * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable
- * | | |0 = Channel 2/3 PDMA function Disabled.
- * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
- * |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer
- * | | |00 = Reserved.
- * | | |01 = PWM_RCAPDAT2/3.
- * | | |10 = PWM_FCAPDAT2/3.
- * | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
- * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
- * | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.
- * | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory.
- * | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory.
- * |[12] |CHSEL2_3 |Select Channel 2/3 To Do PDMA Transfer
- * | | |0 = Channel2.
- * | | |1 = Channel3.
- * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable
- * | | |0 = Channel 4/5 PDMA function Disabled.
- * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
- * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer
- * | | |00 = Reserved.
- * | | |01 = PWM_RCAPDAT4/5.
- * | | |10 = PWM_FCAPDAT4/5.
- * | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.
- * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
- * | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.
- * | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory.
- * | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory.
- * |[20] |CHSEL4_5 |Select Channel 4/5 To Do PDMA Transfer
- * | | |0 = Channel4.
- * | | |1 = Channel5.
- * @var PWM_T::PDMACAP0_1
- * Offset: 0x240 PWM Capture Channel 01 PDMA Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |CAPBUF |PWM Capture PDMA Register
- * | | |(Read Only)
- * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
- * @var PWM_T::PDMACAP2_3
- * Offset: 0x244 PWM Capture Channel 23 PDMA Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |CAPBUF |PWM Capture PDMA Register
- * | | |(Read Only)
- * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
- * @var PWM_T::PDMACAP4_5
- * Offset: 0x248 PWM Capture Channel 45 PDMA Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |CAPBUF |PWM Capture PDMA Register
- * | | |(Read Only)
- * | | |This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
- * @var PWM_T::CAPIEN
- * Offset: 0x250 PWM Capture Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CAPRIENn |PWM Capture Rising Latch Interrupt Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Capture rising edge latch interrupt Disabled.
- * | | |1 = Capture rising edge latch interrupt Enabled.
- * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
- * |[13:8] |CAPFIENn |PWM Capture Falling Latch Interrupt Enable
- * | | |Each bit n controls the corresponding PWM channel n.
- * | | |0 = Capture falling edge latch interrupt Disabled.
- * | | |1 = Capture falling edge latch interrupt Enabled.
- * | | |Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
- * @var PWM_T::CAPIF
- * Offset: 0x254 PWM Capture Interrupt Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CRLIFn |PWM Capture Rising Latch Interrupt Flag
- * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
- * | | |0 = No capture rising latch condition happened.
- * | | |1 = Capture rising latch condition happened, this flag will be set to high.
- * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
- * |[13:8] |CFLIFn |PWM Capture Falling Latch Interrupt Flag
- * | | |This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
- * | | |0 = No capture falling latch condition happened.
- * | | |1 = Capture falling latch condition happened, this flag will be set to high.
- * | | |Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
- * @var PWM_T::PBUF
- * Offset: 0x304~0x318 PWM PERIOD0~5 Buffer
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |PBUF |PWM Period Register Buffer
- * | | |(Read Only)
- * | | |Used as PERIOD active register.
- * @var PWM_T::CMPBUF
- * Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |CMPBUF |PWM Comparator Register Buffer
- * | | |(Read Only)
- * | | |Used as CMP active register.
- * @var PWM_T::FTCBUF0_1
- * Offset: 0x340 PWM FTCMPDAT0_1 Buffer
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
- * | | |Used as FTCMPDAT active register.
- * @var PWM_T::FTCBUF2_3
- * Offset: 0x344 PWM FTCMPDAT2_3 Buffer
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
- * | | |Used as FTCMPDAT active register.
- * @var PWM_T::FTCBUF4_5
- * Offset: 0x348 PWM FTCMPDAT4_5 Buffer
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FTCMPBUF |PWM FTCMPDAT Buffer (Read Only)
- * | | |Used as FTCMPDAT active register.
- * @var PWM_T::FTCI
- * Offset: 0x34C PWM FTCMPDAT Indicator Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |FTCMUn |PWM FTCMPDAT Up Indicator
- * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.
- * | | |Each bit n controls the corresponding PWM channel n.
- * |[10:8] |FTCMDn |PWM FTCMPDAT Down Indicator
- * | | |Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.
- * | | |Each bit n controls the corresponding PWM channel n.
- */
-
- __IO uint32_t CTL0; /* Offset: 0x00 PWM Control Register 0 */
- __IO uint32_t CTL1; /* Offset: 0x04 PWM Control Register 1 */
- __IO uint32_t SYNC; /* Offset: 0x08 PWM Synchronization Register */
- __IO uint32_t SWSYNC; /* Offset: 0x0C PWM Software Control Synchronization Register */
- __IO uint32_t CLKSRC; /* Offset: 0x10 PWM Clock Source Register */
- __IO uint32_t CLKPSC0_1; /* Offset: 0x14 PWM Clock Pre-scale Register 0 */
- __IO uint32_t CLKPSC2_3; /* Offset: 0x18 PWM Clock Pre-scale Register 2 */
- __IO uint32_t CLKPSC4_5; /* Offset: 0x1C PWM Clock Pre-scale Register 4 */
- __IO uint32_t CNTEN; /* Offset: 0x20 PWM Counter Enable Register */
- __IO uint32_t CNTCLR; /* Offset: 0x24 PWM Clear Counter Register */
- __IO uint32_t LOAD; /* Offset: 0x28 PWM Load Register */
- __I uint32_t RESERVE0[1];
- __IO uint32_t PERIOD[6]; /* Offset: 0x30~0x44 PWM Period Register 0~5 */
- __I uint32_t RESERVE1[2];
- __IO uint32_t CMPDAT[6]; /* Offset: 0x50~0x64 PWM Comparator Register 0~5 */
- __I uint32_t RESERVE2[2];
- __IO uint32_t DTCTL0_1; /* Offset: 0x70 PWM Dead-Time Control Register 0 */
- __IO uint32_t DTCTL2_3; /* Offset: 0x74 PWM Dead-Time Control Register 2 */
- __IO uint32_t DTCTL4_5; /* Offset: 0x78 PWM Dead-Time Control Register 4 */
- __I uint32_t RESERVE3[1];
- __IO uint32_t PHS0_1; /* Offset: 0x80 PWM Counter Phase Register 0 */
- __IO uint32_t PHS2_3; /* Offset: 0x84 PWM Counter Phase Register 2 */
- __IO uint32_t PHS4_5; /* Offset: 0x88 PWM Counter Phase Register 4 */
- __I uint32_t RESERVE4[1];
- __I uint32_t CNT[6]; /* Offset: 0x90~0xA4 PWM Counter Register 0~5 */
- __I uint32_t RESERVE5[2];
- __IO uint32_t WGCTL0; /* Offset: 0xB0 PWM Generation Register 0 */
- __IO uint32_t WGCTL1; /* Offset: 0xB4 PWM Generation Register 1 */
- __IO uint32_t MSKEN; /* Offset: 0xB8 PWM Mask Enable Register */
- __IO uint32_t MSK; /* Offset: 0xBC PWM Mask Data Register */
- __IO uint32_t BNF; /* Offset: 0xC0 PWM Brake Noise Filter Register */
- __IO uint32_t FAILBRK; /* Offset: 0xC4 PWM System Fail Brake Control Register */
- __IO uint32_t BRKCTL0_1; /* Offset: 0xC8 PWM Brake Edge Detect Control Register 0 */
- __IO uint32_t BRKCTL2_3; /* Offset: 0xCC PWM Brake Edge Detect Control Register 2 */
- __IO uint32_t BRKCTL4_5; /* Offset: 0xD0 PWM Brake Edge Detect Control Register 4 */
- __IO uint32_t POLCTL; /* Offset: 0xD4 PWM Pin Polar Inverse Register */
- __IO uint32_t POEN; /* Offset: 0xD8 PWM Output Enable Register */
- __O uint32_t SWBRK; /* Offset: 0xDC PWM Software Brake Control Register */
- __IO uint32_t INTEN0; /* Offset: 0xE0 PWM Interrupt Enable Register 0 */
- __IO uint32_t INTEN1; /* Offset: 0xE4 PWM Interrupt Enable Register 1 */
- __IO uint32_t INTSTS0; /* Offset: 0xE8 PWM Interrupt Flag Register 0 */
- __IO uint32_t INTSTS1; /* Offset: 0xEC PWM Interrupt Flag Register 1 */
- __IO uint32_t IFA; /* Offset: 0xF0 PWM Interrupt Flag Accumulator Register */
- __IO uint32_t DACTRGEN; /* Offset: 0xF4 PWM Trigger DAC Enable Register */
- __IO uint32_t EADCTS0; /* Offset: 0xF8 PWM Trigger EADC Source Select Register 0 */
- __IO uint32_t EADCTS1; /* Offset: 0xFC PWM Trigger EADC Source Select Register 1 */
- __IO uint32_t FTCMPDAT0_1; /* Offset: 0x100 PWM Free Trigger Compare Register 0 */
- __IO uint32_t FTCMPDAT2_3; /* Offset: 0x104 PWM Free Trigger Compare Register 2 */
- __IO uint32_t FTCMPDAT4_5; /* Offset: 0x108 PWM Free Trigger Compare Register 4 */
- __I uint32_t RESERVE6[1];
- __IO uint32_t SSCTL; /* Offset: 0x110 PWM Synchronous Start Control Register */
- __O uint32_t SSTRG; /* Offset: 0x114 PWM Synchronous Start Trigger Register */
- __I uint32_t RESERVE7[2];
- __IO uint32_t STATUS; /* Offset: 0x120 PWM Status Register */
- __I uint32_t RESERVE8[55];
- __IO uint32_t CAPINEN; /* Offset: 0x200 PWM Capture Input Enable Register */
- __IO uint32_t CAPCTL; /* Offset: 0x204 PWM Capture Control Register */
- __I uint32_t CAPSTS; /* Offset: 0x208 PWM Capture Status Register */
- __I uint32_t RCAPDAT0; /* Offset: 0x20C PWM Rising Capture Data Register 0 */
- __I uint32_t FCAPDAT0; /* Offset: 0x210 PWM Falling Capture Data Register 0 */
- __I uint32_t RCAPDAT1; /* Offset: 0x214 PWM Rising Capture Data Register 1 */
- __I uint32_t FCAPDAT1; /* Offset: 0x218 PWM Falling Capture Data Register 1 */
- __I uint32_t RCAPDAT2; /* Offset: 0x21C PWM Rising Capture Data Register 2 */
- __I uint32_t FCAPDAT2; /* Offset: 0x220 PWM Falling Capture Data Register 2 */
- __I uint32_t RCAPDAT3; /* Offset: 0x224 PWM Rising Capture Data Register 3 */
- __I uint32_t FCAPDAT3; /* Offset: 0x228 PWM Falling Capture Data Register 3 */
- __I uint32_t RCAPDAT4; /* Offset: 0x22C PWM Rising Capture Data Register 4 */
- __I uint32_t FCAPDAT4; /* Offset: 0x230 PWM Falling Capture Data Register 4 */
- __I uint32_t RCAPDAT5; /* Offset: 0x234 PWM Rising Capture Data Register 5 */
- __I uint32_t FCAPDAT5; /* Offset: 0x238 PWM Falling Capture Data Register 5 */
- __IO uint32_t PDMACTL; /* Offset: 0x23C PWM PDMA Control Register */
- __I uint32_t PDMACAP0_1; /* Offset: 0x240 PWM Capture Channel 01 PDMA Register */
- __I uint32_t PDMACAP2_3; /* Offset: 0x244 PWM Capture Channel 23 PDMA Register */
- __I uint32_t PDMACAP4_5; /* Offset: 0x248 PWM Capture Channel 45 PDMA Register */
- __I uint32_t RESERVE9[1];
- __IO uint32_t CAPIEN; /* Offset: 0x250 PWM Capture Interrupt Enable Register */
- __IO uint32_t CAPIF; /* Offset: 0x254 PWM Capture Interrupt Flag Register */
- __I uint32_t RESERVE10[43];
- __I uint32_t PBUF[6]; /* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer */
- __I uint32_t CMPBUF[6]; /* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer */
- __I uint32_t RESERVE11[3];
- __I uint32_t FTCBUF0_1; /* Offset: 0x340 PWM FTCMPDAT0_1 Buffer */
- __I uint32_t FTCBUF2_3; /* Offset: 0x344 PWM FTCMPDAT2_3 Buffer */
- __I uint32_t FTCBUF4_5; /* Offset: 0x348 PWM FTCMPDAT4_5 Buffer */
- __IO uint32_t FTCI; /* Offset: 0x34C PWM FTCMPDAT Indicator Register */
-
-} PWM_T;
-
-
-
-/**
- @addtogroup PWM_CONST PWM Bit Field Definition
- Constant Definitions for PWM Controller
-@{ */
-
-#define PWM_CTL0_CTRLDn_Pos (0) /*!< PWM_T::CTL0: CTRLDn Position */
-#define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) /*!< PWM_T::CTL0: CTRLDn Mask */
-
-#define PWM_CTL0_CTRLD0_Pos (0) /*!< PWM_T::CTL0: CTRLD0 Position */
-#define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) /*!< PWM_T::CTL0: CTRLD0 Mask */
-
-#define PWM_CTL0_CTRLD1_Pos (1) /*!< PWM_T::CTL0: CTRLD1 Position */
-#define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) /*!< PWM_T::CTL0: CTRLD1 Mask */
-
-#define PWM_CTL0_CTRLD2_Pos (2) /*!< PWM_T::CTL0: CTRLD2 Position */
-#define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) /*!< PWM_T::CTL0: CTRLD2 Mask */
-
-#define PWM_CTL0_CTRLD3_Pos (3) /*!< PWM_T::CTL0: CTRLD3 Position */
-#define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) /*!< PWM_T::CTL0: CTRLD3 Mask */
-
-#define PWM_CTL0_CTRLD4_Pos (4) /*!< PWM_T::CTL0: CTRLD4 Position */
-#define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) /*!< PWM_T::CTL0: CTRLD4 Mask */
-
-#define PWM_CTL0_CTRLD5_Pos (5) /*!< PWM_T::CTL0: CTRLD5 Position */
-#define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) /*!< PWM_T::CTL0: CTRLD5 Mask */
-
-#define PWM_CTL0_WINLDENn_Pos (8) /*!< PWM_T::CTL0: WINLDENn Position */
-#define PWM_CTL0_WINLDENn_Msk (0x3ful << PWM_CTL0_WINLDENn_Pos) /*!< PWM_T::CTL0: WINLDENn Mask */
-
-#define PWM_CTL0_WINLDEN0_Pos (8) /*!< PWM_T::CTL0: WINLDEN0 Position */
-#define PWM_CTL0_WINLDEN0_Msk (0x1ul << PWM_CTL0_WINLDEN0_Pos) /*!< PWM_T::CTL0: WINLDEN0 Mask */
-
-#define PWM_CTL0_WINLDEN1_Pos (9) /*!< PWM_T::CTL0: WINLDEN1 Position */
-#define PWM_CTL0_WINLDEN1_Msk (0x1ul << PWM_CTL0_WINLDEN1_Pos) /*!< PWM_T::CTL0: WINLDEN1 Mask */
-
-#define PWM_CTL0_WINLDEN2_Pos (10) /*!< PWM_T::CTL0: WINLDEN2 Position */
-#define PWM_CTL0_WINLDEN2_Msk (0x1ul << PWM_CTL0_WINLDEN2_Pos) /*!< PWM_T::CTL0: WINLDEN2 Mask */
-
-#define PWM_CTL0_WINLDEN3_Pos (11) /*!< PWM_T::CTL0: WINLDEN3 Position */
-#define PWM_CTL0_WINLDEN3_Msk (0x1ul << PWM_CTL0_WINLDEN3_Pos) /*!< PWM_T::CTL0: WINLDEN3 Mask */
-
-#define PWM_CTL0_WINLDEN4_Pos (12) /*!< PWM_T::CTL0: WINLDEN4 Position */
-#define PWM_CTL0_WINLDEN4_Msk (0x1ul << PWM_CTL0_WINLDEN4_Pos) /*!< PWM_T::CTL0: WINLDEN4 Mask */
-
-#define PWM_CTL0_WINLDEN5_Pos (13) /*!< PWM_T::CTL0: WINLDEN5 Position */
-#define PWM_CTL0_WINLDEN5_Msk (0x1ul << PWM_CTL0_WINLDEN5_Pos) /*!< PWM_T::CTL0: WINLDEN5 Mask */
-
-#define PWM_CTL0_IMMLDENn_Pos (16) /*!< PWM_T::CTL0: IMMLDENn Position */
-#define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) /*!< PWM_T::CTL0: IMMLDENn Mask */
-
-#define PWM_CTL0_IMMLDEN0_Pos (16) /*!< PWM_T::CTL0: IMMLDEN0 Position */
-#define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) /*!< PWM_T::CTL0: IMMLDEN0 Mask */
-
-#define PWM_CTL0_IMMLDEN1_Pos (17) /*!< PWM_T::CTL0: IMMLDEN1 Position */
-#define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) /*!< PWM_T::CTL0: IMMLDEN1 Mask */
-
-#define PWM_CTL0_IMMLDEN2_Pos (18) /*!< PWM_T::CTL0: IMMLDEN2 Position */
-#define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) /*!< PWM_T::CTL0: IMMLDEN2 Mask */
-
-#define PWM_CTL0_IMMLDEN3_Pos (19) /*!< PWM_T::CTL0: IMMLDEN3 Position */
-#define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) /*!< PWM_T::CTL0: IMMLDEN3 Mask */
-
-#define PWM_CTL0_IMMLDEN4_Pos (20) /*!< PWM_T::CTL0: IMMLDEN4 Position */
-#define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) /*!< PWM_T::CTL0: IMMLDEN4 Mask */
-
-#define PWM_CTL0_IMMLDEN5_Pos (21) /*!< PWM_T::CTL0: IMMLDEN5 Position */
-#define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) /*!< PWM_T::CTL0: IMMLDEN5 Mask */
-
-#define PWM_CTL0_GROUPEN_Pos (24) /*!< PWM_T::CTL0: GROUPEN Position */
-#define PWM_CTL0_GROUPEN_Msk (0x1ul << PWM_CTL0_GROUPEN_Pos) /*!< PWM_T::CTL0: GROUPEN Mask */
-
-#define PWM_CTL0_DBGHALT_Pos (30) /*!< PWM_T::CTL0: DBGHALT Position */
-#define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) /*!< PWM_T::CTL0: DBGHALT Mask */
-
-#define PWM_CTL0_DBGTRIOFF_Pos (31) /*!< PWM_T::CTL0: DBGTRIOFF Position */
-#define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) /*!< PWM_T::CTL0: DBGTRIOFF Mask */
-
-#define PWM_CTL1_CNTTYPEn_Pos (0) /*!< PWM_T::CTL1: CNTTYPEn Position */
-#define PWM_CTL1_CNTTYPEn_Msk (0xffful << PWM_CTL1_CNTTYPEn_Pos) /*!< PWM_T::CTL1: CNTTYPEn Mask */
-
-#define PWM_CTL1_CNTTYPE0_Pos (0) /*!< PWM_T::CTL1: CNTTYPE0 Position */
-#define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) /*!< PWM_T::CTL1: CNTTYPE0 Mask */
-
-#define PWM_CTL1_CNTTYPE1_Pos (2) /*!< PWM_T::CTL1: CNTTYPE1 Position */
-#define PWM_CTL1_CNTTYPE1_Msk (0x3ul << PWM_CTL1_CNTTYPE1_Pos) /*!< PWM_T::CTL1: CNTTYPE1 Mask */
-
-#define PWM_CTL1_CNTTYPE2_Pos (4) /*!< PWM_T::CTL1: CNTTYPE2 Position */
-#define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) /*!< PWM_T::CTL1: CNTTYPE2 Mask */
-
-#define PWM_CTL1_CNTTYPE3_Pos (6) /*!< PWM_T::CTL1: CNTTYPE3 Position */
-#define PWM_CTL1_CNTTYPE3_Msk (0x3ul << PWM_CTL1_CNTTYPE3_Pos) /*!< PWM_T::CTL1: CNTTYPE3 Mask */
-
-#define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */
-#define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */
-
-#define PWM_CTL1_CNTTYPE5_Pos (10) /*!< PWM_T::CTL1: CNTTYPE5 Position */
-#define PWM_CTL1_CNTTYPE5_Msk (0x3ul << PWM_CTL1_CNTTYPE5_Pos) /*!< PWM_T::CTL1: CNTTYPE5 Mask */
-
-#define PWM_CTL1_CNTMODEn_Pos (16) /*!< PWM_T::CTL1: CNTMODEn Position */
-#define PWM_CTL1_CNTMODEn_Msk (0x3ful << PWM_CTL1_CNTMODEn_Pos) /*!< PWM_T::CTL1: CNTMODEn Mask */
-
-#define PWM_CTL1_CNTMODE0_Pos (16) /*!< PWM_T::CTL1: CNTMODE0 Position */
-#define PWM_CTL1_CNTMODE0_Msk (0x1ul << PWM_CTL1_CNTMODE0_Pos) /*!< PWM_T::CTL1: CNTMODE0 Mask */
-
-#define PWM_CTL1_CNTMODE1_Pos (17) /*!< PWM_T::CTL1: CNTMODE1 Position */
-#define PWM_CTL1_CNTMODE1_Msk (0x1ul << PWM_CTL1_CNTMODE1_Pos) /*!< PWM_T::CTL1: CNTMODE1 Mask */
-
-#define PWM_CTL1_CNTMODE2_Pos (18) /*!< PWM_T::CTL1: CNTMODE2 Position */
-#define PWM_CTL1_CNTMODE2_Msk (0x1ul << PWM_CTL1_CNTMODE2_Pos) /*!< PWM_T::CTL1: CNTMODE2 Mask */
-
-#define PWM_CTL1_CNTMODE3_Pos (19) /*!< PWM_T::CTL1: CNTMODE3 Position */
-#define PWM_CTL1_CNTMODE3_Msk (0x1ul << PWM_CTL1_CNTMODE3_Pos) /*!< PWM_T::CTL1: CNTMODE3 Mask */
-
-#define PWM_CTL1_CNTMODE4_Pos (20) /*!< PWM_T::CTL1: CNTMODE4 Position */
-#define PWM_CTL1_CNTMODE4_Msk (0x1ul << PWM_CTL1_CNTMODE4_Pos) /*!< PWM_T::CTL1: CNTMODE4 Mask */
-
-#define PWM_CTL1_CNTMODE5_Pos (21) /*!< PWM_T::CTL1: CNTMODE5 Position */
-#define PWM_CTL1_CNTMODE5_Msk (0x1ul << PWM_CTL1_CNTMODE5_Pos) /*!< PWM_T::CTL1: CNTMODE5 Mask */
-
-#define PWM_CTL1_OUTMODEn_Pos (24) /*!< PWM_T::CTL1: OUTMODEn Position */
-#define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos) /*!< PWM_T::CTL1: OUTMODEn Mask */
-
-#define PWM_CTL1_OUTMODE0_Pos (24) /*!< PWM_T::CTL1: OUTMODE0 Position */
-#define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) /*!< PWM_T::CTL1: OUTMODE0 Mask */
-
-#define PWM_CTL1_OUTMODE2_Pos (25) /*!< PWM_T::CTL1: OUTMODE2 Position */
-#define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) /*!< PWM_T::CTL1: OUTMODE2 Mask */
-
-#define PWM_CTL1_OUTMODE4_Pos (26) /*!< PWM_T::CTL1: OUTMODE4 Position */
-#define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) /*!< PWM_T::CTL1: OUTMODE4 Mask */
-
-#define PWM_SYNC_PHSENn_Pos (0) /*!< PWM_T::SYNC: PHSENn Position */
-#define PWM_SYNC_PHSENn_Msk (0x7ul << PWM_SYNC_PHSENn_Pos) /*!< PWM_T::SYNC: PHSENn Mask */
-
-#define PWM_SYNC_PHSEN0_Pos (0) /*!< PWM_T::SYNC: PHSEN0 Position */
-#define PWM_SYNC_PHSEN0_Msk (0x1ul << PWM_SYNC_PHSEN0_Pos) /*!< PWM_T::SYNC: PHSEN0 Mask */
-
-#define PWM_SYNC_PHSEN2_Pos (1) /*!< PWM_T::SYNC: PHSEN2 Position */
-#define PWM_SYNC_PHSEN2_Msk (0x1ul << PWM_SYNC_PHSEN2_Pos) /*!< PWM_T::SYNC: PHSEN2 Mask */
-
-#define PWM_SYNC_PHSEN4_Pos (2) /*!< PWM_T::SYNC: PHSEN4 Position */
-#define PWM_SYNC_PHSEN4_Msk (0x1ul << PWM_SYNC_PHSEN4_Pos) /*!< PWM_T::SYNC: PHSEN4 Mask */
-
-#define PWM_SYNC_SINSRCn_Pos (8) /*!< PWM_T::SYNC: SINSRCn Position */
-#define PWM_SYNC_SINSRCn_Msk (0x3ful << PWM_SYNC_SINSRCn_Pos) /*!< PWM_T::SYNC: SINSRCn Mask */
-
-#define PWM_SYNC_SINSRC0_Pos (8) /*!< PWM_T::SYNC: SINSRC0 Position */
-#define PWM_SYNC_SINSRC0_Msk (0x3ul << PWM_SYNC_SINSRC0_Pos) /*!< PWM_T::SYNC: SINSRC0 Mask */
-
-#define PWM_SYNC_SINSRC2_Pos (10) /*!< PWM_T::SYNC: SINSRC2 Position */
-#define PWM_SYNC_SINSRC2_Msk (0x3ul << PWM_SYNC_SINSRC2_Pos) /*!< PWM_T::SYNC: SINSRC2 Mask */
-
-#define PWM_SYNC_SINSRC4_Pos (12) /*!< PWM_T::SYNC: SINSRC4 Position */
-#define PWM_SYNC_SINSRC4_Msk (0x3ul << PWM_SYNC_SINSRC4_Pos) /*!< PWM_T::SYNC: SINSRC4 Mask */
-
-#define PWM_SYNC_SNFLTEN_Pos (16) /*!< PWM_T::SYNC: SNFLTEN Position */
-#define PWM_SYNC_SNFLTEN_Msk (0x1ul << PWM_SYNC_SNFLTEN_Pos) /*!< PWM_T::SYNC: SNFLTEN Mask */
-
-#define PWM_SYNC_SFLTCSEL_Pos (17) /*!< PWM_T::SYNC: SFLTCSEL Position */
-#define PWM_SYNC_SFLTCSEL_Msk (0x7ul << PWM_SYNC_SFLTCSEL_Pos) /*!< PWM_T::SYNC: SFLTCSEL Mask */
-
-#define PWM_SYNC_SFLTCNT_Pos (20) /*!< PWM_T::SYNC: SFLTCNT Position */
-#define PWM_SYNC_SFLTCNT_Msk (0x7ul << PWM_SYNC_SFLTCNT_Pos) /*!< PWM_T::SYNC: SFLTCNT Mask */
-
-#define PWM_SYNC_SINPINV_Pos (23) /*!< PWM_T::SYNC: SINPINV Position */
-#define PWM_SYNC_SINPINV_Msk (0x1ul << PWM_SYNC_SINPINV_Pos) /*!< PWM_T::SYNC: SINPINV Mask */
-
-#define PWM_SYNC_PHSDIRn_Pos (24) /*!< PWM_T::SYNC: PHSDIRn Position */
-#define PWM_SYNC_PHSDIRn_Msk (0x7ul << PWM_SYNC_PHSDIRn_Pos) /*!< PWM_T::SYNC: PHSDIRn Mask */
-
-#define PWM_SYNC_PHSDIR0_Pos (24) /*!< PWM_T::SYNC: PHSDIR0 Position */
-#define PWM_SYNC_PHSDIR0_Msk (0x1ul << PWM_SYNC_PHSDIR0_Pos) /*!< PWM_T::SYNC: PHSDIR0 Mask */
-
-#define PWM_SYNC_PHSDIR2_Pos (25) /*!< PWM_T::SYNC: PHSDIR2 Position */
-#define PWM_SYNC_PHSDIR2_Msk (0x1ul << PWM_SYNC_PHSDIR2_Pos) /*!< PWM_T::SYNC: PHSDIR2 Mask */
-
-#define PWM_SYNC_PHSDIR4_Pos (26) /*!< PWM_T::SYNC: PHSDIR4 Position */
-#define PWM_SYNC_PHSDIR4_Msk (0x1ul << PWM_SYNC_PHSDIR4_Pos) /*!< PWM_T::SYNC: PHSDIR4 Mask */
-
-#define PWM_SWSYNC_SWSYNCn_Pos (0) /*!< PWM_T::SWSYNC: SWSYNCn Position */
-#define PWM_SWSYNC_SWSYNCn_Msk (0x7ul << PWM_SWSYNC_SWSYNCn_Pos) /*!< PWM_T::SWSYNC: SWSYNCn Mask */
-
-#define PWM_SWSYNC_SWSYNC0_Pos (0) /*!< PWM_T::SWSYNC: SWSYNC0 Position */
-#define PWM_SWSYNC_SWSYNC0_Msk (0x1ul << PWM_SWSYNC_SWSYNC0_Pos) /*!< PWM_T::SWSYNC: SWSYNC0 Mask */
-
-#define PWM_SWSYNC_SWSYNC2_Pos (1) /*!< PWM_T::SWSYNC: SWSYNC2 Position */
-#define PWM_SWSYNC_SWSYNC2_Msk (0x1ul << PWM_SWSYNC_SWSYNC2_Pos) /*!< PWM_T::SWSYNC: SWSYNC2 Mask */
-
-#define PWM_SWSYNC_SWSYNC4_Pos (2) /*!< PWM_T::SWSYNC: SWSYNC4 Position */
-#define PWM_SWSYNC_SWSYNC4_Msk (0x1ul << PWM_SWSYNC_SWSYNC4_Pos) /*!< PWM_T::SWSYNC: SWSYNC4 Mask */
-
-#define PWM_CLKSRC_ECLKSRC0_Pos (0) /*!< PWM_T::CLKSRC: ECLKSRC0 Position */
-#define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) /*!< PWM_T::CLKSRC: ECLKSRC0 Mask */
-
-#define PWM_CLKSRC_ECLKSRC2_Pos (8) /*!< PWM_T::CLKSRC: ECLKSRC2 Position */
-#define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) /*!< PWM_T::CLKSRC: ECLKSRC2 Mask */
-
-#define PWM_CLKSRC_ECLKSRC4_Pos (16) /*!< PWM_T::CLKSRC: ECLKSRC4 Position */
-#define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) /*!< PWM_T::CLKSRC: ECLKSRC4 Mask */
-
-#define PWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC0_1: CLKPSC Position */
-#define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) /*!< PWM_T::CLKPSC0_1: CLKPSC Mask */
-
-#define PWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC2_3: CLKPSC Position */
-#define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) /*!< PWM_T::CLKPSC2_3: CLKPSC Mask */
-
-#define PWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC4_5: CLKPSC Position */
-#define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) /*!< PWM_T::CLKPSC4_5: CLKPSC Mask */
-
-#define PWM_CNTEN_CNTENn_Pos (0) /*!< PWM_T::CNTEN: CNTENn Position */
-#define PWM_CNTEN_CNTENn_Msk (0x3ful << PWM_CNTEN_CNTENn_Pos) /*!< PWM_T::CNTEN: CNTENn Mask */
-
-#define PWM_CNTEN_CNTEN0_Pos (0) /*!< PWM_T::CNTEN: CNTEN0 Position */
-#define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) /*!< PWM_T::CNTEN: CNTEN0 Mask */
-
-#define PWM_CNTEN_CNTEN1_Pos (1) /*!< PWM_T::CNTEN: CNTEN1 Position */
-#define PWM_CNTEN_CNTEN1_Msk (0x1ul << PWM_CNTEN_CNTEN1_Pos) /*!< PWM_T::CNTEN: CNTEN1 Mask */
-
-#define PWM_CNTEN_CNTEN2_Pos (2) /*!< PWM_T::CNTEN: CNTEN2 Position */
-#define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) /*!< PWM_T::CNTEN: CNTEN2 Mask */
-
-#define PWM_CNTEN_CNTEN3_Pos (3) /*!< PWM_T::CNTEN: CNTEN3 Position */
-#define PWM_CNTEN_CNTEN3_Msk (0x1ul << PWM_CNTEN_CNTEN3_Pos) /*!< PWM_T::CNTEN: CNTEN3 Mask */
-
-#define PWM_CNTEN_CNTEN4_Pos (4) /*!< PWM_T::CNTEN: CNTEN4 Position */
-#define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) /*!< PWM_T::CNTEN: CNTEN4 Mask */
-
-#define PWM_CNTEN_CNTEN5_Pos (5) /*!< PWM_T::CNTEN: CNTEN5 Position */
-#define PWM_CNTEN_CNTEN5_Msk (0x1ul << PWM_CNTEN_CNTEN5_Pos) /*!< PWM_T::CNTEN: CNTEN5 Mask */
-
-#define PWM_CNTCLR_CNTCLRn_Pos (0) /*!< PWM_T::CNTCLR: CNTCLRn Position */
-#define PWM_CNTCLR_CNTCLRn_Msk (0x3ful << PWM_CNTCLR_CNTCLRn_Pos) /*!< PWM_T::CNTCLR: CNTCLRn Mask */
-
-#define PWM_CNTCLR_CNTCLR0_Pos (0) /*!< PWM_T::CNTCLR: CNTCLR0 Position */
-#define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) /*!< PWM_T::CNTCLR: CNTCLR0 Mask */
-
-#define PWM_CNTCLR_CNTCLR1_Pos (1) /*!< PWM_T::CNTCLR: CNTCLR1 Position */
-#define PWM_CNTCLR_CNTCLR1_Msk (0x1ul << PWM_CNTCLR_CNTCLR1_Pos) /*!< PWM_T::CNTCLR: CNTCLR1 Mask */
-
-#define PWM_CNTCLR_CNTCLR2_Pos (2) /*!< PWM_T::CNTCLR: CNTCLR2 Position */
-#define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) /*!< PWM_T::CNTCLR: CNTCLR2 Mask */
-
-#define PWM_CNTCLR_CNTCLR3_Pos (3) /*!< PWM_T::CNTCLR: CNTCLR3 Position */
-#define PWM_CNTCLR_CNTCLR3_Msk (0x1ul << PWM_CNTCLR_CNTCLR3_Pos) /*!< PWM_T::CNTCLR: CNTCLR3 Mask */
-
-#define PWM_CNTCLR_CNTCLR4_Pos (4) /*!< PWM_T::CNTCLR: CNTCLR4 Position */
-#define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) /*!< PWM_T::CNTCLR: CNTCLR4 Mask */
-
-#define PWM_CNTCLR_CNTCLR5_Pos (5) /*!< PWM_T::CNTCLR: CNTCLR5 Position */
-#define PWM_CNTCLR_CNTCLR5_Msk (0x1ul << PWM_CNTCLR_CNTCLR5_Pos) /*!< PWM_T::CNTCLR: CNTCLR5 Mask */
-
-#define PWM_LOAD_LOADn_Pos (0) /*!< PWM_T::LOAD: LOADn Position */
-#define PWM_LOAD_LOADn_Msk (0x3ful << PWM_LOAD_LOADn_Pos) /*!< PWM_T::LOAD: LOADn Mask */
-
-#define PWM_LOAD_LOAD0_Pos (0) /*!< PWM_T::LOAD: LOAD0 Position */
-#define PWM_LOAD_LOAD0_Msk (0x1ul << PWM_LOAD_LOAD0_Pos) /*!< PWM_T::LOAD: LOAD0 Mask */
-
-#define PWM_LOAD_LOAD1_Pos (1) /*!< PWM_T::LOAD: LOAD1 Position */
-#define PWM_LOAD_LOAD1_Msk (0x1ul << PWM_LOAD_LOAD1_Pos) /*!< PWM_T::LOAD: LOAD1 Mask */
-
-#define PWM_LOAD_LOAD2_Pos (2) /*!< PWM_T::LOAD: LOAD2 Position */
-#define PWM_LOAD_LOAD2_Msk (0x1ul << PWM_LOAD_LOAD2_Pos) /*!< PWM_T::LOAD: LOAD2 Mask */
-
-#define PWM_LOAD_LOAD3_Pos (3) /*!< PWM_T::LOAD: LOAD3 Position */
-#define PWM_LOAD_LOAD3_Msk (0x1ul << PWM_LOAD_LOAD3_Pos) /*!< PWM_T::LOAD: LOAD3 Mask */
-
-#define PWM_LOAD_LOAD4_Pos (4) /*!< PWM_T::LOAD: LOAD4 Position */
-#define PWM_LOAD_LOAD4_Msk (0x1ul << PWM_LOAD_LOAD4_Pos) /*!< PWM_T::LOAD: LOAD4 Mask */
-
-#define PWM_LOAD_LOAD5_Pos (5) /*!< PWM_T::LOAD: LOAD5 Position */
-#define PWM_LOAD_LOAD5_Msk (0x1ul << PWM_LOAD_LOAD5_Pos) /*!< PWM_T::LOAD: LOAD5 Mask */
-
-#define PWM_PERIOD_PERIOD_Pos (0) /*!< PWM_T::PERIOD: PERIOD Position */
-#define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos) /*!< PWM_T::PERIOD: PERIOD Mask */
-
-#define PWM_CMPDAT_CMP_Pos (0) /*!< PWM_T::CMPDAT: CMP Position */
-#define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos) /*!< PWM_T::CMPDAT: CMP Mask */
-
-#define PWM_DTCTL0_1_DTCNT_Pos (0) /*!< PWM_T::DTCTL0_1: DTCNT Position */
-#define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) /*!< PWM_T::DTCTL0_1: DTCNT Mask */
-
-#define PWM_DTCTL0_1_DTEN_Pos (16) /*!< PWM_T::DTCTL0_1: DTEN Position */
-#define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) /*!< PWM_T::DTCTL0_1: DTEN Mask */
-
-#define PWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL0_1: DTCKSEL Position */
-#define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) /*!< PWM_T::DTCTL0_1: DTCKSEL Mask */
-
-#define PWM_DTCTL2_3_DTCNT_Pos (0) /*!< PWM_T::DTCTL2_3: DTCNT Position */
-#define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) /*!< PWM_T::DTCTL2_3: DTCNT Mask */
-
-#define PWM_DTCTL2_3_DTEN_Pos (16) /*!< PWM_T::DTCTL2_3: DTEN Position */
-#define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) /*!< PWM_T::DTCTL2_3: DTEN Mask */
-
-#define PWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL2_3: DTCKSEL Position */
-#define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) /*!< PWM_T::DTCTL2_3: DTCKSEL Mask */
-
-#define PWM_DTCTL4_5_DTCNT_Pos (0) /*!< PWM_T::DTCTL4_5: DTCNT Position */
-#define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) /*!< PWM_T::DTCTL4_5: DTCNT Mask */
-
-#define PWM_DTCTL4_5_DTEN_Pos (16) /*!< PWM_T::DTCTL4_5: DTEN Position */
-#define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) /*!< PWM_T::DTCTL4_5: DTEN Mask */
-
-#define PWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL4_5: DTCKSEL Position */
-#define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) /*!< PWM_T::DTCTL4_5: DTCKSEL Mask */
-
-#define PWM_PHS0_1_PHS_Pos (0) /*!< PWM_T::PHS0_1: PHS Position */
-#define PWM_PHS0_1_PHS_Msk (0xfffful << PWM_PHS0_1_PHS_Pos) /*!< PWM_T::PHS0_1: PHS Mask */
-
-#define PWM_PHS2_3_PHS_Pos (0) /*!< PWM_T::PHS2_3: PHS Position */
-#define PWM_PHS2_3_PHS_Msk (0xfffful << PWM_PHS2_3_PHS_Pos) /*!< PWM_T::PHS2_3: PHS Mask */
-
-#define PWM_PHS4_5_PHS_Pos (0) /*!< PWM_T::PHS4_5: PHS Position */
-#define PWM_PHS4_5_PHS_Msk (0xfffful << PWM_PHS4_5_PHS_Pos) /*!< PWM_T::PHS4_5: PHS Mask */
-
-#define PWM_CNT_CNT_Pos (0) /*!< PWM_T::CNT: CNT Position */
-#define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) /*!< PWM_T::CNT: CNT Mask */
-
-#define PWM_CNT_DIRF_Pos (16) /*!< PWM_T::CNT: DIRF Position */
-#define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) /*!< PWM_T::CNT: DIRF Mask */
-
-#define PWM_WGCTL0_ZPCTLn_Pos (0) /*!< PWM_T::WGCTL0: ZPCTLn Position */
-#define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos) /*!< PWM_T::WGCTL0: ZPCTLn Mask */
-
-#define PWM_WGCTL0_ZPCTL0_Pos (0) /*!< PWM_T::WGCTL0: ZPCTL0 Position */
-#define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) /*!< PWM_T::WGCTL0: ZPCTL0 Mask */
-
-#define PWM_WGCTL0_ZPCTL1_Pos (2) /*!< PWM_T::WGCTL0: ZPCTL1 Position */
-#define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) /*!< PWM_T::WGCTL0: ZPCTL1 Mask */
-
-#define PWM_WGCTL0_ZPCTL2_Pos (4) /*!< PWM_T::WGCTL0: ZPCTL2 Position */
-#define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) /*!< PWM_T::WGCTL0: ZPCTL2 Mask */
-
-#define PWM_WGCTL0_ZPCTL3_Pos (6) /*!< PWM_T::WGCTL0: ZPCTL3 Position */
-#define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) /*!< PWM_T::WGCTL0: ZPCTL3 Mask */
-
-#define PWM_WGCTL0_ZPCTL4_Pos (8) /*!< PWM_T::WGCTL0: ZPCTL4 Position */
-#define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) /*!< PWM_T::WGCTL0: ZPCTL4 Mask */
-
-#define PWM_WGCTL0_ZPCTL5_Pos (10) /*!< PWM_T::WGCTL0: ZPCTL5 Position */
-#define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) /*!< PWM_T::WGCTL0: ZPCTL5 Mask */
-
-#define PWM_WGCTL0_PRDPCTLn_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTLn Position */
-#define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos) /*!< PWM_T::WGCTL0: PRDPCTLn Mask */
-
-#define PWM_WGCTL0_PRDPCTL0_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTL0 Position */
-#define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) /*!< PWM_T::WGCTL0: PRDPCTL0 Mask */
-
-#define PWM_WGCTL0_PRDPCTL1_Pos (18) /*!< PWM_T::WGCTL0: PRDPCTL1 Position */
-#define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) /*!< PWM_T::WGCTL0: PRDPCTL1 Mask */
-
-#define PWM_WGCTL0_PRDPCTL2_Pos (20) /*!< PWM_T::WGCTL0: PRDPCTL2 Position */
-#define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) /*!< PWM_T::WGCTL0: PRDPCTL2 Mask */
-
-#define PWM_WGCTL0_PRDPCTL3_Pos (22) /*!< PWM_T::WGCTL0: PRDPCTL3 Position */
-#define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) /*!< PWM_T::WGCTL0: PRDPCTL3 Mask */
-
-#define PWM_WGCTL0_PRDPCTL4_Pos (24) /*!< PWM_T::WGCTL0: PRDPCTL4 Position */
-#define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) /*!< PWM_T::WGCTL0: PRDPCTL4 Mask */
-
-#define PWM_WGCTL0_PRDPCTL5_Pos (26) /*!< PWM_T::WGCTL0: PRDPCTL5 Position */
-#define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) /*!< PWM_T::WGCTL0: PRDPCTL5 Mask */
-
-#define PWM_WGCTL1_CMPUCTLn_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTLn Position */
-#define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) /*!< PWM_T::WGCTL1: CMPUCTLn Mask */
-
-#define PWM_WGCTL1_CMPUCTL0_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTL0 Position */
-#define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) /*!< PWM_T::WGCTL1: CMPUCTL0 Mask */
-
-#define PWM_WGCTL1_CMPUCTL1_Pos (2) /*!< PWM_T::WGCTL1: CMPUCTL1 Position */
-#define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) /*!< PWM_T::WGCTL1: CMPUCTL1 Mask */
-
-#define PWM_WGCTL1_CMPUCTL2_Pos (4) /*!< PWM_T::WGCTL1: CMPUCTL2 Position */
-#define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) /*!< PWM_T::WGCTL1: CMPUCTL2 Mask */
-
-#define PWM_WGCTL1_CMPUCTL3_Pos (6) /*!< PWM_T::WGCTL1: CMPUCTL3 Position */
-#define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) /*!< PWM_T::WGCTL1: CMPUCTL3 Mask */
-
-#define PWM_WGCTL1_CMPUCTL4_Pos (8) /*!< PWM_T::WGCTL1: CMPUCTL4 Position */
-#define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) /*!< PWM_T::WGCTL1: CMPUCTL4 Mask */
-
-#define PWM_WGCTL1_CMPUCTL5_Pos (10) /*!< PWM_T::WGCTL1: CMPUCTL5 Position */
-#define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) /*!< PWM_T::WGCTL1: CMPUCTL5 Mask */
-
-#define PWM_WGCTL1_CMPDCTLn_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTLn Position */
-#define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos) /*!< PWM_T::WGCTL1: CMPDCTLn Mask */
-
-#define PWM_WGCTL1_CMPDCTL0_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTL0 Position */
-#define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) /*!< PWM_T::WGCTL1: CMPDCTL0 Mask */
-
-#define PWM_WGCTL1_CMPDCTL1_Pos (18) /*!< PWM_T::WGCTL1: CMPDCTL1 Position */
-#define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) /*!< PWM_T::WGCTL1: CMPDCTL1 Mask */
-
-#define PWM_WGCTL1_CMPDCTL2_Pos (20) /*!< PWM_T::WGCTL1: CMPDCTL2 Position */
-#define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) /*!< PWM_T::WGCTL1: CMPDCTL2 Mask */
-
-#define PWM_WGCTL1_CMPDCTL3_Pos (22) /*!< PWM_T::WGCTL1: CMPDCTL3 Position */
-#define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) /*!< PWM_T::WGCTL1: CMPDCTL3 Mask */
-
-#define PWM_WGCTL1_CMPDCTL4_Pos (24) /*!< PWM_T::WGCTL1: CMPDCTL4 Position */
-#define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) /*!< PWM_T::WGCTL1: CMPDCTL4 Mask */
-
-#define PWM_WGCTL1_CMPDCTL5_Pos (26) /*!< PWM_T::WGCTL1: CMPDCTL5 Position */
-#define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) /*!< PWM_T::WGCTL1: CMPDCTL5 Mask */
-
-#define PWM_MSKEN_MSKENn_Pos (0) /*!< PWM_T::MSKEN: MSKENn Position */
-#define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos) /*!< PWM_T::MSKEN: MSKENn Mask */
-
-#define PWM_MSKEN_MSKEN0_Pos (0) /*!< PWM_T::MSKEN: MSKEN0 Position */
-#define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) /*!< PWM_T::MSKEN: MSKEN0 Mask */
-
-#define PWM_MSKEN_MSKEN1_Pos (1) /*!< PWM_T::MSKEN: MSKEN1 Position */
-#define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) /*!< PWM_T::MSKEN: MSKEN1 Mask */
-
-#define PWM_MSKEN_MSKEN2_Pos (2) /*!< PWM_T::MSKEN: MSKEN2 Position */
-#define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) /*!< PWM_T::MSKEN: MSKEN2 Mask */
-
-#define PWM_MSKEN_MSKEN3_Pos (3) /*!< PWM_T::MSKEN: MSKEN3 Position */
-#define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) /*!< PWM_T::MSKEN: MSKEN3 Mask */
-
-#define PWM_MSKEN_MSKEN4_Pos (4) /*!< PWM_T::MSKEN: MSKEN4 Position */
-#define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) /*!< PWM_T::MSKEN: MSKEN4 Mask */
-
-#define PWM_MSKEN_MSKEN5_Pos (5) /*!< PWM_T::MSKEN: MSKEN5 Position */
-#define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) /*!< PWM_T::MSKEN: MSKEN5 Mask */
-
-#define PWM_MSK_MSKDATn_Pos (0) /*!< PWM_T::MSK: MSKDATn Position */
-#define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos) /*!< PWM_T::MSK: MSKDATn Mask */
-
-#define PWM_MSK_MSKDAT0_Pos (0) /*!< PWM_T::MSK: MSKDAT0 Position */
-#define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) /*!< PWM_T::MSK: MSKDAT0 Mask */
-
-#define PWM_MSK_MSKDAT1_Pos (1) /*!< PWM_T::MSK: MSKDAT1 Position */
-#define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) /*!< PWM_T::MSK: MSKDAT1 Mask */
-
-#define PWM_MSK_MSKDAT2_Pos (2) /*!< PWM_T::MSK: MSKDAT2 Position */
-#define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) /*!< PWM_T::MSK: MSKDAT2 Mask */
-
-#define PWM_MSK_MSKDAT3_Pos (3) /*!< PWM_T::MSK: MSKDAT3 Position */
-#define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) /*!< PWM_T::MSK: MSKDAT3 Mask */
-
-#define PWM_MSK_MSKDAT4_Pos (4) /*!< PWM_T::MSK: MSKDAT4 Position */
-#define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) /*!< PWM_T::MSK: MSKDAT4 Mask */
-
-#define PWM_MSK_MSKDAT5_Pos (5) /*!< PWM_T::MSK: MSKDAT5 Position */
-#define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) /*!< PWM_T::MSK: MSKDAT5 Mask */
-
-#define PWM_BNF_BRK0NFEN_Pos (0) /*!< PWM_T::BNF: BRK0NFEN Position */
-#define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos) /*!< PWM_T::BNF: BRK0NFEN Mask */
-
-#define PWM_BNF_BRK0NFSEL_Pos (1) /*!< PWM_T::BNF: BRK0NFSEL Position */
-#define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos) /*!< PWM_T::BNF: BRK0NFSEL Mask */
-
-#define PWM_BNF_BRK0FCNT_Pos (4) /*!< PWM_T::BNF: BRK0FCNT Position */
-#define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos) /*!< PWM_T::BNF: BRK0FCNT Mask */
-
-#define PWM_BNF_BRK0PINV_Pos (7) /*!< PWM_T::BNF: BRK0PINV Position */
-#define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) /*!< PWM_T::BNF: BRK0PINV Mask */
-
-#define PWM_BNF_BRK1NFEN_Pos (8) /*!< PWM_T::BNF: BRK1NFEN Position */
-#define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos) /*!< PWM_T::BNF: BRK1NFEN Mask */
-
-#define PWM_BNF_BRK1NFSEL_Pos (9) /*!< PWM_T::BNF: BRK1NFSEL Position */
-#define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos) /*!< PWM_T::BNF: BRK1NFSEL Mask */
-
-#define PWM_BNF_BRK1FCNT_Pos (12) /*!< PWM_T::BNF: BRK1FCNT Position */
-#define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) /*!< PWM_T::BNF: BRK1FCNT Mask */
-
-#define PWM_BNF_BRK1PINV_Pos (15) /*!< PWM_T::BNF: BRK1PINV Position */
-#define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) /*!< PWM_T::BNF: BRK1PINV Mask */
-
-#define PWM_BNF_BK0SRC_Pos (16) /*!< PWM_T::BNF: BK0SRC Position */
-#define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) /*!< PWM_T::BNF: BK0SRC Mask */
-
-#define PWM_BNF_BK1SRC_Pos (24) /*!< PWM_T::BNF: BK1SRC Position */
-#define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) /*!< PWM_T::BNF: BK1SRC Mask */
-
-#define PWM_FAILBRK_CSSBRKEN_Pos (0) /*!< PWM_T::FAILBRK: CSSBRKEN Position */
-#define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) /*!< PWM_T::FAILBRK: CSSBRKEN Mask */
-
-#define PWM_FAILBRK_BODBRKEN_Pos (1) /*!< PWM_T::FAILBRK: BODBRKEN Position */
-#define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) /*!< PWM_T::FAILBRK: BODBRKEN Mask */
-
-#define PWM_FAILBRK_RAMBRKEN_Pos (2) /*!< PWM_T::FAILBRK: RAMBRKEN Position */
-#define PWM_FAILBRK_RAMBRKEN_Msk (0x1ul << PWM_FAILBRK_RAMBRKEN_Pos) /*!< PWM_T::FAILBRK: RAMBRKEN Mask */
-
-#define PWM_FAILBRK_CORBRKEN_Pos (3) /*!< PWM_T::FAILBRK: CORBRKEN Position */
-#define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) /*!< PWM_T::FAILBRK: CORBRKEN Mask */
-
-#define PWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position */
-#define PWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask */
-
-#define PWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position */
-#define PWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask */
-
-#define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position */
-#define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask */
-
-#define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position */
-#define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask */
-
-#define PWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL0_1: SYSEBEN Position */
-#define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask */
-
-#define PWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position */
-#define PWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask */
-
-#define PWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position */
-#define PWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask */
-
-#define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position */
-#define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask */
-
-#define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position */
-#define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask */
-
-#define PWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL0_1: SYSLBEN Position */
-#define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask */
-
-#define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position */
-#define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask */
-
-#define PWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL0_1: BRKAODD Position */
-#define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) /*!< PWM_T::BRKCTL0_1: BRKAODD Mask */
-
-#define PWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position */
-#define PWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask */
-
-#define PWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position */
-#define PWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask */
-
-#define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position */
-#define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask */
-
-#define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position */
-#define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask */
-
-#define PWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL2_3: SYSEBEN Position */
-#define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask */
-
-#define PWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position */
-#define PWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask */
-
-#define PWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position */
-#define PWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask */
-
-#define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position */
-#define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask */
-
-#define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position */
-#define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask */
-
-#define PWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL2_3: SYSLBEN Position */
-#define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask */
-
-#define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position */
-#define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask */
-
-#define PWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL2_3: BRKAODD Position */
-#define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) /*!< PWM_T::BRKCTL2_3: BRKAODD Mask */
-
-#define PWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position */
-#define PWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask */
-
-#define PWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position */
-#define PWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask */
-
-#define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position */
-#define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask */
-
-#define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position */
-#define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask */
-
-#define PWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL4_5: SYSEBEN Position */
-#define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask */
-
-#define PWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position */
-#define PWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask */
-
-#define PWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position */
-#define PWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask */
-
-#define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position */
-#define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask */
-
-#define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position */
-#define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask */
-
-#define PWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL4_5: SYSLBEN Position */
-#define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask */
-
-#define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position */
-#define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask */
-
-#define PWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL4_5: BRKAODD Position */
-#define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) /*!< PWM_T::BRKCTL4_5: BRKAODD Mask */
-
-#define PWM_POLCTL_PINVn_Pos (0) /*!< PWM_T::POLCTL: PINVn Position */
-#define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) /*!< PWM_T::POLCTL: PINVn Mask */
-
-#define PWM_POLCTL_PINV0_Pos (0) /*!< PWM_T::POLCTL: PINV0 Position */
-#define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) /*!< PWM_T::POLCTL: PINV0 Mask */
-
-#define PWM_POLCTL_PINV1_Pos (1) /*!< PWM_T::POLCTL: PINV1 Position */
-#define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) /*!< PWM_T::POLCTL: PINV1 Mask */
-
-#define PWM_POLCTL_PINV2_Pos (2) /*!< PWM_T::POLCTL: PINV2 Position */
-#define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) /*!< PWM_T::POLCTL: PINV2 Mask */
-
-#define PWM_POLCTL_PINV3_Pos (3) /*!< PWM_T::POLCTL: PINV3 Position */
-#define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) /*!< PWM_T::POLCTL: PINV3 Mask */
-
-#define PWM_POLCTL_PINV4_Pos (4) /*!< PWM_T::POLCTL: PINV4 Position */
-#define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) /*!< PWM_T::POLCTL: PINV4 Mask */
-
-#define PWM_POLCTL_PINV5_Pos (5) /*!< PWM_T::POLCTL: PINV5 Position */
-#define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) /*!< PWM_T::POLCTL: PINV5 Mask */
-
-#define PWM_POEN_POENn_Pos (0) /*!< PWM_T::POEN: POENn Position */
-#define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) /*!< PWM_T::POEN: POENn Mask */
-
-#define PWM_POEN_POEN0_Pos (0) /*!< PWM_T::POEN: POEN0 Position */
-#define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) /*!< PWM_T::POEN: POEN0 Mask */
-
-#define PWM_POEN_POEN1_Pos (1) /*!< PWM_T::POEN: POEN1 Position */
-#define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) /*!< PWM_T::POEN: POEN1 Mask */
-
-#define PWM_POEN_POEN2_Pos (2) /*!< PWM_T::POEN: POEN2 Position */
-#define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) /*!< PWM_T::POEN: POEN2 Mask */
-
-#define PWM_POEN_POEN3_Pos (3) /*!< PWM_T::POEN: POEN3 Position */
-#define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) /*!< PWM_T::POEN: POEN3 Mask */
-
-#define PWM_POEN_POEN4_Pos (4) /*!< PWM_T::POEN: POEN4 Position */
-#define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) /*!< PWM_T::POEN: POEN4 Mask */
-
-#define PWM_POEN_POEN5_Pos (5) /*!< PWM_T::POEN: POEN5 Position */
-#define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) /*!< PWM_T::POEN: POEN5 Mask */
-
-#define PWM_SWBRK_BRKETRGn_Pos (0) /*!< PWM_T::SWBRK: BRKETRGn Position */
-#define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) /*!< PWM_T::SWBRK: BRKETRGn Mask */
-
-#define PWM_SWBRK_BRKETRG0_Pos (0) /*!< PWM_T::SWBRK: BRKETRG0 Position */
-#define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) /*!< PWM_T::SWBRK: BRKETRG0 Mask */
-
-#define PWM_SWBRK_BRKETRG2_Pos (1) /*!< PWM_T::SWBRK: BRKETRG2 Position */
-#define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) /*!< PWM_T::SWBRK: BRKETRG2 Mask */
-
-#define PWM_SWBRK_BRKETRG4_Pos (2) /*!< PWM_T::SWBRK: BRKETRG4 Position */
-#define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) /*!< PWM_T::SWBRK: BRKETRG4 Mask */
-
-#define PWM_SWBRK_BRKLTRGn_Pos (8) /*!< PWM_T::SWBRK: BRKLTRGn Position */
-#define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) /*!< PWM_T::SWBRK: BRKLTRGn Mask */
-
-#define PWM_SWBRK_BRKLTRG0_Pos (8) /*!< PWM_T::SWBRK: BRKLTRG0 Position */
-#define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) /*!< PWM_T::SWBRK: BRKLTRG0 Mask */
-
-#define PWM_SWBRK_BRKLTRG2_Pos (9) /*!< PWM_T::SWBRK: BRKLTRG2 Position */
-#define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) /*!< PWM_T::SWBRK: BRKLTRG2 Mask */
-
-#define PWM_SWBRK_BRKLTRG4_Pos (10) /*!< PWM_T::SWBRK: BRKLTRG4 Position */
-#define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) /*!< PWM_T::SWBRK: BRKLTRG4 Mask */
-
-#define PWM_INTEN0_ZIENn_Pos (0) /*!< PWM_T::INTEN0: ZIENn Position */
-#define PWM_INTEN0_ZIENn_Msk (0x3ful << PWM_INTEN0_ZIENn_Pos) /*!< PWM_T::INTEN0: ZIENn Mask */
-
-#define PWM_INTEN0_ZIEN0_Pos (0) /*!< PWM_T::INTEN0: ZIEN0 Position */
-#define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) /*!< PWM_T::INTEN0: ZIEN0 Mask */
-
-#define PWM_INTEN0_ZIEN1_Pos (1) /*!< PWM_T::INTEN0: ZIEN1 Position */
-#define PWM_INTEN0_ZIEN1_Msk (0x1ul << PWM_INTEN0_ZIEN1_Pos) /*!< PWM_T::INTEN0: ZIEN1 Mask */
-
-#define PWM_INTEN0_ZIEN2_Pos (2) /*!< PWM_T::INTEN0: ZIEN2 Position */
-#define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) /*!< PWM_T::INTEN0: ZIEN2 Mask */
-
-#define PWM_INTEN0_ZIEN3_Pos (3) /*!< PWM_T::INTEN0: ZIEN3 Position */
-#define PWM_INTEN0_ZIEN3_Msk (0x1ul << PWM_INTEN0_ZIEN3_Pos) /*!< PWM_T::INTEN0: ZIEN3 Mask */
-
-#define PWM_INTEN0_ZIEN4_Pos (4) /*!< PWM_T::INTEN0: ZIEN4 Position */
-#define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) /*!< PWM_T::INTEN0: ZIEN4 Mask */
-
-#define PWM_INTEN0_ZIEN5_Pos (5) /*!< PWM_T::INTEN0: ZIEN5 Position */
-#define PWM_INTEN0_ZIEN5_Msk (0x1ul << PWM_INTEN0_ZIEN5_Pos) /*!< PWM_T::INTEN0: ZIEN5 Mask */
-
-#define PWM_INTEN0_IFAIEN0_1_Pos (7) /*!< PWM_T::INTEN0: IFAIEN0_1 Position */
-#define PWM_INTEN0_IFAIEN0_1_Msk (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos) /*!< PWM_T::INTEN0: IFAIEN0_1 Mask */
-
-#define PWM_INTEN0_PIENn_Pos (8) /*!< PWM_T::INTEN0: PIENn Position */
-#define PWM_INTEN0_PIENn_Msk (0x3ful << PWM_INTEN0_PIENn_Pos) /*!< PWM_T::INTEN0: PIENn Mask */
-
-#define PWM_INTEN0_PIEN0_Pos (8) /*!< PWM_T::INTEN0: PIEN0 Position */
-#define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) /*!< PWM_T::INTEN0: PIEN0 Mask */
-
-#define PWM_INTEN0_PIEN1_Pos (9) /*!< PWM_T::INTEN0: PIEN1 Position */
-#define PWM_INTEN0_PIEN1_Msk (0x1ul << PWM_INTEN0_PIEN1_Pos) /*!< PWM_T::INTEN0: PIEN1 Mask */
-
-#define PWM_INTEN0_PIEN2_Pos (10) /*!< PWM_T::INTEN0: PIEN2 Position */
-#define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) /*!< PWM_T::INTEN0: PIEN2 Mask */
-
-#define PWM_INTEN0_PIEN3_Pos (11) /*!< PWM_T::INTEN0: PIEN3 Position */
-#define PWM_INTEN0_PIEN3_Msk (0x1ul << PWM_INTEN0_PIEN3_Pos) /*!< PWM_T::INTEN0: PIEN3 Mask */
-
-#define PWM_INTEN0_PIEN4_Pos (12) /*!< PWM_T::INTEN0: PIEN4 Position */
-#define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) /*!< PWM_T::INTEN0: PIEN4 Mask */
-
-#define PWM_INTEN0_PIEN5_Pos (13) /*!< PWM_T::INTEN0: PIEN5 Position */
-#define PWM_INTEN0_PIEN5_Msk (0x1ul << PWM_INTEN0_PIEN5_Pos) /*!< PWM_T::INTEN0: PIEN5 Mask */
-
-#define PWM_INTEN0_IFAIEN2_3_Pos (15) /*!< PWM_T::INTEN0: IFAIEN2_3 Position */
-#define PWM_INTEN0_IFAIEN2_3_Msk (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos) /*!< PWM_T::INTEN0: IFAIEN2_3 Mask */
-
-#define PWM_INTEN0_CMPUIENn_Pos (16) /*!< PWM_T::INTEN0: CMPUIENn Position */
-#define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) /*!< PWM_T::INTEN0: CMPUIENn Mask */
-
-#define PWM_INTEN0_CMPUIEN0_Pos (16) /*!< PWM_T::INTEN0: CMPUIEN0 Position */
-#define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) /*!< PWM_T::INTEN0: CMPUIEN0 Mask */
-
-#define PWM_INTEN0_CMPUIEN1_Pos (17) /*!< PWM_T::INTEN0: CMPUIEN1 Position */
-#define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) /*!< PWM_T::INTEN0: CMPUIEN1 Mask */
-
-#define PWM_INTEN0_CMPUIEN2_Pos (18) /*!< PWM_T::INTEN0: CMPUIEN2 Position */
-#define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) /*!< PWM_T::INTEN0: CMPUIEN2 Mask */
-
-#define PWM_INTEN0_CMPUIEN3_Pos (19) /*!< PWM_T::INTEN0: CMPUIEN3 Position */
-#define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) /*!< PWM_T::INTEN0: CMPUIEN3 Mask */
-
-#define PWM_INTEN0_CMPUIEN4_Pos (20) /*!< PWM_T::INTEN0: CMPUIEN4 Position */
-#define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) /*!< PWM_T::INTEN0: CMPUIEN4 Mask */
-
-#define PWM_INTEN0_CMPUIEN5_Pos (21) /*!< PWM_T::INTEN0: CMPUIEN5 Position */
-#define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) /*!< PWM_T::INTEN0: CMPUIEN5 Mask */
-
-#define PWM_INTEN0_IFAIEN4_5_Pos (23) /*!< PWM_T::INTEN0: IFAIEN4_5 Position */
-#define PWM_INTEN0_IFAIEN4_5_Msk (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos) /*!< PWM_T::INTEN0: IFAIEN4_5 Mask */
-
-#define PWM_INTEN0_CMPDIENn_Pos (24) /*!< PWM_T::INTEN0: CMPDIENn Position */
-#define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) /*!< PWM_T::INTEN0: CMPDIENn Mask */
-
-#define PWM_INTEN0_CMPDIEN0_Pos (24) /*!< PWM_T::INTEN0: CMPDIEN0 Position */
-#define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) /*!< PWM_T::INTEN0: CMPDIEN0 Mask */
-
-#define PWM_INTEN0_CMPDIEN1_Pos (25) /*!< PWM_T::INTEN0: CMPDIEN1 Position */
-#define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) /*!< PWM_T::INTEN0: CMPDIEN1 Mask */
-
-#define PWM_INTEN0_CMPDIEN2_Pos (26) /*!< PWM_T::INTEN0: CMPDIEN2 Position */
-#define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) /*!< PWM_T::INTEN0: CMPDIEN2 Mask */
-
-#define PWM_INTEN0_CMPDIEN3_Pos (27) /*!< PWM_T::INTEN0: CMPDIEN3 Position */
-#define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) /*!< PWM_T::INTEN0: CMPDIEN3 Mask */
-
-#define PWM_INTEN0_CMPDIEN4_Pos (28) /*!< PWM_T::INTEN0: CMPDIEN4 Position */
-#define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) /*!< PWM_T::INTEN0: CMPDIEN4 Mask */
-
-#define PWM_INTEN0_CMPDIEN5_Pos (29) /*!< PWM_T::INTEN0: CMPDIEN5 Position */
-#define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) /*!< PWM_T::INTEN0: CMPDIEN5 Mask */
-
-#define PWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< PWM_T::INTEN1: BRKEIEN0_1 Position */
-#define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask */
-
-#define PWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< PWM_T::INTEN1: BRKEIEN2_3 Position */
-#define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask */
-
-#define PWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< PWM_T::INTEN1: BRKEIEN4_5 Position */
-#define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask */
-
-#define PWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< PWM_T::INTEN1: BRKLIEN0_1 Position */
-#define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask */
-
-#define PWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< PWM_T::INTEN1: BRKLIEN2_3 Position */
-#define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask */
-
-#define PWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< PWM_T::INTEN1: BRKLIEN4_5 Position */
-#define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask */
-
-#define PWM_INTSTS0_ZIFn_Pos (0) /*!< PWM_T::INTSTS0: ZIFn Position */
-#define PWM_INTSTS0_ZIFn_Msk (0x3ful << PWM_INTSTS0_ZIFn_Pos) /*!< PWM_T::INTSTS0: ZIFn Mask */
-
-#define PWM_INTSTS0_ZIF0_Pos (0) /*!< PWM_T::INTSTS0: ZIF0 Position */
-#define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) /*!< PWM_T::INTSTS0: ZIF0 Mask */
-
-#define PWM_INTSTS0_ZIF1_Pos (1) /*!< PWM_T::INTSTS0: ZIF1 Position */
-#define PWM_INTSTS0_ZIF1_Msk (0x1ul << PWM_INTSTS0_ZIF1_Pos) /*!< PWM_T::INTSTS0: ZIF1 Mask */
-
-#define PWM_INTSTS0_ZIF2_Pos (2) /*!< PWM_T::INTSTS0: ZIF2 Position */
-#define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) /*!< PWM_T::INTSTS0: ZIF2 Mask */
-
-#define PWM_INTSTS0_ZIF3_Pos (3) /*!< PWM_T::INTSTS0: ZIF3 Position */
-#define PWM_INTSTS0_ZIF3_Msk (0x1ul << PWM_INTSTS0_ZIF3_Pos) /*!< PWM_T::INTSTS0: ZIF3 Mask */
-
-#define PWM_INTSTS0_ZIF4_Pos (4) /*!< PWM_T::INTSTS0: ZIF4 Position */
-#define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) /*!< PWM_T::INTSTS0: ZIF4 Mask */
-
-#define PWM_INTSTS0_ZIF5_Pos (5) /*!< PWM_T::INTSTS0: ZIF5 Position */
-#define PWM_INTSTS0_ZIF5_Msk (0x1ul << PWM_INTSTS0_ZIF5_Pos) /*!< PWM_T::INTSTS0: ZIF5 Mask */
-
-#define PWM_INTSTS0_IFAIF0_1_Pos (7) /*!< PWM_T::INTSTS0: IFAIF0_1 Position */
-#define PWM_INTSTS0_IFAIF0_1_Msk (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos) /*!< PWM_T::INTSTS0: IFAIF0_1 Mask */
-
-#define PWM_INTSTS0_PIFn_Pos (8) /*!< PWM_T::INTSTS0: PIFn Position */
-#define PWM_INTSTS0_PIFn_Msk (0x3ful << PWM_INTSTS0_PIFn_Pos) /*!< PWM_T::INTSTS0: PIFn Mask */
-
-#define PWM_INTSTS0_PIF0_Pos (8) /*!< PWM_T::INTSTS0: PIF0 Position */
-#define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) /*!< PWM_T::INTSTS0: PIF0 Mask */
-
-#define PWM_INTSTS0_PIF1_Pos (9) /*!< PWM_T::INTSTS0: PIF1 Position */
-#define PWM_INTSTS0_PIF1_Msk (0x1ul << PWM_INTSTS0_PIF1_Pos) /*!< PWM_T::INTSTS0: PIF1 Mask */
-
-#define PWM_INTSTS0_PIF2_Pos (10) /*!< PWM_T::INTSTS0: PIF2 Position */
-#define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) /*!< PWM_T::INTSTS0: PIF2 Mask */
-
-#define PWM_INTSTS0_PIF3_Pos (11) /*!< PWM_T::INTSTS0: PIF3 Position */
-#define PWM_INTSTS0_PIF3_Msk (0x1ul << PWM_INTSTS0_PIF3_Pos) /*!< PWM_T::INTSTS0: PIF3 Mask */
-
-#define PWM_INTSTS0_PIF4_Pos (12) /*!< PWM_T::INTSTS0: PIF4 Position */
-#define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) /*!< PWM_T::INTSTS0: PIF4 Mask */
-
-#define PWM_INTSTS0_PIF5_Pos (13) /*!< PWM_T::INTSTS0: PIF5 Position */
-#define PWM_INTSTS0_PIF5_Msk (0x1ul << PWM_INTSTS0_PIF5_Pos) /*!< PWM_T::INTSTS0: PIF5 Mask */
-
-#define PWM_INTSTS0_IFAIF2_3_Pos (15) /*!< PWM_T::INTSTS0: IFAIF2_3 Position */
-#define PWM_INTSTS0_IFAIF2_3_Msk (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos) /*!< PWM_T::INTSTS0: IFAIF2_3 Mask */
-
-#define PWM_INTSTS0_CMPUIFn_Pos (16) /*!< PWM_T::INTSTS0: CMPUIFn Position */
-#define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) /*!< PWM_T::INTSTS0: CMPUIFn Mask */
-
-#define PWM_INTSTS0_CMPUIF0_Pos (16) /*!< PWM_T::INTSTS0: CMPUIF0 Position */
-#define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos) /*!< PWM_T::INTSTS0: CMPUIF0 Mask */
-
-#define PWM_INTSTS0_CMPUIF1_Pos (17) /*!< PWM_T::INTSTS0: CMPUIF1 Position */
-#define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos) /*!< PWM_T::INTSTS0: CMPUIF1 Mask */
-
-#define PWM_INTSTS0_CMPUIF2_Pos (18) /*!< PWM_T::INTSTS0: CMPUIF2 Position */
-#define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos) /*!< PWM_T::INTSTS0: CMPUIF2 Mask */
-
-#define PWM_INTSTS0_CMPUIF3_Pos (19) /*!< PWM_T::INTSTS0: CMPUIF3 Position */
-#define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos) /*!< PWM_T::INTSTS0: CMPUIF3 Mask */
-
-#define PWM_INTSTS0_CMPUIF4_Pos (20) /*!< PWM_T::INTSTS0: CMPUIF4 Position */
-#define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos) /*!< PWM_T::INTSTS0: CMPUIF4 Mask */
-
-#define PWM_INTSTS0_CMPUIF5_Pos (21) /*!< PWM_T::INTSTS0: CMPUIF5 Position */
-#define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos) /*!< PWM_T::INTSTS0: CMPUIF5 Mask */
-
-#define PWM_INTSTS0_IFAIF4_5_Pos (23) /*!< PWM_T::INTSTS0: IFAIF4_5 Position */
-#define PWM_INTSTS0_IFAIF4_5_Msk (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos) /*!< PWM_T::INTSTS0: IFAIF4_5 Mask */
-
-#define PWM_INTSTS0_CMPDIFn_Pos (24) /*!< PWM_T::INTSTS0: CMPDIFn Position */
-#define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) /*!< PWM_T::INTSTS0: CMPDIFn Mask */
-
-#define PWM_INTSTS0_CMPDIF0_Pos (24) /*!< PWM_T::INTSTS0: CMPDIF0 Position */
-#define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) /*!< PWM_T::INTSTS0: CMPDIF0 Mask */
-
-#define PWM_INTSTS0_CMPDIF1_Pos (25) /*!< PWM_T::INTSTS0: CMPDIF1 Position */
-#define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) /*!< PWM_T::INTSTS0: CMPDIF1 Mask */
-
-#define PWM_INTSTS0_CMPDIF2_Pos (26) /*!< PWM_T::INTSTS0: CMPDIF2 Position */
-#define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) /*!< PWM_T::INTSTS0: CMPDIF2 Mask */
-
-#define PWM_INTSTS0_CMPDIF3_Pos (27) /*!< PWM_T::INTSTS0: CMPDIF3 Position */
-#define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) /*!< PWM_T::INTSTS0: CMPDIF3 Mask */
-
-#define PWM_INTSTS0_CMPDIF4_Pos (28) /*!< PWM_T::INTSTS0: CMPDIF4 Position */
-#define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) /*!< PWM_T::INTSTS0: CMPDIF4 Mask */
-
-#define PWM_INTSTS0_CMPDIF5_Pos (29) /*!< PWM_T::INTSTS0: CMPDIF5 Position */
-#define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) /*!< PWM_T::INTSTS0: CMPDIF5 Mask */
-
-#define PWM_INTSTS1_BRKEIFn_Pos (0) /*!< PWM_T::INTSTS1: BRKEIFn Position */
-#define PWM_INTSTS1_BRKEIFn_Msk (0x3ful << PWM_INTSTS1_BRKEIFn_Pos) /*!< PWM_T::INTSTS1: BRKEIFn Mask */
-
-#define PWM_INTSTS1_BRKEIF0_Pos (0) /*!< PWM_T::INTSTS1: BRKEIF0 Position */
-#define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) /*!< PWM_T::INTSTS1: BRKEIF0 Mask */
-
-#define PWM_INTSTS1_BRKEIF1_Pos (1) /*!< PWM_T::INTSTS1: BRKEIF1 Position */
-#define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) /*!< PWM_T::INTSTS1: BRKEIF1 Mask */
-
-#define PWM_INTSTS1_BRKEIF2_Pos (2) /*!< PWM_T::INTSTS1: BRKEIF2 Position */
-#define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) /*!< PWM_T::INTSTS1: BRKEIF2 Mask */
-
-#define PWM_INTSTS1_BRKEIF3_Pos (3) /*!< PWM_T::INTSTS1: BRKEIF3 Position */
-#define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) /*!< PWM_T::INTSTS1: BRKEIF3 Mask */
-
-#define PWM_INTSTS1_BRKEIF4_Pos (4) /*!< PWM_T::INTSTS1: BRKEIF4 Position */
-#define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) /*!< PWM_T::INTSTS1: BRKEIF4 Mask */
-
-#define PWM_INTSTS1_BRKEIF5_Pos (5) /*!< PWM_T::INTSTS1: BRKEIF5 Position */
-#define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) /*!< PWM_T::INTSTS1: BRKEIF5 Mask */
-
-#define PWM_INTSTS1_BRKLIFn_Pos (8) /*!< PWM_T::INTSTS1: BRKLIFn Position */
-#define PWM_INTSTS1_BRKLIFn_Msk (0x3ful << PWM_INTSTS1_BRKLIFn_Pos) /*!< PWM_T::INTSTS1: BRKLIFn Mask */
-
-#define PWM_INTSTS1_BRKLIF0_Pos (8) /*!< PWM_T::INTSTS1: BRKLIF0 Position */
-#define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) /*!< PWM_T::INTSTS1: BRKLIF0 Mask */
-
-#define PWM_INTSTS1_BRKLIF1_Pos (9) /*!< PWM_T::INTSTS1: BRKLIF1 Position */
-#define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) /*!< PWM_T::INTSTS1: BRKLIF1 Mask */
-
-#define PWM_INTSTS1_BRKLIF2_Pos (10) /*!< PWM_T::INTSTS1: BRKLIF2 Position */
-#define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) /*!< PWM_T::INTSTS1: BRKLIF2 Mask */
-
-#define PWM_INTSTS1_BRKLIF3_Pos (11) /*!< PWM_T::INTSTS1: BRKLIF3 Position */
-#define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) /*!< PWM_T::INTSTS1: BRKLIF3 Mask */
-
-#define PWM_INTSTS1_BRKLIF4_Pos (12) /*!< PWM_T::INTSTS1: BRKLIF4 Position */
-#define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) /*!< PWM_T::INTSTS1: BRKLIF4 Mask */
-
-#define PWM_INTSTS1_BRKLIF5_Pos (13) /*!< PWM_T::INTSTS1: BRKLIF5 Position */
-#define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) /*!< PWM_T::INTSTS1: BRKLIF5 Mask */
-
-#define PWM_INTSTS1_BRKESTS0_Pos (16) /*!< PWM_T::INTSTS1: BRKESTS0 Position */
-#define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) /*!< PWM_T::INTSTS1: BRKESTS0 Mask */
-
-#define PWM_INTSTS1_BRKESTS1_Pos (17) /*!< PWM_T::INTSTS1: BRKESTS1 Position */
-#define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) /*!< PWM_T::INTSTS1: BRKESTS1 Mask */
-
-#define PWM_INTSTS1_BRKESTS2_Pos (18) /*!< PWM_T::INTSTS1: BRKESTS2 Position */
-#define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) /*!< PWM_T::INTSTS1: BRKESTS2 Mask */
-
-#define PWM_INTSTS1_BRKESTS3_Pos (19) /*!< PWM_T::INTSTS1: BRKESTS3 Position */
-#define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) /*!< PWM_T::INTSTS1: BRKESTS3 Mask */
-
-#define PWM_INTSTS1_BRKESTS4_Pos (20) /*!< PWM_T::INTSTS1: BRKESTS4 Position */
-#define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) /*!< PWM_T::INTSTS1: BRKESTS4 Mask */
-
-#define PWM_INTSTS1_BRKESTS5_Pos (21) /*!< PWM_T::INTSTS1: BRKESTS5 Position */
-#define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) /*!< PWM_T::INTSTS1: BRKESTS5 Mask */
-
-#define PWM_INTSTS1_BRKLSTS0_Pos (24) /*!< PWM_T::INTSTS1: BRKLSTS0 Position */
-#define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) /*!< PWM_T::INTSTS1: BRKLSTS0 Mask */
-
-#define PWM_INTSTS1_BRKLSTS1_Pos (25) /*!< PWM_T::INTSTS1: BRKLSTS1 Position */
-#define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) /*!< PWM_T::INTSTS1: BRKLSTS1 Mask */
-
-#define PWM_INTSTS1_BRKLSTS2_Pos (26) /*!< PWM_T::INTSTS1: BRKLSTS2 Position */
-#define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) /*!< PWM_T::INTSTS1: BRKLSTS2 Mask */
-
-#define PWM_INTSTS1_BRKLSTS3_Pos (27) /*!< PWM_T::INTSTS1: BRKLSTS3 Position */
-#define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) /*!< PWM_T::INTSTS1: BRKLSTS3 Mask */
-
-#define PWM_INTSTS1_BRKLSTS4_Pos (28) /*!< PWM_T::INTSTS1: BRKLSTS4 Position */
-#define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) /*!< PWM_T::INTSTS1: BRKLSTS4 Mask */
-
-#define PWM_INTSTS1_BRKLSTS5_Pos (29) /*!< PWM_T::INTSTS1: BRKLSTS5 Position */
-#define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) /*!< PWM_T::INTSTS1: BRKLSTS5 Mask */
-
-#define PWM_IFA_IFCNT0_1_Pos (0) /*!< PWM_T::IFA: IFCNT0_1 Position */
-#define PWM_IFA_IFCNT0_1_Msk (0xful << PWM_IFA_IFCNT0_1_Pos) /*!< PWM_T::IFA: IFCNT0_1 Mask */
-
-#define PWM_IFA_IFSEL0_1_Pos (4) /*!< PWM_T::IFA: IFSEL0_1 Position */
-#define PWM_IFA_IFSEL0_1_Msk (0x7ul << PWM_IFA_IFSEL0_1_Pos) /*!< PWM_T::IFA: IFSEL0_1 Mask */
-
-#define PWM_IFA_IFAEN0_1_Pos (7) /*!< PWM_T::IFA: IFAEN0_1 Position */
-#define PWM_IFA_IFAEN0_1_Msk (0x1ul << PWM_IFA_IFAEN0_1_Pos) /*!< PWM_T::IFA: IFAEN0_1 Mask */
-
-#define PWM_IFA_IFCNT2_3_Pos (8) /*!< PWM_T::IFA: IFCNT2_3 Position */
-#define PWM_IFA_IFCNT2_3_Msk (0xful << PWM_IFA_IFCNT2_3_Pos) /*!< PWM_T::IFA: IFCNT2_3 Mask */
-
-#define PWM_IFA_IFSEL2_3_Pos (12) /*!< PWM_T::IFA: IFSEL2_3 Position */
-#define PWM_IFA_IFSEL2_3_Msk (0x7ul << PWM_IFA_IFSEL2_3_Pos) /*!< PWM_T::IFA: IFSEL2_3 Mask */
-
-#define PWM_IFA_IFAEN2_3_Pos (15) /*!< PWM_T::IFA: IFAEN2_3 Position */
-#define PWM_IFA_IFAEN2_3_Msk (0x1ul << PWM_IFA_IFAEN2_3_Pos) /*!< PWM_T::IFA: IFAEN2_3 Mask */
-
-#define PWM_IFA_IFCNT4_5_Pos (16) /*!< PWM_T::IFA: IFCNT4_5 Position */
-#define PWM_IFA_IFCNT4_5_Msk (0xful << PWM_IFA_IFCNT4_5_Pos) /*!< PWM_T::IFA: IFCNT4_5 Mask */
-
-#define PWM_IFA_IFSEL4_5_Pos (20) /*!< PWM_T::IFA: IFSEL4_5 Position */
-#define PWM_IFA_IFSEL4_5_Msk (0x7ul << PWM_IFA_IFSEL4_5_Pos) /*!< PWM_T::IFA: IFSEL4_5 Mask */
-
-#define PWM_IFA_IFAEN4_5_Pos (23) /*!< PWM_T::IFA: IFAEN4_5 Position */
-#define PWM_IFA_IFAEN4_5_Msk (0x1ul << PWM_IFA_IFAEN4_5_Pos) /*!< PWM_T::IFA: IFAEN4_5 Mask */
-
-#define PWM_DACTRGEN_ZTEn_Pos (0) /*!< PWM_T::DACTRGEN: ZTEn Position */
-#define PWM_DACTRGEN_ZTEn_Msk (0x3ful << PWM_DACTRGEN_ZTEn_Pos) /*!< PWM_T::DACTRGEN: ZTEn Mask */
-
-#define PWM_DACTRGEN_ZTE0_Pos (0) /*!< PWM_T::DACTRGEN: ZTE0 Position */
-#define PWM_DACTRGEN_ZTE0_Msk (0x1ul << PWM_DACTRGEN_ZTE0_Pos) /*!< PWM_T::DACTRGEN: ZTE0 Mask */
-
-#define PWM_DACTRGEN_ZTE1_Pos (1) /*!< PWM_T::DACTRGEN: ZTE1 Position */
-#define PWM_DACTRGEN_ZTE1_Msk (0x1ul << PWM_DACTRGEN_ZTE1_Pos) /*!< PWM_T::DACTRGEN: ZTE1 Mask */
-
-#define PWM_DACTRGEN_ZTE2_Pos (2) /*!< PWM_T::DACTRGEN: ZTE2 Position */
-#define PWM_DACTRGEN_ZTE2_Msk (0x1ul << PWM_DACTRGEN_ZTE2_Pos) /*!< PWM_T::DACTRGEN: ZTE2 Mask */
-
-#define PWM_DACTRGEN_ZTE3_Pos (3) /*!< PWM_T::DACTRGEN: ZTE3 Position */
-#define PWM_DACTRGEN_ZTE3_Msk (0x1ul << PWM_DACTRGEN_ZTE3_Pos) /*!< PWM_T::DACTRGEN: ZTE3 Mask */
-
-#define PWM_DACTRGEN_ZTE4_Pos (4) /*!< PWM_T::DACTRGEN: ZTE4 Position */
-#define PWM_DACTRGEN_ZTE4_Msk (0x1ul << PWM_DACTRGEN_ZTE4_Pos) /*!< PWM_T::DACTRGEN: ZTE4 Mask */
-
-#define PWM_DACTRGEN_ZTE5_Pos (5) /*!< PWM_T::DACTRGEN: ZTE5 Position */
-#define PWM_DACTRGEN_ZTE5_Msk (0x1ul << PWM_DACTRGEN_ZTE5_Pos) /*!< PWM_T::DACTRGEN: ZTE5 Mask */
-
-#define PWM_DACTRGEN_PTEn_Pos (8) /*!< PWM_T::DACTRGEN: PTEn Position */
-#define PWM_DACTRGEN_PTEn_Msk (0x3ful << PWM_DACTRGEN_PTEn_Pos) /*!< PWM_T::DACTRGEN: PTEn Mask */
-
-#define PWM_DACTRGEN_PTE0_Pos (8) /*!< PWM_T::DACTRGEN: PTE0 Position */
-#define PWM_DACTRGEN_PTE0_Msk (0x1ul << PWM_DACTRGEN_PTE0_Pos) /*!< PWM_T::DACTRGEN: PTE0 Mask */
-
-#define PWM_DACTRGEN_PTE1_Pos (9) /*!< PWM_T::DACTRGEN: PTE1 Position */
-#define PWM_DACTRGEN_PTE1_Msk (0x1ul << PWM_DACTRGEN_PTE1_Pos) /*!< PWM_T::DACTRGEN: PTE1 Mask */
-
-#define PWM_DACTRGEN_PTE2_Pos (10) /*!< PWM_T::DACTRGEN: PTE2 Position */
-#define PWM_DACTRGEN_PTE2_Msk (0x1ul << PWM_DACTRGEN_PTE2_Pos) /*!< PWM_T::DACTRGEN: PTE2 Mask */
-
-#define PWM_DACTRGEN_PTE3_Pos (11) /*!< PWM_T::DACTRGEN: PTE3 Position */
-#define PWM_DACTRGEN_PTE3_Msk (0x1ul << PWM_DACTRGEN_PTE3_Pos) /*!< PWM_T::DACTRGEN: PTE3 Mask */
-
-#define PWM_DACTRGEN_PTE4_Pos (12) /*!< PWM_T::DACTRGEN: PTE4 Position */
-#define PWM_DACTRGEN_PTE4_Msk (0x1ul << PWM_DACTRGEN_PTE4_Pos) /*!< PWM_T::DACTRGEN: PTE4 Mask */
-
-#define PWM_DACTRGEN_PTE5_Pos (13) /*!< PWM_T::DACTRGEN: PTE5 Position */
-#define PWM_DACTRGEN_PTE5_Msk (0x1ul << PWM_DACTRGEN_PTE5_Pos) /*!< PWM_T::DACTRGEN: PTE5 Mask */
-
-#define PWM_DACTRGEN_CUTRGEn_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGEn Position */
-#define PWM_DACTRGEN_CUTRGEn_Msk (0x3ful << PWM_DACTRGEN_CUTRGEn_Pos) /*!< PWM_T::DACTRGEN: CUTRGEn Mask */
-
-#define PWM_DACTRGEN_CUTRGE0_Pos (16) /*!< PWM_T::DACTRGEN: CUTRGE0 Position */
-#define PWM_DACTRGEN_CUTRGE0_Msk (0x1ul << PWM_DACTRGEN_CUTRGE0_Pos) /*!< PWM_T::DACTRGEN: CUTRGE0 Mask */
-
-#define PWM_DACTRGEN_CUTRGE1_Pos (17) /*!< PWM_T::DACTRGEN: CUTRGE1 Position */
-#define PWM_DACTRGEN_CUTRGE1_Msk (0x1ul << PWM_DACTRGEN_CUTRGE1_Pos) /*!< PWM_T::DACTRGEN: CUTRGE1 Mask */
-
-#define PWM_DACTRGEN_CUTRGE2_Pos (18) /*!< PWM_T::DACTRGEN: CUTRGE2 Position */
-#define PWM_DACTRGEN_CUTRGE2_Msk (0x1ul << PWM_DACTRGEN_CUTRGE2_Pos) /*!< PWM_T::DACTRGEN: CUTRGE2 Mask */
-
-#define PWM_DACTRGEN_CUTRGE3_Pos (19) /*!< PWM_T::DACTRGEN: CUTRGE3 Position */
-#define PWM_DACTRGEN_CUTRGE3_Msk (0x1ul << PWM_DACTRGEN_CUTRGE3_Pos) /*!< PWM_T::DACTRGEN: CUTRGE3 Mask */
-
-#define PWM_DACTRGEN_CUTRGE4_Pos (20) /*!< PWM_T::DACTRGEN: CUTRGE4 Position */
-#define PWM_DACTRGEN_CUTRGE4_Msk (0x1ul << PWM_DACTRGEN_CUTRGE4_Pos) /*!< PWM_T::DACTRGEN: CUTRGE4 Mask */
-
-#define PWM_DACTRGEN_CUTRGE5_Pos (21) /*!< PWM_T::DACTRGEN: CUTRGE5 Position */
-#define PWM_DACTRGEN_CUTRGE5_Msk (0x1ul << PWM_DACTRGEN_CUTRGE5_Pos) /*!< PWM_T::DACTRGEN: CUTRGE5 Mask */
-
-#define PWM_DACTRGEN_CDTRGEn_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGEn Position */
-#define PWM_DACTRGEN_CDTRGEn_Msk (0x3ful << PWM_DACTRGEN_CDTRGEn_Pos) /*!< PWM_T::DACTRGEN: CDTRGEn Mask */
-
-#define PWM_DACTRGEN_CDTRGE0_Pos (24) /*!< PWM_T::DACTRGEN: CDTRGE0 Position */
-#define PWM_DACTRGEN_CDTRGE0_Msk (0x1ul << PWM_DACTRGEN_CDTRGE0_Pos) /*!< PWM_T::DACTRGEN: CDTRGE0 Mask */
-
-#define PWM_DACTRGEN_CDTRGE1_Pos (25) /*!< PWM_T::DACTRGEN: CDTRGE1 Position */
-#define PWM_DACTRGEN_CDTRGE1_Msk (0x1ul << PWM_DACTRGEN_CDTRGE1_Pos) /*!< PWM_T::DACTRGEN: CDTRGE1 Mask */
-
-#define PWM_DACTRGEN_CDTRGE2_Pos (26) /*!< PWM_T::DACTRGEN: CDTRGE2 Position */
-#define PWM_DACTRGEN_CDTRGE2_Msk (0x1ul << PWM_DACTRGEN_CDTRGE2_Pos) /*!< PWM_T::DACTRGEN: CDTRGE2 Mask */
-
-#define PWM_DACTRGEN_CDTRGE3_Pos (27) /*!< PWM_T::DACTRGEN: CDTRGE3 Position */
-#define PWM_DACTRGEN_CDTRGE3_Msk (0x1ul << PWM_DACTRGEN_CDTRGE3_Pos) /*!< PWM_T::DACTRGEN: CDTRGE3 Mask */
-
-#define PWM_DACTRGEN_CDTRGE4_Pos (28) /*!< PWM_T::DACTRGEN: CDTRGE4 Position */
-#define PWM_DACTRGEN_CDTRGE4_Msk (0x1ul << PWM_DACTRGEN_CDTRGE4_Pos) /*!< PWM_T::DACTRGEN: CDTRGE4 Mask */
-
-#define PWM_DACTRGEN_CDTRGE5_Pos (29) /*!< PWM_T::DACTRGEN: CDTRGE5 Position */
-#define PWM_DACTRGEN_CDTRGE5_Msk (0x1ul << PWM_DACTRGEN_CDTRGE5_Pos) /*!< PWM_T::DACTRGEN: CDTRGE5 Mask */
-
-#define PWM_EADCTS0_TRGSEL0_Pos (0) /*!< PWM_T::EADCTS0: TRGSEL0 Position */
-#define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) /*!< PWM_T::EADCTS0: TRGSEL0 Mask */
-
-#define PWM_EADCTS0_TRGEN0_Pos (7) /*!< PWM_T::EADCTS0: TRGEN0 Position */
-#define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) /*!< PWM_T::EADCTS0: TRGEN0 Mask */
-
-#define PWM_EADCTS0_TRGSEL1_Pos (8) /*!< PWM_T::EADCTS0: TRGSEL1 Position */
-#define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) /*!< PWM_T::EADCTS0: TRGSEL1 Mask */
-
-#define PWM_EADCTS0_TRGEN1_Pos (15) /*!< PWM_T::EADCTS0: TRGEN1 Position */
-#define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) /*!< PWM_T::EADCTS0: TRGEN1 Mask */
-
-#define PWM_EADCTS0_TRGSEL2_Pos (16) /*!< PWM_T::EADCTS0: TRGSEL2 Position */
-#define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) /*!< PWM_T::EADCTS0: TRGSEL2 Mask */
-
-#define PWM_EADCTS0_TRGEN2_Pos (23) /*!< PWM_T::EADCTS0: TRGEN2 Position */
-#define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) /*!< PWM_T::EADCTS0: TRGEN2 Mask */
-
-#define PWM_EADCTS0_TRGSEL3_Pos (24) /*!< PWM_T::EADCTS0: TRGSEL3 Position */
-#define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) /*!< PWM_T::EADCTS0: TRGSEL3 Mask */
-
-#define PWM_EADCTS0_TRGEN3_Pos (31) /*!< PWM_T::EADCTS0: TRGEN3 Position */
-#define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) /*!< PWM_T::EADCTS0: TRGEN3 Mask */
-
-#define PWM_EADCTS1_TRGSEL4_Pos (0) /*!< PWM_T::EADCTS1: TRGSEL4 Position */
-#define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) /*!< PWM_T::EADCTS1: TRGSEL4 Mask */
-
-#define PWM_EADCTS1_TRGEN4_Pos (7) /*!< PWM_T::EADCTS1: TRGEN4 Position */
-#define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) /*!< PWM_T::EADCTS1: TRGEN4 Mask */
-
-#define PWM_EADCTS1_TRGSEL5_Pos (8) /*!< PWM_T::EADCTS1: TRGSEL5 Position */
-#define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) /*!< PWM_T::EADCTS1: TRGSEL5 Mask */
-
-#define PWM_EADCTS1_TRGEN5_Pos (15) /*!< PWM_T::EADCTS1: TRGEN5 Position */
-#define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) /*!< PWM_T::EADCTS1: TRGEN5 Mask */
-
-#define PWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT0_1: FTCMP Position */
-#define PWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos) /*!< PWM_T::FTCMPDAT0_1: FTCMP Mask */
-
-#define PWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT2_3: FTCMP Position */
-#define PWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos) /*!< PWM_T::FTCMPDAT2_3: FTCMP Mask */
-
-#define PWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< PWM_T::FTCMPDAT4_5: FTCMP Position */
-#define PWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos) /*!< PWM_T::FTCMPDAT4_5: FTCMP Mask */
-
-#define PWM_SSCTL_SSENn_Pos (0) /*!< PWM_T::SSCTL: SSENn Position */
-#define PWM_SSCTL_SSENn_Msk (0x3ful << PWM_SSCTL_SSENn_Pos) /*!< PWM_T::SSCTL: SSENn Mask */
-
-#define PWM_SSCTL_SSEN0_Pos (0) /*!< PWM_T::SSCTL: SSEN0 Position */
-#define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) /*!< PWM_T::SSCTL: SSEN0 Mask */
-
-#define PWM_SSCTL_SSEN1_Pos (1) /*!< PWM_T::SSCTL: SSEN1 Position */
-#define PWM_SSCTL_SSEN1_Msk (0x1ul << PWM_SSCTL_SSEN1_Pos) /*!< PWM_T::SSCTL: SSEN1 Mask */
-
-#define PWM_SSCTL_SSEN2_Pos (2) /*!< PWM_T::SSCTL: SSEN2 Position */
-#define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) /*!< PWM_T::SSCTL: SSEN2 Mask */
-
-#define PWM_SSCTL_SSEN3_Pos (3) /*!< PWM_T::SSCTL: SSEN3 Position */
-#define PWM_SSCTL_SSEN3_Msk (0x1ul << PWM_SSCTL_SSEN3_Pos) /*!< PWM_T::SSCTL: SSEN3 Mask */
-
-#define PWM_SSCTL_SSEN4_Pos (4) /*!< PWM_T::SSCTL: SSEN4 Position */
-#define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) /*!< PWM_T::SSCTL: SSEN4 Mask */
-
-#define PWM_SSCTL_SSEN5_Pos (5) /*!< PWM_T::SSCTL: SSEN5 Position */
-#define PWM_SSCTL_SSEN5_Msk (0x1ul << PWM_SSCTL_SSEN5_Pos) /*!< PWM_T::SSCTL: SSEN5 Mask */
-
-#define PWM_SSTRG_CNTSEN_Pos (0) /*!< PWM_T::SSTRG: CNTSEN Position */
-#define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) /*!< PWM_T::SSTRG: CNTSEN Mask */
-
-#define PWM_STATUS_CNTMAXFn_Pos (0) /*!< PWM_T::STATUS: CNTMAXFn Position */
-#define PWM_STATUS_CNTMAXFn_Msk (0x3ful << PWM_STATUS_CNTMAXFn_Pos) /*!< PWM_T::STATUS: CNTMAXFn Mask */
-
-#define PWM_STATUS_CNTMAXF0_Pos (0) /*!< PWM_T::STATUS: CNTMAXF0 Position */
-#define PWM_STATUS_CNTMAXF0_Msk (0x1ul << PWM_STATUS_CNTMAXF0_Pos) /*!< PWM_T::STATUS: CNTMAXF0 Mask */
-
-#define PWM_STATUS_CNTMAXF1_Pos (1) /*!< PWM_T::STATUS: CNTMAXF1 Position */
-#define PWM_STATUS_CNTMAXF1_Msk (0x1ul << PWM_STATUS_CNTMAXF1_Pos) /*!< PWM_T::STATUS: CNTMAXF1 Mask */
-
-#define PWM_STATUS_CNTMAXF2_Pos (2) /*!< PWM_T::STATUS: CNTMAXF2 Position */
-#define PWM_STATUS_CNTMAXF2_Msk (0x1ul << PWM_STATUS_CNTMAXF2_Pos) /*!< PWM_T::STATUS: CNTMAXF2 Mask */
-
-#define PWM_STATUS_CNTMAXF3_Pos (3) /*!< PWM_T::STATUS: CNTMAXF3 Position */
-#define PWM_STATUS_CNTMAXF3_Msk (0x1ul << PWM_STATUS_CNTMAXF3_Pos) /*!< PWM_T::STATUS: CNTMAXF3 Mask */
-
-#define PWM_STATUS_CNTMAXF4_Pos (4) /*!< PWM_T::STATUS: CNTMAXF4 Position */
-#define PWM_STATUS_CNTMAXF4_Msk (0x1ul << PWM_STATUS_CNTMAXF4_Pos) /*!< PWM_T::STATUS: CNTMAXF4 Mask */
-
-#define PWM_STATUS_CNTMAXF5_Pos (5) /*!< PWM_T::STATUS: CNTMAXF5 Position */
-#define PWM_STATUS_CNTMAXF5_Msk (0x1ul << PWM_STATUS_CNTMAXF5_Pos) /*!< PWM_T::STATUS: CNTMAXF5 Mask */
-
-#define PWM_STATUS_SYNCINFn_Pos (8) /*!< PWM_T::STATUS: SYNCINFn Position */
-#define PWM_STATUS_SYNCINFn_Msk (0x7ul << PWM_STATUS_SYNCINFn_Pos) /*!< PWM_T::STATUS: SYNCINFn Mask */
-
-#define PWM_STATUS_SYNCINF0_Pos (8) /*!< PWM_T::STATUS: SYNCINF0 Position */
-#define PWM_STATUS_SYNCINF0_Msk (0x1ul << PWM_STATUS_SYNCINF0_Pos) /*!< PWM_T::STATUS: SYNCINF0 Mask */
-
-#define PWM_STATUS_SYNCINF2_Pos (9) /*!< PWM_T::STATUS: SYNCINF2 Position */
-#define PWM_STATUS_SYNCINF2_Msk (0x1ul << PWM_STATUS_SYNCINF2_Pos) /*!< PWM_T::STATUS: SYNCINF2 Mask */
-
-#define PWM_STATUS_SYNCINF4_Pos (10) /*!< PWM_T::STATUS: SYNCINF4 Position */
-#define PWM_STATUS_SYNCINF4_Msk (0x1ul << PWM_STATUS_SYNCINF4_Pos) /*!< PWM_T::STATUS: SYNCINF4 Mask */
-
-#define PWM_STATUS_ADCTRGFn_Pos (16) /*!< PWM_T::STATUS: ADCTRGFn Position */
-#define PWM_STATUS_ADCTRGFn_Msk (0x3ful << PWM_STATUS_ADCTRGFn_Pos) /*!< PWM_T::STATUS: ADCTRGFn Mask */
-
-#define PWM_STATUS_ADCTRGF0_Pos (16) /*!< PWM_T::STATUS: ADCTRGF0 Position */
-#define PWM_STATUS_ADCTRGF0_Msk (0x1ul << PWM_STATUS_ADCTRGF0_Pos) /*!< PWM_T::STATUS: ADCTRGF0 Mask */
-
-#define PWM_STATUS_ADCTRGF1_Pos (17) /*!< PWM_T::STATUS: ADCTRGF1 Position */
-#define PWM_STATUS_ADCTRGF1_Msk (0x1ul << PWM_STATUS_ADCTRGF1_Pos) /*!< PWM_T::STATUS: ADCTRGF1 Mask */
-
-#define PWM_STATUS_ADCTRGF2_Pos (18) /*!< PWM_T::STATUS: ADCTRGF2 Position */
-#define PWM_STATUS_ADCTRGF2_Msk (0x1ul << PWM_STATUS_ADCTRGF2_Pos) /*!< PWM_T::STATUS: ADCTRGF2 Mask */
-
-#define PWM_STATUS_ADCTRGF3_Pos (19) /*!< PWM_T::STATUS: ADCTRGF3 Position */
-#define PWM_STATUS_ADCTRGF3_Msk (0x1ul << PWM_STATUS_ADCTRGF3_Pos) /*!< PWM_T::STATUS: ADCTRGF3 Mask */
-
-#define PWM_STATUS_ADCTRGF4_Pos (20) /*!< PWM_T::STATUS: ADCTRGF4 Position */
-#define PWM_STATUS_ADCTRGF4_Msk (0x1ul << PWM_STATUS_ADCTRGF4_Pos) /*!< PWM_T::STATUS: ADCTRGF4 Mask */
-
-#define PWM_STATUS_ADCTRGF5_Pos (21) /*!< PWM_T::STATUS: ADCTRGF5 Position */
-#define PWM_STATUS_ADCTRGF5_Msk (0x1ul << PWM_STATUS_ADCTRGF5_Pos) /*!< PWM_T::STATUS: ADCTRGF5 Mask */
-
-#define PWM_STATUS_DACTRGF_Pos (24) /*!< PWM_T::STATUS: DACTRGF Position */
-#define PWM_STATUS_DACTRGF_Msk (0x1ul << PWM_STATUS_DACTRGF_Pos) /*!< PWM_T::STATUS: DACTRGF Mask */
-
-#define PWM_CAPINEN_CAPINENn_Pos (0) /*!< PWM_T::CAPINEN: CAPINENn Position */
-#define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) /*!< PWM_T::CAPINEN: CAPINENn Mask */
-
-#define PWM_CAPINEN_CAPINEN0_Pos (0) /*!< PWM_T::CAPINEN: CAPINEN0 Position */
-#define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) /*!< PWM_T::CAPINEN: CAPINEN0 Mask */
-
-#define PWM_CAPINEN_CAPINEN1_Pos (1) /*!< PWM_T::CAPINEN: CAPINEN1 Position */
-#define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) /*!< PWM_T::CAPINEN: CAPINEN1 Mask */
-
-#define PWM_CAPINEN_CAPINEN2_Pos (2) /*!< PWM_T::CAPINEN: CAPINEN2 Position */
-#define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) /*!< PWM_T::CAPINEN: CAPINEN2 Mask */
-
-#define PWM_CAPINEN_CAPINEN3_Pos (3) /*!< PWM_T::CAPINEN: CAPINEN3 Position */
-#define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) /*!< PWM_T::CAPINEN: CAPINEN3 Mask */
-
-#define PWM_CAPINEN_CAPINEN4_Pos (4) /*!< PWM_T::CAPINEN: CAPINEN4 Position */
-#define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) /*!< PWM_T::CAPINEN: CAPINEN4 Mask */
-
-#define PWM_CAPINEN_CAPINEN5_Pos (5) /*!< PWM_T::CAPINEN: CAPINEN5 Position */
-#define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) /*!< PWM_T::CAPINEN: CAPINEN5 Mask */
-
-#define PWM_CAPCTL_CAPENn_Pos (0) /*!< PWM_T::CAPCTL: CAPENn Position */
-#define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) /*!< PWM_T::CAPCTL: CAPENn Mask */
-
-#define PWM_CAPCTL_CAPEN0_Pos (0) /*!< PWM_T::CAPCTL: CAPEN0 Position */
-#define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) /*!< PWM_T::CAPCTL: CAPEN0 Mask */
-
-#define PWM_CAPCTL_CAPEN1_Pos (1) /*!< PWM_T::CAPCTL: CAPEN1 Position */
-#define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) /*!< PWM_T::CAPCTL: CAPEN1 Mask */
-
-#define PWM_CAPCTL_CAPEN2_Pos (2) /*!< PWM_T::CAPCTL: CAPEN2 Position */
-#define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) /*!< PWM_T::CAPCTL: CAPEN2 Mask */
-
-#define PWM_CAPCTL_CAPEN3_Pos (3) /*!< PWM_T::CAPCTL: CAPEN3 Position */
-#define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) /*!< PWM_T::CAPCTL: CAPEN3 Mask */
-
-#define PWM_CAPCTL_CAPEN4_Pos (4) /*!< PWM_T::CAPCTL: CAPEN4 Position */
-#define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) /*!< PWM_T::CAPCTL: CAPEN4 Mask */
-
-#define PWM_CAPCTL_CAPEN5_Pos (5) /*!< PWM_T::CAPCTL: CAPEN5 Position */
-#define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) /*!< PWM_T::CAPCTL: CAPEN5 Mask */
-
-#define PWM_CAPCTL_CAPINVn_Pos (8) /*!< PWM_T::CAPCTL: CAPINVn Position */
-#define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) /*!< PWM_T::CAPCTL: CAPINVn Mask */
-
-#define PWM_CAPCTL_CAPINV0_Pos (8) /*!< PWM_T::CAPCTL: CAPINV0 Position */
-#define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) /*!< PWM_T::CAPCTL: CAPINV0 Mask */
-
-#define PWM_CAPCTL_CAPINV1_Pos (9) /*!< PWM_T::CAPCTL: CAPINV1 Position */
-#define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) /*!< PWM_T::CAPCTL: CAPINV1 Mask */
-
-#define PWM_CAPCTL_CAPINV2_Pos (10) /*!< PWM_T::CAPCTL: CAPINV2 Position */
-#define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) /*!< PWM_T::CAPCTL: CAPINV2 Mask */
-
-#define PWM_CAPCTL_CAPINV3_Pos (11) /*!< PWM_T::CAPCTL: CAPINV3 Position */
-#define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) /*!< PWM_T::CAPCTL: CAPINV3 Mask */
-
-#define PWM_CAPCTL_CAPINV4_Pos (12) /*!< PWM_T::CAPCTL: CAPINV4 Position */
-#define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) /*!< PWM_T::CAPCTL: CAPINV4 Mask */
-
-#define PWM_CAPCTL_CAPINV5_Pos (13) /*!< PWM_T::CAPCTL: CAPINV5 Position */
-#define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) /*!< PWM_T::CAPCTL: CAPINV5 Mask */
-
-#define PWM_CAPCTL_RCRLDENn_Pos (16) /*!< PWM_T::CAPCTL: RCRLDENn Position */
-#define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) /*!< PWM_T::CAPCTL: RCRLDENn Mask */
-
-#define PWM_CAPCTL_RCRLDEN0_Pos (16) /*!< PWM_T::CAPCTL: RCRLDEN0 Position */
-#define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) /*!< PWM_T::CAPCTL: RCRLDEN0 Mask */
-
-#define PWM_CAPCTL_RCRLDEN1_Pos (17) /*!< PWM_T::CAPCTL: RCRLDEN1 Position */
-#define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) /*!< PWM_T::CAPCTL: RCRLDEN1 Mask */
-
-#define PWM_CAPCTL_RCRLDEN2_Pos (18) /*!< PWM_T::CAPCTL: RCRLDEN2 Position */
-#define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) /*!< PWM_T::CAPCTL: RCRLDEN2 Mask */
-
-#define PWM_CAPCTL_RCRLDEN3_Pos (19) /*!< PWM_T::CAPCTL: RCRLDEN3 Position */
-#define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) /*!< PWM_T::CAPCTL: RCRLDEN3 Mask */
-
-#define PWM_CAPCTL_RCRLDEN4_Pos (20) /*!< PWM_T::CAPCTL: RCRLDEN4 Position */
-#define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) /*!< PWM_T::CAPCTL: RCRLDEN4 Mask */
-
-#define PWM_CAPCTL_RCRLDEN5_Pos (21) /*!< PWM_T::CAPCTL: RCRLDEN5 Position */
-#define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) /*!< PWM_T::CAPCTL: RCRLDEN5 Mask */
-
-#define PWM_CAPCTL_FCRLDENn_Pos (24) /*!< PWM_T::CAPCTL: FCRLDENn Position */
-#define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) /*!< PWM_T::CAPCTL: FCRLDENn Mask */
-
-#define PWM_CAPCTL_FCRLDEN0_Pos (24) /*!< PWM_T::CAPCTL: FCRLDEN0 Position */
-#define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) /*!< PWM_T::CAPCTL: FCRLDEN0 Mask */
-
-#define PWM_CAPCTL_FCRLDEN1_Pos (25) /*!< PWM_T::CAPCTL: FCRLDEN1 Position */
-#define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) /*!< PWM_T::CAPCTL: FCRLDEN1 Mask */
-
-#define PWM_CAPCTL_FCRLDEN2_Pos (26) /*!< PWM_T::CAPCTL: FCRLDEN2 Position */
-#define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) /*!< PWM_T::CAPCTL: FCRLDEN2 Mask */
-
-#define PWM_CAPCTL_FCRLDEN3_Pos (27) /*!< PWM_T::CAPCTL: FCRLDEN3 Position */
-#define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) /*!< PWM_T::CAPCTL: FCRLDEN3 Mask */
-
-#define PWM_CAPCTL_FCRLDEN4_Pos (28) /*!< PWM_T::CAPCTL: FCRLDEN4 Position */
-#define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) /*!< PWM_T::CAPCTL: FCRLDEN4 Mask */
-
-#define PWM_CAPCTL_FCRLDEN5_Pos (29) /*!< PWM_T::CAPCTL: FCRLDEN5 Position */
-#define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) /*!< PWM_T::CAPCTL: FCRLDEN5 Mask */
-
-#define PWM_CAPSTS_CRLIFOVn_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOVn Position */
-#define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos) /*!< PWM_T::CAPSTS: CRLIFOVn Mask */
-
-#define PWM_CAPSTS_CRLIFOV0_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOV0 Position */
-#define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) /*!< PWM_T::CAPSTS: CRLIFOV0 Mask */
-
-#define PWM_CAPSTS_CRLIFOV1_Pos (1) /*!< PWM_T::CAPSTS: CRLIFOV1 Position */
-#define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) /*!< PWM_T::CAPSTS: CRLIFOV1 Mask */
-
-#define PWM_CAPSTS_CRLIFOV2_Pos (2) /*!< PWM_T::CAPSTS: CRLIFOV2 Position */
-#define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) /*!< PWM_T::CAPSTS: CRLIFOV2 Mask */
-
-#define PWM_CAPSTS_CRLIFOV3_Pos (3) /*!< PWM_T::CAPSTS: CRLIFOV3 Position */
-#define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) /*!< PWM_T::CAPSTS: CRLIFOV3 Mask */
-
-#define PWM_CAPSTS_CRLIFOV4_Pos (4) /*!< PWM_T::CAPSTS: CRLIFOV4 Position */
-#define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) /*!< PWM_T::CAPSTS: CRLIFOV4 Mask */
-
-#define PWM_CAPSTS_CRLIFOV5_Pos (5) /*!< PWM_T::CAPSTS: CRLIFOV5 Position */
-#define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) /*!< PWM_T::CAPSTS: CRLIFOV5 Mask */
-
-#define PWM_CAPSTS_CFLIFOVn_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOVn Position */
-#define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos) /*!< PWM_T::CAPSTS: CFLIFOVn Mask */
-
-#define PWM_CAPSTS_CFLIFOV0_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOV0 Position */
-#define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) /*!< PWM_T::CAPSTS: CFLIFOV0 Mask */
-
-#define PWM_CAPSTS_CFLIFOV1_Pos (9) /*!< PWM_T::CAPSTS: CFLIFOV1 Position */
-#define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) /*!< PWM_T::CAPSTS: CFLIFOV1 Mask */
-
-#define PWM_CAPSTS_CFLIFOV2_Pos (10) /*!< PWM_T::CAPSTS: CFLIFOV2 Position */
-#define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) /*!< PWM_T::CAPSTS: CFLIFOV2 Mask */
-
-#define PWM_CAPSTS_CFLIFOV3_Pos (11) /*!< PWM_T::CAPSTS: CFLIFOV3 Position */
-#define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) /*!< PWM_T::CAPSTS: CFLIFOV3 Mask */
-
-#define PWM_CAPSTS_CFLIFOV4_Pos (12) /*!< PWM_T::CAPSTS: CFLIFOV4 Position */
-#define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) /*!< PWM_T::CAPSTS: CFLIFOV4 Mask */
-
-#define PWM_CAPSTS_CFLIFOV5_Pos (13) /*!< PWM_T::CAPSTS: CFLIFOV5 Position */
-#define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) /*!< PWM_T::CAPSTS: CFLIFOV5 Mask */
-
-#define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */
-#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */
-
-#define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */
-#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */
-
-#define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT1: RCAPDAT Position */
-#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT1: RCAPDAT Mask */
-
-#define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT1: FCAPDAT Position */
-#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT1: FCAPDAT Mask */
-
-#define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT2: RCAPDAT Position */
-#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT2: RCAPDAT Mask */
-
-#define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT2: FCAPDAT Position */
-#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT2: FCAPDAT Mask */
-
-#define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT3: RCAPDAT Position */
-#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT3: RCAPDAT Mask */
-
-#define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT3: FCAPDAT Position */
-#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT3: FCAPDAT Mask */
-
-#define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT4: RCAPDAT Position */
-#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT4: RCAPDAT Mask */
-
-#define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT4: FCAPDAT Position */
-#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT4: FCAPDAT Mask */
-
-#define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT5: RCAPDAT Position */
-#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT5: RCAPDAT Mask */
-
-#define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT5: FCAPDAT Position */
-#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT5: FCAPDAT Mask */
-
-#define PWM_PDMACTL_CHEN0_1_Pos (0) /*!< PWM_T::PDMACTL: CHEN0_1 Position */
-#define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) /*!< PWM_T::PDMACTL: CHEN0_1 Mask */
-
-#define PWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< PWM_T::PDMACTL: CAPMOD0_1 Position */
-#define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask */
-
-#define PWM_PDMACTL_CAPORD0_1_Pos (3) /*!< PWM_T::PDMACTL: CAPORD0_1 Position */
-#define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) /*!< PWM_T::PDMACTL: CAPORD0_1 Mask */
-
-#define PWM_PDMACTL_CHSEL0_1_Pos (4) /*!< PWM_T::PDMACTL: CHSEL0_1 Position */
-#define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) /*!< PWM_T::PDMACTL: CHSEL0_1 Mask */
-
-#define PWM_PDMACTL_CHEN2_3_Pos (8) /*!< PWM_T::PDMACTL: CHEN2_3 Position */
-#define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) /*!< PWM_T::PDMACTL: CHEN2_3 Mask */
-
-#define PWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< PWM_T::PDMACTL: CAPMOD2_3 Position */
-#define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask */
-
-#define PWM_PDMACTL_CAPORD2_3_Pos (11) /*!< PWM_T::PDMACTL: CAPORD2_3 Position */
-#define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) /*!< PWM_T::PDMACTL: CAPORD2_3 Mask */
-
-#define PWM_PDMACTL_CHSEL2_3_Pos (12) /*!< PWM_T::PDMACTL: CHSEL2_3 Position */
-#define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) /*!< PWM_T::PDMACTL: CHSEL2_3 Mask */
-
-#define PWM_PDMACTL_CHEN4_5_Pos (16) /*!< PWM_T::PDMACTL: CHEN4_5 Position */
-#define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) /*!< PWM_T::PDMACTL: CHEN4_5 Mask */
-
-#define PWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< PWM_T::PDMACTL: CAPMOD4_5 Position */
-#define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask */
-
-#define PWM_PDMACTL_CAPORD4_5_Pos (19) /*!< PWM_T::PDMACTL: CAPORD4_5 Position */
-#define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) /*!< PWM_T::PDMACTL: CAPORD4_5 Mask */
-
-#define PWM_PDMACTL_CHSEL4_5_Pos (20) /*!< PWM_T::PDMACTL: CHSEL4_5 Position */
-#define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) /*!< PWM_T::PDMACTL: CHSEL4_5 Mask */
-
-#define PWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP0_1: CAPBUF Position */
-#define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) /*!< PWM_T::PDMACAP0_1: CAPBUF Mask */
-
-#define PWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP2_3: CAPBUF Position */
-#define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) /*!< PWM_T::PDMACAP2_3: CAPBUF Mask */
-
-#define PWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP4_5: CAPBUF Position */
-#define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) /*!< PWM_T::PDMACAP4_5: CAPBUF Mask */
-
-#define PWM_CAPIEN_CAPRIENn_Pos (0) /*!< PWM_T::CAPIEN: CAPRIENn Position */
-#define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) /*!< PWM_T::CAPIEN: CAPRIENn Mask */
-
-#define PWM_CAPIEN_CAPRIEN0_Pos (0) /*!< PWM_T::CAPIEN: CAPRIEN0 Position */
-#define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) /*!< PWM_T::CAPIEN: CAPRIEN0 Mask */
-
-#define PWM_CAPIEN_CAPRIEN1_Pos (1) /*!< PWM_T::CAPIEN: CAPRIEN1 Position */
-#define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) /*!< PWM_T::CAPIEN: CAPRIEN1 Mask */
-
-#define PWM_CAPIEN_CAPRIEN2_Pos (2) /*!< PWM_T::CAPIEN: CAPRIEN2 Position */
-#define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) /*!< PWM_T::CAPIEN: CAPRIEN2 Mask */
-
-#define PWM_CAPIEN_CAPRIEN3_Pos (3) /*!< PWM_T::CAPIEN: CAPRIEN3 Position */
-#define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) /*!< PWM_T::CAPIEN: CAPRIEN3 Mask */
-
-#define PWM_CAPIEN_CAPRIEN4_Pos (4) /*!< PWM_T::CAPIEN: CAPRIEN4 Position */
-#define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) /*!< PWM_T::CAPIEN: CAPRIEN4 Mask */
-
-#define PWM_CAPIEN_CAPRIEN5_Pos (5) /*!< PWM_T::CAPIEN: CAPRIEN5 Position */
-#define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) /*!< PWM_T::CAPIEN: CAPRIEN5 Mask */
-
-#define PWM_CAPIEN_CAPFIENn_Pos (8) /*!< PWM_T::CAPIEN: CAPFIENn Position */
-#define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) /*!< PWM_T::CAPIEN: CAPFIENn Mask */
-
-#define PWM_CAPIEN_CAPFIEN0_Pos (8) /*!< PWM_T::CAPIEN: CAPFIEN0 Position */
-#define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) /*!< PWM_T::CAPIEN: CAPFIEN0 Mask */
-
-#define PWM_CAPIEN_CAPFIEN1_Pos (9) /*!< PWM_T::CAPIEN: CAPFIEN1 Position */
-#define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) /*!< PWM_T::CAPIEN: CAPFIEN1 Mask */
-
-#define PWM_CAPIEN_CAPFIEN2_Pos (10) /*!< PWM_T::CAPIEN: CAPFIEN2 Position */
-#define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) /*!< PWM_T::CAPIEN: CAPFIEN2 Mask */
-
-#define PWM_CAPIEN_CAPFIEN3_Pos (11) /*!< PWM_T::CAPIEN: CAPFIEN3 Position */
-#define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) /*!< PWM_T::CAPIEN: CAPFIEN3 Mask */
-
-#define PWM_CAPIEN_CAPFIEN4_Pos (12) /*!< PWM_T::CAPIEN: CAPFIEN4 Position */
-#define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) /*!< PWM_T::CAPIEN: CAPFIEN4 Mask */
-
-#define PWM_CAPIEN_CAPFIEN5_Pos (13) /*!< PWM_T::CAPIEN: CAPFIEN5 Position */
-#define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) /*!< PWM_T::CAPIEN: CAPFIEN5 Mask */
-
-#define PWM_CAPIF_CRLIFn_Pos (0) /*!< PWM_T::CAPIF: CRLIFn Position */
-#define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos) /*!< PWM_T::CAPIF: CRLIFn Mask */
-
-#define PWM_CAPIF_CRLIF0_Pos (0) /*!< PWM_T::CAPIF: CRLIF0 Position */
-#define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) /*!< PWM_T::CAPIF: CRLIF0 Mask */
-
-#define PWM_CAPIF_CRLIF1_Pos (1) /*!< PWM_T::CAPIF: CRLIF1 Position */
-#define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) /*!< PWM_T::CAPIF: CRLIF1 Mask */
-
-#define PWM_CAPIF_CRLIF2_Pos (2) /*!< PWM_T::CAPIF: CRLIF2 Position */
-#define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) /*!< PWM_T::CAPIF: CRLIF2 Mask */
-
-#define PWM_CAPIF_CRLIF3_Pos (3) /*!< PWM_T::CAPIF: CRLIF3 Position */
-#define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) /*!< PWM_T::CAPIF: CRLIF3 Mask */
-
-#define PWM_CAPIF_CRLIF4_Pos (4) /*!< PWM_T::CAPIF: CRLIF4 Position */
-#define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) /*!< PWM_T::CAPIF: CRLIF4 Mask */
-
-#define PWM_CAPIF_CRLIF5_Pos (5) /*!< PWM_T::CAPIF: CRLIF5 Position */
-#define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) /*!< PWM_T::CAPIF: CRLIF5 Mask */
-
-#define PWM_CAPIF_CFLIFn_Pos (8) /*!< PWM_T::CAPIF: CFLIFn Position */
-#define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos) /*!< PWM_T::CAPIF: CFLIFn Mask */
-
-#define PWM_CAPIF_CFLIF0_Pos (8) /*!< PWM_T::CAPIF: CFLIF0 Position */
-#define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) /*!< PWM_T::CAPIF: CFLIF0 Mask */
-
-#define PWM_CAPIF_CFLIF1_Pos (9) /*!< PWM_T::CAPIF: CFLIF1 Position */
-#define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) /*!< PWM_T::CAPIF: CFLIF1 Mask */
-
-#define PWM_CAPIF_CFLIF2_Pos (10) /*!< PWM_T::CAPIF: CFLIF2 Position */
-#define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) /*!< PWM_T::CAPIF: CFLIF2 Mask */
-
-#define PWM_CAPIF_CFLIF3_Pos (11) /*!< PWM_T::CAPIF: CFLIF3 Position */
-#define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) /*!< PWM_T::CAPIF: CFLIF3 Mask */
-
-#define PWM_CAPIF_CFLIF4_Pos (12) /*!< PWM_T::CAPIF: CFLIF4 Position */
-#define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) /*!< PWM_T::CAPIF: CFLIF4 Mask */
-
-#define PWM_CAPIF_CFLIF5_Pos (13) /*!< PWM_T::CAPIF: CFLIF5 Position */
-#define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) /*!< PWM_T::CAPIF: CFLIF5 Mask */
-
-#define PWM_PBUF_PBUF_Pos (0) /*!< PWM_T::PBUF: PBUF Position */
-#define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos) /*!< PWM_T::PBUF: PBUF Mask */
-
-#define PWM_CMPBUF_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF: CMPBUF Position */
-#define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos) /*!< PWM_T::CMPBUF: CMPBUF Mask */
-
-#define PWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Position */
-#define PWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF0_1: FTCMPBUF Mask */
-
-#define PWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Position */
-#define PWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF2_3: FTCMPBUF Mask */
-
-#define PWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Position */
-#define PWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< PWM_T::FTCBUF4_5: FTCMPBUF Mask */
-
-#define PWM_FTCI_FTCMUn_Pos (0) /*!< PWM_T::FTCI: FTCMUn Position */
-#define PWM_FTCI_FTCMUn_Msk (0x7ul << PWM_FTCI_FTCMUn_Pos) /*!< PWM_T::FTCI: FTCMUn Mask */
-
-#define PWM_FTCI_FTCMU0_Pos (0) /*!< PWM_T::FTCI: FTCMU0 Position */
-#define PWM_FTCI_FTCMU0_Msk (0x1ul << PWM_FTCI_FTCMU0_Pos) /*!< PWM_T::FTCI: FTCMU0 Mask */
-
-#define PWM_FTCI_FTCMU2_Pos (1) /*!< PWM_T::FTCI: FTCMU2 Position */
-#define PWM_FTCI_FTCMU2_Msk (0x1ul << PWM_FTCI_FTCMU2_Pos) /*!< PWM_T::FTCI: FTCMU2 Mask */
-
-#define PWM_FTCI_FTCMU4_Pos (2) /*!< PWM_T::FTCI: FTCMU4 Position */
-#define PWM_FTCI_FTCMU4_Msk (0x1ul << PWM_FTCI_FTCMU4_Pos) /*!< PWM_T::FTCI: FTCMU4 Mask */
-
-#define PWM_FTCI_FTCMDn_Pos (8) /*!< PWM_T::FTCI: FTCMDn Position */
-#define PWM_FTCI_FTCMDn_Msk (0x7ul << PWM_FTCI_FTCMDn_Pos) /*!< PWM_T::FTCI: FTCMDn Mask */
-
-#define PWM_FTCI_FTCMD0_Pos (8) /*!< PWM_T::FTCI: FTCMD0 Position */
-#define PWM_FTCI_FTCMD0_Msk (0x1ul << PWM_FTCI_FTCMD0_Pos) /*!< PWM_T::FTCI: FTCMD0 Mask */
-
-#define PWM_FTCI_FTCMD2_Pos (9) /*!< PWM_T::FTCI: FTCMD2 Position */
-#define PWM_FTCI_FTCMD2_Msk (0x1ul << PWM_FTCI_FTCMD2_Pos) /*!< PWM_T::FTCI: FTCMD2 Mask */
-
-#define PWM_FTCI_FTCMD4_Pos (10) /*!< PWM_T::FTCI: FTCMD4 Position */
-#define PWM_FTCI_FTCMD4_Msk (0x1ul << PWM_FTCI_FTCMD4_Pos) /*!< PWM_T::FTCI: FTCMD4 Mask */
-
-/**@}*/ /* PWM_CONST */
-/**@}*/ /* end of PWM register group */
-
-
-/*---------------------- Real Time Clock Controller -------------------------*/
-/**
- @addtogroup RTC Real Time Clock Controller(RTC)
- Memory Mapped Structure for RTC Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var RTC_T::INIT
- * Offset: 0x00 RTC Initiation Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |INIT[0]/ACTIVE|RTC Active Status (Read Only)
- * | | |0 = RTC is at reset state.
- * | | |1 = RTC is at normal active state.
- * |[31:1] |INIT[31:1]|RTC Initiation
- * | | |When RTC block is powered on, RTC is at reset state.
- * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
- * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
- * | | |The INIT is a write-only field and read value will be always 0.
- * @var RTC_T::RWEN
- * Offset: 0x04 RTC Access Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |RWEN |RTC Register Access Enable Password (Write Only)
- * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
- * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
- * | | |0 = RTC register read/write Disabled.
- * | | |1 = RTC register read/write Enabled.
- * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
- * @var RTC_T::FREQADJ
- * Offset: 0x08 RTC Frequency Compensation Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |FRACTION |Fraction Part
- * | | |Formula = (fraction part of detected value) x 60.
- * | | |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
- * |[11:8] |INTEGER |Integer Part
- * @var RTC_T::TIME
- * Offset: 0x0C Time Loading Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |SEC |1-Sec Time Digit (0~9)
- * |[6:4] |TENSEC |10-Sec Time Digit (0~5)
- * |[11:8] |MIN |1-Min Time Digit (0~9)
- * |[14:12] |TENMIN |10-Min Time Digit (0~5)
- * |[19:16] |HR |1-Hour Time Digit (0~9)
- * |[21:20] |TENHR |10-Hour Time Digit (0~2)
- * @var RTC_T::CAL
- * Offset: 0x10 RTC Calendar Loading Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |DAY |1-Day Calendar Digit (0~9)
- * |[5:4] |TENDAY |10-Day Calendar Digit (0~3)
- * |[11:8] |MON |1-Month Calendar Digit (0~9)
- * |[12] |TENMON |10-Month Calendar Digit (0~1)
- * |[19:16] |YEAR |1-Year Calendar Digit (0~9)
- * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9)
- * @var RTC_T::CLKFMT
- * Offset: 0x14 Time Scale Selection Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |24HEN |24-Hour / 12-Hour Time Scale Selection
- * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
- * | | |0 = 12-hour time scale with AM and PM indication selected.
- * | | |1 = 24-hour time scale selected.
- * @var RTC_T::WEEKDAY
- * Offset: 0x18 Day of the Week Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |WEEKDAY |Day Of The Week Register
- * | | |000 = Sunday.
- * | | |001 = Monday.
- * | | |010 = Tuesday.
- * | | |011 = Wednesday.
- * | | |100 = Thursday.
- * | | |101 = Friday.
- * | | |110 = Saturday.
- * | | |111 = Reserved.
- * @var RTC_T::TALM
- * Offset: 0x1C Time Alarm Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
- * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
- * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9)
- * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
- * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9)
- * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
- * @var RTC_T::CALM
- * Offset: 0x20 Calendar Alarm Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
- * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
- * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
- * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
- * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
- * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
- * @var RTC_T::LEAPYEAR
- * Offset: 0x24 RTC Leap Year Indicator Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only)
- * | | |0 = This year is not a leap year.
- * | | |1 = This year is leap year.
- * @var RTC_T::INTEN
- * Offset: 0x28 RTC Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ALMIEN |Alarm Interrupt Enable Bit
- * | | |0 = RTC Alarm interrupt Disabled.
- * | | |1 = RTC Alarm interrupt Enabled.
- * |[1] |TICKIEN |Time Tick Interrupt Enable Bit
- * | | |0 = RTC Time Tick interrupt Disabled.
- * | | |1 = RTC Time Tick interrupt Enabled.
- * |[2] |SNPDIEN |Snoop Detection Interrupt Enable Bit
- * | | |0 = Snoop detected interrupt Disabled.
- * | | |1 = Snoop detected interrupt Enabled.
- * @var RTC_T::INTSTS
- * Offset: 0x2C RTC Interrupt Indicator Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ALMIF |RTC Alarm Interrupt Flag
- * | | |When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1.
- * | | |Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.
- * | | |0 = Alarm condition is not matched.
- * | | |1 = Alarm condition is matched.
- * | | |Note: Write 1 to clear this bit.
- * |[1] |TICKIF |RTC Time Tick Interrupt Flag
- * | | |When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1.
- * | | |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
- * | | |0 = Tick condition does not occur.
- * | | |1 = Tick condition occur.
- * | | |Note: Write 1 to clear to clear this bit.
- * |[2] |SNPDIF |Snoop Detect Interrupt Flag
- * | | |When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
- * | | |Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.
- * | | |0 = No snoop event is detected.
- * | | |1 = Snoop event is detected.
- * | | |Note: Write 1 to clear this bit.
- * @var RTC_T::TICK
- * Offset: 0x30 RTC Time Tick Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:0] |TICK |Time Tick Register
- * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
- * | | |000 = Time tick is 1 second.
- * | | |001 = Time tick is 1/2 second.
- * | | |010 = Time tick is 1/4 second.
- * | | |011 = Time tick is 1/8 second.
- * | | |100 = Time tick is 1/16 second.
- * | | |101 = Time tick is 1/32 second.
- * | | |110 = Time tick is 1/64 second.
- * | | |111 = Time tick is 1/28 second.
- * | | |Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
- * @var RTC_T::TAMSK
- * Offset: 0x34 Time Alarm Mask Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
- * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
- * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
- * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
- * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
- * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
- * @var RTC_T::CAMSK
- * Offset: 0x38 Calendar Alarm Mask Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
- * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
- * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
- * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
- * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
- * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
- * @var RTC_T::SPRCTL
- * Offset: 0x3C RTC Spare Functional Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SNPDEN |Snoop Detection Enable Bit
- * | | |0 = TAMPER pin detection is Disabled.
- * | | |1 = TAMPER pin detection is Enabled.
- * |[1] |SNPTYPE0 |Snoop Detection Level
- * | | |This bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
- * | | |0 = Low level/Falling edge detection.
- * | | |1 = High level/Rising edge detection.
- * |[2] |SPRRWEN |Spare Register Enable Bit
- * | | |0 = Spare register is Disabled.
- * | | |1 = Spare register is Enabled.
- * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
- * |[3] |SNPTYPE1 |Snoop Detection Mode
- * | | |This bit controls TAMPER pin is edge or level detection
- * | | |0 = Level detection.
- * | | |1 = Edge detection.
- * |[5] |SPRCSTS |SPR Clear Flag
- * | | |This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
- * | | |0 = Spare register content is not cleared.
- * | | |1 = Spare register content is cleared.
- * | | |Writes 1 to clear this bit.
- * |[7] |SPRRWRDY |SPR Register Ready
- * | | |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
- * | | |After user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.
- * | | |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress.
- * | | |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed.
- * | | |Note: This bit is read only and any write to it won't take any effect.
- * @var RTC_T::SPR
- * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |SPARE |Spare Register
- * | | |This field is used to store back-up information defined by user.
- * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
- * | | |Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
- * @var RTC_T::LXTCTL
- * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |LXTEN |Backup Domain 32K Oscillator Enable Bit
- * | | |0 = Oscillator is Disabled.
- * | | |1 = Oscillator is Enabled.
- * | | |This bit controls 32 kHz oscillator on/off.
- * | | |User can set either LXTEN in RTC domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator.
- * | | |If this bit is set 1, X32 kHz oscillator keep running after system power is turned off, if this bit is clear to 0, oscillator is turned off when system power is turned off.
- * |[3:1] |GAIN |Oscillator Gain Option
- * | | |User can select oscillator gain according to crystal external loading and operating temperature range.
- * | | |The larger gain value corresponding to stronger driving capability and higher power consumption.
- * | | |000 = L0 mode.
- * | | |001 = L1 mode.
- * | | |010 = L2 mode.
- * | | |011 = L3 mode.
- * | | |100 = L4 mode.
- * | | |101 = L5 mode.
- * | | |110 = L6 mode.
- * | | |111 = L7 mode (Default).
- * @var RTC_T::LXTOCTL
- * Offset: 0x104 X32KO Pin Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |OPMODE |GPF0 Operation Mode
- * | | |00 = X32KO (PF.0) is input only mode, without pull-up resistor.
- * | | |01 = X32KO (PF.0) is output push pull mode.
- * | | |10 = X32KO (PF.0) is open drain mode.
- * | | |11 = X32KO (PF.0) is input only mode with internal pull up.
- * |[2] |DOUT |IO Output Data
- * | | |0 = X32KO (PF.0) output low.
- * | | |1 = X32KO (PF.0) output high.
- * |[3] |CTLSEL |IO Pin State Backup Selection
- * | | |When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
- * | | |User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
- * | | |0 = X32KO (PF.0) pin I/O function is controlled by GPIO module.
- * | | |It becomes floating when system power is turned off.
- * | | |1 = X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
- * | | |I/O pin keeps the previous state after system power is turned off.
- * @var RTC_T::LXTICTL
- * Offset: 0x108 X32KI Pin Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |OPMODE |IO Operation Mode
- * | | |00 = X32KI (PF.1) is input only mode, without pull-up resistor.
- * | | |01 = X32KI (PF.1) is output push pull mode.
- * | | |10 = X32KI (PF.1) is open drain mode.
- * | | |11 = X32KI (PF.1) is input only mode with internal pull up.
- * |[2] |DOUT |IO Output Data
- * | | |0 = X32KI (PF.1) output low.
- * | | |1 = X32KI (PF.1) output high.
- * |[3] |CTLSEL |IO Pin State Backup Selection
- * | | |When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
- * | | |User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
- * | | |0 = X32KI (PF.1) pin I/O function is controlled by GPIO module.
- * | | |It becomes floating state when system power is turned off.
- * | | |1 = X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
- * | | |I/O pin keeps the previous state after system power is turned off.
- * @var RTC_T::TAMPCTL
- * Offset: 0x10C TAMPER Pin Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |OPMODE |IO Operation Mode
- * | | |00 = TAMPER (PF.2) is input only mode, without pull-up resistor.
- * | | |01 = TAMPER (PF.2) is output push pull mode.
- * | | |10 = TAMPER (PF.2) is open drain mode.
- * | | |11 = TAMPER (PF.2) is input only mode with internal pull up.
- * |[2] |DOUT |IO Output Data
- * | | |0 = TAMPER (PF.2) output low.
- * | | |1 = TAMPER (PF.2) output high.
- * |[3] |CTLSEL |IO Pin State Backup Selection
- * | | |When tamper function is disabled, TAMPER pin can be used as GPIO function.
- * | | |User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
- * | | |0 =TAMPER (PF.2) I/O function is controlled by GPIO module.
- * | | |It becomes floating state when system power is turned off.
- * | | |1 =TAMPER (PF.2) I/O function is controlled by VBAT power domain.
- * | | |PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
- * | | |I/O pin state keeps previous state after system power is turned off.
- */
-
- __IO uint32_t INIT; /* Offset: 0x00 RTC Initiation Register */
- __O uint32_t RWEN; /* Offset: 0x04 RTC Access Enable Register */
- __IO uint32_t FREQADJ; /* Offset: 0x08 RTC Frequency Compensation Register */
- __IO uint32_t TIME; /* Offset: 0x0C Time Loading Register */
- __IO uint32_t CAL; /* Offset: 0x10 RTC Calendar Loading Register */
- __IO uint32_t CLKFMT; /* Offset: 0x14 Time Scale Selection Register */
- __IO uint32_t WEEKDAY; /* Offset: 0x18 Day of the Week Register */
- __IO uint32_t TALM; /* Offset: 0x1C Time Alarm Register */
- __IO uint32_t CALM; /* Offset: 0x20 Calendar Alarm Register */
- __I uint32_t LEAPYEAR; /* Offset: 0x24 RTC Leap Year Indicator Register */
- __IO uint32_t INTEN; /* Offset: 0x28 RTC Interrupt Enable Register */
- __IO uint32_t INTSTS; /* Offset: 0x2C RTC Interrupt Indicator Register */
- __IO uint32_t TICK; /* Offset: 0x30 RTC Time Tick Register */
- __IO uint32_t TAMSK; /* Offset: 0x34 Time Alarm Mask Register */
- __IO uint32_t CAMSK; /* Offset: 0x38 Calendar Alarm Mask Register */
- __IO uint32_t SPRCTL; /* Offset: 0x3C RTC Spare Functional Control Register */
- __IO uint32_t SPR[20]; /* Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 */
- __I uint32_t RESERVE0[28];
- __IO uint32_t LXTCTL; /* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register */
- __IO uint32_t LXTOCTL; /* Offset: 0x104 X32KO Pin Control Register */
- __IO uint32_t LXTICTL; /* Offset: 0x108 X32KI Pin Control Register */
- __IO uint32_t TAMPCTL; /* Offset: 0x10C TAMPER Pin Control Register */
-
-} RTC_T;
-
-
-
-/**
- @addtogroup RTC_CONST RTC Bit Field Definition
- Constant Definitions for RTC Controller
-@{ */
-
-#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */
-#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */
-
-#define RTC_INIT_INIT_Pos (0) /*!< RTC_T::INIT: INIT Position */
-#define RTC_INIT_INIT_Msk (0xfffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */
-
-#define RTC_RWEN_RWEN_Pos (0) /*!< RTC_T::RWEN: RWEN Position */
-#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC_T::RWEN: RWEN Mask */
-
-#define RTC_RWEN_RWENF_Pos (16) /*!< RTC_T::RWEN: RWENF Position */
-#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC_T::RWEN: RWENF Mask */
-
-#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */
-#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */
-
-#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */
-#define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */
-
-#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */
-#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */
-
-#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */
-#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */
-
-#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */
-#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */
-
-#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */
-#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */
-
-#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */
-#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */
-
-#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */
-#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */
-
-#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */
-#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */
-
-#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */
-#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */
-
-#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */
-#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */
-
-#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */
-#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */
-
-#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */
-#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */
-
-#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */
-#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */
-
-#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */
-#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */
-
-#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */
-#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */
-
-#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */
-#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */
-
-#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */
-#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */
-
-#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */
-#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */
-
-#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */
-#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */
-
-#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */
-#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */
-
-#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */
-#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */
-
-#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */
-#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */
-
-#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */
-#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */
-
-#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */
-#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */
-
-#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */
-#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */
-
-#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */
-#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */
-
-#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */
-#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */
-
-#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */
-#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */
-
-#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */
-#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */
-
-#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */
-#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */
-
-#define RTC_INTEN_SNPDIEN_Pos (2) /*!< RTC_T::INTEN: SNPDIEN Position */
-#define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos) /*!< RTC_T::INTEN: SNPDIEN Mask */
-
-#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */
-#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */
-
-#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */
-#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */
-
-#define RTC_INTSTS_SNPDIF_Pos (2) /*!< RTC_T::INTSTS: SNPDIF Position */
-#define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos) /*!< RTC_T::INTSTS: SNPDIF Mask */
-
-#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */
-#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */
-
-#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */
-#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */
-
-#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */
-#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */
-
-#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */
-#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */
-
-#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */
-#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */
-
-#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */
-#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */
-
-#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */
-#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */
-
-#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */
-#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */
-
-#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */
-#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */
-
-#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */
-#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */
-
-#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */
-#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */
-
-#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */
-#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */
-
-#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */
-#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */
-
-#define RTC_SPRCTL_SNPDEN_Pos (0) /*!< RTC_T::SPRCTL: SNPDEN Position */
-#define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos) /*!< RTC_T::SPRCTL: SNPDEN Mask */
-
-#define RTC_SPRCTL_SNPTYPE0_Pos (1) /*!< RTC_T::SPRCTL: SNPTYPE0 Position */
-#define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos) /*!< RTC_T::SPRCTL: SNPTYPE0 Mask */
-
-#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */
-#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */
-
-#define RTC_SPRCTL_SNPTYPE1_Pos (3) /*!< RTC_T::SPRCTL: SNPTYPE1 Position */
-#define RTC_SPRCTL_SNPTYPE1_Msk (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos) /*!< RTC_T::SPRCTL: SNPTYPE1 Mask */
-
-#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */
-#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */
-
-#define RTC_SPRCTL_SPRRWRDY_Pos (7) /*!< RTC_T::SPRCTL: SPRRWRDY Position */
-#define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /*!< RTC_T::SPRCTL: SPRRWRDY Mask */
-
-#define RTC_SPR_SPARE_Pos (0) /*!< RTC_T::SPR: SPARE Position */
-#define RTC_SPR_SPARE_Msk (0xfffffffful << RTC_SPR_SPARE_Pos) /*!< RTC_T::SPR: SPARE Mask */
-
-#define RTC_LXTCTL_LXTEN_Pos (0) /*!< RTC_T::LXTCTL: LXTEN Position */
-#define RTC_LXTCTL_LXTEN_Msk (0x1ul << RTC_LXTCTL_LXTEN_Pos) /*!< RTC_T::LXTCTL: LXTEN Mask */
-
-#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */
-#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */
-
-#define RTC_LXTOCTL_OPMODE_Pos (0) /*!< RTC_T::LXTOCTL: OPMODE Position */
-#define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos) /*!< RTC_T::LXTOCTL: OPMODE Mask */
-
-#define RTC_LXTOCTL_DOUT_Pos (2) /*!< RTC_T::LXTOCTL: DOUT Position */
-#define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos) /*!< RTC_T::LXTOCTL: DOUT Mask */
-
-#define RTC_LXTOCTL_CTLSEL_Pos (3) /*!< RTC_T::LXTOCTL: CTLSEL Position */
-#define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos) /*!< RTC_T::LXTOCTL: CTLSEL Mask */
-
-#define RTC_LXTICTL_OPMODE_Pos (0) /*!< RTC_T::LXTICTL: OPMODE Position */
-#define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos) /*!< RTC_T::LXTICTL: OPMODE Mask */
-
-#define RTC_LXTICTL_DOUT_Pos (2) /*!< RTC_T::LXTICTL: DOUT Position */
-#define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos) /*!< RTC_T::LXTICTL: DOUT Mask */
-
-#define RTC_LXTICTL_CTLSEL_Pos (3) /*!< RTC_T::LXTICTL: CTLSEL Position */
-#define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos) /*!< RTC_T::LXTICTL: CTLSEL Mask */
-
-#define RTC_TAMPCTL_OPMODE_Pos (0) /*!< RTC_T::TAMPCTL: OPMODE Position */
-#define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos) /*!< RTC_T::TAMPCTL: OPMODE Mask */
-
-#define RTC_TAMPCTL_DOUT_Pos (2) /*!< RTC_T::TAMPCTL: DOUT Position */
-#define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos) /*!< RTC_T::TAMPCTL: DOUT Mask */
-
-#define RTC_TAMPCTL_CTLSEL_Pos (3) /*!< RTC_T::TAMPCTL: CTLSEL Position */
-#define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) /*!< RTC_T::TAMPCTL: CTLSEL Mask */
-
-/**@}*/ /* RTC_CONST */
-/**@}*/ /* end of RTC register group */
-
-
-/*---------------------- Smart Card Host Interface Controller -------------------------*/
-/**
- @addtogroup SC Smart Card Host Interface Controller(SC)
- Memory Mapped Structure for SC Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var SC_T::DAT
- * Offset: 0x00 SC Receiving/Transmit Holding Buffer Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |DAT |Receiving/ Transmit Holding Buffer
- * | | |Write Operation:
- * | | |By writing data to DAT, the SC will send out an 8-bit data.
- * | | |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
- * | | |Read Operation:
- * | | |By reading DAT, the SC will return an 8-bit received data.
- * @var SC_T::CTL
- * Offset: 0x04 SC Control Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SCEN |SC Engine Enable Bit
- * | | |Set this bit to 1 to enable SC operation.
- * | | |If this bit is cleared, SC will force all transition to IDLE state.
- * |[1] |RXOFF |RX Transition Disable Control
- * | | |0 = The receiver Enabled.
- * | | |1 = The receiver Disabled.
- * | | |Note:
- * | | |If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
- * |[2] |TXOFF |TX Transition Disable Control
- * | | |0 = The transceiver Enabled.
- * | | |1 = The transceiver Disabled.
- * |[3] |AUTOCEN |Auto Convention Enable Bit
- * | | |0 = Auto-convention Disabled.
- * | | |1 = Auto-convention Enabled.
- * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
- * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
- * | | |After hardware received first data and stored it at buffer,
- * | | |hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
- * | | |If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
- * |[5:4] |CONSEL |Convention Selection
- * | | |00 = Direct convention.
- * | | |01 = Reserved.
- * | | |10 = Reserved.
- * | | |11 = Inverse convention.
- * | | |Note:
- * | | |If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
- * |[7:6] |RXTRGLV |Rx Buffer Trigger Level
- * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
- * | | |00 = INTR_RDA Trigger Level with 01 Bytes.
- * | | |01 = INTR_RDA Trigger Level with 02 Bytes.
- * | | |10 = INTR_RDA Trigger Level with 03 Bytes.
- * | | |11 = Reserved.
- * |[12:8] |BGT |Block Guard Time (BGT)
- * | | |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
- * | | |This field indicates the counter for the bit length of block guard time.
- * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
- * | | |Note:
- * | | |The real block guard time is BGT + 1.
- * |[14:13] |TMRSEL |Timer Selection
- * | | |00 = All internal timer function Disabled.
- * | | |01 = Internal 24 bit timer Enabled.
- * | | |Software can configure it by setting SC_TMRCTL0 [23:0].
- * | | |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
- * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled.
- * | | |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
- * | | |SC_TMRCTL2 will be ignored in this mode.
- * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled.
- * | | |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
- * |[15] |NSB |Stop Bit Length
- * | | |This field indicates the length of stop bit.
- * | | |0 = The stop bit length is 2 ETU.
- * | | |1= The stop bit length is 1 ETU.
- * | | |Note:
- * | | |The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
- * |[18:16] |RXRTY |RX Error Retry Count Number
- * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
- * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
- * | | |Note2: This field cannot be changed when RXRTYEN enabled.
- * | | |The change flow is to disable RXRTYEN first and then fill in new retry value.
- * |[19] |RXRTYEN |RX Error Retry Enable Bit
- * | | |This bit enables receiver retry function when parity error has occurred.
- * | | |0 = RX error retry function Disabled.
- * | | |1 = RX error retry function Enabled.
- * | | |Note:
- * | | |Software must fill in the RXRTY value before enabling this bit.
- * |[22:20] |TXRTY |TX Error Retry Count Number
- * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
- * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
- * | | |Note2: This field cannot be changed when TXRTYEN enabled.
- * | | |The change flow is to disable TXRTYEN first and then fill in new retry value.
- * |[23] |TXRTYEN |TX Error Retry Enable Bit
- * | | |This bit enables transmitter retry function when parity error has occurred.
- * | | |0 = TX error retry function Disabled.
- * | | |1 = TX error retry function Enabled.
- * |[25:24] |CDDBSEL |Card Detect De-Bounce Selection
- * | | |This field indicates the card detect de-bounce selection.
- * | | |00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks.
- * | | |01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks.
- * | | |10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks.
- * | | |11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks.
- * |[26] |CDLV |Card Detect Level
- * | | |0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected.
- * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
- * | | |Note: Software must select card detect level before Smart Card engine enabled.
- * |[30] |SYNC |SYNC Flag Indicator
- * | | |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
- * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
- * | | |1 = Last value is synchronizing.
- * | | |Note: This bit is read only.
- * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
- * | | |0 = ICE debug mode acknowledgement affects SC counting.
- * | | |SC internal counter will be held while CPU is held by ICE.
- * | | |1 = ICE debug mode acknowledgement Disabled.
- * | | |SC internal counter will keep going no matter CPU is held by ICE or not.
- * @var SC_T::ALTCTL
- * Offset: 0x08 SC Alternate Control Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TXRST |TX Software Reset
- * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the TX internal state machine and pointers.
- * | | |Note:
- * | | |This bit will be auto cleared after reset is complete.
- * |[1] |RXRST |Rx Software Reset
- * | | |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the Rx internal state machine and pointers.
- * | | |Note:
- * | | |This bit will be auto cleared after reset is complete.
- * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit
- * | | |This bit enables SC controller to initiate the card by deactivation sequence
- * | | |0 = No effect.
- * | | |1 = Deactivation sequence generator Enabled.
- * | | |Note1:
- * | | |When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
- * | | |Note2:
- * | | |This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
- * | | |So don't fill this bit, TXRST, and RXRST at the same time.
- * | | |Note3:
- * | | |If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[3] |ACTEN |Activation Sequence Generator Enable Bit
- * | | |This bit enables SC controller to initiate the card by activation sequence
- * | | |0 = No effect.
- * | | |1 = Activation sequence generator Enabled.
- * | | |Note1:
- * | | |When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
- * | | |Note2:
- * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
- * | | |Note3:
- * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit
- * | | |This bit enables SC controller to initiate the card by warm reset sequence
- * | | |0 = No effect.
- * | | |1 = Warm reset sequence generator Enabled.
- * | | |Note1:
- * | | |When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
- * | | |Note2:
- * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
- * | | |Note3:
- * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit
- * | | |This bit enables Timer 0 to start counting.
- * | | |Software can fill 0 to stop it and set 1 to reload and count.
- * | | |0 = Stops counting.
- * | | |1 = Start counting.
- * | | |Note1:
- * | | |This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
- * | | |Note2:
- * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
- * | | |Note3:
- * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
- * | | |So don't fill this bit, TXRST and RXRST at the same time.
- * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit
- * | | |This bit enables Timer 1 to start counting.
- * | | |Software can fill 0 to stop it and set 1 to reload and count.
- * | | |0 = Stops counting.
- * | | |1 = Start counting.
- * | | |Note1:
- * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
- * | | |Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01.
- * | | |Note2:
- * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
- * | | |Note3:
- * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
- * | | |Note4:
- * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit
- * | | |This bit enables Timer 2 to start counting.
- * | | |Software can fill 0 to stop it and set 1 to reload and count.
- * | | |0 = Stops counting.
- * | | |1 = Start counting.
- * | | |Note1:
- * | | |This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
- * | | |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
- * | | |Note2:
- * | | |If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
- * | | |Note3:
- * | | |This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
- * | | |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
- * | | |Note4:
- * | | |If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[9:8] |INITSEL |Initial Timing Selection
- * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
- * | | |Unit: SC clock
- * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4
- * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5
- * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6
- * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit
- * | | |0 = Receiver block guard time function Disabled.
- * | | |1 = Receiver block guard time function Enabled.
- * |[13] |ACTSTS0 |Internal Timer0 Active State (Read Only)
- * | | |This bit indicates the timer counter status of timer0.
- * | | |0 = Timer0 is not active.
- * | | |1 = Timer0 is active.
- * |[14] |ACTSTS1 |Internal Timer1 Active State (Read Only)
- * | | |This bit indicates the timer counter status of timer1.
- * | | |0 = Timer1 is not active.
- * | | |1 = Timer1 is active.
- * |[15] |ACTSTS2 |Internal Timer2 Active State (Read Only)
- * | | |This bit indicates the timer counter status of timer2.
- * | | |0 = Timer2 is not active.
- * | | |1 = Timer2 is active.
- * @var SC_T::EGT
- * Offset: 0x0C SC Extend Guard Time Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |EGT |Extended Guard Time
- * | | |This field indicates the extended guard timer value.
- * | | |Note:
- * | | |The counter is ETU base and the real extended guard time is EGT.
- * @var SC_T::RXTOUT
- * Offset: 0x10 SC Receive buffer Time-out Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8:0] |RFTM |SC Receiver FIFO Time-out (ETU Base)
- * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
- * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
- * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
- * | | |Note2:
- * | | |Filling all 0 to this field indicates to disable this function.
- * @var SC_T::ETUCTL
- * Offset: 0x14 SC ETU Control Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |ETURDIV |ETU Rate Divider
- * | | |The field indicates the clock rate divider.
- * | | |The real ETU is ETURDIV + 1.
- * | | |Note:
- * | | |Software can configure this field, but this field must be greater than 0x004.
- * |[15] |CMPEN |Compensation Mode Enable Bit
- * | | |This bit enables clock compensation function.
- * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
- * | | |0 = Compensation function Disabled.
- * | | |1 = Compensation function Enabled.
- * @var SC_T::INTEN
- * Offset: 0x18 SC Interrupt Enable Control Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit
- * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
- * | | |0 = Receive data reach trigger level interrupt Disabled.
- * | | |1 = Receive data reach trigger level interrupt Enabled.
- * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit
- * | | |This field is used for transmit buffer empty interrupt enable.
- * | | |0 = Transmit buffer empty interrupt Disabled.
- * | | |1 = Transmit buffer empty interrupt Enabled.
- * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit
- * | | |This field is used for transfer error interrupt enable.
- * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
- * | | |0 = Transfer error interrupt Disabled.
- * | | |1 = Transfer error interrupt Enabled.
- * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit
- * | | |This field is used to enable TMR0 interrupt enable.
- * | | |0 = Timer0 interrupt Disabled.
- * | | |1 = Timer0 interrupt Enabled.
- * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit
- * | | |This field is used to enable the TMR1 interrupt.
- * | | |0 = Timer1 interrupt Disabled.
- * | | |1 = Timer1 interrupt Enabled.
- * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit
- * | | |This field is used for TMR2 interrupt enable.
- * | | |0 = Timer2 interrupt Disabled.
- * | | |1 = Timer2 interrupt Enabled.
- * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit
- * | | |This field is used for block guard time interrupt enable.
- * | | |0 = Block guard time Disabled.
- * | | |1 = Block guard time Enabled.
- * |[7] |CDIEN |Card Detect Interrupt Enable Bit
- * | | |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
- * | | |0 = Card detect interrupt Disabled.
- * | | |1 = Card detect interrupt Enabled.
- * |[8] |INITIEN |Initial End Interrupt Enable Bit
- * | | |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable.
- * | | |0 = Initial end interrupt Disabled.
- * | | |1 = Initial end interrupt Enabled.
- * |[9] |RXTOIF |Receiver Buffer Time-Out Interrupt Enable Bit
- * | | |This field is used for receiver buffer time-out interrupt enable.
- * | | |0 = Receiver buffer time-out interrupt Disabled.
- * | | |1 = Receiver buffer time-out interrupt Enabled.
- * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit
- * | | |This field is used for auto-convention error interrupt enable.
- * | | |0 = Auto-convention error interrupt Disabled.
- * | | |1 = Auto-convention error interrupt Enabled.
- * @var SC_T::INTSTS
- * Offset: 0x1C SC Interrupt Status Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
- * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
- * | | |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
- * | | |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
- * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
- * | | |This field is used for transmit buffer empty interrupt status flag.
- * | | |Note: This field is the status flag of transmit buffer empty state.
- * | | |If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
- * |[2] |TERRIF |Transfer Error Interrupt Status Flag (Read Only)
- * | | |This field is used for transfer error interrupt status flag.
- * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]).
- * | | |Note: This field is the status flag of
- * | | |BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]).
- * | | |So, if software wants to clear this bit, software must write 1 to each field.
- * |[3] |TMR0IF |Timer0 Interrupt Status Flag (Read Only)
- * | | |This field is used for TMR0 interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[4] |TMR1IF |Timer1 Interrupt Status Flag (Read Only)
- * | | |This field is used for TMR1 interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[5] |TMR2IF |Timer2 Interrupt Status Flag (Read Only)
- * | | |This field is used for TMR2 interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[6] |BGTIF |Block Guard Time Interrupt Status Flag (Read Only)
- * | | |This field is used for block guard time interrupt status flag.
- * | | |Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
- * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it.
- * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
- * | | |This field is used for card detect interrupt status flag.
- * | | |The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
- * | | |Note:
- * | | |This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])].
- * | | |So if software wants to clear this bit, software must write 1 to this field.
- * |[8] |INITIF |Initial End Interrupt Status Flag (Read Only)
- * | | |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[9] |RBTOIF |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
- * | | |This field is used for receiver buffer time-out interrupt status flag.
- * | | |Note: This field is the status flag of receiver buffer time-out state.
- * | | |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
- * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag (Read Only)
- * | | |This field indicates auto convention sequence error.
- * | | |If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * @var SC_T::STATUS
- * Offset: 0x20 SC Status Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXOV |RX Overflow Error Status Flag (Read Only)
- * | | |This bit is set when RX buffer overflow.
- * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[1] |RXEMPTY |Receiver Buffer Empty Status Flag(Read Only)
- * | | |This bit indicates RX buffer empty or not.
- * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
- * | | |It will be cleared when SC receives any new data.
- * |[2] |RXFULL |Receiver Buffer Full Status Flag (Read Only)
- * | | |This bit indicates RX buffer full or not.
- * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
- * |[4] |PEF |Receiver Parity Error Status Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid
- * | | |"parity bit".
- * | | |Note1:
- * | | |This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2:
- * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
- * |[5] |FEF |Receiver Frame Error Status Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
- * | | |Note1:
- * | | |This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2:
- * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
- * |[6] |BEF |Receiver Break Error Status Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
- * | | |.
- * | | |Note1:
- * | | |This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2:
- * | | |If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
- * |[8] |TXOV |TX Overflow Error Interrupt Status Flag (Read Only)
- * | | |If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to "1" by hardware.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
- * | | |This bit indicates TX buffer empty or not.
- * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
- * | | |It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
- * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
- * | | |This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
- * |[11] |CREMOVE |Card Detect Removal Status Of SC_CD Pin (Read Only)
- * | | |This bit is set whenever card has been removal.
- * | | |0 = No effect.
- * | | |1 = Card removed.
- * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
- * | | |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
- * |[12] |CINSERT |Card Detect Insert Status Of SC_CD Pin (Read Only)
- * | | |This bit is set whenever card has been inserted.
- * | | |0 = No effect.
- * | | |1 = Card insert.
- * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
- * | | |Note2: The
- * | | |card detect engine will start after SCEN (SC_CTL[0]) set.
- * |[13] |CDPINSTS |Card Detect Status Of SC_CD Pin Status (Read Only)
- * | | |This bit is the pin status flag of SC_CD
- * | | |0 = The SC_CD pin state at low.
- * | | |1 = The SC_CD pin state at high.
- * |[17:16] |RXPOINT |Receiver Buffer Pointer Status Flag (Read Only)
- * | | |This field indicates the RX buffer pointer status flag.
- * | | |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
- * | | |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
- * |[21] |RXRERR |Receiver Retry Error (Read Only)
- * | | |This bit is set by hardware when RX has any error and retries transfer.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
- * | | |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
- * |[22] |RXOVERR |Receiver Over Retry Error (Read Only)
- * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
- * |[23] |RXACT |Receiver In Active Status Flag (Read Only)
- * | | |This bit is set by hardware when RX transfer is in active.
- * | | |This bit is cleared automatically when RX transfer is finished.
- * |[25:24] |TXPOINT |Transmit Buffer Pointer Status Flag (Read Only)
- * | | |This field indicates the TX buffer pointer status flag.
- * | | |When CPU writes data into SC_DAT, TXPOINT increases one.
- * | | |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
- * |[29] |TXRERR |Transmitter Retry Error (Read Only)
- * | | |This bit is set by hardware when transmitter re-transmits.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
- * |[30] |TXOVERR |Transmitter Over Retry Error (Read Only)
- * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[31] |TXACT |Transmit In Active Status Flag (Read Only)
- * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
- * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
- * @var SC_T::PINCTL
- * Offset: 0x24 SC Pin Control State Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PWREN |SC_PWREN Pin Signal
- * | | |Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
- * | | |Write this field to drive SC_PWR pin
- * | | |Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.
- * | | |Read this field to get SC_PWR pin status.
- * | | |0 = SC_PWR pin status is low.
- * | | |1 = SC_PWR pin status is high.
- * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when operating in these modes.
- * |[1] |SCRST |SC_RST Pin Signal
- * | | |This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
- * | | |Write this field to drive SC_RST pin.
- * | | |0 = Drive SC_RST pin to low.
- * | | |1 = Drive SC_RST pin to high.
- * | | |Read this field to get SC_RST pin status.
- * | | |0 = SC_RST pin status is low.
- * | | |1 = SC_RST pin status is high.
- * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when operating in these modes.
- * |[5] |CSTOPLV |SC Clock Stop Level
- * | | |This field indicates the clock polarity control in clock stop mode.
- * | | |0 = SC_CLK stopped in low level.
- * | | |1 = SC_CLK stopped in high level.
- * |[6] |CLKKEEP |SC Clock Enable Bit
- * | | |0 = SC clock generation Disabled.
- * | | |1 = SC clock always keeps free running.
- * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when operating in these modes.
- * |[9] |SCDOUT |SC Data Output Pin
- * | | |This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.
- * | | |0 = Drive SCDATOUT pin to low.
- * | | |1 = Drive SCDATOUT pin to high.
- * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when SC is in these modes.
- * |[11] |PWRINV |SC_POW Pin Inverse
- * | | |This bit is used for inverse the SC_POW pin.
- * | | |There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]).
- * | | |PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.
- * | | |00 = SC_POW_ Pin is 0.
- * | | |01 = SC_POW _Pin is 1.
- * | | |10 = SC_POW _Pin is 1.
- * | | |11 = SC_POW_ Pin is 0.
- * | | |Note: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
- * |[12] |SCDOSTS |SC Data Pin Output Status
- * | | |This bit is the pin status of SCDATOUT
- * | | |0 = SCDATOUT pin to low.
- * | | |1 = SCDATOUT pin to high.
- * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |This bit is not allowed to program when SC is operated at these modes.
- * |[16] |DATSTS |This bit is the pin status of SC_DAT
- * | | |0 = The SC_DAT pin is low.
- * | | |1 = The SC_DAT pin is high.
- * |[17] |PWRSTS |SC_PWR Pin Signal
- * | | |This bit is the pin status of SC_PWR
- * | | |0 = SC_PWR pin to low.
- * | | |1 = SC_PWR pin to high.
- * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |This bit is not allowed to program when SC is operated at these modes.
- * |[18] |RSTSTS |SCRST Pin Signals
- * | | |This bit is the pin status of SC_RST
- * | | |0 = SC_RST pin is low.
- * | | |1 = SC_RST pin is high.
- * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |This bit is not allowed to program when SC is operated at these modes.
- * |[30] |SYNC |SYNC Flag Indicator
- * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
- * | | |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
- * | | |1 = Last value is synchronizing.
- * | | |Note: This bit is read only.
- * |[31] |LOOPBK |Loop Back Test
- * | | |0 = loop back test Disabled.
- * | | |1 = Enabling loop back test and the internal SCDATOUT will connect to internal SC_DATA_I.
- * @var SC_T::TMRCTL0
- * Offset: 0x28 SC Internal Timer Control Register 0.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[23:0] |CNT |Timer 0 Counter Value (ETU Base)
- * | | |This field indicates the internal timer operation values.
- * |[27:24] |OPMODE |Timer 0 Operation Mode Selection
- * | | |This field indicates the internal 24-bit timer operation selection.
- * | | |Refer to 6.17.5.4 for programming Timer0
- * @var SC_T::TMRCTL1
- * Offset: 0x2C SC Internal Timer Control Register 1.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CNT |Timer 1 Counter Value (ETU Base)
- * | | |This field indicates the internal timer operation values.
- * |[27:24] |OPMODE |Timer 1 Operation Mode Selection
- * | | |This field indicates the internal 8-bit timer operation selection.
- * | | |Refer to 6.17.5.4 for programming Timer1
- * @var SC_T::TMRCTL2
- * Offset: 0x30 SC Internal Timer Control Register 2.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CNT |Timer 2 Counter Value (ETU Base)
- * | | |This field indicates the internal timer operation values.
- * |[27:24] |OPMODE |Timer 2 Operation Mode Selection
- * | | |This field indicates the internal 8-bit timer operation selection
- * | | |Refer to 6.17.5.4 for programming Timer2
- * @var SC_T::UARTCTL
- * Offset: 0x34 SC UART Mode Control Register.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |UARTEN |UART Mode Enable Bit
- * | | |0 = Smart Card mode.
- * | | |1 = UART mode.
- * | | |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
- * | | |Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00.
- * | | |Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
- * |[5:4] |WLS10 |Word Length Selection
- * | | |00 = Word length is 8 bits.
- * | | |01 = Word length is 7 bits.
- * | | |10 = Word length is 6 bits.
- * | | |11 = Word length is 5 bits.
- * | | |Note: In smart card mode, this WLS must be '00'
- * |[6] |PBOFF |Parity Bit Disable Control
- * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
- * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
- * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
- * |[7] |OPE |Odd Parity Enable Bit
- * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
- * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
- * | | |Note: This bit has effect only when PBOFF bit is '0'.
- * @var SC_T::TMRDAT0
- * Offset: 0x38 SC Timer Current Data Register A.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[23:0] |CNT0 |Timer0 Current Data Value (Read Only)
- * | | |This field indicates the current count values of timer0.
- * @var SC_T::TMRDAT1_2
- * Offset: 0x3C SC Timer Current Data Register B.
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CNT1 |Timer1 Current Data Value (Read Only)
- * | | |This field indicates the current count values of timer1.
- * |[15:8] |CNT2 |Timer2 Current Data Value (Read Only)
- * | | |This field indicates the current count values of timer2.
- */
-
- __IO uint32_t DAT; /* Offset: 0x00 SC Receiving/Transmit Holding Buffer Register. */
- __IO uint32_t CTL; /* Offset: 0x04 SC Control Register. */
- __IO uint32_t ALTCTL; /* Offset: 0x08 SC Alternate Control Register. */
- __IO uint32_t EGT; /* Offset: 0x0C SC Extend Guard Time Register. */
- __IO uint32_t RXTOUT; /* Offset: 0x10 SC Receive buffer Time-out Register. */
- __IO uint32_t ETUCTL; /* Offset: 0x14 SC ETU Control Register. */
- __IO uint32_t INTEN; /* Offset: 0x18 SC Interrupt Enable Control Register. */
- __IO uint32_t INTSTS; /* Offset: 0x1C SC Interrupt Status Register. */
- __IO uint32_t STATUS; /* Offset: 0x20 SC Status Register. */
- __IO uint32_t PINCTL; /* Offset: 0x24 SC Pin Control State Register. */
- __IO uint32_t TMRCTL0; /* Offset: 0x28 SC Internal Timer Control Register 0. */
- __IO uint32_t TMRCTL1; /* Offset: 0x2C SC Internal Timer Control Register 1. */
- __IO uint32_t TMRCTL2; /* Offset: 0x30 SC Internal Timer Control Register 2. */
- __IO uint32_t UARTCTL; /* Offset: 0x34 SC UART Mode Control Register. */
- __I uint32_t TMRDAT0; /* Offset: 0x38 SC Timer Current Data Register A. */
- __I uint32_t TMRDAT1_2; /* Offset: 0x3C SC Timer Current Data Register B. */
-
-} SC_T;
-
-
-
-/**
- @addtogroup SC_CONST SC Bit Field Definition
- Constant Definitions for SC Controller
-@{ */
-
-#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */
-#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */
-
-#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */
-#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */
-
-#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */
-#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */
-
-#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */
-#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */
-
-#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */
-#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */
-
-#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */
-#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */
-
-#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */
-#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */
-
-#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */
-#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */
-
-#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */
-#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */
-
-#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */
-#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */
-
-#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */
-#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */
-
-#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */
-#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */
-
-#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */
-#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */
-
-#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */
-#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */
-
-#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */
-#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */
-
-#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */
-#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */
-
-#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */
-#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */
-
-#define SC_CTL_ICEDEBUG_Pos (31) /*!< SC_T::CTL: ICEDEBUG Position */
-#define SC_CTL_ICEDEBUG_Msk (0x1ul << SC_CTL_ICEDEBUG_Pos) /*!< SC_T::CTL: ICEDEBUG Mask */
-
-#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */
-#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */
-
-#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */
-#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */
-
-#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */
-#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */
-
-#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */
-#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */
-
-#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */
-#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */
-
-#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */
-#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */
-
-#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */
-#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */
-
-#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */
-#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */
-
-#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */
-#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */
-
-#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */
-#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */
-
-#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */
-#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */
-
-#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */
-#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */
-
-#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */
-#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */
-
-#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */
-#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */
-
-#define SC_ALTCTL_OUTSEL_Pos (16) /*!< SC_T::ALTCTL: OUTSEL Position */
-#define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos) /*!< SC_T::ALTCTL: OUTSEL Mask */
-
-#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */
-#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */
-
-#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */
-#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */
-
-#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV_ Position */
-#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV_ Mask */
-
-#define SC_ETUCTL_CMPEN_Pos (15) /*!< SC_T::ETUCTL: CMPEN_ Position */
-#define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /*!< SC_T::ETUCTL: CMPEN_ Mask */
-
-#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */
-#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */
-
-#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */
-#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */
-
-#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */
-#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */
-
-#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN_Position */
-#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */
-
-#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */
-#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */
-
-#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */
-#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */
-
-#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */
-#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */
-
-#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */
-#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */
-
-#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */
-#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */
-
-#define SC_INTEN_RXTOIF_Pos (9) /*!< SC_T::INTEN: RXTOIF Position */
-#define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /*!< SC_T::INTEN: RXTOIF Mask */
-
-#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */
-#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */
-
-#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */
-#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */
-
-#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */
-#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */
-
-#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */
-#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */
-
-#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */
-#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */
-
-#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */
-#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */
-
-#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */
-#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */
-
-#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */
-#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */
-
-#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */
-#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */
-
-#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */
-#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */
-
-#define SC_INTSTS_RBTOIF_Pos (9) /*!< SC_T::INTSTS: RBTOIF Position */
-#define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /*!< SC_T::INTSTS: RBTOIF Mask */
-
-#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */
-#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */
-
-#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXO Position */
-#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXO Mask */
-
-#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */
-#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */
-
-#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */
-#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */
-
-#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */
-#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */
-
-#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */
-#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */
-
-#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */
-#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */
-
-#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */
-#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */
-
-#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */
-#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */
-
-#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */
-#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */
-
-#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */
-#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */
-
-#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */
-#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */
-
-#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */
-#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */
-
-#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */
-#define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */
-
-#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */
-#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */
-
-#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */
-#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */
-
-#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */
-#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Msk */
-
-#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */
-#define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Msk */
-
-#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */
-#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Msk */
-
-#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR_ Position */
-#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR_ Msk */
-
-#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */
-#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Msk */
-
-#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */
-#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Msk */
-
-#define SC_PINCTL_SCRST_Pos (1) /*!< SC_T::PINCTL: SCRST Position */
-#define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /*!< SC_T::PINCTL: SCRST Msk */
-
-#define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */
-#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Msk */
-
-#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */
-#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Msk */
-
-#define SC_PINCTL_SCDOUT_Pos (9) /*!< SC_T::PINCTL: SCDOUT Position */
-#define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /*!< SC_T::PINCTL: SCDOUT Msk */
-
-#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */
-#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Msk */
-
-#define SC_PINCTL_SCDOSTS_Pos (12) /*!< SC_T::PINCTL: SCDOSTS Position */
-#define SC_PINCTL_SCDOSTS_Msk (0x1ul << SC_PINCTL_SCDOSTS_Pos) /*!< SC_T::PINCTL: SCDOSTS Msk */
-
-#define SC_PINCTL_DATSTS_Pos (16) /*!< SC_T::PINCTL: DATSTS Position */
-#define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /*!< SC_T::PINCTL: DATSTS Msk */
-
-#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */
-#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Msk */
-
-#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */
-#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Msk */
-
-#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */
-#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Msk */
-
-#define SC_PINCTL_LOOPBK_Pos (31) /*!< SC_T::PINCTL: LOOPBK Position */
-#define SC_PINCTL_LOOPBK_Msk (0x1ul << SC_PINCTL_LOOPBK_Pos) /*!< SC_T::PINCTL: LOOPBK Msk */
-
-#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */
-#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Msk */
-
-#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */
-#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Msk */
-
-#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */
-#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Msk */
-
-#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */
-#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Msk */
-
-#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */
-#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Msk */
-
-#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */
-#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Msk */
-
-#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */
-#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Msk */
-
-#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */
-#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS10_Pos) /*!< SC_T::UARTCTL: WLS Msk */
-
-#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */
-#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Msk */
-
-#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */
-#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Msk */
-
-#define SC_TMRDAT0_CNT0_Pos (0) /*!< SC_T::TMRDAT0: CNT0 Position */
-#define SC_TMRDAT0_CNT0_Msk (0xfffffful << SC_TMRDAT0_CNT0_Pos) /*!< SC_T::TMRDAT0: CNT0 Msk */
-
-#define SC_TMRDAT1_2_CNT1_Pos (0) /*!< SC_T::TMRDAT1_2: CNT1 Position */
-#define SC_TMRDAT1_2_CNT1_Msk (0xfful << SC_TMRDAT1_2_CNT1_Pos) /*!< SC_T::TMRDAT1_2: CNT1 Msk */
-
-#define SC_TMRDAT1_2_CNT2_Pos (8) /*!< SC_T::TMRDAT1_2: CNT2 Position */
-#define SC_TMRDAT1_2_CNT2_Msk (0xfful << SC_TMRDAT1_2_CNT2_Pos) /*!< SC_T::TMRDAT1_2: CNT2 Msk */
-
-/**@}*/ /* SC_CONST */
-/**@}*/ /* end of SC register group */
-
-
-/*---------------------- Serial Peripheral Interface Controller -------------------------*/
-/**
- @addtogroup SPI Serial Peripheral Interface Controller(SPI)
- Memory Mapped Structure for SPI Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var SPI_T::CTL
- * Offset: 0x00 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SPIEN |SPI Transfer Control Enable Bit
- * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
- * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
- * | | |0 = Transfer control Disabled.
- * | | |1 = Transfer control Enabled.
- * | | |Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
- * |[1] |RXNEG |Receive On Negative Edge
- * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock.
- * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock.
- * |[2] |TXNEG |Transmit On Negative Edge
- * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
- * | | |1 = Transmitted data output signal is changed on the falling edge of SP bus clock.
- * |[3] |CLKPOL |Clock Polarity
- * | | |0 = SPI bus clock is idle low.
- * | | |1 = SPI bus clock is idle high.
- * |[7:4] |SUSPITV |Suspend Interval (Master Only)
- * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
- * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
- * | | |The default value is 0x3.
- * | | |The period of the suspend interval is obtained according to the following equation.
- * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
- * | | |Example:
- * | | |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
- * | | |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
- * | | |...
- * | | |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
- * | | |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
- * |[12:8] |DWIDTH |Data Width
- * | | |This field specifies how many bits can be transmitted / received in one transaction.
- * | | |The minimum bit length is 8 bits and can up to 32 bits.
- * | | |DWIDTH = 0x08 ... 8 bits.
- * | | |DWIDTH = 0x09 ... 9 bits.
- * | | |...
- * | | |DWIDTH = 0x1F ... 31 bits.
- * | | |DWIDTH = 0x00 ... 32 bits.
- * |[13] |LSB |Send LSB First
- * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
- * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
- * |[16] |TWOBIT |2-Bit Transfer Mode Enable Bit (Only Supported in SPI0)
- * | | |0 = 2-Bit Transfer mode Disabled.
- * | | |1 = 2-Bit Transfer mode Enabled.
- * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
- * | | |serial transmitted bit data is from the second FIFO buffer data.
- * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
- * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
- * | | |0 = SPI unit transfer interrupt Disabled.
- * | | |1 = SPI unit transfer interrupt Enabled.
- * |[18] |SLAVE |Slave Mode Control
- * | | |0 = Master mode.
- * | | |1 = Slave mode.
- * |[19] |REORDER |Byte Reorder Function Enable Bit
- * | | |0 = Byte Reorder function Disabled.
- * | | |1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte.
- * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
- * | | |Note:
- * | | |1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
- * | | |2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
- * |[20] |QDIODIR |Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0)
- * | | |0 = Quad or Dual Input mode.
- * | | |1 = Quad or Dual Output mode.
- * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0)
- * | | |0 = Dual I/O mode Disabled.
- * | | |1 = Dual I/O mode Enabled.
- * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0)
- * | | |0 = Quad I/O mode Disabled.
- * | | |1 = Quad I/O mode Enabled.
- * @var SPI_T::CLKDIV
- * Offset: 0x04 Clock Divider Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |DIVIDER |Clock Divider
- * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
- * | | |The frequency is obtained according to the following equation.
- * | | | fspi_eclk = fspi_clock_src / (DIVIDER + 1)
- * | | |where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
- * @var SPI_T::SSCTL
- * Offset: 0x08 Slave Select Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SS |Slave Selection Control (Master Only)
- * | | |If AUTOSS bit is cleared to 0,
- * | | |0 = set the SPIn_SS line to inactive state.
- * | | |1 = set the SPIn_SS line to active state
- * | | |If the AUTOSS bit is set to 1,
- * | | |0 = Keep the SPIn_SS line at inactive state.
- * | | |1 = SPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
- * | | |The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]).
- * |[2] |SSACTPOL |Slave Selection Active Polarity
- * | | |This bit defines the active polarity of slave selection signal (SPIn_SS).
- * | | |0 = The slave selection signal SPIn_SS is active low.
- * | | |1 = The slave selection signal SPIn_SS is active high.
- * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
- * | | |0 = Automatic slave selection function Disabled.
- * | | |Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]).
- * | | |1 = Automatic slave selection function Enabled.
- * |[4] |SLV3WIRE |Slave 3-Wire Mode Enable Bit
- * | | |Slave 3-wire mode is only available in SPI0.
- * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
- * | | |0 = 4-wire bi-direction interface.
- * | | |1 = 3-wire bi-direction interface.
- * |[5] |SLVTOIEN |Slave Mode Time-Out Interrupt Enable Bit (Only Supported in SPI0)
- * | | |0 = Slave mode time-out interrupt Disabled.
- * | | |1 = Slave mode time-out interrupt Enabled.
- * |[6] |SLVTORST |Slave Mode Time-Out Reset Control (Only Supported in SPI0)
- * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
- * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
- * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit
- * | | |0 = Slave mode bit count error interrupt Disabled.
- * | | |1 = Slave mode bit count error interrupt Enabled.
- * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit
- * | | |0 = Slave mode TX under run interrupt Disabled.
- * | | |1 = Slave mode TX under run interrupt Enabled.
- * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit
- * | | |0 = Slave select active interrupt Disabled.
- * | | |1 = Slave select active interrupt Enabled.
- * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
- * | | |0 = Slave select inactive interrupt Disabled.
- * | | |1 = Slave select inactive interrupt Enabled.
- * |[31:16] |SLVTOCNT |Slave Mode Time-Out Period (Only Supported in SPI0)
- * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
- * | | |The clock source of the time-out counter is Slave peripheral clock.
- * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
- * @var SPI_T::PDMACTL
- * Offset: 0x0C SPI PDMA Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TXPDMAEN |Transmit PDMA Enable Bit
- * | | |0 = Transmit PDMA function Disabled.
- * | | |1 = Transmit PDMA function Enabled.
- * | | |Note: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
- * | | |User can enable TX PDMA function firstly or enable both functions simultaneously.
- * |[1] |RXPDMAEN |Receive PDMA Enable Bit
- * | | |0 = Receiver PDMA function Disabled.
- * | | |1 = Receiver PDMA function Enabled.
- * |[2] |PDMARST |PDMA Reset
- * | | |0 = No effect.
- * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
- * @var SPI_T::FIFOCTL
- * Offset: 0x10 SPI FIFO Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXRST |Receive Reset
- * | | |0 = No effect.
- * | | |1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
- * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
- * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
- * | | |Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
- * |[1] |TXRST |Transmit Reset
- * | | |0 = No effect.
- * | | |1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
- * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
- * | | |User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
- * | | |Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
- * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit
- * | | |0 = RX FIFO threshold interrupt Disabled.
- * | | |1 = RX FIFO threshold interrupt Enabled.
- * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit
- * | | |0 = TX FIFO threshold interrupt Disabled.
- * | | |1 = TX FIFO threshold interrupt Enabled.
- * |[4] |RXTOIEN |Slave Receive Time-Out Interrupt Enable Bit
- * | | |0 = Receive time-out interrupt Disabled.
- * | | |1 = Receive time-out interrupt Enabled.
- * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
- * | | |0 = Receive FIFO overrun interrupt Disabled.
- * | | |1 = Receive FIFO overrun interrupt Enabled.
- * |[6] |TXUFPOL |TX Underflow Data Polarity
- * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
- * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
- * | | |Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
- * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit
- * | | |In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.
- * | | |0 = Slave TX underflow interrupt Disabled.
- * | | |1 = Slave TX underflow interrupt Enabled.
- * |[8] |RXFBCLR |Receive FIFO Buffer Clear
- * | | |0 = No effect.
- * | | |1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
- * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
- * | | |Note: The RX shift register will not be cleared.
- * |[9] |TXFBCLR |Transmit FIFO Buffer Clear
- * | | |0 = No effect.
- * | | |1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
- * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
- * | | |Note: The TX shift register will not be cleared.
- * |[26:24] |RXTH |Receive FIFO Threshold
- * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
- * | | |In SPI0, RXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[25:24]).
- * |[30:28] |TXTH |Transmit FIFO Threshold
- * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
- * | | |In SPI0, TXTH is a 3-bit wide configuration; in SPI1 and SPI2, 2-bit wide only (SPI_FIFOCTL[29:28]).
- * @var SPI_T::STATUS
- * Offset: 0x14 SPI Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSY |Busy Status (Read Only)
- * | | |0 = SPI controller is in idle state.
- * | | |1 = SPI controller is in busy state.
- * | | |The following listing are the bus busy conditions:
- * | | |a. SPI_CTL[0] = 1 and the TXEMPTY = 0.
- * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
- * | | |c. For SPI Slave mode, the SPI_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
- * | | |d. For SPI Slave mode, the SPI_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
- * |[1] |UNITIF |Unit Transfer Interrupt Flag
- * | | |0 = No transaction has been finished since this bit was cleared to 0.
- * | | |1 = SPI controller has finished one unit transfer.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[2] |SSACTIF |Slave Select Active Interrupt Flag
- * | | |0 = Slave select active interrupt was cleared or not occurred.
- * | | |1 = Slave select active interrupt event occurred.
- * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
- * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag
- * | | |0 = Slave select inactive interrupt was cleared or not occurred.
- * | | |1 = Slave select inactive interrupt event occurred.
- * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
- * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
- * | | |0 = The slave select line status is 0.
- * | | |1 = The slave select line status is 1.
- * | | |Note: This bit is only available in Slave mode.
- * | | |If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
- * |[5] |SLVTOIF |Slave Time-Out Interrupt Flag (Only Supported in SPI0)
- * | | |When the Slave Select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started.
- * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
- * | | |0 = Slave time-out is not active.
- * | | |1 = Slave time-out is active.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag
- * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
- * | | |0 = No Slave mode bit count error event.
- * | | |1 = Slave mode bit count error event occurs.
- * | | |Note: If the slave select active but there is no any bus clock input, the SLVBCEIF also active when the slave select goes to inactive state.
- * | | |This bit will be cleared by writing 1 to it.
- * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag
- * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
- * | | |0 = No Slave TX under run event.
- * | | |1 = Slave TX under run occurs.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
- * | | |0 = Receive FIFO buffer is not empty.
- * | | |1 = Receive FIFO buffer is empty.
- * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
- * | | |0 = Receive FIFO buffer is not full.
- * | | |1 = Receive FIFO buffer is full.
- * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
- * | | |0 = The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH.
- * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
- * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
- * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
- * | | |0 = No FIFO is over run.
- * | | |1 = Receive FIFO over run.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
- * | | |0 = No receive FIFO time-out event.
- * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
- * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[15] |SPIENSTS |SPI Enable Status (Read Only)
- * | | |0 = The SPI controller is disabled.
- * | | |1 = The SPI controller is enabled.
- * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
- * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
- * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
- * | | |0 = Transmit FIFO buffer is not empty.
- * | | |1 = Transmit FIFO buffer is empty.
- * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
- * | | |0 = Transmit FIFO buffer is not full.
- * | | |1 = Transmit FIFO buffer is full.
- * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
- * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
- * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
- * |[19] |TXUFIF |TX Underflow Interrupt Flag
- * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
- * | | |0 = No effect.
- * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
- * | | |Note 1: This bit will be cleared by writing 1 to it.
- * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
- * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
- * | | |0 = The reset function of TXRST or RXRST is done.
- * | | |1 = Doing the reset function of TXRST or RXRST.
- * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
- * | | |User can check the status of this bit to monitor the reset function is doing or done.
- * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only)
- * | | |This bit field indicates the valid data count of receive FIFO buffer.
- * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only)
- * | | |This bit field indicates the valid data count of transmit FIFO buffer.
- * @var SPI_T::TX
- * Offset: 0x20 Data Transmit Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |TX |Data Transmit Register
- * | | |The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer.
- * | | |The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]).
- * | | |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
- * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
- * | | |Note: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles after user writes to this register.
- * @var SPI_T::RX
- * Offset: 0x30 Data Receive Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |RX |Data Receive Register
- * | | |There are 8-/4-level FIFO buffers in this controller.
- * | | |The data receive register holds the data received from SPI data input pin.
- * | | |If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
- * | | |This is a read only register.
- * @var SPI_T::I2SCTL
- * Offset: 0x60 I2S Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |I2SEN |I2S Controller Enable Bit
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |Note: If enable this bit, I2Sn_BCLK will start to output in master mode.
- * |[1] |TXEN |Transmit Enable Bit
- * | | |0 = Data transmit Disabled.
- * | | |1 = Data transmit Enabled.
- * |[2] |RXEN |Receive Enable Bit
- * | | |0 = Data receiving Disabled.
- * | | |1 = Data receiving Enabled.
- * |[3] |MUTE |Transmit Mute Enable Bit
- * | | |0 = Transmit data is shifted from buffer.
- * | | |1= Transmit channel zero.
- * |[5:4] |WDWIDTH |Word Width
- * | | |00 = data is 8-bit.
- * | | |01 = data is 16-bit.
- * | | |10 = data is 24-bit.
- * | | |11 = data is 32-bit.
- * |[6] |MONO |Monaural Data
- * | | |0 = Data is stereo format.
- * | | |1 = Data is monaural format.
- * |[7] |ORDER |Stereo Data Order In FIFO
- * | | |0 = Left channel data at high byte.
- * | | |1 = Left channel data at low byte.
- * |[8] |SLAVE |Slave Mode
- * | | |I2S can operate as master or slave.
- * | | |For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M451 series to Audio CODEC chip.
- * | | |In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip.
- * | | |0 = Master mode.
- * | | |1 = Slave mode.
- * |[15] |MCLKEN |Master Clock Enable Bit
- * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.
- * | | |0 = Master clock Disabled.
- * | | |1 = Master clock Enabled.
- * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit
- * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1.
- * | | |This function is only available in transmit operation.
- * | | |0 = Right channel zero cross detection Disabled.
- * | | |1 = Right channel zero cross detection Enabled.
- * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit
- * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1.
- * | | |This function is only available in transmit operation.
- * | | |0 = Left channel zero cross detection Disabled.
- * | | |1 = Left channel zero cross detection Enabled.
- * |[23] |RXLCH |Receive Left Channel Enable Bit
- * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
- * | | |0 = Receive right channel data in Mono mode.
- * | | |1 = Receive left channel data in Mono mode.
- * |[24] |RZCIEN |Right Channel Zero-Cross Interrupt Enable Bit
- * | | |Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[25] |LZCIEN |Left Channel Zero-Cross Interrupt Enable Bit
- * | | |Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[29:28] |FORMAT |Data Format Selection
- * | | |00 = I2S data format.
- * | | |01 = MSB justified data format.
- * | | |10 = PCM mode A.
- * | | |11 = PCM mode B.
- * @var SPI_T::I2SCLK
- * Offset: 0x64 I2S Clock Divider Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |MCLKDIV |Master Clock Divider
- * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
- * | | |The master clock rate, F_MCLK, is determined by the following expressions.
- * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
- * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
- * | | |F_I2SCLK is the frequency of I2S peripheral clock.
- * | | |In general, the master clock rate is 256 times sampling clock rate.
- * |[16:8] |BCLKDIV |Bit Clock Divider
- * | | |The I2S controller will generate bit clock in Master mode.
- * | | |The bit clock rate, F_BCLK, is determined by the following expression.
- * | | |F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
- * @var SPI_T::I2SSTS
- * Offset: 0x68 I2S Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4] |RIGHT |Right Channel (Read Only)
- * | | |This bit indicates the current transmit data is belong to which channel.
- * | | |0 = Left channel.
- * | | |1 = Right channel.
- * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
- * | | |0 = Receive FIFO buffer is not empty.
- * | | |1 = Receive FIFO buffer is empty.
- * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
- * | | |0 = Receive FIFO buffer is not full.
- * | | |1 = Receive FIFO buffer is full.
- * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only)
- * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
- * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
- * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
- * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag
- * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[12] |RXTOIF |Receive Time-Out Interrupt Flag
- * | | |0 = No receive FIFO time-out event.
- * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
- * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[15] |I2SENSTS |I2S Enable Status (Read Only)
- * | | |0 = The SPI/I2S control logic is disabled.
- * | | |1 = The SPI/I2S control logic is enabled.
- * | | |Note: The SPI peripheral clock is asynchronous with the system clock.
- * | | |In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
- * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
- * | | |0 = Transmit FIFO buffer is not empty.
- * | | |1 = Transmit FIFO buffer is empty.
- * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
- * | | |0 = Transmit FIFO buffer is not full.
- * | | |1 = Transmit FIFO buffer is full.
- * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
- * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
- * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
- * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
- * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag
- * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input,
- * | | | the output data depends on the setting of TXUFPOL and this bit will be set to 1.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag
- * | | |0 = No zero cross event occurred on right channel.
- * | | |1 = Zero cross event occurred on right channel.
- * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag
- * | | |0 = No zero cross event occurred on left channel.
- * | | |1 = Zero cross event occurred on left channel.
- * |[23] |TXRXRST |TX or RX Reset Status (Read Only)
- * | | |0 = The reset function of TXRST or RXRST is done.
- * | | |1 = Doing the reset function of TXRST or RXRST.
- * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles.
- * | | |User can check the status of this bit to monitor the reset function is doing or done.
- * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only)
- * | | |This bit field indicates the valid data count of receive FIFO buffer.
- * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only)
- * | | |This bit field indicates the valid data count of transmit FIFO buffer.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 Control Register */
- __IO uint32_t CLKDIV; /* Offset: 0x04 Clock Divider Register */
- __IO uint32_t SSCTL; /* Offset: 0x08 Slave Select Control Register */
- __IO uint32_t PDMACTL; /* Offset: 0x0C SPI PDMA Control Register */
- __IO uint32_t FIFOCTL; /* Offset: 0x10 SPI FIFO Control Register */
- __IO uint32_t STATUS; /* Offset: 0x14 SPI Status Register */
- __I uint32_t RESERVE0[2];
- __O uint32_t TX; /* Offset: 0x20 Data Transmit Register */
- __I uint32_t RESERVE1[3];
- __I uint32_t RX; /* Offset: 0x30 Data Receive Register */
- __I uint32_t RESERVE2[11];
- __IO uint32_t I2SCTL; /* Offset: 0x60 I2S Control Register */
- __IO uint32_t I2SCLK; /* Offset: 0x64 I2S Clock Divider Control Register */
- __IO uint32_t I2SSTS; /* Offset: 0x68 I2S Status Register */
-
-} SPI_T;
-
-
-
-/**
- @addtogroup SPI_CONST SPI Bit Field Definition
- Constant Definitions for SPI Controller
-@{ */
-
-#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */
-#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */
-
-#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */
-#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */
-
-#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */
-#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */
-
-#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */
-#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */
-
-#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */
-#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */
-
-#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */
-#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */
-
-#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */
-#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */
-
-#define SPI_CTL_TWOBIT_Pos (16) /*!< SPI_T::CTL: TWOBIT Position */
-#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI_T::CTL: TWOBIT Mask */
-
-#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */
-#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */
-
-#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */
-#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */
-
-#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */
-#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */
-
-#define SPI_CTL_QDIODIR_Pos (20) /*!< SPI_T::CTL: QDIODIR Position */
-#define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /*!< SPI_T::CTL: QDIODIR Mask */
-
-#define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI_T::CTL: DUALIOEN Position */
-#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI_T::CTL: DUALIOEN Mask */
-
-#define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI_T::CTL: QUADIOEN Position */
-#define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI_T::CTL: QUADIOEN Mask */
-
-#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */
-#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */
-
-#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */
-#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */
-
-#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */
-#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */
-
-#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */
-#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */
-
-#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */
-#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */
-
-#define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI_T::SSCTL: SLVTOIEN Position */
-#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI_T::SSCTL: SLVTOIEN Mask */
-
-#define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI_T::SSCTL: SLVTORST Position */
-#define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI_T::SSCTL: SLVTORST Mask */
-
-#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */
-#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */
-
-#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */
-#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */
-
-#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */
-#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */
-
-#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */
-#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */
-
-#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI_T::SSCTL: SLVTOCNT Position */
-#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI_T::SSCTL: SLVTOCNT Mask */
-
-#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */
-#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */
-
-#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */
-#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */
-
-#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */
-#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */
-
-#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */
-#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */
-
-#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */
-#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */
-
-#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */
-#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */
-
-#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */
-#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */
-
-#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */
-#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */
-
-#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */
-#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */
-
-#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */
-#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */
-
-#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */
-#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */
-
-#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */
-#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */
-
-#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */
-#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */
-
-#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */
-#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */
-
-#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */
-#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */
-
-#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */
-#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */
-
-#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */
-#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */
-
-#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */
-#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */
-
-#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */
-#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */
-
-#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */
-#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */
-
-#define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI_T::STATUS: SLVTOIF Position */
-#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI_T::STATUS: SLVTOIF Mask */
-
-#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */
-#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */
-
-#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */
-#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */
-
-#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */
-#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */
-
-#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */
-#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */
-
-#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */
-#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */
-
-#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */
-#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */
-
-#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */
-#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */
-
-#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */
-#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */
-
-#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */
-#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */
-
-#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */
-#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */
-
-#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */
-#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */
-
-#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */
-#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */
-
-#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */
-#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */
-
-#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */
-#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */
-
-#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */
-#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */
-
-#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */
-#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */
-
-#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */
-#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */
-
-#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */
-#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */
-
-#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */
-#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */
-
-#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */
-#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */
-
-#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */
-#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */
-
-#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */
-#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */
-
-#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */
-#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */
-
-#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */
-#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */
-
-#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */
-#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */
-
-#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */
-#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */
-
-#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */
-#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */
-
-#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */
-#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */
-
-#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */
-#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */
-
-#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */
-#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */
-
-#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */
-#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */
-
-#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */
-#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */
-
-#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */
-#define SPI_I2SCLK_MCLKDIV_Msk (0x3ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */
-
-#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */
-#define SPI_I2SCLK_BCLKDIV_Msk (0x1fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */
-
-#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */
-#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */
-
-#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */
-#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */
-
-#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */
-#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */
-
-#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */
-#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */
-
-#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */
-#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */
-
-#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */
-#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */
-
-#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */
-#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */
-
-#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */
-#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */
-
-#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */
-#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */
-
-#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */
-#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */
-
-#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */
-#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */
-
-#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */
-#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */
-
-#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */
-#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */
-
-#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */
-#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */
-
-#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */
-#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */
-
-#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */
-#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */
-
-/**@}*/ /* SPI_CONST */
-/**@}*/ /* end of SPI register group */
-
-
-/*---------------------- System Manger Controller -------------------------*/
-/**
- @addtogroup SYS System Manger Controller(SYS)
- Memory Mapped Structure for SYS Controller
-@{ */
-
-
-typedef struct
-{
-
-/**
- * @var SYS_T::PDID
- * Offset: 0x00 Part Device Identification Number Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |PDID |Part Device Identification Number (Read Only)
- * | | |This register reflects device part number code.
- * | | |Software can read this register to identify which device is used.
- * @var SYS_T::RSTSTS
- * Offset: 0x04 System Reset Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PORF |POR Reset Flag
- * | | |The POR reset flag is set by the "Reset Signal" from the Power-On Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
- * | | |0 = No reset from POR or CHIPRST.
- * | | |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[1] |PINRF |nRESET Pin Reset Flag
- * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
- * | | |0 = No reset from nRESET pin.
- * | | |1 = Pin nRESET had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[2] |WDTRF |WDT Reset Flag
- * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
- * | | |0 = No reset from watchdog timer or window watchdog timer.
- * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
- * | | |Note1:
- * | | |Write 1 to clear this bit to 0.
- * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
- * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
- * |[3] |LVRF |LVR Reset Flag
- * | | |The LVR reset flag is set by the "Reset Signal" from the Low-Voltage-Reset Controller to indicate the previous reset source.
- * | | |0 = No reset from LVR.
- * | | |1 = LVR controller had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |BODRF |BOD Reset Flag
- * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out-Detector to indicate the previous reset source.
- * | | |0 = No reset from BOD.
- * | | |1 = The BOD had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |SYSRF |System Reset Flag
- * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
- * | | |0 = No reset from Cortex-M4.
- * | | |1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |CPURF |CPU Reset Flag
- * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
- * | | |0 = No reset from CPU.
- * | | |1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |CPULKRF |CPU Lockup Reset Flag
- * | | |The CPU reset flag is set by hardware if Cortex-M4 lockup happened.
- * | | |0 = No reset from CPU lockup happened.
- * | | |1 = The Cortex-M4 lockup happened and chip is reset.
- * | | |Note: Write 1 to clear this bit to 0.
- * @var SYS_T::IPRST0
- * Offset: 0x08 Peripheral Reset Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CHIPRST |Chip One-Shot Reset (Write Protect)
- * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
- * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
- * | | |About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2
- * | | |0 = Chip normal operation.
- * | | |1 = Chip one shot reset.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[1] |CPURST |Processor Core One-Shot Reset (Write Protect)
- * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
- * | | |0 = Processor core normal operation.
- * | | |1 = Processor core one-shot reset.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the PDMA.
- * | | |User needs to set this bit to 0 to release from reset state.
- * | | |0 = PDMA controller normal operation.
- * | | |1 = PDMA controller reset.
- * |[3] |EBIRST |EBI Controller Reset (Write Protect)
- * | | |Set this bit to 1 will generate a reset signal to the EBI.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |0 = EBI controller normal operation.
- * | | |1 = EBI controller reset.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[4] |USBHRST |USBH Controller Reset (Write Protect)
- * | | |Set this bit to 1 will generate a reset signal to the USB host controller.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |0 = USBH controller normal operation.
- * | | |1 = USBH controller reset.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[7] |CRCRST |CRC Calculation Unit Reset (Write Protect)
- * | | |Set this bit to 1 will generate a reset signal to the CRC calculation module.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |0 = CRC Calculation unit normal operation.
- * | | |1 = CRC Calculation unit reset.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var SYS_T::IPRST1
- * Offset: 0x0C Peripheral Reset Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |GPIORST |GPIO Controller Reset
- * | | |0 = GPIO controller normal operation.
- * | | |1 = GPIO controller reset.
- * |[2] |TMR0RST |Timer0 Controller Reset
- * | | |0 = Timer0 controller normal operation.
- * | | |1 = Timer0 controller reset.
- * |[3] |TMR1RST |Timer1 Controller Reset
- * | | |0 = Timer1 controller normal operation.
- * | | |1 = Timer1 controller reset.
- * |[4] |TMR2RST |Timer2 Controller Reset
- * | | |0 = Timer2 controller normal operation.
- * | | |1 = Timer2 controller reset.
- * |[5] |TMR3RST |Timer3 Controller Reset
- * | | |0 = Timer3 controller normal operation.
- * | | |1 = Timer3 controller reset.
- * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset
- * | | |0 = Analog Comparator 0/1 controller normal operation.
- * | | |1 = Analog Comparator 0/1 controller reset.
- * |[8] |I2C0RST |I2C0 Controller Reset
- * | | |0 = I2C0 controller normal operation.
- * | | |1 = I2C0 controller reset.
- * |[9] |I2C1RST |I2C1 Controller Reset
- * | | |0 = I2C1 controller normal operation.
- * | | |1 = I2C1 controller reset.
- * |[12] |SPI0RST |SPI0 Controller Reset
- * | | |0 = SPI0 controller normal operation.
- * | | |1 = SPI0 controller reset.
- * |[13] |SPI1RST |SPI1 Controller Reset
- * | | |0 = SPI1 controller normal operation.
- * | | |1 = SPI1 controller reset.
- * |[14] |SPI2RST |SPI2 Controller Reset
- * | | |0 = SPI2 controller normal operation.
- * | | |1 = SPI2 controller reset.
- * |[16] |UART0RST |UART0 Controller Reset
- * | | |0 = UART0 controller normal operation.
- * | | |1 = UART0 controller reset.
- * |[17] |UART1RST |UART1 Controller Reset
- * | | |0 = UART1 controller normal operation.
- * | | |1 = UART1 controller reset.
- * |[18] |UART2RST |UART2 Controller Reset
- * | | |0 = UART2 controller normal operation.
- * | | |1 = UART2 controller reset.
- * |[19] |UART3RST |UART3 Controller Reset
- * | | |0 = UART3 controller normal operation.
- * | | |1 = UART3 controller reset.
- * |[24] |CAN0RST |CAN0 Controller Reset
- * | | |0 = CAN0 controller normal operation.
- * | | |1 = CAN0 controller reset.
- * |[26] |OTGRST |OTG Controller Reset
- * | | |0 = OTG controller normal operation.
- * | | |1 = OTG controller reset.
- * |[27] |USBDRST |USB Device Controller Reset
- * | | |0 = USB device controller normal operation.
- * | | |1 = USB device controller reset.
- * |[28] |EADCRST |EADC Controller Reset
- * | | |0 = EADC controller normal operation.
- * | | |1 = EADC controller reset.
- * @var SYS_T::IPRST2
- * Offset: 0x10 Peripheral Reset Control Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SC0RST |SC0 Controller Reset
- * | | |0 = SC0 controller normal operation.
- * | | |1 = SC0 controller reset.
- * |[12] |DACRST |DAC Controller Reset
- * | | |0 = DAC controller normal operation.
- * | | |1 = DAC controller reset.
- * |[16] |PWM0RST |PWM0 Controller Reset
- * | | |0 = PWM0 controller normal operation.
- * | | |1 = PWM0 controller reset.
- * |[17] |PWM1RST |PWM1 Controller Reset
- * | | |0 = PWM1 controller normal operation.
- * | | |1 = PWM1 controller reset.
- * |[25] |TKRST |Touch Key Controller Reset
- * | | |0 = Touch Key controller normal operation.
- * | | |1 = Touch Key controller reset.
- * @var SYS_T::BODCTL
- * Offset: 0x18 Brown-Out Detector Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BODEN |Brown-Out Detector Enable Bit (Write Protect)
- * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
- * | | |0 = Brown-out Detector function Disabled.
- * | | |1 = Brown-out Detector function Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[2:1] |BODVL |Brown-Out Detector Threshold Voltage Selection (Write Protect)
- * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).
- * | | |00 = Brown-Out Detector Threshold Voltage is 2.2V
- * | | |01 = Brown-Out Detector Threshold Voltage is 2.7V
- * | | |10 = Brown-Out Detector Threshold Voltage is 3.7V
- * | | |11 = Brown-Out Detector Threshold Voltage is 4.5V
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[3] |BODRSTEN |Brown-Out Reset Enable Bit (Write Protect)
- * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
- * | | |0 = Brown-out "INTERRUPT" function Enabled.
- * | | |1 = Brown-out "RESET" function Enabled.
- * | | |Note1:
- * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
- * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
- * | | |BOD interrupt will keep till to the BODEN set to 0.
- * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
- * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[4] |BODIF |Brown-Out Detector Interrupt Flag
- * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
- * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |BODLPM |Brown-Out Detector Low Power Mode (Write Protect)
- * | | |0 = BOD operate in normal mode (default).
- * | | |1 = BOD Low Power mode Enabled.
- * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
- * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[6] |BODOUT |Brown-Out Detector Output Status
- * | | |0 = Brown-out Detector output status is 0.
- * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
- * | | |1 = Brown-out Detector output status is 1.
- * | | |It means the detected voltage is lower than BODVL setting.
- * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
- * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect)
- * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
- * | | |LVR function is enabled by default.
- * | | |0 = Low Voltage Reset function Disabled.
- * | | |1 = Low Voltage Reset function Enabled
- * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
- * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[10:8] |BODDGSEL |Brown-Out Detector Output De-Glitch Time Select (Write Protect)
- * | | |000 = BOD output is sampled by RC10K clock.
- * | | |001 = 4 system clock (HCLK).
- * | | |010 = 8 system clock (HCLK).
- * | | |011 = 16 system clock (HCLK).
- * | | |100 = 32 system clock (HCLK).
- * | | |101 = 64 system clock (HCLK).
- * | | |110 = 128 system clock (HCLK).
- * | | |111 = 256 system clock (HCLK).
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[14:12] |LVRDGSEL |LVR Output De-Glitch Time Select (Write Protect)
- * | | |000 = Without de-glitch function.
- * | | |001 = 4 system clock (HCLK).
- * | | |010 = 8 system clock (HCLK).
- * | | |011 = 16 system clock (HCLK).
- * | | |100 = 32 system clock (HCLK).
- * | | |101 = 64 system clock (HCLK).
- * | | |110 = 128 system clock (HCLK).
- * | | |111 = 256 system clock (HCLK).
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var SYS_T::IVSCTL
- * Offset: 0x1C Internal Voltage Source Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |VTEMPEN |Temperature Sensor Enable Bit
- * | | |This bit is used to enable/disable temperature sensor function.
- * | | |0 = Temperature sensor function Disabled (default).
- * | | |1 = Temperature sensor function Enabled.
- * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
- * | | |Please refer to ADC function chapter for details.
- * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit
- * | | |This bit is used to enable/disable VBAT unity gain buffer function.
- * | | |0 = VBAT unity gain buffer function Disabled (default).
- * | | |1 = VBAT unity gain buffer function Enabled.
- * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
- * @var SYS_T::PORCTL
- * Offset: 0x24 Power-On-Reset Controller Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |POROFF |Power-On-Reset Enable Bit (Write Protect)
- * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
- * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
- * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
- * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var SYS_T::VREFCTL
- * Offset: 0x28 VREF Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:0] |VREFCTL |VREF Control Bits (Write Protect)
- * | | |00011 = VREF is internal 2.65V.
- * | | |00111 = VREF is internal 2.048V.
- * | | |01011 = VREF is internal 3.072V.
- * | | |01111 = VREF is internal 4.096V.
- * | | |Others = Reserved.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var SYS_T::USBPHY
- * Offset: 0x2C USB PHY Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |USBROLE |USB Role Option (Write Protect)
- * | | |These two bits are used to select the role of USB.
- * | | |00 = Standard USB Device mode.
- * | | |01 = Standard USB Host mode.
- * | | |10 = ID dependent mode.
- * | | |11 = On-The-Go device mode.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[8] |LDO33EN |USB LDO33 Enable Bit (Write Protect)
- * | | |0 = USB LDO33 Disabled.
- * | | |1 = USB LDO33 Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var SYS_T::GPA_MFPL
- * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection
- * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection
- * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection
- * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection
- * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection
- * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection
- * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection
- * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection
- * @var SYS_T::GPA_MFPH
- * Offset: 0x34 GPIOA High Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection
- * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection
- * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection
- * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection
- * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection
- * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection
- * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection
- * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection
- * @var SYS_T::GPB_MFPL
- * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection
- * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection
- * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection
- * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection
- * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection
- * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection
- * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection
- * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection
- * @var SYS_T::GPB_MFPH
- * Offset: 0x3C GPIOB High Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection
- * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection
- * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection
- * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection
- * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection
- * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection
- * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection
- * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection
- * @var SYS_T::GPC_MFPL
- * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection
- * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection
- * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection
- * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection
- * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection
- * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection
- * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection
- * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection
- * @var SYS_T::GPC_MFPH
- * Offset: 0x44 GPIOC High Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection
- * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection
- * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection
- * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection
- * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection
- * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection
- * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection
- * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection
- * @var SYS_T::GPD_MFPL
- * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection
- * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection
- * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection
- * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection
- * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection
- * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection
- * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection
- * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection
- * @var SYS_T::GPD_MFPH
- * Offset: 0x4C GPIOD High Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection
- * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection
- * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection
- * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection
- * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection
- * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection
- * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection
- * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection
- * @var SYS_T::GPE_MFPL
- * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection
- * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection
- * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection
- * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection
- * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection
- * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection
- * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection
- * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection
- * @var SYS_T::GPE_MFPH
- * Offset: 0x54 GPIOE High Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection
- * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection
- * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection
- * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection
- * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection
- * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection
- * |[27:24] |PE14_MFP |PE.14 Multi-function Pin Selection
- * @var SYS_T::GPF_MFPL
- * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection
- * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection
- * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection
- * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection
- * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection
- * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection
- * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection
- * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection
- * @var SYS_T::SRAM_INTCTL
- * Offset: 0xC0 System SRAM Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit
- * | | |0 = SRAM parity check error interrupt Disabled.
- * | | |1 = SRAM parity check error interrupt Enabled.
- * @var SYS_T::SRAM_STATUS
- * Offset: 0xC4 System SRAM Parity Error Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PERRIF |SRAM Parity Check Error Flag
- * | | |0 = No System SRAM parity error.
- * | | |1 = System SRAM parity error occur.
- * @var SYS_T::SRAM_ERRADDR
- * Offset: 0xC8 System SRAM Parity Check Error Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |ERRADDR |System SRAM Parity Error Address
- * | | |This register shows system SRAM parity error byte address.
- * @var SYS_T::SRAM_BISTCTL
- * Offset: 0xD0 System SRAM BIST Test Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SRBIST0 |1st
- * | | |SRAM BIST Enable Bit
- * | | |This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF
- * | | |0 = system SRAM BIST Disabled.
- * | | |1 = system SRAM BIST Enabled.
- * |[1] |SRBIST1 |2nd
- * | | |SRAM BIST Enable Bit
- * | | |This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF
- * | | |0 = system SRAM BIST Disabled.
- * | | |1 = system SRAM BIST Enabled.
- * |[2] |CRBIST |CACHE BIST Enable Bit
- * | | |This bit enables BIST test for CACHE RAM
- * | | |0 = system CACHE BIST Disabled.
- * | | |1 = system CACHE BIST Enabled.
- * |[3] |CANBIST |CAN BIST Enable Bit
- * | | |This bit enables BIST test for CAN RAM
- * | | |0 = system CAN BIST Disabled.
- * | | |1 = system CAN BIST Enabled.
- * |[4] |USBBIST |USB BIST Enable Bit
- * | | |This bit enables BIST test for USB RAM
- * | | |0 = system USB BIST Disabled.
- * | | |1 = system USB BIST Enabled.
- * @var SYS_T::SRAM_BISTSTS
- * Offset: 0xD4 System SRAM BIST Test Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag
- * | | |0 = 1st system SRAM BIST test pass.
- * | | |1 = 1st system SRAM BIST test fail.
- * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag
- * | | |0 = 2nd system SRAM BIST test pass.
- * | | |1 = 2nd system SRAM BIST test fail.
- * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag
- * | | |0 = System CACHE RAM BIST test pass.
- * | | |1 = System CACHE RAM BIST test fail.
- * |[3] |CANBEF |CAN SRAM BIST Fail Flag
- * | | |0 = CAN SRAM BIST test pass.
- * | | |1 = CAN SRAM BIST test fail.
- * |[4] |USBBEF |USB SRAM BIST Fail Flag
- * | | |0 = USB SRAM BIST test pass.
- * | | |1 = USB SRAM BIST test fail.
- * |[16] |SRBEND0 |1st SRAM BIST Test Finish
- * | | |0 = 1st system SRAM BIST active.
- * | | |1 = 1st system SRAM BIST finish.
- * |[17] |SRBEND1 |2nd SRAM BIST Test Finish
- * | | |0 = 2nd system SRAM BIST is active.
- * | | |1 = 2nd system SRAM BIST finish.
- * |[18] |CRBEND |CACHE SRAM BIST Test Finish
- * | | |0 = System CACHE RAM BIST is active.
- * | | |1 = System CACHE RAM BIST test finish.
- * |[19] |CANBEND |CAN SRAM BIST Test Finish
- * | | |0 = CAN SRAM BIST is active.
- * | | |1 = CAN SRAM BIST test finish.
- * |[20] |USBBEND |USB SRAM BIST Test Finish
- * | | |0 = USB SRAM BIST is active.
- * | | |1 = USB SRAM BIST test finish.
- * @var SYS_T::IRCTCTL
- * Offset: 0xF0 IRC Trim Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |FREQSEL |Trim Frequency Selection
- * | | |This field indicates the target frequency of internal 22.1184 MHz high-speed oscillator auto trim.
- * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
- * | | |00 = Disable HIRC auto trim function.
- * | | |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
- * | | |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
- * | | |11 = Reserved.
- * |[5:4] |LOOPSEL |Trim Calculation Loop Selection
- * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
- * | | |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
- * | | |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
- * | | |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
- * | | |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
- * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
- * |[7:6] |RETRYCNT |Trim Value Update Limitation Count
- * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
- * | | |Once the HIRC locked, the internal trim value update counter will be reset.
- * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
- * | | |00 = Trim retry count limitation is 64 loops.
- * | | |01 = Trim retry count limitation is 128 loops.
- * | | |10 = Trim retry count limitation is 256 loops.
- * | | |11 = Trim retry count limitation is 512 loops.
- * |[8] |CESTOPEN |Clock Error Stop Enable Bit
- * | | |0 = The trim operation is keep going if clock is inaccuracy.
- * | | |1 = The trim operation is stopped if clock is inaccuracy.
- * @var SYS_T::IRCTIEN
- * Offset: 0xF4 IRC Trim Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit
- * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
- * | | |If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
- * | | |0 = Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
- * | | |1 = Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
- * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit
- * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
- * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
- * | | |0 = Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
- * | | |1 = Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
- * @var SYS_T::IRCTISTS
- * Offset: 0xF8 IRC Trim Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FREQLOCK |HIRC Frequency Lock Status
- * | | |This bit indicates the internal 22.1184 MHz high-speed oscillator frequency is locked.
- * | | |This is a status bit and doesn't trigger any interrupt.
- * |[1] |TFAILIF |Trim Failure Interrupt Status
- * | | |This bit indicates that internal 22.1184 MHz high-speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high-speed oscillator clock frequency still doesn't be locked.
- * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
- * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
- * | | |Write 1 to clear this to 0.
- * | | |0 = Trim value update limitation count does not reach.
- * | | |1 = Trim value update limitation count reached and internal 22.1184 MHz high-speed oscillator frequency still not locked.
- * |[2] |CLKERRIF |Clock Error Interrupt Status
- * | | |When the frequency of external 32.768 kHz low-speed crystal or internal 22.1184 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
- * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
- * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
- * | | |Write 1 to clear this to 0.
- * | | |0 = Clock frequency is accuracy.
- * | | |1 = Clock frequency is inaccuracy.
- * @var SYS_T::REGLCTL
- * Offset: 0x100 Register Lock Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |REGLCTL |Register Lock Control Code
- * | | |Write operation:
- * | | |Some registers have write-protection function.
- * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
- * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
- * | | |Read operation:
- * | | |0 = Write-protection Enabled for writing protected registers.
- * | | |Any write to the protected register is ignored.
- * | | |1 = Write-protection Disabled for writing protected registers.
- * | | |The Protected registers are:
- * | | |SYS_IPRST0: address 0x4000_0008
- * | | |SYS_BODCTL: address 0x4000_0018
- * | | |SYS_PORCTL: address 0x4000_0024
- * | | |SYS_VREFCTL: address 0x4000_0028
- * | | |SYS_USBPHY: address 0x4000_002C
- * | | |CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
- * | | |SYS_SRAM_BISTCTL: address 0x4000_00D0
- * | | |CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
- * | | |CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
- * | | |CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
- * | | |CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
- * | | |CLK_CLKDSTS: address 0x4000_0274
- * | | |NMIEN: address 0x4000_0300
- * | | |FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
- * | | |FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
- * | | |FMC_ISPSTS: address 0x4000_C040
- * | | |WDT_CTL: address 0x4004_0000
- * | | |FMC_FTCTL: address 0x4000_5018
- * | | |FMC_ICPCMD: address 0x4000_501C
- * | | |CLK_PLLCTL: address 0x40000240
- * | | |PWM_CTL0: address 0x4005_8000
- * | | |PWM_CTL0: address 0x4005_9000
- * | | |PWM_DTCTL0_1: address 0x4005_8070
- * | | |PWM_DTCTL0_1: address 0x4005_9070
- * | | |PWM_DTCTL2_3: address 0x4005_8074
- * | | |PWM_DTCTL2_3: address 0x4005_9074
- * | | |PWM_DTCTL4_5: address 0x4005_8078
- * | | |PWM_DTCTL4_5: address 0x4005_9078
- * | | |PWM_BRKCTL0_1: address 0x4005_80C8
- * | | |PWM_BRKCTL0_1: address 0x4005_90C8
- * | | |PWM_BRKCTL2_3: address0x4005_80CC
- * | | |PWM_BRKCTL2_3: address0x4005_90CC
- * | | |PWM_BRKCTL4_5: address0x4005_80D0
- * | | |PWM_BRKCTL4_5: address0x4005_90D0
- * | | |PWM_INTEN1: address0x4005_80E4
- * | | |PWM_INTEN1: address0x4005_90E4
- * | | |PWM_INTSTS1: address0x4005_80EC
- * | | |PWM_INTSTS1: address0x4005_90EC
- */
-
- __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
- __IO uint32_t RSTSTS; /* Offset: 0x04 System Reset Status Register */
- __IO uint32_t IPRST0; /* Offset: 0x08 Peripheral Reset Control Register 0 */
- __IO uint32_t IPRST1; /* Offset: 0x0C Peripheral Reset Control Register 1 */
- __IO uint32_t IPRST2; /* Offset: 0x10 Peripheral Reset Control Register 2 */
- __I uint32_t RESERVE0[1];
- __IO uint32_t BODCTL; /* Offset: 0x18 Brown-Out Detector Control Register */
- __IO uint32_t IVSCTL; /* Offset: 0x1C Internal Voltage Source Control Register */
- __I uint32_t RESERVE1[1];
- __IO uint32_t PORCTL; /* Offset: 0x24 Power-On-Reset Controller Register */
- __IO uint32_t VREFCTL; /* Offset: 0x28 VREF Control Register */
- __IO uint32_t USBPHY; /* Offset: 0x2C USB PHY Control Register */
- __IO uint32_t GPA_MFPL; /* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register */
- __IO uint32_t GPA_MFPH; /* Offset: 0x34 GPIOA High Byte Multiple Function Control Register */
- __IO uint32_t GPB_MFPL; /* Offset: 0x38 GPIOB Low Byte Multiple Function Control Register */
- __IO uint32_t GPB_MFPH; /* Offset: 0x3C GPIOB High Byte Multiple Function Control Register */
- __IO uint32_t GPC_MFPL; /* Offset: 0x40 GPIOC Low Byte Multiple Function Control Register */
- __IO uint32_t GPC_MFPH; /* Offset: 0x44 GPIOC High Byte Multiple Function Control Register */
- __IO uint32_t GPD_MFPL; /* Offset: 0x48 GPIOD Low Byte Multiple Function Control Register */
- __IO uint32_t GPD_MFPH; /* Offset: 0x4C GPIOD High Byte Multiple Function Control Register */
- __IO uint32_t GPE_MFPL; /* Offset: 0x50 GPIOE Low Byte Multiple Function Control Register */
- __IO uint32_t GPE_MFPH; /* Offset: 0x54 GPIOE High Byte Multiple Function Control Register */
- __IO uint32_t GPF_MFPL; /* Offset: 0x58 GPIOF Low Byte Multiple Function Control Register */
- __I uint32_t RESERVE2[25];
- __IO uint32_t SRAM_INTCTL; /* Offset: 0xC0 System SRAM Interrupt Enable Control Register */
- __I uint32_t SRAM_STATUS; /* Offset: 0xC4 System SRAM Parity Error Status Register */
- __I uint32_t SRAM_ERRADDR; /* Offset: 0xC8 System SRAM Parity Check Error Address Register */
- __I uint32_t RESERVE3[1];
- __IO uint32_t SRAM_BISTCTL; /* Offset: 0xD0 System SRAM BIST Test Control Register */
- __I uint32_t SRAM_BISTSTS; /* Offset: 0xD4 System SRAM BIST Test Status Register */
- __I uint32_t RESERVE4[6];
- __IO uint32_t IRCTCTL; /* Offset: 0xF0 IRC Trim Control Register */
- __IO uint32_t IRCTIEN; /* Offset: 0xF4 IRC Trim Interrupt Enable Register */
- __IO uint32_t IRCTISTS; /* Offset: 0xF8 IRC Trim Interrupt Status Register */
- __I uint32_t RESERVE5[1];
- __IO uint32_t REGLCTL; /* Offset: 0x100 Register Lock Control Register */
-
-} SYS_T;
-
-
-
-/**
- @addtogroup SYS_CONST SYS Bit Field Definition
- Constant Definitions for SYS Controller
-@{ */
-
-#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */
-#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */
-
-#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */
-#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */
-
-#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */
-#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */
-
-#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */
-#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */
-
-#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */
-#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */
-
-#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */
-#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */
-
-#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */
-#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */
-
-#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */
-#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */
-
-#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */
-#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */
-
-#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */
-#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */
-
-#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */
-#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */
-
-#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */
-#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */
-
-#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */
-#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */
-
-#define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */
-#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */
-
-#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */
-#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */
-
-#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */
-#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */
-
-#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */
-#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */
-
-#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */
-#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */
-
-#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */
-#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */
-
-#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */
-#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */
-
-#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */
-#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */
-
-#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */
-#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */
-
-#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */
-#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */
-
-#define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS_T::IPRST1: SPI0RST Position */
-#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */
-
-#define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS_T::IPRST1: SPI1RST Position */
-#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */
-
-#define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS_T::IPRST1: SPI2RST Position */
-#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */
-
-#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */
-#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */
-
-#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */
-#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */
-
-#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */
-#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */
-
-#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */
-#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */
-
-#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
-#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
-
-#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */
-#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */
-
-#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */
-#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */
-
-#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */
-#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */
-
-#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */
-#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */
-
-#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */
-#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */
-
-#define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS_T::IPRST2: PWM0RST Position */
-#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS_T::IPRST2: PWM0RST Mask */
-
-#define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS_T::IPRST2: PWM1RST Position */
-#define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS_T::IPRST2: PWM1RST Mask */
-
-#define SYS_IPRST2_TKRST_Pos (25) /*!< SYS_T::IPRST2: TKRST Position */
-#define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos) /*!< SYS_T::IPRST2: TKRST Mask */
-
-#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */
-#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */
-
-#define SYS_BODCTL_BODVL_Pos (1) /*!< SYS_T::BODCTL: BODVL Position */
-#define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */
-
-#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */
-#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */
-
-#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */
-#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */
-
-#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */
-#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */
-
-#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */
-#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */
-
-#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */
-#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */
-
-#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */
-#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */
-
-#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */
-#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */
-
-#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */
-#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */
-
-#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */
-#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */
-
-#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS_T::PORCTL: POROFF Position */
-#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS_T::PORCTL: POROFF Mask */
-
-#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */
-#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */
-
-#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */
-#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */
-
-#define SYS_USBPHY_LDO33EN_Pos (8) /*!< SYS_T::USBPHY: LDO33EN Position */
-#define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /*!< SYS_T::USBPHY: LDO33EN Mask */
-
-#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */
-#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */
-
-#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */
-#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */
-
-#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */
-#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */
-
-#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */
-#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */
-
-#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */
-#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */
-
-#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */
-#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */
-
-#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */
-#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */
-
-#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */
-#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */
-
-#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */
-#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */
-
-#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */
-#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */
-
-#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */
-#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */
-
-#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */
-#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */
-
-#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */
-#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */
-
-#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */
-#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */
-
-#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */
-#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */
-
-#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */
-#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */
-
-#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */
-#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */
-
-#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */
-#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */
-
-#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */
-#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */
-
-#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */
-#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */
-
-#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */
-#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */
-
-#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */
-#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */
-
-#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */
-#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */
-
-#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */
-#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */
-
-#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */
-#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */
-
-#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */
-#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */
-
-#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */
-#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */
-
-#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */
-#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */
-
-#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */
-#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */
-
-#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */
-#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */
-
-#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */
-#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */
-
-#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */
-#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */
-
-#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */
-#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */
-
-#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */
-#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */
-
-#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */
-#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */
-
-#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */
-#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */
-
-#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */
-#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */
-
-#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */
-#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */
-
-#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */
-#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */
-
-#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */
-#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */
-
-#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */
-#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */
-
-#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */
-#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */
-
-#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */
-#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */
-
-#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */
-#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */
-
-#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */
-#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */
-
-#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */
-#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */
-
-#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */
-#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */
-
-#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */
-#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */
-
-#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */
-#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */
-
-#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */
-#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */
-
-#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */
-#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */
-
-#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */
-#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */
-
-#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */
-#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */
-
-#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */
-#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */
-
-#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */
-#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */
-
-#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */
-#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */
-
-#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */
-#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */
-
-#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */
-#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */
-
-#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */
-#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */
-
-#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */
-#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */
-
-#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */
-#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */
-
-#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */
-#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */
-
-#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */
-#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */
-
-#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */
-#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */
-
-#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */
-#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */
-
-#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */
-#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */
-
-#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */
-#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */
-
-#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */
-#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */
-
-#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */
-#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */
-
-#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */
-#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */
-
-#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */
-#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */
-
-#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */
-#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */
-
-#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */
-#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */
-
-#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */
-#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */
-
-#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */
-#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */
-
-#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */
-#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */
-
-#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */
-#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */
-
-#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */
-#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */
-
-#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */
-#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */
-
-#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */
-#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */
-
-#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */
-#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */
-
-#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */
-#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */
-
-#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */
-#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */
-
-#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */
-#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */
-
-#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */
-#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */
-
-#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */
-#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */
-
-#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */
-#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */
-
-#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */
-#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */
-
-#define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */
-#define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */
-
-#define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */
-#define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */
-
-#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */
-#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */
-
-#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */
-#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */
-
-#define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */
-#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */
-
-#define SYS_SRAM_BISTCTL_CANBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANBIST Position */
-#define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANBIST Mask */
-
-#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */
-#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */
-
-#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position */
-#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */
-
-#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position */
-#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */
-
-#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */
-#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */
-
-#define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */
-#define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */
-
-#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */
-#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */
-
-#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */
-#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */
-
-#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */
-#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */
-
-#define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */
-#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */
-
-#define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */
-#define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */
-
-#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */
-#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */
-
-#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */
-#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */
-
-#define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */
-#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */
-
-#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */
-#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */
-
-#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */
-#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */
-
-#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */
-#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */
-
-#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */
-#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */
-
-#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */
-#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */
-
-#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */
-#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */
-
-#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */
-#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */
-
-#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */
-#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */
-
-/**@}*/ /* SYS_CONST */
-
-
-typedef struct
-{
-
-/**
- * @var SYS_INT_T::NMIEN
- * Offset: 0x00 NMI Source Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BODOUT |BOD NMI Source Enable (Write Protect)
- * | | |0 = BOD NMI source Disabled.
- * | | |1 = BOD NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect)
- * | | |0 = IRC TRIM NMI source Disabled.
- * | | |1 = IRC TRIM NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[2] |PWRWU_INT |Power-Down Mode Wake-Up NMI Source Enable (Write Protect)
- * | | |0 = Power-down mode wake-up NMI source Disabled.
- * | | |1 = Power-down mode wake-up NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[3] |SRAM_PERR |SRAM ParityCheck Error NMI Source Enable (Write Protect)
- * | | |0 = SRAM parity check error NMI source Disabled.
- * | | |1 = SRAM parity check error NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect)
- * | | |0 = Clock fail detected interrupt NMI source Disabled.
- * | | |1 = Clock fail detected interrupt NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect)
- * | | |0 = RTC NMI source Disabled.
- * | | |1 = RTC NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect)
- * | | |0 = Backup register tamper detected interrupt.NMI source Disabled.
- * | | |1 = Backup register tamper detected interrupt.NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin NMI Source Enable (Write Protect)
- * | | |0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
- * | | |1 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin NMI Source Enable (Write Protect)
- * | | |0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled.
- * | | |1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[10] |EINT2 |External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)
- * | | |0 = External interrupt from PC.0 pin NMI source Disabled.
- * | | |1 = External interrupt from PC.0 pin NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[11] |EINT3 |External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)
- * | | |0 = External interrupt from PD.0 pin NMI source Disabled.
- * | | |1 = External interrupt from PD.0 pin NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[12] |EINT4 |External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)
- * | | |0 = External interrupt from PE.0 pin NMI source Disabled.
- * | | |1 = External interrupt from PE.0 pin NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[13] |EINT5 |External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)
- * | | |0 = External interrupt from PF.0 pin NMI source Disabled.
- * | | |1 = External interrupt from PF.0 pin NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect)
- * | | |0 = UART0 NMI source Disabled.
- * | | |1 = UART0 NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect)
- * | | |0 = UART1 NMI source Disabled.
- * | | |1 = UART1 NMI source Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var SYS_INT_T::NMISTS
- * Offset: 0x04 NMI source interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BODOUT |BOD Interrupt Flag (Read Only)
- * | | |0 = BOD interrupt is deasserted.
- * | | |1 = BOD interrupt is asserted.
- * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only)
- * | | |0 = HIRC TRIM interrupt is deasserted.
- * | | |1 = HIRC TRIM interrupt is asserted.
- * |[2] |PWRWU_INT |Power-Down Mode Wake-Up Interrupt Flag (Read Only)
- * | | |0 = Power-down mode wake-up interrupt is deasserted.
- * | | |1 = Power-down mode wake-up interrupt is asserted.
- * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only)
- * | | |0 = SRAM parity check error interrupt is deasserted.
- * | | |1 = SRAM parity check error interrupt is asserted.
- * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only)
- * | | |0 = Clock fail detected interrupt is deasserted.
- * | | |1 = Clock fail detected interrupt is asserted.
- * |[6] |RTC_INT |RTC Interrupt Flag (Read Only)
- * | | |0 = RTC interrupt is deasserted.
- * | | |1 = RTC interrupt is asserted.
- * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only)
- * | | |0 = Backup register tamper detected interrupt is deasserted.
- * | | |1 = Backup register tamper detected interrupt is asserted.
- * |[8] |EINT0 |External Interrupt From PA.0, PD.2 Or PE.4 Pin Interrupt Flag (Read Only)
- * | | |0 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted.
- * | | |1 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted.
- * |[9] |EINT1 |External Interrupt From PB.0, PD.3 Or PE.5 Pin Interrupt Flag (Read Only)
- * | | |0 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted.
- * | | |1 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted.
- * |[10] |EINT2 |External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
- * | | |0 = External Interrupt from PC.0 interrupt is deasserted.
- * | | |1 = External Interrupt from PC.0 interrupt is asserted.
- * |[11] |EINT3 |External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
- * | | |0 = External Interrupt from PD.0 interrupt is deasserted.
- * | | |1 = External Interrupt from PD.0 interrupt is asserted.
- * |[12] |EINT4 |External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
- * | | |0 = External Interrupt from PE.0 interrupt is deasserted.
- * | | |1 = External Interrupt from PE.0 interrupt is asserted.
- * |[13] |EINT5 |External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
- * | | |0 = External Interrupt from PF.0 interrupt is deasserted.
- * | | |1 = External Interrupt from PF.0 interrupt is asserted.
- * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only)
- * | | |0 = UART1 interrupt is deasserted.
- * | | |1 = UART1 interrupt is asserted.
- * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only)
- * | | |0 = UART1 interrupt is deasserted.
- * | | |1 = UART1 interrupt is asserted.
- */
-
- __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */
- __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */
-
-} SYS_INT_T;
-
-
-
-/**
- @addtogroup INT_CONST INT Bit Field Definition
- Constant Definitions for SYS Controller
-@{ */
-
-#define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */
-#define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */
-
-#define SYS_NMIEN_IRC_INT_Pos (1) /*!< SYS_INT_T::NMIEN: IRC_INT Position */
-#define SYS_NMIEN_IRC_INT_Msk (0x1ul << SYS_NMIEN_IRC_INT_Pos ) /*!< SYS_INT_T::NMIEN: IRC_INT Mask */
-
-#define SYS_NMIEN_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWU_INT Position */
-#define SYS_NMIEN_PWRWU_INT_Msk (0x1ul << SYS_NMIEN_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWU_INT Mask */
-
-#define SYS_NMIEN_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAM_PERR Position */
-#define SYS_NMIEN_SRAM_PERR_Msk (0x1ul << SYS_NMIEN_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAM_PERR Mask */
-
-#define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */
-#define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */
-
-#define SYS_NMIEN_RTC_INT_Pos (6) /*!< SYS_INT_T::NMIEN: RTC_INT Position */
-#define SYS_NMIEN_RTC_INT_Msk (0x1ul << SYS_NMIEN_RTC_INT_Pos ) /*!< SYS_INT_T::NMIEN: RTC_INT Mask */
-
-#define SYS_NMIEN_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPER_INT Position */
-#define SYS_NMIEN_TAMPER_INT_Msk (0x1ul << SYS_NMIEN_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPER_INT Mask */
-
-#define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */
-#define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */
-
-#define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */
-#define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */
-
-#define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */
-#define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */
-
-#define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */
-#define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */
-
-#define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */
-#define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */
-
-#define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */
-#define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */
-
-#define SYS_NMIEN_UART0_INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0_INT Position */
-#define SYS_NMIEN_UART0_INT_Msk (0x1ul << SYS_NMIEN_UART0_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0_INT Mask */
-
-#define SYS_NMIEN_UART1_INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1_INT Position */
-#define SYS_NMIEN_UART1_INT_Msk (0x1ul << SYS_NMIEN_UART1_INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1_INT Mask */
-
-#define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */
-#define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */
-
-#define SYS_NMISTS_IRC_INT_Pos (1) /*!< SYS_INT_T::NMISTS: IRC_INT Position */
-#define SYS_NMISTS_IRC_INT_Msk (0x1ul << SYS_NMISTS_IRC_INT_Pos ) /*!< SYS_INT_T::NMISTS: IRC_INT Mask */
-
-#define SYS_NMISTS_PWRWU_INT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWU_INT Position */
-#define SYS_NMISTS_PWRWU_INT_Msk (0x1ul << SYS_NMISTS_PWRWU_INT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWU_INT Mask */
-
-#define SYS_NMISTS_SRAM_PERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAM_PERR Position */
-#define SYS_NMISTS_SRAM_PERR_Msk (0x1ul << SYS_NMISTS_SRAM_PERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAM_PERR Mask */
-
-#define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */
-#define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */
-
-#define SYS_NMISTS_RTC_INT_Pos (6) /*!< SYS_INT_T::NMISTS: RTC_INT Position */
-#define SYS_NMISTS_RTC_INT_Msk (0x1ul << SYS_NMISTS_RTC_INT_Pos ) /*!< SYS_INT_T::NMISTS: RTC_INT Mask */
-
-#define SYS_NMISTS_TAMPER_INT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPER_INT Position */
-#define SYS_NMISTS_TAMPER_INT_Msk (0x1ul << SYS_NMISTS_TAMPER_INT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPER_INT Mask */
-
-#define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */
-#define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */
-
-#define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */
-#define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */
-
-#define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */
-#define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */
-
-#define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */
-#define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */
-
-#define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */
-#define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */
-
-#define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */
-#define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */
-
-#define SYS_NMISTS_UART0_INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */
-#define SYS_NMISTS_UART0_INT_Msk (0x1ul << SYS_NMISTS_UART0_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */
-
-#define SYS_NMISTS_UART1_INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */
-#define SYS_NMISTS_UART1_INT_Msk (0x1ul << SYS_NMISTS_UART1_INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */
-
-/**@}*/ /* INT_CONST */
-/**@}*/ /* end of SYS register group */
-
-
-/*---------------------- Touch Key Controller -------------------------*/
-/**
- @addtogroup TK Touch Key Controller(TK)
- Memory Mapped Structure for TK Controller
-@{ */
-
-
-typedef struct
-{
-
-
-/**
- * @var TK_T::CTL
- * Offset: 0x00 Touch Key Scan Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TKSEN0 |TK0 Scan Enable Bit
- * | | |This bit is ignored if TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
- * | | |0 = TKDAT0 (TK_DAT0[7:0]) is invalid.
- * | | |1 = TK0 is always enable for Touch Key scan. TKDAT0 (TK_DAT0[7:0]) is valid.
- * |[1] |TKSEN1 |TK1 Scan Enable Bit
- * | | |This bit is ignored if TKREN1 (TK_REFCTL[1]) is "1".
- * | | |0 = TKDAT1 (TK_DAT0[15:8]) is invalid.
- * | | |1 = TK1 is always enable for Touch Key scan. TKDAT1 (TK_DAT0[15:8]) is valid.
- * |[2] |TKSEN2 |TK2 Scan Enable Bit
- * | | |This bit is ignored if TKREN2 (TK_REFCTL[2]) is "1".
- * | | |0 = TKDAT2 (TK_DAT0[23:16]) is invalid.
- * | | |1 = TK2 is always enable for Touch Key scan. TKDAT2 (TK_DAT0[23:16]) is valid.
- * |[3] |TKSEN3 |TK3 Scan Enable Bit
- * | | |0 = TKDAT3 (TK_DAT0[31:24]) is invalid.
- * | | |1 = TK3 is always enable for Touch Key scan. TKDAT3 (TK_DAT0[31:24]) is valid.
- * | | |This bit is ignored if TKREN3 (TK_REFCTL[3]) is "1".
- * |[4] |TKSEN4 |TK4 Scan Enable Bit
- * | | |This bit is ignored if TKREN4 (TK_REFCTL[4]) is "1".
- * | | |0 = TKDAT4 (TK_DAT1[7:0]) is invalid.
- * | | |1 = TK4 is always enable for Touch Key scan. TKDAT4 (TK_DAT1[7:0]) is valid.
- * |[5] |TKSEN5 |TK5 Scan Enable Bit
- * | | |This bit is ignored if TKREN5 (TK_REFCTL[5]) is "1".
- * | | |0 = TKDAT5 (TK_DAT1[15:8]) is invalid.
- * | | |1 = TK5 is always enable for Touch Key scan. TKDAT5 (TK_DAT1[15:8]) is valid.
- * |[6] |TKSEN6 |TK6 Scan Enable Bit
- * | | |This bit is ignored if TKREN6 (TK_REFCTL[6]) is "1".
- * | | |0 = TKDAT6 (TK_DAT1[23:16]) is invalid.
- * | | |1 = TK6 is always enable for Touch Key scan. TKDAT6 (TK_DAT1[23:16]) is valid.
- * |[7] |TKSEN7 |TK7 Scan Enable
- * | | |This bit is ignored if TKREN7 (TK_REFCTL[7]) is "1".
- * | | |0 = TKDAT7 (TK_DAT1[31:24]) is invalid.
- * | | |1 = TK7 is always enable for Touch Key scan. TKDAT7 (TK_DAT1[31:24]) is valid.
- * |[8] |TKSEN8 |TK8 Scan Enable Bit
- * | | |This bit is ignored if TKREN8 (TK_REFCTL[8]) is "1".
- * | | |0 = TKDAT8 (TK_DAT2[7:0]) is invalid.
- * | | |1 = TK8 is always enable for Touch Key scan. TKDAT8 (TK_DAT2[7:0]) is valid.
- * |[9] |TKSEN9 |TK9 Scan Enable Bit
- * | | |This bit is ignored if TKREN9 (TK_REFCTL[9]) is "1".
- * | | |0 = TKDAT9 (TK_DAT2[15:8]) is invalid.
- * | | |1 = TK9 is always enable for Touch Key scan. TKDAT9 (TK_DAT2[15:8]) is valid.
- * |[10] |TKSEN10 |TK10 Scan Enable Bit
- * | | |This bit is ignored if TKREN10 (TK_REFCTL[10]) is "1".
- * | | |0 = TKDAT10 (TK_DAT2[23:16]) is invalid.
- * | | |1 = TK10 is always enable for Touch Key scan. TKDAT10 (TK_DAT2[23:16]) is valid.
- * |[11] |TKSEN11 |TK11 Scan Enable
- * | | |This bit is ignored if TKREN11 (TK_REFCTL[11]) is "1".
- * | | |0 = TKDAT11 (TK_DAT2[31:24]) is invalid.
- * | | |1 = TK11 is always enable for Touch Key scan. TKDAT11 (TK_DAT2[31:24]) is valid.
- * |[12] |TKSEN12 |TK12 Scan Enable Bit
- * | | |This bit is ignored if TKREN12 (TK_REFCTL[12]) is "1".
- * | | |0 = TKDAT12 (TK_DAT3[7:0]) is invalid.
- * | | |1 = TK12 is always enable for Touch Key scan. TKDAT12 (TK_DAT3[7:0]) is valid.
- * |[13] |TKSEN13 |TK13 Scan Enable Bit
- * | | |This bit is ignored if TKREN13 (TK_REFCTL[13]) is "1".
- * | | |0 = TKDAT13 (TK_DAT3[15:8]) is invalid.
- * | | |1 = TK13 is always enable for key scan. TKDAT13 (TK_DAT3[15:8]) is valid.
- * |[14] |TKSEN14 |TK14 Scan Enable Bit
- * | | |This bit is ignored if TKREN14 (TK_REFCTL[14]) is "1".
- * | | |0 = TKDAT14 (TK_DAT3[23:16]) is invalid.
- * | | |1 = TK14 is always enabled for key scan. TKDAT14 (TK_DAT3[23:16]) is valid.
- * |[15] |TKSEN15 |TK15 Scan Enable Bit
- * | | |This bit is ignored if TKREN15 (TK_REFCTL[15]) is "1".
- * | | |0 = TKDAT15 (TK_DAT3[31:24]) is invalid.
- * | | |1 = TK15 is always enabled for key scan. TKDAT15 (TK_DAT3[31:24]) is valid.
- * |[16] |TKSEN16 |TK16 Scan Enable Bit
- * | | |This bit is ignored if TKREN16 (TK_REFCTL[16]) is "1".
- * | | |0 = TKDAT16 (TK_DAT4[7:0]) is invalid.
- * | | |1 = TK16 is always enabled for key scan. TKDAT16 (TK_DAT4[7:0]) is valid.
- * |[22:20] |AVCCHSEL |AVCCH Voltage Select
- * | | |000 = 1/16 VDD.
- * | | |001 = 1/8 VDD.
- * | | |010 = 3/16 VDD.
- * | | |011 = 1/4 VDD.
- * | | |100 = 5/16 VDD.
- * | | |101 = 3/8 VDD.
- * | | |110 = 7/16 VDD.
- * | | |111 = 1/2 VDD.
- * |[24] |SCAN |Scan
- * | | |Write an '1' to this bit will immediately initiate key scan on all channels which are enabled.
- * | | |This bit will be self-cleared after key scan started.
- * |[25] |TMRTRGEN |Timer Trigger Enable Bit
- * | | |0 = Disable timer to trigger key scan.
- * | | |1 = Enable timer triggers key scan periodically. Key scan will be initiated by Timer0 periodically.
- * |[31] |TKEN |Touch Key Scan Enable Bit
- * | | |0 = Disable Touch Key Function.
- * | | |1 = Enable Touch Key Function.
- * @var TK_T::REFCTL
- * Offset: 0x04 Touch Key Reference Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TKREN0 |TK0 Reference Enable Bit
- * | | |0 = TK0 is not reference.
- * | | |1 = TK0 is set as reference, and TKDAT0 (TK_DAT0[7:0]) is invalid except SCANALL (TK_REFCTL[23]) is "1".
- * |[1] |TKREN1 |TK1 Reference Enable Bit
- * | | |0 = TK1 is not reference.
- * | | |1 = TK1 is set as reference, and TKDAT1 (TK_DAT0[15:8]) is invalid.
- * |[2] |TKREN2 |TK2 Reference Enable Bit
- * | | |0 = TK2 is not reference.
- * | | |1 = TK2 is set as reference, and TKDAT2 (TK_DAT0[23:16]) is invalid.
- * |[3] |TKREN3 |TK3 Reference Enable Bit
- * | | |0 = TK3 is not reference.
- * | | |1 = TK3 is set as reference, and TKDAT3 (TK_DAT0[31:24]) is invalid.
- * |[4] |TKREN4 |TK4 Reference Enable Bit
- * | | |0 = TK4 is not reference.
- * | | |1 = TK4 is set as reference, and TKDAT4 (TK_DAT1[7:0]) is invalid.
- * |[5] |TKREN5 |TK5 Reference Enable Bit
- * | | |0 = TK5 is not reference.
- * | | |1 = TK5 is set as reference, and TKDAT5 (TK_DAT1[15:8]) is invalid.
- * |[6] |TKREN6 |TK6 Reference Enable Bit
- * | | |0 = TK6 is not reference.
- * | | |1 = TK6 is set as reference, and TKDAT6 (TK_DAT1[23:16]) is invalid.
- * |[7] |TKREN7 |TK7 Reference Enable Bit
- * | | |0 = TK7 is not reference.
- * | | |1 = TK7 is set as reference, and TKDAT7 (TK_DAT1[31:24]) is invalid.
- * |[8] |TKREN8 |TK8 Reference Enable Bit
- * | | |0 = TK8 is not reference.
- * | | |1 = TK8 is set as reference, and TKDAT8 (TK_DAT2[7:0]) is invalid.
- * |[9] |TKREN9 |TK9 Reference Enable Bit
- * | | |0 = TK9 is not reference.
- * | | |1 = TK9 is set as reference, and TKDAT9 (TK_DAT2[15:8]) is invalid.
- * |[10] |TKREN10 |TK10 Reference Enable Bit
- * | | |0 = TK10 is not reference.
- * | | |1 = TK10 is set as reference, and TKDAT10 (TK_DAT2[23:16]) is invalid.
- * |[11] |TKREN11 |TK11 Reference Enable Bit
- * | | |0 = TK11 is not reference.
- * | | |1 = TK11 is set as reference, and TKDAT11 (TK_DAT2[31:24]) is invalid.
- * |[12] |TKREN12 |TK12 Reference Enable Bit
- * | | |0 = TK12 is not reference.
- * | | |1 = TK12 is set as reference, and TKDAT12 (TK_DAT3[7:0]) is invalid.
- * |[13] |TKREN13 |TK13 Reference Enable Bit
- * | | |0 = TK13 is not reference.
- * | | |1 = TK13 is set as reference, and TKDAT13 (TK_DAT3[15:8]) is invalid.
- * |[14] |TKREN14 |TK14 Reference Enable Bit
- * | | |0 = TK14 is not reference.
- * | | |1 = TK14 is set as reference, and TKDAT14 (TK_DAT3[23:16]) is invalid.
- * |[15] |TKREN15 |TK15 Reference Enable Bit
- * | | |0 = TK15 is not reference.
- * | | |1 = TK15 is set as reference, and TKDAT15 (TK_DAT3[31:24]) is invalid.
- * |[16] |TKREN16 |TK16 Reference Enable Bit
- * | | |0 = TK16 is not reference.
- * | | |1 = TK16 is set as reference, and TKDAT16 (TK_DAT4[7:0]) is invalid.
- * | | |Note: This bit is forced to "1" automatically if none is set as reference.
- * |[23] |SCANALL |All Key Scan Enable Bit
- * | | |This function is used for low power key scanning operation.
- * | | |TKDAT0 (TK_DAT0[7:0]) is the only one valid data when key scan is complete.
- * | | |0 = Disable All Keys Scan function.
- * | | |1 = Enable All Keys Scan function.
- * |[25:24] |SENTCTL |Touch Key Sensing Time Control
- * | | |00 = 128 x SENPTCTL.
- * | | |01 = 255 x SENPTCTL.
- * | | |10 = 511 x SENPTCTL.
- * | | |11 = 1023 x SENPTCTL.
- * |[29:28] |SENPTCTL |Touch Key Sensing Pulse Width Time Control
- * | | |00 = 1us.
- * | | |01 = 2us.
- * | | |10 = 4us.
- * | | |11 = 8us.
- * @var TK_T::CCBDAT0
- * Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CCBDAT0 |TK0 Complement CB Data
- * | | |This is register is used for TK0 sensitivity adjustment.
- * |[15:8] |CCBDAT1 |TK1 Complement CB Data
- * | | |This is register is used for TK1 sensitivity adjustment.
- * |[23:16] |CCBDAT2 |TK2 Complement CB Data
- * | | |This is register is used for TK2 sensitivity adjustment.
- * |[31:24] |CCBDAT3 |TK3 Complement CB Data
- * | | |This is register is used for TK3 sensitivity adjustment.
- * @var TK_T::CCBDAT1
- * Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CCBDAT4 |TK4 Complement CB Data
- * | | |This is register is used for TK4 sensitivity adjustment.
- * |[15:8] |CCBDAT5 |TK5 Complement CB Data
- * | | |This is register is used for TK5 sensitivity adjustment.
- * |[23:16] |CCBDAT6 |TK6 Complement CB Data
- * | | |This is register is used for TK6 sensitivity adjustment.
- * |[31:24] |CCBDAT7 |TK7 Complement CB Data
- * | | |This is register is used for TK7 sensitivity adjustment.
- * @var TK_T::CCBDAT2
- * Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CCBDAT8 |TK8 Complement CB Data
- * | | |This is register is used for TK8 sensitivity adjustment.
- * |[15:8] |CCBDAT9 |TK9 Complement CB Data
- * | | |This is register is used for TK9 sensitivity adjustment.
- * |[23:16] |CCBDAT10 |TK10 Complement CB Data
- * | | |This is register is used for TK10 sensitivity adjustment.
- * |[31:24] |CCBDAT11 |TK11 Complement CB Data
- * | | |This is register is used for TK11 sensitivity adjustment.
- * @var TK_T::CCBDAT3
- * Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CCBDAT12 |TK12 Complement CB Data
- * | | |This is register is used for TK12 sensitivity adjustment.
- * |[15:8] |CCBDAT13 |TK13 Complement CB Data
- * | | |This is register is used for TK13 sensitivity adjustment.
- * |[23:16] |CCBDAT14 |TK14 Complement CB Data
- * | | |This is register is used for TK14 sensitivity adjustment.
- * |[31:24] |CCBDAT15 |TK15 Complement CB Data
- * | | |This is register is used for TK15 sensitivity adjustment.
- * @var TK_T::CCBDAT4
- * Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |CCBDAT16 |TK16 Complement CB Data
- * | | |This is register is used for TK16 sensitivity adjustment.
- * |[31:24] |REFCBDAT |Reference CB Data
- * @var TK_T::IDLESEL
- * Offset: 0x1C Touch Key Idle State Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |IDLSn |TKn Idle State Control
- * | | |This register is ignored if both TKSENn (TK_CTL[n]) and POLENn (TK_POLCTL[n+8]) are "0" or TKRENn (TK_REFCTL[n]) is "1".
- * | | |00 = TKn connected to GND.
- * | | |01 = TKn connected to AVCCH.
- * | | |10 = TKn connected to VDD.
- * | | |11 = TKn connected to VDD.
- * | | |n = 0 to 15.
- * @var TK_T::POLSEL
- * Offset: 0x20 Touch Key Polarity Select Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |POLSELn |TKn Polarity Select
- * | | |This register is ignored if POLENn (TK_POLCTL[n+8]) is "0", or either TKSENn (TK_CTL[n]) or TKRENn (TK_REFCTL[n]) is "1".
- * | | |00 = TKn connected to Gnd.
- * | | |01 = TKn connected to AVCCH.
- * | | |10 = TKn connected to VDD.
- * | | |11 = TKn connected to VDD.
- * @var TK_T::POLCTL
- * Offset: 0x24 Touch Key Polarity Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |IDLS16 |TK16 Idle State Control
- * | | |This register is ignored if both TKSEN16 (TK_CTL[16]) and POLEN16 (TK_POLCTL[24]) are "0" or TKREN16 (TK_REFCTL[16]) is "1".
- * | | |00 = TK16 connected to Gnd.
- * | | |01 = TK16 connected to AVCCH.
- * | | |10 = TK16 connected to VDD.
- * | | |11 = TK16 connected to VDD.
- * |[3:2] |POLSEL16 |TK16 Polarity Control
- * | | |This register is ignored if POLEN16 (TK_POLCTL[24]) is "0", or either TKSEN16 (TK_CTL[16]) or TKREN16 (TK_REFCTL[16]) is "1".
- * | | |00 = TK16 connected to Gnd.
- * | | |01 = TK16 connected to AVCCH.
- * | | |10 = TK16 connected to VDD.
- * | | |11 = TK16 connected to VDD.
- * |[5:4] |CBPOLSEL |Capacitor Bank Polarity Select
- * | | |00 = Gnd.
- * | | |01 = AVCCH.
- * | | |10 = VDD.
- * | | |11 = VDD.
- * |[8] |POLEN0 |TK0 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |POLEN1 |TK1 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |POLEN2 |TK2 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |POLEN3 |TK3 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |POLEN4 |TK4 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |POLEN5 |TK5 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |POLEN6 |TK6 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |POLEN7 |TK7 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |POLEN8 |TK8 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |POLEN9 |TK9 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |POLEN10 |TK10 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |POLEN11 |TK11 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |POLEN12 |TK12 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |POLEN13 |TK13 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |POLEN14 |TK14 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |POLEN15 |TK15 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |POLEN16 |TK16 Polarity Function Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |SPOTINIT |Touch Key Sensing Initial Potential Control
- * | | |0 = Key pad is connected to Gnd before sensing.
- * | | |1 = Key pad is connected to AVCCH before sensing.
- * @var TK_T::STATUS
- * Offset: 0x28 Touch Key Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSY |Touch Key Busy (Read Only)
- * | | |0 = Key scan is complete or stopped.
- * | | |1 = Key scan is proceeding.
- * |[1] |SCIF |Touch Key Scan Complete Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = Key scan is proceeding and data is not ready for read.
- * | | |1 = Key scan is complete and data is ready for read in TKDATx registers.
- * | | |Note1: The Touch Key interrupt asserts if SCINTEN bit of TK_INTEN register is set.
- * | | |Note2: The Touch Key interrupt also asserts if SCTHIEN bit of TK_INTEN register is set and any channel data value is greater/less than its threshold setting
- * |[8] |TKIF0 |TK0 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK0.
- * | | |1 = Threshold control event occurs with TK0.
- * |[9] |TKIF1 |TK1 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK1.
- * | | |1 = Threshold control event occurs with TK1.
- * |[10] |TKIF2 |TK2 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK2.
- * | | |1 = Threshold control event occurs with TK2.
- * |[11] |TKIF3 |TK3 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK3.
- * | | |1 = Threshold control event occurs with TK3.
- * |[12] |TKIF4 |TK4 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK4.
- * | | |1 = Threshold control event occurs with TK4.
- * |[13] |TKIF5 |TK5 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK5.
- * | | |1 = Threshold control event occurs with TK5.
- * |[14] |TKIF6 |TK6 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK6.
- * | | |1 = Threshold control event occurs with TK6.
- * |[15] |TKIF7 |TK7 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK7.
- * | | |1 = Threshold control event occurs with TK7.
- * |[16] |TKIF8 |TK8 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK8.
- * | | |1 = Threshold control event occurs with TK8.
- * |[17] |TKIF9 |TK9 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK9.
- * | | |1 = Threshold control event occurs with TK9.
- * |[18] |TKIF10 |TK10 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK10.
- * | | |1 = Threshold control event occurs with TK10.
- * |[19] |TKIF11 |TK11 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK11.
- * | | |1 = Threshold control event occurs with TK11.
- * |[20] |TKIF12 |TK12 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK12.
- * | | |1 = Threshold control event occurs with TK12.
- * |[21] |TKIF13 |TK13 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK13.
- * | | |1 = Threshold control event occurs with TK13.
- * |[22] |TKIF14 |TK14 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK14.
- * | | |1 = Threshold control event occurs with TK14.
- * |[23] |TKIF15 |TK15 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK15.
- * | | |1 = Threshold control event occurs with TK15.
- * |[24] |TKIF16 |TK16 Interrupt Flag
- * | | |This bit will be cleared by writing a "1" to this bit.
- * | | |0 = No threshold control event with TK16.
- * | | |1 = Threshold control event occurs with TK16.
- * @var TK_T::DAT0
- * Offset: 0x2C Touch Key Data Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TKDAT0 |TK0 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN0 (TK_CTL[0]) is "0" or TKREN0 (TK_REFCTL[0]) is "1" except SCANALL (TK_REFCTL[23]) is "1".
- * |[15:8] |TKDAT1 |TK1 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN1 (TK_CTL[1]) is "0" or TKREN1 (TK_REFCTL[1]) is "1".
- * |[23:16] |TKDAT2 |TK2 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN2 (TK_CTL[2]) is "0" or TKREN2 (TK_REFCTL[2]) is "1".
- * |[31:24] |TKDAT3 |TK3 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN3 (TK_CTL[3]) is "0" or TKREN3 (TK_REFCTL[3]) is "1".
- * @var TK_T::DAT1
- * Offset: 0x30 Touch Key Data Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TKDAT4 |TK0 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN4 (TK_CTL[4]) is "0" or TKREN4 (TK_REFCTL[4]) is "1".
- * |[15:8] |TKDAT5 |TK5 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN5 (TK_CTL[5]) is "0" or TKREN5 (TK_REFCTL[5]) is "1".
- * |[23:16] |TKDAT6 |TK6 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN6 (TK_CTL[6]) is "0" or TKREN6 (TK_REFCTL[6]) is "1".
- * |[31:24] |TKDAT7 |TK7 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN7 (TK_CTL[7]) is "0" or TKREN7 (TK_REFCTL[7]) is "1".
- * @var TK_T::DAT2
- * Offset: 0x34 Touch Key Data Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TKDAT8 |TK8 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN8 (TK_CTL[8]) is "0" or TKREN8 (TK_REFCTL[8]) is "1".
- * |[15:8] |TKDAT9 |TK9 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN9 (TK_CTL[9]) is "0" or TKREN9 (TK_REFCTL[9]) is "1".
- * |[23:16] |TKDAT10 |TK10 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN10 (TK_CTL[10]) is "0" or TKREN10 (TK_REFCTL[10]) is "1".
- * |[31:24] |TKDAT11 |TK11 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN11 (TK_CTL[11]) is "0" or TKREN11 (TK_REFCTL[11]) is "1".
- * @var TK_T::DAT3
- * Offset: 0x38 Touch Key Data Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TKDAT12 |TK12 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN12 (TK_CTL[12]) is "0" or TKREN12 (TK_REFCTL[12]) is "1".
- * |[15:8] |TKDAT13 |TK13 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN13 (TK_CTL[13]) is "0" or TKREN13 (TK_REFCTL[13]) is "1".
- * |[23:16] |TKDAT14 |TK14 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN14 (TK_CTL[14]) is "0" or TKREN14 (TK_REFCTL[14]) is "1".
- * |[31:24] |TKDAT15 |TK15 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN15 (TK_CTL[15]) is "0" or TKREN15 (TK_REFCTL[15]) is "1".
- * @var TK_T::DAT4
- * Offset: 0x3C Touch Key Data Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TKDAT16 |TK16 Sensing Result Data (Read Only)
- * | | |This data is invalid if TKSEN16 (TK_CTL[16]) is "0" or TKREN16 (TK_REFCTL[16]) is "1".
- * @var TK_T::INTEN
- * Offset: 0x40 Touch Key Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SCTHIEN |Touch Key Scan Complete With High/Low Threshold Control Interrupt Enable Bit
- * | | |0 = Key scan complete with threshold control interrupt is disable.
- * | | |1 = Key scan complete with threshold control interrupt is enable.
- * |[1] |SCINTEN |Touch Key Scan Complete Interrupt Enable
- * | | |Bit
- * | | |0 = Key scan complete without threshold control interrupt is disable.
- * | | |1 = Key scan complete without threshold control interrupt is enable.
- * |[31] |THIMOD |Touch Key Threshold Interrupt Mode Select
- * | | |0 = Edge trigger mode.
- * | | |1 = Level trigger mode.
- * @var TK_T::TH0_1
- * Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH0 |Low Threshold Of TK0
- * | | |Low level for TK0 threshold control.
- * |[15:8] |HTH0 |High Threshold Of TK0
- * | | |High level for TK0 threshold control.
- * |[23:16] |LTH1 |Low Threshold Of TK1
- * | | |Low level for TK1 threshold control.
- * |[31:24] |HTH1 |High Threshold Of TK1
- * | | |High level for TK1 threshold control.
- * @var TK_T::TH2_3
- * Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH2 |Low Threshold Of TK2
- * | | |Low level for TK2 threshold control.
- * |[15:8] |HTH2 |High Threshold Of TK2
- * | | |High level for TK2 threshold control.
- * |[23:16] |LTH3 |Low Threshold Of TK3
- * | | |Low level for TK3 threshold control.
- * |[31:24] |HTH3 |High Threshold Of TK3
- * | | |High level for TK3 threshold control.
- * @var TK_T::TH4_5
- * Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH4 |Low Threshold Of TK4
- * | | |Low level for TK4 threshold control.
- * |[15:8] |HTH4 |High Threshold Of TK4
- * | | |High level for TK4 threshold control.
- * |[23:16] |LTH5 |Low Threshold Of TK5
- * | | |Low level for TK5 threshold control.
- * |[31:24] |HTH5 |High Threshold Of TK5
- * | | |High level for TK5 threshold control.
- * @var TK_T::TH6_7
- * Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH6 |Low Threshold Of TK6
- * | | |Low level for TK6 threshold control.
- * |[15:8] |HTH6 |High Threshold Of TK6
- * | | |High level for TK6 threshold control.
- * |[23:16] |LTH7 |Low Threshold Of TK7
- * | | |Low level for TK7 threshold control.
- * |[31:24] |HTH7 |High Threshold Of TK7
- * | | |High level for TK7 threshold control.
- * @var TK_T::TH8_9
- * Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH8 |Low Threshold Of TK8
- * | | |Low level for TK8 threshold control.
- * |[15:8] |HTH8 |High Threshold Of TK8
- * | | |High level for TK8 threshold control.
- * |[23:16] |LTH9 |Low Threshold Of TK9
- * | | |Low level for TK9 threshold control.
- * |[31:24] |HTH9 |High Threshold Of TK9
- * | | |High level for TK9 threshold control.
- * @var TK_T::TH10_11
- * Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH10 |Low Threshold Of TK10
- * | | |Low level for TK10 threshold control.
- * |[15:8] |HTH10 |High Threshold Of TK10
- * | | |High level for TK10 threshold control.
- * |[23:16] |LTH11 |Low Threshold Of TK11
- * | | |Low level for TK11 threshold control.
- * |[31:24] |HTH11 |High Threshold Of TK11
- * | | |High level for TK11 threshold control.
- * @var TK_T::TH12_13
- * Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH12 |Low Threshold Of TK12
- * | | |Low level for TK12 threshold control.
- * |[15:8] |HTH12 |High Threshold Of TK12
- * | | |High level for TK12 threshold control.
- * |[23:16] |LTH13 |Low Threshold Of TK13
- * | | |Low level for TK13 threshold control.
- * |[31:24] |HTH13 |High Threshold Of TK13
- * | | |High level for TK13 threshold control.
- * @var TK_T::TH14_15
- * Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH14 |Low Threshold Of TK14
- * | | |Low level for TK14 threshold control.
- * |[15:8] |HTH14 |High Threshold Of TK14
- * | | |High level for TK14 threshold control.
- * |[23:16] |LTH15 |Low Threshold Of TK15
- * | | |Low level for TK15 threshold control.
- * |[31:24] |HTH15 |High Threshold Of TK15
- * | | |High level for TK15 threshold control.
- * @var TK_T::TH16
- * Offset: 0x64 Touch Key TK16 Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |LTH16 |Low Threshold Of TK16
- * | | |Low level for TK16 threshold control.
- * |[15:8] |HTH16 |High Threshold Of TK16
- * | | |High level for TK16 threshold control.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 Touch Key Scan Control Register */
- __IO uint32_t REFCTL; /* Offset: 0x04 Touch Key Reference Control Register */
- __IO uint32_t CCBDAT0; /* Offset: 0x08 Touch Key Complement Capacitor Bank Data Register 0 */
- __IO uint32_t CCBDAT1; /* Offset: 0x0C Touch Key Complement Capacitor Bank Data Register 1 */
- __IO uint32_t CCBDAT2; /* Offset: 0x10 Touch Key Complement Capacitor Bank Data Register 2 */
- __IO uint32_t CCBDAT3; /* Offset: 0x14 Touch Key Complement Capacitor Bank Data Register 3 */
- __IO uint32_t CCBDAT4; /* Offset: 0x18 Touch Key Complement Capacitor Bank Data Register 4 */
- __IO uint32_t IDLESEL; /* Offset: 0x1C Touch Key Idle State Control Register */
- __IO uint32_t POLSEL; /* Offset: 0x20 Touch Key Polarity Select Register */
- __IO uint32_t POLCTL; /* Offset: 0x24 Touch Key Polarity Control Register */
- __IO uint32_t STATUS; /* Offset: 0x28 Touch Key Status Register */
- __I uint32_t DAT0; /* Offset: 0x2C Touch Key Data Register 0 */
- __I uint32_t DAT1; /* Offset: 0x30 Touch Key Data Register 1 */
- __I uint32_t DAT2; /* Offset: 0x34 Touch Key Data Register 2 */
- __I uint32_t DAT3; /* Offset: 0x38 Touch Key Data Register 3 */
- __I uint32_t DAT4; /* Offset: 0x3C Touch Key Data Register 4 */
- __IO uint32_t INTEN; /* Offset: 0x40 Touch Key Interrupt Enable Register */
- __IO uint32_t TH0_1; /* Offset: 0x44 Touch Key TK0/TK1 Threshold Control Register */
- __IO uint32_t TH2_3; /* Offset: 0x48 Touch Key TK2/TK3 Threshold Control Register */
- __IO uint32_t TH4_5; /* Offset: 0x4C Touch Key TK4/TK5 Threshold Control Register */
- __IO uint32_t TH6_7; /* Offset: 0x50 Touch Key TK6/TK7 Threshold Control Register */
- __IO uint32_t TH8_9; /* Offset: 0x54 Touch Key TK8/TK9 Threshold Control Register */
- __IO uint32_t TH10_11; /* Offset: 0x58 Touch Key TK10/TK11 Threshold Control Register */
- __IO uint32_t TH12_13; /* Offset: 0x5C Touch Key TK12/TK13 Threshold Control Register */
- __IO uint32_t TH14_15; /* Offset: 0x60 Touch Key TK14/TK15 Threshold Control Register */
- __IO uint32_t TH16; /* Offset: 0x64 Touch Key TK16 Threshold Control Register */
-
-} TK_T;
-
-
-
-/**
- @addtogroup TK_CONST TK Bit Field Definition
- Constant Definitions for TK Controller
-@{ */
-
-
-#define TK_CTL_TKSEN0_Pos (0) /*!< TK_T::CTL: TKSEN0 Position */
-#define TK_CTL_TKSEN0_Msk (0x1ul << TK_CTL_TKSEN0_Pos) /*!< TK_T::CTL: TKSEN0 Mask */
-
-#define TK_CTL_TKSEN1_Pos (1) /*!< TK_T::CTL: TKSEN1 Position */
-#define TK_CTL_TKSEN1_Msk (0x1ul << TK_CTL_TKSEN1_Pos) /*!< TK_T::CTL: TKSEN1 Mask */
-
-#define TK_CTL_TKSEN2_Pos (2) /*!< TK_T::CTL: TKSEN2 Position */
-#define TK_CTL_TKSEN2_Msk (0x1ul << TK_CTL_TKSEN2_Pos) /*!< TK_T::CTL: TKSEN2 Mask */
-
-#define TK_CTL_TKSEN3_Pos (3) /*!< TK_T::CTL: TKSEN3 Position */
-#define TK_CTL_TKSEN3_Msk (0x1ul << TK_CTL_TKSEN3_Pos) /*!< TK_T::CTL: TKSEN3 Mask */
-
-#define TK_CTL_TKSEN4_Pos (4) /*!< TK_T::CTL: TKSEN4 Position */
-#define TK_CTL_TKSEN4_Msk (0x1ul << TK_CTL_TKSEN4_Pos) /*!< TK_T::CTL: TKSEN4 Mask */
-
-#define TK_CTL_TKSEN5_Pos (5) /*!< TK_T::CTL: TKSEN5 Position */
-#define TK_CTL_TKSEN5_Msk (0x1ul << TK_CTL_TKSEN5_Pos) /*!< TK_T::CTL: TKSEN5 Mask */
-
-#define TK_CTL_TKSEN6_Pos (6) /*!< TK_T::CTL: TKSEN6 Position */
-#define TK_CTL_TKSEN6_Msk (0x1ul << TK_CTL_TKSEN6_Pos) /*!< TK_T::CTL: TKSEN6 Mask */
-
-#define TK_CTL_TKSEN7_Pos (7) /*!< TK_T::CTL: TKSEN7 Position */
-#define TK_CTL_TKSEN7_Msk (0x1ul << TK_CTL_TKSEN7_Pos) /*!< TK_T::CTL: TKSEN7 Mask */
-
-#define TK_CTL_TKSEN8_Pos (8) /*!< TK_T::CTL: TKSEN8 Position */
-#define TK_CTL_TKSEN8_Msk (0x1ul << TK_CTL_TKSEN8_Pos) /*!< TK_T::CTL: TKSEN8 Mask */
-
-#define TK_CTL_TKSEN9_Pos (9) /*!< TK_T::CTL: TKSEN9 Position */
-#define TK_CTL_TKSEN9_Msk (0x1ul << TK_CTL_TKSEN9_Pos) /*!< TK_T::CTL: TKSEN9 Mask */
-
-#define TK_CTL_TKSEN10_Pos (10) /*!< TK_T::CTL: TKSEN10 Position */
-#define TK_CTL_TKSEN10_Msk (0x1ul << TK_CTL_TKSEN10_Pos) /*!< TK_T::CTL: TKSEN10 Mask */
-
-#define TK_CTL_TKSEN11_Pos (11) /*!< TK_T::CTL: TKSEN11 Position */
-#define TK_CTL_TKSEN11_Msk (0x1ul << TK_CTL_TKSEN11_Pos) /*!< TK_T::CTL: TKSEN11 Mask */
-
-#define TK_CTL_TKSEN12_Pos (12) /*!< TK_T::CTL: TKSEN12 Position */
-#define TK_CTL_TKSEN12_Msk (0x1ul << TK_CTL_TKSEN12_Pos) /*!< TK_T::CTL: TKSEN12 Mask */
-
-#define TK_CTL_TKSEN13_Pos (13) /*!< TK_T::CTL: TKSEN13 Position */
-#define TK_CTL_TKSEN13_Msk (0x1ul << TK_CTL_TKSEN13_Pos) /*!< TK_T::CTL: TKSEN13 Mask */
-
-#define TK_CTL_TKSEN14_Pos (14) /*!< TK_T::CTL: TKSEN14 Position */
-#define TK_CTL_TKSEN14_Msk (0x1ul << TK_CTL_TKSEN14_Pos) /*!< TK_T::CTL: TKSEN14 Mask */
-
-#define TK_CTL_TKSEN15_Pos (15) /*!< TK_T::CTL: TKSEN15 Position */
-#define TK_CTL_TKSEN15_Msk (0x1ul << TK_CTL_TKSEN15_Pos) /*!< TK_T::CTL: TKSEN15 Mask */
-
-#define TK_CTL_TKSEN16_Pos (16) /*!< TK_T::CTL: TKSEN16 Position */
-#define TK_CTL_TKSEN16_Msk (0x1ul << TK_CTL_TKSEN16_Pos) /*!< TK_T::CTL: TKSEN16 Mask */
-
-#define TK_CTL_AVCCHSEL_Pos (20) /*!< TK_T::CTL: AVCCHSEL Position */
-#define TK_CTL_AVCCHSEL_Msk (0x7ul << TK_CTL_AVCCHSEL_Pos) /*!< TK_T::CTL: AVCCHSEL Mask */
-
-#define TK_CTL_SCAN_Pos (24) /*!< TK_T::CTL: SCAN Position */
-#define TK_CTL_SCAN_Msk (0x1ul << TK_CTL_SCAN_Pos) /*!< TK_T::CTL: SCAN Mask */
-
-#define TK_CTL_TMRTRGEN_Pos (25) /*!< TK_T::CTL: TMRTRGEN Position */
-#define TK_CTL_TMRTRGEN_Msk (0x1ul << TK_CTL_TMRTRGEN_Pos) /*!< TK_T::CTL: TMRTRGEN Mask */
-
-#define TK_CTL_TKEN_Pos (31) /*!< TK_T::CTL: TKEN Position */
-#define TK_CTL_TKEN_Msk (0x1ul << TK_CTL_TKEN_Pos) /*!< TK_T::CTL: TKEN Mask */
-
-#define TK_REFCTL_TKREN0_Pos (0) /*!< TK_T::REFCTL: TKREN0 Position */
-#define TK_REFCTL_TKREN0_Msk (0x1ul << TK_REFCTL_TKREN0_Pos) /*!< TK_T::REFCTL: TKREN0 Mask */
-
-#define TK_REFCTL_TKREN1_Pos (1) /*!< TK_T::REFCTL: TKREN1 Position */
-#define TK_REFCTL_TKREN1_Msk (0x1ul << TK_REFCTL_TKREN1_Pos) /*!< TK_T::REFCTL: TKREN1 Mask */
-
-#define TK_REFCTL_TKREN2_Pos (2) /*!< TK_T::REFCTL: TKREN2 Position */
-#define TK_REFCTL_TKREN2_Msk (0x1ul << TK_REFCTL_TKREN2_Pos) /*!< TK_T::REFCTL: TKREN2 Mask */
-
-#define TK_REFCTL_TKREN3_Pos (3) /*!< TK_T::REFCTL: TKREN3 Position */
-#define TK_REFCTL_TKREN3_Msk (0x1ul << TK_REFCTL_TKREN3_Pos) /*!< TK_T::REFCTL: TKREN3 Mask */
-
-#define TK_REFCTL_TKREN4_Pos (4) /*!< TK_T::REFCTL: TKREN4 Position */
-#define TK_REFCTL_TKREN4_Msk (0x1ul << TK_REFCTL_TKREN4_Pos) /*!< TK_T::REFCTL: TKREN4 Mask */
-
-#define TK_REFCTL_TKREN5_Pos (5) /*!< TK_T::REFCTL: TKREN5 Position */
-#define TK_REFCTL_TKREN5_Msk (0x1ul << TK_REFCTL_TKREN5_Pos) /*!< TK_T::REFCTL: TKREN5 Mask */
-
-#define TK_REFCTL_TKREN6_Pos (6) /*!< TK_T::REFCTL: TKREN6 Position */
-#define TK_REFCTL_TKREN6_Msk (0x1ul << TK_REFCTL_TKREN6_Pos) /*!< TK_T::REFCTL: TKREN6 Mask */
-
-#define TK_REFCTL_TKREN7_Pos (7) /*!< TK_T::REFCTL: TKREN7 Position */
-#define TK_REFCTL_TKREN7_Msk (0x1ul << TK_REFCTL_TKREN7_Pos) /*!< TK_T::REFCTL: TKREN7 Mask */
-
-#define TK_REFCTL_TKREN8_Pos (8) /*!< TK_T::REFCTL: TKREN8 Position */
-#define TK_REFCTL_TKREN8_Msk (0x1ul << TK_REFCTL_TKREN8_Pos) /*!< TK_T::REFCTL: TKREN8 Mask */
-
-#define TK_REFCTL_TKREN9_Pos (9) /*!< TK_T::REFCTL: TKREN9 Position */
-#define TK_REFCTL_TKREN9_Msk (0x1ul << TK_REFCTL_TKREN9_Pos) /*!< TK_T::REFCTL: TKREN9 Mask */
-
-#define TK_REFCTL_TKREN10_Pos (10) /*!< TK_T::REFCTL: TKREN10 Position */
-#define TK_REFCTL_TKREN10_Msk (0x1ul << TK_REFCTL_TKREN10_Pos) /*!< TK_T::REFCTL: TKREN10 Mask */
-
-#define TK_REFCTL_TKREN11_Pos (11) /*!< TK_T::REFCTL: TKREN11 Position */
-#define TK_REFCTL_TKREN11_Msk (0x1ul << TK_REFCTL_TKREN11_Pos) /*!< TK_T::REFCTL: TKREN11 Mask */
-
-#define TK_REFCTL_TKREN12_Pos (12) /*!< TK_T::REFCTL: TKREN12 Position */
-#define TK_REFCTL_TKREN12_Msk (0x1ul << TK_REFCTL_TKREN12_Pos) /*!< TK_T::REFCTL: TKREN12 Mask */
-
-#define TK_REFCTL_TKREN13_Pos (13) /*!< TK_T::REFCTL: TKREN13 Position */
-#define TK_REFCTL_TKREN13_Msk (0x1ul << TK_REFCTL_TKREN13_Pos) /*!< TK_T::REFCTL: TKREN13 Mask */
-
-#define TK_REFCTL_TKREN14_Pos (14) /*!< TK_T::REFCTL: TKREN14 Position */
-#define TK_REFCTL_TKREN14_Msk (0x1ul << TK_REFCTL_TKREN14_Pos) /*!< TK_T::REFCTL: TKREN14 Mask */
-
-#define TK_REFCTL_TKREN15_Pos (15) /*!< TK_T::REFCTL: TKREN15 Position */
-#define TK_REFCTL_TKREN15_Msk (0x1ul << TK_REFCTL_TKREN15_Pos) /*!< TK_T::REFCTL: TKREN15 Mask */
-
-#define TK_REFCTL_TKREN16_Pos (16) /*!< TK_T::REFCTL: TKREN16 Position */
-#define TK_REFCTL_TKREN16_Msk (0x1ul << TK_REFCTL_TKREN16_Pos) /*!< TK_T::REFCTL: TKREN16 Mask */
-
-#define TK_REFCTL_SCANALL_Pos (23) /*!< TK_T::REFCTL: SCANALL Position */
-#define TK_REFCTL_SCANALL_Msk (0x1ul << TK_REFCTL_SCANALL_Pos) /*!< TK_T::REFCTL: SCANALL Mask */
-
-#define TK_REFCTL_SENTCTL_Pos (24) /*!< TK_T::REFCTL: SENTCTL Position */
-#define TK_REFCTL_SENTCTL_Msk (0x3ul << TK_REFCTL_SENTCTL_Pos) /*!< TK_T::REFCTL: SENTCTL Mask */
-
-#define TK_REFCTL_SENPTCTL_Pos (28) /*!< TK_T::REFCTL: SENPTCTL Position */
-#define TK_REFCTL_SENPTCTL_Msk (0x3ul << TK_REFCTL_SENPTCTL_Pos) /*!< TK_T::REFCTL: SENPTCTL Mask */
-
-#define TK_CCBDAT0_CCBDAT0_Pos (0) /*!< TK_T::CCBDAT0: CCBDAT0 Position */
-#define TK_CCBDAT0_CCBDAT0_Msk (0xfful << TK_CCBDAT0_CCBDAT0_Pos) /*!< TK_T::CCBDAT0: CCBDAT0 Mask */
-
-#define TK_CCBDAT0_CCBDAT1_Pos (8) /*!< TK_T::CCBDAT0: CCBDAT1 Position */
-#define TK_CCBDAT0_CCBDAT1_Msk (0xfful << TK_CCBDAT0_CCBDAT1_Pos) /*!< TK_T::CCBDAT0: CCBDAT1 Mask */
-
-#define TK_CCBDAT0_CCBDAT2_Pos (16) /*!< TK_T::CCBDAT0: CCBDAT2 Position */
-#define TK_CCBDAT0_CCBDAT2_Msk (0xfful << TK_CCBDAT0_CCBDAT2_Pos) /*!< TK_T::CCBDAT0: CCBDAT2 Mask */
-
-#define TK_CCBDAT0_CCBDAT3_Pos (24) /*!< TK_T::CCBDAT0: CCBDAT3 Position */
-#define TK_CCBDAT0_CCBDAT3_Msk (0xfful << TK_CCBDAT0_CCBDAT3_Pos) /*!< TK_T::CCBDAT0: CCBDAT3 Mask */
-
-#define TK_CCBDAT1_CCBDAT4_Pos (0) /*!< TK_T::CCBDAT1: CCBDAT4 Position */
-#define TK_CCBDAT1_CCBDAT4_Msk (0xfful << TK_CCBDAT1_CCBDAT4_Pos) /*!< TK_T::CCBDAT1: CCBDAT4 Mask */
-
-#define TK_CCBDAT1_CCBDAT5_Pos (8) /*!< TK_T::CCBDAT1: CCBDAT5 Position */
-#define TK_CCBDAT1_CCBDAT5_Msk (0xfful << TK_CCBDAT1_CCBDAT5_Pos) /*!< TK_T::CCBDAT1: CCBDAT5 Mask */
-
-#define TK_CCBDAT1_CCBDAT6_Pos (16) /*!< TK_T::CCBDAT1: CCBDAT6 Position */
-#define TK_CCBDAT1_CCBDAT6_Msk (0xfful << TK_CCBDAT1_CCBDAT6_Pos) /*!< TK_T::CCBDAT1: CCBDAT6 Mask */
-
-#define TK_CCBDAT1_CCBDAT7_Pos (24) /*!< TK_T::CCBDAT1: CCBDAT7 Position */
-#define TK_CCBDAT1_CCBDAT7_Msk (0xfful << TK_CCBDAT1_CCBDAT7_Pos) /*!< TK_T::CCBDAT1: CCBDAT7 Mask */
-
-#define TK_CCBDAT2_CCBDAT8_Pos (0) /*!< TK_T::CCBDAT2: CCBDAT8 Position */
-#define TK_CCBDAT2_CCBDAT8_Msk (0xfful << TK_CCBDAT2_CCBDAT8_Pos) /*!< TK_T::CCBDAT2: CCBDAT8 Mask */
-
-#define TK_CCBDAT2_CCBDAT9_Pos (8) /*!< TK_T::CCBDAT2: CCBDAT9 Position */
-#define TK_CCBDAT2_CCBDAT9_Msk (0xfful << TK_CCBDAT2_CCBDAT9_Pos) /*!< TK_T::CCBDAT2: CCBDAT9 Mask */
-
-#define TK_CCBDAT2_CCBDAT10_Pos (16) /*!< TK_T::CCBDAT2: CCBDAT10 Position */
-#define TK_CCBDAT2_CCBDAT10_Msk (0xfful << TK_CCBDAT2_CCBDAT10_Pos) /*!< TK_T::CCBDAT2: CCBDAT10 Mask */
-
-#define TK_CCBDAT2_CCBDAT11_Pos (24) /*!< TK_T::CCBDAT2: CCBDAT11 Position */
-#define TK_CCBDAT2_CCBDAT11_Msk (0xfful << TK_CCBDAT2_CCBDAT11_Pos) /*!< TK_T::CCBDAT2: CCBDAT11 Mask */
-
-#define TK_CCBDAT3_CCBDAT12_Pos (0) /*!< TK_T::CCBDAT3: CCBDAT12 Position */
-#define TK_CCBDAT3_CCBDAT12_Msk (0xfful << TK_CCBDAT3_CCBDAT12_Pos) /*!< TK_T::CCBDAT3: CCBDAT12 Mask */
-
-#define TK_CCBDAT3_CCBDAT13_Pos (8) /*!< TK_T::CCBDAT3: CCBDAT13 Position */
-#define TK_CCBDAT3_CCBDAT13_Msk (0xfful << TK_CCBDAT3_CCBDAT13_Pos) /*!< TK_T::CCBDAT3: CCBDAT13 Mask */
-
-#define TK_CCBDAT3_CCBDAT14_Pos (16) /*!< TK_T::CCBDAT3: CCBDAT14 Position */
-#define TK_CCBDAT3_CCBDAT14_Msk (0xfful << TK_CCBDAT3_CCBDAT14_Pos) /*!< TK_T::CCBDAT3: CCBDAT14 Mask */
-
-#define TK_CCBDAT3_CCBDAT15_Pos (24) /*!< TK_T::CCBDAT3: CCBDAT15 Position */
-#define TK_CCBDAT3_CCBDAT15_Msk (0xfful << TK_CCBDAT3_CCBDAT15_Pos) /*!< TK_T::CCBDAT3: CCBDAT15 Mask */
-
-#define TK_CCBDAT4_CCBDAT16_Pos (0) /*!< TK_T::CCBDAT4: CCBDAT16 Position */
-#define TK_CCBDAT4_CCBDAT16_Msk (0xfful << TK_CCBDAT4_CCBDAT16_Pos) /*!< TK_T::CCBDAT4: CCBDAT16 Mask */
-
-#define TK_CCBDAT4_REFCBDAT_Pos (24) /*!< TK_T::CCBDAT4: REFCBDAT Position */
-#define TK_CCBDAT4_REFCBDAT_Msk (0xfful << TK_CCBDAT4_REFCBDAT_Pos) /*!< TK_T::CCBDAT4: REFCBDAT Mask */
-
-#define TK_IDLESEL_IDLS_Pos (0) /*!< TK_T::IDLESEL: IDLS Position */
-#define TK_IDLESEL_IDLS_Msk (0xfffffffful << TK_IDLESEL_IDLS_Pos) /*!< TK_T::IDLESEL: IDLS Mask */
-
-#define TK_IDLESEL_IDLSn_Pos (0) /*!< TK_T::IDLESEL: IDLSn Position */
-#define TK_IDLESEL_IDLSn_Msk (0x3ul << TK_IDLESEL_IDLSn_Pos) /*!< TK_T::IDLESEL: IDLSn Mask */
-
-#define TK_POLSEL_POLSEL_Pos (0) /*!< TK_T::POLSEL: POLSEL Position */
-#define TK_POLSEL_POLSEL_Msk (0xfffffffful << TK_POLSEL_POLSEL_Pos) /*!< TK_T::POLSEL: POLSEL Mask */
-
-#define TK_POLSEL_POLSELn_Pos (0) /*!< TK_T::POLSEL: POLSELn Position */
-#define TK_POLSEL_POLSELn_Msk (0x3ul << TK_POLSEL_POLSELn_Pos) /*!< TK_T::POLSEL: POLSELn Mask */
-
-#define TK_POLCTL_IDLS16_Pos (0) /*!< TK_T::POLCTL: IDLS16 Position */
-#define TK_POLCTL_IDLS16_Msk (0x3ul << TK_POLCTL_IDLS16_Pos) /*!< TK_T::POLCTL: IDLS16 Mask */
-
-#define TK_POLCTL_POLSEL16_Pos (2) /*!< TK_T::POLCTL: POLSEL16 Position */
-#define TK_POLCTL_POLSEL16_Msk (0x3ul << TK_POLCTL_POLSEL16_Pos) /*!< TK_T::POLCTL: POLSEL16 Mask */
-
-#define TK_POLCTL_CBPOLSEL_Pos (4) /*!< TK_T::POLCTL: CBPOLSEL Position */
-#define TK_POLCTL_CBPOLSEL_Msk (0x3ul << TK_POLCTL_CBPOLSEL_Pos) /*!< TK_T::POLCTL: CBPOLSEL Mask */
-
-#define TK_POLCTL_POLEN0_Pos (8) /*!< TK_T::POLCTL: POLEN0 Position */
-#define TK_POLCTL_POLEN0_Msk (0x1ul << TK_POLCTL_POLEN0_Pos) /*!< TK_T::POLCTL: POLEN0 Mask */
-
-#define TK_POLCTL_POLEN1_Pos (9) /*!< TK_T::POLCTL: POLEN1 Position */
-#define TK_POLCTL_POLEN1_Msk (0x1ul << TK_POLCTL_POLEN1_Pos) /*!< TK_T::POLCTL: POLEN1 Mask */
-
-#define TK_POLCTL_POLEN2_Pos (10) /*!< TK_T::POLCTL: POLEN2 Position */
-#define TK_POLCTL_POLEN2_Msk (0x1ul << TK_POLCTL_POLEN2_Pos) /*!< TK_T::POLCTL: POLEN2 Mask */
-
-#define TK_POLCTL_POLEN3_Pos (11) /*!< TK_T::POLCTL: POLEN3 Position */
-#define TK_POLCTL_POLEN3_Msk (0x1ul << TK_POLCTL_POLEN3_Pos) /*!< TK_T::POLCTL: POLEN3 Mask */
-
-#define TK_POLCTL_POLEN4_Pos (12) /*!< TK_T::POLCTL: POLEN4 Position */
-#define TK_POLCTL_POLEN4_Msk (0x1ul << TK_POLCTL_POLEN4_Pos) /*!< TK_T::POLCTL: POLEN4 Mask */
-
-#define TK_POLCTL_POLEN5_Pos (13) /*!< TK_T::POLCTL: POLEN5 Position */
-#define TK_POLCTL_POLEN5_Msk (0x1ul << TK_POLCTL_POLEN5_Pos) /*!< TK_T::POLCTL: POLEN5 Mask */
-
-#define TK_POLCTL_POLEN6_Pos (14) /*!< TK_T::POLCTL: POLEN6 Position */
-#define TK_POLCTL_POLEN6_Msk (0x1ul << TK_POLCTL_POLEN6_Pos) /*!< TK_T::POLCTL: POLEN6 Mask */
-
-#define TK_POLCTL_POLEN7_Pos (15) /*!< TK_T::POLCTL: POLEN7 Position */
-#define TK_POLCTL_POLEN7_Msk (0x1ul << TK_POLCTL_POLEN7_Pos) /*!< TK_T::POLCTL: POLEN7 Mask */
-
-#define TK_POLCTL_POLEN8_Pos (16) /*!< TK_T::POLCTL: POLEN8 Position */
-#define TK_POLCTL_POLEN8_Msk (0x1ul << TK_POLCTL_POLEN8_Pos) /*!< TK_T::POLCTL: POLEN8 Mask */
-
-#define TK_POLCTL_POLEN9_Pos (17) /*!< TK_T::POLCTL: POLEN9 Position */
-#define TK_POLCTL_POLEN9_Msk (0x1ul << TK_POLCTL_POLEN9_Pos) /*!< TK_T::POLCTL: POLEN9 Mask */
-
-#define TK_POLCTL_POLEN10_Pos (18) /*!< TK_T::POLCTL: POLEN10 Position */
-#define TK_POLCTL_POLEN10_Msk (0x1ul << TK_POLCTL_POLEN10_Pos) /*!< TK_T::POLCTL: POLEN10 Mask */
-
-#define TK_POLCTL_POLEN11_Pos (19) /*!< TK_T::POLCTL: POLEN11 Position */
-#define TK_POLCTL_POLEN11_Msk (0x1ul << TK_POLCTL_POLEN11_Pos) /*!< TK_T::POLCTL: POLEN11 Mask */
-
-#define TK_POLCTL_POLEN12_Pos (20) /*!< TK_T::POLCTL: POLEN12 Position */
-#define TK_POLCTL_POLEN12_Msk (0x1ul << TK_POLCTL_POLEN12_Pos) /*!< TK_T::POLCTL: POLEN12 Mask */
-
-#define TK_POLCTL_POLEN13_Pos (21) /*!< TK_T::POLCTL: POLEN13 Position */
-#define TK_POLCTL_POLEN13_Msk (0x1ul << TK_POLCTL_POLEN13_Pos) /*!< TK_T::POLCTL: POLEN13 Mask */
-
-#define TK_POLCTL_POLEN14_Pos (22) /*!< TK_T::POLCTL: POLEN14 Position */
-#define TK_POLCTL_POLEN14_Msk (0x1ul << TK_POLCTL_POLEN14_Pos) /*!< TK_T::POLCTL: POLEN14 Mask */
-
-#define TK_POLCTL_POLEN15_Pos (23) /*!< TK_T::POLCTL: POLEN15 Position */
-#define TK_POLCTL_POLEN15_Msk (0x1ul << TK_POLCTL_POLEN15_Pos) /*!< TK_T::POLCTL: POLEN15 Mask */
-
-#define TK_POLCTL_POLEN16_Pos (24) /*!< TK_T::POLCTL: POLEN16 Position */
-#define TK_POLCTL_POLEN16_Msk (0x1ul << TK_POLCTL_POLEN16_Pos) /*!< TK_T::POLCTL: POLEN16 Mask */
-
-#define TK_POLCTL_SPOTINIT_Pos (31) /*!< TK_T::POLCTL: SPOTINIT Position */
-#define TK_POLCTL_SPOTINIT_Msk (0x1ul << TK_POLCTL_SPOTINIT_Pos) /*!< TK_T::POLCTL: SPOTINIT Mask */
-
-#define TK_STATUS_BUSY_Pos (0) /*!< TK_T::STATUS: BUSY Position */
-#define TK_STATUS_BUSY_Msk (0x1ul << TK_STATUS_BUSY_Pos) /*!< TK_T::STATUS: BUSY Mask */
-
-#define TK_STATUS_SCIF_Pos (1) /*!< TK_T::STATUS: SCIF Position */
-#define TK_STATUS_SCIF_Msk (0x1ul << TK_STATUS_SCIF_Pos) /*!< TK_T::STATUS: SCIF Mask */
-
-#define TK_STATUS_TKIF0_Pos (8) /*!< TK_T::STATUS: TKIF0 Position */
-#define TK_STATUS_TKIF0_Msk (0x1ul << TK_STATUS_TKIF0_Pos) /*!< TK_T::STATUS: TKIF0 Mask */
-
-#define TK_STATUS_TKIF1_Pos (9) /*!< TK_T::STATUS: TKIF1 Position */
-#define TK_STATUS_TKIF1_Msk (0x1ul << TK_STATUS_TKIF1_Pos) /*!< TK_T::STATUS: TKIF1 Mask */
-
-#define TK_STATUS_TKIF2_Pos (10) /*!< TK_T::STATUS: TKIF2 Position */
-#define TK_STATUS_TKIF2_Msk (0x1ul << TK_STATUS_TKIF2_Pos) /*!< TK_T::STATUS: TKIF2 Mask */
-
-#define TK_STATUS_TKIF3_Pos (11) /*!< TK_T::STATUS: TKIF3 Position */
-#define TK_STATUS_TKIF3_Msk (0x1ul << TK_STATUS_TKIF3_Pos) /*!< TK_T::STATUS: TKIF3 Mask */
-
-#define TK_STATUS_TKIF4_Pos (12) /*!< TK_T::STATUS: TKIF4 Position */
-#define TK_STATUS_TKIF4_Msk (0x1ul << TK_STATUS_TKIF4_Pos) /*!< TK_T::STATUS: TKIF4 Mask */
-
-#define TK_STATUS_TKIF5_Pos (13) /*!< TK_T::STATUS: TKIF5 Position */
-#define TK_STATUS_TKIF5_Msk (0x1ul << TK_STATUS_TKIF5_Pos) /*!< TK_T::STATUS: TKIF5 Mask */
-
-#define TK_STATUS_TKIF6_Pos (14) /*!< TK_T::STATUS: TKIF6 Position */
-#define TK_STATUS_TKIF6_Msk (0x1ul << TK_STATUS_TKIF6_Pos) /*!< TK_T::STATUS: TKIF6 Mask */
-
-#define TK_STATUS_TKIF7_Pos (15) /*!< TK_T::STATUS: TKIF7 Position */
-#define TK_STATUS_TKIF7_Msk (0x1ul << TK_STATUS_TKIF7_Pos) /*!< TK_T::STATUS: TKIF7 Mask */
-
-#define TK_STATUS_TKIF8_Pos (16) /*!< TK_T::STATUS: TKIF8 Position */
-#define TK_STATUS_TKIF8_Msk (0x1ul << TK_STATUS_TKIF8_Pos) /*!< TK_T::STATUS: TKIF8 Mask */
-
-#define TK_STATUS_TKIF9_Pos (17) /*!< TK_T::STATUS: TKIF9 Position */
-#define TK_STATUS_TKIF9_Msk (0x1ul << TK_STATUS_TKIF9_Pos) /*!< TK_T::STATUS: TKIF9 Mask */
-
-#define TK_STATUS_TKIF10_Pos (18) /*!< TK_T::STATUS: TKIF10 Position */
-#define TK_STATUS_TKIF10_Msk (0x1ul << TK_STATUS_TKIF10_Pos) /*!< TK_T::STATUS: TKIF10 Mask */
-
-#define TK_STATUS_TKIF11_Pos (19) /*!< TK_T::STATUS: TKIF11 Position */
-#define TK_STATUS_TKIF11_Msk (0x1ul << TK_STATUS_TKIF11_Pos) /*!< TK_T::STATUS: TKIF11 Mask */
-
-#define TK_STATUS_TKIF12_Pos (20) /*!< TK_T::STATUS: TKIF12 Position */
-#define TK_STATUS_TKIF12_Msk (0x1ul << TK_STATUS_TKIF12_Pos) /*!< TK_T::STATUS: TKIF12 Mask */
-
-#define TK_STATUS_TKIF13_Pos (21) /*!< TK_T::STATUS: TKIF13 Position */
-#define TK_STATUS_TKIF13_Msk (0x1ul << TK_STATUS_TKIF13_Pos) /*!< TK_T::STATUS: TKIF13 Mask */
-
-#define TK_STATUS_TKIF14_Pos (22) /*!< TK_T::STATUS: TKIF14 Position */
-#define TK_STATUS_TKIF14_Msk (0x1ul << TK_STATUS_TKIF14_Pos) /*!< TK_T::STATUS: TKIF14 Mask */
-
-#define TK_STATUS_TKIF15_Pos (23) /*!< TK_T::STATUS: TKIF15 Position */
-#define TK_STATUS_TKIF15_Msk (0x1ul << TK_STATUS_TKIF15_Pos) /*!< TK_T::STATUS: TKIF15 Mask */
-
-#define TK_STATUS_TKIF16_Pos (24) /*!< TK_T::STATUS: TKIF16 Position */
-#define TK_STATUS_TKIF16_Msk (0x1ul << TK_STATUS_TKIF16_Pos) /*!< TK_T::STATUS: TKIF16 Mask */
-
-#define TK_DAT0_TKDAT0_Pos (0) /*!< TK_T::DAT0: TKDAT0 Position */
-#define TK_DAT0_TKDAT0_Msk (0xfful << TK_DAT0_TKDAT0_Pos) /*!< TK_T::DAT0: TKDAT0 Mask */
-
-#define TK_DAT0_TKDAT1_Pos (8) /*!< TK_T::DAT0: TKDAT1 Position */
-#define TK_DAT0_TKDAT1_Msk (0xfful << TK_DAT0_TKDAT1_Pos) /*!< TK_T::DAT0: TKDAT1 Mask */
-
-#define TK_DAT0_TKDAT2_Pos (16) /*!< TK_T::DAT0: TKDAT2 Position */
-#define TK_DAT0_TKDAT2_Msk (0xfful << TK_DAT0_TKDAT2_Pos) /*!< TK_T::DAT0: TKDAT2 Mask */
-
-#define TK_DAT0_TKDAT3_Pos (24) /*!< TK_T::DAT0: TKDAT3 Position */
-#define TK_DAT0_TKDAT3_Msk (0xfful << TK_DAT0_TKDAT3_Pos) /*!< TK_T::DAT0: TKDAT3 Mask */
-
-#define TK_DAT1_TKDAT4_Pos (0) /*!< TK_T::DAT1: TKDAT4 Position */
-#define TK_DAT1_TKDAT4_Msk (0xfful << TK_DAT1_TKDAT4_Pos) /*!< TK_T::DAT1: TKDAT4 Mask */
-
-#define TK_DAT1_TKDAT5_Pos (8) /*!< TK_T::DAT1: TKDAT5 Position */
-#define TK_DAT1_TKDAT5_Msk (0xfful << TK_DAT1_TKDAT5_Pos) /*!< TK_T::DAT1: TKDAT5 Mask */
-
-#define TK_DAT1_TKDAT6_Pos (16) /*!< TK_T::DAT1: TKDAT6 Position */
-#define TK_DAT1_TKDAT6_Msk (0xfful << TK_DAT1_TKDAT6_Pos) /*!< TK_T::DAT1: TKDAT6 Mask */
-
-#define TK_DAT1_TKDAT7_Pos (24) /*!< TK_T::DAT1: TKDAT7 Position */
-#define TK_DAT1_TKDAT7_Msk (0xfful << TK_DAT1_TKDAT7_Pos) /*!< TK_T::DAT1: TKDAT7 Mask */
-
-#define TK_DAT2_TKDAT8_Pos (0) /*!< TK_T::DAT2: TKDAT8 Position */
-#define TK_DAT2_TKDAT8_Msk (0xfful << TK_DAT2_TKDAT8_Pos) /*!< TK_T::DAT2: TKDAT8 Mask */
-
-#define TK_DAT2_TKDAT9_Pos (8) /*!< TK_T::DAT2: TKDAT9 Position */
-#define TK_DAT2_TKDAT9_Msk (0xfful << TK_DAT2_TKDAT9_Pos) /*!< TK_T::DAT2: TKDAT9 Mask */
-
-#define TK_DAT2_TKDAT10_Pos (16) /*!< TK_T::DAT2: TKDAT10 Position */
-#define TK_DAT2_TKDAT10_Msk (0xfful << TK_DAT2_TKDAT10_Pos) /*!< TK_T::DAT2: TKDAT10 Mask */
-
-#define TK_DAT2_TKDAT11_Pos (24) /*!< TK_T::DAT2: TKDAT11 Position */
-#define TK_DAT2_TKDAT11_Msk (0xfful << TK_DAT2_TKDAT11_Pos) /*!< TK_T::DAT2: TKDAT11 Mask */
-
-#define TK_DAT3_TKDAT12_Pos (0) /*!< TK_T::DAT3: TKDAT12 Position */
-#define TK_DAT3_TKDAT12_Msk (0xfful << TK_DAT3_TKDAT12_Pos) /*!< TK_T::DAT3: TKDAT12 Mask */
-
-#define TK_DAT3_TKDAT13_Pos (8) /*!< TK_T::DAT3: TKDAT13 Position */
-#define TK_DAT3_TKDAT13_Msk (0xfful << TK_DAT3_TKDAT13_Pos) /*!< TK_T::DAT3: TKDAT13 Mask */
-
-#define TK_DAT3_TKDAT14_Pos (16) /*!< TK_T::DAT3: TKDAT14 Position */
-#define TK_DAT3_TKDAT14_Msk (0xfful << TK_DAT3_TKDAT14_Pos) /*!< TK_T::DAT3: TKDAT14 Mask */
-
-#define TK_DAT3_TKDAT15_Pos (24) /*!< TK_T::DAT3: TKDAT15 Position */
-#define TK_DAT3_TKDAT15_Msk (0xfful << TK_DAT3_TKDAT15_Pos) /*!< TK_T::DAT3: TKDAT15 Mask */
-
-#define TK_DAT4_TKDAT16_Pos (0) /*!< TK_T::DAT4: TKDAT16 Position */
-#define TK_DAT4_TKDAT16_Msk (0xfful << TK_DAT4_TKDAT16_Pos) /*!< TK_T::DAT4: TKDAT16 Mask */
-
-#define TK_INTEN_SCTHIEN_Pos (0) /*!< TK_T::INTEN: SCTHIEN Position */
-#define TK_INTEN_SCTHIEN_Msk (0x1ul << TK_INTEN_SCTHIEN_Pos) /*!< TK_T::INTEN: SCTHIEN Mask */
-
-#define TK_INTEN_SCINTEN_Pos (1) /*!< TK_T::INTEN: SCINTEN Position */
-#define TK_INTEN_SCINTEN_Msk (0x1ul << TK_INTEN_SCINTEN_Pos) /*!< TK_T::INTEN: SCINTEN Mask */
-
-#define TK_INTEN_THIMOD_Pos (31) /*!< TK_T::INTEN: THIMOD Position */
-#define TK_INTEN_THIMOD_Msk (0x1ul << TK_INTEN_THIMOD_Pos) /*!< TK_T::INTEN: THIMOD Mask */
-
-#define TK_TH0_1_LTH0_Pos (0) /*!< TK_T::TH0_1: LTH0 Position */
-#define TK_TH0_1_LTH0_Msk (0xfful << TK_TH0_1_LTH0_Pos) /*!< TK_T::TH0_1: LTH0 Mask */
-
-#define TK_TH0_1_HTH0_Pos (8) /*!< TK_T::TH0_1: HTH0 Position */
-#define TK_TH0_1_HTH0_Msk (0xfful << TK_TH0_1_HTH0_Pos) /*!< TK_T::TH0_1: HTH0 Mask */
-
-#define TK_TH0_1_LTH1_Pos (16) /*!< TK_T::TH0_1: LTH1 Position */
-#define TK_TH0_1_LTH1_Msk (0xfful << TK_TH0_1_LTH1_Pos) /*!< TK_T::TH0_1: LTH1 Mask */
-
-#define TK_TH0_1_HTH1_Pos (24) /*!< TK_T::TH0_1: HTH1 Position */
-#define TK_TH0_1_HTH1_Msk (0xfful << TK_TH0_1_HTH1_Pos) /*!< TK_T::TH0_1: HTH1 Mask */
-
-#define TK_TH2_3_LTH2_Pos (0) /*!< TK_T::TH2_3: LTH2 Position */
-#define TK_TH2_3_LTH2_Msk (0xfful << TK_TH2_3_LTH2_Pos) /*!< TK_T::TH2_3: LTH2 Mask */
-
-#define TK_TH2_3_HTH2_Pos (8) /*!< TK_T::TH2_3: HTH2 Position */
-#define TK_TH2_3_HTH2_Msk (0xfful << TK_TH2_3_HTH2_Pos) /*!< TK_T::TH2_3: HTH2 Mask */
-
-#define TK_TH2_3_LTH3_Pos (16) /*!< TK_T::TH2_3: LTH3 Position */
-#define TK_TH2_3_LTH3_Msk (0xfful << TK_TH2_3_LTH3_Pos) /*!< TK_T::TH2_3: LTH3 Mask */
-
-#define TK_TH2_3_HTH3_Pos (24) /*!< TK_T::TH2_3: HTH3 Position */
-#define TK_TH2_3_HTH3_Msk (0xfful << TK_TH2_3_HTH3_Pos) /*!< TK_T::TH2_3: HTH3 Mask */
-
-#define TK_TH4_5_LTH4_Pos (0) /*!< TK_T::TH4_5: LTH4 Position */
-#define TK_TH4_5_LTH4_Msk (0xfful << TK_TH4_5_LTH4_Pos) /*!< TK_T::TH4_5: LTH4 Mask */
-
-#define TK_TH4_5_HTH4_Pos (8) /*!< TK_T::TH4_5: HTH4 Position */
-#define TK_TH4_5_HTH4_Msk (0xfful << TK_TH4_5_HTH4_Pos) /*!< TK_T::TH4_5: HTH4 Mask */
-
-#define TK_TH4_5_LTH5_Pos (16) /*!< TK_T::TH4_5: LTH5 Position */
-#define TK_TH4_5_LTH5_Msk (0xfful << TK_TH4_5_LTH5_Pos) /*!< TK_T::TH4_5: LTH5 Mask */
-
-#define TK_TH4_5_HTH5_Pos (24) /*!< TK_T::TH4_5: HTH5 Position */
-#define TK_TH4_5_HTH5_Msk (0xfful << TK_TH4_5_HTH5_Pos) /*!< TK_T::TH4_5: HTH5 Mask */
-
-#define TK_TH6_7_LTH6_Pos (0) /*!< TK_T::TH6_7: LTH6 Position */
-#define TK_TH6_7_LTH6_Msk (0xfful << TK_TH6_7_LTH6_Pos) /*!< TK_T::TH6_7: LTH6 Mask */
-
-#define TK_TH6_7_HTH6_Pos (8) /*!< TK_T::TH6_7: HTH6 Position */
-#define TK_TH6_7_HTH6_Msk (0xfful << TK_TH6_7_HTH6_Pos) /*!< TK_T::TH6_7: HTH6 Mask */
-
-#define TK_TH6_7_LTH7_Pos (16) /*!< TK_T::TH6_7: LTH7 Position */
-#define TK_TH6_7_LTH7_Msk (0xfful << TK_TH6_7_LTH7_Pos) /*!< TK_T::TH6_7: LTH7 Mask */
-
-#define TK_TH6_7_HTH7_Pos (24) /*!< TK_T::TH6_7: HTH7 Position */
-#define TK_TH6_7_HTH7_Msk (0xfful << TK_TH6_7_HTH7_Pos) /*!< TK_T::TH6_7: HTH7 Mask */
-
-#define TK_TH8_9_LTH8_Pos (0) /*!< TK_T::TH8_9: LTH8 Position */
-#define TK_TH8_9_LTH8_Msk (0xfful << TK_TH8_9_LTH8_Pos) /*!< TK_T::TH8_9: LTH8 Mask */
-
-#define TK_TH8_9_HTH8_Pos (8) /*!< TK_T::TH8_9: HTH8 Position */
-#define TK_TH8_9_HTH8_Msk (0xfful << TK_TH8_9_HTH8_Pos) /*!< TK_T::TH8_9: HTH8 Mask */
-
-#define TK_TH8_9_LTH9_Pos (16) /*!< TK_T::TH8_9: LTH9 Position */
-#define TK_TH8_9_LTH9_Msk (0xfful << TK_TH8_9_LTH9_Pos) /*!< TK_T::TH8_9: LTH9 Mask */
-
-#define TK_TH8_9_HTH9_Pos (24) /*!< TK_T::TH8_9: HTH9 Position */
-#define TK_TH8_9_HTH9_Msk (0xfful << TK_TH8_9_HTH9_Pos) /*!< TK_T::TH8_9: HTH9 Mask */
-
-#define TK_TH10_11_LTH10_Pos (0) /*!< TK_T::TH10_11: LTH10 Position */
-#define TK_TH10_11_LTH10_Msk (0xfful << TK_TH10_11_LTH10_Pos) /*!< TK_T::TH10_11: LTH10 Mask */
-
-#define TK_TH10_11_HTH10_Pos (8) /*!< TK_T::TH10_11: HTH10 Position */
-#define TK_TH10_11_HTH10_Msk (0xfful << TK_TH10_11_HTH10_Pos) /*!< TK_T::TH10_11: HTH10 Mask */
-
-#define TK_TH10_11_LTH11_Pos (16) /*!< TK_T::TH10_11: LTH11 Position */
-#define TK_TH10_11_LTH11_Msk (0xfful << TK_TH10_11_LTH11_Pos) /*!< TK_T::TH10_11: LTH11 Mask */
-
-#define TK_TH10_11_HTH11_Pos (24) /*!< TK_T::TH10_11: HTH11 Position */
-#define TK_TH10_11_HTH11_Msk (0xfful << TK_TH10_11_HTH11_Pos) /*!< TK_T::TH10_11: HTH11 Mask */
-
-#define TK_TH12_13_LTH12_Pos (0) /*!< TK_T::TH12_13: LTH12 Position */
-#define TK_TH12_13_LTH12_Msk (0xfful << TK_TH12_13_LTH12_Pos) /*!< TK_T::TH12_13: LTH12 Mask */
-
-#define TK_TH12_13_HTH12_Pos (8) /*!< TK_T::TH12_13: HTH12 Position */
-#define TK_TH12_13_HTH12_Msk (0xfful << TK_TH12_13_HTH12_Pos) /*!< TK_T::TH12_13: HTH12 Mask */
-
-#define TK_TH12_13_LTH13_Pos (16) /*!< TK_T::TH12_13: LTH13 Position */
-#define TK_TH12_13_LTH13_Msk (0xfful << TK_TH12_13_LTH13_Pos) /*!< TK_T::TH12_13: LTH13 Mask */
-
-#define TK_TH12_13_HTH13_Pos (24) /*!< TK_T::TH12_13: HTH13 Position */
-#define TK_TH12_13_HTH13_Msk (0xfful << TK_TH12_13_HTH13_Pos) /*!< TK_T::TH12_13: HTH13 Mask */
-
-#define TK_TH14_15_LTH14_Pos (0) /*!< TK_T::TH14_15: LTH14 Position */
-#define TK_TH14_15_LTH14_Msk (0xfful << TK_TH14_15_LTH14_Pos) /*!< TK_T::TH14_15: LTH14 Mask */
-
-#define TK_TH14_15_HTH14_Pos (8) /*!< TK_T::TH14_15: HTH14 Position */
-#define TK_TH14_15_HTH14_Msk (0xfful << TK_TH14_15_HTH14_Pos) /*!< TK_T::TH14_15: HTH14 Mask */
-
-#define TK_TH14_15_LTH15_Pos (16) /*!< TK_T::TH14_15: LTH15 Position */
-#define TK_TH14_15_LTH15_Msk (0xfful << TK_TH14_15_LTH15_Pos) /*!< TK_T::TH14_15: LTH15 Mask */
-
-#define TK_TH14_15_HTH15_Pos (24) /*!< TK_T::TH14_15: HTH15 Position */
-#define TK_TH14_15_HTH15_Msk (0xfful << TK_TH14_15_HTH15_Pos) /*!< TK_T::TH14_15: HTH15 Mask */
-
-#define TK_TH16_LTH16_Pos (0) /*!< TK_T::TH16: LTH16 Position */
-#define TK_TH16_LTH16_Msk (0xfful << TK_TH16_LTH16_Pos) /*!< TK_T::TH16: LTH16 Mask */
-
-#define TK_TH16_HTH16_Pos (8) /*!< TK_T::TH16: HTH16 Position */
-#define TK_TH16_HTH16_Msk (0xfful << TK_TH16_HTH16_Pos) /*!< TK_T::TH16: HTH16 Mask */
-
-/**@}*/ /* TK_CONST */
-/**@}*/ /* end of TK register group */
-
-
-/*---------------------- Timer Controller -------------------------*/
-/**
- @addtogroup TMR Timer Controller(TMR)
- Memory Mapped Structure for TMR Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var TIMER_T::CTL
- * Offset: 0x00 Timer Control and Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |PSC |Prescale Counter
- * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
- * | | |If this field is 0 (PSC = 0), then there is no scaling.
- * |[17] |WKTKEN |Wake-Up Touch-Key Scan Enable Bit
- * | | |If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan.
- * | | |0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled.
- * | | |1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled.
- * | | |Note: This bit is only available in TIMER0_CTL.
- * |[18] |TRGSSEL |Trigger Source Select Bit
- * | | |This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal.
- * | | |0 = Timer time-out interrupt signal is used to trigger PWM, EADC and DAC.
- * | | |1 = Capture interrupt signal is used to trigger PWM, EADC and DAC.
- * |[19] |TRGPWM |Trigger PWM Enable Bit
- * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.
- * | | |0 = Timer interrupt trigger PWM Disabled.
- * | | |1 = Timer interrupt trigger PWM Enabled.
- * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM.
- * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
- * |[20] |TRGDAC |Trigger DAC Enable Bit
- * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
- * | | |0 = Timer interrupt trigger DAC Disabled.
- * | | |1 = Timer interrupt trigger DAC Enabled.
- * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger DAC.
- * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger DAC.
- * |[21] |TRGEADC |Trigger EADC Enable Bit
- * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC.
- * | | |0 = Timer interrupt trigger EADC Disabled.
- * | | |1 = Timer interrupt trigger EADC Enabled.
- * | | |Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC.
- * | | |If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC.
- * |[22] |TGLPINSEL |Toggle-Output Pin Select
- * | | |0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin).
- * | | |1 = Toggle mode output to Tx_EXT(Timer External Capture Pin).
- * |[23] |WKEN |Wake-Up Function Enable Bit
- * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
- * | | |0 = Wake-up function Disabled if timer interrupt signal generated.
- * | | |1 = Wake-up function Enabled if timer interrupt signal generated.
- * |[24] |EXTCNTEN |Event Counter Mode Enable Bit
- * | | |This bit is for external counting pin function enabled.
- * | | |0 = Event counter mode Disabled.
- * | | |1 = Event counter mode Enabled.
- * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
- * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
- * | | |This bit indicates the 24-bit up counter status.
- * | | |0 = 24-bit up counter is not active.
- * | | |1 = 24-bit up counter is active.
- * |[26] |RSTCNT |Timer Counter Reset Bit
- * | | |Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
- * | | |0 = No effect.
- * | | |1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
- * |[28:27] |OPMODE |Timer Counting Mode Select
- * | | |00 = The Timer controller is operated in One-shot mode.
- * | | |01 = The Timer controller is operated in Periodic mode.
- * | | |10 = The Timer controller is operated in Toggle-output mode.
- * | | |11 = The Timer controller is operated in Continuous Counting mode.
- * |[29] |INTEN |Timer Interrupt Enable Bit
- * | | |0 = Timer Interrupt Disabled.
- * | | |1 = Timer Interrupt Enabled.
- * | | |Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
- * |[30] |CNTEN |Timer Counting Enable Bit
- * | | |0 = Stops/Suspends counting.
- * | | |1 = Starts counting.
- * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
- * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
- * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable
- * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
- * | | |TIMER counter will be held while CPU is held by ICE.
- * | | |1 = ICE debug mode acknowledgement Disabled.
- * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
- * @var TIMER_T::CMP
- * Offset: 0x04 Timer Compare Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[23:0] |CMPDAT |Timer Compared Value
- * | | |CMPDAT is a 24-bit compared value register.
- * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
- * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
- * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
- * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
- * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
- * @var TIMER_T::INTSTS
- * Offset: 0x08 Timer Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TIF |Timer Interrupt Flag
- * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
- * | | |0 = No effect.
- * | | |1 = CNT value matches the CMPDAT value.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[1] |TWKF |Timer Wake-Up Flag
- * | | |This bit indicates the interrupt wake-up flag status of timer.
- * | | |0 = Timer does not cause CPU wake-up.
- * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
- * | | |Note: This bit is cleared by writing 1 to it.
- * @var TIMER_T::CNT
- * Offset: 0x0C Timer Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[23:0] |CNT |Timer Data Register
- * | | |This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin.
- * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .
- * | | |If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.
- * @var TIMER_T::CAP
- * Offset: 0x10 Timer Capture Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[23:0] |CAPDAT |Timer Capture Data Register
- * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
- * @var TIMER_T::EXTCTL
- * Offset: 0x14 Timer External Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CNTPHASE |Timer External Count Phase
- * | | |This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3).
- * | | |0 = A Falling edge of external counting pin will be counted.
- * | | |1 = A Rising edge of external counting pin will be counted.
- * |[2:1] |CAPEDGE |Timer External Capture Pin Edge Detect
- * | | |00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected.
- * | | |01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected.
- * | | |10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.
- * | | |11 = Reserved.
- * |[3] |CAPEN |Timer External Capture Pin Enable
- * | | |This bit enables the Tx_EXT pin.
- * | | |0 =Tx_EXT (x= 0~3) pin Disabled.
- * | | |1 =Tx_EXT (x= 0~3) pin Enabled.
- * |[4] |CAPFUNCS |Capture Function Selection
- * | | |0 = External Capture Mode Enabled.
- * | | |1 = External Reset Mode Enabled.
- * | | |Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
- * | | |Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
- * |[5] |CAPIEN |Timer External Capture Interrupt Enable
- * | | |0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled.
- * | | |1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled.
- * | | |Note: CAPIEN is used to enable timer external interrupt.
- * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
- * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
- * |[6] |CAPDBEN |Timer External Capture Pin De-Bounce Enable
- * | | |0 = Tx_EXT (x= 0~3) pin de-bounce Disabled.
- * | | |1 = Tx_EXT (x= 0~3) pin de-bounce Enabled.
- * | | |Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
- * |[7] |CNTDBEN |Timer Counter Pin De-Bounce Enable
- * | | |0 = Tx_CNT (x= 0~3) pin de-bounce Disabled.
- * | | |1 = Tx_CNT (x= 0~3) pin de-bounce Enabled.
- * | | |Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit.
- * @var TIMER_T::EINTSTS
- * Offset: 0x18 Timer External Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CAPIF |Timer External Capture Interrupt Flag
- * | | |This bit indicates the timer external capture interrupt flag status.
- * | | |0 = Tx_EXT (x= 0~3) pin interrupt did not occur.
- * | | |1 = Tx_EXT (x= 0~3) pin interrupt occurred.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
- * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
- * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 Timer Control and Status Register */
- __IO uint32_t CMP; /* Offset: 0x04 Timer Compare Register */
- __IO uint32_t INTSTS; /* Offset: 0x08 Timer Interrupt Status Register */
- __I uint32_t CNT; /* Offset: 0x0C Timer Data Register */
- __I uint32_t CAP; /* Offset: 0x10 Timer Capture Data Register */
- __IO uint32_t EXTCTL; /* Offset: 0x14 Timer External Control Register */
- __IO uint32_t EINTSTS; /* Offset: 0x18 Timer External Interrupt Status Register */
-
-} TIMER_T;
-
-
-
-/**
- @addtogroup TMR_CONST TMR Bit Field Definition
- Constant Definitions for TMR Controller
-@{ */
-
-#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */
-#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */
-
-#define TIMER_CTL_WKTKEN_Pos (17) /*!< TIMER_T::CTL: WKTKEN Position */
-#define TIMER_CTL_WKTKEN_Msk (0x1ul << TIMER_CTL_WKTKEN_Pos) /*!< TIMER_T::CTL: WKTKEN Mask */
-
-#define TIMER_CTL_TRGSSEL_Pos (18) /*!< TIMER_T::CTL: TRGSSEL Position */
-#define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos) /*!< TIMER_T::CTL: TRGSSEL Mask */
-
-#define TIMER_CTL_TRGPWM_Pos (19) /*!< TIMER_T::CTL: TRGPWM Position */
-#define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos) /*!< TIMER_T::CTL: TRGPWM Mask */
-
-#define TIMER_CTL_TRGDAC_Pos (20) /*!< TIMER_T::CTL: TRGDAC Position */
-#define TIMER_CTL_TRGDAC_Msk (0x1ul << TIMER_CTL_TRGDAC_Pos) /*!< TIMER_T::CTL: TRGDAC Mask */
-
-#define TIMER_CTL_TRGEADC_Pos (21) /*!< TIMER_T::CTL: TRGEADC Position */
-#define TIMER_CTL_TRGEADC_Msk (0x1ul << TIMER_CTL_TRGEADC_Pos) /*!< TIMER_T::CTL: TRGEADC Mask */
-
-#define TIMER_CTL_TGLPINSEL_Pos (22) /*!< TIMER_T::CTL: TGLPINSEL Position */
-#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */
-
-#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */
-#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */
-
-#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */
-#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */
-
-#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */
-#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */
-
-#define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER_T::CTL: RSTCNT Position */
-#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER_T::CTL: RSTCNT Mask */
-
-#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */
-#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */
-
-#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */
-#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */
-
-#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */
-#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */
-
-#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */
-#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */
-
-#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */
-#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */
-
-#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */
-#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */
-
-#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */
-#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */
-
-#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */
-#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */
-
-#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */
-#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */
-
-#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */
-#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */
-
-#define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER_T::EXTCTL: CAPEDGE Position */
-#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */
-
-#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */
-#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */
-
-#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */
-#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */
-
-#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */
-#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */
-
-#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */
-#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */
-
-#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */
-#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */
-
-#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */
-#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */
-
-/**@}*/ /* TIMER_CONST */
-/**@}*/ /* end of TIMER register group */
-
-
-/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
-/**
- @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
- Memory Mapped Structure for UART Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var UART_T::DAT
- * Offset: 0x00 UART Receive/Transmit Buffer Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |DAT |Receiving/Transmit Buffer
- * | | |Write Operation:
- * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO.
- * | | |The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
- * | | |Read Operation:
- * | | |By reading this register, the UART will return an 8-bit data received from receiving FIFO.
- * @var UART_T::INTEN
- * Offset: 0x04 UART Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit
- * | | |0 = Receive data available interrupt Disabled.
- * | | |1 = Receive data available interrupt Enabled.
- * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit
- * | | |0 = Transmit holding register empty interrupt Disabled.
- * | | |1 = Transmit holding register empty interrupt Enabled.
- * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit
- * | | |0 = Receive Line Status interrupt Disabled.
- * | | |1 = Receive Line Status interrupt Enabled.
- * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit
- * | | |0 = Modem status interrupt Disabled.
- * | | |1 = Modem status interrupt Enabled.
- * |[4] |RXTOIEN |RX Time-Out Interrupt Enable Bit
- * | | |0 = RX time-out interrupt Disabled.
- * | | |1 = RX time-out interrupt Enabled.
- * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit
- * | | |0 = Buffer error interrupt Disabled.
- * | | |1 = Buffer error interrupt Enabled.
- * |[8] |LINIEN |LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3)
- * | | |0 = LIN bus interrupt Disabled.
- * | | |1 = LIN bus interrupt Enabled.
- * | | |Note: This bit is used for LIN function mode.
- * |[9] |WKCTSIEN |nCTS Wake-Up Interrupt Enable Bit
- * | | |0 = nCTS wake-up system function Disabled.
- * | | |1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode.
- * |[10] |WKDATIEN |Incoming Data Wake-Up Interrupt Enable Bit
- * | | |0 = Incoming data wake-up system function Disabled.
- * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
- * | | |Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
- * |[11] |TOCNTEN |Time-Out Counter Enable Bit
- * | | |0 = Time-out counter Disabled.
- * | | |1 = Time-out counter Enabled.
- * |[12] |ATORTSEN |nRTS Auto-Flow Control Enable Bit
- * | | |0 = nRTS auto-flow control Disabled.
- * | | |1 = nRTS auto-flow control Enabled.
- * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
- * |[13] |ATOCTSEN |nCTS Auto-Flow Control Enable Bit
- * | | |0 = nCTS auto-flow control Disabled.
- * | | |1 = nCTS auto-flow control Enabled.
- * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
- * |[14] |TXPDMAEN |TX DMA Enable Bit
- * | | |This bit can enable or disable TX DMA service.
- * | | |0 = TX DMA Disabled.
- * | | |1 = TX DMA Enabled.
- * |[15] |RXPDMAEN |RX DMA Enable Bit
- * | | |This bit can enable or disable RX DMA service.
- * | | |0 = RX DMA Disabled.
- * | | |1 = RX DMA Enabled.
- * |[18] |ABRIEN |Auto-Baud Rate Interrupt Enable Bit
- * | | |0 = Auto-baud rate interrupt Disabled.
- * | | |1 = Auto-baud rate interrupt Enabled.
- * @var UART_T::FIFO
- * Offset: 0x08 UART FIFO Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |RXRST |RX Field Software Reset
- * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the RX internal state machine and pointers.
- * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
- * |[2] |TXRST |TX Field Software Reset
- * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the TX internal state machine and pointers.
- * | | |Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
- * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level
- * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
- * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
- * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
- * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
- * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
- * | | |Others = Reserved.
- * |[8] |RXOFF |Receiver Disable
- * | | |The receiver is disabled or not (set 1 to disable receiver)
- * | | |0 = Receiver Enabled.
- * | | |1 = Receiver Disabled.
- * | | |Note: This bit is used for RS-485 Normal Multi-drop mode.
- * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
- * |[19:16] |RTSTRGLV |nRTS Trigger Level For Auto-Flow Control Use
- * | | |0000 = nRTS Trigger Level is 1 bytes.
- * | | |0001 = nRTS Trigger Level is 4bytes.
- * | | |0010 = nRTS Trigger Level is 8 bytes.
- * | | |0011 = nRTS Trigger Level is 14 bytes.
- * | | |Others = Reserved.
- * | | |Note: This field is used for auto nRTS flow control.
- * @var UART_T::LINE
- * Offset: 0x0C UART Line Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |WLS |Word Length Selection
- * | | |This field sets UART word length.
- * | | |00 = 5 bits.
- * | | |01 = 6 bits.
- * | | |10 = 7 bits.
- * | | |11 = 8 bits.
- * |[2] |NSB |Number Of "STOP Bit"
- * | | |0 = One "STOP bit" is generated in the transmitted data.
- * | | |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
- * | | |When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
- * |[3] |PBE |Parity Bit Enable Bit
- * | | |0 = No parity bit generated Disabled.
- * | | |1 = Parity bit generated Enabled.
- * | | |Note : Parity bit is generated on each outgoing character and is checked on each incoming data.
- * |[4] |EPE |Even Parity Enable Bit
- * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
- * | | |1 = Even number of logic 1's is transmitted and checked in each word.
- * | | |Note:This bit has effect only when PBE (UART_LINE[3]) is set.
- * |[5] |SPE |Stick Parity Enable Bit
- * | | |0 = Stick parity Disabled.
- * | | |1 = Stick parity Enabled.
- * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
- * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
- * |[6] |BCB |Break Control Bit
- * | | |0 = Break Control Disabled.
- * | | |1 = Break Control Enabled.
- * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
- * | | |This bit acts only on TX line and has no effect on the transmitter logic.
- * @var UART_T::MODEM
- * Offset: 0x10 UART Modem Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |RTS |nRTS (Request-To-Send) Signal Control
- * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
- * | | |0 = nRTS signal is active.
- * | | |1 = nRTS signal is inactive.
- * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
- * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
- * |[9] |RTSACTLV |nRTS Pin Active Level
- * | | |This bit defines the active level state of nRTS pin output.
- * | | |0 =n RTS pin output is high level active.
- * | | |1 = nRTS pin output is low level active. (Default)
- * | | |Note1: Refer to Figure 6.21-10 and Figure 6.21-11 for UART function mode.
- * | | |Note2: Refer to Figure 6.21-21 and Figure 6.21-22 for RS-485 function mode.
- * |[13] |RTSSTS |nRTS Pin Status (Read Only)
- * | | |This bit mirror from nRTS pin output of voltage logic status.
- * | | |0 = nRTS pin output is low level voltage logic state.
- * | | |1 = nRTS pin output is high level voltage logic state.
- * @var UART_T::MODEMSTS
- * Offset: 0x14 UART Modem Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CTSDETF |Detect nCTS State Change Flag (Read Only)
- * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
- * | | |0 = nCTS input has not change state.
- * | | |1 = nCTS input has change state.
- * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
- * |[4] |CTSSTS |nCTS Pin Status (Read Only)
- * | | |This bit mirror from nCTS pin input of voltage logic status.
- * | | |0 = nCTS pin input is low level voltage logic state.
- * | | |1 = nCTS pin input is high level voltage logic state.
- * | | |Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
- * |[8] |CTSACTLV |nCTS Pin Active Level
- * | | |This bit defines the active level state of nCTS pin input.
- * | | |0 = nCTS pin input is high level active.
- * | | |1 = nCTS pin input is low level active. (Default)
- * @var UART_T::FIFOSTS
- * Offset: 0x18 UART FIFO Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXOVIF |RX Overflow Error Interrupt Flag (Read Only)
- * | | |This bit is set when RX FIFO overflow.
- * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
- * | | |0 = RX FIFO is not overflow.
- * | | |1 = RX FIFO is overflow.
- * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
- * |[1] |ABRDIF |Auto-Baud Rate Detect Interrupt (Read Only)
- * | | |0 = Auto-baud rate detect function is not finished.
- * | | |1 = Auto-baud rate detect function is finished.
- * | | |This bit is set to logic "1" when auto-baud rate detect function is finished.
- * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
- * |[2] |ABRDTOIF |Auto-Baud Rate Time-Out Interrupt (Read Only)
- * | | |0 = Auto-baud rate counter is underflow.
- * | | |1 = Auto-baud rate counter is overflow.
- * | | |Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
- * | | |Note2: This bit is read only, but can be cleared by writing "1" to it.
- * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag (Read Only)
- * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
- * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1').
- * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .
- * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
- * |[4] |PEF |Parity Error Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
- * | | |0 = No parity error is generated.
- * | | |1 = Parity error is generated.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[5] |FEF |Framing Error Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
- * | | |0 = No framing error is generated.
- * | | |1 = Framing error is generated.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[6] |BIF |Break Interrupt Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
- * | | |0 = No Break interrupt is generated.
- * | | |1 = Break interrupt is generated.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[13:8] |RXPTR |RX FIFO Pointer (Read Only)
- * | | |This field indicates the RX FIFO Buffer Pointer.
- * | | |When UART receives one byte from external device, RXPTR increases one.
- * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
- * | | |The Maximum value shown in RXPTR is 15.
- * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
- * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
- * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
- * | | |This bit initiate RX FIFO empty or not.
- * | | |0 = RX FIFO is not empty.
- * | | |1 = RX FIFO is empty.
- * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
- * | | |It will be cleared when UART receives any new data.
- * |[15] |RXFULL |Receiver FIFO Full (Read Only)
- * | | |This bit initiates RX FIFO full or not.
- * | | |0 = RX FIFO is not full.
- * | | |1 = RX FIFO is full.
- * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
- * |[21:16] |TXPTR |TX FIFO Pointer (Read Only)
- * | | |This field indicates the TX FIFO Buffer Pointer.
- * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.
- * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
- * | | |The Maximum value shown in TXPTR is 15.
- * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
- * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
- * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
- * | | |This bit indicates TX FIFO empty or not.
- * | | |0 = TX FIFO is not empty.
- * | | |1 = TX FIFO is empty.
- * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
- * | | |It will be cleared when writing data into DAT (TX FIFO not empty).
- * |[23] |TXFULL |Transmitter FIFO Full (Read Only)
- * | | |This bit indicates TX FIFO full or not.
- * | | |0 = TX FIFO is not full.
- * | | |1 = TX FIFO is full.
- * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
- * |[24] |TXOVIF |TX Overflow Error Interrupt Flag (Read Only)
- * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
- * | | |0 = TX FIFO is not overflow.
- * | | |1 = TX FIFO is overflow.
- * | | |Note: This bit is read only, but can be cleared by writing "1" to it.
- * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
- * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
- * | | |0 = TX FIFO is not empty.
- * | | |1 = TX FIFO is empty.
- * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
- * @var UART_T::INTSTS
- * Offset: 0x1C UART Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only)
- * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
- * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
- * | | |0 = No RDA interrupt flag is generated.
- * | | |1 = RDA interrupt flag is generated.
- * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])).
- * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only)
- * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
- * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
- * | | |0 = No THRE interrupt flag is generated.
- * | | |1 = THRE interrupt flag is generated.
- * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
- * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
- * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
- * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
- * | | |0 = No RLS interrupt flag is generated.
- * | | |1 = RLS interrupt flag is generated.
- * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit.
- * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
- * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
- * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
- * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
- * | | |0 = No Modem interrupt flag is generated.
- * | | |1 = Modem interrupt flag is generated.
- * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
- * |[4] |RXTOIF |Time-Out Interrupt Flag (Read Only)
- * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
- * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
- * | | |0 = No Time-out interrupt flag is generated.
- * | | |1 = Time-out interrupt flag is generated.
- * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
- * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
- * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
- * | | |When BERRIF (UART_INTSTS[5])is set, the transfer is not correct.
- * | | |If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
- * | | |0 = No buffer error interrupt flag is generated.
- * | | |1 = Buffer error interrupt flag is generated.
- * | | |Note: This bit is read only.
- * | | |This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
- * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only)
- * | | |This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.
- * | | |0 = No DATWKIF and CTSWKIF are generated.
- * | | |1 = DATWKIF or CTSWKIF.
- * | | |Note: This bit is read only.
- * | | |This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
- * |[7] |LINIF |LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel)
- * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])).
- * | | |If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
- * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
- * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
- * | | |Note: This bit is read only.
- * | | |This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
- * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
- * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
- * | | |0 = No RDA interrupt is generated.
- * | | |1 = RDA interrupt is generated.
- * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only)
- * | | |This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.
- * | | |0 = No DATE interrupt is generated.
- * | | |1 = DATE interrupt is generated.
- * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
- * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
- * | | |0 = No RLS interrupt is generated.
- * | | |1 = RLS interrupt is generated.
- * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
- * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1
- * | | |0 = No Modem interrupt is generated.
- * | | |1 = Modem interrupt is generated.
- * |[12] |RXTOINT |Time-Out Interrupt Indicator (Read Only)
- * | | |This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
- * | | |0 = No Tout interrupt is generated.
- * | | |1 = Tout interrupt is generated.
- * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
- * | | |This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1.
- * | | |0 = No buffer error interrupt is generated.
- * | | |1 = Buffer error interrupt is generated.
- * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel)
- * | | |This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.
- * | | |0 = No LIN Bus interrupt is generated.
- * | | |1 = The LIN Bus interrupt is generated.
- * |[16] |CTSWKIF |nCTS Wake-Up Interrupt Flag (Read Only)
- * | | |0 = Chip stays in power-down state.
- * | | |1 = Chip wake-up from power-down state by nCTS wake-up.
- * | | |Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.
- * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
- * |[17] |DATWKIF |Data Wake-Up Interrupt Flag (Read Only)
- * | | |This bit is set if chip wake-up from power-down state by data wake-up.
- * | | |0 = Chip stays in power-down state.
- * | | |1 = Chip wake-up from power-down state by data wake-up.
- * | | |Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.
- * | | |Note2: This bit is read only, but can be cleared by writing '1' to it.
- * |[18] |HWRLSIF |In DMA Mode, Receive Line Status Flag (Read Only)
- * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
- * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
- * | | |0 = No RLS interrupt flag is generated.
- * | | |1 = RLS interrupt flag is generated.
- * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
- * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
- * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
- * |[19] |HWMODIF |In DMA Mode, MODEM Interrupt Flag (Read Only)
- * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)).
- * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
- * | | |0 = No Modem interrupt flag is generated.
- * | | |1 = Modem interrupt flag is generated.
- * | | |Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]).
- * |[20] |HWTOIF |In DMA Mode, Time-Out Interrupt Flag (Read Only)
- * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
- * | | |If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
- * | | |0 = No Time-out interrupt flag is generated.
- * | | |1 = Time-out interrupt flag is generated.
- * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
- * |[21] |HWBUFEIF |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
- * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
- * | | |When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
- * | | |If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
- * | | |0 = No buffer error interrupt flag is generated.
- * | | |1 = Buffer error interrupt flag is generated.
- * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
- * |[26] |HWRLSINT |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
- * | | |This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1.
- * | | |0 = No RLS interrupt is generated in DMA mode.
- * | | |1 = RLS interrupt is generated in DMA mode.
- * |[27] |HWMODINT |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
- * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1.
- * | | |0 = No Modem interrupt is generated in DMA mode.
- * | | |1 = Modem interrupt is generated in DMA mode.
- * |[28] |HWTOINT |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
- * | | |This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1.
- * | | |0 = No Tout interrupt is generated in DMA mode.
- * | | |1 = Tout interrupt is generated in DMA mode.
- * |[29] |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
- * | | |This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1.
- * | | |0 = No buffer error interrupt is generated in DMA mode.
- * | | |1 = Buffer error interrupt is generated in DMA mode.
- * @var UART_T::TOUT
- * Offset: 0x20 UART Time-out Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |TOIC |Time-Out Interrupt Comparator
- * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
- * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
- * | | |A new incoming data word or RX FIFO empty will clear RXTOINT(UART_INTSTS[12]).
- * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
- * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
- * |[15:8] |DLY |TX Delay Time Value
- * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit.
- * | | |The unit is bit time.
- * @var UART_T::BAUD
- * Offset: 0x24 UART Baud Rate Divisor Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |BRD |Baud Rate Divider
- * | | |The field indicates the baud rate divider.
- * | | |This filed is used in baud rate calculation.
- * | | |The detail description is shown in Table 6.21-2.
- * |[27:24] |EDIVM1 |Extra Divider For BAUD Rate Mode 1
- * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
- * | | |The detail description is shown in Table 6.21-2.
- * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0
- * | | |This bit is baud rate mode selection bit 0.
- * | | |UART provides three baud rate calculation modes.
- * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
- * | | |The detail description is shown in Table 6.21-2.
- * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1
- * | | |This bit is baud rate mode selection bit 1.
- * | | |UART provides three baud rate calculation modes.
- * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
- * | | |The detail description is shown in Table 6.21-2.
- * | | |Note: In IrDA mode must be operated in mode 0.
- * @var UART_T::IRDA
- * Offset: 0x28 UART IrDA Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
- * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
- * | | |1 = IrDA Transmitter Enabled and Receiver Disabled.
- * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
- * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
- * | | |0 = None inverse transmitting signal. (Default)
- * | | |1 = Inverse transmitting output signal.
- * |[6] |RXINV |IrDA Inverse Receive Input Signal
- * | | |0 = None inverse receiving input signal.
- * | | |1 = Inverse receiving input signal. (Default)
- * @var UART_T::ALTCTL
- * Offset: 0x2C UART Alternate Control/Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |BRKFL |UART LIN Break Field Length (Only Available In UART0/UART1 Channel)
- * | | |This field indicates a 4-bit LIN TX break field count.
- * | | |Note1: This break field length is BRKFL + 1
- * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
- * |[6] |LINRXEN |LIN RX Enable Bit (Only Available In UART0/UART1 Channel)
- * | | |0 = LIN RX mode Disabled.
- * | | |1 = LIN RX mode Enabled.
- * |[7] |LINTXEN |LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel)
- * | | |0 = LIN TX Break mode Disabled.
- * | | |1 = LIN TX Break mode Enabled.
- * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
- * |[8] |RS485NMM |RS-485 Normal Multi-Drop Operation Mode (NMM)
- * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
- * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
- * | | |Note: It cannot be active with RS-485_AAD operation mode.
- * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
- * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
- * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
- * | | |Note: It cannot be active with RS-485_NMM operation mode.
- * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD)
- * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
- * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
- * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
- * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit
- * | | |This bit is used to enable RS-485 Address Detection mode.
- * | | |0 = Address detection mode Disabled.
- * | | |1 = Address detection mode Enabled.
- * | | |Note: This bit is used for RS-485 any operation mode.
- * |[17] |ABRIF |Auto-Baud Rate Interrupt Flag (Read Only)
- * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
- * | | |Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
- * |[18] |ABRDEN |Auto-Baud Rate Detect Enable Bit
- * | | |0 = Auto-baud rate detect function Disabled.
- * | | |1 = Auto-baud rate detect function Enabled.
- * | | |This bit is cleared automatically after auto-baud detection is finished.
- * |[20:19] |ABRDBITS |Auto-Baud Rate Detect Bit Length
- * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
- * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
- * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
- * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
- * | | |Note : The calculation of bit number includes the START bit.
- * |[31:24] |ADDRMV |Address Match Value
- * | | |This field contains the RS-485 address match values.
- * | | |Note: This field is used for RS-485 auto address detection mode.
- * @var UART_T::FUNCSEL
- * Offset: 0x30 UART Function Select Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |FUNCSEL |Function Select
- * | | |00 = UART function.
- * | | |01 = LIN function (Only Available in UART0/UART1 Channel).
- * | | |10 = IrDA function.
- * | | |11 = RS-485 function.
- * | | |Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
- * @var UART_T::LINCTL
- * Offset: 0x34 UART LIN Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SLVEN |LIN Slave Mode Enable Bit
- * | | |0 = LIN slave mode Disabled.
- * | | |1 = LIN slave mode Enabled.
- * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit
- * | | |0 = LIN slave header detection Disabled.
- * | | |1 = LIN slave header detection Enabled.
- * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
- * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.
- * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
- * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit
- * | | |0 = LIN automatic resynchronization Disabled.
- * | | |1 = LIN automatic resynchronization Enabled.
- * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
- * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
- * | | |Note3: The control and interactions of this field are explained in 6.21.5.9(Slave mode with automatic resynchronization).
- * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit
- * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
- * | | |1 = UART_BAUD is updated at the next received character.
- * | | |User must set the bit before checksum reception.
- * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
- * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode.
- * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared).
- * | | |Note3: The control and interactions of this field are explained in 6.21.5.9 (Slave mode with automatic resynchronization).
- * |[4] |MUTE |LIN Mute Mode Enable Bit
- * | | |0 = LIN mute mode Disabled.
- * | | |1 = LIN mute mode Enabled.
- * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.21.5.9 (LIN slave mode).
- * |[8] |SENDH |LIN TX Send Header Enable Bit
- * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]).
- * | | |0 = Send LIN TX header Disabled.
- * | | |1 = Send LIN TX header Enabled.
- * | | |Note1: These registers are shadow registers of SENDH (UART_ALTCTL [7]); user can read/write it by setting SENDH (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
- * | | |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
- * |[9] |IDPEN |LIN ID Parity Enable Bit
- * | | |0 = LIN frame ID parity Disabled.
- * | | |1 = LIN frame ID parity Enabled.
- * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8]) = 1 and HSEL (UART_LINCTL[23:22]) = 10) or be used for enable LIN slave received frame ID parity checked.
- * | | |Note2: This bit is only use when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10
- * |[10] |BRKDETEN |LIN Break Detection Enable Bit
- * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set in UART_LINSTS register at the end of break field.
- * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
- * | | |0 = LIN break detection Disabled .
- * | | |1 = LIN break detection Enabled.
- * |[11] |RXOFF |LIN Receiver Disable Bit
- * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0),
- * | | |all received byte data will be accepted and stored in the RX-FIFO,
- * | | |and if the receiver is disabled (RXOFF (UART_LINCTL[11]) = 1), all received byte data will be ignore.
- * | | |0 = LIN receiver Enabled.
- * | | |1 = LIN receiver Disabled.
- * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
- * |[12] |BITERREN |Bit Error Detect Enable Bit
- * | | |0 = Bit error detection function Disabled.
- * | | |1 = Bit error detection Enabled.
- * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.
- * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
- * |[19:16] |BRKFL |LIN Break Field Length
- * | | |This field indicates a 4-bit LIN TX break field count.
- * | | |Note1: These registers are shadow registers of BRKFL, User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
- * | | |Note2: This break field length is BRKFL + 1.
- * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
- * |[21:20] |BSL |LIN Break/Sync Delimiter Length
- * | | |00 = The LIN break/sync delimiter length is 1-bit time.
- * | | |01 = The LIN break/sync delimiter length is 2-bit time.
- * | | |10 = The LIN break/sync delimiter length is 3-bit time.
- * | | |11 = The LIN break/sync delimiter length is 4-bit time.
- * | | |Note: This bit used for LIN master to sending header field.
- * |[23:22] |HSEL |LIN Header Select
- * | | |00 = The LIN header includes "break field".
- * | | |01 = The LIN header includes "break field" and "sync field".
- * | | |10 = The LIN header includes "break field", "sync field" and "frame ID field".
- * | | |11 = Reserved.
- * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4]) = 1).
- * |[31:24] |PID |LIN PID Bits
- * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
- * | | |If the parity generated by hardware, user fill ID0~ID5, (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
- * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
- * | | |Note2: This field can be used for LIN master mode or slave mode.
- * @var UART_T::LINSTS
- * Offset: 0x38 UART LIN Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SLVHDETF |LIN Slave Header Detection Flag (Read Only)
- * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
- * | | |0 = LIN header not detected.
- * | | |1 = LIN header detected (break + sync + frame ID).
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
- * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not.
- * |[1] |SLVHEF |LIN Slave Header Error Flag (Read Only)
- * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
- * | | |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", "sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out".
- * | | |0 = LIN header error not detected.
- * | | |1 = LIN header error detected.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
- * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag
- * | | |This bit is set by hardware when receipted frame ID parity is not correct.
- * | | |0 = No active.
- * | | |1 = Receipted frame ID parity is not correct.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
- * |[3] |SLVSYNCF |LIN Slave Sync Field (Read Only)
- * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
- * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
- * | | |0 = The current character is not at LIN sync state.
- * | | |1 = The current character is at LIN sync state.
- * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
- * | | |Note2: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
- * |[8] |BRKDETF |LIN Break Detection Flag (Read Only)
- * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
- * | | |0 = LIN break not detected.
- * | | |1 = LIN break detected.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1).
- * |[9] |BITEF |Bit Error Detect Status Flag (Read Only)
- * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF (UART_LINSTS[9]) will be set.
- * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
- */
-
- __IO uint32_t DAT; /* Offset: 0x00 UART Receive/Transmit Buffer Register */
- __IO uint32_t INTEN; /* Offset: 0x04 UART Interrupt Enable Register */
- __IO uint32_t FIFO; /* Offset: 0x08 UART FIFO Control Register */
- __IO uint32_t LINE; /* Offset: 0x0C UART Line Control Register */
- __IO uint32_t MODEM; /* Offset: 0x10 UART Modem Control Register */
- __IO uint32_t MODEMSTS; /* Offset: 0x14 UART Modem Status Register */
- __IO uint32_t FIFOSTS; /* Offset: 0x18 UART FIFO Status Register */
- __IO uint32_t INTSTS; /* Offset: 0x1C UART Interrupt Status Register */
- __IO uint32_t TOUT; /* Offset: 0x20 UART Time-out Register */
- __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
- __IO uint32_t IRDA; /* Offset: 0x28 UART IrDA Control Register */
- __IO uint32_t ALTCTL; /* Offset: 0x2C UART Alternate Control/Status Register */
- __IO uint32_t FUNCSEL; /* Offset: 0x30 UART Function Select Register */
- __IO uint32_t LINCTL; /* Offset: 0x34 UART LIN Control Register */
- __IO uint32_t LINSTS; /* Offset: 0x38 UART LIN Status Register */
-
-} UART_T;
-
-
-
-/**
- @addtogroup UART_CONST UART Bit Field Definition
- Constant Definitions for UART Controller
-@{ */
-
-#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */
-#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */
-
-#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */
-#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */
-
-#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */
-#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */
-
-#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */
-#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */
-
-#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */
-#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */
-
-#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */
-#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */
-
-#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */
-#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */
-
-#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */
-#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */
-
-#define UART_INTEN_WKCTSIEN_Pos (9) /*!< UART_T::INTEN: WKCTSIEN Position */
-#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /*!< UART_T::INTEN: WKCTSIEN Mask */
-
-#define UART_INTEN_WKDATIEN_Pos (10) /*!< UART_T::INTEN: WKDATIEN Position */
-#define UART_INTEN_WKDATIEN_Msk (0x1ul << UART_INTEN_WKDATIEN_Pos) /*!< UART_T::INTEN: WKDATIEN Mask */
-
-#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */
-#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */
-
-#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */
-#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */
-
-#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */
-#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */
-
-#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */
-#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */
-
-#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */
-#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */
-
-#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */
-#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */
-
-#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */
-#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */
-
-#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */
-#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */
-
-#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */
-#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */
-
-#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */
-#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */
-
-#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */
-#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */
-
-#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */
-#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */
-
-#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */
-#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */
-
-#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */
-#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */
-
-#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */
-#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */
-
-#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */
-#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */
-
-#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */
-#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */
-
-#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */
-#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */
-
-#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */
-#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */
-
-#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */
-#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */
-
-#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */
-#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */
-
-#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */
-#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */
-
-#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */
-#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */
-
-#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */
-#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */
-
-#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */
-#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */
-
-#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */
-#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */
-
-#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */
-#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */
-
-#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */
-#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */
-
-#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */
-#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */
-
-#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */
-#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */
-
-#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */
-#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */
-
-#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */
-#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */
-
-#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */
-#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */
-
-#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */
-#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */
-
-#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */
-#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */
-
-#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */
-#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */
-
-#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */
-#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */
-
-#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */
-#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */
-
-#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */
-#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */
-
-#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */
-#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */
-
-#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */
-#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */
-
-#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */
-#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */
-
-#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */
-#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */
-
-#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */
-#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */
-
-#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */
-#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */
-
-#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */
-#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */
-
-#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */
-#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */
-
-#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */
-#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */
-
-#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */
-#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */
-
-#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */
-#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */
-
-#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */
-#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */
-
-#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */
-#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */
-
-#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */
-#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */
-
-#define UART_INTSTS_CTSWKIF_Pos (16) /*!< UART_T::INTSTS: CTSWKIF Position */
-#define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos) /*!< UART_T::INTSTS: CTSWKIF Mask */
-
-#define UART_INTSTS_DATWKIF_Pos (17) /*!< UART_T::INTSTS: DATWKIF Position */
-#define UART_INTSTS_DATWKIF_Msk (0x1ul << UART_INTSTS_DATWKIF_Pos) /*!< UART_T::INTSTS: DATWKIF Mask */
-
-#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */
-#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */
-
-#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */
-#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */
-
-#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */
-#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */
-
-#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */
-#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */
-
-#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */
-#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */
-
-#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */
-#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */
-
-#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */
-#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */
-
-#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */
-#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */
-
-#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */
-#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */
-
-#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */
-#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */
-
-#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */
-#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */
-
-#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */
-#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */
-
-#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */
-#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */
-
-#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */
-#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */
-
-#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */
-#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */
-
-#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */
-#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */
-
-#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */
-#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */
-
-#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */
-#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */
-
-#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */
-#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */
-
-#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */
-#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */
-
-#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */
-#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */
-
-#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */
-#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */
-
-#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */
-#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */
-
-#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */
-#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */
-
-#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */
-#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */
-
-#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */
-#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */
-
-#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */
-#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */
-
-#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */
-#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */
-
-#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */
-#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */
-
-#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */
-#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */
-
-#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */
-#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */
-
-#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */
-#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */
-
-#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */
-#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */
-
-#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */
-#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */
-
-#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */
-#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */
-
-#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */
-#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */
-
-#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */
-#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */
-
-#define UART_LINCTL_RXOFF_Pos (11) /*!< UART_T::LINCTL: RXOFF Position */
-#define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /*!< UART_T::LINCTL: RXOFF Mask */
-
-#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */
-#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */
-
-#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */
-#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */
-
-#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */
-#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */
-
-#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */
-#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */
-
-#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */
-#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */
-
-#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */
-#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */
-
-#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */
-#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */
-
-#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */
-#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */
-
-#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */
-#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */
-
-#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */
-#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */
-
-#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */
-#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */
-
-
-/**@}*/ /* UART_CONST */
-/**@}*/ /* end of UART register group */
-
-
-/*---------------------- Universal Serial Bus Controller -------------------------*/
-/**
- @addtogroup USB Universal Serial Bus Controller(USB)
- Memory Mapped Structure for USB Controller
-@{ */
-
-/**
- * @brief USBD endpoints register
- */
-
-typedef struct
-{
-
-
-/**
- * @var USBD_EP_T::BUFSEG
- * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8:3] |BUFSEG |Endpoint Buffer Segmentation
- * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
- * | | |USB_SRAM address + { BUFSEG[8:3], 3'b000}
- * | | |Where the USB_SRAM address = USBD_BA+0x100h.
- * | | |Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description.
- * @var USBD_EP_T::MXPLD
- * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8:0] |MXPLD |Maximal Payload
- * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
- * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
- * | | |(1) When the register is written by CPU,
- * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
- * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
- * | | |(2) When the register is read by CPU,
- * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host
- * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
- * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
- * @var USBD_EP_T::CFG
- * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[3:0] |EPNUM |Endpoint Number
- * | | |These bits are used to define the endpoint number of the current endpoint.
- * |[4] |ISOCH |Isochronous Endpoint
- * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
- * | | |0 = No Isochronous endpoint.
- * | | |1 = Isochronous endpoint.
- * |[6:5] |STATE |Endpoint STATE
- * | | |00 = Endpoint is Disabled.
- * | | |01 = Out endpoint.
- * | | |10 = IN endpoint.
- * | | |11 = Undefined.
- * |[7] |DSQSYNC |Data Sequence Synchronization
- * | | |0 = DATA0 PID.
- * | | |1 = DATA1 PID.
- * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
- * | | |Hardware will toggle automatically in IN token base on the bit.
- * |[9] |CSTALL |Clear STALL Response
- * | | |0 = Disable the device to clear the STALL handshake in setup stage.
- * | | |1 = Clear the device to response STALL handshake in setup stage.
- * @var USBD_EP_T::CFGP
- * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CLRRDY |Clear Ready
- * | | |When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
- * | | |If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
- * | | |For IN token, write 1 to clear the IN token had ready to transmit the data to USB.
- * | | |For OUT token, write 1 to clear the OUT token had ready to receive the data from USB.
- * | | |This bit is write 1 only and is always 0 when it is read back.
- * |[1] |SSTALL |Set STALL
- * | | |0 = Disable the device to response STALL.
- * | | |1 = Set the device to respond STALL automatically.
- */
-
- __IO uint32_t BUFSEG; /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register */
- __IO uint32_t MXPLD; /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register */
- __IO uint32_t CFG; /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register */
- __IO uint32_t CFGP; /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
-
-} USBD_EP_T;
-
-
-
-
-
-typedef struct
-{
-
-
-/**
- * @var USBD_T::INTEN
- * Offset: 0x00 USB Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSIEN |Bus Event Interrupt Enable
- * | | |0 = BUS event interrupt Disabled.
- * | | |1 = BUS event interrupt Enabled.
- * |[1] |USBIEN |USB Event Interrupt Enable
- * | | |0 = USB event interrupt Disabled.
- * | | |1 = USB event interrupt Enabled.
- * |[2] |VBDETIEN |VBUS Detection Interrupt Enable
- * | | |0 = Floating detection Interrupt Disabled.
- * | | |1 = Floating detection Interrupt Enabled.
- * |[3] |NEVWKIEN |USB No-Event-Wake-Up Interrupt Enable
- * | | |0 = No-Event-Wake-up Interrupt Disabled.
- * | | |1 = No-Event-Wake-up Interrupt Enabled.
- * |[8] |WKEN |Wake-Up Function Enable
- * | | |0 = USB wake-up function Disabled.
- * | | |1 = USB wake-up function Enabled.
- * |[15] |INNAKEN |Active NAK Function And Its Status In IN Token
- * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be
- * | | | updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted.
- * | | |1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event
- * | | | will be asserted, when the device responds NAK after receiving IN token.
- * @var USBD_T::INTSTS
- * Offset: 0x04 USB Interrupt Event Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSIF |BUS Interrupt Status
- * | | |The BUS event means that there is one of the suspense or the resume function in the bus.
- * | | |0 = No BUS event occurred.
- * | | |1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0].
- * |[1] |USBIF |USB Event Interrupt Status
- * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
- * | | |0 = No USB event occurred.
- * | | |1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred.
- * | | |Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]).
- * |[2] |VBDETIF |VBUS Detection Interrupt Status
- * | | |0 = There is not attached/detached event in the USB.
- * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2].
- * |[3] |NEVWKIF |USB No-Event-Wake-Up Interrupt Status
- * | | |0 = No Wake-up event occurred.
- * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3].
- * |[16] |EPEVT0 |Endpoint 0's USB Event Status
- * | | |0 = No event occurred on endpoint 0.
- * | | |1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1].
- * |[17] |EPEVT1 |Endpoint 1's USB Event Status
- * | | |0 = No event occurred on endpoint 1.
- * | | |1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1].
- * |[18] |EPEVT2 |Endpoint 2's USB Event Status
- * | | |0 = No event occurred on endpoint 2.
- * | | |1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1].
- * |[19] |EPEVT3 |Endpoint 3's USB Event Status
- * | | |0 = No event occurred on endpoint 3.
- * | | |1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1].
- * |[20] |EPEVT4 |Endpoint 4's USB Event Status
- * | | |0 = No event occurred on endpoint 4.
- * | | |1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1].
- * |[21] |EPEVT5 |Endpoint 5's USB Event Status
- * | | |0 = No event occurred on endpoint 5.
- * | | |1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1].
- * |[22] |EPEVT6 |Endpoint 6's USB Event Status
- * | | |0 = No event occurred on endpoint 6.
- * | | |1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1].
- * |[23] |EPEVT7 |Endpoint 7's USB Event Status
- * | | |0 = No event occurred on endpoint 7.
- * | | |1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1].
- * |[31] |SETUP |Setup Event Status
- * | | |0 = No Setup event.
- * | | |1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31].
- * @var USBD_T::FADDR
- * Offset: 0x08 USB Device Function Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[6:0] |FADDR |USB Device Function Address
- * @var USBD_T::EPSTS
- * Offset: 0x0C USB Endpoint Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7] |OV |Overrun
- * | | |It indicates that the received data is over the maximum payload number or not.
- * | | |0 = No overrun.
- * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
- * |[10:8] |EPSTS0 |Endpoint 0 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * |[13:11] |EPSTS1 |Endpoint 1 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * |[16:14] |EPSTS2 |Endpoint 2 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * |[19:17] |EPSTS3 |Endpoint 3 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * |[22:20] |EPSTS4 |Endpoint 4 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * |[25:23] |EPSTS5 |Endpoint 5 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * |[28:26] |EPSTS6 |Endpoint 6 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * |[31:29] |EPSTS7 |Endpoint 7 Bus Status
- * | | |These bits are used to indicate the current status of this endpoint
- * | | |000 = In ACK.
- * | | |001 = In NAK.
- * | | |010 = Out Packet Data0 ACK.
- * | | |110 = Out Packet Data1 ACK.
- * | | |011 = Setup ACK.
- * | | |111 = Isochronous transfer end.
- * @var USBD_T::ATTR
- * Offset: 0x10 USB Bus Status and Attribution Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |USBRST |USB Reset Status
- * | | |0 = Bus no reset.
- * | | |1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us.
- * | | |Note: This bit is read only.
- * |[1] |SUSPEND |Suspend Status
- * | | |0 = Bus no suspend.
- * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
- * | | |Note: This bit is read only.
- * |[2] |RESUME |Resume Status
- * | | |0 = No bus resume.
- * | | |1 = Resume from suspend.
- * | | |Note: This bit is read only.
- * |[3] |TOUT |Time-Out Status
- * | | |0 = No time-out.
- * | | |1 = No Bus response more than 18 bits time.
- * | | |Note: This bit is read only.
- * |[4] |PHYEN |PHY Transceiver Function Enable
- * | | |0 = PHY transceiver function Disabled.
- * | | |1 = PHY transceiver function Enabled.
- * |[5] |RWAKEUP |Remote Wake-Up
- * | | |0 = Release the USB bus from K state.
- * | | |1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up.
- * |[7] |USBEN |USB Controller Enable
- * | | |0 = USB Controller Disabled.
- * | | |1 = USB Controller Enabled.
- * |[8] |DPPUEN |Pull-Up Resistor On USB_D+ Enable
- * | | |0 = Pull-up resistor in USB_D+ pin Disabled.
- * | | |1 = Pull-up resistor in USB_D+ pin Enabled.
- * |[9] |PWRDN |Power Down PHY Transceiver, Low Active (M45xD/M45xC Only)
- * | | |0 = Power down related circuits of PHY transceiver.
- * | | |1 = Turn on related circuits of PHY transceiver.
- * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection
- * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
- * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
- * @var USBD_T::VBUSDET
- * Offset: 0x14 USB Device VBUS Detection Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLDET |Device VBUS Detected
- * | | |0 = Controller is not attached into the USB host.
- * | | |1 =Controller is attached into the BUS.
- * @var USBD_T::STBUFSEG
- * Offset: 0x18 Setup Token Buffer Segmentation Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8:3] |STBUFSEG |Setup Token Buffer Segmentation
- * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
- * | | |USB_SRAM address + {STBUFSEG[8:3], 3'b000}
- * | | |Where the USB_SRAM address = USBD_BA+0x100h.
- * | | |Note: It is used for SETUP token only.
- * @var USBD_T::SE0
- * Offset: 0x90 USB Drive SE0 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DRVSE0 |Drive Single Ended Zero In USB Bus
- * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
- * | | |0 = None.
- * | | |1 = Force USB PHY transceiver to drive SE0.
- * @var USBD_T::EP
- * Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register
- * ---------------------------------------------------------------------------------------------------
- */
-
- __IO uint32_t INTEN; /* Offset: 0x00 USB Interrupt Enable Register */
- __IO uint32_t INTSTS; /* Offset: 0x04 USB Interrupt Event Status Register */
- __IO uint32_t FADDR; /* Offset: 0x08 USB Device Function Address Register */
- __I uint32_t EPSTS; /* Offset: 0x0C USB Endpoint Status Register */
- __IO uint32_t ATTR; /* Offset: 0x10 USB Bus Status and Attribution Register */
- __I uint32_t VBUSDET; /* Offset: 0x14 USB Device VBUS Detection Register */
- __IO uint32_t STBUFSEG; /* Offset: 0x18 Setup Token Buffer Segmentation Register */
- __I uint32_t RESERVE0[29];
- __IO uint32_t SE0; /* Offset: 0x90 USB Drive SE0 Control Register */
- __I uint32_t RESERVE1[283];
- USBD_EP_T EP[8]; /* Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register */
-
-} USBD_T;
-
-
-
-/**
- @addtogroup USB_CONST USB Bit Field Definition
- Constant Definitions for USB Controller
-@{ */
-
-#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */
-#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */
-
-#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */
-#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */
-
-#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */
-#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */
-
-#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */
-#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */
-
-#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */
-#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */
-
-#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */
-#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */
-
-#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */
-#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */
-
-#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */
-#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */
-
-#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */
-#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */
-
-#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */
-#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */
-
-#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */
-#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */
-
-#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */
-#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */
-
-#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */
-#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */
-
-#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */
-#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */
-
-#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */
-#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */
-
-#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */
-#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */
-
-#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */
-#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */
-
-#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */
-#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */
-
-#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */
-#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */
-
-#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */
-#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */
-
-#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */
-#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */
-
-#define USBD_EPSTS_EPSTS0_Pos (8) /*!< USBD_T::EPSTS: EPSTS0 Position */
-#define USBD_EPSTS_EPSTS0_Msk (0x7ul << USBD_EPSTS_EPSTS0_Pos) /*!< USBD_T::EPSTS: EPSTS0 Mask */
-
-#define USBD_EPSTS_EPSTS1_Pos (11) /*!< USBD_T::EPSTS: EPSTS1 Position */
-#define USBD_EPSTS_EPSTS1_Msk (0x7ul << USBD_EPSTS_EPSTS1_Pos) /*!< USBD_T::EPSTS: EPSTS1 Mask */
-
-#define USBD_EPSTS_EPSTS2_Pos (14) /*!< USBD_T::EPSTS: EPSTS2 Position */
-#define USBD_EPSTS_EPSTS2_Msk (0x7ul << USBD_EPSTS_EPSTS2_Pos) /*!< USBD_T::EPSTS: EPSTS2 Mask */
-
-#define USBD_EPSTS_EPSTS3_Pos (17) /*!< USBD_T::EPSTS: EPSTS3 Position */
-#define USBD_EPSTS_EPSTS3_Msk (0x7ul << USBD_EPSTS_EPSTS3_Pos) /*!< USBD_T::EPSTS: EPSTS3 Mask */
-
-#define USBD_EPSTS_EPSTS4_Pos (20) /*!< USBD_T::EPSTS: EPSTS4 Position */
-#define USBD_EPSTS_EPSTS4_Msk (0x7ul << USBD_EPSTS_EPSTS4_Pos) /*!< USBD_T::EPSTS: EPSTS4 Mask */
-
-#define USBD_EPSTS_EPSTS5_Pos (23) /*!< USBD_T::EPSTS: EPSTS5 Position */
-#define USBD_EPSTS_EPSTS5_Msk (0x7ul << USBD_EPSTS_EPSTS5_Pos) /*!< USBD_T::EPSTS: EPSTS5 Mask */
-
-#define USBD_EPSTS_EPSTS6_Pos (26) /*!< USBD_T::EPSTS: EPSTS6 Position */
-#define USBD_EPSTS_EPSTS6_Msk (0x7ul << USBD_EPSTS_EPSTS6_Pos) /*!< USBD_T::EPSTS: EPSTS6 Mask */
-
-#define USBD_EPSTS_EPSTS7_Pos (29) /*!< USBD_T::EPSTS: EPSTS7 Position */
-#define USBD_EPSTS_EPSTS7_Msk (0x7ul << USBD_EPSTS_EPSTS7_Pos) /*!< USBD_T::EPSTS: EPSTS7 Mask */
-
-#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */
-#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */
-
-#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */
-#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */
-
-#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */
-#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */
-
-#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */
-#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */
-
-#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */
-#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */
-
-#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */
-#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */
-
-#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */
-#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */
-
-#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */
-#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */
-
-#define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */
-#define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */
-
-#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */
-#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */
-
-#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */
-#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */
-
-#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */
-#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */
-
-#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */
-#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */
-
-#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */
-#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */
-
-#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */
-#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */
-
-#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */
-#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */
-
-#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */
-#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */
-
-#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */
-#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */
-
-#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */
-#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */
-
-#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */
-#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */
-
-#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */
-#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */
-
-#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */
-#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */
-
-/**@}*/ /* USB_CONST */
-/**@}*/ /* end of USB register group */
-
-
-/*---------------------- USB Host Controller -------------------------*/
-/**
- @addtogroup USBH USB Host Controller(USBH)
- Memory Mapped Structure for USBH Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var USBH_T::HcRevision
- * Offset: 0x00 Host Controller Revision Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |REV |Revision Number
- * | | |Indicates the Open HCI Specification revision number implemented by the Hardware.
- * | | |Host Controller supports 1.1 specification.
- * | | |(X.Y = XYh).
- * @var USBH_T::HcControl
- * Offset: 0x04 Host Controller Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |CBSR |Control Bulk Service Ratio
- * | | |This specifies the service ratio between Control and Bulk EDs.
- * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
- * | | |The internal count will be retained when crossing the frame boundary.
- * | | |In case of reset, HCD is responsible for restoring this.
- * | | |Value.
- * | | |00 = Number of Control EDs over Bulk EDs served is 1:1.
- * | | |01 = Number of Control EDs over Bulk EDs served is 2:1.
- * | | |10 = Number of Control EDs over Bulk EDs served is 3:1.
- * | | |11 = Number of Control EDs over Bulk EDs served is 4:1.
- * |[2] |PLE |Periodic List Enable Bit
- * | | |When set, this bit enables processing of the Periodic (interrupt and Isochronous) list.
- * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
- * | | |0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame).
- * | | |1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame.
- * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
- * |[3] |IE |Isochronous List Enable Bit
- * | | |Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list.
- * | | |Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
- * | | |0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame).
- * | | |1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too.
- * |[4] |CLE |Control List Enable Bit
- * | | |0 = Disable processing of the Control list after next SOF (Start-Of-Frame).
- * | | |1 = Enable processing of the Control list in the next frame.
- * |[5] |BLE |Bulk List Enable Bit
- * | | |0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame).
- * | | |1 = Enable processing of the Bulk list in the next frame.
- * |[7:6] |HCFS |Host Controller Functional State
- * | | |This field sets the Host Controller state.
- * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
- * | | |States are:
- * | | |00 = USBSUSPEND.
- * | | |01 = USBRESUME.
- * | | |10 = USBOPERATIONAL.
- * | | |11 = USBRESET.
- * @var USBH_T::HcCommandStatus
- * Offset: 0x08 Host Controller CMD Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HCR |Host Controller Reset
- * | | |This bit is set to initiate the software reset of Host Controller.
- * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
- * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
- * | | |0 = Host Controller is not in software reset state.
- * | | |1 = Host Controller is in software reset state.
- * |[1] |CLF |Control List Filled
- * | | |Set high to indicate there is an active TD on the Control List.
- * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
- * | | |0 = No active TD found or Host Controller begins to process the head of the Control list.
- * | | |1 = An active TD added or found on the Control list.
- * |[2] |BLF |Bulk List Filled
- * | | |Set high to indicate there is an active TD on the Bulk list.
- * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
- * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
- * | | |1 = An active TD added or found on the Bulk list.
- * |[17:16] |SOC |Schedule Overrun Count
- * | | |These bits are incremented on each scheduling overrun error.
- * | | |It is initialized to 00b and wraps around at 11b.
- * | | |This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set.
- * @var USBH_T::HcInterruptStatus
- * Offset: 0x0C Host Controller Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SO |Scheduling Overrun
- * | | |Set when the List Processor determines a Schedule Overrun has occurred.
- * | | |0 = Schedule Overrun didn't occur.
- * | | |1 = Schedule Overrun has occurred.
- * |[1] |WDH |Write Back Done Head
- * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
- * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
- * | | |0 =.Host Controller didn't update HccaDoneHead.
- * | | |1 =.Host Controller has written HcDoneHead to HccaDoneHead.
- * |[2] |SF |Start Of Frame
- * | | |Set when the Frame Management functional block signals a 'Start of Frame' event.
- * | | |Host Control generates a SOF token at the same time.
- * | | |0 =.Not the start of a frame.
- * | | |1 =.Indicate the start of a frame and Host Controller generates a SOF token.
- * |[3] |RD |Resume Detected
- * | | |Set when Host Controller detects resume signaling on a downstream port.
- * | | |0 = No resume signaling detected on a downstream port.
- * | | |1 = Resume signaling detected on a downstream port.
- * |[5] |FNO |Frame Number Overflow
- * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
- * | | |0 = The bit 15 of Frame Number didn't change.
- * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
- * |[6] |RHSC |Root Hub Status Change
- * | | |This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed.
- * | | |0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change.
- * | | |1 = The content of HcRhSts or the content of HcRhPrt1 register has changed.
- * @var USBH_T::HcInterruptEnable
- * Offset: 0x10 Host Controller Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SO |Scheduling Overrun Enable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable interrupt generation due to SO (HcIntSts[0]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
- * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
- * |[1] |WDH |Write Back Done Head Enable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable interrupt generation due to WDH (HcIntSts[1]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
- * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
- * |[2] |SF |Start Of Frame Enable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable interrupt generation due to SF (HcIntSts[2]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
- * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
- * |[3] |RD |Resume Detected Enable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable interrupt generation due to RD (HcIntSts[3]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
- * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
- * |[5] |FNO |Frame Number Overflow Enable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable interrupt generation due to FNO (HcIntSts[5]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
- * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
- * |[6] |RHSC |Root Hub Status Change Enable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
- * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
- * |[31] |MIE |Master Interrupt Enable Bit
- * | | |This bit is a global interrupt enable.
- * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
- * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
- * @var USBH_T::HcInterruptDisable
- * Offset: 0x14 Host Controller Interrupt Disable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SO |Scheduling Overrun Disable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Disable interrupt generation due to SO (HcIntSts[0]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
- * | | |1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
- * |[1] |WDH |Write Back Done Head Disable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Disable interrupt generation due to WDH (HcIntSts[1]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
- * | | |1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
- * |[2] |SF |Start Of Frame Disable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Disable interrupt generation due to SF (HcIntSts[2]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
- * | | |1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
- * |[3] |RD |Resume Detected Disable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Disable interrupt generation due to RD (HcIntSts[3]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
- * | | |1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
- * |[5] |FNO |Frame Number Overflow Disable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Disable interrupt generation due to FNO (HcIntSts[5]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
- * | | |1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
- * |[6] |RHSC |Root Hub Status Change Disable Bit
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]).
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
- * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
- * |[31] |MIE |Master Interrupt Disable Bit
- * | | |Global interrupt disable. Writing '1' to disable all interrupts.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
- * | | |Read Operation:
- * | | |0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
- * | | |1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.
- * @var USBH_T::HcHCCA
- * Offset: 0x18 Host Controller Communication Area Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:8] |HCCA |Host Controller Communication Area
- * | | |Pointer to indicate base address of the Host Controller Communication Area (HCCA).
- * @var USBH_T::HcPeriodCurrentED
- * Offset: 0x1C Host Controller Period Current ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:4] |PCED |Periodic Current ED
- * | | |Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.
- * @var USBH_T::HcControlHeadED
- * Offset: 0x20 Host Controller Control Head ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:4] |CHED |Control Head ED
- * | | |Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.
- * @var USBH_T::HcControlCurrentED
- * Offset: 0x24 Host Controller Control Current ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:4] |CCED |Control Current Head ED
- * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
- * @var USBH_T::HcBulkHeadED
- * Offset: 0x28 Host Controller Bulk Head ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:4] |BHED |Bulk Head ED
- * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
- * @var USBH_T::HcBulkCurrentED
- * Offset: 0x2C Host Controller Bulk Current ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:4] |BCED |Bulk Current Head ED
- * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list.
- * @var USBH_T::HcDoneHead
- * Offset: 0x30 Host Controller Done Head Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:4] |DH |Done Head
- * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
- * @var USBH_T::HcFmInterval
- * Offset: 0x34 Host Controller Frame Interval Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[13:0] |FI |Frame Interval
- * | | |This field specifies the length of a frame as (bit times - 1).
- * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
- * |[30:16] |FSMPS |FS Largest Data Packet
- * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
- * |[31] |FIT |Frame Interval Toggle
- * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]).
- * | | |0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]).
- * | | |1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]).
- * @var USBH_T::HcFmRemaining
- * Offset: 0x38 Host Controller Frame Remaining Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[13:0] |FR |Frame Remaining
- * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
- * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
- * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
- * |[31] |FRT |Frame Remaining Toggle
- * | | |This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0.
- * @var USBH_T::HcFmNumber
- * Offset: 0x3C Host Controller Frame Number Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[15:0] |FN |Frame Number
- * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRem[13:0]).
- * | | |The count rolls over from 'FFFFh' to '0h.'.
- * @var USBH_T::HcPeriodicStart
- * Offset: 0x40 Host Controller Periodic Start Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[13:0] |PS |Periodic Start
- * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
- * @var USBH_T::HcLSThreshold
- * Offset: 0x44 Host Controller Low-speed Threshold Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[11:0] |LST |Low-Speed Threshold
- * | | |This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction.
- * | | |The transaction is started only if FR (HcFmRem[13:0]) >= this field.
- * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
- * @var USBH_T::HcRhDescriptorA
- * Offset: 0x48 Host Controller Root Hub Descriptor A Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[7:0] |NDP |Number Downstream Ports
- * | | |USB host control supports two downstream ports and only one port is available in this series of chip.
- * |[8] |PSM |Power Switching Mode
- * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled.
- * | | |0 = Global Switching.
- * | | |1 = Individual Switching.
- * |[11] |OCPM |Over Current Protection Mode
- * | | |This bit describes how the over current status for the Root Hub ports reported.
- * | | |This bit is only valid when NOCP (HcRhDeA[12]) is cleared.
- * | | |0 = Global Over current.
- * | | |1 = Individual Over current.
- * |[12] |NOCP |No Over Current Protection
- * | | |This bit describes how the over current status for the Root Hub ports reported.
- * | | |0 = Over current status is reported.
- * | | |1 = Over current status is not reported.
- * @var USBH_T::HcRhDescriptorB
- * Offset: 0x4C Host Controller Root Hub Descriptor B Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:16] |PPCM |Port Power Control Mask
- * | | |Global power switching.
- * | | |This field is only valid if PowerSwitchingMode is set (individual port switching).
- * | | |When set, the port only responds to individual port power switching commands (Set/ClearPortPower).
- * | | |When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
- * | | |0 = Port power controlled by global power switching.
- * | | |1 = Port power controlled by port power switching.
- * | | |Note: PPCM[15:2] and PPCM[0] are reserved.
- * @var USBH_T::HcRhStatus
- * Offset: 0x50 Host Controller Root Hub Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |LPS |Clear Global Power
- * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power.
- * | | |This bit always read as zero.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Clear global power.
- * |[1] |OCI |Over Current Indicator
- * | | |This bit reflects the state of the over current status pin.
- * | | |This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
- * | | |0 = No over current condition.
- * | | |1 = Over current condition.
- * |[15] |DRWE |Device Remote Wakeup Enable Bit
- * | | |This bit controls if port's Connect Status Change as a remote wake-up event.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Enable Connect Status Change as a remote wake-up event.
- * | | |Read Operation:
- * | | |0 = Connect Status Change as a remote wake-up event disabled.
- * | | |1 = Connect Status Change as a remote wake-up event enabled.
- * |[16] |LPSC |Set Global Power
- * | | |In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports.
- * | | |This bit always read as zero.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Set global power.
- * |[17] |OCIC |Over Current Indicator Change
- * | | |This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]).
- * | | |Write 1 to clear this bit to zero.
- * | | |0 = OCI (HcRhSts[1]) didn't change.
- * | | |1 = OCI (HcRhSts[1]) change.
- * |[31] |CRWE |Clear Remote Wake-up Enable Bit
- * | | |This bit is use to clear DRWE (HcRhSts[15]).
- * | | |This bit always read as zero.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Clear DRWE (HcRhSts[15]).
- * @var USBH_T::HcRhPortStatus
- * Offset: 0x54 Host Controller Root Hub Port Status [1]
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CCS |CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Clear port enable.
- * | | |Read Operation:
- * | | |0 = No device connected.
- * | | |1 = Device connected.
- * |[1] |PES |Port Enable Status
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Set port enable.
- * | | |Read Operation:
- * | | |0 = Port Disabled.
- * | | |1 = Port Enabled.
- * |[2] |PSS |Port Suspend Status
- * | | |This bit indicates the port is suspended
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Set port suspend.
- * | | |Read Operation:
- * | | |0 = Port is not suspended.
- * | | |1 = Port is selectively suspended.
- * |[3] |POCI |Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
- * | | |This bit reflects the state of the over current status pin dedicated to this port.
- * | | |This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set.
- * | | |This bit is also used to initiate the selective result sequence for the port.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Clear port suspend.
- * | | |Read Operation:
- * | | |0 = No over current condition.
- * | | |1 = Over current condition.
- * |[4] |PRS |Port Reset Status
- * | | |This bit reflects the reset state of the port.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Set port reset.
- * | | |Read Operation
- * | | |0 = Port reset signal is not active.
- * | | |1 = Port reset signal is active.
- * |[8] |PPS |Port Power Status
- * | | |This bit reflects the power state of the port regardless of the power switching mode.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Port Power Enabled.
- * | | |Read Operation:
- * | | |0 = Port power is Disabled.
- * | | |1 = Port power is Enabled.
- * |[9] |LSDA |Low Speed Device Attached (Read) Or Clear Port Power (Write)
- * | | |This bit defines the speed (and bud idle) of the attached device.
- * | | |It is only valid when CCS (HcRhPrt1[0]) is set.
- * | | |This bit is also used to clear port power.
- * | | |Write Operation:
- * | | |0 = No effect.
- * | | |1 = Clear PPS (HcRhPrt1[8]).
- * | | |Read Operation:
- * | | |0 = Full Speed device.
- * | | |1 = Low-speed device.
- * |[16] |CSC |Connect Status Change
- * | | |This bit indicates connect or disconnect event has been detected (CCS
- * | | |(HcRhPrt1[0]) changed).
- * | | |Write 1 to clear this bit to zero.
- * | | |0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change).
- * | | |1 = Hardware detection of connect/disconnect event (CCS
- * | | |(HcRhPrt1[0]) changed).
- * |[17] |PESC |Port Enable Status Change
- * | | |This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event.
- * | | |Write 1 to clear this bit to zero.
- * | | |0 = PES (HcRhPrt1[1]) didn't change.
- * | | |1 = PES (HcRhPrt1[1]) changed.
- * |[18] |PSSC |Port Suspend Status Change
- * | | |This bit indicates the completion of the selective resume sequence for the port.
- * | | |Write 1 to clear this bit to zero.
- * | | |0 = Port resume is not completed.
- * | | |1 = Port resume completed.
- * |[19] |OCIC |Port Over Current Indicator Change
- * | | |This bit is set when POCI (HcRhPrt1[3]) changes.
- * | | |Write 1 to clear this bit to zero.
- * | | |0 = POCI (HcRhPrt1[3]) didn't change.
- * | | |1 = POCI (HcRhPrt1[3]) changes.
- * |[20] |PRSC |Port Reset Status Change
- * | | |This bit indicates that the port reset signal has completed.
- * | | |Write 1 to clear this bit to zero.
- * | | |0 = Port reset is not complete.
- * | | |1 = Port reset is complete.
- * @var USBH_T::HcPhyControl
- * Offset: 0x200 USB Host Controller PHY Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[27] |STBYEN |USB Transceiver Standby Enable Bit
- * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
- * | | |0 = The USB transceiver would never enter the standby mode.
- * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
- * @var USBH_T::HcMiscControl
- * Offset: 0x204 USB Host Controller Miscellaneous Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |ABORT |AHB Bus ERROR Response
- * | | |This bit indicates there is an ERROR response received in AHB bus.
- * | | |0 = No ERROR response received.
- * | | |1 = ERROR response received.
- * |[3] |OCAL |Over Current Active Low
- * | | |This bit controls the polarity of over current flag from external power IC.
- * | | |0 = Over current flag is high active.
- * | | |1 = Over current flag is low active.
- * |[16] |DPRT1 |Disable Port 1
- * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
- * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
- * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
- * | | |0 = The connection between USB host controller and transceiver of port 1 is enabled.
- * | | |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
- */
-
- __I uint32_t HcRevision; /* Offset: 0x00 Host Controller Revision Register */
- __IO uint32_t HcControl; /* Offset: 0x04 Host Controller Control Register */
- __IO uint32_t HcCommandStatus; /* Offset: 0x08 Host Controller CMD Status Register */
- __IO uint32_t HcInterruptStatus; /* Offset: 0x0C Host Controller Interrupt Status Register */
- __IO uint32_t HcInterruptEnable; /* Offset: 0x10 Host Controller Interrupt Enable Register */
- __IO uint32_t HcInterruptDisable; /* Offset: 0x14 Host Controller Interrupt Disable Register */
- __IO uint32_t HcHCCA; /* Offset: 0x18 Host Controller Communication Area Register */
- __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C Host Controller Period Current ED Register */
- __IO uint32_t HcControlHeadED; /* Offset: 0x20 Host Controller Control Head ED Register */
- __IO uint32_t HcControlCurrentED; /* Offset: 0x24 Host Controller Control Current ED Register */
- __IO uint32_t HcBulkHeadED; /* Offset: 0x28 Host Controller Bulk Head ED Register */
- __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C Host Controller Bulk Current ED Register */
- __IO uint32_t HcDoneHead; /* Offset: 0x30 Host Controller Done Head Register */
- __IO uint32_t HcFmInterval; /* Offset: 0x34 Host Controller Frame Interval Register */
- __I uint32_t HcFmRemaining; /* Offset: 0x38 Host Controller Frame Remaining Register */
- __I uint32_t HcFmNumber; /* Offset: 0x3C Host Controller Frame Number Register */
- __IO uint32_t HcPeriodicStart; /* Offset: 0x40 Host Controller Periodic Start Register */
- __IO uint32_t HcLSThreshold; /* Offset: 0x44 Host Controller Low-speed Threshold Register */
- __IO uint32_t HcRhDescriptorA; /* Offset: 0x48 Host Controller Root Hub Descriptor A Register */
- __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C Host Controller Root Hub Descriptor B Register */
- __IO uint32_t HcRhStatus; /* Offset: 0x50 Host Controller Root Hub Status Register */
- __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54 Host Controller Root Hub Port Status [1] */
- __I uint32_t RESERVE0[105];
- __IO uint32_t HcPhyControl; /* Offset: 0x200 USB Host Controller PHY Control Register */
- __IO uint32_t HcMiscControl; /* Offset: 0x204 USB Host Controller Miscellaneous Control Register */
-
-} USBH_T;
-
-
-
-
-/**
- @addtogroup USBH_CONST USBH Bit Field Definition
- Constant Definitions for USBH Controller
-@{ */
-
-#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */
-#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */
-
-#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */
-#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */
-
-#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: CBSR Position */
-#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: CBSR Mask */
-
-#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */
-#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */
-
-#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */
-#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */
-
-#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */
-#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */
-
-#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */
-#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */
-
-#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */
-#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */
-
-#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */
-#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */
-
-#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */
-#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */
-
-#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */
-#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */
-
-#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */
-#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */
-
-#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position */
-#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */
-
-#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */
-#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */
-
-#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */
-#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */
-
-#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position */
-#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */
-
-#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position */
-#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */
-
-#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */
-#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */
-
-#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position */
-#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */
-
-#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */
-#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */
-
-#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */
-#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */
-
-#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position */
-#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */
-
-#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position */
-#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */
-
-#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position */
-#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */
-
-#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position */
-#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */
-
-#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position */
-#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */
-
-#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position */
-#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */
-
-#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position */
-#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */
-
-#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position */
-#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */
-
-#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position */
-#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */
-
-#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position */
-#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */
-
-#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */
-#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */
-
-#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position */
-#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */
-
-#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */
-#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */
-
-#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position */
-#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */
-
-#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */
-#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */
-
-#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */
-#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */
-
-#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */
-#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */
-
-#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */
-#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */
-
-#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */
-#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */
-
-#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */
-#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */
-
-#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */
-#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */
-
-#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */
-#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */
-
-#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */
-#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */
-
-#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */
-#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */
-
-#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */
-#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */
-
-#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */
-#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */
-
-#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */
-#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */
-
-#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */
-#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */
-
-#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */
-#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */
-
-#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */
-#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */
-
-#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */
-#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */
-
-#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */
-#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */
-
-#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */
-#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */
-
-#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */
-#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */
-
-#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */
-#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */
-
-#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
-#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
-
-#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */
-#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */
-
-#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */
-#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */
-
-#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */
-#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */
-
-#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */
-#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */
-
-#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */
-#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */
-
-#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */
-#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */
-
-#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */
-#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */
-
-#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */
-#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */
-
-#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */
-#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */
-
-#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */
-#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */
-
-#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */
-#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */
-
-#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */
-#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */
-
-#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
-#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
-
-#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */
-#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */
-
-#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */
-#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */
-
-#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */
-#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */
-
-/**@}*/ /* USBH_CONST */
-/**@}*/ /* end of USBH register group */
-
-
-/*---------------------- Watch Dog Timer Controller -------------------------*/
-/**
- @addtogroup WDT Watch Dog Timer Controller(WDT)
- Memory Mapped Structure for WDT Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var WDT_T::CTL
- * Offset: 0x00 WDT Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RSTCNT |Reset WDT Up Counter (Write Protect)
- * | | |0 = No effect.
- * | | |1 = Reset the internal 18-bit WDT up counter value.
- * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
- * | | |Note2: This bit will be automatically cleared by hardware.
- * |[1] |RSTEN |WDT Time-Out Reset Enable Control (Write Protect)
- * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
- * | | |0 = WDT time-out reset function Disabled.
- * | | |1 = WDT time-out reset function Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[2] |RSTF |WDT Time-Out Reset Flag
- * | | |This bit indicates the system has been reset by WDT time-out reset or not.
- * | | |0 = WDT time-out reset did not occur.
- * | | |1 = WDT time-out reset occurred.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[3] |IF |WDT Time-Out Interrupt Flag
- * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
- * | | |0 = WDT time-out interrupt did not occur.
- * | | |1 = WDT time-out interrupt occurred.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[4] |WKEN |WDT Time-Out Wake-Up Function Control (Write Protect)
- * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
- * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
- * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
- * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
- * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
- * |[5] |WKF |WDT Time-Out Wake-Up Flag
- * | | |This bit indicates the interrupt wake-up flag status of WDT
- * | | |0 = WDT does not cause chip wake-up.
- * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
- * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
- * | | |Note2: This bit is cleared by writing 1 to it.
- * |[6] |INTEN |WDT Time-Out Interrupt Enable Control (Write Protect)
- * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
- * | | |0 = WDT time-out interrupt Disabled.
- * | | |1 = WDT time-out interrupt Enabled.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[7] |WDTEN |WDT Enable Control (Write Protect)
- * | | |0 = WDT Disabled (This action will reset the internal up counter value).
- * | | |1 = WDT Enabled.
- * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
- * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
- * |[10:8] |TOUTSEL |WDT Time-Out Interval Selection (Write Protect)
- * | | |These three bits select the time-out interval period for the WDT.
- * | | |000 = (2^4)*TWDT.
- * | | |001 = (2^6)*TWDT.
- * | | |010 = (2^8)*TWDT.
- * | | |011 = (2^10)*TWDT.
- * | | |100 = (2^12)*TWDT.
- * | | |101 = (2^14)*TWDT.
- * | | |110 = (2^16)*TWDT.
- * | | |111 = (2^18)*TWDT.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
- * | | |0 = ICE debug mode acknowledgement affects WDT counting.
- * | | |WDT up counter will be held while CPU is held by ICE.
- * | | |1 = ICE debug mode acknowledgement Disabled.
- * | | |WDT up counter will keep going no matter CPU is held by ICE or not.
- * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
- * @var WDT_T::ALTCTL
- * Offset: 0x04 WDT Alternative Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect)
- * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
- * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
- * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
- * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
- * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
- * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
- * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
- * | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
- */
-
- __IO uint32_t CTL; /* Offset: 0x00 WDT Control Register */
- __IO uint32_t ALTCTL; /* Offset: 0x04 WDT Alternative Control Register */
-
-} WDT_T;
-
-
-
-/**
- @addtogroup WDT_CONST WDT Bit Field Definition
- Constant Definitions for WDT Controller
-@{ */
-
-#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT_T::CTL: RSTCNT Position */
-#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT_T::CTL: RSTCNT Mask */
-
-#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
-#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
-
-#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
-#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
-
-#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
-#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
-
-#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
-#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
-
-#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
-#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
-
-#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
-#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
-
-#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
-#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
-
-#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
-#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
-
-#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
-#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
-
-#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
-#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
-
-/**@}*/ /* WDT_CONST */
-/**@}*/ /* end of WDT register group */
-
-
-/*---------------------- Window Watchdog Timer -------------------------*/
-/**
- @addtogroup WWDT Window Watchdog Timer(WWDT)
- Memory Mapped Structure for WWDT Controller
-@{ */
-
-
-typedef struct
-{
-
-
-
-
-/**
- * @var WWDT_T::RLDCNT
- * Offset: 0x00 WWDT Reload Counter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[31:0] |WWDT_RLDCNT|WWDT Reload Counter Register
- * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
- * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
- * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.
- * @var WWDT_T::CTL
- * Offset: 0x04 WWDT Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WWDTEN |WWDT Enable Control Bit
- * | | |Set this bit to enable WWDT counter counting.
- * | | |0 = WWDT counter is stopped.
- * | | |1 = WWDT counter is starting counting.
- * |[1] |INTEN |WWDT Interrupt Enable Control Bit
- * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
- * | | |0 = WWDT counter compare match interrupt Disabled.
- * | | |1 = WWDT counter compare match interrupt Enabled.
- * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
- * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
- * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
- * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
- * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
- * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
- * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
- * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
- * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
- * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
- * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
- * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
- * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
- * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
- * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
- * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
- * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
- * |[21:16] |CMPDAT |WWDT Window Compare Register
- * | | |Set this register to adjust the valid reload window.
- * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
- * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
- * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
- * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
- * | | |WWDT down counter will be held while CPU is held by ICE.
- * | | |1 = ICE debug mode acknowledgement Disabled.
- * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
- * @var WWDT_T::STATUS
- * Offset: 0x08 WWDT Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
- * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
- * | | |0 = No effect.
- * | | |1 = WWDT counter value matches CMPDAT.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[1] |WWDTRF |WWDT Timer-Out Reset Flag
- * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
- * | | |0 = WWDT time-out reset did not occur.
- * | | |1 = WWDT time-out reset occurred.
- * | | |Note: This bit is cleared by writing 1 to it.
- * @var WWDT_T::CNT
- * Offset: 0x0C WWDT Counter Value Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[5:0] |CNTDAT |WWDT Counter Value
- * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
- */
-
- __O uint32_t RLDCNT; /* Offset: 0x00 WWDT Reload Counter Register */
- __IO uint32_t CTL; /* Offset: 0x04 WWDT Control Register */
- __IO uint32_t STATUS; /* Offset: 0x08 WWDT Status Register */
- __I uint32_t CNT; /* Offset: 0x0C WWDT Counter Value Register */
-
-} WWDT_T;
-
-
-
-/**
- @addtogroup WWDT_CONST WWDT Bit Field Definition
- Constant Definitions for WWDT Controller
-@{ */
-
-#define WWDT_RLDCNT_WWDT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Position */
-#define WWDT_RLDCNT_WWDT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: WWDT_RLDCNT Mask */
-
-#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
-#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
-
-#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
-#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
-
-#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
-#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
-
-#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
-#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
-
-#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
-#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
-
-#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
-#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
-
-#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
-#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
-
-#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
-#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
-
-/**@}*/ /* WWDT_CONST */
-/**@}*/ /* end of WWDT register group */
-
-
-/**@}*/ /* end of REGISTER group */
-
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/** @addtogroup MemoryMap Memory Mapping
- @{
-*/
-
-/* Peripheral and SRAM base address */
-#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
-#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
-
-
-/* Peripheral memory map */
-#define AHBPERIPH_BASE PERIPH_BASE
-#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
-
-/*!< AHB peripherals */
-#define GCR_BASE (AHBPERIPH_BASE + 0x00000)
-#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
-#define INT_BASE (AHBPERIPH_BASE + 0x00300)
-#define GPIO_BASE (AHBPERIPH_BASE + 0x04000)
-#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
-#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
-#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
-#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
-#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
-#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
-#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
-#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
-#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
-#define USBH_BASE (AHBPERIPH_BASE + 0x09000)
-#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
-#define EBI_BASE (AHBPERIPH_BASE + 0x10000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x31000)
-
-/*!< APB0 peripherals */
-#define WDT_BASE (APBPERIPH_BASE + 0x00000)
-#define WWDT_BASE (APBPERIPH_BASE + 0x00100)
-#define TMR01_BASE (APBPERIPH_BASE + 0x10000)
-#define PWM0_BASE (APBPERIPH_BASE + 0x18000)
-#define SPI0_BASE (APBPERIPH_BASE + 0x20000)
-#define SPI2_BASE (APBPERIPH_BASE + 0x22000)
-#define UART0_BASE (APBPERIPH_BASE + 0x30000)
-#define UART2_BASE (APBPERIPH_BASE + 0x32000)
-#define I2C0_BASE (APBPERIPH_BASE + 0x40000)
-#define SC0_BASE (APBPERIPH_BASE + 0x50000)
-#define CAN0_BASE (APBPERIPH_BASE + 0x60000)
-#define USBD_BASE (APBPERIPH_BASE + 0x80000)
-#define TK_BASE (APBPERIPH_BASE + 0xA2000)
-
-/*!< APB1 peripherals */
-#define RTC_BASE (APBPERIPH_BASE + 0x01000)
-#define EADC0_BASE (APBPERIPH_BASE + 0x03000)
-#define ACMP01_BASE (APBPERIPH_BASE + 0x05000)
-#define DAC_BASE (APBPERIPH_BASE + 0x07000)
-#define OTG_BASE (APBPERIPH_BASE + 0x0D000)
-#define TMR23_BASE (APBPERIPH_BASE + 0x11000)
-#define PWM1_BASE (APBPERIPH_BASE + 0x19000)
-#define SPI1_BASE (APBPERIPH_BASE + 0x21000)
-#define UART1_BASE (APBPERIPH_BASE + 0x31000)
-#define UART3_BASE (APBPERIPH_BASE + 0x33000)
-#define I2C1_BASE (APBPERIPH_BASE + 0x41000)
-/*@}*/ /* end of group MemoryMap */
-
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-/** @addtogroup PeripheralDecl Peripheral Declaration
- @{
-*/
-
-
-#define SYS ((SYS_T *) GCR_BASE)
-#define SYSINT ((SYS_INT_T *) INT_BASE)
-#define CLK ((CLK_T *) CLK_BASE)
-#define PA ((GPIO_T *) GPIOA_BASE)
-#define PB ((GPIO_T *) GPIOB_BASE)
-#define PC ((GPIO_T *) GPIOC_BASE)
-#define PD ((GPIO_T *) GPIOD_BASE)
-#define PE ((GPIO_T *) GPIOE_BASE)
-#define PF ((GPIO_T *) GPIOF_BASE)
-#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
-#define PDMA ((PDMA_T *) PDMA_BASE)
-#define USBH ((USBH_T *) USBH_BASE)
-#define FMC ((FMC_T *) FMC_BASE)
-#define EBI ((EBI_T *) EBI_BASE)
-#define CRC ((CRC_T *) CRC_BASE)
-
-#define WDT ((WDT_T *) WDT_BASE)
-#define WWDT ((WWDT_T *) WWDT_BASE)
-#define RTC ((RTC_T *) RTC_BASE)
-#define EADC ((EADC_T *) EADC0_BASE)
-#define ACMP01 ((ACMP_T *) ACMP01_BASE)
-
-#define USBD ((USBD_T *) USBD_BASE)
-#define OTG ((OTG_T *) OTG_BASE)
-#define TIMER0 ((TIMER_T *) TMR01_BASE)
-#define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20))
-#define TIMER2 ((TIMER_T *) TMR23_BASE)
-#define TIMER3 ((TIMER_T *) (TMR23_BASE+ 0x20))
-#define PWM0 ((PWM_T *) PWM0_BASE)
-#define PWM1 ((PWM_T *) PWM1_BASE)
-#define DAC ((DAC_T *) DAC_BASE)
-#define SPI0 ((SPI_T *) SPI0_BASE)
-#define SPI1 ((SPI_T *) SPI1_BASE)
-#define SPI2 ((SPI_T *) SPI2_BASE)
-#define UART0 ((UART_T *) UART0_BASE)
-#define UART1 ((UART_T *) UART1_BASE)
-#define UART2 ((UART_T *) UART2_BASE)
-#define UART3 ((UART_T *) UART3_BASE)
-#define I2C0 ((I2C_T *) I2C0_BASE)
-#define I2C1 ((I2C_T *) I2C1_BASE)
-#define SC0 ((SC_T *) SC0_BASE)
-#define CAN0 ((CAN_T *) CAN0_BASE)
-#define TK ((TK_T *) TK_BASE)
-
-/* One Bit Mask Definitions */
-#define BIT0 0x00000001
-#define BIT1 0x00000002
-#define BIT2 0x00000004
-#define BIT3 0x00000008
-#define BIT4 0x00000010
-#define BIT5 0x00000020
-#define BIT6 0x00000040
-#define BIT7 0x00000080
-#define BIT8 0x00000100
-#define BIT9 0x00000200
-#define BIT10 0x00000400
-#define BIT11 0x00000800
-#define BIT12 0x00001000
-#define BIT13 0x00002000
-#define BIT14 0x00004000
-#define BIT15 0x00008000
-#define BIT16 0x00010000
-#define BIT17 0x00020000
-#define BIT18 0x00040000
-#define BIT19 0x00080000
-#define BIT20 0x00100000
-#define BIT21 0x00200000
-#define BIT22 0x00400000
-#define BIT23 0x00800000
-#define BIT24 0x01000000
-#define BIT25 0x02000000
-#define BIT26 0x04000000
-#define BIT27 0x08000000
-#define BIT28 0x10000000
-#define BIT29 0x20000000
-#define BIT30 0x40000000
-#define BIT31 0x80000000
-
-/* Byte Mask Definitions */
-#define BYTE0_Msk (0x000000FF)
-#define BYTE1_Msk (0x0000FF00)
-#define BYTE2_Msk (0x00FF0000)
-#define BYTE3_Msk (0xFF000000)
-
-#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
-#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
-#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
-#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
-
-#ifndef TRUE
-# define TRUE 1
-#endif
-#ifndef FALSE
-# define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-#include "m451_sys.h"
-#include "m451_clk.h"
-#include "m451_gpio.h"
-#include "m451_i2c.h"
-#include "m451_crc.h"
-#include "m451_ebi.h"
-#include "m451_rtc.h"
-#include "m451_timer.h"
-#include "m451_wdt.h"
-#include "m451_wwdt.h"
-#include "m451_spi.h"
-#include "m451_sc.h"
-#include "m451_scuart.h"
-#include "m451_acmp.h"
-#include "m451_eadc.h"
-#include "m451_dac.h"
-#include "m451_can.h"
-#include "m451_usbd.h"
-#include "m451_fmc.h"
-#include "m451_uart.h"
-#include "m451_pwm.h"
-#include "m451_pdma.h"
-#include "m451_tk.h"
-#include "m451_otg.h"
-
-typedef volatile unsigned char vu8;
-typedef volatile unsigned long vu32;
-typedef volatile unsigned short vu16;
-#define M8(adr) (*((vu8 *) (adr)))
-#define M16(adr) (*((vu16 *) (adr)))
-#define M32(adr) (*((vu32 *) (adr)))
-
-#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
-#define inpw(port) (*((volatile unsigned int *)(port)))
-#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
-#define inpb(port) (*((volatile unsigned char *)(port)))
-#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
-#define inps(port) (*((volatile unsigned short *)(port)))
-
-#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
-#define inp32(port) (*((volatile unsigned int *)(port)))
-#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
-#define inp8(port) (*((volatile unsigned char *)(port)))
-#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
-#define inp16(port) (*((volatile unsigned short *)(port)))
-
-/*@}*/ /* end of group PeripheralDecl */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __M451SERIES_H__ */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
-
-
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_acmp.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,84 +0,0 @@
-/**************************************************************************//**
- * @file acmp.c
- * @version V3.00
- * $Revision: 4 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series Analog Comparator(ACMP) driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup ACMP_Driver ACMP Driver
- @{
-*/
-
-
-/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
- @{
-*/
-
-
-/**
- * @brief Configure the specified ACMP module
- *
- * @param[in] Acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum Comparator number.
- * @param[in] u32NegSrc Comparator negative input selection. Including:
- * - \ref ACMP_CTL_NEGSEL_PIN
- * - \ref ACMP_CTL_NEGSEL_CRV
- * - \ref ACMP_CTL_NEGSEL_VBG
- * - \ref ACMP_CTL_NEGSEL_DAC
- * @param[in] u32HysteresisEn The hysteresis function option. Including:
- * - \ref ACMP_CTL_HYSTERESIS_ENABLE
- * - \ref ACMP_CTL_HYSTERESIS_DISABLE
- *
- * @return None
- *
- * @details Configure hysteresis function, select the source of negative input and enable analog comparator.
- */
-void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
-{
- Acmp->CTL[u32ChNum] = (Acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CTL_ACMPEN_Msk);
-}
-
-/**
- * @brief Close analog comparator
- *
- * @param[in] Acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum Comparator number.
- *
- * @return None
- *
- * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
- */
-void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
-{
- Acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
-}
-
-
-
-/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group ACMP_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_acmp.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,333 +0,0 @@
-/**************************************************************************//**
- * @file ACMP.h
- * @version V0.10
- * $Revision: 10 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 Series ACMP Driver Header File
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __ACMP_H__
-#define __ACMP_H__
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Include related headers */
-/*---------------------------------------------------------------------------------------------------------*/
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup ACMP_Driver ACMP Driver
- @{
-*/
-
-
-/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
- @{
-*/
-
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* ACMP_CTL constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define ACMP_CTL_FILTSEL_OFF (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */
-#define ACMP_CTL_FILTSEL_1PCLK (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */
-#define ACMP_CTL_FILTSEL_2PCLK (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */
-#define ACMP_CTL_FILTSEL_4PCLK (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */
-#define ACMP_CTL_FILTSEL_8PCLK (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */
-#define ACMP_CTL_FILTSEL_16PCLK (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */
-#define ACMP_CTL_FILTSEL_32PCLK (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */
-#define ACMP_CTL_FILTSEL_64PCLK (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */
-#define ACMP_CTL_INTPOL_RF (0UL << 8) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */
-#define ACMP_CTL_INTPOL_R (1UL << 8) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */
-#define ACMP_CTL_INTPOL_F (2UL << 8) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */
-#define ACMP_CTL_POSSEL_P0 (0UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */
-#define ACMP_CTL_POSSEL_P1 (1UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */
-#define ACMP_CTL_POSSEL_P2 (2UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */
-#define ACMP_CTL_POSSEL_P3 (3UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */
-#define ACMP_CTL_NEGSEL_PIN (0UL << 4) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
-#define ACMP_CTL_NEGSEL_CRV (1UL << 4) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */
-#define ACMP_CTL_NEGSEL_VBG (2UL << 4) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */
-#define ACMP_CTL_NEGSEL_DAC (3UL << 4) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */
-#define ACMP_CTL_HYSTERESIS_ENABLE (1UL << 2) /*!< ACMP_CTL setting for enabling the hysteresis function. */
-#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << 2) /*!< ACMP_CTL setting for disabling the hysteresis function. */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* ACMP_VREF constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define ACMP_VREF_CRVSSEL_VDDA (0UL << 6) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */
-#define ACMP_VREF_CRVSSEL_INTVREF (1UL << 6) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */
-
-
-/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define Macros and functions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-
-/**
- * @brief This macro is used to enable output inverse function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
- */
-#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPOINV_Msk)
-
-/**
- * @brief This macro is used to disable output inverse function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
- */
-#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPOINV_Msk)
-
-/**
- * @brief This macro is used to select ACMP negative input source
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @param[in] u32Src is comparator negative input selection. Including:
- * - \ref ACMP_CTL_NEGSEL_PIN
- * - \ref ACMP_CTL_NEGSEL_CRV
- * - \ref ACMP_CTL_NEGSEL_VBG
- * - \ref ACMP_CTL_NEGSEL_DAC
- * @return None
- * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
- */
-#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
-
-/**
- * @brief This macro is used to enable hysteresis function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will set HYSEN bit of ACMP_CTL register to enable hysteresis function.
- */
-#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_HYSEN_Msk)
-
-/**
- * @brief This macro is used to disable hysteresis function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will clear HYSEN bit of ACMP_CTL register to disable hysteresis function.
- */
-#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_HYSEN_Msk)
-
-/**
- * @brief This macro is used to enable interrupt
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
- * If wake-up function is enabled, the wake-up interrupt will be enabled as well.
- */
-#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPIE_Msk)
-
-/**
- * @brief This macro is used to disable interrupt
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
- */
-#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPIE_Msk)
-
-/**
- * @brief This macro is used to enable ACMP
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
- */
-#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_ACMPEN_Msk)
-
-/**
- * @brief This macro is used to disable ACMP
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
- */
-#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_ACMPEN_Msk)
-
-/**
- * @brief This macro is used to get ACMP output value
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return ACMP output value
- * @details This macro will return the ACMP output value.
- */
-#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum)%2)))?1:0)
-
-/**
- * @brief This macro is used to get ACMP interrupt flag
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return ACMP interrupt occurred (1) or not (0)
- * @details This macro will return the ACMP interrupt flag.
- */
-#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)%2)))?1:0)
-
-/**
- * @brief This macro is used to clear ACMP interrupt flag
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
- */
-#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)%2)))
-
-/**
- * @brief This macro is used to clear ACMP wake-up interrupt flag
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
- */
-#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)%2)))
-
-/**
- * @brief This macro is used to enable ACMP wake-up function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
- */
-#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_WKEN_Msk)
-
-/**
- * @brief This macro is used to disable ACMP wake-up function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
- */
-#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_WKEN_Msk)
-
-/**
- * @brief This macro is used to select ACMP positive input pin
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @param[in] u32Pin Comparator positive pin selection. Including:
- * - \ref ACMP_CTL_POSSEL_P0
- * - \ref ACMP_CTL_POSSEL_P1
- * - \ref ACMP_CTL_POSSEL_P2
- * - \ref ACMP_CTL_POSSEL_P3
- * @return None
- * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
- */
-#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
-
-/**
- * @brief This macro is used to enable ACMP filter function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
- */
-#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] |= ACMP_CTL_OUTSEL_Msk)
-
-/**
- * @brief This macro is used to disable ACMP filter function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @return None
- * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
- */
-#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)%2] &= ~ACMP_CTL_OUTSEL_Msk)
-
-/**
- * @brief This macro is used to set ACMP filter function
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @param[in] u32Cnt is comparator filter count setting.
- * - \ref ACMP_CTL_FILTSEL_OFF
- * - \ref ACMP_CTL_FILTSEL_1PCLK
- * - \ref ACMP_CTL_FILTSEL_2PCLK
- * - \ref ACMP_CTL_FILTSEL_4PCLK
- * - \ref ACMP_CTL_FILTSEL_8PCLK
- * - \ref ACMP_CTL_FILTSEL_16PCLK
- * - \ref ACMP_CTL_FILTSEL_32PCLK
- * - \ref ACMP_CTL_FILTSEL_64PCLK
- * @return None
- * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
- */
-#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
-
-/**
- * @brief This macro is used to select comparator reference voltage
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32Level The comparator reference voltage setting.
- * The formula is:
- * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
- * The range of u32Level is 0 ~ 15.
- * @return None
- * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
- */
-#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<<ACMP_VREF_CRVCTL_Pos))
-
-/**
- * @brief This macro is used to select the source of CRV
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32Src is the source of CRV. Including:
- * - \ref ACMP_VREF_CRVSSEL_VDDA
- * - \ref ACMP_VREF_CRVSSEL_INTVREF
- * @return None
- * @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.
- */
-#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
-
-/**
- * @brief This macro is used to select ACMP interrupt condition
- * @param[in] acmp The pointer of the specified ACMP module
- * @param[in] u32ChNum The ACMP number
- * @param[in] u32Cond Comparator interrupt condition selection. Including:
- * - \ref ACMP_CTL_INTPOL_RF
- * - \ref ACMP_CTL_INTPOL_R
- * - \ref ACMP_CTL_INTPOL_F
- * @return None
- * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
- */
-#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)%2] = ((acmp)->CTL[(u32ChNum)%2] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
-
-
-
-/* Function prototype declaration */
-void ACMP_Open(ACMP_T *, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
-void ACMP_Close(ACMP_T *, uint32_t u32ChNum);
-
-
-
-/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group ACMP_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif //__ACMP_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1004 +0,0 @@
-/**************************************************************************//**
- * @file can.c
- * @version V2.00
- * $Revision: 8 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series CAN driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup CAN_Driver CAN Driver
- @{
-*/
-
-/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
- @{
-*/
-
-/// @cond HIDDEN_SYMBOLS
-
-#if defined(CAN1)
-static uint8_t gu8LockCanIf[2][2] = {0}; // The chip has two CANs.
-#elif defined(CAN0) || defined(CAN)
-static uint8_t gu8LockCanIf[1][2] = {0}; // The chip only has one CAN.
-#endif
-
-#define RETRY_COUNTS (0x10000000)
-
-//#define DEBUG_PRINTF printf
-#define DEBUG_PRINTF(...)
-
-/**
- * @brief Check if any interface is available then lock it for usage.
- * @param[in] tCAN The pointer to CAN module base address.
- * @retval 0 IF0 is free
- * @retval 1 IF1 is free
- * @retval 2 No IF is free
- * @details Search the first free message interface, starting from 0. If a interface is
- * available, set a flag to lock the interface.
- */
-static uint32_t LockIF(CAN_T *tCAN)
-{
- uint32_t u32CanNo;
- uint32_t u32FreeIfNo;
- uint32_t u32IntMask;
-
-#if defined(CAN1)
- u32CanNo = (tCAN == CAN1) ? 1 : 0;
-#else // defined(CAN0) || defined(CAN)
- u32CanNo = 0;
-#endif
-
- u32FreeIfNo = 2;
-
- /* Disable CAN interrupt */
- u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
- tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
-
- /* Check interface 1 is available or not */
- if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
- {
- if(gu8LockCanIf[u32CanNo][0] == FALSE)
- {
- gu8LockCanIf[u32CanNo][0] = TRUE;
- u32FreeIfNo = 0;
- }
- }
-
- /* Or check interface 2 is available or not */
- if(u32FreeIfNo == 2 && (tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
- {
- if(gu8LockCanIf[u32CanNo][1] == FALSE)
- {
- gu8LockCanIf[u32CanNo][1] = TRUE;
- u32FreeIfNo = 1;
- }
- }
-
- /* Enable CAN interrupt */
- tCAN->CON |= u32IntMask;
-
- return u32FreeIfNo;
-}
-
-/**
- * @brief Check if any interface is available in a time limitation then lock it for usage.
- * @param[in] tCAN The pointer to CAN module base address.
- * @retval 0 IF0 is free
- * @retval 1 IF1 is free
- * @retval 2 No IF is free
- * @details Search the first free message interface, starting from 0. If no interface is
- * it will try again until time out. If a interface is available, set a flag to
- * lock the interface.
- */
-static uint32_t LockIF_TL(CAN_T *tCAN)
-{
- uint32_t u32Count;
- uint32_t u32FreeIfNo;
-
- for(u32Count = 0; u32Count < RETRY_COUNTS; u32Count++)
- {
- if((u32FreeIfNo = LockIF(tCAN)) != 2)
- return u32FreeIfNo;
- }
-
- return u32FreeIfNo;
-}
-
-/**
- * @brief Release locked interface.
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32Info The interface number, 0 or 1.
- * @return none
- * @details Release the locked interface.
- */
-static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)
-{
- uint32_t u32IntMask;
- uint32_t u32CanNo;
-
- if(u32IfNo >= 2)
- return;
-
-#if defined(CAN1)
- u32CanNo = (tCAN == CAN1) ? 1 : 0;
-#else // defined(CAN0) || defined(CAN)
- u32CanNo = 0;
-#endif
-
- /* Disable CAN interrupt */
- u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
- tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
-
- gu8LockCanIf[u32CanNo][u32IfNo] = FALSE;
-
- /* Enable CAN interrupt */
- tCAN->CON |= u32IntMask;
-}
-
-/**
- * @brief Enter initialization mode
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] Following values can be used.
- * \ref CAN_CON_DAR_Msk Disable automatic retransmission.
- * \ref CAN_CON_EIE_Msk Enable error interrupt.
- * \ref CAN_CON_SIE_Msk Enable status interrupt.
- * \ref CAN_CON_IE_Msk CAN interrupt.
- * @return None
- * @details This function is used to set CAN to enter initialization mode and enable access bit timing
- * register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
- * to leave initialization mode and lock bit timing register to let new configuration
- * take effect.
- */
-void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)
-{
- tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
-}
-
-
-/**
- * @brief Leave initialization mode
- * @param[in] tCAN The pointer to CAN module base address.
- * @return None
- * @details This function is used to set CAN to leave initialization mode to let
- * bit timing configuration take effect after configuration ready.
- */
-void CAN_LeaveInitMode(CAN_T *tCAN)
-{
- tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
- while(tCAN->CON & CAN_CON_INIT_Msk); /* Check INIT bit is released */
-}
-
-/**
- * @brief Wait message into message buffer in basic mode.
- * @param[in] tCAN The pointer to CAN module base address.
- * @return None
- * @details This function is used to wait message into message buffer in basic mode. Please notice the
- * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
- */
-void CAN_WaitMsg(CAN_T *tCAN)
-{
- tCAN->STATUS = 0x0; /* clr status */
-
- while(1)
- {
- if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */
- {
- DEBUG_PRINTF("New Data IN\n");
- break;
- }
-
- if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
- DEBUG_PRINTF("Rx OK\n");
-
- if(tCAN->STATUS & CAN_STATUS_LEC_Msk)
- {
- DEBUG_PRINTF("Error\n");
- }
- }
-}
-
-/**
- * @brief Get current bit rate
- * @param[in] tCAN The pointer to CAN module base address.
- * @return Current Bit-Rate (kilo bit per second)
- * @details Return current CAN bit rate according to the user bit-timing parameter settings
- */
-uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
-{
- uint8_t u8Tseg1, u8Tseg2;
- uint32_t u32Bpr;
-
- u8Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos;
- u8Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos;
- u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6);
-
- return (SystemCoreClock / (u32Bpr + 1) / (u8Tseg1 + u8Tseg2 + 3));
-}
-
-/**
- * @brief Switch the CAN into test mode.
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u8TestMask Specifies the configuration in test modes
- * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode
- * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode
- * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode
- * \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field
- * @return None
- * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
- * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
- * must call CAN_LeaveInitMode() to let the setting take effect.
- */
-void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
-{
- tCAN->CON |= CAN_CON_TEST_Msk;
- tCAN->TEST = u8TestMask;
-}
-
-
-/**
- * @brief Leave the test mode
- * @param[in] tCAN The pointer to CAN module base address.
- * @return None
- * @details This function is used to Leave the test mode (switch into normal mode).
- */
-void CAN_LeaveTestMode(CAN_T *tCAN)
-{
- tCAN->CON |= CAN_CON_TEST_Msk;
- tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
- tCAN->CON &= (~CAN_CON_TEST_Msk);
-}
-
-/**
- * @brief Get the waiting status of a received message.
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
- * @retval non-zero The corresponding message object has a new data bit is set.
- * @retval 0 No message object has new data.
- * @details This function is used to get the waiting status of a received message.
- */
-uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
-{
- return (u8MsgObj < 16 ? tCAN->NDAT1 & (1 << u8MsgObj) : tCAN->NDAT2 & (1 << (u8MsgObj - 16)));
-}
-
-
-/**
- * @brief Send CAN message in BASIC mode of test mode
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
- * @return TRUE: Transmission OK
- * FALSE: Check busy flag of interface 0 is timeout
- * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
- * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter
- * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
- */
-int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
-{
- uint32_t i = 0;
- while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk);
-
- tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
-
- if(pCanMsg->IdType == CAN_STD_ID)
- {
- /* standard ID*/
- tCAN->IF[0].ARB1 = 0;
- tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FF) << 2) ;
- }
- else
- {
- /* extended ID*/
- tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFF;
- tCAN->IF[0].ARB2 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 | CAN_IF_ARB2_XTD_Msk;
-
- }
-
- if(pCanMsg->FrameType)
- tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
- else
- tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
-
- tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
- tCAN->IF[0].DAT_A1 = ((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];
- tCAN->IF[0].DAT_A2 = ((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];
- tCAN->IF[0].DAT_B1 = ((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
- tCAN->IF[0].DAT_B2 = ((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
-
- /* request transmission*/
- tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
- if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
- {
- DEBUG_PRINTF("Cannot clear busy for sending ...\n");
- return FALSE;
- }
-
- tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; // sending
-
- for(i = 0; i < 0xFFFFF; i++)
- {
- if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
- break;
- }
-
- if(i >= 0xFFFFF)
- {
- DEBUG_PRINTF("Cannot send out...\n");
- return FALSE;
- }
-
- return TRUE;
-}
-
-/**
- * @brief Get a message information in BASIC mode.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @return FALSE No any message received.
- * TRUE Receive a message success.
- *
- */
-int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
-{
-
- if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0) /* In basic mode, receive data always save in IF2 */
- {
- return FALSE;
- }
-
- tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
-
- tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
- | CAN_IF_CMASK_CONTROL_Msk
- | CAN_IF_CMASK_DATAA_Msk
- | CAN_IF_CMASK_DATAB_Msk;
-
- if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0)
- {
- /* standard ID*/
- pCanMsg->IdType = CAN_STD_ID;
- pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FF;
-
- }
- else
- {
- /* extended ID*/
- pCanMsg->IdType = CAN_EXT_ID;
- pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFF) << 16;
- pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
- }
-
- pCanMsg->FrameType = !((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos);
-
- pCanMsg->DLC = tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk;
- pCanMsg->Data[0] = tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
- pCanMsg->Data[1] = (tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
- pCanMsg->Data[2] = tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
- pCanMsg->Data[3] = (tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
- pCanMsg->Data[4] = tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
- pCanMsg->Data[5] = (tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
- pCanMsg->Data[6] = tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
- pCanMsg->Data[7] = (tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
-
- return TRUE;
-}
-
-/**
- * @brief Set Rx message object, include ID mask.
- * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
- * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
- * This parameter can be one of the following values:
- * \ref CAN_STD_ID (standard ID, 11-bit)
- * \ref CAN_EXT_ID (extended ID, 29-bit)
- * @param[in] u32id Specifies the identifier used for acceptance filtering.
- * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
- * This parameter can be one of the following values:
- * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
- * FALSE: for a FIFO receive object that is not the last one.
- * @retval TRUE SUCCESS
- * @retval FALSE No useful interface
- * @details The function is used to configure a receive message object.
- */
-int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)
-{
- uint8_t u8MsgIfNum;
-
- /* Get and lock a free interface */
- if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
- return FALSE;
-
- /* Command Setting */
- tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
- CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
-
- if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */
- {
- tCAN->IF[u8MsgIfNum].ARB1 = 0;
- tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FF) << 2;
- }
- else
- {
- tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFF;
- tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000) >> 16;
- }
-
- tCAN->IF[u8MsgIfNum].MASK1 = (u32idmask & 0xFFFF);
- tCAN->IF[u8MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFF;
-
- //tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
- tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
- if(u8singleOrFifoLast)
- tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
- else
- tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
-
- tCAN->IF[u8MsgIfNum].DAT_A1 = 0;
- tCAN->IF[u8MsgIfNum].DAT_A2 = 0;
- tCAN->IF[u8MsgIfNum].DAT_B1 = 0;
- tCAN->IF[u8MsgIfNum].DAT_B2 = 0;
-
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
- ReleaseIF(tCAN, u8MsgIfNum);
-
- return TRUE;
-}
-
-/**
- * @brief Set Rx message object
- * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
- * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
- * This parameter can be one of the following values:
- * \ref CAN_STD_ID (standard ID, 11-bit)
- * \ref CAN_EXT_ID (extended ID, 29-bit)
- * @param[in] u32id Specifies the identifier used for acceptance filtering.
- * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
- * This parameter can be one of the following values:
- * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
- * FALSE: for a FIFO receive object that is not the last one.
- * @retval TRUE SUCCESS
- * @retval FALSE No useful interface
- * @details The function is used to configure a receive message object.
- */
-int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
-{
- uint8_t u8MsgIfNum;
-
- /* Get and lock a free interface */
- if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
- return FALSE;
-
- /* Command Setting */
- tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
- CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
-
- if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */
- {
- tCAN->IF[u8MsgIfNum].ARB1 = 0;
- tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FF) << 2;
- }
- else
- {
- tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFF;
- tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000) >> 16;
- }
-
- //tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
- tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
- if(u8singleOrFifoLast)
- tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
- else
- tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
-
- tCAN->IF[u8MsgIfNum].DAT_A1 = 0;
- tCAN->IF[u8MsgIfNum].DAT_A2 = 0;
- tCAN->IF[u8MsgIfNum].DAT_B1 = 0;
- tCAN->IF[u8MsgIfNum].DAT_B2 = 0;
-
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
- ReleaseIF(tCAN, u8MsgIfNum);
-
- return TRUE;
-}
-
-/**
- * @brief Gets the message
- * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
- * @param[in] u8Release Specifies the message release indicator.
- * This parameter can be one of the following values:
- * TRUE: the message object is released when getting the data.
- * FALSE:the message object is not released.
- * @param[in] pCanMsg Pointer to the message structure where received data is copied.
- * @retval TRUE Success
- * @retval FALSE No any message received
- * @details Gets the message, if received.
- */
-int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)
-{
- uint8_t u8MsgIfNum;
-
- if(!CAN_IsNewDataReceived(tCAN, u8MsgObj))
- return FALSE;
-
- /* Get and lock a free interface */
- if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
- return FALSE;
-
- tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
-
- /* read the message contents*/
- tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk
- | CAN_IF_CMASK_ARB_Msk
- | CAN_IF_CMASK_CONTROL_Msk
- | CAN_IF_CMASK_CLRINTPND_Msk
- | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0)
- | CAN_IF_CMASK_DATAA_Msk
- | CAN_IF_CMASK_DATAB_Msk;
-
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
-
- while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
- {
- /*Wait*/
- }
-
- if((tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0)
- {
- /* standard ID*/
- pCanMsg->IdType = CAN_STD_ID;
- pCanMsg->Id = (tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2;
- }
- else
- {
- /* extended ID*/
- pCanMsg->IdType = CAN_EXT_ID;
- pCanMsg->Id = (((tCAN->IF[u8MsgIfNum].ARB2) & 0x1FFF) << 16) | tCAN->IF[u8MsgIfNum].ARB1;
- }
-
- pCanMsg->DLC = tCAN->IF[u8MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk;
- pCanMsg->Data[0] = tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
- pCanMsg->Data[1] = (tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
- pCanMsg->Data[2] = tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
- pCanMsg->Data[3] = (tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
- pCanMsg->Data[4] = tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
- pCanMsg->Data[5] = (tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
- pCanMsg->Data[6] = tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
- pCanMsg->Data[7] = (tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
-
- ReleaseIF(tCAN, u8MsgIfNum);
- return TRUE;
-}
-
-/// @endcond HIDDEN_SYMBOLS
-
-
-/**
- * @brief Set bus baud-rate.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
- *
- * @return u32CurrentBitRate Real baud-rate value.
- *
- * @details The function is used to set bus timing parameter according current clock and target baud-rate.
- */
-uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
-{
- uint8_t u8Tseg1, u8Tseg2;
- uint32_t u32Brp;
- uint32_t u32Value;
-
- CAN_EnterInitMode(tCAN, 0);
- SystemCoreClockUpdate();
- u32Value = SystemCoreClock / u32BaudRate;
-
-#if 0
- u8Tseg1 = 2;
- u8Tseg2 = 1;
- while(1)
- {
- if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0))
- break;
- if(u8Tseg1 < 7)
- u8Tseg2++;
-
- if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
- break;
- if(u8Tseg1 < 15)
- u8Tseg1++;
- else
- {
- u8Tseg1 = 2;
- u8Tseg2 = 1;
- break;
- }
- }
-#else
-
- /* Fix for most standard baud rates, include 125K */
-
- u8Tseg1 = 3;
- u8Tseg2 = 2;
- while(1)
- {
- if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0) | (u8Tseg1 >= 15))
- break;
-
- u8Tseg1++;
-
- if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
- break;
-
- if(u8Tseg2 < 7)
- u8Tseg2++;
- }
-#endif
- u32Brp = SystemCoreClock / (u32BaudRate) / (u8Tseg1 + u8Tseg2 + 3) - 1;
-
- u32Value = ((uint32_t)u8Tseg2 << CAN_BTIME_TSEG2_Pos) | ((uint32_t)u8Tseg1 << CAN_BTIME_TSEG1_Pos) |
- (u32Brp & CAN_BTIME_BRP_Msk) | (tCAN->BTIME & CAN_BTIME_SJW_Msk);
- tCAN->BTIME = u32Value;
- tCAN->BRPE = (u32Brp >> 6) & 0x0F;
-
- CAN_LeaveInitMode(tCAN);
-
- return (CAN_GetCANBitRate(tCAN));
-}
-
-/**
- * @brief The function is used to disable all CAN interrupt.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- *
- * @return None
- *
- * @details No Status Change Interrupt and Error Status Interrupt will be generated.
- */
-void CAN_Close(CAN_T *tCAN)
-{
- CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
-}
-
-/**
- * @brief Set CAN operation mode and target baud-rate.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
- * @param[in] u32Mode The CAN operation mode. Valid values are:
- * - \ref CAN_NORMAL_MODE Normal operation.
- * - \ref CAN_BASIC_MODE Basic mode.
- * @return u32CurrentBitRate Real baud-rate value.
- *
- * @details Set bus timing parameter according current clock and target baud-rate.
- * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
- */
-uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
-{
- uint32_t u32CurrentBitRate;
-
- u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
-
- if(u32Mode == CAN_BASIC_MODE)
- CAN_EnterTestMode(tCAN, CAN_TEST_BASIC_Msk);
-
- return u32CurrentBitRate;
-}
-
-/**
- * @brief The function is used to configure a transmit object.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- * @param[in] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @retval FALSE No useful interface.
- * @retval TRUE Config message object success.
- *
- * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
- * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
- */
-int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
-{
- uint8_t u8MsgIfNum;
-
- if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
- return FALSE;
-
- /* update the contents needed for transmission*/
- tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
- CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
-
- if(pCanMsg->IdType == CAN_STD_ID)
- {
- /* standard ID*/
- tCAN->IF[u8MsgIfNum].ARB1 = 0;
- tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FF) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
- }
- else
- {
- /* extended ID*/
- tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFF;
- tCAN->IF[u8MsgIfNum].ARB2 = ((pCanMsg->Id) & 0x1FFF0000) >> 16 |
- CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
- }
-
- if(pCanMsg->FrameType)
- tCAN->IF[u8MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk;
- else
- tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
-
- tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint16_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];
- tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint16_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];
- tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint16_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
- tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint16_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
-
- tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
-
- ReleaseIF(tCAN, u8MsgIfNum);
- return TRUE;
-}
-
-/**
- * @brief Set transmit request bit.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- *
- * @return TRUE: Start transmit message.
- *
- * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.
- */
-int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum)
-{
- uint8_t u8MsgIfNum;
-
- if((u8MsgIfNum = LockIF_TL(tCAN)) == 2)
- return FALSE;
-
- tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
-
- /* read the message contents*/
- tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk
- | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
-
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
-
- while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
- {
- /*Wait*/
- }
- tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
-
- ReleaseIF(tCAN, u8MsgIfNum);
- return TRUE;
-}
-
-/**
- * @brief Enable CAN interrupt.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32Mask Interrupt Mask. Valid values are:
- * - \ref CAN_CON_IE_Msk Module interrupt enable.
- * - \ref CAN_CON_SIE_Msk Status change interrupt enable.
- * - \ref CAN_CON_EIE_Msk Error interrupt enable.
- *
- * @return None
- *
- * @details The application software has two possibilities to follow the source of a message interrupt.
- * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.
- */
-void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
-{
- tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |
- (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
-}
-
-/**
- * @brief Disable CAN interrupt.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).
- *
- * @return None
- *
- * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
- */
-void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
-{
- tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));
-}
-
-
-/**
- * @brief The function is used to configure a receive message object.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
- * - \ref CAN_STD_ID The 11-bit identifier.
- * - \ref CAN_EXT_ID The 29-bit identifier.
- * @param[in] u32ID Specifies the identifier used for acceptance filtering.
- *
- * @retval FALSE No useful interface.
- * @retval TRUE Configure a receive message object success.
- *
- * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
- * will be set when a received Data Frame is accepted and stored in the Message Object.
- */
-int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID)
-{
- uint32_t u32TimeOutCount = 0;
-
- while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, TRUE) == FALSE)
- {
- if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
- }
-
- return TRUE;
-}
-
-/**
- * @brief The function is used to configure a receive message object.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
- * - \ref CAN_STD_ID The 11-bit identifier.
- * - \ref CAN_EXT_ID The 29-bit identifier.
- * @param[in] u32ID Specifies the identifier used for acceptance filtering.
- * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.
- *
- * @retval FALSE No useful interface.
- * @retval TRUE Configure a receive message object success.
- *
- * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
- * will be set when a received Data Frame is accepted and stored in the Message Object.
- */
-int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)
-{
- uint32_t u32TimeOutCount = 0;
-
- while(CAN_SetRxMsgObjAndMsk(tCAN, u32MsgNum, u32IDType, u32ID, u32IDMask, TRUE) == FALSE)
- {
- if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
- }
-
- return TRUE;
-}
-
-/**
- * @brief The function is used to configure several receive message objects.
- *
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).
- * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
- * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
- * - \ref CAN_STD_ID The 11-bit identifier.
- * - \ref CAN_EXT_ID The 29-bit identifier.
- * @param[in] u32ID Specifies the identifier used for acceptance filtering.
- *
- * @retval FALSE No useful interface.
- * @retval TRUE Configure receive message objects success.
- *
- * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
- * and transmission by buffering the data to be transferred.
- */
-int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
-{
- uint32_t i = 0;
- uint32_t u32TimeOutCount;
- uint32_t u32EOB_Flag = 0;
-
- for(i = 1; i < u32MsgCount; i++)
- {
- u32TimeOutCount = 0;
-
- u32MsgNum += (i - 1);
-
- if(i == u32MsgCount) u32EOB_Flag = 1;
-
- while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, u32EOB_Flag) == FALSE)
- {
- if(++u32TimeOutCount >= RETRY_COUNTS) return FALSE;
- }
- }
-
- return TRUE;
-}
-
-
-/**
- * @brief Send CAN message.
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- * @param[in] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n
- * 2. When operation in normal mode: No useful interface. \n
- * @retval TRUE Transmit Message success.
- *
- * @details The receive/transmit priority for the Message Objects is attached to the message number.
- * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.
- */
-int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
-{
- if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk))
- {
- return (CAN_BasicSendMsg(tCAN, pCanMsg));
- }
- else
- {
- if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE)
- return FALSE;
- CAN_TriggerTxMsg(tCAN, u32MsgNum);
- }
-
- return TRUE;
-}
-
-
-/**
- * @brief Gets the message, if received.
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- * @param[in] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @retval FALSE No any message received.
- * @retval TRUE Receive Message success.
- *
- * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
- * and transmission by buffering the data to be transferred.
- */
-int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
-{
- if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk))
- {
- return (CAN_BasicReceiveMsg(tCAN, pCanMsg));
- }
- else
- {
- return CAN_ReadMsgObj(tCAN, u32MsgNum, TRUE, pCanMsg);
- }
-}
-
-/**
- * @brief Clear interrupt pending bit.
- * @param[in] tCAN The pointer to CAN module base address.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- *
- * @return None
- *
- * @details An interrupt remains pending until the application software has cleared it.
- */
-void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
-{
- uint32_t u32MsgIfNum;
-
- if((u32MsgIfNum = LockIF_TL(tCAN)) == 2)
- u32MsgIfNum = 0;
-
- tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
- tCAN->IF[u32MsgIfNum].CREQ = 1 + u32MsgNum;
-
- ReleaseIF(tCAN, u32MsgIfNum);
-}
-
-
-/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group CAN_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_can.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,179 +0,0 @@
-/**************************************************************************//**
- * @file can.h
- * @version V2.00
- * $Revision: 9 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 Series CAN Driver Header File
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __CAN_H__
-#define __CAN_H__
-
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup CAN_Driver CAN Driver
- @{
-*/
-
-/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* CAN Test Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CAN_NORMAL_MODE 0
-#define CAN_BASIC_MODE 1
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Message ID Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CAN_STD_ID 0
-#define CAN_EXT_ID 1
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Message Frame Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CAN_REMOTE_FRAME 0
-#define CAN_DATA_FRAME 1
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CAN message structure */
-/*---------------------------------------------------------------------------------------------------------*/
-typedef struct
-{
- uint32_t IdType;
- uint32_t FrameType;
- uint32_t Id;
- uint8_t DLC;
- uint8_t Data[8];
-} STR_CANMSG_T;
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CAN mask message structure */
-/*---------------------------------------------------------------------------------------------------------*/
-typedef struct
-{
- uint8_t u8Xtd;
- uint8_t u8Dir;
- uint32_t u32Id;
- uint8_t u8IdType;
-} STR_CANMASK_T;
-
-#define MSG(id) (id)
-
-
-/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
- @{
-*/
-
-/**
- * @brief Get interrupt status.
- *
- * @param[in] can The base address of can module.
- *
- * @return CAN module status register value.
- *
- * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
- * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
- */
-#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
-
-/**
- * @brief Get specified interrupt pending status.
- *
- * @param[in] can The base address of can module.
- *
- * @return The source of the interrupt.
- *
- * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
- * with the highest priority, disregarding their chronological order.
- */
-#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
-
-/**
- * @brief Disable wake-up function.
- *
- * @param[in] can The base address of can module.
- *
- * @return None
- *
- * @details The macro is used to disable wake-up function.
- */
-#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0)
-
-/**
- * @brief Enable wake-up function.
- *
- * @param[in] can The base address of can module.
- *
- * @return None
- *
- * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
- */
-#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WUEN_WAKUP_EN_Msk)
-
-/**
- * @brief Get specified Message Object new data into bit value.
- *
- * @param[in] can The base address of can module.
- * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
- *
- * @return Specified Message Object new data into bit value.
- *
- * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
- * or by the Message Handler after reception of a Data Frame or after a successful transmission.
- */
-#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define CAN functions prototype */
-/*---------------------------------------------------------------------------------------------------------*/
-uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
-uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
-void CAN_Close(CAN_T *tCAN);
-void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
-void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
-void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
-int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
-int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
-int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
-int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
-int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
-int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
-int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);
-uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
-void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
-void CAN_LeaveInitMode(CAN_T *tCAN);
-void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
-void CAN_LeaveTestMode(CAN_T *tCAN);
-
-/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group CAN_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__CAN_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,751 +0,0 @@
-/**************************************************************************//**
- * @file clk.c
- * @version V3.00
- * $Revision: 35 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series CLK driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup CLK_Driver CLK Driver
- @{
-*/
-
-/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
- @{
-*/
-
-/**
- * @brief Disable clock divider output function
- * @param None
- * @return None
- * @details This function disable clock divider output function.
- */
-void CLK_DisableCKO(void)
-{
- /* Disable CKO clock source */
- CLK_DisableModuleClock(CLKO_MODULE);
-}
-
-/**
- * @brief This function enable clock divider output module clock,
- * enable clock divider output function and set frequency selection.
- * @param[in] u32ClkSrc is frequency divider function clock source. Including :
- * - \ref CLK_CLKSEL1_CLKOSEL_HXT
- * - \ref CLK_CLKSEL1_CLKOSEL_LXT
- * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
- * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
- * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15.
- * @param[in] u32ClkDivBy1En is clock divided by one enabled.
- * @return None
- * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
- * The formula is: \n
- * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
- * This function is just used to set CKO clock.
- * User must enable I/O for CKO clock output pin by themselves. \n
- */
-void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
-{
- /* CKO = clock source / 2^(u32ClkDiv + 1) */
- CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
-
- /* Enable CKO clock source */
- CLK_EnableModuleClock(CLKO_MODULE);
-
- /* Select CKO clock source */
- CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0);
-}
-
-/**
- * @brief Enter to Power-down mode
- * @param None
- * @return None
- * @details This function is used to let system enter to Power-down mode. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_PowerDown(void)
-{
- /* Set the processor uses deep sleep as its low power mode */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Set system Power-down enabled and Power-down entry condition */
- CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWTCPU_Msk);
-
- /* Chip enter Power-down mode after CPU run WFI instruction */
- __WFI();
-}
-
-/**
- * @brief Enter to Idle mode
- * @param None
- * @return None
- * @details This function let system enter to Idle mode. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_Idle(void)
-{
- /* Set the processor uses sleep as its low power mode */
- SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-
- /* Set chip in idle mode because of WFI command */
- CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
-
- /* Chip enter idle mode after CPU run WFI instruction */
- __WFI();
-}
-
-/**
- * @brief Get external high speed crystal clock frequency
- * @param None
- * @return External high frequency crystal frequency
- * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetHXTFreq(void)
-{
- if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
- return __HXT;
- else
- return 0;
-}
-
-
-/**
- * @brief Get external low speed crystal clock frequency
- * @param None
- * @return External low speed crystal clock frequency
- * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetLXTFreq(void)
-{
- if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
- return __LXT;
- else
- return 0;
-}
-
-/**
- * @brief Get PCLK0 frequency
- * @param None
- * @return PCLK0 frequency
- * @details This function get PCLK0 frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetPCLK0Freq(void)
-{
- SystemCoreClockUpdate();
- if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk)
- return SystemCoreClock / 2;
- else
- return SystemCoreClock;
-}
-
-
-/**
- * @brief Get PCLK1 frequency
- * @param None
- * @return PCLK1 frequency
- * @details This function get PCLK1 frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetPCLK1Freq(void)
-{
- SystemCoreClockUpdate();
- if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk)
- return SystemCoreClock / 2;
- else
- return SystemCoreClock;
-}
-
-
-/**
- * @brief Get HCLK frequency
- * @param None
- * @return HCLK frequency
- * @details This function get HCLK frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetHCLKFreq(void)
-{
- SystemCoreClockUpdate();
- return SystemCoreClock;
-}
-
-
-/**
- * @brief Get CPU frequency
- * @param None
- * @return CPU frequency
- * @details This function get CPU frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetCPUFreq(void)
-{
- SystemCoreClockUpdate();
- return SystemCoreClock;
-}
-
-
-/**
- * @brief Set HCLK frequency
- * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 72 MHz.
- * @return HCLK frequency
- * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n
- * It would configure PLL frequency to 50MHz ~ 144MHz,
- * set HCLK clock divider as 2 and switch HCLK clock source to PLL. \n
- * The register write-protection function should be disabled before using this function.
- */
-uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
-{
- uint32_t u32HIRCSTB;
-
- /* Read HIRC clock source stable flag */
- u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
-
- /* The range of u32Hclk is 25 MHz ~ 72 MHz */
- if(u32Hclk > FREQ_72MHZ)
- u32Hclk = FREQ_72MHZ;
- if(u32Hclk < FREQ_25MHZ)
- u32Hclk = FREQ_25MHZ;
-
- /* Switch HCLK clock source to HIRC clock for safe */
- CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
- CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
- CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
- CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
-
- /* Configure PLL setting if HXT clock is enabled */
- if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
- u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, (u32Hclk << 1));
-
- /* Configure PLL setting if HXT clock is not enabled */
- else
- {
- u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, (u32Hclk << 1));
-
- /* Read HIRC clock source stable flag */
- u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
- }
-
- /* Select HCLK clock source to PLL,
- Select HCLK clock source divider as 2
- and update system core clock
- */
- CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2));
-
- /* Disable HIRC if HIRC is disabled before setting core clock */
- if(u32HIRCSTB == 0)
- CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
-
- /* Return actually HCLK frequency is PLL frequency divide 2 */
- return u32Hclk >> 1;
-}
-
-/**
- * @brief This function set HCLK clock source and HCLK clock divider
- * @param[in] u32ClkSrc is HCLK clock source. Including :
- * - \ref CLK_CLKSEL0_HCLKSEL_HXT
- * - \ref CLK_CLKSEL0_HCLKSEL_LXT
- * - \ref CLK_CLKSEL0_HCLKSEL_PLL
- * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
- * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
- * @param[in] u32ClkDiv is HCLK clock divider. Including :
- * - \ref CLK_CLKDIV0_HCLK(x)
- * @return None
- * @details This function set HCLK clock source and HCLK clock divider. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
-{
- uint32_t u32HIRCSTB;
-
- /* Read HIRC clock source stable flag */
- u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
-
- /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
- CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
- CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
- CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
-
- /* Apply new Divider */
- CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
-
- /* Switch HCLK to new HCLK source */
- CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
-
- /* Update System Core Clock */
- SystemCoreClockUpdate();
-
- /* Disable HIRC if HIRC is disabled before switching HCLK source */
- if(u32HIRCSTB == 0)
- CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
-}
-
-/**
- * @brief This function set selected module clock source and module clock divider
- * @param[in] u32ModuleIdx is module index.
- * @param[in] u32ClkSrc is module clock source.
- * @param[in] u32ClkDiv is module clock divider.
- * @return None
- * @details Valid parameter combinations listed in following table:
- *
- * |Module index |Clock source |Divider |
- * | :---------------- | :----------------------------------- | :---------------------- |
- * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
- * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_PCLK0_DIV2048 | x |
- * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
- * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x |
- * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
- * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
- * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
- * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK0 | x |
- * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
- * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
- * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |
- * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK1 | x |
- * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
- * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |
- * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |
- * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK0 | x |
- * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |
- * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref USBH_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
- * |\ref USBD_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
- * |\ref OTG_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
- * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PLL | x |
- * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PCLK0 | x |
- * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PLL | x |
- * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PCLK1 | x |
- * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_PCLK0_DIV2048 | x |
- * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
- */
-void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
-{
- uint32_t u32sel = 0, u32div = 0;
-
- if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
- {
- /* Get clock divider control register address */
- u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4);
- /* Apply new divider */
- M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
- }
-
- if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
- {
- /* Get clock select control register address */
- u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4);
- /* Set new clock selection setting */
- M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
- }
-}
-
-
-/**
- * @brief Set SysTick clock source
- * @param[in] u32ClkSrc is module clock source. Including:
- * - \ref CLK_CLKSEL0_STCLKSEL_HXT
- * - \ref CLK_CLKSEL0_STCLKSEL_LXT
- * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
- * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
- * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
- * @return None
- * @details This function set SysTick clock source. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
-{
- CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
-
-}
-
-/**
- * @brief Enable clock source
- * @param[in] u32ClkMask is clock source mask. Including :
- * - \ref CLK_PWRCTL_HXTEN_Msk
- * - \ref CLK_PWRCTL_LXTEN_Msk
- * - \ref CLK_PWRCTL_HIRCEN_Msk
- * - \ref CLK_PWRCTL_LIRCEN_Msk
- * @return None
- * @details This function enable clock source. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_EnableXtalRC(uint32_t u32ClkMask)
-{
- CLK->PWRCTL |= u32ClkMask;
-}
-
-/**
- * @brief Disable clock source
- * @param[in] u32ClkMask is clock source mask. Including :
- * - \ref CLK_PWRCTL_HXTEN_Msk
- * - \ref CLK_PWRCTL_LXTEN_Msk
- * - \ref CLK_PWRCTL_HIRCEN_Msk
- * - \ref CLK_PWRCTL_LIRCEN_Msk
- * @return None
- * @details This function disable clock source. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_DisableXtalRC(uint32_t u32ClkMask)
-{
- CLK->PWRCTL &= ~u32ClkMask;
-}
-
-/**
- * @brief Enable module clock
- * @param[in] u32ModuleIdx is module index. Including :
- * - \ref PDMA_MODULE
- * - \ref ISP_MODULE
- * - \ref EBI_MODULE
- * - \ref USBH_MODULE
- * - \ref CRC_MODULE
- * - \ref WDT_MODULE
- * - \ref WWDT_MODULE
- * - \ref RTC_MODULE
- * - \ref TMR0_MODULE
- * - \ref TMR1_MODULE
- * - \ref TMR2_MODULE
- * - \ref TMR3_MODULE
- * - \ref CLKO_MODULE
- * - \ref ACMP01_MODULE
- * - \ref I2C0_MODULE
- * - \ref I2C1_MODULE
- * - \ref SPI0_MODULE
- * - \ref SPI1_MODULE
- * - \ref SPI2_MODULE
- * - \ref UART0_MODULE
- * - \ref UART1_MODULE
- * - \ref UART2_MODULE
- * - \ref UART3_MODULE
- * - \ref CAN0_MODULE
- * - \ref OTG_MODULE
- * - \ref USBD_MODULE
- * - \ref EADC_MODULE
- * - \ref SC0_MODULE
- * - \ref DAC_MODULE
- * - \ref PWM0_MODULE
- * - \ref PWM1_MODULE
- * - \ref TK_MODULE
- * @return None
- * @details This function is used to enable module clock.
- */
-void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
-{
- *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
-}
-
-/**
- * @brief Disable module clock
- * @param[in] u32ModuleIdx is module index. Including :
- * - \ref PDMA_MODULE
- * - \ref ISP_MODULE
- * - \ref EBI_MODULE
- * - \ref USBH_MODULE
- * - \ref CRC_MODULE
- * - \ref WDT_MODULE
- * - \ref WWDT_MODULE
- * - \ref RTC_MODULE
- * - \ref TMR0_MODULE
- * - \ref TMR1_MODULE
- * - \ref TMR2_MODULE
- * - \ref TMR3_MODULE
- * - \ref CLKO_MODULE
- * - \ref ACMP01_MODULE
- * - \ref I2C0_MODULE
- * - \ref I2C1_MODULE
- * - \ref SPI0_MODULE
- * - \ref SPI1_MODULE
- * - \ref SPI2_MODULE
- * - \ref UART0_MODULE
- * - \ref UART1_MODULE
- * - \ref UART2_MODULE
- * - \ref UART3_MODULE
- * - \ref CAN0_MODULE
- * - \ref OTG_MODULE
- * - \ref USBD_MODULE
- * - \ref EADC_MODULE
- * - \ref SC0_MODULE
- * - \ref DAC_MODULE
- * - \ref PWM0_MODULE
- * - \ref PWM1_MODULE
- * - \ref TK_MODULE
- * @return None
- * @details This function is used to disable module clock.
- */
-void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
-{
- *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
-}
-
-
-/**
- * @brief Set PLL frequency
- * @param[in] u32PllClkSrc is PLL clock source. Including :
- * - \ref CLK_PLLCTL_PLLSRC_HXT
- * - \ref CLK_PLLCTL_PLLSRC_HIRC
- * @param[in] u32PllFreq is PLL frequency.
- * @return PLL frequency
- * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
- * The register write-protection function should be disabled before using this function.
- */
-uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
-{
- uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
- uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
-
- /* Disable PLL first to avoid unstable when setting PLL */
- CLK_DisablePLL();
-
- /* PLL source clock is from HXT */
- if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
- {
- /* Enable HXT clock */
- CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
-
- /* Wait for HXT clock ready */
- CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
-
- /* Select PLL source clock from HXT */
- u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
- u32PllSrcClk = __HXT;
-
- /* u32NR start from 2 */
- u32NR = 2;
- }
-
- /* PLL source clock is from HIRC */
- else
- {
- /* Enable HIRC clock */
- CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
-
- /* Wait for HIRC clock ready */
- CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
-
- /* Select PLL source clock from HIRC */
- u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
- u32PllSrcClk = __HIRC;
-
- /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
- u32NR = 4;
- }
-
- /* Select "NO" according to request frequency */
- if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ))
- {
- u32NO = 0;
- }
- else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ))
- {
- u32NO = 1;
- u32PllFreq = u32PllFreq << 1;
- }
- else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ))
- {
- u32NO = 3;
- u32PllFreq = u32PllFreq << 2;
- }
- else
- {
- /* Wrong frequency request. Just return default setting. */
- goto lexit;
- }
-
- /* Find best solution */
- u32Min = (uint32_t) - 1;
- u32MinNR = 0;
- u32MinNF = 0;
- for(; u32NR <= 33; u32NR++)
- {
- u32Tmp = u32PllSrcClk / u32NR;
- if((u32Tmp > 1600000) && (u32Tmp < 16000000))
- {
- for(u32NF = 2; u32NF <= 513; u32NF++)
- {
- u32Tmp2 = u32Tmp * u32NF;
- if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000))
- {
- u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
- if(u32Tmp3 < u32Min)
- {
- u32Min = u32Tmp3;
- u32MinNR = u32NR;
- u32MinNF = u32NF;
-
- /* Break when get good results */
- if(u32Min == 0)
- break;
- }
- }
- }
- }
- }
-
- /* Enable and apply new PLL setting. */
- CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
-
- /* Wait for PLL clock stable */
- CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
-
- /* Return actual PLL output clock frequency */
- return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
-
-lexit:
-
- /* Apply default PLL setting and return */
- if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
- CLK->PLLCTL = CLK_PLLCTL_72MHz_HXT; /* 72MHz */
- else
- CLK->PLLCTL = CLK_PLLCTL_72MHz_HIRC; /* 71.8848MHz */
-
- /* Wait for PLL clock stable */
- CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
-
- return CLK_GetPLLClockFreq();
-
-}
-
-/**
- * @brief Disable PLL
- * @param None
- * @return None
- * @details This function set PLL in Power-down mode. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_DisablePLL(void)
-{
- CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
-}
-
-
-/**
- * @brief This function check selected clock source status
- * @param[in] u32ClkMask is selected clock source. Including :
- * - \ref CLK_STATUS_HXTSTB_Msk
- * - \ref CLK_STATUS_LXTSTB_Msk
- * - \ref CLK_STATUS_HIRCSTB_Msk
- * - \ref CLK_STATUS_LIRCSTB_Msk
- * - \ref CLK_STATUS_PLLSTB_Msk
- * @retval 0 clock is not stable
- * @retval 1 clock is stable
- * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)
- */
-uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
-{
- int32_t i32TimeOutCnt = 2160000;
-
- while((CLK->STATUS & u32ClkMask) != u32ClkMask)
- {
- if(i32TimeOutCnt-- <= 0)
- return 0;
- }
-
- return 1;
-}
-
-/**
- * @brief Enable System Tick counter
- * @param[in] u32ClkSrc is System Tick clock source. Including:
- * - \ref CLK_CLKSEL0_STCLKSEL_HXT
- * - \ref CLK_CLKSEL0_STCLKSEL_LXT
- * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
- * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
- * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
- * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
- * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
- * @return None
- * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
- * The register write-protection function should be disabled before using this function.
- */
-void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
-{
- /* Set System Tick counter disabled */
- SysTick->CTRL = 0;
-
- /* Set System Tick clock source */
- if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
- SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
- else
- CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
-
- /* Set System Tick reload value */
- SysTick->LOAD = u32Count;
-
- /* Clear System Tick current value and counter flag */
- SysTick->VAL = 0;
-
- /* Set System Tick interrupt enabled and counter enabled */
- SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
-}
-
-/**
- * @brief Disable System Tick counter
- * @param None
- * @return None
- * @details This function disable System Tick counter.
- */
-void CLK_DisableSysTick(void)
-{
- /* Set System Tick counter disabled */
- SysTick->CTRL = 0;
-}
-
-
-/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group CLK_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,447 +0,0 @@
-/******************************************************************************
- * @file CLK.h
- * @version V3.0
- * $Revision 1 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 Series CLK Header File
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- ******************************************************************************/
-#ifndef __CLK_H__
-#define __CLK_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup CLK_Driver CLK Driver
- @{
-*/
-
-/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
- @{
-*/
-
-
-#define FREQ_25MHZ 25000000
-#define FREQ_50MHZ 50000000
-#define FREQ_72MHZ 72000000
-#define FREQ_125MHZ 125000000
-#define FREQ_200MHZ 200000000
-#define FREQ_250MHZ 250000000
-#define FREQ_500MHZ 500000000
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL0 constant definitions. (Write-protection) */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HXT */
-#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LXT */
-#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as PLL */
-#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LIRC */
-#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HIRC */
-
-#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
-#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as LXT */
-#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
-#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HCLK/2 */
-#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HIRC/2 */
-#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
-
-#define CLK_CLKSEL0_PCLK0SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK */
-#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK/2 */
-
-#define CLK_CLKSEL0_PCLK1SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK */
-#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK/2 */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL1 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LXT */
-#define CLK_CLKSEL1_WDTSEL_PCLK0_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as PCLK0/2048 */
-#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LIRC */
-
-#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HXT */
-#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LXT */
-#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 */
-#define CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
-#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LIRC */
-#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HIRC */
-
-#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HXT */
-#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LXT */
-#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK0 */
-#define CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger */
-#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LIRC */
-#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HIRC */
-
-#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HXT */
-#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LXT */
-#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK1 */
-#define CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger */
-#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LIRC */
-#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HIRC */
-
-#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HXT */
-#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LXT */
-#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK1 */
-#define CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger */
-#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LIRC */
-#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HIRC */
-
-#define CLK_CLKSEL1_UARTSEL_HXT (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as HXT */
-#define CLK_CLKSEL1_UARTSEL_PLL (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as PLL */
-#define CLK_CLKSEL1_UARTSEL_LXT (0x2UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as LXT */
-#define CLK_CLKSEL1_UARTSEL_HIRC (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UART clock source as HIRC */
-
-#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HXT */
-#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as LXT */
-#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK */
-#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HIRC */
-
-#define CLK_CLKSEL1_WWDTSEL_PCLK0_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as PCLK0/2048 */
-#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as LIRC */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL2 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL2_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PLL */
-#define CLK_CLKSEL2_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PCLK0 */
-
-#define CLK_CLKSEL2_PWM1SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM1 clock source as PLL */
-#define CLK_CLKSEL2_PWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM1 clock source as PCLK1 */
-
-#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HXT */
-#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL */
-#define CLK_CLKSEL2_SPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK0 */
-#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HIRC */
-
-#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HXT */
-#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL */
-#define CLK_CLKSEL2_SPI1SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK1 */
-#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HIRC */
-
-#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HXT */
-#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL */
-#define CLK_CLKSEL2_SPI2SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK0 */
-#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HIRC */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL3 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HXT */
-#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL */
-#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK0 */
-#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HIRC */
-
-#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LXT */
-#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LIRC */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKDIV0 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
-#define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 */
-#define CLK_CLKDIV0_UART(x) (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLKDIV0 Setting for UART clock divider. It could be 1~16 */
-#define CLK_CLKDIV0_EADC(x) (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKDIV1 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 3.2MHz < FIN < 150MHz */
-#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 3.2MHz < FIN < 150MHz */
-
-#define CLK_PLLCTL_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*NF/NR < 500MHz. (FIN*NF/NR > 250MHz is preferred.) */
-#define CLK_PLLCTL_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 16MHz */
-
-#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */
-#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */
-#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */
-
-#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) */
-#define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) */
-#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 71.8848MHz PLL output with HIRC(22.1184MHz IRC) */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* MODULE constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-
-/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
-
-#define MODULE_APBCLK(x) (((x) >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
-#define MODULE_CLKSEL(x) (((x) >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
-#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index */
-#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
-#define MODULE_CLKDIV(x) (((x) >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
-#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
-#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
-#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
-#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
-#define NA MODULE_NoMsk /*!< Not Available */
-
-#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
-#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
-#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */
-#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
-#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1 */
-#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
-#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
-#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */
-
-
-//AHBCLK
-#define PDMA_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMACKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */
-
-#define ISP_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISPCKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */
-
-#define EBI_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_EBICKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */
-
-#define USBH_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_USBHCKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBH Module */
-
-#define CRC_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRCCKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */
-
-
-//APBCLK0
-#define WDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos) |\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WDT Module */
-
-#define WWDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos) |\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(30)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */
-
-#define RTC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_RTCCKEN_Pos) |\
- MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 8)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */
-
-#define TMR0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR0CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 8)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR0 Module */
-
-#define TMR1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR1CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(12)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR1 Module */
-
-#define TMR2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR2CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(16)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR2 Module */
-
-#define TMR3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR3CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(20)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR3 Module */
-
-#define CLKO_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CLKOCKEN_Pos) |\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(28)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CLKO Module */
-
-#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ACMP01CKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */
-
-#define I2C0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C0CKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */
-
-#define I2C1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C1CKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */
-
-#define SPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI0CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI0 Module */
-
-#define SPI1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI1CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI1 Module */
-
-#define SPI2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI2CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 6)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI2 Module */
-
-#define UART0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART0CKEN_Pos)|\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART0 Module */
-
-#define UART1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART1CKEN_Pos)|\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART1 Module */
-
-#define UART2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART2CKEN_Pos)|\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART2 Module */
-
-#define UART3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART3CKEN_Pos)|\
- MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART3 Module */
-
-#define CAN0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CAN0CKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */
-
-#define OTG_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_OTGCKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< OTG Module */
-
-#define USBD_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_USBDCKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBD Module */
-
-#define EADC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_EADCCKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< EADC Module */
-
-
-//APBCLK1
-#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC0CKEN_Pos) |\
- MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
- MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< SC0 Module */
-
-#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_DACCKEN_Pos) |\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */
-
-#define PWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM0CKEN_Pos)|\
- MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 0)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM0 Module */
-
-#define PWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM1CKEN_Pos)|\
- MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 1)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM1 Module */
-
-#define TK_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_TKCKEN_Pos)|\
- MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
- MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TK Module */
-
-
-/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
- @{
-*/
-
-
-/**
- * @brief Get PLL clock frequency
- * @param None
- * @return PLL frequency
- * @details This function get PLL frequency. The frequency unit is Hz.
- */
-__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
-{
- uint32_t u32PllFreq = 0, u32PllReg;
- uint32_t u32FIN, u32NF, u32NR, u32NO;
- uint8_t au8NoTbl[4] = {1, 2, 2, 4};
-
- u32PllReg = CLK->PLLCTL;
-
- if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
- return 0; /* PLL is in power down mode or fix low */
-
- if(u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
- u32FIN = __HIRC; /* PLL source clock from HIRC */
- else
- u32FIN = __HXT; /* PLL source clock from HXT */
-
- if(u32PllReg & CLK_PLLCTL_BP_Msk)
- return u32FIN; /* PLL is in bypass mode */
-
- /* PLL is output enabled in normal work mode */
- u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
- u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
- u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
-
- /* u32FIN is shifted 2 bits to avoid overflow */
- u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
-
- return u32PllFreq;
-}
-
-/**
- * @brief This function execute delay function.
- * @param us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
- * 72MHz => 233016us, 50MHz => 335544us,
- 48MHz => 349525us, 28MHz => 699050us ...
- * @return None
- * @details Use the SysTick to generate the delay time and the unit is in us.
- * The SysTick clock source is from HCLK, i.e the same as system core clock.
- */
-__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
-{
- SysTick->LOAD = us * CyclesPerUs;
- SysTick->VAL = (0x00);
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-
- /* Waiting for down-count to zero */
- while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
-
- /* Disable SysTick counter */
- SysTick->CTRL = 0;
-}
-
-
-void CLK_DisableCKO(void);
-void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
-void CLK_PowerDown(void);
-void CLK_Idle(void);
-uint32_t CLK_GetHXTFreq(void);
-uint32_t CLK_GetLXTFreq(void);
-uint32_t CLK_GetHCLKFreq(void);
-uint32_t CLK_GetPCLK0Freq(void);
-uint32_t CLK_GetPCLK1Freq(void);
-uint32_t CLK_GetCPUFreq(void);
-uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
-void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
-void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
-void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
-void CLK_EnableXtalRC(uint32_t u32ClkMask);
-void CLK_DisableXtalRC(uint32_t u32ClkMask);
-void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
-void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
-uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
-void CLK_DisablePLL(void);
-uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
-void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
-void CLK_DisableSysTick(void);
-
-
-
-/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group CLK_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__CLK_H__
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_crc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/**************************************************************************//**
- * @file crc.c
- * @version V3.00
- * $Revision: 7 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series CRC driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup CRC_Driver CRC Driver
- @{
-*/
-
-/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
- @{
-*/
-
-/**
- * @brief CRC Open
- *
- * @param[in] u32Mode CRC operation polynomial mode. Valid values are:
- * - \ref CRC_CCITT
- * - \ref CRC_8
- * - \ref CRC_16
- * - \ref CRC_32
- * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
- * - \ref CRC_CHECKSUM_COM
- * - \ref CRC_CHECKSUM_RVS
- * - \ref CRC_WDATA_COM
- * - \ref CRC_WDATA_RVS
- * @param[in] u32Seed Seed value.
- * @param[in] u32DataLen CPU Write Data Length. Valid values are:
- * - \ref CRC_CPU_WDATA_8
- * - \ref CRC_CPU_WDATA_16
- * - \ref CRC_CPU_WDATA_32
- *
- * @return None
- *
- * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
- * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
- */
-void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
-{
- CRC->SEED = u32Seed;
- CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
-
- /* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
- CRC->CTL |= CRC_CTL_CRCRST_Msk;
-}
-
-/**
- * @brief Get CRC Checksum
- *
- * @param[in] None
- *
- * @return Checksum Result
- *
- * @details This macro gets the CRC checksum result by current CRC polynomial mode.
- */
-uint32_t CRC_GetChecksum(void)
-{
- switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
- {
- case CRC_CCITT:
- case CRC_16:
- return (CRC->CHECKSUM & 0xFFFF);
-
- case CRC_32:
- return (CRC->CHECKSUM);
-
- case CRC_8:
- return (CRC->CHECKSUM & 0xFF);
-
- default:
- return 0;
- }
-}
-
-/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group CRC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_crc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,112 +0,0 @@
-/**************************************************************************//**
- * @file crc.h
- * @version V3.00
- * $Revision: 6 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series CRC driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __CRC_H__
-#define __CRC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup CRC_Driver CRC Driver
- @{
-*/
-
-/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* CRC Polynomial Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CRC_CCITT 0x00000000UL /*!<CRC Polynomial Mode - CCITT */
-#define CRC_8 0x40000000UL /*!<CRC Polynomial Mode - CRC8 */
-#define CRC_16 0x80000000UL /*!<CRC Polynomial Mode - CRC16 */
-#define CRC_32 0xC0000000UL /*!<CRC Polynomial Mode - CRC32 */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Checksum, Write data Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CRC_CHECKSUM_COM 0x08000000UL /*!<CRC Checksum Complement */
-#define CRC_CHECKSUM_RVS 0x02000000UL /*!<CRC Checksum Reverse */
-#define CRC_WDATA_COM 0x04000000UL /*!<CRC Write Data Complement */
-#define CRC_WDATA_RVS 0x01000000UL /*!<CRC Write Data Reverse */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CPU Write Data Length Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CRC_CPU_WDATA_8 0x00000000UL /*!<CRC CPU Write Data length is 8-bit */
-#define CRC_CPU_WDATA_16 0x10000000UL /*!<CRC CPU Write Data length is 16-bit */
-#define CRC_CPU_WDATA_32 0x20000000UL /*!<CRC CPU Write Data length is 32-bit */
-
-/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
- @{
-*/
-
-/**
- * @brief Set CRC Seed Value
- *
- * @param[in] u32Seed Seed value
- *
- * @return None
- *
- * @details This macro is used to set CRC seed value.
- *
- * @note User must to perform CRC_RST(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
- * to CRC controller.
- */
-#define CRC_SET_SEED(u32Seed) { CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CRCRST_Msk; }
-
-/**
- * @brief Get CRC Seed Value
- *
- * @param None
- *
- * @return CRC seed value
- *
- * @details This macro gets the current CRC seed value.
- */
-#define CRC_GET_SEED() (CRC->SEED)
-
-/**
- * @brief CRC Write Data
- *
- * @param[in] u32Data Write data
- *
- * @return None
- *
- * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
- */
-#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
-
-void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
-uint32_t CRC_GetChecksum(void);
-
-/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group CRC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__CRC_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,94 +0,0 @@
-/**************************************************************************//**
- * @file dac.c
- * @version V2.00
- * $Revision: 8 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series DAC driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup DAC_Driver DAC Driver
- @{
-*/
-
-/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
- @{
-*/
-
-/**
- * @brief This function make DAC module be ready to convert.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @param[in] u32TrgSrc Decides the trigger source. Valid values are:
- * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger
- * - \ref DAC_SOFTWARE_TRIGGER :Software trigger
- * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger
- * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger
- * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger
- * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger
- * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger
- * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger
- * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger
- * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger
- * - \ref DAC_PWM0_TRIGGER :PWM0 trigger
- * - \ref DAC_PWM1_TRIGGER :PWM1 trigger
- * @return None
- * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
- * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
- * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
- * external STDAC pin, timer event, or PWM timer event.
- */
-void DAC_Open(DAC_T *dac,
- uint32_t u32Ch,
- uint32_t u32TrgSrc)
-{
- dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
-
- dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
-}
-
-/**
- * @brief Disable DAC analog power.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @return None
- * @details Disable DAC analog power for saving power consumption.
- */
-void DAC_Close(DAC_T *dac, uint32_t u32Ch)
-{
- dac->CTL &= (~DAC_CTL_DACEN_Msk);
-}
-
-/**
- * @brief Set delay time for DAC to become stable.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK*1000000) micro seconds.
- * @return Real DAC conversion settling time (micro second).
- * @details For example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x48.
- * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
- */
-float DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
-{
- SystemCoreClockUpdate();
-
- dac->TCTL = ((SystemCoreClock * u32Delay / 1000000) & 0x3FF);
-
- return ((dac->TCTL) * 1000000 / SystemCoreClock);
-}
-
-
-
-/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group DAC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_dac.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,245 +0,0 @@
-/******************************************************************************
- * @file dac.h
- * @version V0.10
- * $Revision: 12 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series DAC driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __DAC_H__
-#define __DAC_H__
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Include related headers */
-/*---------------------------------------------------------------------------------------------------------*/
-#include "M451Series.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup DAC_Driver DAC Driver
- @{
-*/
-
-
-/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* DAC_CTL Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. */
-#define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment */
-
-#define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger */
-#define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger */
-#define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger */
-#define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger */
-#define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger */
-#define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger */
-#define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger */
-#define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger */
-#define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger */
-#define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger */
-#define DAC_PWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM0 trigger */
-#define DAC_PWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM1 trigger */
-
-#define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable */
-#define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable */
-
-
-/*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* DAC Macro Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-/**
- * @brief Start the D/A conversion.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
- */
-#define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
-
-/**
- * @brief Enable DAC data left-aligned.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
- */
-#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
-
-/**
- * @brief Enable DAC data right-aligned.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
- */
-#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
-
-/**
- * @brief Enable output voltage buffer.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
- * drive external loads directly without having to add an external operational amplifier.
- */
-#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
-
-/**
- * @brief Disable output voltage buffer.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details This macro is used to disable output voltage buffer.
- */
-#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
-
-/**
- * @brief Enable the interrupt.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @return None
- * @details This macro is used to enable DAC interrupt.
- */
-#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
-
-/**
- * @brief Disable the interrupt.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @return None
- * @details This macro is used to disable DAC interrupt.
- */
-#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
-
-/**
- * @brief Enable DMA under-run interrupt.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details This macro is used to enable DMA under-run interrupt.
- */
-#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
-
-/**
- * @brief Disable DMA under-run interrupt.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details This macro is used to disable DMA under-run interrupt.
- */
-#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
-
-/**
- * @brief Enable PDMA mode.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
- */
-#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
-
-/**
- * @brief Disable PDMA mode.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details This macro is used to disable DMA mode.
- */
-#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
-
-/**
- * @brief Write data for conversion.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
- * @return None
- * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
- * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
- */
-#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
-
-/**
- * @brief Read DAC 12-bit holding data.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @return Return DAC 12-bit holding data.
- * @details This macro is used to read DAC_DAT register.
- */
-#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
-
-/**
- * @brief Get the busy state of DAC.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @retval 0 Idle state.
- * @retval 1 Busy state.
- * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
- */
-#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
-
-/**
- * @brief Get the interrupt flag.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @retval 0 DAC is in conversion state.
- * @retval 1 DAC conversion finish.
- * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
- */
-#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
-
-/**
- * @brief Get the DMA under-run flag.
- * @param[in] dac Base address of DAC module.
- * @retval 0 No DMA under-run error condition occurred.
- * @retval 1 DMA under-run error condition occurred.
- * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
- */
-#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
-
-/**
- * @brief This macro clear the interrupt status bit.
- * @param[in] dac Base address of DAC module.
- * @param[in] u32Ch Not used in M451 Series DAC.
- * @return None
- * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
- */
-#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
-
-/**
- * @brief This macro clear the DMA under-run flag.
- * @param[in] dac Base address of DAC module.
- * @return None
- * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
- */
-#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
-
-void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
-void DAC_Close(DAC_T *dac, uint32_t u32Ch);
-float DAC_SetDelayTime(DAC_T *dac, uint32_t u16Delay);
-
-/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group DAC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__DAC_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_eadc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,159 +0,0 @@
-/**************************************************************************//**
- * @file eadc.c
- * @version V2.00
- * $Revision: 8 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series EADC driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup EADC_Driver EADC Driver
- @{
-*/
-
-/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
- @{
-*/
-
-/**
- * @brief This function make EADC_module be ready to convert.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32InputMode Decides the input mode.
- * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode.
- * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type.
- * @return None
- * @details This function is used to set analog input mode and enable A/D Converter.
- * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
- * @note
- */
-void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
-{
- eadc->CTL &= (~EADC_CTL_DIFFEN_Msk);
-
- eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
-}
-
-/**
- * @brief Disable EADC_module.
- * @param[in] eadc The pointer of the specified EADC module..
- * @return None
- * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
- */
-void EADC_Close(EADC_T *eadc)
-{
- eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
-}
-
-/**
- * @brief Configure the sample control logic module.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
- * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
- * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
- * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger
- * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger
- * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger
- * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger
- * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger
- * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
- * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
- * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
- * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
- * - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger
- * - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger
- * - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger
- * - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger
- * - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger
- * - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger
- * - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger
- * - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger
- * - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger
- * - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger
- * - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger
- * - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger
- * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
- * @return None
- * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
- * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
- */
-void EADC_ConfigSampleModule(EADC_T *eadc, \
- uint32_t u32ModuleNum, \
- uint32_t u32TriggerSrc, \
- uint32_t u32Channel)
-{
- eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
- eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
-}
-
-
-/**
- * @brief Set trigger delay time.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
- * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
- * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
- * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1
- * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2
- * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4
- * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16
- * @return None
- * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
- * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
- */
-void EADC_SetTriggerDelayTime(EADC_T *eadc, \
- uint32_t u32ModuleNum, \
- uint32_t u32TriggerDelayTime, \
- uint32_t u32DelayClockDivider)
-{
- eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
- eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
-}
-
-/**
- * @brief Set ADC internal sample time.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32SampleTime Decides the internal sampling time, the range is from 1~8 ADC clock. Valid value are from 1 to 8.
- * @return None
- * @details When A/D operation at high ADC clock rate, the sampling time of analog input voltage may not enough
- * if the analog channel has heavy loading to cause fully charge time is longer.
- * User can set SMPTSEL (EADC_CTL[18:16]) to select the sampling cycle in ADC.
- */
-void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime)
-{
- eadc->CTL &= ~EADC_CTL_SMPTSEL_Msk;
-
- eadc->CTL |= (u32SampleTime - 1) << EADC_CTL_SMPTSEL_Pos;
-
-}
-
-/**
- * @brief Set ADC extend sample time.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
- * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
- * @return None
- * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
- * user can extend A/D sampling time after trigger source is coming to get enough sampling time.
- */
-void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
-{
- eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
-
- eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
-
-}
-
-/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group EADC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_eadc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,569 +0,0 @@
-/******************************************************************************
- * @file eadc.h
- * @version V0.10
- * $Revision: 18 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series EADC driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __EADC_H__
-#define __EADC_H__
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Include related headers */
-/*---------------------------------------------------------------------------------------------------------*/
-#include "M451Series.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup EADC_Driver EADC Driver
- @{
-*/
-
-/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC_CTL Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode */
-#define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode */
-
-#define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */
-#define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */
-
-#define EADC_CTL_SMPTSEL1 (0UL<<EADC_CTL_SMPTSEL_Pos) /*!< 1 ADC clock sampling time */
-#define EADC_CTL_SMPTSEL2 (1UL<<EADC_CTL_SMPTSEL_Pos) /*!< 2 ADC clock sampling time */
-#define EADC_CTL_SMPTSEL3 (2UL<<EADC_CTL_SMPTSEL_Pos) /*!< 3 ADC clock sampling time */
-#define EADC_CTL_SMPTSEL4 (3UL<<EADC_CTL_SMPTSEL_Pos) /*!< 4 ADC clock sampling time */
-#define EADC_CTL_SMPTSEL5 (4UL<<EADC_CTL_SMPTSEL_Pos) /*!< 5 ADC clock sampling time */
-#define EADC_CTL_SMPTSEL6 (5UL<<EADC_CTL_SMPTSEL_Pos) /*!< 6 ADC clock sampling time */
-#define EADC_CTL_SMPTSEL7 (6UL<<EADC_CTL_SMPTSEL_Pos) /*!< 7 ADC clock sampling time */
-#define EADC_CTL_SMPTSEL8 (7UL<<EADC_CTL_SMPTSEL_Pos) /*!< 8 ADC clock sampling time */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC_SCTL Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */
-#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */
-#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */
-
-#define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */
-#define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger */
-#define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger */
-#define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */
-#define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger */
-#define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger */
-#define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */
-#define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */
-#define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */
-#define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */
-#define EADC_PWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG0 trigger */
-#define EADC_PWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG1 trigger */
-#define EADC_PWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG2 trigger */
-#define EADC_PWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG3 trigger */
-#define EADC_PWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG4 trigger */
-#define EADC_PWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG5 trigger */
-#define EADC_PWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG0 trigger */
-#define EADC_PWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG1 trigger */
-#define EADC_PWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG2 trigger */
-#define EADC_PWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG3 trigger */
-#define EADC_PWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG4 trigger */
-#define EADC_PWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG5 trigger */
-
-#define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */
-#define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */
-#define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */
-#define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC_CMP Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */
-#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */
-#define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */
-#define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */
-#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */
-#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */
-
-/*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
-
-/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC Macro Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-/**
- * @brief A/D Converter Control Circuits Reset.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return None
- * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
- */
-#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADRST_Msk)
-
-/**
- * @brief Enable PDMA transfer.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return None
- * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
- * user can enable this bit to generate a PDMA data transfer request.
- * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
- */
-#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
-
-/**
- * @brief Disable PDMA transfer.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return None
- * @details This macro is used to disable PDMA transfer.
- */
-#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
-
-/**
- * @brief Enable double buffer mode.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
- * @return None
- * @details The ADC controller supports a double buffer mode in sample module 0~3.
- * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
- */
-#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
-
-/**
- * @brief Disable double buffer mode.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
- * @return None
- * @details Sample has one sample result register.
- */
-#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
-
-/**
- * @brief Set ADIFn at A/D end of conversion.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
- * @return None
- * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
- */
-#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
-
-/**
- * @brief Set ADIFn at A/D start of conversion.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
- * @return None
- * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
- */
-#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
-
-/**
- * @brief Enable the interrupt.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
- * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
- * @return None
- * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
- * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
- */
-#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
-
-/**
- * @brief Disable the interrupt.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
- * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
- * @return None
- * @details Specific sample module A/D ADINT0 interrupt function Disabled.
- */
-#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
-
-/**
- * @brief Enable the sample module interrupt.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
- * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
- * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
- * @return None
- * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
- */
-#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
-
-/**
- * @brief Disable the sample module interrupt.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
- * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
- * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
- * @return None
- * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
- */
-#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
-
-/**
- * @brief Set the input mode output format.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32Format Decides the output format. Valid values are:
- * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.
- * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
- * @return None
- * @details The macro is used to set A/D input mode output format.
- */
-#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
-
-/**
- * @brief Start the A/D conversion.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
- * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
- * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
- * @return None
- * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
- */
-#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
-
-/**
- * @brief Cancel the conversion for sample module.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
- * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
- * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
- * @return None
- * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
- */
-#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
-
-/**
- * @brief Get the conversion pending flag.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return Return the conversion pending sample module.
- * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
- * the STPFn (n=0~18) bit is automatically cleared to 0.
- */
-#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
-
-/**
- * @brief Get the conversion data of the user-specified sample module.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
- * @return Return the conversion data of the user-specified sample module.
- * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
- */
-#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
-
-/**
- * @brief Get the data overrun flag of the user-specified sample module.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
- * @return Return the data overrun flag of the user-specified sample module.
- * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
- */
-#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
-
-/**
- * @brief Get the data valid flag of the user-specified sample module.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
- * @return Return the data valid flag of the user-specified sample module.
- * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[1:0]) field to get data overrun status.
- */
-#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
-
-/**
- * @brief Get the double data of the user-specified sample module.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
- * @return Return the double data of the user-specified sample module.
- * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
- */
-#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk)
-
-/**
- * @brief Get the user-specified interrupt flags.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
- * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
- * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
- * @return Return the user-specified interrupt flags.
- * @details This macro is used to get the user-specified interrupt flags.
- */
-#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
-
-/**
- * @brief Get the user-specified sample module overrun flags.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
- * @return Return the user-specified sample module overrun flags.
- * @details This macro is used to get the user-specified sample module overrun flags.
- */
-#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
-
-/**
- * @brief Clear the selected interrupt status bits.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
- * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
- * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
- * @return None
- * @details This macro is used to clear clear the selected interrupt status bits.
- */
-#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
-
-/**
- * @brief Clear the selected sample module overrun status bits.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
- * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
- * @return None
- * @details This macro is used to clear the selected sample module overrun status bits.
- */
-#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
-
-/**
- * @brief Check all sample module A/D result data register overrun flags.
- * @param[in] eadc The pointer of the specified EADC module.
- * @retval 0 None of sample module data register overrun flag is set to 1.
- * @retval 1 Any one of sample module data register overrun flag is set to 1.
- * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
- */
-#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
-
-/**
- * @brief Check all sample module A/D result data register valid flags.
- * @param[in] eadc The pointer of the specified EADC module.
- * @retval 0 None of sample module data register valid flag is set to 1.
- * @retval 1 Any one of sample module data register valid flag is set to 1.
- * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
- */
-#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
-
-/**
- * @brief Check all A/D sample module start of conversion overrun flags.
- * @param[in] eadc The pointer of the specified EADC module.
- * @retval 0 None of sample module event overrun flag is set to 1.
- * @retval 1 Any one of sample module event overrun flag is set to 1.
- * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
- */
-#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
-
-/**
- * @brief Check all A/D interrupt flag overrun bits.
- * @param[in] eadc The pointer of the specified EADC module.
- * @retval 0 None of ADINT interrupt flag is overwritten to 1.
- * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
- * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
- */
-#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
-
-/**
- * @brief Get the busy state of EADC.
- * @param[in] eadc The pointer of the specified EADC module.
- * @retval 0 Idle state.
- * @retval 1 Busy state.
- * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
- */
-#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
-
-/**
- * @brief Configure the comparator 0 and enable it.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
- * @param[in] u32Condition specifies the compare condition. Valid values are:
- * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
- * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
- * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
- * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
- * @return None
- * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
- * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
- * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
- */
-#define EADC_ENABLE_CMP0(eadc,\
- u32ModuleNum,\
- u32Condition,\
- u16CMPData,\
- u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
- (u32Condition) |\
- ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
- (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
- EADC_CMP_ADCMPEN_Msk))
-
-/**
- * @brief Configure the comparator 1 and enable it.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
- * @param[in] u32Condition specifies the compare condition. Valid values are:
- * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
- * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
- * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
- * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
- * @return None
- * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
- * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
- * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
- */
-#define EADC_ENABLE_CMP1(eadc,\
- u32ModuleNum,\
- u32Condition,\
- u16CMPData,\
- u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
- (u32Condition) |\
- ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
- (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
- EADC_CMP_ADCMPEN_Msk))
-
-/**
- * @brief Configure the comparator 2 and enable it.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
- * @param[in] u32Condition specifies the compare condition. Valid values are:
- * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
- * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
- * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
- * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
- * @return None
- * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
- * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
- * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
- */
-#define EADC_ENABLE_CMP2(eadc,\
- u32ModuleNum,\
- u32Condition,\
- u16CMPData,\
- u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
- (u32Condition) |\
- ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
- (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
- EADC_CMP_ADCMPEN_Msk))
-
-/**
- * @brief Configure the comparator 3 and enable it.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
- * @param[in] u32Condition specifies the compare condition. Valid values are:
- * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
- * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
- * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
- * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
- * @return None
- * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
- * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
- * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
- */
-#define EADC_ENABLE_CMP3(eadc,\
- u32ModuleNum,\
- u32Condition,\
- u16CMPData,\
- u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
- (u32Condition) |\
- ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
- (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
- EADC_CMP_ADCMPEN_Msk))
-
-/**
- * @brief Enable the compare window mode.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
- * @return None
- * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
- */
-#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
-
-/**
- * @brief Disable the compare window mode.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
- * @return None
- * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
- */
-#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
-
-/**
- * @brief Enable the compare interrupt.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
- * @return None
- * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
- * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
- * if ADCMPIE is set to 1, a compare interrupt request is generated.
- */
-#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
-
-/**
- * @brief Disable the compare interrupt.
- * @param[in] eadc The pointer of the specified EADC module.
- * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
- * @return None
- * @details This macro is used to disable the compare interrupt.
- */
-#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
-
-/**
- * @brief Disable comparator 0.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return None
- * @details This macro is used to disable comparator 0.
- */
-#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
-
-/**
- * @brief Disable comparator 1.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return None
- * @details This macro is used to disable comparator 1.
- */
-#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
-
-/**
- * @brief Disable comparator 2.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return None
- * @details This macro is used to disable comparator 2.
- */
-#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
-
-/**
- * @brief Disable comparator 3.
- * @param[in] eadc The pointer of the specified EADC module.
- * @return None
- * @details This macro is used to disable comparator 3.
- */
-#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define EADC functions prototype */
-/*---------------------------------------------------------------------------------------------------------*/
-void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
-void EADC_Close(EADC_T *eadc);
-void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel);
-void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
-void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime);
-void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
-
-/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group EADC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__EADC_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_ebi.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,178 +0,0 @@
-/**************************************************************************//**
- * @file ebi.c
- * @version V3.00
- * $Revision: 9 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series EBI driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup EBI_Driver EBI Driver
- @{
-*/
-
-/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
- @{
-*/
-
-/**
- * @brief Initialize EBI for specify Bank
- *
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- * @param[in] u32DataWidth Data bus width. Valid values are:
- * - \ref EBI_BUSWIDTH_8BIT
- * - \ref EBI_BUSWIDTH_16BIT
- * @param[in] u32TimingClass Default timing configuration. Valid values are:
- * - \ref EBI_TIMING_FASTEST
- * - \ref EBI_TIMING_VERYFAST
- * - \ref EBI_TIMING_FAST
- * - \ref EBI_TIMING_NORMAL
- * - \ref EBI_TIMING_SLOW
- * - \ref EBI_TIMING_VERYSLOW
- * - \ref EBI_TIMING_SLOWEST
- * @param[in] u32BusMode Enable EBI separate mode. This parameter is current not used.
- * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
- * - \ref EBI_CS_ACTIVE_HIGH
- * - \ref EBI_CS_ACTIVE_LOW
- *
- * @return none
- *
- * @details This function is used to open specify EBI bank with different bus width, timing setting and \n
- * active level of CS pin to access EBI device.
- * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
- */
-void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
-{
- volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
- volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
-
- if(u32DataWidth == EBI_BUSWIDTH_8BIT)
- *pu32EBICTL &= ~EBI_CTL0_DW16_Msk;
- else
- *pu32EBICTL |= EBI_CTL0_DW16_Msk;
-
- switch(u32TimingClass)
- {
- case EBI_TIMING_FASTEST:
- *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
- (EBI_MCLKDIV_1 << EBI_CTL0_MCLKDIV_Pos) |
- (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk;
- *pu32EBITCTL = 0x0;
- break;
-
- case EBI_TIMING_VERYFAST:
- *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
- (EBI_MCLKDIV_1 << EBI_CTL0_MCLKDIV_Pos) |
- (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
- (0x3 << EBI_CTL0_TALE_Pos) ;
- *pu32EBITCTL = 0x03003318;
- break;
-
- case EBI_TIMING_FAST:
- *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
- (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
- (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk;
- *pu32EBITCTL = 0x0;
- break;
-
- case EBI_TIMING_NORMAL:
- *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
- (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
- (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
- (0x3 << EBI_CTL0_TALE_Pos) ;
- *pu32EBITCTL = 0x03003318;
- break;
-
- case EBI_TIMING_SLOW:
- *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
- (EBI_MCLKDIV_2 << EBI_CTL0_MCLKDIV_Pos) |
- (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
- (0x7 << EBI_CTL0_TALE_Pos) ;
- *pu32EBITCTL = 0x07007738;
- break;
-
- case EBI_TIMING_VERYSLOW:
- *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
- (EBI_MCLKDIV_4 << EBI_CTL0_MCLKDIV_Pos) |
- (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
- (0x7 << EBI_CTL0_TALE_Pos) ;
- *pu32EBITCTL = 0x07007738;
- break;
-
- case EBI_TIMING_SLOWEST:
- *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL0_MCLKDIV_Msk | EBI_CTL0_TALE_Msk)) |
- (EBI_MCLKDIV_8 << EBI_CTL0_MCLKDIV_Pos) |
- (u32CSActiveLevel << EBI_CTL0_CSPOLINV_Pos) | EBI_CTL0_EN_Msk |
- (0x7 << EBI_CTL0_TALE_Pos) ;
- *pu32EBITCTL = 0x07007738;
- break;
-
- default:
- *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
- break;
- }
-}
-
-/**
- * @brief Disable EBI on specify Bank
- *
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- *
- * @return none
- *
- * @details This function is used to close specify EBI function.
- */
-void EBI_Close(uint32_t u32Bank)
-{
- volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
-
- *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
-}
-
-/**
- * @brief Set EBI Bus Timing for specify Bank
- *
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
- * @param[in] u32MclkDiv Divider for MCLK. Valid values are:
- * - \ref EBI_MCLKDIV_1
- * - \ref EBI_MCLKDIV_2
- * - \ref EBI_MCLKDIV_4
- * - \ref EBI_MCLKDIV_8
- * - \ref EBI_MCLKDIV_16
- * - \ref EBI_MCLKDIV_32
- *
- * @return none
- *
- * @details This function is used to configure specify EBI bus timing for access EBI device.
- */
-void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
-{
- volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
- volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
-
- *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL0_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL0_MCLKDIV_Pos);
- *pu32EBITCTL = u32TimingConfig;
-}
-
-/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group EBI_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_ebi.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,235 +0,0 @@
-/**************************************************************************//**
- * @file ebi.h
- * @version V3.00
- * $Revision: 8 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series EBI driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __EBI_H__
-#define __EBI_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup EBI_Driver EBI Driver
- @{
-*/
-
-/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* Miscellaneous Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address */
-#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address */
-#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Constants for EBI bank number */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EBI_BANK0 0 /*!< EBI bank 0 */
-#define EBI_BANK1 1 /*!< EBI bank 1 */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Constants for EBI data bus width */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EBI_BUSWIDTH_8BIT 8 /*!< EBI bus width is 8-bit */
-#define EBI_BUSWIDTH_16BIT 16 /*!< EBI bus width is 16-bit */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Constants for EBI CS Active Level */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EBI_CS_ACTIVE_LOW 0 /*!< EBI CS active level is low */
-#define EBI_CS_ACTIVE_HIGH 1 /*!< EBI CS active level is high */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Constants for EBI MCLK divider and Timing */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 */
-#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 */
-#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 */
-#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 */
-#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 */
-#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 */
-
-#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest */
-#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast */
-#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast */
-#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal */
-#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow */
-#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow */
-#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest */
-
-/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
- @{
-*/
-
-/**
- * @brief Read 8-bit data on EBI bank0
- *
- * @param[in] u32Addr The data address on EBI bank0.
- *
- * @return 8-bit Data
- *
- * @details This macro is used to read 8-bit data from specify address on EBI bank0.
- */
-#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
-
-/**
- * @brief Write 8-bit data to EBI bank0
- *
- * @param[in] u32Addr The data address on EBI bank0.
- * @param[in] u32Data Specify data to be written.
- *
- * @return None
- *
- * @details This macro is used to write 8-bit data to specify address on EBI bank0.
- */
-#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
-
-/**
- * @brief Read 16-bit data on EBI bank0
- *
- * @param[in] u32Addr The data address on EBI bank0.
- *
- * @return 16-bit Data
- *
- * @details This macro is used to read 16-bit data from specify address on EBI bank0.
- */
-#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
-
-/**
- * @brief Write 16-bit data to EBI bank0
- *
- * @param[in] u32Addr The data address on EBI bank0.
- * @param[in] u32Data Specify data to be written.
- *
- * @return None
- *
- * @details This macro is used to write 16-bit data to specify address on EBI bank0.
- */
-#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
-
-/**
- * @brief Read 32-bit data on EBI bank0
- *
- * @param[in] u32Addr The data address on EBI bank0.
- *
- * @return 32-bit Data
- *
- * @details This macro is used to read 32-bit data from specify address on EBI bank0.
- */
-#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
-
-/**
- * @brief Write 32-bit data to EBI bank0
- *
- * @param[in] u32Addr The data address on EBI bank0.
- * @param[in] u32Data Specify data to be written.
- *
- * @return None
- *
- * @details This macro is used to write 32-bit data to specify address on EBI bank0.
- */
-#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
-
-/**
- * @brief Read 8-bit data on EBI bank1
- *
- * @param[in] u32Addr The data address on EBI bank1.
- *
- * @return 8-bit Data
- *
- * @details This macro is used to read 8-bit data from specify address on EBI bank1.
- */
-#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
-
-/**
- * @brief Write 8-bit data to EBI bank1
- *
- * @param[in] u32Addr The data address on EBI bank1.
- * @param[in] u32Data Specify data to be written.
- *
- * @return None
- *
- * @details This macro is used to write 8-bit data to specify address on EBI bank1.
- */
-#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
-
-/**
- * @brief Read 16-bit data on EBI bank1
- *
- * @param[in] u32Addr The data address on EBI bank1.
- *
- * @return 16-bit Data
- *
- * @details This macro is used to read 16-bit data from specify address on EBI bank1.
- */
-#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
-
-/**
- * @brief Write 16-bit data to EBI bank1
- *
- * @param[in] u32Addr The data address on EBI bank1.
- * @param[in] u32Data Specify data to be written.
- *
- * @return None
- *
- * @details This macro is used to write 16-bit data to specify address on EBI bank1.
- */
-#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
-
-/**
- * @brief Read 32-bit data on EBI bank1
- *
- * @param[in] u32Addr The data address on EBI bank1.
- *
- * @return 32-bit Data
- *
- * @details This macro is used to read 32-bit data from specify address on EBI bank1.
- */
-#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
-
-/**
- * @brief Write 32-bit data to EBI bank1
- *
- * @param[in] u32Addr The data address on EBI bank1.
- * @param[in] u32Data Specify data to be written.
- *
- * @return None
- *
- * @details This macro is used to write 32-bit data to specify address on EBI bank1.
- */
-#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
-
-void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
-void EBI_Close(uint32_t u32Bank);
-void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
-
-/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group EBI_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__EBI_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_fmc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,320 +0,0 @@
-/**************************************************************************//**
- * @file fmc.c
- * @version V3.00
- * $Revision: 7 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series FMC driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-
-//* Includes ------------------------------------------------------------------*/
-#include <stdio.h>
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup FMC_Driver FMC Driver
- @{
-*/
-
-
-/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
- @{
-*/
-
-
-/**
- * @brief Set boot source from LDROM or APROM after next software reset
- *
- * @param[in] i32BootSrc
- * 1: Boot from LDROM,
- * 0: Boot from APROM
- *
- * @return None
- *
- * @details This function is used to switch APROM boot or LDROM boot. User need to call
- * FMC_SetBootSource to select boot source first, then use CPU reset or
- * System Reset Request to reset system.
- *
- */
-void FMC_SetBootSource(int32_t i32BootSrc)
-{
- if(i32BootSrc)
- FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
- else
- FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
-}
-
-
-/**
- * @brief Disable ISP Functions
- *
- * @param None
- *
- * @return None
- *
- * @details This function will clear ISPEN bit of ISPCTL to disable ISP function
- *
- */
-void FMC_Close(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
-}
-
-
-/**
- * @brief Disable APROM update function
- *
- * @param None
- *
- * @return None
- *
- * @details Disable APROM update function will forbid APROM programming when boot form APROM.
- * APROM update is default to be disable.
- *
- */
-void FMC_DisableAPUpdate(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk;
-}
-
-
-/**
- * @brief Disable User Configuration update function
- *
- * @param None
- *
- * @return None
- *
- * @details Disable User Configuration update function will forbid User Configuration programming.
- * User Configuration update is default to be disable.
- */
-void FMC_DisableConfigUpdate(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk;
-}
-
-
-/**
- * @brief Disable LDROM update function
- *
- * @param None
- *
- * @return None
-
- * @details Disable LDROM update function will forbid LDROM programming.
- * LDROM update is default to be disable.
- */
-void FMC_DisableLDUpdate(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk;
-}
-
-
-/**
- * @brief Enable APROM update function
- *
- * @param None
- *
- * @return None
- *
- * @details Enable APROM to be able to program when boot from APROM.
- *
- */
-void FMC_EnableAPUpdate(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk;
-}
-
-
-/**
- * @brief Enable User Configuration update function
- *
- * @param None
- *
- * @return None
- *
- * @details Enable User Configuration to be able to program.
- *
- */
-void FMC_EnableConfigUpdate(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk;
-}
-
-
-/**
- * @brief Enable LDROM update function
- *
- * @param None
- *
- * @return None
- *
- * @details Enable LDROM to be able to program.
- *
- */
-void FMC_EnableLDUpdate(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk;
-}
-
-
-/**
- * @brief Get the current boot source
- *
- * @param None
- *
- * @retval 0 This chip is currently booting from APROM
- * @retval 1 This chip is currently booting from LDROM
- *
- * @note This function only show the boot source.
- * User need to read ISPSTA register to know if IAP mode supported or not in relative boot.
- */
-int32_t FMC_GetBootSource(void)
-{
- if(FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
- return 1;
- else
- return 0;
-}
-
-
-/**
- * @brief Enable FMC ISP function
- *
- * @param None
- *
- * @return None
- *
- * @details ISPEN bit of ISPCTL must be set before we can use ISP commands.
- * Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions.
- *
- * @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions.
- *
- */
-void FMC_Open(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
-}
-
-/**
- * @brief Get the base address of Data Flash if enabled.
- *
- * @param None
- *
- * @return The base address of Data Flash
- *
- * @details This function is used to return the base address of Data Flash.
- *
- */
-uint32_t FMC_ReadDataFlashBaseAddr(void)
-{
- return FMC->DFBA;
-}
-
-
-/**
- * @brief Read the User Configuration words.
- *
- * @param[out] u32Config The word buffer to store the User Configuration data.
- * @param[in] u32Count The word count to be read.
- *
- * @retval 0 Success
- * @retval -1 Failed
- *
- * @details This function is used to read the settings of user configuration.
- * if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config.
- * if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned.
- */
-int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
-{
- int32_t i;
-
- for(i = 0; i < u32Count; i++)
- u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4);
-
- return 0;
-}
-
-
-/**
- * @brief Write User Configuration
- *
- * @param[in] u32Config The word buffer to store the User Configuration data.
- * @param[in] u32Count The word count to program to User Configuration.
- *
- * @retval 0 Success
- * @retval -1 Failed
- *
- * @details User must enable User Configuration update before writing it.
- * User must erase User Configuration before writing it.
- * User Configuration is also be page erase. User needs to backup necessary data
- * before erase User Configuration.
- */
-int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
-{
- int32_t i;
-
- for(i = 0; i < u32Count; i++)
- {
- FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]);
- if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i])
- return -1;
- }
-
- return 0;
-}
-
-/**
- * @brief Enable Flash Access Frequency Optimization Mode
- *
- * @param[in] u32Mode Optimize flash access cycle mode
- * - \ref FMC_FTCTL_OPTIMIZE_DISABLE
- * - \ref FMC_FTCTL_OPTIMIZE_12MHZ
- * - \ref FMC_FTCTL_OPTIMIZE_36MHZ
- * - \ref FMC_FTCTL_OPTIMIZE_60MHZ
- * - \ref FMC_FTCTL_OPTIMIZE_72MHZ
- *
- * @return None
- *
- * @details This function will set FOM bit fields of FTCTL register to set flash access frequency optimization mode.
- *
- * @note The flash optimization mode (FOM) bits are write protect.
- *
- */
-void FMC_EnableFreqOptimizeMode(uint32_t u32Mode)
-{
- FMC->FTCTL &= ~FMC_FTCTL_FOM_Msk;
- FMC->FTCTL |= (u32Mode << FMC_FTCTL_FOM_Pos);
-}
-
-/**
- * @brief Disable Flash Access Frequency Optimization Mode
- *
- * @param None
- *
- * @return None
- *
- * @details This function will clear FOM bit fields of FTCTL register to disable flash access frequency optimization mode.
- *
- * @note The flash optimization mode (FOM) bits are write protect.
- *
- */
-void FMC_DisableFreqOptimizeMode(void)
-{
- FMC->FTCTL &= ~FMC_FTCTL_FOM_Msk;
-}
-
-/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group FMC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
-
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_fmc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,605 +0,0 @@
-/**************************************************************************//**
- * @file FMC.h
- * @version V2.1
- * $Revision: 19 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 Series Flash Memory Controller Driver Header File
- *
- * @note
- * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __FMC_H__
-#define __FMC_H__
-
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup FMC_Driver FMC Driver
- @{
-*/
-
-/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Global constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define ISBEN 0
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define Base Address */
-/*---------------------------------------------------------------------------------------------------------*/
-#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
-#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
-#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM Base Address */
-#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
-
-#define FMC_CONFIG0_ADDR (FMC_CONFIG_BASE) /*!< CONFIG 0 Address */
-#define FMC_CONFIG1_ADDR (FMC_CONFIG_BASE + 4) /*!< CONFIG 1 Address */
-
-
-#define FMC_FLASH_PAGE_SIZE 0x800 /*!< Flash Page Size (2048 Bytes) */
-#define FMC_LDROM_SIZE 0x1000 /*!< LDROM Size (4 kBytes) */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* ISPCTL constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define FMC_ISPCTL_BS_LDROM 0x2 /*!< ISPCTL setting to select to boot from LDROM */
-#define FMC_ISPCTL_BS_APROM 0x0 /*!< ISPCTL setting to select to boot from APROM */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* ISPCMD constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */
-#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: 32-bit Program Flash */
-#define FMC_ISPCMD_WRITE_8 0x61 /*!< ISP Command: 64-bit program Flash */
-#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
-#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
-#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
-#define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID */
-#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Set vector mapping */
-#define FMC_ISPCMD_CHECKSUM 0x0D /*!< ISP Command: Read Checksum */
-#define FMC_ISPCMD_CAL_CHECKSUM 0x2D /*!< ISP Command: Run Check Calculation */
-#define FMC_ISPCMD_MULTI_PROG 0x27 /*!< ISP Command: Flash Multi-Word Program */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* FTCTL constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define FMC_FTCTL_OPTIMIZE_DISABLE 0x00 /*!< Frequency Optimize Mode disable */
-#define FMC_FTCTL_OPTIMIZE_12MHZ 0x01 /*!< Frequency Optimize Mode <= 12Mhz */
-#define FMC_FTCTL_OPTIMIZE_36MHZ 0x02 /*!< Frequency Optimize Mode <= 36Mhz */
-#define FMC_FTCTL_OPTIMIZE_60MHZ 0x04 /*!< Frequency Optimize Mode <= 60Mhz */
-#define FMC_FTCTL_OPTIMIZE_72MHZ 0x05 /*!< Frequency Optimize Mode <= 72Mhz */
-
-/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
-
-/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* FMC Macro Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-/**
- * @brief Enable ISP Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function.
- *
- */
-#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */
-
-/**
- * @brief Disable ISP Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function.
- *
- */
-#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */
-
-/**
- * @brief Enable LDROM Update Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function.
- * User needs to set LDUEN bit before they can update LDROM.
- *
- */
-#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */
-
-/**
- * @brief Disable LDROM Update Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.
- *
- */
-#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */
-
-/**
- * @brief Enable User Configuration Update Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.
- * User needs to set CFGUEN bit before they can update User Configuration area.
- *
- */
-#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */
-
-/**
- * @brief Disable User Configuration Update Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.
- *
- */
-#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
-
-
-/**
- * @brief Enable APROM Update Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function.
- * User needs to set APUEN bit before they can update APROM in APROM boot mode.
- *
- */
-#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */
-
-/**
- * @brief Disable APROM Update Function
- *
- * @param None
- *
- * @return None
- *
- * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function.
- *
- */
-#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */
-
-/**
- * @brief Next Booting Selection function
- *
- * @param[in] x Booting from APROM(0)/LDROM(1)
- *
- * @return None
- *
- * @details This function will set MCU next booting from LDROM/APROM.
- *
- * @note When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set.
- *
- */
-#define FMC_SELECT_NEXT_BOOT(x) (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */
-
-/**
- * @brief Get MCU Booting Status
- *
- * @param None
- *
- * @return None
- *
- * @details This function will get status of chip next booting from LDROM/APROM.
- *
- */
-#define FMC_GET_BOOT_STATUS() ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* inline functions */
-/*---------------------------------------------------------------------------------------------------------*/
-/**
- * @brief Program 32-bit data into specified address of flash
- *
- * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
- * @param[in] u32Data 32-bit Data to program
- *
- * @return None
- *
- * @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG.
- * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
- *
- */
-static __INLINE void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
-{
- FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
- FMC->ISPADDR = u32Addr;
- FMC->ISPDAT = u32Data;
- FMC->ISPTRG = 0x1;
-#if ISBEN
- __ISB();
-#endif
- while(FMC->ISPTRG);
-}
-
-/**
- * @brief Program 64-bit data into specified address of flash
- *
- * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
- * @param[in] u32Data0 32-bit Data to program
- * @param[in] u32Data1 32-bit Data to program
- *
- * @return None
- *
- * @details To program two words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
- * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
- *
- */
-static __INLINE void FMC_Write8(uint32_t u32Addr, uint32_t u32Data0, uint32_t u32Data1)
-{
- FMC->ISPCMD = FMC_ISPCMD_WRITE_8;
- FMC->ISPADDR = u32Addr;
- FMC->MPDAT0 = u32Data0;
- FMC->MPDAT1 = u32Data1;
- FMC->ISPTRG = 0x1;
-#if ISBEN
- __ISB();
-#endif
- while(FMC->ISPTRG);
-}
-
-
-/**
- * @brief Read 32-bit Data from specified address of flash
- *
- * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
- *
- * @return The data of specified address
- *
- * @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG.
- *
- */
-static __INLINE uint32_t FMC_Read(uint32_t u32Addr)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ;
- FMC->ISPADDR = u32Addr;
- FMC->ISPDAT = 0;
- FMC->ISPTRG = 0x1;
-#if ISBEN
- __ISB();
-#endif
- while(FMC->ISPTRG);
-
- return FMC->ISPDAT;
-}
-
-/**
- * @brief Flash page erase
- *
- * @param[in] u32Addr Flash address including APROM, LDROM, Data Flash, and CONFIG
- *
- * @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG.
- * The page size is 2048 bytes.
- *
- * @retval 0 Success
- * @retval -1 Erase failed
- *
- */
-static __INLINE int32_t FMC_Erase(uint32_t u32Addr)
-{
- FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
- FMC->ISPADDR = u32Addr;
- FMC->ISPTRG = 0x1;
-#if ISBEN
- __ISB();
-#endif
- while(FMC->ISPTRG);
-
- /* Check ISPFF flag to know whether erase OK or fail. */
- if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
- {
- FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
- return -1;
- }
- return 0;
-}
-
-/**
- * @brief Read Unique ID
- *
- * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
- *
- * @return The 32-bit unique ID data of specified UID index.
- *
- * @details To read out 96-bit Unique ID.
- *
- */
-static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_UID;
- FMC->ISPADDR = (u8Index << 2);
- FMC->ISPDAT = 0;
- FMC->ISPTRG = 0x1;
-#if ISBEN
- __ISB();
-#endif
- while(FMC->ISPTRG);
-
- return FMC->ISPDAT;
-}
-
-/**
- * @brief Read company ID
- *
- * @param None
- *
- * @return The company ID (32-bit)
- *
- * @details The company ID of Nuvoton is fixed to be 0xDA
- *
- */
-static __INLINE uint32_t FMC_ReadCID(void)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
- FMC->ISPADDR = 0x0; /* Must keep 0x0 when read CID */
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
-#if ISBEN
- __ISB();
-#endif /* To make sure ISP/CPU be Synchronized */
- while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; /* Waiting for ISP Done */
-
- return FMC->ISPDAT;
-}
-
-/**
- * @brief Read product ID
- *
- * @param None
- *
- * @return The product ID (32-bit)
- *
- * @details This function is used to read product ID.
- *
- */
-static __INLINE uint32_t FMC_ReadPID(void)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
- FMC->ISPADDR = 0x04; /* Must keep 0x4 when read PID */
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
-#if ISBEN
- __ISB();
-#endif /* To make sure ISP/CPU be Synchronized */
- while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
-
- return FMC->ISPDAT;
-}
-
-/**
- * @brief To read UCID
- *
- * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
- *
- * @return The UCID of specified index
- *
- * @details This function is used to read unique chip ID (UCID).
- *
- */
-static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
- FMC->ISPADDR = (0x04 * u32Index) + 0x10; /* The UCID is at offset 0x10 with word alignment. */
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
-#if ISBEN
- __ISB();
-#endif /* To make sure ISP/CPU be Synchronized */
- while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
-
- return FMC->ISPDAT;
-}
-
-/**
- * @brief Set vector mapping address
- *
- * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
- *
- * @return To set VECMAP to remap specified page address to 0x0.
- *
- * @details This function is used to set VECMAP to map specified page to vector page (0x0).
- *
- * @note
- * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
- *
- */
-static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
-{
- FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
- FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
- FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
-#if ISBEN
- __ISB();
-#endif /* To make sure ISP/CPU be Synchronized */
- while(FMC->ISPTRG); /* Waiting for ISP Done */
-}
-
-/**
- * @brief Get current vector mapping address.
- *
- * @param None
- *
- * @return The current vector mapping address.
- *
- * @details To get VECMAP value which is the page address for remapping to vector page (0x0).
- *
- * @note
- * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
- *
- */
-static __INLINE uint32_t FMC_GetVECMAP(void)
-{
- return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
-}
-
-/**
- * @brief Get Flash Checksum
- *
- * @param[in] u32Addr Specific flash start address
- * @param[in] i32Size Specific a size of Flash area
- *
- * @return A checksum value of a flash block.
- *
- * @details To get VECMAP value which is the page address for remapping to vector page (0x0).
- *
- */
-static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size)
-{
- FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
- FMC->ISPADDR = u32Addr;
- FMC->ISPDAT = i32Size;
- FMC->ISPTRG = 0x1;
-#if ISBEN
- __ISB();
-#endif
- while(FMC->ISPTRG);
-
- FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
- FMC->ISPTRG = 0x1;
- while(FMC->ISPTRG);
-
- return FMC->ISPDAT;
-}
-
-/**
- * @brief Program Multi-Word data into specified address of flash
- *
- * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
- * @param[in] pu32Buf A data pointer is point to a data buffer start address;
- *
- * @return None
- *
- * @details To program multi-words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
- * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
- *
- */
-static __INLINE void FMC_Write256(uint32_t u32Addr, uint32_t *pu32Buf)
-{
- int32_t i, idx;
- volatile uint32_t *pu32IspData;
- //int32_t i32Err;
-
- //i32Err = 0;
- idx = 0;
- FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG;
- FMC->ISPADDR = u32Addr;
-
-retrigger:
-
- //if(i32Err)
- // printf("idx=%d ISPADDR = 0x%08x\n",idx, FMC->ISPADDR);
-
- FMC->MPDAT0 = pu32Buf[idx + 0];
- FMC->MPDAT1 = pu32Buf[idx + 1];
- FMC->MPDAT2 = pu32Buf[idx + 2];
- FMC->MPDAT3 = pu32Buf[idx + 3];
-
-
-
- FMC->ISPTRG = 0x1;
-
- pu32IspData = &FMC->MPDAT0;
- idx += 4;
-
- for(i = idx; i < 256 / 4; i += 4) // Max data length is 256 bytes (256/4 words)
- {
-
- __set_PRIMASK(1); // Mask interrupt to avoid status check coherence error
- do
- {
- if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
- {
- __set_PRIMASK(0);
- //printf("%d %x\n", i, FMC->MPADDR);
- FMC->ISPADDR = FMC->MPADDR & (~0xful);
- idx = (FMC->ISPADDR - u32Addr) / 4;
- //i32Err = -1;
- goto retrigger;
- }
- }
- while(FMC->MPSTS & (3 << FMC_MPSTS_D0_Pos));
-
- // Update new data for D0
- pu32IspData[0] = pu32Buf[i ];
- pu32IspData[1] = pu32Buf[i + 1];
-
- do
- {
- if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
- {
- __set_PRIMASK(0);
- //printf("%d %x\n", i, FMC->MPADDR);
- FMC->ISPADDR = FMC->MPADDR & (~0xful);
- idx = (FMC->ISPADDR - u32Addr) / 4;
- //i32Err = -1;
- goto retrigger;
- }
- }
- while(FMC->MPSTS & (3 << FMC_MPSTS_D2_Pos));
-
- // Update new data for D2
- pu32IspData[2] = pu32Buf[i + 2];
- pu32IspData[3] = pu32Buf[i + 3];
- __set_PRIMASK(0);
- }
-
- while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk);
-}
-
-void FMC_Open(void);
-void FMC_Close(void);
-void FMC_EnableAPUpdate(void);
-void FMC_DisableAPUpdate(void);
-void FMC_EnableConfigUpdate(void);
-void FMC_DisableConfigUpdate(void);
-void FMC_EnableLDUpdate(void);
-void FMC_DisableLDUpdate(void);
-int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
-int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
-void FMC_SetBootSource(int32_t i32BootSrc);
-int32_t FMC_GetBootSource(void);
-uint32_t FMC_ReadDataFlashBaseAddr(void);
-void FMC_EnableFreqOptimizeMode(uint32_t u32Mode);
-void FMC_DisableFreqOptimizeMode(void);
-/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group FMC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_gpio.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,102 +0,0 @@
-/**************************************************************************//**
- * @file gpio.c
- * @version V3.00
- * $Revision: 6 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series GPIO driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup GPIO_Driver GPIO Driver
- @{
-*/
-
-/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
- @{
-*/
-
-/**
- * @brief Set GPIO operation mode
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD GPIO port.
- * It could be BIT0 ~ BIT14 for PE GPIO port.
- * It could be BIT0 ~ BIT7 for PF GPIO port.
- * @param[in] u32Mode Operation mode. It could be \n
- * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI.
- *
- * @return None
- *
- * @details This function is used to set specified GPIO operation mode.
- */
-void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
-{
- uint32_t i;
-
- for(i = 0; i < GPIO_PIN_MAX; i++)
- {
- if(u32PinMask & (1 << i))
- {
- port->MODE = (port->MODE & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
- }
- }
-}
-
-/**
- * @brief Enable GPIO interrupt
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32Pin The pin of specified GPIO port.
- * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
- * It could be 0 ~ 14 for PE GPIO port.
- * It could be 0 ~ 7 for PF GPIO port.
- * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
- * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
-{
- port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
- port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
-}
-
-
-/**
- * @brief Disable GPIO interrupt
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32Pin The pin of specified GPIO port.
- * It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
- * It could be 0 ~ 14 for PE GPIO port.
- * It could be 0 ~ 7 for PF GPIO port.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
-{
- port->INTTYPE &= ~(1UL << u32Pin);
- port->INTEN &= ~((0x00010001UL) << u32Pin);
-}
-
-
-/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group GPIO_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_gpio.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,439 +0,0 @@
-/**************************************************************************//**
- * @file GPIO.h
- * @version V3.00
- * $Revision: 21 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series GPIO driver header file
- *
- * @note
- * Copyright (C) 2011~2015 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup GPIO_Driver GPIO Driver
- @{
-*/
-
-/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
- @{
-*/
-
-
-#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* GPIO_MODE Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
-#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
-#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
-#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* GPIO Interrupt Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
-#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
-#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
-#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
-#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* GPIO_INTTYPE Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */
-#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* GPIO_DBCTL Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */
-#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
-
-#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
-#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */
-
-#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */
-#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */
-#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */
-#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */
-#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */
-#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */
-#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */
-#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */
-#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */
-#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */
-#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */
-#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */
-#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */
-#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */
-#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */
-#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */
-
-
-/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
- Example 1:
-
- PA0 = 1;
-
- It is used to set GPIO PA.0 to high;
-
- Example 2:
-
- if (PA0)
- PA0 = 0;
-
- If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low.
- */
-#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
-#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
-#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
-#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
-#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
-#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
-#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
-#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
-#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
-#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
-#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
-#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
-#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
-#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
-#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
-#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
-#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
-#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
-#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
-#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
-#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
-#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
-#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
-#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
-#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
-#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
-#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
-#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
-#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
-#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
-#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
-#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
-#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
-#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
-#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
-#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
-#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
-#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
-#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
-#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
-#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
-#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
-#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
-#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
-#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
-#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
-#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
-#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */
-#define PC15 GPIO_PIN_DATA(2, 15) /*!< Specify PC.15 Pin Data Input/Output */
-#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
-#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
-#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
-#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
-#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
-#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
-#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
-#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
-#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
-#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
-#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
-#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
-#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
-#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
-#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
-#define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */
-#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
-#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
-#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
-#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
-#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
-#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
-#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
-#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
-#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
-#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
-#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
-#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
-#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
-#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
-#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
-#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
-#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
-#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
-#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
-#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
-#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
-#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
-#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
-
-
-/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
- @{
-*/
-
-/**
- * @brief Clear GPIO Pin Interrupt Flag
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- *
- * @return None
- *
- * @details Clear the interrupt status of specified GPIO pin.
- */
-#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
-
-/**
- * @brief Disable Pin De-bounce Function
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- *
- * @return None
- *
- * @details Disable the interrupt de-bounce function of specified GPIO pin.
- */
-#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
-
-/**
- * @brief Enable Pin De-bounce Function
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- * @return None
- *
- * @details Enable the interrupt de-bounce function of specified GPIO pin.
- */
-#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
-
-/**
- * @brief Disable I/O Digital Input Path
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- *
- * @return None
- *
- * @details Disable I/O digital input path of specified GPIO pin.
- */
-#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
-
-/**
- * @brief Enable I/O Digital Input Path
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- *
- * @return None
- *
- * @details Enable I/O digital input path of specified GPIO pin.
- */
-#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
-
-/**
- * @brief Disable I/O DOUT mask
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- *
- * @return None
- *
- * @details Disable I/O DOUT mask of specified GPIO pin.
- */
-#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
-
-/**
- * @brief Enable I/O DOUT mask
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- *
- * @return None
- *
- * @details Enable I/O DOUT mask of specified GPIO pin.
- */
-#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
-
-/**
- * @brief Get GPIO Pin Interrupt Flag
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * It could be BIT0 ~ BIT15 for PA, PB, PC and PD.
- * It could be BIT0 ~ BIT14 for PE.
- * It could be BIT0 ~ BIT7 for PF.
- *
- * @retval 0 No interrupt at specified GPIO pin
- * @retval 1 The specified GPIO pin generate an interrupt
- *
- * @details Get the interrupt status of specified GPIO pin.
- */
-#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
-
-/**
- * @brief Set De-bounce Sampling Cycle Time
- *
- * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
- * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
- * - \ref GPIO_DBCTL_DBCLKSEL_1
- * - \ref GPIO_DBCTL_DBCLKSEL_2
- * - \ref GPIO_DBCTL_DBCLKSEL_4
- * - \ref GPIO_DBCTL_DBCLKSEL_8
- * - \ref GPIO_DBCTL_DBCLKSEL_16
- * - \ref GPIO_DBCTL_DBCLKSEL_32
- * - \ref GPIO_DBCTL_DBCLKSEL_64
- * - \ref GPIO_DBCTL_DBCLKSEL_128
- * - \ref GPIO_DBCTL_DBCLKSEL_256
- * - \ref GPIO_DBCTL_DBCLKSEL_512
- * - \ref GPIO_DBCTL_DBCLKSEL_1024
- * - \ref GPIO_DBCTL_DBCLKSEL_2048
- * - \ref GPIO_DBCTL_DBCLKSEL_4096
- * - \ref GPIO_DBCTL_DBCLKSEL_8192
- * - \ref GPIO_DBCTL_DBCLKSEL_16384
- * - \ref GPIO_DBCTL_DBCLKSEL_32768
- *
- * @return None
- *
- * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
- * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
- * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
- * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
- * and system will sampling interrupt input once per 00 us.
- */
-#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
-
-/**
- * @brief Get GPIO Port IN Data
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- *
- * @return The specified port data
- *
- * @details Get the PIN register of specified GPIO port.
- */
-#define GPIO_GET_IN_DATA(port) ((port)->PIN)
-
-/**
- * @brief Set GPIO Port OUT Data
- *
- * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
- * @param[in] u32Data GPIO port data.
- *
- * @return None
- *
- * @details Set the Data into specified GPIO port.
- */
-#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
-
-/**
- * @brief Toggle Specified GPIO pin
- *
- * @param[in] u32Pin Pxy
- *
- * @return None
- *
- * @details Toggle the specified GPIO pint.
- */
-#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
-
-
-/**
-* @brief Enable External GPIO interrupt
-*
-* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
-* @param[in] u32Pin The pin of specified GPIO port.
-* It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
-* It could be 0 ~ 14 for PE GPIO port.
-* It could be 0 ~ 7 for PF GPIO port.
-* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
-* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW.
-*
-* @return None
-*
-* @details This function is used to enable specified GPIO pin interrupt.
-*/
-#define GPIO_EnableEINT GPIO_EnableInt
-
-/**
-* @brief Disable External GPIO interrupt
-*
-* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF.
-* @param[in] u32Pin The pin of specified GPIO port.
-* It could be 0 ~ 15 for PA, PB, PC and PD GPIO port.
-* It could be 0 ~ 14 for PE GPIO port.
-* It could be 0 ~ 7 for PF GPIO port.
-*
-* @return None
-*
-* @details This function is used to enable specified GPIO pin interrupt.
-*/
-#define GPIO_DisableEINT GPIO_DisableInt
-
-
-void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
-void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
-void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
-
-
-/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group GPIO_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __GPIO_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_i2c.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,612 +0,0 @@
-/**************************************************************************//**
- * @file i2c.c
- * @version V3.00
- * $Revision: 23 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series I2C driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup I2C_Driver I2C Driver
- @{
-*/
-
-
-/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
- @{
-*/
-
-/**
- * @brief Enable specify I2C Controller and set Clock Divider
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u32BusClock The target I2C bus clock in Hz
- *
- * @return Actual I2C bus clock frequency
- *
- * @details The function enable the specify I2C Controller and set proper Clock Divider
- * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
- * I2C Bus clock = PCLK / (4*(divider+1).
- *
- */
-uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
-{
- uint32_t u32Div;
-
- u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
- i2c->CLKDIV = u32Div;
-
- /* Enable I2C */
- i2c->CTL |= I2C_CTL_I2CEN_Msk;
-
- return (SystemCoreClock / ((u32Div + 1) << 2));
-}
-
-/**
- * @brief Disable specify I2C Controller
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details Reset I2C Controller and disable specify I2C port.
- *
- */
-
-void I2C_Close(I2C_T *i2c)
-{
- /* Reset I2C Controller */
- if((uint32_t)i2c == I2C0_BASE)
- {
- SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
- }
- else if((uint32_t)i2c == I2C1_BASE)
- {
- SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
- }
-
- /* Disable I2C */
- i2c->CTL &= ~I2C_CTL_I2CEN_Msk;
-}
-
-/**
- * @brief Clear Time-out Counter flag
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .
- *
- */
-void I2C_ClearTimeoutFlag(I2C_T *i2c)
-{
- i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
-}
-
-/**
- * @brief Set Control bit of I2C Controller
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8Start Set I2C START condition
- * @param[in] u8Stop Set I2C STOP condition
- * @param[in] u8Si Clear SI flag
- * @param[in] u8Ack Set I2C ACK bit
- *
- * @return None
- *
- * @details The function set I2C Control bit of I2C Bus protocol.
- *
- */
-void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
-{
- uint32_t u32Reg = 0;
-
- if(u8Start)
- u32Reg |= I2C_CTL_STA;
- if(u8Stop)
- u32Reg |= I2C_CTL_STO;
- if(u8Si)
- u32Reg |= I2C_CTL_SI;
- if(u8Ack)
- u32Reg |= I2C_CTL_AA;
-
- i2c->CTL = (i2c->CTL & ~0x3C) | u32Reg;
-}
-
-/**
- * @brief Disable Interrupt of I2C Controller
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details The function is used for disable I2C interrupt
- *
- */
-void I2C_DisableInt(I2C_T *i2c)
-{
- i2c->CTL &= ~I2C_CTL_INTEN_Msk;
-}
-
-/**
- * @brief Enable Interrupt of I2C Controller
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details The function is used for enable I2C interrupt
- *
- */
-void I2C_EnableInt(I2C_T *i2c)
-{
- i2c->CTL |= I2C_CTL_INTEN_Msk;
-}
-
-/**
- * @brief Get I2C Bus Clock
- *
- * @param[in] i2c Specify I2C port
- *
- * @return The actual I2C Bus clock in Hz
- *
- * @details To get the actual I2C Bus Clock frequency.
- */
-uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
-{
- uint32_t u32Divider = i2c->CLKDIV;
-
- return (SystemCoreClock / ((u32Divider + 1) << 2));
-}
-
-/**
- * @brief Set I2C Bus Clock
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u32BusClock The target I2C Bus Clock in Hz
- *
- * @return The actual I2C Bus Clock in Hz
- *
- * @details To set the actual I2C Bus Clock frequency.
- */
-uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
-{
- uint32_t u32Div;
-
- u32Div = (uint32_t)(((SystemCoreClock * 10) / (u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
- i2c->CLKDIV = u32Div;
-
- return (SystemCoreClock / ((u32Div + 1) << 2));
-}
-
-/**
- * @brief Get Interrupt Flag
- *
- * @param[in] i2c Specify I2C port
- *
- * @return I2C interrupt flag status
- *
- * @details To get I2C Bus interrupt flag.
- */
-uint32_t I2C_GetIntFlag(I2C_T *i2c)
-{
- return ((i2c->CTL & I2C_CTL_SI_Msk) == I2C_CTL_SI_Msk ? 1 : 0);
-}
-
-/**
- * @brief Get I2C Bus Status Code
- *
- * @param[in] i2c Specify I2C port
- *
- * @return I2C Status Code
- *
- * @details To get I2C Bus Status Code.
- */
-uint32_t I2C_GetStatus(I2C_T *i2c)
-{
- return (i2c->STATUS);
-}
-
-/**
- * @brief Read a Byte from I2C Bus
- *
- * @param[in] i2c Specify I2C port
- *
- * @return I2C Data
- *
- * @details To read a bytes data from specify I2C port.
- */
-uint8_t I2C_GetData(I2C_T *i2c)
-{
- return (i2c->DAT);
-}
-
-/**
- * @brief Send a byte to I2C Bus
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8Data The data to send to I2C bus
- *
- * @return None
- *
- * @details This function is used to write a byte to specified I2C port
- */
-void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
-{
- i2c->DAT = u8Data;
-}
-
-/**
- * @brief Set 7-bit Slave Address and GC Mode
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8SlaveNo Set the number of I2C address register (0~3)
- * @param[in] u8SlaveAddr 7-bit slave address
- * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE)
- *
- * @return None
- *
- * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
- * and enable GC Mode.
- *
- */
-void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
-{
- switch(u8SlaveNo)
- {
- case 1:
- i2c->ADDR1 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- case 2:
- i2c->ADDR2 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- case 3:
- i2c->ADDR3 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- case 0:
- default:
- i2c->ADDR0 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- }
-}
-
-/**
- * @brief Configure the mask bits of 7-bit Slave Address
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3)
- * @param[in] u8SlaveAddrMask A byte for slave address mask
- *
- * @return None
- *
- * @details This function is used to set 7-bit slave addresses.
- *
- */
-void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
-{
- switch(u8SlaveNo)
- {
- case 1:
- i2c->ADDRMSK1 = u8SlaveAddrMask << 1;
- break;
- case 2:
- i2c->ADDRMSK2 = u8SlaveAddrMask << 1;
- break;
- case 3:
- i2c->ADDRMSK3 = u8SlaveAddrMask << 1;
- break;
- case 0:
- default:
- i2c->ADDRMSK0 = u8SlaveAddrMask << 1;
- break;
- }
-}
-
-/**
- * @brief Enable Time-out Counter Function and support Long Time-out
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1)
- *
- * @return None
- *
- * @details This function enable Time-out Counter function and configure DIV4 to support Long
- * Time-out.
- *
- */
-void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
-{
- if(u8LongTimeout)
- i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
- else
- i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
-
- i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
-}
-
-/**
- * @brief Disable Time-out Counter Function
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details To disable Time-out Counter function in I2CTOC register.
- *
- */
-void I2C_DisableTimeout(I2C_T *i2c)
-{
- i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
-}
-
-/**
- * @brief Enable I2C Wake-up Function
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details To enable Wake-up function of I2C Wake-up control register.
- *
- */
-void I2C_EnableWakeup(I2C_T *i2c)
-{
- i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
-}
-
-/**
- * @brief Disable I2C Wake-up Function
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details To disable Wake-up function of I2C Wake-up control register.
- *
- */
-void I2C_DisableWakeup(I2C_T *i2c)
-{
- i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
-}
-
-/**
- * @brief To get SMBus Status
- *
- * @param[in] i2c Specify I2C port
- *
- * @return SMBus status
- *
- * @details To get the Bus Management status of I2C_BUSSTS register
- *
- */
-uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
-{
- return (i2c->BUSSTS);
-}
-
-/**
- * @brief Clear SMBus Interrupt Flag
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag
- *
- * @return None
- *
- * @details To clear flags of I2C_BUSSTS status register if interrupt set.
- *
- */
-void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
-{
- i2c->BUSSTS |= u8SMBusIntFlag;
-}
-
-/**
- * @brief Set SMBus Bytes Counts of Transmission or Reception
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u32PktSize Transmit / Receive bytes
- *
- * @return None
- *
- * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
- *
- */
-void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
-{
- i2c->PKTSIZE = u32PktSize;
-}
-
-/**
- * @brief Init SMBus Host/Device Mode
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0))
- *
- * @return None
- *
- * @details Using SMBus communication must specify the port is a Host or a Device.
- *
- */
-void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
-{
- /* Clear BMHEN, BMDEN of BUSCTL Register */
- i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);
-
- /* Set SMBus Host/Device Mode, and enable Bus Management*/
- if(u8HostDevice == I2C_SMBH_ENABLE)
- i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);
- else
- i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);
-}
-
-/**
- * @brief Disable SMBus function
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode.
- *
- */
-void I2C_SMBusClose(I2C_T *i2c)
-{
-
- i2c->BUSCTL = 0x00;
-}
-
-/**
- * @brief Enable SMBus PEC Transmit Function
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE)
- *
- * @return None
- *
- * @details When enable CRC check function, the Host or Device needs to transmit CRC byte.
- *
- */
-void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
-{
- i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
-
- if(u8PECTxEn)
- i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);
- else
- i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;
-}
-
-/**
- * @brief Get SMBus CRC value
- *
- * @param[in] i2c Specify I2C port
- *
- * @return A byte is packet error check value
- *
- * @details The CRC check value after a transmission or a reception by count by using CRC8
- *
- */
-uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
-{
- return i2c->PKTCRC;
-}
-
-/**
- * @brief Calculate Time-out of SMBus idle period
- *
- * @param[in] i2c Specify I2C port
- * @param[in] us Time-out length(us)
- * @param[in] u32Hclk I2C peripheral clock frequency
- *
- * @return None
- *
- * @details This function is used to set SMBus Time-out length when bus is in Idle state.
- *
- */
-
-void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk)
-{
- uint32_t u32Div, u32Hclk_kHz;
-
- i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
- u32Hclk_kHz = u32Hclk / 1000;
- u32Div = (((us * u32Hclk_kHz) / 1000) >> 2) - 1;
- if(u32Div > 255)
- {
- i2c->BUSTOUT = 0xFF;
- }
- else
- {
- i2c->BUSTOUT = u32Div;
- }
-
-}
-
-/**
- * @brief Calculate Time-out of SMBus active period
- *
- * @param[in] i2c Specify I2C port
- * @param[in] ms Time-out length(ms)
- * @param[in] u32Pclk peripheral clock frequency
- *
- * @return None
- *
- * @details This function is used to set SMBus Time-out length when bus is in active state.
- * Time-out length is calculate the SCL line "one clock" pull low timing.
- *
- */
-
-void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
-{
- uint32_t u32Div, u32Pclk_kHz;
-
- i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
-
- /* DIV4 disabled */
- i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
- u32Pclk_kHz = u32Pclk / 1000;
- u32Div = ((ms * u32Pclk_kHz) / (16 * 1024)) - 1;
- if(u32Div <= 0xFF)
- {
- i2c->BUSTOUT = u32Div;
- return;
- }
-
- /* DIV4 enabled */
- i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
-
- i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16 * 1024 * 4)) - 1) & 0xFF; //The max value is 255
-}
-
-/**
- * @brief Calculate Cumulative Clock low Time-out of SMBus active period
- *
- * @param[in] i2c Specify I2C port
- * @param[in] ms Time-out length(ms)
- * @param[in] u32Pclk peripheral clock frequency
- *
- * @return None
- *
- * @details This function is used to set SMBus Time-out length when bus is in Active state.
- * Time-out length is calculate the SCL line "clocks" low cumulative timing.
- *
- */
-
-void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
-{
- uint32_t u32Div, u32Pclk_kHz;
-
- i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
-
- /* DIV4 disabled */
- i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
- u32Pclk_kHz = u32Pclk / 1000;
- u32Div = ((ms * u32Pclk_kHz) / (16 * 1024)) - 1;
- if(u32Div <= 0xFF)
- {
- i2c->CLKTOUT = u32Div;
- return;
- }
-
- /* DIV4 enabled */
- i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
- i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16 * 1024 * 4)) - 1) & 0xFF; //The max value is 255
-}
-
-/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group I2C_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_i2c.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,415 +0,0 @@
-/**************************************************************************//**
- * @file I2C.h
- * @version V3.0
- * $Revision: 19 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 Series I2C Driver Header File
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __I2C_H__
-#define __I2C_H__
-
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup I2C_Driver I2C Driver
- @{
-*/
-
-/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* I2C_CTL constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define I2C_CTL_STA_STO_SI 0x38UL /*!< I2C_CTL setting for I2C control bits. It would set STA, STO and SI bits */
-#define I2C_CTL_STA_STO_SI_AA 0x3CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, STO, SI and AA bits */
-#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */
-#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */
-#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */
-#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */
-#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit */
-#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */
-#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit */
-#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit */
-#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* I2C GCMode constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */
-#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* I2C SMBUS constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable */
-#define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable */
-#define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function */
-#define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function */
-
-/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
-
-/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
- @{
-*/
-/**
- * @brief The macro is used to set I2C bus condition at One Time
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8Ctrl A byte writes to I2C control register
- *
- * @return None
- *
- * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
- */
-#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL = ((i2c)->CTL & ~0x3c) | (u8Ctrl))
-
-/**
- * @brief The macro is used to set START condition of I2C Bus
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details Set the I2C bus START condition in I2C_CTL register.
- */
-#define I2C_START(i2c) ((i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk)
-
-/**
- * @brief The macro is used to wait I2C bus status get ready
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
- */
-#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
-
-/**
- * @brief The macro is used to Read I2C Bus Data Register
- *
- * @param[in] i2c Specify I2C port
- *
- * @return A byte of I2C data register
- *
- * @details I2C controller read data from bus and save it in I2CDAT register.
- */
-#define I2C_GET_DATA(i2c) ((i2c)->DAT)
-
-/**
- * @brief Write a Data to I2C Data Register
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u8Data A byte that writes to data register
- *
- * @return None
- *
- * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
- */
-#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
-
-/**
- * @brief Get I2C Bus status code
- *
- * @param[in] i2c Specify I2C port
- *
- * @return I2C status code
- *
- * @details To get this status code to monitor I2C bus event.
- */
-#define I2C_GET_STATUS(i2c) ((i2c)->STATUS)
-
-/**
- * @brief Get Time-out flag from I2C Bus
- *
- * @param[in] i2c Specify I2C port
- *
- * @retval 0 I2C Bus time-out is not happened
- * @retval 1 I2C Bus time-out is happened
- *
- * @details When I2C bus occurs time-out event, the time-out flag will be set.
- */
-#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
-
-/**
- * @brief To get wake-up flag from I2C Bus
- *
- * @param[in] i2c Specify I2C port
- *
- * @retval 0 Chip is not woken-up from power-down mode
- * @retval 1 Chip is woken-up from power-down mode
- *
- * @details I2C bus occurs wake-up event, wake-up flag will be set.
- */
-#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
-
-/**
- * @brief To clear wake-up flag
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details If wake-up flag is set, use this macro to clear it.
- */
-#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
-
-/**
- * @brief To get SMBus Status
- *
- * @param[in] i2c Specify I2C port
- *
- * @return SMBus status
- *
- * @details To get the Bus Management status of I2C_BUSSTS register
- *
- */
-#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
-
-/**
- * @brief Get SMBus CRC value
- *
- * @param[in] i2c Specify I2C port
- *
- * @return Packet error check byte value
- *
- * @details The CRC check value after a transmission or a reception by count by using CRC8
- *
- */
-#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
-
-/**
- * @brief Set SMBus Bytes number of Transmission or reception
- *
- * @param[in] i2c Specify I2C port
- * @param[in] u32PktSize Transmit / Receive bytes
- *
- * @return None
- *
- * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
- *
- */
-#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
-
-/**
- * @brief Enable SMBus Alert function
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
- * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
- *
- */
-#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
-
-/**
- * @brief Disable SMBus Alert pin function
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
- * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
- *
- */
-#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
-
-/**
- * @brief Set SMBus SUSCON pin is output mode
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
- *
- *
- */
-#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
-
-/**
- * @brief Set SMBus SUSCON pin is input mode
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
- *
- *
- */
-#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
-
-/**
- * @brief Set SMBus SUSCON pin output high state
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
- *
- */
-#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
-
-
-/**
- * @brief Set SMBus SUSCON pin output low state
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
- *
- */
-#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
-
-/**
- * @brief Enable SMBus Acknowledge control by manual
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
- *
- */
-#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
-
-/**
- * @brief Disable SMBus Acknowledge control by manual
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details Disable acknowledge response control by user.
- *
- */
-#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
-
-/**
- * @brief Enable SMBus Acknowledge manual interrupt
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
- *
- */
-#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
-
-/**
- * @brief Disable SMBus Acknowledge manual interrupt
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
- *
- */
-#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
-
-/**
- * @brief Enable SMBus PEC clear at REPEAT START
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
- *
- */
-#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
-
-/**
- * @brief Disable SMBus PEC clear at Repeat START
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
- *
- */
-#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* inline functions */
-/*---------------------------------------------------------------------------------------------------------*/
-/**
- * @brief The macro is used to set STOP condition of I2C Bus
- *
- * @param[in] i2c Specify I2C port
- *
- * @return None
- *
- * @details Set the I2C bus STOP condition in I2C_CTL register.
- */
-static __INLINE void I2C_STOP(I2C_T *i2c)
-{
-
- (i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk);
- while(i2c->CTL & I2C_CTL_STO_Msk);
-}
-
-void I2C_ClearTimeoutFlag(I2C_T *i2c);
-void I2C_Close(I2C_T *i2c);
-void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
-void I2C_DisableInt(I2C_T *i2c);
-void I2C_EnableInt(I2C_T *i2c);
-uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
-uint32_t I2C_GetIntFlag(I2C_T *i2c);
-uint32_t I2C_GetStatus(I2C_T *i2c);
-uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
-uint8_t I2C_GetData(I2C_T *i2c);
-void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
-void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
-uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
-void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
-void I2C_DisableTimeout(I2C_T *i2c);
-void I2C_EnableWakeup(I2C_T *i2c);
-void I2C_DisableWakeup(I2C_T *i2c);
-void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
-
-uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
-void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);
-void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
-void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
-void I2C_SMBusClose(I2C_T *i2c);
-void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
-uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
-void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
-void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
-void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
-/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group I2C_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-#endif //__I2C_H__
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_otg.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,260 +0,0 @@
-/**************************************************************************//**
- * @file otg.h
- * @version V0.10
- * $Revision: 3 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 Series OTG Driver Header File
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __OTG_H__
-#define __OTG_H__
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Include related headers */
-/*---------------------------------------------------------------------------------------------------------*/
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup OTG_Driver OTG Driver
- @{
-*/
-
-
-/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants
- @{
-*/
-
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* OTG constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. */
-#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. */
-#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. */
-#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. */
-
-
-/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define Macros and functions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-
-/**
- * @brief This macro is used to enable OTG function
- * @param None
- * @return None
- * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
- */
-#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
-
-/**
- * @brief This macro is used to disable OTG function
- * @param None
- * @return None
- * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
- */
-#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
-
-/**
- * @brief This macro is used to enable USB PHY
- * @param None
- * @return None
- * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
- * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
- */
-#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
-
-/**
- * @brief This macro is used to disable USB PHY
- * @param None
- * @return None
- * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
- */
-#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
-
-/**
- * @brief This macro is used to enable ID detection function
- * @param None
- * @return None
- * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
- */
-#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
-
-/**
- * @brief This macro is used to disable ID detection function
- * @param None
- * @return None
- * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
- */
-#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
-
-/**
- * @brief This macro is used to enable OTG wake-up function
- * @param None
- * @return None
- * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
- */
-#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
-
-/**
- * @brief This macro is used to disable OTG wake-up function
- * @param None
- * @return None
- * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
- */
-#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
-
-/**
- * @brief This macro is used to set the polarity of USB_VBUS_EN pin
- * @param[in] u32Pol The polarity selection. Valid values are listed below.
- * - \ref OTG_VBUS_EN_ACTIVE_HIGH
- * - \ref OTG_VBUS_EN_ACTIVE_LOW
- * @return None
- * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
- */
-#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))
-
-/**
- * @brief This macro is used to set the polarity of USB_VBUS_ST pin
- * @param[in] u32Pol The polarity selection. Valid values are listed below.
- * - \ref OTG_VBUS_ST_VALID_HIGH
- * - \ref OTG_VBUS_ST_VALID_LOW
- * @return None
- * @details This macro is used to set the polarity of external USB VBUS power switch status signal.
- */
-#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))
-
-/**
- * @brief This macro is used to enable OTG related interrupts
- * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
- * - \ref OTG_INTEN_ROLECHGIEN_Msk
- * - \ref OTG_INTEN_VBEIEN_Msk
- * - \ref OTG_INTEN_SRPFIEN_Msk
- * - \ref OTG_INTEN_HNPFIEN_Msk
- * - \ref OTG_INTEN_GOIDLEIEN_Msk
- * - \ref OTG_INTEN_IDCHGIEN_Msk
- * - \ref OTG_INTEN_PDEVIEN_Msk
- * - \ref OTG_INTEN_HOSTIEN_Msk
- * - \ref OTG_INTEN_BVLDCHGIEN_Msk
- * - \ref OTG_INTEN_AVLDCHGIEN_Msk
- * - \ref OTG_INTEN_VBCHGIEN_Msk
- * - \ref OTG_INTEN_SECHGIEN_Msk
- * - \ref OTG_INTEN_SRPDETIEN_Msk
- * @return None
- * @details This macro will enable OTG related interrupts specified by u32Mask parameter.
- */
-#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask))
-
-/**
- * @brief This macro is used to disable OTG related interrupts
- * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
- * - \ref OTG_INTEN_ROLECHGIEN_Msk
- * - \ref OTG_INTEN_VBEIEN_Msk
- * - \ref OTG_INTEN_SRPFIEN_Msk
- * - \ref OTG_INTEN_HNPFIEN_Msk
- * - \ref OTG_INTEN_GOIDLEIEN_Msk
- * - \ref OTG_INTEN_IDCHGIEN_Msk
- * - \ref OTG_INTEN_PDEVIEN_Msk
- * - \ref OTG_INTEN_HOSTIEN_Msk
- * - \ref OTG_INTEN_BVLDCHGIEN_Msk
- * - \ref OTG_INTEN_AVLDCHGIEN_Msk
- * - \ref OTG_INTEN_VBCHGIEN_Msk
- * - \ref OTG_INTEN_SECHGIEN_Msk
- * - \ref OTG_INTEN_SRPDETIEN_Msk
- * @return None
- * @details This macro will disable OTG related interrupts specified by u32Mask parameter.
- */
-#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))
-
-/**
- * @brief This macro is used to get OTG related interrupt flags
- * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
- * - \ref OTG_INTSTS_ROLECHGIF_Msk
- * - \ref OTG_INTSTS_VBEIF_Msk
- * - \ref OTG_INTSTS_SRPFIF_Msk
- * - \ref OTG_INTSTS_HNPFIF_Msk
- * - \ref OTG_INTSTS_GOIDLEIF_Msk
- * - \ref OTG_INTSTS_IDCHGIF_Msk
- * - \ref OTG_INTSTS_PDEVIF_Msk
- * - \ref OTG_INTSTS_HOSTIF_Msk
- * - \ref OTG_INTSTS_BVLDCHGIF_Msk
- * - \ref OTG_INTSTS_AVLDCHGIF_Msk
- * - \ref OTG_INTSTS_VBCHGIF_Msk
- * - \ref OTG_INTSTS_SECHGIF_Msk
- * - \ref OTG_INTSTS_SRPDETIF_Msk
- * @return Interrupt flags of selected sources.
- * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
- */
-#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))
-
-/**
- * @brief This macro is used to clear OTG related interrupt flags
- * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
- * - \ref OTG_INTSTS_ROLECHGIF_Msk
- * - \ref OTG_INTSTS_VBEIF_Msk
- * - \ref OTG_INTSTS_SRPFIF_Msk
- * - \ref OTG_INTSTS_HNPFIF_Msk
- * - \ref OTG_INTSTS_GOIDLEIF_Msk
- * - \ref OTG_INTSTS_IDCHGIF_Msk
- * - \ref OTG_INTSTS_PDEVIF_Msk
- * - \ref OTG_INTSTS_HOSTIF_Msk
- * - \ref OTG_INTSTS_BVLDCHGIF_Msk
- * - \ref OTG_INTSTS_AVLDCHGIF_Msk
- * - \ref OTG_INTSTS_VBCHGIF_Msk
- * - \ref OTG_INTSTS_SECHGIF_Msk
- * - \ref OTG_INTSTS_SRPDETIF_Msk
- * @return None
- * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
- */
-#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))
-
-/**
- * @brief This macro is used to get OTG related status
- * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
- * - \ref OTG_STATUS_OVERCUR_Msk
- * - \ref OTG_STATUS_IDSTS_Msk
- * - \ref OTG_STATUS_SESSEND_Msk
- * - \ref OTG_STATUS_BVLD_Msk
- * - \ref OTG_STATUS_AVLD_Msk
- * - \ref OTG_STATUS_VBUSVLD_Msk
- * @return The user specified status.
- * @details This macro will return OTG related status specified by u32Mask parameter.
- */
-#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))
-
-
-
-/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group OTG_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif //__OTG_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,389 +0,0 @@
-/**************************************************************************//**
- * @file pdma.c
- * @version V1.00
- * $Revision: 12 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series PDMA driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-
-static uint8_t u32ChSelect[PDMA_CH_MAX];
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup PDMA_Driver PDMA Driver
- @{
-*/
-
-
-/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
- @{
-*/
-
-/**
- * @brief PDMA Open
- *
- * @param[in] u32Mask Channel enable bits.
- *
- * @return None
- *
- * @details This function enable the PDMA channels.
- */
-void PDMA_Open(uint32_t u32Mask)
-{
- int volatile i;
-
- for(i = 0; i < PDMA_CH_MAX; i++)
- {
- PDMA->DSCT[i].CTL = 0;
- u32ChSelect[i] = 0x1f;
- }
-
- PDMA->CHCTL |= u32Mask;
-}
-
-/**
- * @brief PDMA Close
- *
- * @param None
- *
- * @return None
- *
- * @details This function disable all PDMA channels.
- */
-void PDMA_Close(void)
-{
- PDMA->CHCTL = 0;
-}
-
-/**
- * @brief Set PDMA Transfer Count
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Width Data width. Valid values are
- * - \ref PDMA_WIDTH_8
- * - \ref PDMA_WIDTH_16
- * - \ref PDMA_WIDTH_32
- * @param[in] u32TransCount Transfer count
- *
- * @return None
- *
- * @details This function set the selected channel data width and transfer count.
- */
-void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
-{
- PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
- PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1) << PDMA_DSCT_CTL_TXCNT_Pos));
-}
-
-/**
- * @brief Set PDMA Transfer Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32SrcAddr Source address
- * @param[in] u32SrcCtrl Source control attribute. Valid values are
- * - \ref PDMA_SAR_INC
- * - \ref PDMA_SAR_FIX
- * @param[in] u32DstAddr destination address
- * @param[in] u32DstCtrl destination control attribute. Valid values are
- * - \ref PDMA_DAR_INC
- * - \ref PDMA_DAR_FIX
- *
- * @return None
- *
- * @details This function set the selected channel source/destination address and attribute.
- */
-void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
-{
- PDMA->DSCT[u32Ch].SA = u32SrcAddr;
- PDMA->DSCT[u32Ch].DA = u32DstAddr;
- PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
- PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
-}
-
-/**
- * @brief Set PDMA Transfer Mode
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Peripheral The selected peripheral. Valid values are
- * - \ref PDMA_SPI0_TX
- * - \ref PDMA_SPI1_TX
- * - \ref PDMA_SPI2_TX
- * - \ref PDMA_UART0_TX
- * - \ref PDMA_UART1_TX
- * - \ref PDMA_UART2_TX
- * - \ref PDMA_UART3_TX
- * - \ref PDMA_DAC_TX
- * - \ref PDMA_ADC_RX
- * - \ref PDMA_PWM0_P1_RX
- * - \ref PDMA_PWM0_P2_RX
- * - \ref PDMA_PWM0_P3_RX
- * - \ref PDMA_PWM1_P1_RX
- * - \ref PDMA_PWM1_P2_RX
- * - \ref PDMA_PWM1_P3_RX
- * - \ref PDMA_SPI0_RX
- * - \ref PDMA_SPI1_RX
- * - \ref PDMA_SPI2_RX
- * - \ref PDMA_UART0_RX
- * - \ref PDMA_UART1_RX
- * - \ref PDMA_UART2_RX
- * - \ref PDMA_UART3_RX
- * - \ref PDMA_MEM
- * @param[in] u32ScatterEn Scatter-gather mode enable
- * @param[in] u32DescAddr Scatter-gather descriptor address
- *
- * @return None
- *
- * @details This function set the selected channel transfer mode. Include peripheral setting.
- */
-void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
-{
- u32ChSelect[u32Ch] = u32Peripheral;
- switch(u32Ch)
- {
- case 0:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
- break;
- case 1:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
- break;
- case 2:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
- break;
- case 3:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
- break;
- case 4:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
- break;
- case 5:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
- break;
- case 6:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
- break;
- case 7:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
- break;
- case 8:
- PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
- break;
- case 9:
- PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
- break;
- case 10:
- PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
- break;
- case 11:
- PDMA->REQSEL8_11 = (PDMA->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
- break;
- default:
- ;
- }
-
- if(u32ScatterEn)
- {
- PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
- PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
- }
- else
- PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
-}
-
-/**
- * @brief Set PDMA Burst Type and Size
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32BurstType Burst mode or single mode. Valid values are
- * - \ref PDMA_REQ_SINGLE
- * - \ref PDMA_REQ_BURST
- * @param[in] u32BurstSize Set the size of burst mode. Valid values are
- * - \ref PDMA_BURST_128
- * - \ref PDMA_BURST_64
- * - \ref PDMA_BURST_32
- * - \ref PDMA_BURST_16
- * - \ref PDMA_BURST_8
- * - \ref PDMA_BURST_4
- * - \ref PDMA_BURST_2
- * - \ref PDMA_BURST_1
- *
- * @return None
- *
- * @details This function set the selected channel burst type and size.
- */
-void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
-{
- PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
- PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
-}
-
-/**
- * @brief Enable timeout function
- *
- * @param[in] u32Mask Channel enable bits.
- *
- * @return None
- *
- * @details This function enable timeout function of the selected channel(s).
- * @note This function is only supported in M45xD/M45xC.
- */
-void PDMA_EnableTimeout(uint32_t u32Mask)
-{
- PDMA->TOUTEN |= u32Mask;
-}
-
-/**
- * @brief Disable timeout function
- *
- * @param[in] u32Mask Channel enable bits.
- *
- * @return None
- *
- * @details This function disable timeout function of the selected channel(s).
- * @note This function is only supported in M45xD/M45xC.
- */
-void PDMA_DisableTimeout(uint32_t u32Mask)
-{
- PDMA->TOUTEN &= ~u32Mask;
-}
-
-/**
- * @brief Set PDMA Timeout Count
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32OnOff Enable/disable time out function
- * @param[in] u32TimeOutCnt Timeout count
- *
- * @return None
- *
- * @details This function set the timeout count.
- * @note This function is only supported in M45xD/M45xC.
- */
-void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
-{
- switch(u32Ch)
- {
- case 0:
- PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
- break;
- case 1:
- PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
- break;
- case 2:
- PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
- break;
- case 3:
- PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos);
- break;
- case 4:
- PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
- break;
- case 5:
- PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
- break;
- case 6:
- PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
- break;
- case 7:
- PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
- break;
-
- default:
- ;
- }
-}
-
-/**
- * @brief Trigger PDMA
- *
- * @param[in] u32Ch The selected channel
- *
- * @return None
- *
- * @details This function trigger the selected channel.
- */
-void PDMA_Trigger(uint32_t u32Ch)
-{
- if(u32ChSelect[u32Ch] == PDMA_MEM)
- PDMA->SWREQ = (1 << u32Ch);
-}
-
-/**
- * @brief Enable Interrupt
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Mask The Interrupt Type. Valid values are
- * - \ref PDMA_INT_TRANS_DONE
- * - \ref PDMA_INT_TEMPTY
- * - \ref PDMA_INT_TIMEOUT
- *
- * @return None
- *
- * @details This function enable the selected channel interrupt.
- * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
- */
-void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
-{
- switch(u32Mask)
- {
- case PDMA_INT_TRANS_DONE:
- PDMA->INTEN |= (1 << u32Ch);
- break;
- case PDMA_INT_TEMPTY:
- PDMA->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
- break;
- case PDMA_INT_TIMEOUT:
- PDMA->TOUTIEN |= (1 << u32Ch);
- break;
-
- default:
- ;
- }
-}
-
-/**
- * @brief Disable Interrupt
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Mask The Interrupt Type. Valid values are
- * - \ref PDMA_INT_TRANS_DONE
- * - \ref PDMA_INT_TEMPTY
- * - \ref PDMA_INT_TIMEOUT
- *
- * @return None
- *
- * @details This function disable the selected channel interrupt.
- * @note PDMA_INT_TIMEOUT is only supported in M45xD/M45xC.
- */
-void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
-{
- switch(u32Mask)
- {
- case PDMA_INT_TRANS_DONE:
- PDMA->INTEN &= ~(1 << u32Ch);
- break;
- case PDMA_INT_TEMPTY:
- PDMA->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
- break;
- case PDMA_INT_TIMEOUT:
- PDMA->TOUTIEN &= ~(1 << u32Ch);
- break;
-
- default:
- ;
- }
-}
-
-/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group PDMA_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pdma.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,300 +0,0 @@
-/**************************************************************************//**
- * @file pdma.h
- * @version V1.00
- * $Revision: 15 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series PDMA driver header file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __PDMA_H__
-#define __PDMA_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup PDMA_Driver PDMA Driver
- @{
-*/
-
-/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
- @{
-*/
-#define PDMA_CH_MAX 12 /*!< Specify Maximum Channels of PDMA \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Operation Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
-#define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
-#define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Data Width Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
-#define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
-#define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Address Attribute Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
-#define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
-#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
-#define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Burst Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
-#define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
-
-#define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
-#define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
-#define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
-#define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
-#define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
-#define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
-#define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
-#define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Peripheral Transfer Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_SPI0_TX 0x00000001UL /*!<DMA Connect to SPI1 TX \hideinitializer */
-#define PDMA_SPI1_TX 0x00000002UL /*!<DMA Connect to SPI2 TX \hideinitializer */
-#define PDMA_SPI2_TX 0x00000003UL /*!<DMA Connect to SPI3 TX \hideinitializer */
-#define PDMA_UART0_TX 0x00000004UL /*!<DMA Connect to UART0 TX \hideinitializer */
-#define PDMA_UART1_TX 0x00000005UL /*!<DMA Connect to UART1 TX \hideinitializer */
-#define PDMA_UART2_TX 0x00000006UL /*!<DMA Connect to UART2 TX \hideinitializer */
-#define PDMA_UART3_TX 0x00000007UL /*!<DMA Connect to UART3 TX \hideinitializer */
-#define PDMA_DAC_TX 0x00000008UL /*!<DMA Connect to DAC TX \hideinitializer */
-#define PDMA_ADC_RX 0x00000009UL /*!<DMA Connect to ADC RX \hideinitializer */
-#define PDMA_PWM0_P1_RX 0x0000000BUL /*!<DMA Connect to PWM0 P1 RX \hideinitializer */
-#define PDMA_PWM0_P2_RX 0x0000000CUL /*!<DMA Connect to PWM0 P2 RX \hideinitializer */
-#define PDMA_PWM0_P3_RX 0x0000000DUL /*!<DMA Connect to PWM0 P3 RX \hideinitializer */
-#define PDMA_PWM1_P1_RX 0x0000000EUL /*!<DMA Connect to PWM1 P1 RX \hideinitializer */
-#define PDMA_PWM1_P2_RX 0x0000000FUL /*!<DMA Connect to PWM1 P2 RX \hideinitializer */
-#define PDMA_PWM1_P3_RX 0x00000010UL /*!<DMA Connect to PWM1 P3 RX \hideinitializer */
-#define PDMA_SPI0_RX 0x00000011UL /*!<DMA Connect to SPI0 RX \hideinitializer */
-#define PDMA_SPI1_RX 0x00000012UL /*!<DMA Connect to SPI1 RX \hideinitializer */
-#define PDMA_SPI2_RX 0x00000013UL /*!<DMA Connect to SPI2 RX \hideinitializer */
-#define PDMA_UART0_RX 0x00000014UL /*!<DMA Connect to UART0 RX \hideinitializer */
-#define PDMA_UART1_RX 0x00000015UL /*!<DMA Connect to UART1 RX \hideinitializer */
-#define PDMA_UART2_RX 0x00000016UL /*!<DMA Connect to UART2 RX \hideinitializer */
-#define PDMA_UART3_RX 0x00000017UL /*!<DMA Connect to UART3 RX \hideinitializer */
-#define PDMA_MEM 0x0000001FUL /*!<DMA Connect to Memory \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Interrupt Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */
-#define PDMA_INT_TEMPTY 0x00000001UL /*!<Table Empty Interrupt \hideinitializer */
-#define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt(M45xD/M45xC Only) \hideinitializer */
-
-
-/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */
-
-/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
- @{
-*/
-
-/**
- * @brief Get PDMA Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This macro gets the interrupt status.
- */
-#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMA->INTSTS))
-
-/**
- * @brief Get Transfer Done Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details Get the transfer done Interrupt status.
- */
-#define PDMA_GET_TD_STS() ((uint32_t)(PDMA->TDSTS))
-
-/**
- * @brief Clear Transfer Done Interrupt Status
- *
- * @param[in] u32Mask The channel mask
- *
- * @return None
- *
- * @details Clear the transfer done Interrupt status.
- */
-#define PDMA_CLR_TD_FLAG(u32Mask) ((uint32_t)(PDMA->TDSTS = (u32Mask)))
-
-/**
- * @brief Get Target Abort Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details Get the target abort Interrupt status.
- */
-#define PDMA_GET_ABORT_STS() ((uint32_t)(PDMA->ABTSTS))
-
-/**
- * @brief Clear Target Abort Interrupt Status
- *
- * @param[in] u32Mask The channel mask
- *
- * @return None
- *
- * @details Clear the target abort Interrupt status.
- */
-#define PDMA_CLR_ABORT_FLAG(u32Mask) ((uint32_t)(PDMA->ABTSTS = (u32Mask)))
-
-/**
- * @brief Get Scatter-Gather Table Empty Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details Get the scatter-gather table empty Interrupt status.
- */
-#define PDMA_GET_EMPTY_STS() ((uint32_t)(PDMA->SCATSTS))
-
-/**
- * @brief Clear Scatter-Gather Table Empty Interrupt Status
- *
- * @param[in] u32Mask The channel mask
- *
- * @return None
- *
- * @details Clear the scatter-gather table empty Interrupt status.
- */
-#define PDMA_CLR_EMPTY_FLAG(u32Mask) ((uint32_t)(PDMA->SCATSTS = (u32Mask)))
-
-/**
- * @brief Clear Timeout Interrupt Status
- *
- * @param[in] u32Ch The selected channel
- *
- * @return None
- *
- * @details Clear the selected channel timeout interrupt status.
- * @note This function is only supported in M45xD/M45xC.
- */
-#define PDMA_CLR_TMOUT_FLAG(u32Ch) ((uint32_t)(PDMA->INTSTS = (1 << ((u32Ch) + 8))))
-
-/**
- * @brief Check Channel Status
- *
- * @param[in] u32Ch The selected channel
- *
- * @retval 0 Idle state
- * @retval 1 Busy state
- *
- * @details Check the selected channel is busy or not.
- */
-#define PDMA_IS_CH_BUSY(u32Ch) ((uint32_t)(PDMA->TRGSTS & (1 << (u32Ch)))? 1 : 0)
-
-/**
- * @brief Set Source Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Addr The selected address
- *
- * @return None
- *
- * @details This macro set the selected channel source address.
- */
-#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].SA = (u32Addr)))
-
-/**
- * @brief Set Destination Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Addr The selected address
- *
- * @return None
- *
- * @details This macro set the selected channel destination address.
- */
-#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].DA = (u32Addr)))
-
-/**
- * @brief Set Transfer Count
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32TransCount Transfer Count
- *
- * @return None
- *
- * @details This macro set the selected channel transfer count.
- */
-#define PDMA_SET_TRANS_CNT(u32Ch, u32TransCount) ((uint32_t)(PDMA->DSCT[(u32Ch)].CTL=(PDMA->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|((u32TransCount-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
-
-/**
- * @brief Set Scatter-gather descriptor Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Addr The descriptor address
- *
- * @return None
- *
- * @details This macro set the selected channel scatter-gather descriptor address.
- */
-#define PDMA_SET_SCATTER_DESC(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[(u32Ch)].NEXT = (u32Addr) - (PDMA->SCATBA)))
-
-/**
- * @brief Stop the channel
- *
- * @param[in] u32Ch The selected channel
- *
- * @return None
- *
- * @details This macro stop the selected channel.
- */
-#define PDMA_STOP(u32Ch) ((uint32_t)(PDMA->STOP = (1 << (u32Ch))))
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define PWM functions prototype */
-/*---------------------------------------------------------------------------------------------------------*/
-void PDMA_Open(uint32_t u32Mask);
-void PDMA_Close(void);
-void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
-void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
-void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
-void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
-void PDMA_EnableTimeout(uint32_t u32Mask);
-void PDMA_DisableTimeout(uint32_t u32Mask);
-void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
-void PDMA_Trigger(uint32_t u32Ch);
-void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
-void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
-
-
-/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group PDMA_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__PDMA_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1375 +0,0 @@
-/**************************************************************************//**
- * @file pwm.c
- * @version V3.00
- * $Revision: 21 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series PWM driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup PWM_Driver PWM Driver
- @{
-*/
-
-
-/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
- @{
-*/
-
-/**
- * @brief Configure PWM capture and get the nearest unit time.
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32UnitTimeNsec The unit time of counter
- * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
- * @return The nearest unit time in nano second.
- * @details This function is used to Configure PWM capture and get the nearest unit time.
- */
-uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
-{
- uint32_t u32Src;
- uint32_t u32PWMClockSrc;
- uint32_t u32NearestUnitTimeNsec;
- uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
-
- if(pwm == PWM0)
- u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
- else//(pwm == PWM1)
- u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
-
- if(u32Src == 0)
- {
- //clock source is from PLL clock
- u32PWMClockSrc = CLK_GetPLLClockFreq();
- }
- else
- {
- //clock source is from PCLK
- SystemCoreClockUpdate();
- u32PWMClockSrc = SystemCoreClock;
- }
-
- u32PWMClockSrc /= 1000;
- for(u16Prescale = 1; u16Prescale <= 0x1000; u16Prescale++)
- {
- u32NearestUnitTimeNsec = (1000000 * u16Prescale) / u32PWMClockSrc;
- if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
- {
- if(u16Prescale == 0x1000) //limit to the maximum unit time(nano second)
- break;
- if(!((1000000 * (u16Prescale + 1) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
- break;
- continue;
- }
- break;
- }
-
- // convert to real register value
- // every two channels share a prescaler
- PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
-
- // set PWM to down count type(edge aligned)
- (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
- // set PWM to auto-reload mode
- (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
- PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);
-
- return (u32NearestUnitTimeNsec);
-}
-
-/**
- * @brief This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Frequency Target generator frequency
- * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
- * @return Nearest frequency clock in nano second
- * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect
- * existing frequency of other channel.
- */
-uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32Frequency,
- uint32_t u32DutyCycle)
-{
- return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
-}
-
-/**
- * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
- * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
- * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
- * @return Nearest frequency clock in nano second
- * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
- * existing frequency of other channel.
- */
-uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32Frequency,
- uint32_t u32DutyCycle,
- uint32_t u32Frequency2)
-{
- uint32_t u32Src;
- uint32_t u32PWMClockSrc;
- uint32_t i;
- uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
-
- if(pwm == PWM0)
- u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
- else//(pwm == PWM1)
- u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
-
- if(u32Src == 0)
- {
- //clock source is from PLL clock
- u32PWMClockSrc = CLK_GetPLLClockFreq();
- }
- else
- {
- //clock source is from PCLK
- SystemCoreClockUpdate();
- u32PWMClockSrc = SystemCoreClock;
- }
-
- for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++)//prescale could be 0~0xFFF
- {
- // Note: Support frequency < 1
- i = (uint64_t) u32PWMClockSrc * u32Frequency2 / u32Frequency / u16Prescale;
- // If target value is larger than CNR, need to use a larger prescaler
- if(i > (0x10000))
- continue;
-
- u16CNR = i;
- break;
- }
- // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
- i = u32PWMClockSrc / (u16Prescale * u16CNR);
-
- // convert to real register value
- // every two channels share a prescaler
- PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
- // set PWM to down count type(edge aligned)
- (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
- // set PWM to auto-reload mode
- (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
-
- PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR);
- if(u32DutyCycle)
- {
- PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1);
- (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
- (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTL0_Pos));
- (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
- (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
- }
- else
- {
- PWM_SET_CMR(pwm, u32ChannelNum, 0);
- (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
- (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_ZPCTL0_Pos));
- (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
- (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
- }
-
- return(i);
-}
-
-/**
- * @brief Start PWM module
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * @details This function is used to start PWM module.
- */
-void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- (pwm)->CNTEN |= u32ChannelMask;
-}
-
-/**
- * @brief Stop PWM module
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * @details This function is used to stop PWM module.
- */
-void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- uint32_t i;
- for(i = 0; i < PWM_CHANNEL_NUM; i ++)
- {
- if(u32ChannelMask & (1 << i))
- {
- (pwm)->PERIOD[i] = 0;
- }
- }
-}
-
-/**
- * @brief Stop PWM generation immediately by clear channel enable bit
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * @details This function is used to stop PWM generation immediately by clear channel enable bit.
- */
-void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- (pwm)->CNTEN &= ~u32ChannelMask;
-}
-
-/**
- * @brief Enable selected channel to trigger EADC
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Condition The condition to trigger EADC. Combination of following conditions:
- * - \ref PWM_TRIGGER_ADC_EVEN_ZERO_POINT
- * - \ref PWM_TRIGGER_ADC_EVEN_PERIOD_POINT
- * - \ref PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
- * - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_ODD_ZERO_POINT
- * - \ref PWM_TRIGGER_ADC_ODD_PERIOD_POINT
- * - \ref PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT
- * - \ref PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT
- * - \ref PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT
- * @return None
- * @details This function is used to enable selected channel to trigger EADC.
- */
-void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
-{
- if(u32ChannelNum < 4)
- {
- (pwm)->EADCTS0 &= ~((PWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8));
- (pwm)->EADCTS0 |= ((PWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8));
- }
- else
- {
- (pwm)->EADCTS1 &= ~((PWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4) * 8));
- (pwm)->EADCTS1 |= ((PWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4) * 8));
- }
-}
-
-/**
- * @brief Disable selected channel to trigger EADC
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to disable selected channel to trigger EADC.
- */
-void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- if(u32ChannelNum < 4)
- {
- (pwm)->EADCTS0 &= ~(PWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8));
- }
- else
- {
- (pwm)->EADCTS1 &= ~(PWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4) * 8));
- }
-}
-
-/**
- * @brief Clear selected channel trigger EADC flag
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Condition This parameter is not used
- * @return None
- * @details This function is used to clear selected channel trigger EADC flag.
- */
-void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
-{
- (pwm)->STATUS = (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum);
-}
-
-/**
- * @brief Get selected channel trigger EADC flag
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @retval 0 The specified channel trigger EADC to start of conversion flag is not set
- * @retval 1 The specified channel trigger EADC to start of conversion flag is set
- * @details This function is used to get PWM trigger EADC to start of conversion flag for specified channel.
- */
-uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return (((pwm)->STATUS & (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum)) ? 1 : 0);
-}
-
-/**
- * @brief Enable selected channel to trigger DAC
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
- * - \ref PWM_TRIGGER_DAC_ZERO_POINT
- * - \ref PWM_TRIGGER_DAC_PERIOD_POINT
- * - \ref PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT
- * - \ref PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT
- * @return None
- * @details This function is used to enable selected channel to trigger DAC.
- */
-void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
-{
- (pwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
-}
-
-/**
- * @brief Disable selected channel to trigger DAC
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to disable selected channel to trigger DAC.
- */
-void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->DACTRGEN &= ~((PWM_TRIGGER_DAC_ZERO_POINT | PWM_TRIGGER_DAC_PERIOD_POINT | PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT | \
- PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT) << u32ChannelNum);
-}
-
-/**
- * @brief Clear selected channel trigger DAC flag
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. This parameter is not used
- * @param[in] u32Condition The condition to trigger DAC. This parameter is not used
- * @return None
- * @details This function is used to clear selected channel trigger DAC flag.
- */
-void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
-{
- (pwm)->STATUS = PWM_STATUS_DACTRGF_Msk;
-}
-
-/**
- * @brief Get selected channel trigger DAC flag
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. This parameter is not used
- * @retval 0 The specified channel trigger DAC to start of conversion flag is not set
- * @retval 1 The specified channel trigger DAC to start of conversion flag is set
- * @details This function is used to get selected channel trigger DAC flag.
- */
-uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return (((pwm)->STATUS & PWM_STATUS_DACTRGF_Msk) ? 1 : 0);
-}
-
-/**
- * @brief This function enable fault brake of selected channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
- * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
- * @param[in] u32BrakeSource Fault brake source, could be one of following source
- * - \ref PWM_FB_EDGE_ACMP0
- * - \ref PWM_FB_EDGE_ACMP1
- * - \ref PWM_FB_EDGE_BKP0
- * - \ref PWM_FB_EDGE_BKP1
- * - \ref PWM_FB_EDGE_SYS_CSS
- * - \ref PWM_FB_EDGE_SYS_BOD
- * - \ref PWM_FB_EDGE_SYS_RAM
- * - \ref PWM_FB_EDGE_SYS_COR
- * - \ref PWM_FB_LEVEL_ACMP0
- * - \ref PWM_FB_LEVEL_ACMP1
- * - \ref PWM_FB_LEVEL_BKP0
- * - \ref PWM_FB_LEVEL_BKP1
- * - \ref PWM_FB_LEVEL_SYS_CSS
- * - \ref PWM_FB_LEVEL_SYS_BOD
- * - \ref PWM_FB_LEVEL_SYS_RAM
- * - \ref PWM_FB_LEVEL_SYS_COR
- * @return None
- * @details This function is used to enable fault brake of selected channel(s).
- * The write-protection function should be disabled before using this function.
- */
-void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
-{
- uint32_t i;
- for(i = 0; i < PWM_CHANNEL_NUM; i ++)
- {
- if(u32ChannelMask & (1 << i))
- {
- if((u32BrakeSource == PWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == PWM_FB_EDGE_SYS_BOD) || \
- (u32BrakeSource == PWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == PWM_FB_EDGE_SYS_COR) || \
- (u32BrakeSource == PWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == PWM_FB_LEVEL_SYS_BOD) || \
- (u32BrakeSource == PWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == PWM_FB_LEVEL_SYS_COR))
- {
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= (u32BrakeSource & (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_BRKCTL0_1_SYSLBEN_Msk));
- (pwm)->FAILBRK |= (u32BrakeSource & 0xF);
- }
- else
- {
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= u32BrakeSource;
- }
- }
-
- if(u32LevelMask & (1 << i))
- {
- if(i % 2 == 0)
- {
- //set brake action as high level for even channel
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
- }
- else
- {
- //set brake action as high level for odd channel
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
- }
- }
- else
- {
- if(i % 2 == 0)
- {
- //set brake action as low level for even channel
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
- }
- else
- {
- //set brake action as low level for odd channel
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
- *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
- }
- }
- }
-
-}
-
-/**
- * @brief Enable capture of selected channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * @details This function is used to enable capture of selected channel(s).
- */
-void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- (pwm)->CAPINEN |= u32ChannelMask;
- (pwm)->CAPCTL |= u32ChannelMask;
-}
-
-/**
- * @brief Disable capture of selected channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * @details This function is used to disable capture of selected channel(s).
- */
-void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- (pwm)->CAPINEN &= ~u32ChannelMask;
- (pwm)->CAPCTL &= ~u32ChannelMask;
-}
-
-/**
- * @brief Enables PWM output generation of selected channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
- * @return None
- * @details This function is used to enable PWM output generation of selected channel(s).
- */
-void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- (pwm)->POEN |= u32ChannelMask;
-}
-
-/**
- * @brief Disables PWM output generation of selected channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
- * @return None
- * @details This function is used to disable PWM output generation of selected channel(s).
- */
-void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- (pwm)->POEN &= ~u32ChannelMask;
-}
-
-/**
- * @brief Enables PDMA transfer of selected channel for PWM capture
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number.
- * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
- * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
- * - \ref PWM_CAPTURE_PDMA_RISING_LATCH
- * - \ref PWM_CAPTURE_PDMA_FALLING_LATCH
- * - \ref PWM_CAPTURE_PDMA_RISING_FALLING_LATCH
- * @return None
- * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
- * @note This function can only selects even or odd channel of pairs to do PDMA transfer.
- */
-void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
-{
- uint32_t u32IsOddCh;
- u32IsOddCh = u32ChannelNum % 2;
- (pwm)->PDMACTL = ((pwm)->PDMACTL & ~((PWM_PDMACTL_CHSEL0_1_Msk | PWM_PDMACTL_CAPORD0_1_Msk | PWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
- (((u32IsOddCh << PWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << PWM_PDMACTL_CAPORD0_1_Pos) | \
- u32Mode | PWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) * 8));
-}
-
-/**
- * @brief Disables PDMA transfer of selected channel for PWM capture
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number.
- * @return None
- * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture.
- */
-void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->PDMACTL &= ~(PWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
-}
-
-/**
- * @brief Enable Dead zone of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Duration Dead zone length in PWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
- * @return None
- * @details This function is used to enable Dead zone of selected channel.
- * The write-protection function should be disabled before using this function.
- * @note Every two channels share the same setting.
- */
-void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
-{
- // every two channels share the same setting
- *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTCNT_Msk;
- *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) |= PWM_DTCTL0_1_DTEN_Msk | u32Duration;
-}
-
-/**
- * @brief Disable Dead zone of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to disable Dead zone of selected channel.
- * The write-protection function should be disabled before using this function.
- */
-void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- // every two channels shares the same setting
- *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTEN_Msk;
-}
-
-/**
- * @brief Enable capture interrupt of selected channel.
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Edge Rising or falling edge to latch counter.
- * - \ref PWM_CAPTURE_INT_RISING_LATCH
- * - \ref PWM_CAPTURE_INT_FALLING_LATCH
- * @return None
- * @details This function is used to enable capture interrupt of selected channel.
- */
-void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
-{
- (pwm)->CAPIEN |= (u32Edge << u32ChannelNum);
-}
-
-/**
- * @brief Disable capture interrupt of selected channel.
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Edge Rising or falling edge to latch counter.
- * - \ref PWM_CAPTURE_INT_RISING_LATCH
- * - \ref PWM_CAPTURE_INT_FALLING_LATCH
- * @return None
- * @details This function is used to disable capture interrupt of selected channel.
- */
-void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
-{
- (pwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
-}
-
-/**
- * @brief Clear capture interrupt of selected channel.
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Edge Rising or falling edge to latch counter.
- * - \ref PWM_CAPTURE_INT_RISING_LATCH
- * - \ref PWM_CAPTURE_INT_FALLING_LATCH
- * @return None
- * @details This function is used to clear capture interrupt of selected channel.
- */
-void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
-{
- (pwm)->CAPIF = (u32Edge << u32ChannelNum);
-}
-
-/**
- * @brief Get capture interrupt of selected channel.
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @retval 0 No capture interrupt
- * @retval 1 Rising edge latch interrupt
- * @retval 2 Falling edge latch interrupt
- * @retval 3 Rising and falling latch interrupt
- * @details This function is used to get capture interrupt of selected channel.
- */
-uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return (((((pwm)->CAPIF & (PWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1 : 0) << 1) | \
- (((pwm)->CAPIF & (PWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1 : 0));
-}
-/**
- * @brief Enable duty interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32IntDutyType Duty interrupt type, could be either
- * - \ref PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
- * - \ref PWM_DUTY_INT_UP_COUNT_MATCH_CMP
- * @return None
- * @details This function is used to enable duty interrupt of selected channel.
- */
-void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
-{
- (pwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
-}
-
-/**
- * @brief Disable duty interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to disable duty interrupt of selected channel.
- */
-void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTEN0 &= ~((PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | PWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
-}
-
-/**
- * @brief Clear duty interrupt flag of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to clear duty interrupt flag of selected channel.
- */
-void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTSTS0 = (PWM_INTSTS0_CMPUIF0_Msk | PWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
-}
-
-/**
- * @brief Get duty interrupt flag of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Duty interrupt flag of specified channel
- * @retval 0 Duty interrupt did not occur
- * @retval 1 Duty interrupt occurred
- * @details This function is used to get duty interrupt flag of selected channel.
- */
-uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return ((((pwm)->INTSTS0 & ((PWM_INTSTS0_CMPDIF0_Msk | PWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1 : 0);
-}
-
-/**
- * @brief This function enable fault brake interrupt
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32BrakeSource Fault brake source.
- * - \ref PWM_FB_EDGE
- * - \ref PWM_FB_LEVEL
- * @return None
- * @details This function is used to enable fault brake interrupt.
- * The write-protection function should be disabled before using this function.
- * @note Every two channels share the same setting.
- */
-void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
-{
- (pwm)->INTEN1 |= (0x7 << u32BrakeSource);
-}
-
-/**
- * @brief This function disable fault brake interrupt
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32BrakeSource Fault brake source.
- * - \ref PWM_FB_EDGE
- * - \ref PWM_FB_LEVEL
- * @return None
- * @details This function is used to disable fault brake interrupt.
- * The write-protection function should be disabled before using this function.
- * @note Every two channels share the same setting.
- */
-void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
-{
- (pwm)->INTEN1 &= ~(0x7 << u32BrakeSource);
-}
-
-/**
- * @brief This function clear fault brake interrupt of selected source
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32BrakeSource Fault brake source.
- * - \ref PWM_FB_EDGE
- * - \ref PWM_FB_LEVEL
- * @return None
- * @details This function is used to clear fault brake interrupt of selected source.
- * The write-protection function should be disabled before using this function.
- */
-void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
-{
- (pwm)->INTSTS1 = (0x3f << u32BrakeSource);
-}
-
-/**
- * @brief This function get fault brake interrupt flag of selected source
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32BrakeSource Fault brake source, could be either
- * - \ref PWM_FB_EDGE
- * - \ref PWM_FB_LEVEL
- * @return Fault brake interrupt flag of specified source
- * @retval 0 Fault brake interrupt did not occurred
- * @retval 1 Fault brake interrupt occurred
- * @details This function is used to get fault brake interrupt flag of selected source.
- */
-uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
-{
- return (((pwm)->INTSTS1 & (0x3f << u32BrakeSource)) ? 1 : 0);
-}
-
-/**
- * @brief Enable period interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
- * @return None
- * @details This function is used to enable period interrupt of selected channel.
- */
-void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
-{
- (pwm)->INTEN0 |= (PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
-}
-
-/**
- * @brief Disable period interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to disable period interrupt of selected channel.
- */
-void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTEN0 &= ~(PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
-}
-
-/**
- * @brief Clear period interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to clear period interrupt of selected channel.
- */
-void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTSTS0 = (PWM_INTSTS0_PIF0_Msk << u32ChannelNum);
-}
-
-/**
- * @brief Get period interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Period interrupt flag of specified channel
- * @retval 0 Period interrupt did not occur
- * @retval 1 Period interrupt occurred
- * @details This function is used to get period interrupt of selected channel.
- */
-uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return ((((pwm)->INTSTS0 & (PWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1 : 0);
-}
-
-/**
- * @brief Enable zero interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to enable zero interrupt of selected channel.
- */
-void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTEN0 |= (PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
-}
-
-/**
- * @brief Disable zero interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to disable zero interrupt of selected channel.
- */
-void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTEN0 &= ~(PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
-}
-
-/**
- * @brief Clear zero interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to clear zero interrupt of selected channel.
- */
-void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTSTS0 = (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum);
-}
-
-/**
- * @brief Get zero interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Zero interrupt flag of specified channel
- * @retval 0 Zero interrupt did not occur
- * @retval 1 Zero interrupt occurred
- * @details This function is used to get zero interrupt of selected channel.
- */
-uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return ((((pwm)->INTSTS0 & (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1 : 0);
-}
-
-/**
- * @brief Enable interrupt flag accumulator of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~15.
- * @param[in] u32IntAccSrc Interrupt flag accumulator source selection.
- * - \ref PWM_IFA_EVEN_ZERO_POINT
- * - \ref PWM_IFA_EVEN_PERIOD_POINT
- * - \ref PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT
- * - \ref PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT
- * - \ref PWM_IFA_ODD_ZERO_POINT
- * - \ref PWM_IFA_ODD_PERIOD_POINT
- * - \ref PWM_IFA_ODD_COMPARE_UP_COUNT_POINT
- * - \ref PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT
- * @return None
- * @details This function is used to enable interrupt flag accumulator of selected channel.
- * @note Every two channels share the same setting.
- */
-void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
-{
- (pwm)->IFA = ((pwm)->IFA & ~((PWM_IFA_IFCNT0_1_Msk | PWM_IFA_IFSEL0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
- ((PWM_IFA_IFAEN0_1_Msk | (u32IntAccSrc << PWM_IFA_IFSEL0_1_Pos) | u32IntFlagCnt) << ((u32ChannelNum >> 1) * 8));
-}
-
-/**
- * @brief Disable interrupt flag accumulator of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to Disable interrupt flag accumulator of selected channel.
- * @note Every two channels share the same setting.
- */
-void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->IFA = (pwm)->IFA & ~(PWM_IFA_IFAEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
-}
-
-/**
- * @brief Enable interrupt flag accumulator interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to enable interrupt flag accumulator interrupt of selected channel.
- * @note Every two channels share the same setting.
- */
-void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTEN0 |= (PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
-}
-
-/**
- * @brief Disable interrupt flag accumulator interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to disable interrupt flag accumulator interrupt of selected channel.
- * @note Every two channels share the same setting.
- */
-void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTEN0 &= ~(PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
-}
-
-/**
- * @brief Clear interrupt flag accumulator interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to clear interrupt flag accumulator interrupt of selected channel.
- * @note Every two channels share the same setting.
- */
-void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->INTSTS0 = (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8));
-}
-
-/**
- * @brief Get interrupt flag accumulator interrupt of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @retval 0 Accumulator interrupt did not occur
- * @retval 1 Accumulator interrupt occurred
- * @details This function is used to Get interrupt flag accumulator interrupt of selected channel.
- * @note Every two channels share the same setting.
- */
-uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return (((pwm)->INTSTS0 & (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8))) ? 1 : 0);
-}
-
-/**
- * @brief Clear free trigger duty interrupt flag of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to clear free trigger duty interrupt flag of selected channel.
- */
-void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->FTCI = ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1));
-}
-
-/**
- * @brief Get free trigger duty interrupt flag of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Duty interrupt flag of specified channel
- * @retval 0 Free trigger duty interrupt did not occur
- * @retval 1 Free trigger duty interrupt occurred
- * @details This function is used to get free trigger duty interrupt flag of selected channel.
- */
-uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return (((pwm)->FTCI & ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1 : 0);
-}
-
-/**
- * @brief Enable load mode of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32LoadMode PWM counter loading mode.
- * - \ref PWM_LOAD_MODE_IMMEDIATE
- * - \ref PWM_LOAD_MODE_WINDOW
- * - \ref PWM_LOAD_MODE_CENTER
- * @return None
- * @details This function is used to enable load mode of selected channel.
- */
-void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
-{
- (pwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
-}
-
-/**
- * @brief Disable load mode of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32LoadMode PWM counter loading mode.
- * - \ref PWM_LOAD_MODE_IMMEDIATE
- * - \ref PWM_LOAD_MODE_WINDOW
- * - \ref PWM_LOAD_MODE_CENTER
- * @return None
- * @details This function is used to disable load mode of selected channel.
- */
-void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
-{
- (pwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
-}
-
-/**
- * @brief Configure synchronization phase of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32SyncSrc PWM synchronize source selection.
- * - \ref PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC
- * - \ref PWM_SYNC_OUT_FROM_COUNT_TO_ZERO
- * - \ref PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR
- * - \ref PWM_SYNC_OUT_DISABLE
- * @param[in] u32Direction Phase direction. Control PWM counter count decrement or increment after synchronizing.
- * - \ref PWM_PHS_DIR_DECREMENT
- * - \ref PWM_PHS_DIR_INCREMENT
- * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535.
- * @return None
- * @details This function is used to configure synchronization phase of selected channel.
- * @note Every two channels share the same setting.
- */
-void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
-{
- // every two channels shares the same setting
- u32ChannelNum >>= 1;
- (pwm)->SYNC = (((pwm)->SYNC & ~((PWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (PWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \
- (u32Direction << PWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << PWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1));
- *(__IO uint32_t *)(&((pwm)->PHS0_1) + u32ChannelNum) = u32StartPhase;
-}
-
-
-/**
- * @brief Enable SYNC phase of selected channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * @details This function is used to enable SYNC phase of selected channel(s).
- * @note Every two channels share the same setting.
- */
-void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- uint32_t i;
- for(i = 0; i < PWM_CHANNEL_NUM; i ++)
- {
- if(u32ChannelMask & (1 << i))
- {
- (pwm)->SYNC |= (PWM_SYNC_PHSEN0_Msk << (i >> 1));
- }
- }
-}
-
-/**
- * @brief Disable SYNC phase of selected channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * @details This function is used to disable SYNC phase of selected channel(s).
- * @note Every two channels share the same setting.
- */
-void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
-{
- uint32_t i;
- for(i = 0; i < PWM_CHANNEL_NUM; i ++)
- {
- if(u32ChannelMask & (1 << i))
- {
- (pwm)->SYNC &= ~(PWM_SYNC_PHSEN0_Msk << (i >> 1));
- }
- }
-}
-
-/**
- * @brief Enable PWM SYNC_IN noise filter function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector.
- * The valid value is 0~7.
- * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
- * - \ref PWM_NF_CLK_DIV_1
- * - \ref PWM_NF_CLK_DIV_2
- * - \ref PWM_NF_CLK_DIV_4
- * - \ref PWM_NF_CLK_DIV_8
- * - \ref PWM_NF_CLK_DIV_16
- * - \ref PWM_NF_CLK_DIV_32
- * - \ref PWM_NF_CLK_DIV_64
- * - \ref PWM_NF_CLK_DIV_128
- * @return None
- * @details This function is used to enable PWM SYNC_IN noise filter function.
- */
-void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
-{
- (pwm)->SYNC = ((pwm)->SYNC & ~(PWM_SYNC_SFLTCNT_Msk | PWM_SYNC_SFLTCSEL_Msk)) | \
- ((u32ClkCnt << PWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << PWM_SYNC_SFLTCSEL_Pos) | PWM_SYNC_SNFLTEN_Msk);
-}
-
-/**
- * @brief Disable PWM SYNC_IN noise filter function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @return None
- * @details This function is used to Disable PWM SYNC_IN noise filter function.
- */
-void PWM_DisableSyncNoiseFilter(PWM_T *pwm)
-{
- (pwm)->SYNC &= ~PWM_SYNC_SNFLTEN_Msk;
-}
-
-/**
- * @brief Enable PWM SYNC input pin inverse function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @return None
- * @details This function is used to enable PWM SYNC input pin inverse function.
- */
-void PWM_EnableSyncPinInverse(PWM_T *pwm)
-{
- (pwm)->SYNC |= PWM_SYNC_SINPINV_Msk;
-}
-
-/**
- * @brief Disable PWM SYNC input pin inverse function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @return None
- * @details This function is used to Disable PWM SYNC input pin inverse function.
- */
-void PWM_DisableSyncPinInverse(PWM_T *pwm)
-{
- (pwm)->SYNC &= ~PWM_SYNC_SINPINV_Msk;
-}
-
-/**
- * @brief Set PWM clock source
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32ClkSrcSel PWM external clock source.
- * - \ref PWM_CLKSRC_PWM_CLK
- * - \ref PWM_CLKSRC_TIMER0
- * - \ref PWM_CLKSRC_TIMER1
- * - \ref PWM_CLKSRC_TIMER2
- * - \ref PWM_CLKSRC_TIMER3
- * @return None
- * @details This function is used to set PWM clock source.
- * @note Every two channels share the same setting.
- */
-void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
-{
- (pwm)->CLKSRC = (pwm)->CLKSRC & ~(PWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos)) | \
- (u32ClkSrcSel << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos));
-}
-
-/**
- * @brief Enable PWM brake noise filter function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
- * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
- * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
- * - \ref PWM_NF_CLK_DIV_1
- * - \ref PWM_NF_CLK_DIV_2
- * - \ref PWM_NF_CLK_DIV_4
- * - \ref PWM_NF_CLK_DIV_8
- * - \ref PWM_NF_CLK_DIV_16
- * - \ref PWM_NF_CLK_DIV_32
- * - \ref PWM_NF_CLK_DIV_64
- * - \ref PWM_NF_CLK_DIV_128
- * @return None
- * @details This function is used to enable PWM brake noise filter function.
- */
-void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
-{
- (pwm)->BNF = ((pwm)->BNF & ~((PWM_BNF_BRK0FCNT_Msk | PWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos))) | \
- (((u32ClkCnt << PWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << PWM_BNF_BRK0NFSEL_Pos) | PWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
-}
-
-/**
- * @brief Disable PWM brake noise filter function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
- * @return None
- * @details This function is used to disable PWM brake noise filter function.
- */
-void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
-{
- (pwm)->BNF &= ~(PWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
-}
-
-/**
- * @brief Enable PWM brake pin inverse function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
- * @return None
- * @details This function is used to enable PWM brake pin inverse function.
- */
-void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
-{
- (pwm)->BNF |= (PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
-}
-
-/**
- * @brief Disable PWM brake pin inverse function
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
- * @return None
- * @details This function is used to disable PWM brake pin inverse function.
- */
-void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
-{
- (pwm)->BNF &= ~(PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
-}
-
-/**
- * @brief Set PWM brake pin source
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
- * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
- * @return None
- * @details This function is used to set PWM brake pin source.
- * @note This function is only supported in M45xD/M45xC.
- */
-void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
-{
- (pwm)->BNF = ((pwm)->BNF & ~(PWM_BNF_BK0SRC_Msk << (u32BrakePinNum * 8))) | (u32SelAnotherModule << (PWM_BNF_BK0SRC_Pos + u32BrakePinNum * 8));
-}
-
-/**
- * @brief Get the time-base counter reached its maximum value flag of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Count to max interrupt flag of specified channel
- * @retval 0 Count to max interrupt did not occur
- * @retval 1 Count to max interrupt occurred
- * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
- */
-uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return (((pwm)->STATUS & (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1 : 0);
-}
-
-/**
- * @brief Clear the time-base counter reached its maximum value flag of selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * - PWM0 : PWM Group 0
- * - PWM1 : PWM Group 1
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
- */
-void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
-{
- (pwm)->STATUS = (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
-}
-
-
-/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group PWM_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_pwm.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,560 +0,0 @@
-/**************************************************************************//**
- * @file pwm.h
- * @version V1.00
- * $Revision: 26 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series PWM driver header file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __PWM_H__
-#define __PWM_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup PWM_Driver PWM Driver
- @{
-*/
-
-/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
- @{
-*/
-#define PWM_CHANNEL_NUM (6) /*!< PWM channel number */
-#define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask \hideinitializer */
-#define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask \hideinitializer */
-#define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask \hideinitializer */
-#define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask \hideinitializer */
-#define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask \hideinitializer */
-#define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Counter Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_UP_COUNTER (0UL) /*!< Up counter type */
-#define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */
-#define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Aligned Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */
-#define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Output Level Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */
-#define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */
-#define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */
-#define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Trigger Source Select Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger ADC while counter of even channel matches zero point */
-#define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger ADC while counter of even channel matches period point */
-#define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger ADC while counter of even channel matches zero or period point */
-#define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< PWM trigger ADC while counter of even channel matches up count to comparator point */
-#define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< PWM trigger ADC while counter of even channel matches down count to comparator point */
-#define PWM_TRIGGER_ADC_ODD_ZERO_POINT (5UL) /*!< PWM trigger ADC while counter of odd channel matches zero point */
-#define PWM_TRIGGER_ADC_ODD_PERIOD_POINT (6UL) /*!< PWM trigger ADC while counter of odd channel matches period point */
-#define PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT (7UL) /*!< PWM trigger ADC while counter of odd channel matches zero or period point */
-#define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point */
-#define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point */
-#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT (10UL) /*!< PWM trigger ADC while counter of channel 0 matches up count to free comparator point */
-#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT (11UL) /*!< PWM trigger ADC while counter of channel 0 matches down count to free comparator point */
-#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT (12UL) /*!< PWM trigger ADC while counter of channel 2 matches up count to free comparator point */
-#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT (13UL) /*!< PWM trigger ADC while counter of channel 2 matches down count to free comparator point */
-#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT (14UL) /*!< PWM trigger ADC while counter of channel 4 matches up count to free comparator point */
-#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT (15UL) /*!< PWM trigger ADC while counter of channel 4 matches down count to free comparator point */
-
-#define PWM_TRIGGER_DAC_ZERO_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
-#define PWM_TRIGGER_DAC_PERIOD_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
-#define PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT (0x10000UL) /*!< PWM trigger ADC while counter up count to CMPDAT \hideinitializer */
-#define PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT (0x1000000UL) /*!< PWM trigger ADC while counter down count to CMPDAT \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Fail brake Control Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
-#define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
-#define PWM_FB_EDGE_BKP0 (PWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
-#define PWM_FB_EDGE_BKP1 (PWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
-#define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
-#define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
-#define PWM_FB_EDGE_SYS_RAM (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
-#define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
-
-#define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
-#define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
-#define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
-#define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
-#define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
-#define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
-#define PWM_FB_LEVEL_SYS_RAM (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
-#define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */
-
-#define PWM_FB_EDGE (0UL) /*!< edge-detect fault brake */
-#define PWM_FB_LEVEL (8UL) /*!< level-detect fault brake */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Capture Control Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition */
-#define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition */
-
-#define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA */
-#define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA */
-#define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Duty Interrupt Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator */
-#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up down match comparator */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Interrupt Flag Accumulator Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_IFA_EVEN_ZERO_POINT (0UL) /*!< PWM counter equal to zero in even channel \hideinitializer */
-#define PWM_IFA_EVEN_PERIOD_POINT (1UL) /*!< PWM counter equal to period in even channel \hideinitializer */
-#define PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT (2UL) /*!< PWM counter up count to comparator value in even channel \hideinitializer */
-#define PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT (3UL) /*!< PWM counter down count to comparator value in even channel \hideinitializer */
-#define PWM_IFA_ODD_ZERO_POINT (4UL) /*!< PWM counter equal to zero in odd channel \hideinitializer */
-#define PWM_IFA_ODD_PERIOD_POINT (5UL) /*!< PWM counter equal to period in odd channel \hideinitializer */
-#define PWM_IFA_ODD_COMPARE_UP_COUNT_POINT (6UL) /*!< PWM counter up count to comparator value in odd channel \hideinitializer */
-#define PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT (7UL) /*!< PWM counter down count to comparator value in odd channel \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Load Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode \hideinitializer */
-#define PWM_LOAD_MODE_WINDOW (PWM_CTL0_WINLDEN0_Msk) /*!< PWM window load mode \hideinitializer */
-#define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Synchronize Control Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
-#define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */
-#define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
-#define PWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */
-#define PWM_PHS_DIR_DECREMENT (0UL) /*!< PWM counter count decrement \hideinitializer */
-#define PWM_PHS_DIR_INCREMENT (1UL) /*!< PWM counter count increment \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Noise Filter Clock Divide Select Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
-#define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
-#define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
-#define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
-#define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
-#define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
-#define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
-#define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Clock Source Select Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */
-#define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */
-#define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */
-#define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */
-#define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */
-
-
-/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
- @{
-*/
-
-/**
- * @brief This macro enable complementary mode
- * @param[in] pwm The pointer of the specified PWM module
- * @return None
- * @details This macro is used to enable complementary mode of PWM module.
- * \hideinitializer
- */
-#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | PWM_CTL1_OUTMODEn_Msk)
-
-/**
- * @brief This macro disable complementary mode, and enable independent mode.
- * @param[in] pwm The pointer of the specified PWM module
- * @return None
- * @details This macro is used to disable complementary mode of PWM module.
- * \hideinitializer
- */
-#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~PWM_CTL1_OUTMODEn_Msk)
-
-/**
- * @brief This macro enable group mode
- * @param[in] pwm The pointer of the specified PWM module
- * @return None
- * @details This macro is used to enable group mode of PWM module.
- * \hideinitializer
- */
-#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 | PWM_CTL0_GROUPEN_Msk)
-
-/**
- * @brief This macro disable group mode
- * @param[in] pwm The pointer of the specified PWM module
- * @return None
- * @details This macro is used to disable group mode of PWM module.
- * \hideinitializer
- */
-#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 & ~PWM_CTL0_GROUPEN_Msk)
-
-/**
- * @brief Enable timer synchronous mode of specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @return None
- * @details This macro is used to enable timer synchronous mode of specified channel(s).
- * \hideinitializer
- */
-#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask) ((pwm)->SSCTL |= (u32ChannelMask))
-
-/**
- * @brief Disable timer synchronous mode of specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @return None
- * @details This macro is used to disable timer synchronous mode of specified channel(s).
- * \hideinitializer
- */
-#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
- do{ \
- int i;\
- for(i = 0; i < 6; i++) { \
- if((u32ChannelMask) & (1 << i)) \
- (pwm)->SSCTL &= ~(1UL << i); \
- } \
- }while(0)
-
-/**
- * @brief This macro enable output inverter of specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @return None
- * @details This macro is used to enable output inverter of specified channel(s).
- * \hideinitializer
- */
-#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
-
-/**
- * @brief This macro get captured rising data
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This macro is used to get captured rising data of specified channel.
- * \hideinitializer
- */
-#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + 2 * (u32ChannelNum)))
-
-/**
- * @brief This macro get captured falling data
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * @details This macro is used to get captured falling data of specified channel.
- * \hideinitializer
- */
-#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + 2 * (u32ChannelNum)))
-
-/**
- * @brief This macro mask output logic to high or low
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @param[in] u32LevelMask Output logic to high or low
- * @return None
- * @details This macro is used to mask output logic to high or low of specified channel(s).
- * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
- * \hideinitializer
- */
-#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
- { \
- (pwm)->MSKEN = (u32ChannelMask); \
- (pwm)->MSK = (u32LevelMask); \
- }
-
-/**
- * @brief This macro set the prescaler of the selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
- * @return None
- * @details This macro is used to set the prescaler of specified channel.
- * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
- * channel 1 will also be affected.
- * \hideinitializer
- */
-#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1)) = (u32Prescaler))
-
-/**
- * @brief This macro set the comparator of the selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
- * @return None
- * @details This macro is used to set the comparator of specified channel.
- * @note This new setting will take effect on next PWM period.
- * \hideinitializer
- */
-#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
-
-/**
- * @brief This macro set the free trigger comparator of the selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
- * @return None
- * @details This macro is used to set the free trigger comparator of specified channel.
- * @note This new setting will take effect on next PWM period.
- * \hideinitializer
- */
-#define PWM_SET_FTCMR(pwm, u32ChannelNum, u32FTCMR) (*(__IO uint32_t *) (&((pwm)->FTCMPDAT0_1) + ((u32ChannelNum) >> 1)) = (u32FTCMR))
-
-/**
- * @brief This macro set the period of the selected channel
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
- * @return None
- * @details This macro is used to set the period of specified channel.
- * @note This new setting will take effect on next PWM period.
- * @note PWM counter will stop if period length set to 0.
- * \hideinitializer
- */
-#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
-
-/**
- * @brief This macro set the PWM aligned type
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @param[in] u32AlignedType PWM aligned type, valid values are:
- * - \ref PWM_EDGE_ALIGNED
- * - \ref PWM_CENTER_ALIGNED
- * @return None
- * @details This macro is used to set the PWM aligned type of specified channel(s).
- * \hideinitializer
- */
-#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
- do{ \
- int i; \
- for(i = 0; i < 6; i++) { \
- if((u32ChannelMask) & (1 << i)) \
- (pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (2 * i))) | ((u32AlignedType) << ( 2 * i))); \
- } \
- }while(0)
-
-/**
- * @brief Set load window of window loading mode for specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @return None
- * @details This macro is used to set load window of window loading mode for specified channel(s).
- * \hideinitializer
- */
-#define PWM_SET_LOAD_WINDOW(pwm, u32ChannelMask) ((pwm)->LOAD |= (u32ChannelMask))
-
-/**
- * @brief Trigger synchronous event from specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are 0, 2, 4
- * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
- * @return None
- * @details This macro is used to trigger synchronous event from specified channel(s).
- * \hideinitializer
- */
-#define PWM_TRIGGER_SYNC(pwm, u32ChannelNum) ((pwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1)))
-
-/**
- * @brief Clear counter of specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @return None
- * @details This macro is used to clear counter of specified channel(s).
- * \hideinitializer
- */
-#define PWM_CLR_COUNTER(pwm, u32ChannelMask) ((pwm)->CNTCLR |= (u32ChannelMask))
-
-/**
- * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @param[in] u32ZeroLevel output level at zero point, valid values are:
- * - \ref PWM_OUTPUT_NOTHING
- * - \ref PWM_OUTPUT_LOW
- * - \ref PWM_OUTPUT_HIGH
- * - \ref PWM_OUTPUT_TOGGLE
- * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
- * - \ref PWM_OUTPUT_NOTHING
- * - \ref PWM_OUTPUT_LOW
- * - \ref PWM_OUTPUT_HIGH
- * - \ref PWM_OUTPUT_TOGGLE
- * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
- * - \ref PWM_OUTPUT_NOTHING
- * - \ref PWM_OUTPUT_LOW
- * - \ref PWM_OUTPUT_HIGH
- * - \ref PWM_OUTPUT_TOGGLE
- * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
- * - \ref PWM_OUTPUT_NOTHING
- * - \ref PWM_OUTPUT_LOW
- * - \ref PWM_OUTPUT_HIGH
- * - \ref PWM_OUTPUT_TOGGLE
- * @return None
- * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
- * \hideinitializer
- */
-#define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
- do{ \
- int i; \
- for(i = 0; i < 6; i++) { \
- if((u32ChannelMask) & (1 << i)) { \
- (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
- (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \
- (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
- (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \
- } \
- } \
- }while(0)
-
-/**
- * @brief Trigger brake event from specified channel(s)
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
- * @param[in] u32BrakeType Type of brake trigger. PWM_FB_EDGE of this macro is only supported in M45xD/M45xC.
- * - \ref PWM_FB_EDGE
- * - \ref PWM_FB_LEVEL
- * @return None
- * @details This macro is used to trigger brake event from specified channel(s).
- * \hideinitializer
- */
-#define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
-
-/**
- * @brief Set Dead zone clock source
- * @param[in] pwm The pointer of the specified PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
- * @return None
- * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
- * @note The write-protection function should be disabled before using this function.
- * @note This function is only supported in M45xD/M45xC.
- * \hideinitializer
- */
-#define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
- (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) = (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
- ((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos))
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define PWM functions prototype */
-/*---------------------------------------------------------------------------------------------------------*/
-uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
-uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
-uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32Frequency,
- uint32_t u32DutyCycle,
- uint32_t u32Frequency2);
-void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
-void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
-uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
-void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
-uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
-void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
-void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
-void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
-void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
-void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
-uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
-void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
-void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
-void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
-uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
-void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
-void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
-void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
-uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
-void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
-void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
-void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
-void PWM_DisableSyncNoiseFilter(PWM_T *pwm);
-void PWM_EnableSyncPinInverse(PWM_T *pwm);
-void PWM_DisableSyncPinInverse(PWM_T *pwm);
-void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
-void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
-void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
-void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
-void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
-void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
-uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-
-
-/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group PWM_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__PWM_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_rtc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,789 +0,0 @@
-/**************************************************************************//**
- * @file rtc.c
- * @version V3.00
- * $Revision: 7 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series RTC driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-
-/// @cond HIDDEN_SYMBOLS
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Macro, type and constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_GLOBALS
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Global file scope (static) variables */
-/*---------------------------------------------------------------------------------------------------------*/
-static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
-static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
-
-/// @endcond HIDDEN_SYMBOLS
-
-
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup RTC_Driver RTC Driver
- @{
-*/
-
-/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
- @{
-*/
-
-/**
- * @brief Initialize RTC module and start counting
- *
- * @param[in] sPt Specify the time property and current date and time. It includes: \n
- * u32Year: Year value, range between 2000 ~ 2099. \n
- * u32Month: Month value, range between 1 ~ 12. \n
- * u32Day: Day value, range between 1 ~ 31. \n
- * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
- * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
- * RTC_SATURDAY] \n
- * u32Hour: Hour value, range between 0 ~ 23. \n
- * u32Minute: Minute value, range between 0 ~ 59. \n
- * u32Second: Second value, range between 0 ~ 59. \n
- * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
- * u8AmPm: [RTC_AM / RTC_PM] \n
- *
- * @return None
- *
- * @details This function is used to: \n
- * 1. Write initial key to let RTC start count. \n
- * 2. Input parameter indicates start date/time. \n
- * 3. User has to make sure that parameters of RTC date/time are reasonable. \n
- * @note Null pointer for using default starting date/time.
- */
-void RTC_Open(S_RTC_TIME_DATA_T *sPt)
-{
- RTC->INIT = RTC_INIT_KEY;
-
- if(RTC->INIT != RTC_INIT_ACTIVE_Msk)
- {
- RTC->INIT = RTC_INIT_KEY;
- while(RTC->INIT != RTC_INIT_ACTIVE_Msk);
- }
-
- if(sPt == 0)
- return ;
-
- /* Set RTC date and time */
- RTC_SetDateAndTime(sPt);
-
- /* Waiting for RTC settings stable */
- while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == RTC_RWEN_RWENF_Msk);
-}
-
-/**
- * @brief Disable RTC Clock
- *
- * @param None
- *
- * @return None
- *
- * @details This API will disable RTC peripheral clock and stops RTC counting.
- */
-void RTC_Close(void)
-{
- CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
-}
-
-/**
- * @brief Set 32k Frequency Compensation Data
- *
- * @param[in] i32FrequencyX100 Specify the RTC clock X100, ex: 3277365 means 32773.65.
- *
- * @return None
- *
- * @details This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application.
- */
-void RTC_32KCalibration(int32_t i32FrequencyX100)
-{
- int32_t i32RegInt, i32RegFra;
-
- /* Compute integer and fraction for RTC FCR register */
- i32RegInt = (i32FrequencyX100 / 100) - RTC_FCR_REFERENCE;
- i32RegFra = (((i32FrequencyX100 % 100)) * 60) / 100;
-
- /* Judge Integer part is reasonable */
- if((i32RegInt < 0) | (i32RegInt > 15))
- {
- return ;
- }
-
- RTC_WaitAccessEnable();
- RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra);
-}
-
-/**
- * @brief Get Current RTC Date and Time
- *
- * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n
- * u32Year: Year value \n
- * u32Month: Month value \n
- * u32Day: Day value \n
- * u32DayOfWeek: Day of week \n
- * u32Hour: Hour value \n
- * u32Minute: Minute value \n
- * u32Second: Second value \n
- * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
- * u8AmPm: [RTC_AM / RTC_PM] \n
- *
- * @return None
- *
- * @details This API is used to get the current RTC date and time value.
- */
-void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32Tmp;
-
- sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
- sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
-
- /* Get [Date digit] data */
- g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
- g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
- g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
- g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
- g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
- g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
-
- /* Get [Time digit] data */
- g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
- g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
- g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
- g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
- g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
- g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
-
- /* Compute to 20XX year */
- u32Tmp = (g_u32hiYear * 10);
- u32Tmp += g_u32loYear;
- sPt->u32Year = u32Tmp + RTC_YEAR2000;
-
- /* Compute 0~12 month */
- u32Tmp = (g_u32hiMonth * 10);
- sPt->u32Month = u32Tmp + g_u32loMonth;
-
- /* Compute 0~31 day */
- u32Tmp = (g_u32hiDay * 10);
- sPt->u32Day = u32Tmp + g_u32loDay;
-
- /* Compute 12/24 hour */
- if(sPt->u32TimeScale == RTC_CLOCK_12)
- {
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp += g_u32loHour;
- sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
-
- if(sPt->u32Hour >= 21)
- {
- sPt->u32AmPm = RTC_PM;
- sPt->u32Hour -= 20;
- }
- else
- {
- sPt->u32AmPm = RTC_AM;
- }
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp += g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp += g_u32loSec;
- sPt->u32Second = u32Tmp;
- }
- else
- {
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp += g_u32loHour;
- sPt->u32Hour = u32Tmp;
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp += g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp += g_u32loSec;
- sPt->u32Second = u32Tmp;
- }
-}
-
-/**
- * @brief Get RTC Alarm Date and Time
- *
- * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n
- * u32Year: Year value \n
- * u32Month: Month value \n
- * u32Day: Day value \n
- * u32DayOfWeek: Day of week \n
- * u32Hour: Hour value \n
- * u32Minute: Minute value \n
- * u32Second: Second value \n
- * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
- * u8AmPm: [RTC_AM / RTC_PM] \n
- *
- * @return None
- *
- * @details This API is used to get the RTC alarm date and time setting.
- */
-void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32Tmp;
-
- sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
- sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
-
- /* Get alarm [Date digit] data */
- RTC_WaitAccessEnable();
- g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
- g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
- g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
- g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
- g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
- g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
-
- /* Get alarm [Time digit] data */
- RTC_WaitAccessEnable();
- g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
- g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
- g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
- g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
- g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
- g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
-
- /* Compute to 20XX year */
- u32Tmp = (g_u32hiYear * 10);
- u32Tmp += g_u32loYear;
- sPt->u32Year = u32Tmp + RTC_YEAR2000;
-
- /* Compute 0~12 month */
- u32Tmp = (g_u32hiMonth * 10);
- sPt->u32Month = u32Tmp + g_u32loMonth;
-
- /* Compute 0~31 day */
- u32Tmp = (g_u32hiDay * 10);
- sPt->u32Day = u32Tmp + g_u32loDay;
-
- /* Compute 12/24 hour */
- if(sPt->u32TimeScale == RTC_CLOCK_12)
- {
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp += g_u32loHour;
- sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
-
- if(sPt->u32Hour >= 21)
- {
- sPt->u32AmPm = RTC_PM;
- sPt->u32Hour -= 20;
- }
- else
- {
- sPt->u32AmPm = RTC_AM;
- }
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp += g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp += g_u32loSec;
- sPt->u32Second = u32Tmp;
-
- }
- else
- {
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp += g_u32loHour;
- sPt->u32Hour = u32Tmp;
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp += g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp += g_u32loSec;
- sPt->u32Second = u32Tmp;
- }
-}
-
-/**
- * @brief Update Current RTC Date and Time
- *
- * @param[in] sPt Specify the time property and current date and time. It includes: \n
- * u32Year: Year value, range between 2000 ~ 2099. \n
- * u32Month: Month value, range between 1 ~ 12. \n
- * u32Day: Day value, range between 1 ~ 31. \n
- * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
- * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
- * RTC_SATURDAY] \n
- * u32Hour: Hour value, range between 0 ~ 23. \n
- * u32Minute: Minute value, range between 0 ~ 59. \n
- * u32Second: Second value, range between 0 ~ 59. \n
- * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
- * u8AmPm: [RTC_AM / RTC_PM] \n
- *
- * @return None
- *
- * @details This API is used to update current date and time to RTC.
- */
-void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32RegCAL, u32RegTIME;
-
- if(sPt == 0)
- return ;
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC 24/12 hour setting and Day of the Week */
- /*-----------------------------------------------------------------------------------------------------*/
- RTC_WaitAccessEnable();
- if(sPt->u32TimeScale == RTC_CLOCK_12)
- {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
-
- /*-------------------------------------------------------------------------------------------------*/
- /* Important, range of 12-hour PM mode is 21 up to 32 */
- /*-------------------------------------------------------------------------------------------------*/
- if(sPt->u32AmPm == RTC_PM)
- sPt->u32Hour += 20;
- }
- else
- {
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- /* Set Day of the Week */
- RTC->WEEKDAY = sPt->u32DayOfWeek;
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC Current Date and Time */
- /*-----------------------------------------------------------------------------------------------------*/
- u32RegCAL = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
- u32RegCAL |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
- u32RegCAL |= ((sPt->u32Month / 10) << 12);
- u32RegCAL |= ((sPt->u32Month % 10) << 8);
- u32RegCAL |= ((sPt->u32Day / 10) << 4);
- u32RegCAL |= (sPt->u32Day % 10);
-
- u32RegTIME = ((sPt->u32Hour / 10) << 20);
- u32RegTIME |= ((sPt->u32Hour % 10) << 16);
- u32RegTIME |= ((sPt->u32Minute / 10) << 12);
- u32RegTIME |= ((sPt->u32Minute % 10) << 8);
- u32RegTIME |= ((sPt->u32Second / 10) << 4);
- u32RegTIME |= (sPt->u32Second % 10);
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC Calender and Time Loading */
- /*-----------------------------------------------------------------------------------------------------*/
- RTC_WaitAccessEnable();
- RTC->CAL = (uint32_t)u32RegCAL;
- RTC->TIME = (uint32_t)u32RegTIME;
-}
-
-/**
- * @brief Update RTC Alarm Date and Time
- *
- * @param[in] sPt Specify the time property and alarm date and time. It includes: \n
- * u32Year: Year value, range between 2000 ~ 2099. \n
- * u32Month: Month value, range between 1 ~ 12. \n
- * u32Day: Day value, range between 1 ~ 31. \n
- * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
- * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
- * RTC_SATURDAY] \n
- * u32Hour: Hour value, range between 0 ~ 23. \n
- * u32Minute: Minute value, range between 0 ~ 59. \n
- * u32Second: Second value, range between 0 ~ 59. \n
- * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n
- * u8AmPm: [RTC_AM / RTC_PM] \n
- *
- * @return None
- *
- * @details This API is used to update alarm date and time setting to RTC.
- */
-void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32RegCALM, u32RegTALM;
-
- if(sPt == 0)
- return ;
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC 24/12 hour setting and Day of the Week */
- /*-----------------------------------------------------------------------------------------------------*/
- RTC_WaitAccessEnable();
- if(sPt->u32TimeScale == RTC_CLOCK_12)
- {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
-
- /*-------------------------------------------------------------------------------------------------*/
- /* Important, range of 12-hour PM mode is 21 up to 32 */
- /*-------------------------------------------------------------------------------------------------*/
- if(sPt->u32AmPm == RTC_PM)
- sPt->u32Hour += 20;
- }
- else
- {
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- /* Set Day of the Week */
- RTC->WEEKDAY = sPt->u32DayOfWeek;
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC Alarm Date and Time */
- /*-----------------------------------------------------------------------------------------------------*/
- u32RegCALM = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
- u32RegCALM |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
- u32RegCALM |= ((sPt->u32Month / 10) << 12);
- u32RegCALM |= ((sPt->u32Month % 10) << 8);
- u32RegCALM |= ((sPt->u32Day / 10) << 4);
- u32RegCALM |= (sPt->u32Day % 10);
-
- u32RegTALM = ((sPt->u32Hour / 10) << 20);
- u32RegTALM |= ((sPt->u32Hour % 10) << 16);
- u32RegTALM |= ((sPt->u32Minute / 10) << 12);
- u32RegTALM |= ((sPt->u32Minute % 10) << 8);
- u32RegTALM |= ((sPt->u32Second / 10) << 4);
- u32RegTALM |= (sPt->u32Second % 10);
-
- RTC_WaitAccessEnable();
- RTC->CALM = (uint32_t)u32RegCALM;
- RTC->TALM = (uint32_t)u32RegTALM;
-}
-
-/**
- * @brief Update RTC Current Date
- *
- * @param[in] u32Year The year calendar digit of current RTC setting.
- * @param[in] u32Month The month calendar digit of current RTC setting.
- * @param[in] u32Day The day calendar digit of current RTC setting.
- * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
- * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
- * RTC_SATURDAY]
- *
- * @return None
- *
- * @details This API is used to update current date to RTC.
- */
-void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
-{
- uint32_t u32RegCAL;
-
- u32RegCAL = ((u32Year - RTC_YEAR2000) / 10) << 20;
- u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10) << 16);
- u32RegCAL |= ((u32Month / 10) << 12);
- u32RegCAL |= ((u32Month % 10) << 8);
- u32RegCAL |= ((u32Day / 10) << 4);
- u32RegCAL |= (u32Day % 10);
-
- RTC_WaitAccessEnable();
-
- /* Set Day of the Week */
- RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
-
- /* Set RTC Calender Loading */
- RTC->CAL = (uint32_t)u32RegCAL;
-}
-
-/**
- * @brief Update RTC Current Time
- *
- * @param[in] u32Hour The hour time digit of current RTC setting.
- * @param[in] u32Minute The minute time digit of current RTC setting.
- * @param[in] u32Second The second time digit of current RTC setting.
- * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
- * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
- *
- * @return None
- *
- * @details This API is used to update current time to RTC.
- */
-void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
-{
- uint32_t u32RegTIME;
-
- /* Important, range of 12-hour PM mode is 21 up to 32 */
- if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
- u32Hour += 20;
-
- u32RegTIME = ((u32Hour / 10) << 20);
- u32RegTIME |= ((u32Hour % 10) << 16);
- u32RegTIME |= ((u32Minute / 10) << 12);
- u32RegTIME |= ((u32Minute % 10) << 8);
- u32RegTIME |= ((u32Second / 10) << 4);
- u32RegTIME |= (u32Second % 10);
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC 24/12 hour setting and Day of the Week */
- /*-----------------------------------------------------------------------------------------------------*/
- RTC_WaitAccessEnable();
- if(u32TimeMode == RTC_CLOCK_12)
- {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
- }
- else
- {
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- RTC->TIME = (uint32_t)u32RegTIME;
-}
-
-/**
- * @brief Update RTC Alarm Date
- *
- * @param[in] u32Year The year calendar digit of RTC alarm setting.
- * @param[in] u32Month The month calendar digit of RTC alarm setting.
- * @param[in] u32Day The day calendar digit of RTC alarm setting.
- *
- * @return None
- *
- * @details This API is used to update alarm date setting to RTC.
- */
-void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
-{
- uint32_t u32RegCALM;
-
- u32RegCALM = ((u32Year - RTC_YEAR2000) / 10) << 20;
- u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10) << 16);
- u32RegCALM |= ((u32Month / 10) << 12);
- u32RegCALM |= ((u32Month % 10) << 8);
- u32RegCALM |= ((u32Day / 10) << 4);
- u32RegCALM |= (u32Day % 10);
-
- RTC_WaitAccessEnable();
-
- /* Set RTC Alarm Date */
- RTC->CALM = (uint32_t)u32RegCALM;
-}
-
-/**
- * @brief Update RTC Alarm Time
- *
- * @param[in] u32Hour The hour time digit of RTC alarm setting.
- * @param[in] u32Minute The minute time digit of RTC alarm setting.
- * @param[in] u32Second The second time digit of RTC alarm setting.
- * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
- * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
- *
- * @return None
- *
- * @details This API is used to update alarm time setting to RTC.
- */
-void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
-{
- uint32_t u32RegTALM;
-
- /* Important, range of 12-hour PM mode is 21 up to 32 */
- if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
- u32Hour += 20;
-
- u32RegTALM = ((u32Hour / 10) << 20);
- u32RegTALM |= ((u32Hour % 10) << 16);
- u32RegTALM |= ((u32Minute / 10) << 12);
- u32RegTALM |= ((u32Minute % 10) << 8);
- u32RegTALM |= ((u32Second / 10) << 4);
- u32RegTALM |= (u32Second % 10);
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC 24/12 hour setting and Day of the Week */
- /*-----------------------------------------------------------------------------------------------------*/
- RTC_WaitAccessEnable();
- if(u32TimeMode == RTC_CLOCK_12)
- {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
- }
- else
- {
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- /* Set RTC Alarm Time */
- RTC->TALM = (uint32_t)u32RegTALM;
-}
-
-/**
- * @brief Get Day of the Week
- *
- * @param None
- *
- * @retval 0 Sunday
- * @retval 1 Monday
- * @retval 2 Tuesday
- * @retval 3 Wednesday
- * @retval 4 Thursday
- * @retval 5 Friday
- * @retval 6 Saturday
- *
- * @details This API is used to get day of the week of current RTC date.
- */
-uint32_t RTC_GetDayOfWeek(void)
-{
- return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
-}
-
-/**
- * @brief Set RTC Tick Period Time
- *
- * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n
- * It consists of: \n
- * RTC_TICK_1_SEC: Time tick is 1 second \n
- * RTC_TICK_1_2_SEC: Time tick is 1/2 second \n
- * RTC_TICK_1_4_SEC: Time tick is 1/4 second \n
- * RTC_TICK_1_8_SEC: Time tick is 1/8 second \n
- * RTC_TICK_1_16_SEC: Time tick is 1/16 second \n
- * RTC_TICK_1_32_SEC: Time tick is 1/32 second \n
- * RTC_TICK_1_64_SEC: Time tick is 1/64 second \n
- * RTC_TICK_1_128_SEC: Time tick is 1/128 second
- *
- * @return None
- *
- * @details This API is used to set RTC tick period time for each tick interrupt.
- */
-void RTC_SetTickPeriod(uint32_t u32TickSelection)
-{
- RTC_WaitAccessEnable();
-
- RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
-}
-
-/**
- * @brief Enable RTC Interrupt
- *
- * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: \n
- * RTC_INTEN_ALMIEN_Msk: Alarm interrupt \n
- * RTC_INTEN_TICKIEN_Msk: Tick interrupt \n
- * RTC_INTEN_SNPDIEN_Msk: Snooper Pin Event Detection interrupt \n
- *
- * @return None
- *
- * @details This API is used to enable the specify RTC interrupt function.
- */
-void RTC_EnableInt(uint32_t u32IntFlagMask)
-{
- RTC->INTEN |= u32IntFlagMask;
-}
-
-/**
- * @brief Disable RTC Interrupt
- *
- * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: \n
- * RTC_INTEN_ALMIEN_Msk: Alarm interrupt \n
- * RTC_INTEN_TICKIEN_Msk: Tick interrupt \n
- * RTC_INTEN_SNPDIEN_Msk: Snooper Pin Event Detection interrupt \n
- *
- * @return None
- *
- * @details This API is used to disable the specify RTC interrupt function.
- */
-void RTC_DisableInt(uint32_t u32IntFlagMask)
-{
- if(u32IntFlagMask & RTC_INTEN_ALMIEN_Msk)
- {
- RTC->INTEN &= ~RTC_INTEN_ALMIEN_Msk;
- RTC->INTSTS = RTC_INTSTS_ALMIF_Msk;
- }
-
- if(u32IntFlagMask & RTC_INTEN_TICKIEN_Msk)
- {
- RTC->INTEN &= ~RTC_INTEN_TICKIEN_Msk;
- RTC->INTSTS = RTC_INTSTS_TICKIF_Msk;
- }
-
- if(u32IntFlagMask & RTC_INTEN_SNPDIEN_Msk)
- {
- RTC->INTEN &= ~RTC_INTEN_SNPDIEN_Msk;
- RTC->INTSTS = RTC_INTSTS_SNPDIF_Msk;
- }
-}
-
-/**
- * @brief Enable Spare Registers Access
- *
- * @param None
- *
- * @return None
- *
- * @details This API is used to enable the spare registers 0~19 can be accessed.
- */
-void RTC_EnableSpareAccess(void)
-{
- RTC_WaitAccessEnable();
-
- RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
-
- while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
-}
-
-/**
- * @brief Disable Spare Register
- *
- * @param None
- *
- * @return None
- *
- * @details This API is used to disable the spare register 0~19 cannot be accessed.
- */
-void RTC_DisableSpareRegister(void)
-{
- RTC_WaitAccessEnable();
-
- RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
-}
-
-/**
- * @brief Enable Snooper Pin Detect
- *
- * @param[in] u32PinCondition Snooper pin trigger condition. Possible options are
- * - \ref RTC_SNOOPER_LOW_LEVEL
- * - \ref RTC_SNOOPER_HIGH_LEVEL
- * - \ref RTC_SNOOPER_FALLING_EDGE
- * - \ref RTC_SNOOPER_RISING_EDGE
- *
- * @return None
- *
- * @details This API is used to enable the snooper pin detect function with specify trigger condition.
- */
-void RTC_EnableSnooperDetection(uint32_t u32PinCondition)
-{
- RTC_WaitAccessEnable();
-
- RTC->SPRCTL = ((RTC->SPRCTL & ~RTC_SNOOPER_DETECT_Msk) | u32PinCondition) | RTC_SPRCTL_SNPDEN_Msk;
-}
-
-/**
- * @brief Disable Snooper Pin Detect
- *
- * @param None
- *
- * @return None
- *
- * @details This API is used to disable the snooper pin detect function.
- */
-void RTC_DisableSnooperDetection(void)
-{
- RTC_WaitAccessEnable();
-
- RTC->SPRCTL &= ~RTC_SPRCTL_SNPDEN_Msk;
-}
-
-/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group RTC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_rtc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,272 +0,0 @@
-/**************************************************************************//**
- * @file rtc.h
- * @version V3.00
- * $Revision: 10 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series RTC driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __RTC_H__
-#define __RTC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup RTC_Driver RTC Driver
- @{
-*/
-
-/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* RTC Initial Keyword Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state */
-#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* RTC Time Attribute Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_CLOCK_12 0 /*!< RTC as 12-hour time scale with AM and PM indication */
-#define RTC_CLOCK_24 1 /*!< RTC as 24-hour time scale */
-#define RTC_AM 1 /*!< RTC as AM indication */
-#define RTC_PM 2 /*!< RTC as PM indication */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* RTC Tick Period Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second */
-#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second */
-#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second */
-#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second */
-#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second */
-#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second */
-#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second */
-#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* RTC Day of Week Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday */
-#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday */
-#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday */
-#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday */
-#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday */
-#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday */
-#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* RTC Snooper Detection Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_SNOOPER_LOW_LEVEL 0x0UL /*!< Snooper pin detected is low-level trigger */
-#define RTC_SNOOPER_HIGH_LEVEL 0x2UL /*!< Snooper pin detected is high-level trigger */
-#define RTC_SNOOPER_FALLING_EDGE 0x8UL /*!< Snooper pin detected is falling-edge trigger */
-#define RTC_SNOOPER_RISING_EDGE 0xAUL /*!< Snooper pin detected is rising-edge trigger */
-#define RTC_SNOOPER_DETECT_Msk 0xAUL /*!< Snooper pin detected mask bits */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* RTC Miscellaneous Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_WAIT_COUNT 0xFFFFFFFF /*!< Initial Time-out Value */
-#define RTC_YEAR2000 2000 /*!< RTC Reference for compute year data */
-#define RTC_FCR_REFERENCE 32761 /*!< RTC Reference for frequency compensation */
-
-/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
- @{
-*/
-/**
- * @details RTC define Time Data Struct
- */
-typedef struct
-{
- uint32_t u32Year; /*!< Year value */
- uint32_t u32Month; /*!< Month value */
- uint32_t u32Day; /*!< Day value */
- uint32_t u32DayOfWeek; /*!< Day of week value */
- uint32_t u32Hour; /*!< Hour value */
- uint32_t u32Minute; /*!< Minute value */
- uint32_t u32Second; /*!< Second value */
- uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
- uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
-} S_RTC_TIME_DATA_T;
-
-/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
-
-
-/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
- @{
-*/
-
-/**
- * @brief Indicate is Leap Year or not
- *
- * @param None
- *
- * @retval 0 This year is not a leap year
- * @retval 1 This year is a leap year
- *
- * @details According to current date, return this year is leap year or not.
- */
-#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
-
-/**
- * @brief Clear RTC Alarm Interrupt Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro is used to clear RTC alarm interrupt flag.
- */
-#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_TICKIF_Msk | RTC_INTSTS_SNPDIF_Msk)) | RTC_INTSTS_ALMIF_Msk)
-
-/**
- * @brief Clear RTC Tick Interrupt Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro is used to clear RTC tick interrupt flag.
- */
-#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_ALMIF_Msk | RTC_INTSTS_SNPDIF_Msk)) | RTC_INTSTS_TICKIF_Msk)
-
-/**
- * @brief Clear RTC Snooper Interrupt Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro is used to clear RTC snooper pin interrupt flag.
- */
-#define RTC_CLEAR_SNOOPER_INT_FLAG() (RTC->INTSTS = (RTC->INTSTS & ~(RTC_INTSTS_ALMIF_Msk | RTC_INTSTS_TICKIF_Msk)) | RTC_INTSTS_SNPDIF_Msk)
-
-/**
- * @brief Get RTC Alarm Interrupt Flag
- *
- * @param None
- *
- * @retval 0 RTC alarm interrupt did not occur
- * @retval 1 RTC alarm interrupt occurred
- *
- * @details This macro indicates RTC alarm interrupt occurred or not.
- */
-#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
-
-/**
- * @brief Get RTC Time Tick Interrupt Flag
- *
- * @param None
- *
- * @retval 0 RTC time tick interrupt did not occur
- * @retval 1 RTC time tick interrupt occurred
- *
- * @details This macro indicates RTC time tick interrupt occurred or not.
- */
-#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
-
-/**
- * @brief Get RTC Snooper Interrupt Flag
- *
- * @param None
- *
- * @retval 0 RTC snooper pin interrupt did not occur
- * @retval 1 RTC snooper pin interrupt occurred
- *
- * @details This macro indicates RTC snooper pin interrupt occurred or not.
- */
-#define RTC_GET_SNPPOER_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_SNPDIF_Msk)? 1:0)
-
-/**
- * @brief Read Spare Register
- *
- * @param[in] u32RegNum The spare register number, 0~19.
- *
- * @return Spare register content
- *
- * @details Read the specify spare register content.
- * @note The returned value is valid only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
- * And its controlled by RTC Access Enable Register.
- */
-#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)])
-
-/**
- * @brief Write Spare Register
- *
- * @param[in] u32RegNum The spare register number, 0~19.
- * @param[in] u32RegValue The spare register value.
- *
- * @return None
- *
- * @details Write specify data to spare register.
- * @note This macro is effect only when SPRRDY(SPRCTL[7] SPR Register Ready) bit is set. \n
- * And its controlled by RTC Access Enable Register(RTC_RWEN).
- */
-#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue))
-
-/**
- * @brief Wait RTC Access Enable
- *
- * @param None
- *
- * @return None
- *
- * @details This function is used to enable the maximum RTC read/write accessible time.
- */
-static __INLINE void RTC_WaitAccessEnable(void)
-{
- /* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
- while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == RTC_RWEN_RWENF_Msk);
- RTC->RWEN = RTC_WRITE_KEY;
-
- /* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
- while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0);
-}
-
-void RTC_Open(S_RTC_TIME_DATA_T *sPt);
-void RTC_Close(void);
-void RTC_32KCalibration(int32_t i32FrequencyX100);
-void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
-void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
-void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
-void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
-void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
-void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
-void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
-void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
-uint32_t RTC_GetDayOfWeek(void);
-void RTC_SetTickPeriod(uint32_t u32TickSelection);
-void RTC_EnableInt(uint32_t u32IntFlagMask);
-void RTC_DisableInt(uint32_t u32IntFlagMask);
-void RTC_EnableSpareAccess(void);
-void RTC_DisableSpareRegister(void);
-void RTC_EnableSnooperDetection(uint32_t u32PinCondition);
-void RTC_DisableSnooperDetection(void);
-
-/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group RTC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__RTC_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,299 +0,0 @@
-/**************************************************************************//**
- * @file sc.c
- * @version V3.00
- * $Revision: 9 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series Smartcard(SC) driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-// Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined
-/// @cond HIDDEN_SYMBOLS
-static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0};
-
-/// @endcond HIDDEN_SYMBOLS
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SC_Driver SC Driver
- @{
-*/
-
-
-/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
- @{
-*/
-
-/**
- * @brief This function indicates specified smartcard slot status.
- * @param[in] sc The pointer of smartcard module.
- * @retval TRUE Card insert.
- * @retval FALSE Card remove.
- * @details This function is used to check if specified smart card slot is presented.
- */
-uint32_t SC_IsCardInserted(SC_T *sc)
-{
- // put conditions into two variable to remove IAR compilation warning
- uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
- uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
-
- if(sc == SC0 && u32CardStateIgnore[0] == 1)
- return TRUE;
-#if 0 /* M451 series has only one SC interface */
- else if(sc == SC1 && u32CardStateIgnore[1] == 1)
- return TRUE;
- else if(sc == SC2 && u32CardStateIgnore[2] == 1)
- return TRUE;
- else if(sc == SC3 && u32CardStateIgnore[3] == 1)
- return TRUE;
- else if(sc == SC4 && u32CardStateIgnore[4] == 1)
- return TRUE;
- else if(sc == SC5 && u32CardStateIgnore[5] == 1)
- return TRUE;
-#endif
- else if(cond1 != cond2)
- return FALSE;
- else
- return TRUE;
-}
-
-/**
- * @brief Reset the Tx/Rx FIFO.
- * @param[in] sc The pointer of smartcard module.
- * @return None
- * @details This function reset both transmit and receive FIFO of specified smartcard module.
- */
-void SC_ClearFIFO(SC_T *sc)
-{
- sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
-}
-
-/**
- * @brief This function disable specified smartcard module.
- * @param[in] sc The pointer of smartcard module.
- * @return None
- * @details SC will force all transition to IDLE state.
- */
-void SC_Close(SC_T *sc)
-{
- sc->INTEN = 0;
- sc->PINCTL = 0;
- sc->ALTCTL = 0;
- sc->CTL = 0;
-}
-
-/**
- * @brief This function initialized smartcard module.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card insert. Could be:
- * -\ref SC_PIN_STATE_HIGH.
- * -\ref SC_PIN_STATE_LOW.
- * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present.
- * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be:
- * -\ref SC_PIN_STATE_HIGH.
- * -\ref SC_PIN_STATE_LOW.
- * @return None
- * @details Initialization process configures smartcard and enables engine clock.
- */
-void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR)
-{
- uint32_t u32Reg = 0, u32Intf;
-
- if(sc == SC0)
- u32Intf = 0;
-#if 0 /* M451 series has only one SC interface */
- else if(sc == SC1)
- u32Intf = 1;
- else if(sc == SC2)
- u32Intf = 2;
- else if(sc == SC3)
- u32Intf = 3;
- else if(sc == SC4)
- u32Intf = 4;
- else if(sc == SC5)
- u32Intf = 5;
-#endif
- else
- return ;
-
- if(u32CD != SC_PIN_STATE_IGNORE) {
- u32Reg = u32CD ? 0: SC_CTL_CDLV_Msk;
- u32CardStateIgnore[u32Intf] = 0;
- } else {
- u32CardStateIgnore[u32Intf] = 1;
- }
- while(sc->PINCTL & SC_PINCTL_SYNC_Msk);
- sc->PINCTL = u32PWR ? 0 : SC_PINCTL_PWRINV_Msk;
- while(sc->CTL & SC_CTL_SYNC_Msk);
- sc->CTL = SC_CTL_SCEN_Msk | u32Reg;
-}
-
-/**
- * @brief This function reset specified smartcard module to its default state for activate smartcard.
- * @param[in] sc The pointer of smartcard module.
- * @return None
- * @details Reset the Tx/Rx FIFO & clock & initial default parameter.
- */
-void SC_ResetReader(SC_T *sc)
-{
- uint32_t u32Intf;
-
- if(sc == SC0)
- u32Intf = 0;
-#if 0 /* M451 series has only one SC interface */
- else if(sc == SC1)
- u32Intf = 1;
- else if(sc == SC2)
- u32Intf = 2;
- else if(sc == SC3)
- u32Intf = 3;
- else if(sc == SC4)
- u32Intf = 4;
- else if(sc == SC5)
- u32Intf = 5;
-#endif
- else
- return ;
-
- // Reset FIFO, enable auto de-activation while card removal
- sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
- // Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry)
- while(sc->CTL & SC_CTL_SYNC_Msk);
- sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | SC_CTL_CDDBSEL_Msk | SC_CTL_TXRTY_Msk | SC_CTL_RXRTY_Msk);
- // Enable auto convention, and all three smartcard internal timers
- sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
- // Disable Rx timeout
- sc->RXTOUT = 0;
- // 372 clocks per ETU by default
- sc->ETUCTL = 371;
-
- /* Enable necessary interrupt for smartcard operation */
- if(u32CardStateIgnore[u32Intf]) // Do not enable card detect interrupt if card present state ignore
- sc->INTEN = (SC_INTEN_RDAIEN_Msk |
- SC_INTEN_TERRIEN_Msk |
- SC_INTEN_TMR0IEN_Msk |
- SC_INTEN_TMR1IEN_Msk |
- SC_INTEN_TMR2IEN_Msk |
- SC_INTEN_BGTIEN_Msk |
- SC_INTEN_ACERRIEN_Msk);
- else
- sc->INTEN = (SC_INTEN_RDAIEN_Msk |
- SC_INTEN_TERRIEN_Msk |
- SC_INTEN_TMR0IEN_Msk |
- SC_INTEN_TMR1IEN_Msk |
- SC_INTEN_TMR2IEN_Msk |
- SC_INTEN_BGTIEN_Msk |
- SC_INTEN_ACERRIEN_Msk |
- SC_INTEN_CDIEN_Msk);
-
- return;
-}
-
-/**
- * @brief Set Block Guard Time.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32.
- * @return None
- * @details This function block guard time (BGT) of specified smartcard module.
- */
-void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
-{
- sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1) << SC_CTL_BGT_Pos);
-}
-
-/**
- * @brief Set character guard time.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267.
- * @return None
- * @details This function character guard time (CGT) of specified smartcard module.
- * @note Before using this API, user should set the correct stop bit length first.
- */
-void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
-{
- u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11 : 12;
- sc->EGT = u32CGT;
-}
-
-/**
- * @brief Stop all Timer counting.
- * @param[in] sc The pointer of smartcard module.
- * @return None
- * @details This function stop all smartcard timer of specified smartcard module.
- * @note This function stop the timers within smartcard module, \b not timer module.
- */
-void SC_StopAllTimer(SC_T *sc)
-{
- sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
-}
-
-/**
- * @brief This function configure and start a smartcard timer of specified smartcard module.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2.
- * @param[in] u32Mode Timer operating mode, valid values are:
- * - \ref SC_TMR_MODE_0
- * - \ref SC_TMR_MODE_1
- * - \ref SC_TMR_MODE_2
- * - \ref SC_TMR_MODE_3
- * - \ref SC_TMR_MODE_4
- * - \ref SC_TMR_MODE_5
- * - \ref SC_TMR_MODE_6
- * - \ref SC_TMR_MODE_7
- * - \ref SC_TMR_MODE_8
- * - \ref SC_TMR_MODE_F
- * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs.
- * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs.
- * @return None
- * @details Enable Timer starting, counter will count when condition match.
- * @note This function start the timer within smartcard module, \b not timer module.
- * @note Depend on the timer operating mode, timer may not start counting immediately.
- */
-void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
-{
- uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1));
-
- if(u32TimerNum == 0) {
- sc->TMRCTL0 = reg;
- sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
- } else if(u32TimerNum == 1) {
- sc->TMRCTL1 = reg;
- sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
- } else { // timer 2
- sc->TMRCTL2 = reg;
- sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
- }
-}
-
-/**
- * @brief Stop Timer counting.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2.
- * @return None
- * @details This function stop a smartcard timer of specified smartcard module.
- * @note This function stop the timer within smartcard module, \b not timer module.
- */
-void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
-{
- if(u32TimerNum == 0)
- sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
- else if(u32TimerNum == 1)
- sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
- else // timer 2
- sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
-}
-
-
-
-/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,269 +0,0 @@
-/**************************************************************************//**
- * @file sc.h
- * @version V3.00
- * $Revision: 13 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series Smartcard (SC) driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __SC_H__
-#define __SC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SC_Driver SC Driver
- @{
-*/
-
-/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
- @{
-*/
-#define SC_INTERFACE_NUM 1 /*!< Smartcard interface numbers */ /* M451 series has only one SC interface */
-#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high */
-#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low */
-#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status */
-#define SC_CLK_ON 1 /*!< Smartcard clock on */
-#define SC_CLK_OFF 0 /*!< Smartcard clock off */
-
-#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 0, down count */
-#define SC_TMR_MODE_1 (1ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit */
-#define SC_TMR_MODE_2 (2ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit */
-#define SC_TMR_MODE_3 (3ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode */
-#define SC_TMR_MODE_4 (4ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout */
-#define SC_TMR_MODE_5 (5ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout */
-#define SC_TMR_MODE_6 (6ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout */
-#define SC_TMR_MODE_7 (7ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit */
-#define SC_TMR_MODE_8 (8ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 8, up count */
-#define SC_TMR_MODE_F (0xF << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit */
-
-
-/*@}*/ /* end of group SC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
- @{
-*/
-
-/**
- * @brief Enable smartcard interrupt.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Mask Interrupt mask to be enabled. A combination of
- * - \ref SC_INTEN_ACERRIEN_Msk
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_INITIEN_Msk
- * - \ref SC_INTEN_CDIEN_Msk
- * - \ref SC_INTEN_BGTIEN_Msk
- * - \ref SC_INTEN_TMR2IEN_Msk
- * - \ref SC_INTEN_TMR1IEN_Msk
- * - \ref SC_INTEN_TMR0IEN_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * @details The macro is used to enable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
- * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
- * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
- * \hideinitializer
- */
-#define SC_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
-
-/**
- * @brief Disable smartcard interrupt.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Mask Interrupt mask to be disabled. A combination of
- * - \ref SC_INTEN_ACERRIEN_Msk
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_INITIEN_Msk
- * - \ref SC_INTEN_CDIEN_Msk
- * - \ref SC_INTEN_BGTIEN_Msk
- * - \ref SC_INTEN_TMR2IEN_Msk
- * - \ref SC_INTEN_TMR1IEN_Msk
- * - \ref SC_INTEN_TMR0IEN_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
- * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
- * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
- * \hideinitializer
- */
-#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
-
-/**
- * @brief This macro set VCC pin state of smartcard interface.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32State Pin state of VCC pin, valid parameters are:
- * \ref SC_PIN_STATE_HIGH :Smartcard pin status high.
- * \ref SC_PIN_STATE_LOW :Smartcard pin status low.
- * @return None
- * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
- * \hideinitializer
- */
-#define SC_SET_VCC_PIN(sc, u32State) \
- do {\
- while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32State)\
- (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
- else\
- (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
- }while(0)
-
-
-/**
- * @brief Set CLK output status.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are:
- * \ref SC_CLK_ON :Smartcard clock on.
- * \ref SC_CLK_OFF :Smartcard clock off.
- * @return None
- * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not.
- * \hideinitializer
- */
-#define SC_SET_CLK_PIN(sc, u32OnOff)\
- do {\
- while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32OnOff)\
- (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
- else\
- (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
- }while(0)
-
-/**
- * @brief Set I/O pin state.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32State Pin state of I/O pin, valid parameters are:
- * \ref SC_PIN_STATE_HIGH :Smartcard pin status high.
- * \ref SC_PIN_STATE_LOW :Smartcard pin status low.
- * @return None
- * @details User can set SCDOUT(SC_PINCTL[9]) to decide SCDOUT pin to high or low.
- * \hideinitializer
- */
-#define SC_SET_IO_PIN(sc, u32State)\
- do {\
- while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32State)\
- (sc)->PINCTL |= SC_PINCTL_SCDOUT_Msk;\
- else\
- (sc)->PINCTL &= ~SC_PINCTL_SCDOUT_Msk;\
- }while(0)
-
-/**
- * @brief Set RST pin state.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32State Pin state of RST pin, valid parameters are:
- * \ref SC_PIN_STATE_HIGH :Smartcard pin status high.
- * \ref SC_PIN_STATE_LOW :Smartcard pin status low.
- * @return None
- * @details User can set SCRST(SC_PINCTL[1]) to decide SCRST pin to high or low.
- * \hideinitializer
- */
-#define SC_SET_RST_PIN(sc, u32State)\
- do {\
- while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32State)\
- (sc)->PINCTL |= SC_PINCTL_SCRST_Msk;\
- else\
- (sc)->PINCTL &= ~SC_PINCTL_SCRST_Msk;\
- }while(0)
-
-/**
- * @brief Read one byte from smartcard module receive FIFO.
- * @param[in] sc The pointer of smartcard module.
- * @return One byte read from receive FIFO.
- * @details By reading DAT register, the SC will return an 8-bit received data.
- * \hideinitializer
- */
-#define SC_READ(sc) ((char)((sc)->DAT))
-
-/**
- * @brief Write one byte to smartcard module transmit FIFO.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u8Data Data to write to transmit FIFO.
- * @return None
- * @details By writing data to DAT register, the SC will send out an 8-bit data.
- * \hideinitializer
- */
-#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
-
-/**
- * @brief This macro set smartcard stop bit length.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Len Stop bit length, ether 1 or 2.
- * @return None
- * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
- * \hideinitializer
- */
-#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | ((u32Len) == 1 ? SC_CTL_NSB_Msk : 0))
-
-/**
- * @brief Enable/Disable Tx error retry, and set Tx error retry count.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry.
- * @return None
- * @details This macro enable/disable transmitter retry function when parity error has occurred, and set error retry count.
- */
-__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
-{
- while((sc)->CTL & SC_CTL_SYNC_Msk);
- if(u32Count == 0) { // disable Tx error retry
- (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
- } else {
- (sc)->CTL = ((sc)->CTL & ~SC_CTL_TXRTY_Msk) | ((u32Count - 1) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
- }
-}
-
-/**
- * @brief Enable/Disable Rx error retry, and set Rx error retry count.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry.
- * @return None
- * @details This macro enable/disable receiver retry function when parity error has occurred, and set error retry count.
- */
-__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
-{
- while((sc)->CTL & SC_CTL_SYNC_Msk);
- if(u32Count == 0) { // disable Rx error retry
- (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
- } else {
- (sc)->CTL = ((sc)->CTL & ~SC_CTL_RXRTY_Msk) | ((u32Count - 1) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
- }
-}
-
-
-uint32_t SC_IsCardInserted(SC_T *sc);
-void SC_ClearFIFO(SC_T *sc);
-void SC_Close(SC_T *sc);
-void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
-void SC_ResetReader(SC_T *sc);
-void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
-void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
-void SC_StopAllTimer(SC_T *sc);
-void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
-void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
-
-
-/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SC_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SC_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_scuart.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,223 +0,0 @@
-/**************************************************************************//**
- * @file scuart.c
- * @version V3.00
- * $Revision: 8 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series Smartcard UART mode (SCUART) driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SCUART_Driver SCUART Driver
- @{
-*/
-
-
-/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
- @{
-*/
-
-/**
- * @brief Disable smartcard uart interface.
- * @param sc The pointer of smartcard module.
- * @return None
- * @details The function is used to disable smartcard interface UART mode.
- */
-void SCUART_Close(SC_T* sc)
-{
- sc->INTEN = 0;
- sc->UARTCTL = 0;
- sc->CTL = 0;
-
-}
-
-/// @cond HIDDEN_SYMBOLS
-/**
- * @brief This function returns module clock of specified SC interface
- * @param[in] sc The pointer of smartcard module.
- * @return Module clock of specified SC interface
- */
-static uint32_t SCUART_GetClock(SC_T *sc)
-{
- uint32_t u32ClkSrc, u32Num, u32Clk;
-
- if(sc == SC0)
- u32Num = 0;
-#if 0 /* M451 series has only one SC interface */
- else if(sc == SC1)
- u32Num = 1;
- else if(sc == SC2)
- u32Num = 2;
- else if(sc == SC3)
- u32Num = 3;
- else if(sc == SC4)
- u32Num = 4;
- else if(sc == SC5)
- u32Intf = 5;
-#endif
- else
- return FALSE;
-
- u32ClkSrc = (CLK->CLKSEL3 >> (2 * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
-
- // Get smartcard module clock
- if(u32ClkSrc == 0)
- u32Clk = __HXT;
- else if(u32ClkSrc == 1)
- u32Clk = CLK_GetPLLClockFreq();
- else if(u32ClkSrc == 2) {
- SystemCoreClockUpdate();
- if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk)
- u32Clk = SystemCoreClock / 2;
- else
- u32Clk = SystemCoreClock;
- } else
- u32Clk = __HIRC;
-
-#if 0 /* M451 series has only one SC interface */
- if(u32Num < 4) {
- u32Clk /= (((CLK->CLKDIV1 >> (8 * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1);
- } else {
- u32Clk /= (((CLK->CLKDIV2 >> (8 * (u32Num - 4))) & CLK_CLKDIV2_SC4DIV_Msk) + 1);
- }
-#else
- u32Clk /= (((CLK->CLKDIV1 >> (8 * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1);
-#endif
-
- return u32Clk;
-}
-/// @endcond HIDDEN_SYMBOLS
-
-/**
- * @brief Enable smartcard uart interface.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32baudrate Target baudrate of smartcard module.
- * @return Actual baudrate of smartcard mode.
- * @details This function use to enable smartcard module UART mode and set baudrate.
- * @note This function configures character width to 8 bits, 1 stop bit, and no parity.
- * And can use \ref SCUART_SetLineConfig function to update these settings.
- */
-uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate)
-{
- uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
-
- // Calculate divider for target baudrate
- u32Div = (u32Clk + (u32baudrate >> 1) - 1) / u32baudrate - 1;
-
- sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; // Enable smartcard interface and stop bit = 1
- sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; // Enable UART mode, disable parity and 8 bit per character
- sc->ETUCTL = u32Div;
-
- return(u32Clk / (u32Div+1));
-}
-
-/**
- * @brief Read data from smartcard UART interface.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] pu8RxBuf The buffer to store receive the data.
- * @param[in] u32ReadBytes Target number of characters to receive.
- * @return Actual character number reads to buffer.
- * @details The function is used to read Rx data from RX FIFO.
- * @note This function does not block and return immediately if there's no data available.
- */
-uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
-{
- uint32_t u32Count;
-
- for(u32Count = 0; u32Count < u32ReadBytes; u32Count++) {
- if(SCUART_GET_RX_EMPTY(sc)) { // no data available
- break;
- }
- pu8RxBuf[u32Count] = SCUART_READ(sc); // get data from FIFO
- }
-
- return u32Count;
-}
-
-/**
- * @brief This function use to config smartcard UART mode line setting.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
- * @param[in] u32DataWidth The data length, could be:
- * - \ref SCUART_CHAR_LEN_5
- * - \ref SCUART_CHAR_LEN_6
- * - \ref SCUART_CHAR_LEN_7
- * - \ref SCUART_CHAR_LEN_8
- * @param[in] u32Parity The parity setting, could be:
- * - \ref SCUART_PARITY_NONE
- * - \ref SCUART_PARITY_ODD
- * - \ref SCUART_PARITY_EVEN
- * @param[in] u32StopBits The stop bit length, could be:
- * - \ref SCUART_STOP_BIT_1
- * - \ref SCUART_STOP_BIT_2
- * @return Actual baudrate of smartcard.
- * @details Smartcard UART mode is operated in LIN data frame.
- */
-uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
-{
-
- uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
-
- if(u32Baudrate == 0) { // keep original baudrate setting
- u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
- } else {
- // Calculate divider for target baudrate
- u32Div = (u32Clk + (u32Baudrate >> 1) - 1) / u32Baudrate - 1;
- sc->ETUCTL = u32Div;
- }
-
- sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; // Set stop bit
- sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; // Set character width and parity
-
- return(u32Clk / (u32Div+1));
-}
-
-/**
- * @brief This function use to set receive timeout count.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
- * set this value to 0 will disable timeout counter.
- * @return None
- * @details The time-out counter resets and starts counting whenever the RX buffer received a
- * new data word. Once the counter decrease to 1 and no new data is received or CPU
- * does not read any data from FIFO, a receiver time-out interrupt will be generated.
- */
-void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
-{
- sc->RXTOUT = u32TOC;
-}
-
-
-/**
- * @brief Write data to smartcard UART interface.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
- * @param[in] u32WriteBytes Number of data to send.
- * @return None
- * @details This function is to write data into transmit FIFO to send data out.
- * @note This function blocks until all data write into FIFO.
- */
-void SCUART_Write(SC_T* sc, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
-{
- uint32_t u32Count;
-
- for(u32Count = 0; u32Count != u32WriteBytes; u32Count++) {
- while(SCUART_GET_TX_FULL(sc)); // Wait 'til FIFO not full
- sc->DAT = pu8TxBuf[u32Count]; // Write 1 byte to FIFO
- }
-}
-
-
-/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SCUART_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_scuart.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,279 +0,0 @@
-/**************************************************************************//**
- * @file sc.h
- * @version V3.00
- * $Revision: 7 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series Smartcard UART mode (SCUART) driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __SCUART_H__
-#define __SCUART_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SCUART_Driver SCUART Driver
- @{
-*/
-
-/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
- @{
-*/
-#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits */
-#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits */
-#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits */
-#define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits */
-
-#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity */
-#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity */
-#define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity */
-
-#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit */
-#define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits */
-
-
-/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
- @{
-*/
-
-/* TX Macros */
-/**
- * @brief Write Data to Tx data register.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u8Data Data byte to transmit.
- * @return None
- * @details By writing data to DAT register, the SC will send out an 8-bit data.
- * \hideinitializer
- */
-#define SCUART_WRITE(sc, u8Data) ((sc)-> DAT = (u8Data))
-
-/**
- * @brief Get TX FIFO empty flag status from register.
- * @param[in] sc The pointer of smartcard module.
- * @return Transmit FIFO empty status.
- * @retval 0 Transmit FIFO is not empty.
- * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty.
- * @details When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY bit (SC_STATUS[9]) high.
- * It will be cleared when writing data into DAT (SC_DAT[7:0]).
- * \hideinitializer
- */
-#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
-
-/**
- * @brief Get TX FIFO full flag status from register.
- * @param[in] sc The pointer of smartcard module.
- * @retval 0 Transmit FIFO is not full.
- * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full.
- * @details TXFULL(SC_STATUS[10]) is set when TX pointer is equal to 4, otherwise is cleared by hardware.
- * \hideinitializer
- */
-#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
-
-/**
- * @brief Wait specified smartcard port transmission complete.
- * @param[in] sc The pointer of smartcard module.
- * @return None
- * @details TXACT (SC_STATUS[31]) is cleared automatically when TX transfer is finished or the last byte transmission has completed.
- * @note This macro blocks until transmit complete.
- * \hideinitializer
- */
-#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
-
-/**
- * @brief Check specified smartcard port transmit FIFO is full or not.
- * @param[in] sc The pointer of smartcard module.
- * @retval 0 Transmit FIFO is not full.
- * @retval 1 Transmit FIFO is full.
- * @details TXFULL(SC_STATUS[10]) indicates TX buffer full or not.
- * This is set when TX pointer is equal to 4, otherwise is cleared by hardware.
- * \hideinitializer
- */
-#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
-
-/**
- * @brief Check specified smartcard port transmission is over.
- * @param[in] sc The pointer of smartcard module.
- * @retval 0 Transmit is not complete.
- * @retval 1 Transmit complete.
- * @details TXACT (SC_STATUS[31]) is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
- * \hideinitializer
- */
-#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
-
-
-/* RX Macros */
-
-/**
- * @brief Read Rx data register.
- * @param[in] sc The pointer of smartcard module.
- * @return The oldest data byte in RX FIFO.
- * @details By reading DAT register, the SC will return an 8-bit received data.
- * \hideinitializer
- */
-#define SCUART_READ(sc) ((sc)->DAT)
-
-/**
- * @brief Get RX FIFO empty flag status from register.
- * @param[in] sc The pointer of smartcard module.
- * @retval 0 Receive FIFO is not empty.
- * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty.
- * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY(SC_STATUS[1]) high.
- * It will be cleared when SC receives any new data.
- * \hideinitializer
- */
-#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
-
-
-/**
- * @brief Get RX FIFO full flag status from register.
- * @param[in] sc The pointer of smartcard module.
- * @retval 0 Receive FIFO is not full.
- * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full.
- * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
- * \hideinitializer
- */
-#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
-
-/**
- * @brief Check if receive data number in FIFO reach FIFO trigger level or not.
- * @param[in] sc The pointer of smartcard module.
- * @retval 0 The number of bytes in receive FIFO is less than trigger level.
- * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level.
- * @details RDAIF(SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
- * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO.
- * \hideinitializer
- */
-#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
-
-/**
- * @brief Check specified smartcard port receive FIFO is full or not.
- * @param[in] sc The pointer of smartcard module.
- * @retval 0 Receive FIFO is not full.
- * @retval 1 Receive FIFO is full.
- * @details RXFULLF(SC_STATUS[2]) is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
- * \hideinitializer
- */
-#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0)
-
-/* Interrupt Macros */
-
-/**
- * @brief Enable specified interrupts.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Mask Interrupt masks to enable, a combination of following bits.
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt,
- * transmit buffer empty interrupt or receive data reach trigger level interrupt.
- * \hideinitializer
- */
-#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
-
-/**
- * @brief Disable specified interrupts.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Mask Interrupt masks to disable, a combination of following bits.
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt,
- * transmit buffer empty interrupt or receive data reach trigger level interrupt.
- * \hideinitializer
- */
-#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
-
-/**
- * @brief Get specified interrupt flag/status.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Type Interrupt flag/status to check, could be one of following value:
- * - \ref SC_INTSTS_RBTOIF_Msk
- * - \ref SC_INTSTS_TERRIF_Msk
- * - \ref SC_INTSTS_TBEIF_Msk
- * - \ref SC_INTSTS_RDAIF_Msk
- * @return The status of specified interrupt.
- * @retval 0 Specified interrupt does not happened.
- * @retval 1 Specified interrupt happened.
- * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status,
- * transmit buffer empty interrupt status or receive data reach interrupt status.
- * \hideinitializer
- */
-#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & (u32Type) ? 1 : 0)
-
-/**
- * @brief Clear specified interrupt flag/status.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values:
- * - \ref SC_INTSTS_RBTOIF_Msk
- * - \ref SC_INTSTS_TERRIF_Msk
- * - \ref SC_INTSTS_TBEIF_Msk
- * @return None
- * @details The macro is used to clear receiver buffer time-out interrupt flag, transfer error interrupt flag or
- * transmit buffer empty interrupt flag.
- * \hideinitializer
- */
-#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))
-
-/**
- * @brief Get receive error flag/status.
- * @param[in] sc The pointer of smartcard module.
- * @return Current receive error status, could one of following errors:
- * @retval SC_STATUS_PEF_Msk Parity error.
- * @retval SC_STATUS_FEF_Msk Frame error.
- * @retval SC_STATUS_BEF_Msk Break error.
- * @details The macro is used to get receiver parity error status, receiver frame error status or
- * receiver break error status.
- * \hideinitializer
- */
-#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
-
-/**
- * @brief Clear specified receive error flag/status.
- * @param[in] sc The pointer of smartcard module.
- * @param[in] u32Mask Receive error flag/status to clear, combination following values:
- * - \ref SC_STATUS_PEF_Msk
- * - \ref SC_STATUS_FEF_Msk
- * - \ref SC_STATUS_BEF_Msk
- * @return None
- * @details The macro is used to clear receiver parity error flag, receiver frame error flag or
- * receiver break error flag.
- * \hideinitializer
- */
-#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))
-
-void SCUART_Close(SC_T* sc);
-uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
-uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
-uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
-void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
-void SCUART_Write(SC_T* sc, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
-
-/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SCUART_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SCUART_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1154 +0,0 @@
-/**************************************************************************//**
- * @file spi.c
- * @version V3.00
- * $Revision: 11 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series SPI driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SPI_Driver SPI Driver
- @{
-*/
-
-
-/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
- @{
-*/
-
-/**
- * @brief This function make SPI module be ready to transfer.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
- * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)
- * @param[in] u32DataWidth Decides the data width of a SPI transaction.
- * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
- * @return Actual frequency of SPI peripheral clock.
- * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
- * slave selection function is disabled.
- * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.
- * The actual clock rate may be different from the target SPI clock rate.
- * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the
- * actual SPI clock rate will be 6MHz.
- * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
- * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
- * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
- * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
- */
-uint32_t SPI_Open(SPI_T *spi,
- uint32_t u32MasterSlave,
- uint32_t u32SPIMode,
- uint32_t u32DataWidth,
- uint32_t u32BusClock)
-{
- uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq;
-
- if((spi == SPI1) || (spi == SPI2))
- /* Disable I2S mode */
- spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
-
- if(u32DataWidth == 32)
- u32DataWidth = 0;
-
- /* Get system clock frequency */
- u32HCLKFreq = CLK_GetHCLKFreq();
-
- if(u32MasterSlave == SPI_MASTER)
- {
- /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
- spi->SSCTL = SPI_SS_ACTIVE_LOW;
-
- /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
- spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
-
- if(u32BusClock >= u32HCLKFreq)
- {
- /* Select PCLK as the clock source of SPI */
- if(spi == SPI0)
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
- else if(spi == SPI1)
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
- else
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
- }
-
- /* Check clock source of SPI */
- if(spi == SPI0)
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
- {
- /* Clock source is PCLK0 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
- else if(spi == SPI1)
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
- {
- /* Clock source is PCLK1 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
- else
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
- {
- /* Clock source is PCLK0 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
-
- if(u32BusClock >= u32HCLKFreq)
- {
- /* Set DIVIDER = 0 */
- spi->CLKDIV = 0;
- /* Return master peripheral clock rate */
- return u32ClkSrc;
- }
- else if(u32BusClock >= u32ClkSrc)
- {
- /* Set DIVIDER = 0 */
- spi->CLKDIV = 0;
- /* Return master peripheral clock rate */
- return u32ClkSrc;
- }
- else if(u32BusClock == 0)
- {
- /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
- spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
- /* Return master peripheral clock rate */
- return (u32ClkSrc / (0xFF + 1));
- }
- else
- {
- u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
- if(u32Div > 0xFF)
- {
- u32Div = 0xFF;
- spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
- /* Return master peripheral clock rate */
- return (u32ClkSrc / (0xFF + 1));
- }
- else
- {
- spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
- /* Return master peripheral clock rate */
- return (u32ClkSrc / (u32Div + 1));
- }
- }
- }
- else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
- {
- /* Default setting: slave selection signal is low level active. */
- spi->SSCTL = SPI_SS_ACTIVE_LOW;
-
- /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
- spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
-
- /* Set DIVIDER = 0 */
- spi->CLKDIV = 0;
-
- /* Select PCLK as the clock source of SPI */
- if(spi == SPI0)
- {
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
- /* Return slave peripheral clock rate */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- return (u32HCLKFreq / 2);
- else
- return u32HCLKFreq;
- }
- else if(spi == SPI1)
- {
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
- /* Return slave peripheral clock rate */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
- return (u32HCLKFreq / 2);
- else
- return u32HCLKFreq;
- }
- else
- {
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
- /* Return slave peripheral clock rate */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- return (u32HCLKFreq / 2);
- else
- return u32HCLKFreq;
- }
- }
-}
-
-/**
- * @brief Disable SPI controller.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None
- * @details This function will reset SPI controller.
- */
-void SPI_Close(SPI_T *spi)
-{
- if(spi == SPI0)
- {
- /* Reset SPI */
- SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
- }
- else if(spi == SPI1)
- {
- /* Reset SPI */
- SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
- }
- else
- {
- /* Reset SPI */
- SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
- }
-}
-
-/**
- * @brief Clear RX FIFO buffer.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None
- * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.
- */
-void SPI_ClearRxFIFO(SPI_T *spi)
-{
- spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
-}
-
-/**
- * @brief Clear TX FIFO buffer.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None
- * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.
- * @note The TX shift register will not be cleared.
- */
-void SPI_ClearTxFIFO(SPI_T *spi)
-{
- spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
-}
-
-/**
- * @brief Disable the automatic slave selection function.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None
- * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
- */
-void SPI_DisableAutoSS(SPI_T *spi)
-{
- spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
-}
-
-/**
- * @brief Enable the automatic slave selection function.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS)
- * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
- * @return None
- * @details This function will enable the automatic slave selection function. Only available in Master mode.
- * The slave selection pin and the active level will be set in this function.
- */
-void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
-{
- spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
-}
-
-/**
- * @brief Set the SPI bus clock.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz.
- * @return Actual frequency of SPI bus clock.
- * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.
- * For example, if the SPI source clock rate is 12MHz and the target SPI bus clock rate is 7MHz, the actual SPI bus clock
- * rate will be 6MHz.
- * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
- * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
- * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
- */
-uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
-{
- uint32_t u32ClkSrc, u32HCLKFreq;
- uint32_t u32Div;
-
- /* Get system clock frequency */
- u32HCLKFreq = CLK_GetHCLKFreq();
-
- if(u32BusClock >= u32HCLKFreq)
- {
- /* Select PCLK as the clock source of SPI */
- if(spi == SPI0)
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
- else if(spi == SPI1)
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
- else
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
- }
-
- /* Check clock source of SPI */
- if(spi == SPI0)
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
- {
- /* Clock source is PCLK0 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
- else if(spi == SPI1)
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
- {
- /* Clock source is PCLK1 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
- else
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
- {
- /* Clock source is PCLK0 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
-
- if(u32BusClock >= u32HCLKFreq)
- {
- /* Set DIVIDER = 0 */
- spi->CLKDIV = 0;
- /* Return master peripheral clock rate */
- return u32ClkSrc;
- }
- else if(u32BusClock >= u32ClkSrc)
- {
- /* Set DIVIDER = 0 */
- spi->CLKDIV = 0;
- /* Return master peripheral clock rate */
- return u32ClkSrc;
- }
- else if(u32BusClock == 0)
- {
- /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
- spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
- /* Return master peripheral clock rate */
- return (u32ClkSrc / (0xFF + 1));
- }
- else
- {
- u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
- if(u32Div > 0xFF)
- {
- u32Div = 0xFF;
- spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
- /* Return master peripheral clock rate */
- return (u32ClkSrc / (0xFF + 1));
- }
- else
- {
- spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
- /* Return master peripheral clock rate */
- return (u32ClkSrc / (u32Div + 1));
- }
- }
-}
-
-/**
- * @brief Configure FIFO threshold setting.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32TxThreshold Decides the TX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
- * @param[in] u32RxThreshold Decides the RX FIFO threshold. For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
- * @return None
- * @details Set TX FIFO threshold and RX FIFO threshold configurations.
- */
-void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
-{
- spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
- (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
- (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
-}
-
-/**
- * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return Actual SPI bus clock frequency in Hz.
- * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode.
- */
-uint32_t SPI_GetBusClock(SPI_T *spi)
-{
- uint32_t u32Div;
- uint32_t u32ClkSrc, u32HCLKFreq;
-
- /* Get DIVIDER setting */
- u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;
-
- /* Get system clock frequency */
- u32HCLKFreq = CLK_GetHCLKFreq();
-
- /* Check clock source of SPI */
- if(spi == SPI0)
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK0)
- {
- /* Clock source is PCLK0 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
- else if(spi == SPI1)
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
- {
- /* Clock source is PCLK1 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
- else
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
- u32ClkSrc = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
- u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
- {
- /* Clock source is PCLK0 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- u32ClkSrc = (u32HCLKFreq / 2);
- else
- u32ClkSrc = u32HCLKFreq;
- }
- else
- u32ClkSrc = __HIRC; /* Clock source is HIRC */
- }
-
- /* Return SPI bus clock rate */
- return (u32ClkSrc / (u32Div + 1));
-}
-
-/**
- * @brief Enable interrupt function.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32Mask The combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt enable bit.
- * This parameter decides which interrupts will be enabled. It is combination of:
- * - \ref SPI_UNIT_INT_MASK
- * - \ref SPI_SSACT_INT_MASK
- * - \ref SPI_SSINACT_INT_MASK
- * - \ref SPI_SLVUR_INT_MASK
- * - \ref SPI_SLVBE_INT_MASK
- * - \ref SPI_SLVTO_INT_MASK
- * - \ref SPI_TXUF_INT_MASK
- * - \ref SPI_FIFO_TXTH_INT_MASK
- * - \ref SPI_FIFO_RXTH_INT_MASK
- * - \ref SPI_FIFO_RXOV_INT_MASK
- * - \ref SPI_FIFO_RXTO_INT_MASK
- *
- * @return None
- * @details Enable SPI related interrupts specified by u32Mask parameter.
- */
-void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
-{
- /* Enable unit transfer interrupt flag */
- if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
- spi->CTL |= SPI_CTL_UNITIEN_Msk;
-
- /* Enable slave selection signal active interrupt flag */
- if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
- spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
-
- /* Enable slave selection signal inactive interrupt flag */
- if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
- spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
-
- /* Enable slave TX under run interrupt flag */
- if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
- spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
-
- /* Enable slave bit count error interrupt flag */
- if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
- spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
-
- /* Enable slave time-out interrupt flag */
- if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
- spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk;
-
- /* Enable slave TX underflow interrupt flag */
- if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
-
- /* Enable TX threshold interrupt flag */
- if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
-
- /* Enable RX threshold interrupt flag */
- if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
-
- /* Enable RX overrun interrupt flag */
- if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
-
- /* Enable RX time-out interrupt flag */
- if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
-}
-
-/**
- * @brief Disable interrupt function.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32Mask The combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt bit.
- * This parameter decides which interrupts will be disabled. It is combination of:
- * - \ref SPI_UNIT_INT_MASK
- * - \ref SPI_SSACT_INT_MASK
- * - \ref SPI_SSINACT_INT_MASK
- * - \ref SPI_SLVUR_INT_MASK
- * - \ref SPI_SLVBE_INT_MASK
- * - \ref SPI_SLVTO_INT_MASK
- * - \ref SPI_TXUF_INT_MASK
- * - \ref SPI_FIFO_TXTH_INT_MASK
- * - \ref SPI_FIFO_RXTH_INT_MASK
- * - \ref SPI_FIFO_RXOV_INT_MASK
- * - \ref SPI_FIFO_RXTO_INT_MASK
- *
- * @return None
- * @details Disable SPI related interrupts specified by u32Mask parameter.
- */
-void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
-{
- /* Disable unit transfer interrupt flag */
- if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
- spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
-
- /* Disable slave selection signal active interrupt flag */
- if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
-
- /* Disable slave selection signal inactive interrupt flag */
- if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
-
- /* Disable slave TX under run interrupt flag */
- if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
-
- /* Disable slave bit count error interrupt flag */
- if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
-
- /* Disable slave time-out interrupt flag */
- if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
-
- /* Disable slave TX underflow interrupt flag */
- if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
-
- /* Disable TX threshold interrupt flag */
- if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
-
- /* Disable RX threshold interrupt flag */
- if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
-
- /* Disable RX overrun interrupt flag */
- if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
-
- /* Disable RX time-out interrupt flag */
- if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
-}
-
-/**
- * @brief Get interrupt flag.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32Mask The combination of all related interrupt sources.
- * Each bit corresponds to a interrupt source.
- * This parameter decides which interrupt flags will be read. It is combination of:
- * - \ref SPI_UNIT_INT_MASK
- * - \ref SPI_SSACT_INT_MASK
- * - \ref SPI_SSINACT_INT_MASK
- * - \ref SPI_SLVUR_INT_MASK
- * - \ref SPI_SLVBE_INT_MASK
- * - \ref SPI_SLVTO_INT_MASK
- * - \ref SPI_TXUF_INT_MASK
- * - \ref SPI_FIFO_TXTH_INT_MASK
- * - \ref SPI_FIFO_RXTH_INT_MASK
- * - \ref SPI_FIFO_RXOV_INT_MASK
- * - \ref SPI_FIFO_RXTO_INT_MASK
- *
- * @return Interrupt flags of selected sources.
- * @details Get SPI related interrupt flags specified by u32Mask parameter.
- */
-uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
-{
- uint32_t u32IntFlag = 0;
-
- /* Check unit transfer interrupt flag */
- if((u32Mask & SPI_UNIT_INT_MASK) && (spi->STATUS & SPI_STATUS_UNITIF_Msk))
- u32IntFlag |= SPI_UNIT_INT_MASK;
-
- /* Check slave selection signal active interrupt flag */
- if((u32Mask & SPI_SSACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSACTIF_Msk))
- u32IntFlag |= SPI_SSACT_INT_MASK;
-
- /* Check slave selection signal inactive interrupt flag */
- if((u32Mask & SPI_SSINACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSINAIF_Msk))
- u32IntFlag |= SPI_SSINACT_INT_MASK;
-
- /* Check slave TX under run interrupt flag */
- if((u32Mask & SPI_SLVUR_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVURIF_Msk))
- u32IntFlag |= SPI_SLVUR_INT_MASK;
-
- /* Check slave bit count error interrupt flag */
- if((u32Mask & SPI_SLVBE_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVBEIF_Msk))
- u32IntFlag |= SPI_SLVBE_INT_MASK;
-
- /* Check slave time-out interrupt flag */
- if((u32Mask & SPI_SLVTO_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVTOIF_Msk))
- u32IntFlag |= SPI_SLVTO_INT_MASK;
-
- /* Check slave TX underflow interrupt flag */
- if((u32Mask & SPI_TXUF_INT_MASK) && (spi->STATUS & SPI_STATUS_TXUFIF_Msk))
- u32IntFlag |= SPI_TXUF_INT_MASK;
-
- /* Check TX threshold interrupt flag */
- if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_TXTHIF_Msk))
- u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
-
- /* Check RX threshold interrupt flag */
- if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTHIF_Msk))
- u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
-
- /* Check RX overrun interrupt flag */
- if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RXOVIF_Msk))
- u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
-
- /* Check RX time-out interrupt flag */
- if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTOIF_Msk))
- u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
-
- return u32IntFlag;
-}
-
-/**
- * @brief Clear interrupt flag.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32Mask The combination of all related interrupt sources.
- * Each bit corresponds to a interrupt source.
- * This parameter decides which interrupt flags will be cleared. It could be the combination of:
- * - \ref SPI_UNIT_INT_MASK
- * - \ref SPI_SSACT_INT_MASK
- * - \ref SPI_SSINACT_INT_MASK
- * - \ref SPI_SLVUR_INT_MASK
- * - \ref SPI_SLVBE_INT_MASK
- * - \ref SPI_SLVTO_INT_MASK
- * - \ref SPI_TXUF_INT_MASK
- * - \ref SPI_FIFO_RXOV_INT_MASK
- * - \ref SPI_FIFO_RXTO_INT_MASK
- *
- * @return None
- * @details Clear SPI related interrupt flags specified by u32Mask parameter.
- */
-void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
-{
- if(u32Mask & SPI_UNIT_INT_MASK)
- spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
-
- if(u32Mask & SPI_SSACT_INT_MASK)
- spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
-
- if(u32Mask & SPI_SSINACT_INT_MASK)
- spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
-
- if(u32Mask & SPI_SLVUR_INT_MASK)
- spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
-
- if(u32Mask & SPI_SLVBE_INT_MASK)
- spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
-
- if(u32Mask & SPI_SLVTO_INT_MASK)
- spi->STATUS = SPI_STATUS_SLVTOIF_Msk; /* Clear slave time-out interrupt flag */
-
- if(u32Mask & SPI_TXUF_INT_MASK)
- spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
-
- if(u32Mask & SPI_FIFO_RXOV_INT_MASK)
- spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
-
- if(u32Mask & SPI_FIFO_RXTO_INT_MASK)
- spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
-}
-
-/**
- * @brief Get SPI status.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32Mask The combination of all related sources.
- * Each bit corresponds to a source.
- * This parameter decides which flags will be read. It is combination of:
- * - \ref SPI_BUSY_MASK
- * - \ref SPI_RX_EMPTY_MASK
- * - \ref SPI_RX_FULL_MASK
- * - \ref SPI_TX_EMPTY_MASK
- * - \ref SPI_TX_FULL_MASK
- * - \ref SPI_TXRX_RESET_MASK
- * - \ref SPI_SPIEN_STS_MASK
- * - \ref SPI_SSLINE_STS_MASK
- *
- * @return Flags of selected sources.
- * @details Get SPI related status specified by u32Mask parameter.
- */
-uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
-{
- uint32_t u32Flag = 0;
-
- /* Check busy status */
- if((u32Mask & SPI_BUSY_MASK) && (spi->STATUS & SPI_STATUS_BUSY_Msk))
- u32Flag |= SPI_BUSY_MASK;
-
- /* Check RX empty flag */
- if((u32Mask & SPI_RX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_RXEMPTY_Msk))
- u32Flag |= SPI_RX_EMPTY_MASK;
-
- /* Check RX full flag */
- if((u32Mask & SPI_RX_FULL_MASK) && (spi->STATUS & SPI_STATUS_RXFULL_Msk))
- u32Flag |= SPI_RX_FULL_MASK;
-
- /* Check TX empty flag */
- if((u32Mask & SPI_TX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_TXEMPTY_Msk))
- u32Flag |= SPI_TX_EMPTY_MASK;
-
- /* Check TX full flag */
- if((u32Mask & SPI_TX_FULL_MASK) && (spi->STATUS & SPI_STATUS_TXFULL_Msk))
- u32Flag |= SPI_TX_FULL_MASK;
-
- /* Check TX/RX reset flag */
- if((u32Mask & SPI_TXRX_RESET_MASK) && (spi->STATUS & SPI_STATUS_TXRXRST_Msk))
- u32Flag |= SPI_TXRX_RESET_MASK;
-
- /* Check SPIEN flag */
- if((u32Mask & SPI_SPIEN_STS_MASK) && (spi->STATUS & SPI_STATUS_SPIENSTS_Msk))
- u32Flag |= SPI_SPIEN_STS_MASK;
-
- /* Check SPIn_SS line status */
- if((u32Mask & SPI_SSLINE_STS_MASK) && (spi->STATUS & SPI_STATUS_SSLINE_Msk))
- u32Flag |= SPI_SSLINE_STS_MASK;
-
- return u32Flag;
-}
-
-
-/**
- * @brief This function is used to get I2S source clock frequency.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return I2S source clock frequency (Hz).
- * @details Return the source clock frequency according to the setting of SPI1SEL (CLKSEL2[5:4]) or SPI2SEL (CLKSEL2[7:6]).
- * @note Only SPI1 and SPI2 support I2S mode.
- */
-static uint32_t I2S_GetSourceClockFreq(SPI_T *i2s)
-{
- uint32_t u32Freq, u32HCLKFreq;
-
- if(i2s == SPI1)
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_HXT)
- u32Freq = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PLL)
- u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI1SEL_Msk) == CLK_CLKSEL2_SPI1SEL_PCLK1)
- {
- /* Get system clock frequency */
- u32HCLKFreq = CLK_GetHCLKFreq();
- /* Clock source is PCLK1 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
- u32Freq = (u32HCLKFreq / 2);
- else
- u32Freq = u32HCLKFreq;
- }
- else
- u32Freq = __HIRC; /* Clock source is HIRC */
- }
- else
- {
- if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_HXT)
- u32Freq = __HXT; /* Clock source is HXT */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PLL)
- u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
- else if((CLK->CLKSEL2 & CLK_CLKSEL2_SPI2SEL_Msk) == CLK_CLKSEL2_SPI2SEL_PCLK0)
- {
- /* Get system clock frequency */
- u32HCLKFreq = CLK_GetHCLKFreq();
- /* Clock source is PCLK0 */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- u32Freq = (u32HCLKFreq / 2);
- else
- u32Freq = u32HCLKFreq;
- }
- else
- u32Freq = __HIRC; /* Clock source is HIRC */
- }
-
- return u32Freq;
-}
-
-/**
- * @brief This function configures some parameters of I2S interface for general purpose use.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below.
- * - \ref I2S_MODE_MASTER
- * - \ref I2S_MODE_SLAVE
- * @param[in] u32SampleRate Sample rate
- * @param[in] u32WordWidth Data length. Valid values are listed below.
- * - \ref I2S_DATABIT_8
- * - \ref I2S_DATABIT_16
- * - \ref I2S_DATABIT_24
- * - \ref I2S_DATABIT_32
- * @param[in] u32Channels Audio format. Valid values are listed below.
- * - \ref I2S_MONO
- * - \ref I2S_STEREO
- * @param[in] u32DataFormat Data format. Valid values are listed below.
- * - \ref I2S_FORMAT_I2S
- * - \ref I2S_FORMAT_MSB
- * - \ref I2S_FORMAT_PCMA
- * - \ref I2S_FORMAT_PCMB
- * @return Real sample rate of master mode or peripheral clock rate of slave mode.
- * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters.
- * Set TX and RX FIFO threshold to middle value. Both the TX and RX functions will be enabled.
- * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
- * @note Only SPI1 and SPI2 support I2S mode.
- * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate.
- */
-uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
-{
- uint32_t u32Divider;
- uint32_t u32BitRate, u32SrcClk;
- uint32_t u32HCLKFreq;
-
- /* Reset SPI/I2S */
- if(i2s == SPI1)
- {
- SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
- }
- else
- {
- SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
- }
-
- /* Configure I2S controller */
- i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;
- /* Set TX and RX FIFO threshold to middle value */
- i2s->FIFOCTL = I2S_FIFO_TX_LEVEL_WORD_2 | I2S_FIFO_RX_LEVEL_WORD_2;
-
- if(u32MasterSlave == SPI_MASTER)
- {
- /* Get the source clock rate */
- u32SrcClk = I2S_GetSourceClockFreq(i2s);
-
- /* Calculate the bit clock rate */
- u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16;
- u32Divider = ((u32SrcClk / u32BitRate) >> 1) - 1;
- /* Set BCLKDIV setting */
- i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);
-
- /* Calculate bit clock rate */
- u32BitRate = u32SrcClk / ((u32Divider + 1) * 2);
- /* Calculate real sample rate */
- u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1) * 16);
-
- /* Enable TX function, RX function and I2S mode. */
- i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
-
- /* Return the real sample rate */
- return u32SampleRate;
- }
- else
- {
- /* Set BCLKDIV = 0 */
- i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;
- /* Get system clock frequency */
- u32HCLKFreq = CLK_GetHCLKFreq();
-
- if(i2s == SPI1)
- {
- /* Set the peripheral clock rate to equal APB clock rate */
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
- /* Enable TX function, RX function and I2S mode. */
- i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
- /* Return slave peripheral clock rate */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2)
- return (u32HCLKFreq / 2);
- else
- return u32HCLKFreq;
- }
- else
- {
- /* Set the peripheral clock rate to equal APB clock rate */
- CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK0;
- /* Enable TX function, RX function and I2S mode. */
- i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
- /* Return slave peripheral clock rate */
- if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2)
- return (u32HCLKFreq / 2);
- else
- return u32HCLKFreq;
- }
- }
-}
-
-/**
- * @brief Disable I2S function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details Disable I2S function.
- * @note Only SPI1 and SPI2 support I2S mode.
- */
-void I2S_Close(SPI_T *i2s)
-{
- i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
-}
-
-/**
- * @brief Enable interrupt function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32Mask The combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt source. Valid values are listed below.
- * - \ref I2S_FIFO_TXTH_INT_MASK
- * - \ref I2S_FIFO_RXTH_INT_MASK
- * - \ref I2S_FIFO_RXOV_INT_MASK
- * - \ref I2S_FIFO_RXTO_INT_MASK
- * - \ref I2S_TXUF_INT_MASK
- * - \ref I2S_RIGHT_ZC_INT_MASK
- * - \ref I2S_LEFT_ZC_INT_MASK
- * @return None
- * @details This function enables the interrupt according to the u32Mask parameter.
- * @note Only SPI1 and SPI2 support I2S mode.
- */
-void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
-{
- /* Enable TX threshold interrupt flag */
- if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK)
- i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
-
- /* Enable RX threshold interrupt flag */
- if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK)
- i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
-
- /* Enable RX overrun interrupt flag */
- if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK)
- i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
-
- /* Enable RX time-out interrupt flag */
- if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK)
- i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
-
- /* Enable TX underflow interrupt flag */
- if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK)
- i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
-
- /* Enable right channel zero cross interrupt flag */
- if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK)
- i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;
-
- /* Enable left channel zero cross interrupt flag */
- if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK)
- i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;
-}
-
-/**
- * @brief Disable interrupt function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32Mask The combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt source. Valid values are listed below.
- * - \ref I2S_FIFO_TXTH_INT_MASK
- * - \ref I2S_FIFO_RXTH_INT_MASK
- * - \ref I2S_FIFO_RXOV_INT_MASK
- * - \ref I2S_FIFO_RXTO_INT_MASK
- * - \ref I2S_TXUF_INT_MASK
- * - \ref I2S_RIGHT_ZC_INT_MASK
- * - \ref I2S_LEFT_ZC_INT_MASK
- * @return None
- * @details This function disables the interrupt according to the u32Mask parameter.
- * @note Only SPI1 and SPI2 support I2S mode.
- */
-void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
-{
- /* Disable TX threshold interrupt flag */
- if((u32Mask & I2S_FIFO_TXTH_INT_MASK) == I2S_FIFO_TXTH_INT_MASK)
- i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
-
- /* Disable RX threshold interrupt flag */
- if((u32Mask & I2S_FIFO_RXTH_INT_MASK) == I2S_FIFO_RXTH_INT_MASK)
- i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
-
- /* Disable RX overrun interrupt flag */
- if((u32Mask & I2S_FIFO_RXOV_INT_MASK) == I2S_FIFO_RXOV_INT_MASK)
- i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
-
- /* Disable RX time-out interrupt flag */
- if((u32Mask & I2S_FIFO_RXTO_INT_MASK) == I2S_FIFO_RXTO_INT_MASK)
- i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
-
- /* Disable TX underflow interrupt flag */
- if((u32Mask & I2S_TXUF_INT_MASK) == I2S_TXUF_INT_MASK)
- i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
-
- /* Disable right channel zero cross interrupt flag */
- if((u32Mask & I2S_RIGHT_ZC_INT_MASK) == I2S_RIGHT_ZC_INT_MASK)
- i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;
-
- /* Disable left channel zero cross interrupt flag */
- if((u32Mask & I2S_LEFT_ZC_INT_MASK) == I2S_LEFT_ZC_INT_MASK)
- i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;
-}
-
-/**
- * @brief Enable master clock (MCLK).
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32BusClock The target MCLK clock rate.
- * @return Actual MCLK clock rate
- * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
- * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
- * @note Only SPI1 and SPI2 support I2S mode.
- */
-uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
-{
- uint32_t u32Divider;
- uint32_t u32SrcClk;
-
- u32SrcClk = I2S_GetSourceClockFreq(i2s);
- if(u32BusClock == u32SrcClk)
- u32Divider = 0;
- else
- {
- u32Divider = (u32SrcClk / u32BusClock) >> 1;
- /* MCLKDIV is a 6-bit width configuration. The maximum value is 0x3F. */
- if(u32Divider > 0x3F)
- u32Divider = 0x3F;
- }
-
- /* Write u32Divider to MCLKDIV (SPI_I2SCLK[5:0]) */
- i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);
-
- /* Enable MCLK output */
- i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;
-
- if(u32Divider == 0)
- return u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */
- else
- return ((u32SrcClk >> 1) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */
-}
-
-/**
- * @brief Disable master clock (MCLK).
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.
- * @note Only SPI1 and SPI2 support I2S mode.
- */
-void I2S_DisableMCLK(SPI_T *i2s)
-{
- i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;
-}
-
-/**
- * @brief Configure FIFO threshold setting.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
- * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
- * @return None
- * @details Set TX FIFO threshold and RX FIFO threshold configurations.
- */
-void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
-{
- i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
- (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
- (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
-}
-
-/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SPI_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_spi.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,630 +0,0 @@
-/******************************************************************************
- * @file spi.h
- * @version V0.10
- * $Revision: 17 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series SPI driver header file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __SPI_H__
-#define __SPI_H__
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Include related headers */
-/*---------------------------------------------------------------------------------------------------------*/
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SPI_Driver SPI Driver
- @{
-*/
-
-/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
- @{
-*/
-
-#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
-#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
-#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
-#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
-
-#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
-#define SPI_MASTER (0x0) /*!< Set as master */
-
-#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */
-#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
-#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
-
-/* SPI Interrupt Mask */
-#define SPI_UNIT_INT_MASK (0x001) /*!< Unit transfer interrupt mask */
-#define SPI_SSACT_INT_MASK (0x002) /*!< Slave selection signal active interrupt mask */
-#define SPI_SSINACT_INT_MASK (0x004) /*!< Slave selection signal inactive interrupt mask */
-#define SPI_SLVUR_INT_MASK (0x008) /*!< Slave under run interrupt mask */
-#define SPI_SLVBE_INT_MASK (0x010) /*!< Slave bit count error interrupt mask */
-#define SPI_SLVTO_INT_MASK (0x020) /*!< Slave time-out interrupt mask */
-#define SPI_TXUF_INT_MASK (0x040) /*!< Slave TX underflow interrupt mask */
-#define SPI_FIFO_TXTH_INT_MASK (0x080) /*!< FIFO TX threshold interrupt mask */
-#define SPI_FIFO_RXTH_INT_MASK (0x100) /*!< FIFO RX threshold interrupt mask */
-#define SPI_FIFO_RXOV_INT_MASK (0x200) /*!< FIFO RX overrun interrupt mask */
-#define SPI_FIFO_RXTO_INT_MASK (0x400) /*!< FIFO RX time-out interrupt mask */
-
-/* SPI Status Mask */
-#define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
-#define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
-#define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
-#define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
-#define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
-#define SPI_TXRX_RESET_MASK (0x20) /*!< TX or RX reset status mask */
-#define SPI_SPIEN_STS_MASK (0x40) /*!< SPIEN status mask */
-#define SPI_SSLINE_STS_MASK (0x80) /*!< SPIn_SS line status mask */
-
-
-/* I2S Data Width */
-#define I2S_DATABIT_8 (0 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */
-#define I2S_DATABIT_16 (1 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */
-#define I2S_DATABIT_24 (2 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */
-#define I2S_DATABIT_32 (3 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */
-
-/* I2S Audio Format */
-#define I2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */
-#define I2S_STEREO 0 /*!< Stereo channel */
-
-/* I2S Data Format */
-#define I2S_FORMAT_I2S (0<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */
-#define I2S_FORMAT_MSB (1<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */
-#define I2S_FORMAT_PCMA (2<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */
-#define I2S_FORMAT_PCMB (3<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */
-
-/* I2S Operation mode */
-#define I2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */
-#define I2S_MODE_MASTER 0 /*!< As master mode */
-
-/* I2S TX FIFO Threshold */
-#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */
-#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */
-#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */
-#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */
-/* I2S RX FIFO Threshold */
-#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */
-#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */
-#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */
-#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */
-
-/* I2S Record Channel */
-#define I2S_MONO_RIGHT 0 /*!< Record mono right channel */
-#define I2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */
-
-/* I2S Channel */
-#define I2S_RIGHT 0 /*!< Select right channel */
-#define I2S_LEFT 1 /*!< Select left channel */
-
-/* I2S Interrupt Mask */
-#define I2S_FIFO_TXTH_INT_MASK (0x01) /*!< TX FIFO threshold interrupt mask */
-#define I2S_FIFO_RXTH_INT_MASK (0x02) /*!< RX FIFO threshold interrupt mask */
-#define I2S_FIFO_RXOV_INT_MASK (0x04) /*!< RX FIFO overrun interrupt mask */
-#define I2S_FIFO_RXTO_INT_MASK (0x08) /*!< RX FIFO time-out interrupt mask */
-#define I2S_TXUF_INT_MASK (0x10) /*!< TX FIFO underflow interrupt mask */
-#define I2S_RIGHT_ZC_INT_MASK (0x20) /*!< Right channel zero cross interrupt mask */
-#define I2S_LEFT_ZC_INT_MASK (0x40) /*!< Left channel zero cross interrupt mask */
-
-/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
- @{
-*/
-
-/**
- * @brief Clear the unit transfer interrupt flag.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
- */
-#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
-
-/**
- * @brief Disable 2-bit Transfer mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear TWOBIT bit of SPI_CTL register to disable 2-bit Transfer mode.
- */
-#define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CTL &= ~SPI_CTL_TWOBIT_Msk)
-
-/**
- * @brief Disable Slave 3-wire mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
- */
-#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
-
-/**
- * @brief Disable Dual I/O mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear DUALIOEN bit of SPI_CTL register to disable Dual I/O mode.
- */
-#define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk)
-
-/**
- * @brief Disable Quad I/O mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear QUADIOEN bit of SPI_CTL register to disable Quad I/O mode.
- */
-#define SPI_DISABLE_QUAD_MODE(spi) ((spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk)
-
-/**
- * @brief Enable 2-bit Transfer mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set TWOBIT bit of SPI_CTL register to enable 2-bit Transfer mode.
- */
-#define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CTL |= SPI_CTL_TWOBIT_Msk)
-
-/**
- * @brief Enable Slave 3-wire mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
- */
-#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
-
-/**
- * @brief Enable Dual input mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear QDIODIR bit and set DUALIOEN bit of SPI_CTL register to enable Dual input mode.
- */
-#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_DUALIOEN_Msk)
-
-/**
- * @brief Enable Dual output mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set QDIODIR bit and DUALIOEN bit of SPI_CTL register to enable Dual output mode.
- */
-#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk))
-
-/**
- * @brief Enable Quad input mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear QDIODIR bit and set QUADIOEN bit of SPI_CTL register to enable Quad input mode.
- */
-#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_QUADIOEN_Msk)
-
-/**
- * @brief Enable Quad output mode.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set QDIODIR bit and QUADIOEN bit of SPI_CTL register to enable Quad output mode.
- */
-#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk))
-
-/**
- * @brief Trigger RX PDMA function.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
- */
-#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
-
-/**
- * @brief Trigger TX PDMA function.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
- */
-#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
-
-/**
- * @brief Disable RX PDMA transfer.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
- */
-#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
-
-/**
- * @brief Disable TX PDMA transfer.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
- */
-#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
-
-/**
- * @brief Get the count of available data in RX FIFO.
- * @param[in] spi The pointer of the specified SPI module.
- * @return The count of available data in RX FIFO.
- * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
- */
-#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
-
-/**
- * @brief Get the RX FIFO empty flag.
- * @param[in] spi The pointer of the specified SPI module.
- * @retval 0 RX FIFO is not empty.
- * @retval 1 RX FIFO is empty.
- * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
- */
-#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
-
-/**
- * @brief Get the TX FIFO empty flag.
- * @param[in] spi The pointer of the specified SPI module.
- * @retval 0 TX FIFO is not empty.
- * @retval 1 TX FIFO is empty.
- * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
- */
-#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
-
-/**
- * @brief Get the TX FIFO full flag.
- * @param[in] spi The pointer of the specified SPI module.
- * @retval 0 TX FIFO is not full.
- * @retval 1 TX FIFO is full.
- * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
- */
-#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
-
-/**
- * @brief Get the datum read from RX register.
- * @param[in] spi The pointer of the specified SPI module.
- * @return Data in RX register.
- * @details Read SPI_RX register to get the received datum.
- */
-#define SPI_READ_RX(spi) ((spi)->RX)
-
-/**
- * @brief Write datum to TX register.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
- * @return None.
- * @details Write u32TxData to SPI_TX register.
- */
-#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
-
-/**
- * @brief Set SPIn_SS pin to high state.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Disable automatic slave selection function and set SPIn_SS pin to high state.
- */
-#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
-
-/**
- * @brief Set SPIn_SS pin to low state.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Disable automatic slave selection function and set SPIn_SS pin to low state.
- */
-#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
-
-/**
- * @brief Enable Byte Reorder function.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
- */
-#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
-
-/**
- * @brief Disable Byte Reorder function.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
- */
-#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
-
-/**
- * @brief Set the length of suspend interval.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
- * @return None.
- * @details Set the length of suspend interval according to u32SuspCycle.
- * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
- */
-#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
-
-/**
- * @brief Set the SPI transfer sequence with LSB first.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
- */
-#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
-
-/**
- * @brief Set the SPI transfer sequence with MSB first.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
- */
-#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
-
-/**
- * @brief Set the data width of a SPI transaction.
- * @param[in] spi The pointer of the specified SPI module.
- * @param[in] u32Width The bit width of one transaction.
- * @return None.
- * @details The data width can be 8 ~ 32 bits.
- */
-#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
-
-/**
- * @brief Get the SPI busy state.
- * @param[in] spi The pointer of the specified SPI module.
- * @retval 0 SPI controller is not busy.
- * @retval 1 SPI controller is busy.
- * @details This macro will return the busy state of SPI controller.
- */
-#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
-
-/**
- * @brief Enable SPI controller.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
- */
-#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
-
-/**
- * @brief Disable SPI controller.
- * @param[in] spi The pointer of the specified SPI module.
- * @return None.
- * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
- */
-#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
-
-
-/**
- * @brief Enable zero cross detection function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32ChMask The mask for left or right channel. Valid values are:
- * - \ref I2S_RIGHT
- * - \ref I2S_LEFT
- * @return None
- * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
- */
-static __INLINE void I2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
-{
- if(u32ChMask == I2S_RIGHT)
- i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
- else
- i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
-}
-
-/**
- * @brief Disable zero cross detection function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32ChMask The mask for left or right channel. Valid values are:
- * - \ref I2S_RIGHT
- * - \ref I2S_LEFT
- * @return None
- * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
- */
-static __INLINE void I2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
-{
- if(u32ChMask == I2S_RIGHT)
- i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
- else
- i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
-}
-
-/**
- * @brief Enable I2S TX DMA function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
- */
-#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
-
-/**
- * @brief Disable I2S TX DMA function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
- */
-#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
-
-/**
- * @brief Enable I2S RX DMA function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
- */
-#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
-
-/**
- * @brief Disable I2S RX DMA function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
- */
-#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
-
-/**
- * @brief Enable I2S TX function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
- */
-#define I2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
-
-/**
- * @brief Disable I2S TX function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
- */
-#define I2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
-
-/**
- * @brief Enable I2S RX function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
- */
-#define I2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
-
-/**
- * @brief Disable I2S RX function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
- */
-#define I2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
-
-/**
- * @brief Enable TX Mute function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
- */
-#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
-
-/**
- * @brief Disable TX Mute function.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
- */
-#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
-
-/**
- * @brief Clear TX FIFO.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
- */
-#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
-
-/**
- * @brief Clear RX FIFO.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return None
- * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
- */
-#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
-
-/**
- * @brief This function sets the recording source channel when mono mode is used.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32Ch left or right channel. Valid values are:
- * - \ref I2S_MONO_LEFT
- * - \ref I2S_MONO_RIGHT
- * @return None
- * @details This function selects the recording source channel of monaural mode.
- */
-static __INLINE void I2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
-{
- u32Ch == I2S_MONO_LEFT ?
- (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
- (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
-}
-
-/**
- * @brief Write data to I2S TX FIFO.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32Data The value written to TX FIFO.
- * @return None
- * @details This macro will write a value to TX FIFO.
- */
-#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
-
-/**
- * @brief Read RX FIFO.
- * @param[in] i2s The pointer of the specified I2S module.
- * @return The value read from RX FIFO.
- * @details This function will return a value read from RX FIFO.
- */
-#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
-
-/**
- * @brief Get the interrupt flag.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32Mask The mask value for all interrupt flags.
- * @return The interrupt flags specified by the u32mask parameter.
- * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
- */
-#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
-
-/**
- * @brief Clear the interrupt flag.
- * @param[in] i2s The pointer of the specified I2S module.
- * @param[in] u32Mask The mask value for all interrupt flags.
- * @return None
- * @details This macro will clear the interrupt flags specified by the u32mask parameter.
- * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
- */
-#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
-
-/**
- * @brief Get transmit FIFO level
- * @param[in] i2s The pointer of the specified I2S module.
- * @return TX FIFO level
- * @details This macro will return the number of available words in TX FIFO.
- */
-#define I2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
-
-/**
- * @brief Get receive FIFO level
- * @param[in] i2s The pointer of the specified I2S module.
- * @return RX FIFO level
- * @details This macro will return the number of available words in RX FIFO.
- */
-#define I2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
-
-
-
-/* Function prototype declaration */
-uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
-void SPI_Close(SPI_T *spi);
-void SPI_ClearRxFIFO(SPI_T *spi);
-void SPI_ClearTxFIFO(SPI_T *spi);
-void SPI_DisableAutoSS(SPI_T *spi);
-void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
-uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
-void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
-uint32_t SPI_GetBusClock(SPI_T *spi);
-void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
-void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
-uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
-void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
-uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
-
-uint32_t I2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
-void I2S_Close(SPI_T *i2s);
-void I2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
-void I2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
-uint32_t I2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
-void I2S_DisableMCLK(SPI_T *i2s);
-void I2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
-
-
-/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SPI_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SPI_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,213 +0,0 @@
-/**************************************************************************//**
- * @file sys.c
- * @version V3.00
- * $Revision: 12 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series SYS driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SYS_Driver SYS Driver
- @{
-*/
-
-
-/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
- @{
-*/
-
-/**
- * @brief Clear reset source
- * @param[in] u32Src is system reset source. Including :
- * - \ref SYS_RSTSTS_CPURF_Msk
- * - \ref SYS_RSTSTS_SYSRF_Msk
- * - \ref SYS_RSTSTS_BODRF_Msk
- * - \ref SYS_RSTSTS_LVRF_Msk
- * - \ref SYS_RSTSTS_WDTRF_Msk
- * - \ref SYS_RSTSTS_PINRF_Msk
- * - \ref SYS_RSTSTS_PORF_Msk
- * @return None
- * @details This function clear the selected system reset source.
- */
-void SYS_ClearResetSrc(uint32_t u32Src)
-{
- SYS->RSTSTS |= u32Src;
-}
-
-/**
- * @brief Get Brown-out detector output status
- * @param None
- * @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0.
- * @retval 1 System voltage is lower than BOD_VL setting.
- * @details This function get Brown-out detector output status.
- */
-uint32_t SYS_GetBODStatus(void)
-{
- return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
-}
-
-/**
- * @brief Get reset status register value
- * @param None
- * @return Reset source
- * @details This function get the system reset status register value.
- */
-uint32_t SYS_GetResetSrc(void)
-{
- return (SYS->RSTSTS);
-}
-
-/**
- * @brief Check if register is locked nor not
- * @param None
- * @retval 0 Write-protection function is disabled.
- * 1 Write-protection function is enabled.
- * @details This function check register write-protection bit setting.
- */
-uint32_t SYS_IsRegLocked(void)
-{
- return !(SYS->REGLCTL & 0x1);
-}
-
-/**
- * @brief Get product ID
- * @param None
- * @return Product ID
- * @details This function get product ID.
- */
-uint32_t SYS_ReadPDID(void)
-{
- return SYS->PDID;
-}
-
-/**
- * @brief Reset chip with chip reset
- * @param None
- * @return None
- * @details This function reset chip with chip reset.
- * The register write-protection function should be disabled before using this function.
- */
-void SYS_ResetChip(void)
-{
- SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
-}
-
-/**
- * @brief Reset chip with CPU reset
- * @param None
- * @return None
- * @details This function reset CPU with CPU reset.
- * The register write-protection function should be disabled before using this function.
- */
-void SYS_ResetCPU(void)
-{
- SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
-}
-
-/**
- * @brief Reset selected module
- * @param[in] u32ModuleIndex is module index. Including :
- * - \ref PDMA_RST
- * - \ref EBI_RST
- * - \ref USBH_RST
- * - \ref CRC_RST
- * - \ref GPIO_RST
- * - \ref TMR0_RST
- * - \ref TMR1_RST
- * - \ref TMR2_RST
- * - \ref TMR3_RST
- * - \ref ACMP01_RST
- * - \ref I2C0_RST
- * - \ref I2C1_RST
- * - \ref SPI0_RST
- * - \ref SPI1_RST
- * - \ref SPI2_RST
- * - \ref UART0_RST
- * - \ref UART1_RST
- * - \ref UART2_RST
- * - \ref UART3_RST
- * - \ref CAN0_RST
- * - \ref OTG_RST
- * - \ref USBD_RST
- * - \ref EADC_RST
- * - \ref SC0_RST
- * - \ref DAC_RST
- * - \ref PWM0_RST
- * - \ref PWM1_RST
- * - \ref TK_RST
- * @return None
- * @details This function reset selected module.
- */
-void SYS_ResetModule(uint32_t u32ModuleIndex)
-{
- /* Generate reset signal to the corresponding module */
- *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff);
-
- /* Release corresponding module from reset state */
- *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
-}
-
-/**
- * @brief Enable and configure Brown-out detector function
- * @param[in] i32Mode is reset or interrupt mode. Including :
- * - \ref SYS_BODCTL_BOD_RST_EN
- * - \ref SYS_BODCTL_BOD_INTERRUPT_EN
- * @param[in] u32BODLevel is Brown-out voltage level. Including :
- * - \ref SYS_BODCTL_BODVL_4_5V
- * - \ref SYS_BODCTL_BODVL_3_7V
- * - \ref SYS_BODCTL_BODVL_2_7V
- * - \ref SYS_BODCTL_BODVL_2_2V
- * @return None
- * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
- * The register write-protection function should be disabled before using this function.
- */
-void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
-{
- /* Enable Brown-out Detector function */
- SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
-
- /* Enable Brown-out interrupt or reset function */
- SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode;
-
- /* Select Brown-out Detector threshold voltage */
- SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
-}
-
-/**
- * @brief Disable Brown-out detector function
- * @param None
- * @return None
- * @details This function disable Brown-out detector function.
- * The register write-protection function should be disabled before using this function.
- */
-void SYS_DisableBOD(void)
-{
- SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
-}
-
-
-
-/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SYS_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_sys.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,970 +0,0 @@
-/**************************************************************************//**
- * @file SYS.h
- * @version V3.0
- * $Revision 1 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 Series SYS Header File
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- ******************************************************************************/
-
-#ifndef __SYS_H__
-#define __SYS_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup SYS_Driver SYS Driver
- @{
-*/
-
-/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
- @{
-*/
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Module Reset Control Resister constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_RST ((0x0<<24) | SYS_IPRST0_PDMARST_Pos ) /*!< Reset PDMA */
-#define EBI_RST ((0x0<<24) | SYS_IPRST0_EBIRST_Pos ) /*!< Reset EBI */
-#define USBH_RST ((0x0<<24) | SYS_IPRST0_USBHRST_Pos ) /*!< Reset USBH */
-#define CRC_RST ((0x0<<24) | SYS_IPRST0_CRCRST_Pos ) /*!< Reset CRC */
-
-#define GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos ) /*!< Reset GPIO */
-#define TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos ) /*!< Reset TMR0 */
-#define TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos ) /*!< Reset TMR1 */
-#define TMR2_RST ((0x4<<24) | SYS_IPRST1_TMR2RST_Pos ) /*!< Reset TMR2 */
-#define TMR3_RST ((0x4<<24) | SYS_IPRST1_TMR3RST_Pos ) /*!< Reset TMR3 */
-#define ACMP01_RST ((0x4<<24) | SYS_IPRST1_ACMP01RST_Pos ) /*!< Reset ACMP01 */
-#define I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos ) /*!< Reset I2C0 */
-#define I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos ) /*!< Reset I2C1 */
-#define SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos ) /*!< Reset SPI0 */
-#define SPI1_RST ((0x4<<24) | SYS_IPRST1_SPI1RST_Pos ) /*!< Reset SPI1 */
-#define SPI2_RST ((0x4<<24) | SYS_IPRST1_SPI2RST_Pos ) /*!< Reset SPI2 */
-#define UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos ) /*!< Reset UART0 */
-#define UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos ) /*!< Reset UART1 */
-#define UART2_RST ((0x4<<24) | SYS_IPRST1_UART2RST_Pos ) /*!< Reset UART2 */
-#define UART3_RST ((0x4<<24) | SYS_IPRST1_UART3RST_Pos ) /*!< Reset UART3 */
-#define CAN0_RST ((0x4<<24) | SYS_IPRST1_CAN0RST_Pos ) /*!< Reset CAN0 */
-#define OTG_RST ((0x4<<24) | SYS_IPRST1_OTGRST_Pos ) /*!< Reset OTG */
-#define USBD_RST ((0x4<<24) | SYS_IPRST1_USBDRST_Pos ) /*!< Reset USBD */
-#define EADC_RST ((0x4<<24) | SYS_IPRST1_EADCRST_Pos ) /*!< Reset EADC */
-
-#define SC0_RST ((0x8<<24) | SYS_IPRST2_SC0RST_Pos ) /*!< Reset SC0 */
-#define DAC_RST ((0x8<<24) | SYS_IPRST2_DACRST_Pos ) /*!< Reset DAC */
-#define PWM0_RST ((0x8<<24) | SYS_IPRST2_PWM0RST_Pos ) /*!< Reset PWM0 */
-#define PWM1_RST ((0x8<<24) | SYS_IPRST2_PWM1RST_Pos ) /*!< Reset PWM1 */
-#define TK_RST ((0x8<<24) | SYS_IPRST2_TKRST_Pos ) /*!< Reset TK */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Brown Out Detector Threshold Voltage Selection constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */
-#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */
-#define SYS_BODCTL_BODVL_4_5V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 4.5V */
-#define SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.7V */
-#define SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.7V */
-#define SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* VREFCTL constant definitions. (Write-Protection Register) */
-/*---------------------------------------------------------------------------------------------------------*/
-#define SYS_VREFCTL_VREF_2_56V (0x3UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 2.56V */
-#define SYS_VREFCTL_VREF_2_048V (0x7UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 2.048V */
-#define SYS_VREFCTL_VREF_3_072V (0xBUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 3.072V */
-#define SYS_VREFCTL_VREF_4_096V (0xFUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT = 4.096V */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* USBPHY constant definitions. (Write-Protection Register) */
-/*---------------------------------------------------------------------------------------------------------*/
-#define SYS_USBPHY_USBROLE_OTG_V33_EN (0x1UL<<SYS_USBPHY_LDO33EN_Pos) /*!< USB LDO33 Enabled */
-#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */
-#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */
-#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */
-#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Multi-Function constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-/* How to use below #define?
-Example 1: If user want to set PA.0 as SC0_CLK in initial function,
- user can issue following command to achieve it.
-
- SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0_MFP_SC0_CLK ;
-
-*/
-//PA0 MFP
-#define SYS_GPA_MFPL_PA0MFP_GPIO (0ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO*/
-#define SYS_GPA_MFPL_PA0MFP_UART1_nCTS (1ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nCTS*/
-#define SYS_GPA_MFPL_PA0MFP_UART1_TXD (3ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_TXD*/
-#define SYS_GPA_MFPL_PA0MFP_CAN0_RXD (4ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for CAN0_RXD*/
-#define SYS_GPA_MFPL_PA0MFP_SC0_CLK (5ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CLK*/
-#define SYS_GPA_MFPL_PA0MFP_PWM1_CH5 (6ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for PWM1_CH5*/
-#define SYS_GPA_MFPL_PA0MFP_EBI_AD0 (7ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for EBI_AD0*/
-#define SYS_GPA_MFPL_PA0MFP_INT0 (8ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for INT0*/
-#define SYS_GPA_MFPL_PA0MFP_SPI1_I2SMCLK (9ul << SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI1_I2SMCLK*/
-
-//PA1 MFP
-#define SYS_GPA_MFPL_PA1MFP_GPIO (0ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO*/
-#define SYS_GPA_MFPL_PA1MFP_UART1_nRTS (1ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nRTS*/
-#define SYS_GPA_MFPL_PA1MFP_UART1_RXD (3ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_RXD*/
-#define SYS_GPA_MFPL_PA1MFP_CAN0_TXD (4ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for CAN0_TXD*/
-#define SYS_GPA_MFPL_PA1MFP_SC0_DAT (5ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC0_DAT*/
-#define SYS_GPA_MFPL_PA1MFP_PWM1_CH4 (6ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for PWM1_CH4*/
-#define SYS_GPA_MFPL_PA1MFP_EBI_AD1 (7ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EBI_AD1*/
-#define SYS_GPA_MFPL_PA1MFP_STADC (10ul << SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for STADC*/
-
-//PA2 MFP
-#define SYS_GPA_MFPL_PA2MFP_GPIO (0ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO*/
-#define SYS_GPA_MFPL_PA2MFP_USB_VBUS_EN (1ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for USB_VBUS_EN*/
-#define SYS_GPA_MFPL_PA2MFP_UART0_TXD (2ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_TXD*/
-#define SYS_GPA_MFPL_PA2MFP_UART0_nCTS (3ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART0_nCTS*/
-#define SYS_GPA_MFPL_PA2MFP_I2C0_SDA (4ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C0_SDA*/
-#define SYS_GPA_MFPL_PA2MFP_SC0_RST (5ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC0_RST*/
-#define SYS_GPA_MFPL_PA2MFP_PWM1_CH3 (6ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for PWM1_CH3*/
-#define SYS_GPA_MFPL_PA2MFP_EBI_AD2 (7ul << SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EBI_AD2*/
-
-//PA3 MFP
-#define SYS_GPA_MFPL_PA3MFP_GPIO (0ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO*/
-#define SYS_GPA_MFPL_PA3MFP_USB_VBUS_ST (1ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for USB_VBUS_ST*/
-#define SYS_GPA_MFPL_PA3MFP_UART0_RXD (2ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_RXD*/
-#define SYS_GPA_MFPL_PA3MFP_UART0_nRTS (3ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART0_nRTS*/
-#define SYS_GPA_MFPL_PA3MFP_I2C0_SCL (4ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C0_SCL*/
-#define SYS_GPA_MFPL_PA3MFP_SC0_PWR (5ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC0_PWR*/
-#define SYS_GPA_MFPL_PA3MFP_PWM1_CH2 (6ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for PWM1_CH2*/
-#define SYS_GPA_MFPL_PA3MFP_EBI_AD3 (7ul << SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EBI_AD3*/
-
-//PA4 MFP
-#define SYS_GPA_MFPL_PA4MFP_GPIO (0ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO*/
-#define SYS_GPA_MFPL_PA4MFP_SPI1_SS (2ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI1_SS*/
-#define SYS_GPA_MFPL_PA4MFP_EBI_AD4 (7ul << SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EBI_AD4*/
-
-//PA5 MFP
-#define SYS_GPA_MFPL_PA5MFP_GPIO (0ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO*/
-#define SYS_GPA_MFPL_PA5MFP_SPI1_MOSI (2ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI1_MOSI*/
-#define SYS_GPA_MFPL_PA5MFP_T2_EXT (3ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for T2_EXT*/
-#define SYS_GPA_MFPL_PA5MFP_EBI_AD5 (7ul << SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EBI_AD5*/
-
-//PA6 MFP
-#define SYS_GPA_MFPL_PA6MFP_GPIO (0ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO*/
-#define SYS_GPA_MFPL_PA6MFP_SPI1_MISO (2ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SPI1_MISO*/
-#define SYS_GPA_MFPL_PA6MFP_T1_EXT (3ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for T1_EXT*/
-#define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (7ul << SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6*/
-
-//PA7 MFP
-#define SYS_GPA_MFPL_PA7MFP_GPIO (0ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO*/
-#define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (2ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI1_CLK*/
-#define SYS_GPA_MFPL_PA7MFP_T0_EXT (3ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for T0_EXT*/
-#define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (7ul << SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7*/
-
-//PA8 MFP
-#define SYS_GPA_MFPH_PA8MFP_GPIO (0ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO*/
-#define SYS_GPA_MFPH_PA8MFP_UART3_TXD (3ul << SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART3_TXD*/
-
-//PA9 MFP
-#define SYS_GPA_MFPH_PA9MFP_GPIO (0ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO*/
-#define SYS_GPA_MFPH_PA9MFP_UART3_RXD (3ul << SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART3_RXD*/
-
-//PA10 MFP
-#define SYS_GPA_MFPH_PA10MFP_GPIO (0ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for GPIO*/
-#define SYS_GPA_MFPH_PA10MFP_UART3_nCTS (3ul << SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for UART3_nCTS*/
-
-//PA11 MFP
-#define SYS_GPA_MFPH_PA11MFP_GPIO (0ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for GPIO*/
-#define SYS_GPA_MFPH_PA11MFP_UART3_nRTS (3ul << SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for UART3_nRTS*/
-
-//PA12 MFP
-#define SYS_GPA_MFPH_PA12MFP_GPIO (0ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for GPIO*/
-#define SYS_GPA_MFPH_PA12MFP_SPI1_I2SMCLK (2ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SPI1_I2SMCLK*/
-#define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (4ul << SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for CAN0_TXD*/
-
-//PA13 MFP
-#define SYS_GPA_MFPH_PA13MFP_GPIO (0ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for GPIO*/
-#define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (4ul << SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for CAN0_RXD*/
-
-//PA14 MFP
-#define SYS_GPA_MFPH_PA14MFP_GPIO (0ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for GPIO*/
-#define SYS_GPA_MFPH_PA14MFP_UART2_nCTS (3ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for UART2_nCTS*/
-#define SYS_GPA_MFPH_PA14MFP_I2C0_SMBAL (4ul << SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for I2C0_SMBAL*/
-
-//PA15 MFP
-#define SYS_GPA_MFPH_PA15MFP_GPIO (0ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for GPIO*/
-#define SYS_GPA_MFPH_PA15MFP_UART2_nRTS (3ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for UART2_nRTS*/
-#define SYS_GPA_MFPH_PA15MFP_I2C0_SMBSUS (4ul << SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2C0_SMBSUS*/
-
-//PB0 MFP
-#define SYS_GPB_MFPL_PB0MFP_GPIO (0ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO*/
-#define SYS_GPB_MFPL_PB0MFP_EADC_CH0 (1ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC_CH0*/
-#define SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1 (2ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_MOSI1*/
-#define SYS_GPB_MFPL_PB0MFP_UART2_RXD (3ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD*/
-#define SYS_GPB_MFPL_PB0MFP_T2 (4ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for T2*/
-#define SYS_GPB_MFPL_PB0MFP_DAC (5ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for DAC*/
-#define SYS_GPB_MFPL_PB0MFP_EBI_nWRL (7ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_nWRL*/
-#define SYS_GPB_MFPL_PB0MFP_INT1 (8ul << SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for INT1*/
-
-//PB1 MFP
-#define SYS_GPB_MFPL_PB1MFP_GPIO (0ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO*/
-#define SYS_GPB_MFPL_PB1MFP_EADC_CH1 (1ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EADC_CH1*/
-#define SYS_GPB_MFPL_PB1MFP_SPI0_MISO1 (2ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI0_MISO1*/
-#define SYS_GPB_MFPL_PB1MFP_UART2_TXD (3ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD*/
-#define SYS_GPB_MFPL_PB1MFP_T3 (4ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for T3*/
-#define SYS_GPB_MFPL_PB1MFP_SC0_RST (5ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SC0_RST*/
-#define SYS_GPB_MFPL_PB1MFP_PWM0_SYNC_OUT (6ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for PWM0_SYNC_OUT*/
-#define SYS_GPB_MFPL_PB1MFP_EBI_nWRH (7ul << SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_nWRH*/
-
-//PB2 MFP
-#define SYS_GPB_MFPL_PB2MFP_GPIO (0ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO*/
-#define SYS_GPB_MFPL_PB2MFP_EADC_CH2 (1ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EADC_CH2*/
-#define SYS_GPB_MFPL_PB2MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI0_CLK*/
-#define SYS_GPB_MFPL_PB2MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI1_CLK*/
-#define SYS_GPB_MFPL_PB2MFP_UART1_RXD (4ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD*/
-#define SYS_GPB_MFPL_PB2MFP_SC0_CD (5ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SC0_CD*/
-#define SYS_GPB_MFPL_PB2MFP_UART3_RXD (9ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART3_RXD*/
-#define SYS_GPB_MFPL_PB2MFP_T2_EXT (11ul << SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for T2_EXT*/
-
-//PB3
-#define SYS_GPB_MFPL_PB3MFP_GPIO (0ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO*/
-#define SYS_GPB_MFPL_PB3MFP_EADC_CH3 (1ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EADC_CH3*/
-#define SYS_GPB_MFPL_PB3MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI0_MISO0*/
-#define SYS_GPB_MFPL_PB3MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI1_MISO*/
-#define SYS_GPB_MFPL_PB3MFP_UART1_TXD (4ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD*/
-#define SYS_GPB_MFPL_PB3MFP_UART3_TXD (9ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART3_TXD*/
-#define SYS_GPB_MFPL_PB3MFP_T0_EXT (11ul << SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for T0_EXT*/
-
-//PB4
-#define SYS_GPB_MFPL_PB4MFP_GPIO (0ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO*/
-#define SYS_GPB_MFPL_PB4MFP_EADC_CH4 (1ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EADC_CH4*/
-#define SYS_GPB_MFPL_PB4MFP_SPI0_SS (2ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI0_SS*/
-#define SYS_GPB_MFPL_PB4MFP_SPI1_SS (3ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI1_SS*/
-#define SYS_GPB_MFPL_PB4MFP_UART1_nCTS (4ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART1_nCTS*/
-#define SYS_GPB_MFPL_PB4MFP_ACMP0_N (5ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP0_N*/
-#define SYS_GPB_MFPL_PB4MFP_EBI_AD7 (7ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_AD7*/
-#define SYS_GPB_MFPL_PB4MFP_UART2_TXD (9ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART2_TXD*/
-#define SYS_GPB_MFPL_PB4MFP_T1_EXT (11ul << SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for T1_EXT*/
-
-//PB5
-#define SYS_GPB_MFPL_PB5MFP_GPIO (0ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO*/
-#define SYS_GPB_MFPL_PB5MFP_EADC_CH13 (1ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EADC_CH13*/
-#define SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0 (2ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI0_MOSI0*/
-#define SYS_GPB_MFPL_PB5MFP_SPI1_MOSI (3ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI1_MOSI*/
-#define SYS_GPB_MFPL_PB5MFP_TK3 (4ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TK3*/
-#define SYS_GPB_MFPL_PB5MFP_ACMP0_P2 (5ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP0_P2*/
-#define SYS_GPB_MFPL_PB5MFP_EBI_AD6 (7ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_AD6*/
-#define SYS_GPB_MFPL_PB5MFP_UART2_RXD (9ul << SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART2_RXD*/
-
-//PB6
-#define SYS_GPB_MFPL_PB6MFP_GPIO (0ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO*/
-#define SYS_GPB_MFPL_PB6MFP_EADC_CH14 (1ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EADC_CH14*/
-#define SYS_GPB_MFPL_PB6MFP_SPI0_MISO0 (2ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI0_MISO0*/
-#define SYS_GPB_MFPL_PB6MFP_SPI1_MISO (3ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for SPI1_MISO*/
-#define SYS_GPB_MFPL_PB6MFP_TK4 (4ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for TK4*/
-#define SYS_GPB_MFPL_PB6MFP_ACMP0_P1 (5ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP0_P1*/
-#define SYS_GPB_MFPL_PB6MFP_EBI_AD5 (7ul << SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_AD5*/
-
-//PB7
-#define SYS_GPB_MFPL_PB7MFP_GPIO (0ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO*/
-#define SYS_GPB_MFPL_PB7MFP_EADC_CH15 (1ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EADC_CH15*/
-#define SYS_GPB_MFPL_PB7MFP_SPI0_CLK (2ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI0_CLK*/
-#define SYS_GPB_MFPL_PB7MFP_SPI1_CLK (3ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for SPI1_CLK*/
-#define SYS_GPB_MFPL_PB7MFP_TK5 (4ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for TK5*/
-#define SYS_GPB_MFPL_PB7MFP_ACMP0_P0 (5ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_P0*/
-#define SYS_GPB_MFPL_PB7MFP_EBI_AD4 (7ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_AD4*/
-#define SYS_GPB_MFPL_PB7MFP_STADC (10ul << SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for STADC*/
-
-//PB8
-#define SYS_GPB_MFPH_PB8MFP_GPIO (0ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO*/
-#define SYS_GPB_MFPH_PB8MFP_EADC_CH5 (1ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EADC_CH5*/
-#define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (4ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS*/
-#define SYS_GPB_MFPH_PB8MFP_PWM0_CH2 (6ul << SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for PWM0_CH2*/
-
-//PB9
-#define SYS_GPB_MFPH_PB9MFP_GPIO (0ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO*/
-#define SYS_GPB_MFPH_PB9MFP_EADC_CH6 (1ul << SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EADC_CH6*/
-
-//PB10
-#define SYS_GPB_MFPH_PB10MFP_GPIO (0ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for GPIO*/
-#define SYS_GPB_MFPH_PB10MFP_EADC_CH7 (1ul << SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH_ PB10 setting for EADC_CH7*/
-
-//PB11
-#define SYS_GPB_MFPH_PB11MFP_GPIO (0ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for GPIO*/
-#define SYS_GPB_MFPH_PB11MFP_EADC_CH8 (1ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for EADC_CH8*/
-#define SYS_GPB_MFPH_PB11MFP_TK0 (4ul << SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH_ PB11 setting for TK0*/
-
-//PB12
-#define SYS_GPB_MFPH_PB12MFP_GPIO (0ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for GPIO*/
-#define SYS_GPB_MFPH_PB12MFP_EADC_CH9 (1ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for EADC_CH9*/
-#define SYS_GPB_MFPH_PB12MFP_TK1 (4ul << SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH_ PB12 setting for TK1*/
-
-//PB13
-#define SYS_GPB_MFPH_PB13MFP_GPIO (0ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for GPIO*/
-#define SYS_GPB_MFPH_PB13MFP_EADC_CH10 (1ul << SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EADC_CH10*/
-
-//PB14
-#define SYS_GPB_MFPH_PB14MFP_GPIO (0ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for GPIO*/
-#define SYS_GPB_MFPH_PB14MFP_EADC_CH11 (1ul << SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EADC_CH11*/
-
-//PB15
-#define SYS_GPB_MFPH_PB15MFP_GPIO (0ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for GPIO*/
-#define SYS_GPB_MFPH_PB15MFP_EADC_CH12 (1ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EADC_CH12*/
-#define SYS_GPB_MFPH_PB15MFP_TK2 (4ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for TK2*/
-#define SYS_GPB_MFPH_PB15MFP_ACMP0_P3 (5ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for ACMP0_P3*/
-#define SYS_GPB_MFPH_PB15MFP_EBI_nCS1 (7ul << SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EBI_nCS1*/
-
-//PC0
-#define SYS_GPC_MFPL_PC0MFP_GPIO (0ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO*/
-#define SYS_GPC_MFPL_PC0MFP_SPI2_CLK (2ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI2_CLK*/
-#define SYS_GPC_MFPL_PC0MFP_UART2_nCTS (3ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_nCTS*/
-#define SYS_GPC_MFPL_PC0MFP_CAN0_TXD (4ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for CAN0_TXD*/
-#define SYS_GPC_MFPL_PC0MFP_PWM0_CH0 (6ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for PWM0_CH0*/
-#define SYS_GPC_MFPL_PC0MFP_EBI_AD8 (7ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD8*/
-#define SYS_GPC_MFPL_PC0MFP_INT2 (8ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for INT2*/
-#define SYS_GPC_MFPL_PC0MFP_UART3_TXD (9ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART3_TXD*/
-#define SYS_GPC_MFPL_PC0MFP_T3_EXT (11ul << SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for T3_EXT*/
-
-//PC1
-#define SYS_GPC_MFPL_PC1MFP_GPIO (0ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO*/
-#define SYS_GPC_MFPL_PC1MFP_CLKO (1ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CLKO*/
-#define SYS_GPC_MFPL_PC1MFP_STDAC (2ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for STDAC*/
-#define SYS_GPC_MFPL_PC1MFP_UART2_nRTS (3ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_nRTS*/
-#define SYS_GPC_MFPL_PC1MFP_CAN0_RXD (4ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for CAN0_RXD*/
-#define SYS_GPC_MFPL_PC1MFP_PWM0_CH1 (6ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for PWM0_CH1*/
-#define SYS_GPC_MFPL_PC1MFP_EBI_AD9 (7ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD9*/
-#define SYS_GPC_MFPL_PC1MFP_UART3_RXD (9ul << SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART3_RXD*/
-
-//PC2
-#define SYS_GPC_MFPL_PC2MFP_GPIO (0ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO*/
-#define SYS_GPC_MFPL_PC2MFP_SPI2_SS (2ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI2_SS*/
-#define SYS_GPC_MFPL_PC2MFP_UART2_TXD (3ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_TXD*/
-#define SYS_GPC_MFPL_PC2MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for ACMP1_O*/
-#define SYS_GPC_MFPL_PC2MFP_PWM0_CH2 (6ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for PWM0_CH2*/
-#define SYS_GPC_MFPL_PC2MFP_EBI_AD10 (7ul << SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD10*/
-
-//PC3
-#define SYS_GPC_MFPL_PC3MFP_GPIO (0ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO*/
-#define SYS_GPC_MFPL_PC3MFP_SPI2_MOSI (2ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI2_MOSI*/
-#define SYS_GPC_MFPL_PC3MFP_UART2_RXD (3ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_RXD*/
-#define SYS_GPC_MFPL_PC3MFP_USB_VBUS_ST (4ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for USB_VBUS_ST*/
-#define SYS_GPC_MFPL_PC3MFP_PWM0_CH3 (6ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for PWM0_CH3*/
-#define SYS_GPC_MFPL_PC3MFP_EBI_AD11 (7ul << SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD11*/
-
-//PC4
-#define SYS_GPC_MFPL_PC4MFP_GPIO (0ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO*/
-#define SYS_GPC_MFPL_PC4MFP_SPI2_MISO (2ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI2_MISO*/
-#define SYS_GPC_MFPL_PC4MFP_I2C1_SCL (3ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SCL*/
-#define SYS_GPC_MFPL_PC4MFP_USB_VBUS_EN (4ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for USB_VBUS_EN*/
-#define SYS_GPC_MFPL_PC4MFP_PWM0_CH4 (6ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for PWM0_CH4*/
-#define SYS_GPC_MFPL_PC4MFP_EBI_AD12 (7ul << SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD12*/
-
-//PC5
-#define SYS_GPC_MFPL_PC5MFP_GPIO (0ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO*/
-#define SYS_GPC_MFPL_PC5MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for SPI2_I2SMCLK*/
-#define SYS_GPC_MFPL_PC5MFP_PWM0_CH5 (6ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for PWM0_CH5*/
-#define SYS_GPC_MFPL_PC5MFP_EBI_AD13 (7ul << SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD13*/
-
-//PC6
-#define SYS_GPC_MFPL_PC6MFP_GPIO (0ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO*/
-#define SYS_GPC_MFPL_PC6MFP_I2C1_SMBAL (3ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for I2C1_SMBAL*/
-#define SYS_GPC_MFPL_PC6MFP_ACMP1_O (5ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for ACMP1_O*/
-#define SYS_GPC_MFPL_PC6MFP_PWM1_CH0 (6ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for PWM1_CH0*/
-#define SYS_GPC_MFPL_PC6MFP_EBI_AD14 (7ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD14*/
-#define SYS_GPC_MFPL_PC6MFP_UART0_TXD (9ul << SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_TXD*/
-
-//PC7
-#define SYS_GPC_MFPL_PC7MFP_GPIO (0ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO*/
-#define SYS_GPC_MFPL_PC7MFP_I2C1_SMBSUS (3ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for I2C1_SMBSUS*/
-#define SYS_GPC_MFPL_PC7MFP_PWM1_CH1 (6ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for PWM1_CH1*/
-#define SYS_GPC_MFPL_PC7MFP_EBI_AD15 (7ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD15*/
-#define SYS_GPC_MFPL_PC7MFP_UART0_RXD (9ul << SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_RXD*/
-
-//PC8
-#define SYS_GPC_MFPH_PC8MFP_GPIO (0ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for GPIO*/
-#define SYS_GPC_MFPH_PC8MFP_TK7 (4ul << SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH_ PC8 setting for TK7*/
-
-//PC9
-#define SYS_GPC_MFPH_PC9MFP_GPIO (0ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO*/
-#define SYS_GPC_MFPH_PC9MFP_SPI2_I2SMCLK (2ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SPI2_I2SMCLK*/
-#define SYS_GPC_MFPH_PC9MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for PWM1_CH0*/
-
-//PC10
-#define SYS_GPC_MFPH_PC10MFP_GPIO (0ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for GPIO*/
-#define SYS_GPC_MFPH_PC10MFP_SPI2_MOSI (2ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for SPI2_MOSI*/
-#define SYS_GPC_MFPH_PC10MFP_PWM1_CH1 (6ul << SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for PWM1_CH1*/
-
-//PC11
-#define SYS_GPC_MFPH_PC11MFP_GPIO (0ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for GPIO*/
-#define SYS_GPC_MFPH_PC11MFP_SPI2_MISO (2ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for SPI2_MISO*/
-#define SYS_GPC_MFPH_PC11MFP_PWM1_CH2 (6ul << SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for PWM1_CH2*/
-
-//PC12
-#define SYS_GPC_MFPH_PC12MFP_GPIO (0ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for GPIO*/
-#define SYS_GPC_MFPH_PC12MFP_SPI2_CLK (2ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SPI2_CLK*/
-#define SYS_GPC_MFPH_PC12MFP_PWM1_CH3 (6ul << SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for PWM1_CH3*/
-
-//PC13
-#define SYS_GPC_MFPH_PC13MFP_GPIO (0ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for GPIO*/
-#define SYS_GPC_MFPH_PC13MFP_SPI2_SS (2ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SPI2_SS*/
-#define SYS_GPC_MFPH_PC13MFP_PWM1_CH4 (6ul << SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for PWM1_CH4*/
-
-//PC14
-#define SYS_GPC_MFPH_PC14MFP_GPIO (0ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for GPIO*/
-#define SYS_GPC_MFPH_PC14MFP_PWM1_CH5 (6ul << SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for PWM1_CH5*/
-
-//PC15
-#define SYS_GPC_MFPH_PC15MFP_GPIO (0ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for GPIO*/
-#define SYS_GPC_MFPH_PC15MFP_PWM1_CH0 (6ul << SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for PWM1_CH0*/
-
-//PD0
-#define SYS_GPD_MFPL_PD0MFP_GPIO (0ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO*/
-#define SYS_GPD_MFPL_PD0MFP_EADC_CH6 (1ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EADC_CH6*/
-#define SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK (2ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI1_I2SMCLK*/
-#define SYS_GPD_MFPL_PD0MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART0_RXD*/
-#define SYS_GPD_MFPL_PD0MFP_TK6 (4ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TK6*/
-#define SYS_GPD_MFPL_PD0MFP_ACMP1_N (5ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for ACMP1_N*/
-#define SYS_GPD_MFPL_PD0MFP_INT3 (8ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for INT3*/
-#define SYS_GPD_MFPL_PD0MFP_T3 (11ul << SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for T3*/
-
-//PD1
-#define SYS_GPD_MFPL_PD1MFP_GPIO (0ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO*/
-#define SYS_GPD_MFPL_PD1MFP_EADC_CH11 (1ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EADC_CH11*/
-#define SYS_GPD_MFPL_PD1MFP_PWM0_SYNC_IN (2ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for PWM0_SYNC_IN*/
-#define SYS_GPD_MFPL_PD1MFP_UART0_TXD (3ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART0_TXD*/
-#define SYS_GPD_MFPL_PD1MFP_TK10 (4ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for TK10*/
-#define SYS_GPD_MFPL_PD1MFP_ACMP1_P2 (5ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for ACMP1_P2*/
-#define SYS_GPD_MFPL_PD1MFP_T0 (6ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for T0*/
-#define SYS_GPD_MFPL_PD1MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_nRD*/
-
-//PD2
-#define SYS_GPD_MFPL_PD2MFP_GPIO (0ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO*/
-#define SYS_GPD_MFPL_PD2MFP_STADC (1ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for STADC*/
-#define SYS_GPD_MFPL_PD2MFP_T0_EXT (3ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for T0_EXT*/
-#define SYS_GPD_MFPL_PD2MFP_TK11 (4ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for TK11*/
-#define SYS_GPD_MFPL_PD2MFP_ACMP1_P1 (5ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for ACMP1_P1*/
-#define SYS_GPD_MFPL_PD2MFP_PWM0_BRAKE0 (6ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for PWM0_BRAKE0*/
-#define SYS_GPD_MFPL_PD2MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_nWR*/
-#define SYS_GPD_MFPL_PD2MFP_INT0 (8ul << SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for INT0*/
-
-//PD3
-#define SYS_GPD_MFPL_PD3MFP_GPIO (0ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO*/
-#define SYS_GPD_MFPL_PD3MFP_T2 (1ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T2*/
-#define SYS_GPD_MFPL_PD3MFP_T1_EXT (3ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for T1_EXT*/
-#define SYS_GPD_MFPL_PD3MFP_TK12 (4ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for TK12*/
-#define SYS_GPD_MFPL_PD3MFP_ACMP1_P0 (5ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for ACMP1_P0*/
-#define SYS_GPD_MFPL_PD3MFP_PWM0_BRAKE1 (6ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for PWM0_BRAKE1*/
-#define SYS_GPD_MFPL_PD3MFP_EBI_MCLK (7ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_MCLK*/
-#define SYS_GPD_MFPL_PD3MFP_INT1 (8ul << SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for INT1*/
-
-//PD4
-#define SYS_GPD_MFPL_PD4MFP_GPIO (0ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO*/
-#define SYS_GPD_MFPL_PD4MFP_SPI1_CLK (2ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SPI1_CLK*/
-#define SYS_GPD_MFPL_PD4MFP_I2C0_SDA (3ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C0_SDA*/
-#define SYS_GPD_MFPL_PD4MFP_TK13 (4ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for TK13*/
-#define SYS_GPD_MFPL_PD4MFP_PWM0_BRAKE0 (5ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for PWM0_BRAKE0*/
-#define SYS_GPD_MFPL_PD4MFP_T0 (6ul << SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for T0*/
-
-//PD5
-#define SYS_GPD_MFPL_PD5MFP_GPIO (0ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO*/
-#define SYS_GPD_MFPL_PD5MFP_CLKO (1ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for CLKO*/
-#define SYS_GPD_MFPL_PD5MFP_SPI1_MISO (2ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SPI1_MISO*/
-#define SYS_GPD_MFPL_PD5MFP_I2C0_SCL (3ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C0_SCL*/
-#define SYS_GPD_MFPL_PD5MFP_TK14 (4ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for TK14*/
-#define SYS_GPD_MFPL_PD5MFP_PWM0_BRAKE1 (5ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for PWM0_BRAKE1*/
-#define SYS_GPD_MFPL_PD5MFP_T1 (6ul << SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for T1*/
-
-//PD6
-#define SYS_GPD_MFPL_PD6MFP_GPIO (0ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO*/
-#define SYS_GPD_MFPL_PD6MFP_CLKO (1ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for CLKO*/
-#define SYS_GPD_MFPL_PD6MFP_SPI1_SS (2ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SPI1_SS*/
-#define SYS_GPD_MFPL_PD6MFP_UART0_RXD (3ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART0_RXD*/
-#define SYS_GPD_MFPL_PD6MFP_TK16 (4ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for TK16*/
-#define SYS_GPD_MFPL_PD6MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for ACMP0_O*/
-#define SYS_GPD_MFPL_PD6MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for PWM0_CH5*/
-#define SYS_GPD_MFPL_PD6MFP_EBI_nWR (7ul << SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for EBI_nWR*/
-
-//PD7
-#define SYS_GPD_MFPL_PD7MFP_GPIO (0ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO*/
-#define SYS_GPD_MFPL_PD7MFP_PWM0_SYNC_IN (3ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_SYNC_IN*/
-#define SYS_GPD_MFPL_PD7MFP_T1 (4ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for T1*/
-#define SYS_GPD_MFPL_PD7MFP_ACMP0_O (5ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for ACMP0_O*/
-#define SYS_GPD_MFPL_PD7MFP_PWM0_CH5 (6ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for PWM0_CH5*/
-#define SYS_GPD_MFPL_PD7MFP_EBI_nRD (7ul << SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for EBI_nRD*/
-
-//PD8
-#define SYS_GPD_MFPH_PD8MFP_GPIO (0ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO*/
-#define SYS_GPD_MFPH_PD8MFP_EADC_CH7 (1ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EADC_CH7*/
-#define SYS_GPD_MFPH_PD8MFP_TK8 (4ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for TK8*/
-#define SYS_GPD_MFPH_PD8MFP_EBI_nCS0 (7ul << SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_nCS0*/
-
-//PD9
-#define SYS_GPD_MFPH_PD9MFP_GPIO (0ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO*/
-#define SYS_GPD_MFPH_PD9MFP_EADC_CH10 (1ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EADC_CH10*/
-#define SYS_GPD_MFPH_PD9MFP_TK9 (4ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for TK9*/
-#define SYS_GPD_MFPH_PD9MFP_ACMP1_P3 (5ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for ACMP1_P3*/
-#define SYS_GPD_MFPH_PD9MFP_EBI_ALE (7ul << SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_ALE*/
-
-//PD10
-#define SYS_GPD_MFPH_PD10MFP_GPIO (0ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for GPIO*/
-#define SYS_GPD_MFPH_PD10MFP_T2 (4ul << SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for T2*/
-
-//PD11
-#define SYS_GPD_MFPH_PD11MFP_GPIO (0ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for GPIO*/
-#define SYS_GPD_MFPH_PD11MFP_T3 (4ul << SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for T3*/
-
-//PD12
-#define SYS_GPD_MFPH_PD12MFP_GPIO (0ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for GPIO*/
-#define SYS_GPD_MFPH_PD12MFP_SPI2_SS (2ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for SPI2_SS*/
-#define SYS_GPD_MFPH_PD12MFP_UART3_TXD (3ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for UART3_TXD*/
-#define SYS_GPD_MFPH_PD12MFP_PWM1_CH0 (6ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for PWM1_CH0*/
-#define SYS_GPD_MFPH_PD12MFP_EBI_ADR16 (7ul << SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for EBI_ADR16*/
-
-//PD13
-#define SYS_GPD_MFPH_PD13MFP_GPIO (0ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for GPIO*/
-#define SYS_GPD_MFPH_PD13MFP_SPI2_MOSI (2ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for SPI2_MOSI*/
-#define SYS_GPD_MFPH_PD13MFP_UART3_RXD (3ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for UART3_RXD*/
-#define SYS_GPD_MFPH_PD13MFP_PWM1_CH1 (6ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for PWM1_CH1*/
-#define SYS_GPD_MFPH_PD13MFP_EBI_ADR17 (7ul << SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for EBI_ADR17*/
-
-//PD14
-#define SYS_GPD_MFPH_PD14MFP_GPIO (0ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for GPIO*/
-#define SYS_GPD_MFPH_PD14MFP_SPI2_MISO (2ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for SPI2_MISO*/
-#define SYS_GPD_MFPH_PD14MFP_UART3_nCTS (3ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for UART3_nCTS*/
-#define SYS_GPD_MFPH_PD14MFP_PWM1_CH2 (6ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for PWM1_CH2*/
-#define SYS_GPD_MFPH_PD14MFP_EBI_ADR18 (7ul << SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH_ PD14 setting for EBI_ADR18*/
-
-//PD15
-#define SYS_GPD_MFPH_PD15MFP_GPIO (0ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for GPIO*/
-#define SYS_GPD_MFPH_PD15MFP_SPI2_CLK (2ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for SPI2_CLK*/
-#define SYS_GPD_MFPH_PD15MFP_UART3_nRTS (3ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for UART3_nRTS*/
-#define SYS_GPD_MFPH_PD15MFP_PWM1_CH3 (6ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for PWM1_CH3*/
-#define SYS_GPD_MFPH_PD15MFP_EBI_ADR19 (7ul << SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH_ PD15 setting for EBI_ADR19*/
-
-//PE0
-#define SYS_GPE_MFPL_PE0MFP_GPIO (0ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO*/
-#define SYS_GPE_MFPL_PE0MFP_SPI2_CLK (2ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SPI2_CLK*/
-#define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA*/
-#define SYS_GPE_MFPL_PE0MFP_T2_EXT (4ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for T2_EXT*/
-#define SYS_GPE_MFPL_PE0MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SC0_CD*/
-#define SYS_GPE_MFPL_PE0MFP_PWM0_CH0 (6ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for PWM0_CH0*/
-#define SYS_GPE_MFPL_PE0MFP_EBI_nCS1 (7ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_nCS1*/
-#define SYS_GPE_MFPL_PE0MFP_INT4 (8ul << SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for INT4*/
-
-//PE1
-#define SYS_GPE_MFPL_PE1MFP_GPIO (0ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO*/
-#define SYS_GPE_MFPL_PE1MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for T3_EXT*/
-#define SYS_GPE_MFPL_PE1MFP_SC0_CD (5ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SC0_CD*/
-#define SYS_GPE_MFPL_PE1MFP_PWM0_CH1 (6ul << SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for PWM0_CH1*/
-
-//PE2
-#define SYS_GPE_MFPL_PE2MFP_GPIO (0ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO*/
-#define SYS_GPE_MFPL_PE2MFP_PWM1_CH1 (6ul << SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for PWM1_CH1*/
-
-//PE3
-#define SYS_GPE_MFPL_PE3MFP_GPIO (0ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO*/
-#define SYS_GPE_MFPL_PE3MFP_SPI1_MOSI (2ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI1_MOSI*/
-#define SYS_GPE_MFPL_PE3MFP_TK15 (4ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for TK15*/
-#define SYS_GPE_MFPL_PE3MFP_PWM0_CH3 (6ul << SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for PWM0_CH3*/
-
-//PE4
-#define SYS_GPE_MFPL_PE4MFP_GPIO (0ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO*/
-#define SYS_GPE_MFPL_PE4MFP_I2C1_SCL (3ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for I2C1_SCL*/
-#define SYS_GPE_MFPL_PE4MFP_SC0_PWR (5ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_PWR*/
-#define SYS_GPE_MFPL_PE4MFP_PWM1_BRAKE0 (6ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for PWM1_BRAKE0*/
-#define SYS_GPE_MFPL_PE4MFP_EBI_nCS0 (7ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nCS0*/
-#define SYS_GPE_MFPL_PE4MFP_INT0 (8ul << SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for INT0*/
-
-//PE5
-#define SYS_GPE_MFPL_PE5MFP_GPIO (0ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO*/
-#define SYS_GPE_MFPL_PE5MFP_I2C1_SDA (3ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for I2C1_SDA*/
-#define SYS_GPE_MFPL_PE5MFP_SC0_RST (5ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_RST*/
-#define SYS_GPE_MFPL_PE5MFP_PWM1_BRAKE1 (6ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for PWM1_BRAKE1*/
-#define SYS_GPE_MFPL_PE5MFP_EBI_ALE (7ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_ALE*/
-#define SYS_GPE_MFPL_PE5MFP_INT1 (8ul << SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for INT1*/
-
-//PE6
-#define SYS_GPE_MFPL_PE6MFP_GPIO (0ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO*/
-#define SYS_GPE_MFPL_PE6MFP_T3_EXT (3ul << SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for T3_EXT*/
-
-//PE7
-#define SYS_GPE_MFPL_PE7MFP_GPIO (0ul << SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO*/
-
-//PE8
-#define SYS_GPE_MFPH_PE8MFP_GPIO (0ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO*/
-#define SYS_GPE_MFPH_PE8MFP_UART1_TXD (1ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART1_TXD*/
-#define SYS_GPE_MFPH_PE8MFP_SPI0_MISO1 (2ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SPI0_MISO1*/
-#define SYS_GPE_MFPH_PE8MFP_I2C1_SCL (4ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for I2C1_SCL*/
-#define SYS_GPE_MFPH_PE8MFP_SC0_PWR (5ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SC0_PWR*/
-#define SYS_GPE_MFPH_PE8MFP_CLKO (9ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for CLKO*/
-#define SYS_GPE_MFPH_PE8MFP_PWM0_BRAKE0 (10ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for PWM0_BRAKE0*/
-#define SYS_GPE_MFPH_PE8MFP_T1 (11ul << SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for T1*/
-
-//PE9
-#define SYS_GPE_MFPH_PE9MFP_GPIO (0ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO*/
-#define SYS_GPE_MFPH_PE9MFP_UART1_RXD (1ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART1_RXD*/
-#define SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1 (2ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI0_MOSI1*/
-#define SYS_GPE_MFPH_PE9MFP_I2C1_SDA (4ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for I2C1_SDA*/
-#define SYS_GPE_MFPH_PE9MFP_SC0_RST (5ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SC0_RST*/
-#define SYS_GPE_MFPH_PE9MFP_SPI1_I2SMCLK (9ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI1_I2SMCLK*/
-#define SYS_GPE_MFPH_PE9MFP_PWM1_BRAKE1 (10ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for PWM1_BRAKE1*/
-#define SYS_GPE_MFPH_PE9MFP_T2 (11ul << SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for T2*/
-
-//PE10
-#define SYS_GPE_MFPH_PE10MFP_GPIO (0ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for GPIO*/
-#define SYS_GPE_MFPH_PE10MFP_SPI1_MISO (1ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI1_MISO*/
-#define SYS_GPE_MFPH_PE10MFP_SPI0_MISO0 (2ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI0_MISO0*/
-#define SYS_GPE_MFPH_PE10MFP_UART1_nCTS (3ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART1_nCTS*/
-#define SYS_GPE_MFPH_PE10MFP_I2C0_SMBAL (4ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C0_SMBAL*/
-#define SYS_GPE_MFPH_PE10MFP_SC0_DAT (5ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SC0_DAT*/
-#define SYS_GPE_MFPH_PE10MFP_UART3_TXD (9ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART3_TXD*/
-#define SYS_GPE_MFPH_PE10MFP_I2C1_SCL (11ul << SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2C1_SCL*/
-
-//PE11
-#define SYS_GPE_MFPH_PE11MFP_GPIO (0ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for GPIO*/
-#define SYS_GPE_MFPH_PE11MFP_SPI1_MOSI (1ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI1_MOSI*/
-#define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0 (2ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI0_MOSI0*/
-#define SYS_GPE_MFPH_PE11MFP_UART1_nRTS (3ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART1_nRTS*/
-#define SYS_GPE_MFPH_PE11MFP_I2C0_SMBSUS (4ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C0_SMBSUS*/
-#define SYS_GPE_MFPH_PE11MFP_SC0_CLK (5ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SC0_CLK*/
-#define SYS_GPE_MFPH_PE11MFP_UART3_RXD (9ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART3_RXD*/
-#define SYS_GPE_MFPH_PE11MFP_I2C1_SDA (11ul << SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2C1_SDA*/
-
-//PE12
-#define SYS_GPE_MFPH_PE12MFP_GPIO (0ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for GPIO*/
-#define SYS_GPE_MFPH_PE12MFP_SPI1_SS (1ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI1_SS*/
-#define SYS_GPE_MFPH_PE12MFP_SPI0_SS (2ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI0_SS*/
-#define SYS_GPE_MFPH_PE12MFP_UART1_TXD (3ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for UART1_TXD*/
-#define SYS_GPE_MFPH_PE12MFP_I2C0_SCL (4ul << SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for I2C0_SCL*/
-
-//PE13
-#define SYS_GPE_MFPH_PE13MFP_GPIO (0ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for GPIO*/
-#define SYS_GPE_MFPH_PE13MFP_SPI1_CLK (1ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI1_CLK*/
-#define SYS_GPE_MFPH_PE13MFP_SPI0_CLK (2ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for SPI0_CLK*/
-#define SYS_GPE_MFPH_PE13MFP_UART1_RXD (3ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for UART1_RXD*/
-#define SYS_GPE_MFPH_PE13MFP_I2C0_SDA (4ul << SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for I2C0_SDA*/
-
-//PE14
-#define SYS_GPE_MFPH_PE14MFP_GPIO (0ul << SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for GPIO*/
-
-//PF0
-#define SYS_GPF_MFPL_PF0MFP_GPIO (0ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO*/
-#define SYS_GPF_MFPL_PF0MFP_X32_OUT (1ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for X32_OUT*/
-#define SYS_GPF_MFPL_PF0MFP_INT5 (8ul << SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for INT5*/
-
-//PF1
-#define SYS_GPF_MFPL_PF1MFP_GPIO (0ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO*/
-#define SYS_GPF_MFPL_PF1MFP_X32_IN (1ul << SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for X32_IN*/
-
-//PF2
-#define SYS_GPF_MFPL_PF2MFP_GPIO (0ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO*/
-#define SYS_GPF_MFPL_PF2MFP_TAMPER (1ul << SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for TAMPER*/
-
-//PF3
-#define SYS_GPF_MFPL_PF3MFP_GPIO (0ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO*/
-#define SYS_GPF_MFPL_PF3MFP_XT1_OUT (1ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_OUT*/
-#define SYS_GPF_MFPL_PF3MFP_I2C1_SCL (3ul << SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C1_SCL*/
-
-//PF4
-#define SYS_GPF_MFPL_PF4MFP_GPIO (0ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO*/
-#define SYS_GPF_MFPL_PF4MFP_XT1_IN (1ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for XT1_IN*/
-#define SYS_GPF_MFPL_PF4MFP_I2C1_SDA (3ul << SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for I2C1_SDA*/
-
-//PF5
-#define SYS_GPF_MFPL_PF5MFP_GPIO (0ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO*/
-#define SYS_GPF_MFPL_PF5MFP_ICE_CLK (1ul << SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for ICE_CLK*/
-
-//PF6
-#define SYS_GPF_MFPL_PF6MFP_GPIO (0ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO*/
-#define SYS_GPF_MFPL_PF6MFP_ICE_DAT (1ul << SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for ICE_DAT*/
-
-//PF7
-#define SYS_GPF_MFPL_PF7MFP_GPIO (0ul << SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO*/
-
-
-/*@}*/ /* end of group SYS_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
- @{
-*/
-
-
-/**
- * @brief Clear Brown-out detector interrupt flag
- * @param None
- * @return None
- * @details This macro clear Brown-out detector interrupt flag.
- */
-#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
-
-/**
- * @brief Set Brown-out detector function to normal mode
- * @param None
- * @return None
- * @details This macro set Brown-out detector to normal mode.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
-
-/**
- * @brief Disable Brown-out detector function
- * @param None
- * @return None
- * @details This macro disable Brown-out detector function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
-
-/**
- * @brief Enable Brown-out detector function
- * @param None
- * @return None
- * @details This macro enable Brown-out detector function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
-
-/**
- * @brief Get Brown-out detector interrupt flag
- * @param None
- * @retval 0 Brown-out detect interrupt flag is not set.
- * @retval >=1 Brown-out detect interrupt flag is set.
- * @details This macro get Brown-out detector interrupt flag.
- */
-#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
-
-/**
- * @brief Get Brown-out detector status
- * @param None
- * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
- * @retval >=1 System voltage is lower than BOD threshold voltage setting.
- * @details This macro get Brown-out detector output status.
- * If the BOD function is disabled, this function always return 0.
- */
-#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
-
-/**
- * @brief Enable Brown-out detector interrupt function
- * @param None
- * @return None
- * @details This macro enable Brown-out detector interrupt function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
-
-/**
- * @brief Enable Brown-out detector reset function
- * @param None
- * @return None
- * @details This macro enable Brown-out detect reset function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
-
-/**
- * @brief Set Brown-out detector function low power mode
- * @param None
- * @return None
- * @details This macro set Brown-out detector to low power mode.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
-
-/**
- * @brief Set Brown-out detector voltage level
- * @param[in] u32Level is Brown-out voltage level. Including :
- * - \ref SYS_BODCTL_BODVL_4_5V
- * - \ref SYS_BODCTL_BODVL_3_7V
- * - \ref SYS_BODCTL_BODVL_2_7V
- * - \ref SYS_BODCTL_BODVL_2_2V
- * @return None
- * @details This macro set Brown-out detector voltage level.
- * The write-protection function should be disabled before using this macro.
- */
-#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
-
-/**
- * @brief Get reset source is from Brown-out detector reset
- * @param None
- * @retval 0 Previous reset source is not from Brown-out detector reset
- * @retval >=1 Previous reset source is from Brown-out detector reset
- * @details This macro get previous reset source is from Brown-out detect reset or not.
- */
-#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
-
-/**
- * @brief Get reset source is from CPU reset
- * @param None
- * @retval 0 Previous reset source is not from CPU reset
- * @retval >=1 Previous reset source is from CPU reset
- * @details This macro get previous reset source is from CPU reset.
- */
-#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
-
-/**
- * @brief Get reset source is from LVR Reset
- * @param None
- * @retval 0 Previous reset source is not from Low-Voltage-Reset
- * @retval >=1 Previous reset source is from Low-Voltage-Reset
- * @details This macro get previous reset source is from Low-Voltage-Reset.
- */
-#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
-
-/**
- * @brief Get reset source is from Power-on Reset
- * @param None
- * @retval 0 Previous reset source is not from Power-on Reset
- * @retval >=1 Previous reset source is from Power-on Reset
- * @details This macro get previous reset source is from Power-on Reset.
- */
-#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
-
-/**
- * @brief Get reset source is from reset pin reset
- * @param None
- * @retval 0 Previous reset source is not from reset pin reset
- * @retval >=1 Previous reset source is from reset pin reset
- * @details This macro get previous reset source is from reset pin reset.
- */
-#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
-
-/**
- * @brief Get reset source is from system reset
- * @param None
- * @retval 0 Previous reset source is not from system reset
- * @retval >=1 Previous reset source is from system reset
- * @details This macro get previous reset source is from system reset.
- */
-#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
-
-/**
- * @brief Get reset source is from window watch dog reset
- * @param None
- * @retval 0 Previous reset source is not from window watch dog reset
- * @retval >=1 Previous reset source is from window watch dog reset
- * @details This macro get previous reset source is from window watch dog reset.
- */
-#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
-
-/**
- * @brief Disable Low-Voltage-Reset function
- * @param None
- * @return None
- * @details This macro disable Low-Voltage-Reset function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
-
-/**
- * @brief Enable Low-Voltage-Reset function
- * @param None
- * @return None
- * @details This macro enable Low-Voltage-Reset function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
-
-/**
- * @brief Disable Power-on Reset function
- * @param None
- * @return None
- * @details This macro disable Power-on Reset function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
-
-/**
- * @brief Enable Power-on Reset function
- * @param None
- * @return None
- * @details This macro enable Power-on Reset function.
- * The register write-protection function should be disabled before using this macro.
- */
-#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
-
-/**
- * @brief Clear reset source flag
- * @param[in] u32RstSrc is reset source. Including :
- * - \ref SYS_RSTSTS_PORF_Msk
- * - \ref SYS_RSTSTS_PINRF_Msk
- * - \ref SYS_RSTSTS_WDTRF_Msk
- * - \ref SYS_RSTSTS_LVRF_Msk
- * - \ref SYS_RSTSTS_BODRF_Msk
- * - \ref SYS_RSTSTS_SYSRF_Msk
- * - \ref SYS_RSTSTS_CPURF_Msk
- * - \ref SYS_RSTSTS_CPULKRF_Msk
- * @return None
- * @details This macro clear reset source flag.
- */
-#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* static inline functions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-
-/**
- * @brief Disable register write-protection function
- * @param None
- * @return None
- * @details This function disable register write-protection function.
- * To unlock the protected register to allow write access.
- */
-__STATIC_INLINE void SYS_UnlockReg(void)
-{
- do
- {
- SYS->REGLCTL = 0x59;
- SYS->REGLCTL = 0x16;
- SYS->REGLCTL = 0x88;
- }
- while(SYS->REGLCTL == 0);
-}
-
-/**
- * @brief Enable register write-protection function
- * @param None
- * @return None
- * @details This function is used to enable register write-protection function.
- * To lock the protected register to forbid write access.
- */
-__STATIC_INLINE void SYS_LockReg(void)
-{
- SYS->REGLCTL = 0;
-}
-
-
-void SYS_ClearResetSrc(uint32_t u32Src);
-uint32_t SYS_GetBODStatus(void);
-uint32_t SYS_GetResetSrc(void);
-uint32_t SYS_IsRegLocked(void);
-uint32_t SYS_ReadPDID(void);
-void SYS_ResetChip(void);
-void SYS_ResetCPU(void);
-void SYS_ResetModule(uint32_t u32ModuleIndex);
-void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
-void SYS_DisableBOD(void);
-
-
-/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group SYS_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SYS_H__
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_timer.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,292 +0,0 @@
-/**************************************************************************//**
- * @file timer.c
- * @version V3.00
- * $Revision: 6 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series Timer driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup TIMER_Driver TIMER Driver
- @{
-*/
-
-/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
- @{
-*/
-
-/**
- * @brief Open Timer with Operate Mode and Frequency
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- * @param[in] u32Mode Operation mode. Possible options are
- * - \ref TIMER_ONESHOT_MODE
- * - \ref TIMER_PERIODIC_MODE
- * - \ref TIMER_TOGGLE_MODE
- * - \ref TIMER_CONTINUOUS_MODE
- * @param[in] u32Freq Target working frequency
- *
- * @return Real timer working frequency
- *
- * @details This API is used to configure timer to operate in specified mode and frequency.
- * If timer cannot work in target frequency, a closest frequency will be chose and returned.
- * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
- * \ref TIMER_Start macro or program registers directly.
- */
-uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
-{
- uint32_t u32Clk = TIMER_GetModuleClock(timer);
- uint32_t u32Cmpr = 0, u32Prescale = 0;
-
- // Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0.
- if(u32Freq > (u32Clk / 2))
- {
- u32Cmpr = 2;
- }
- else
- {
- if(u32Clk > 64000000)
- {
- u32Prescale = 7; // real prescaler value is 8
- u32Clk >>= 3;
- }
- else if(u32Clk > 32000000)
- {
- u32Prescale = 3; // real prescaler value is 4
- u32Clk >>= 2;
- }
- else if(u32Clk > 16000000)
- {
- u32Prescale = 1; // real prescaler value is 2
- u32Clk >>= 1;
- }
-
- u32Cmpr = u32Clk / u32Freq;
- }
-
- timer->CTL = u32Mode | u32Prescale;
- timer->CMP = u32Cmpr;
-
- return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
-}
-
-/**
- * @brief Stop Timer Counting
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This API stops timer counting and disable all timer interrupt function.
- */
-void TIMER_Close(TIMER_T *timer)
-{
- timer->CTL = 0;
- timer->EXTCTL = 0;
-}
-
-/**
- * @brief Create a specify Delay Time
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
- *
- * @return None
- *
- * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
- * @note This API overwrites the register setting of the timer used to count the delay time.
- * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
- */
-void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
-{
- uint32_t u32Clk = TIMER_GetModuleClock(timer);
- uint32_t u32Prescale = 0, delay = (SystemCoreClock / u32Clk) + 1;
- uint32_t u32Cmpr, u32NsecPerTick;
-
- // Clear current timer configuration/
- timer->CTL = 0;
- timer->EXTCTL = 0;
-
- if(u32Clk <= 1000000) // min delay is 1000 us if timer clock source is <= 1 MHz
- {
- if(u32Usec < 1000)
- u32Usec = 1000;
- if(u32Usec > 1000000)
- u32Usec = 1000000;
- }
- else
- {
- if(u32Usec < 100)
- u32Usec = 100;
- if(u32Usec > 1000000)
- u32Usec = 1000000;
- }
-
- if(u32Clk <= 1000000)
- {
- u32Prescale = 0;
- u32NsecPerTick = 1000000000 / u32Clk;
- u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
- }
- else
- {
- if(u32Clk > 64000000)
- {
- u32Prescale = 7; // real prescaler value is 8
- u32Clk >>= 3;
- }
- else if(u32Clk > 32000000)
- {
- u32Prescale = 3; // real prescaler value is 4
- u32Clk >>= 2;
- }
- else if(u32Clk > 16000000)
- {
- u32Prescale = 1; // real prescaler value is 2
- u32Clk >>= 1;
- }
-
- if(u32Usec < 250)
- {
- u32Cmpr = (u32Usec * u32Clk) / 1000000;
- }
- else
- {
- u32NsecPerTick = 1000000000 / u32Clk;
- u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
- }
- }
-
- timer->CMP = u32Cmpr;
- timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
-
- // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
- // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
- for(; delay > 0; delay--)
- {
- __NOP();
- }
-
- while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
-}
-
-/**
- * @brief Enable Timer Capture Function
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- * @param[in] u32CapMode Timer capture mode. Could be
- * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
- * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
- * @param[in] u32Edge Timer capture trigger edge. Possible values are
- * - \ref TIMER_CAPTURE_FALLING_EDGE
- * - \ref TIMER_CAPTURE_RISING_EDGE
- * - \ref TIMER_CAPTURE_FALLING_AND_RISING_EDGE
- *
- * @return None
- *
- * @details This API is used to enable timer capture function with specify capture trigger edge \n
- * to get current counter value or reset counter value to 0.
- * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
- */
-void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
-{
-
- timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
- u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
-}
-
-/**
- * @brief Disable Timer Capture Function
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This API is used to disable the timer capture function.
- */
-void TIMER_DisableCapture(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
-}
-
-/**
- * @brief Enable Timer Counter Function
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- * @param[in] u32Edge Detection edge of counter pin. Could be ether
- * - \ref TIMER_COUNTER_FALLING_EDGE, or
- * - \ref TIMER_COUNTER_RISING_EDGE
- *
- * @return None
- *
- * @details This function is used to enable the timer counter function with specify detection edge.
- * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
- * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
- */
-void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
-{
- timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
- timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
-}
-
-/**
- * @brief Disable Timer Counter Function
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This API is used to disable the timer event counter function.
- */
-void TIMER_DisableEventCounter(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
-}
-
-/**
- * @brief Get Timer Clock Frequency
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return Timer clock frequency
- *
- * @details This API is used to get the timer clock frequency.
- * @note This API cannot return correct clock rate if timer source is from external clock input.
- */
-uint32_t TIMER_GetModuleClock(TIMER_T *timer)
-{
- uint32_t u32Src;
- const uint32_t au32Clk[] = {__HXT, __LXT, 0, 0, 0, __LIRC, 0, __HIRC};
-
- if(timer == TIMER0)
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
- else if(timer == TIMER1)
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
- else if(timer == TIMER2)
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
- else // Timer 3
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
-
- if(u32Src == 2)
- {
- return (SystemCoreClock);
- }
-
- return (au32Clk[u32Src]);
-}
-
-/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group TIMER_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_timer.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,415 +0,0 @@
-/**************************************************************************//**
- * @file timer.h
- * @version V3.00
- * $Revision: 10 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series Timer driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __TIMER_H__
-#define __TIMER_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup TIMER_Driver TIMER Driver
- @{
-*/
-
-/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode */
-#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode */
-#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode */
-#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode */
-#define TIMER_TOUT_PIN_FROM_TX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx pin */
-#define TIMER_TOUT_PIN_FROM_TX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx_EXT pin */
-#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value */
-#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter */
-#define TIMER_CAPTURE_FALLING_EDGE (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger timer capture */
-#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger timer capture */
-#define TIMER_CAPTURE_FALLING_AND_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger timer capture */
-#define TIMER_COUNTER_FALLING_EDGE (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection */
-#define TIMER_COUNTER_RISING_EDGE (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection */
-
-/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
- @{
-*/
-
-/**
- * @brief Set Timer Compared Value
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
- *
- * @return None
- *
- * @details This macro is used to set timer compared value to adjust timer time-out interval.
- * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
- * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
- * But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
- */
-#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
-
-/**
- * @brief Set Timer Prescale Value
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
- *
- * @return None
- *
- * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
- * before it is fed into timer.
- */
-#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
-
-/**
- * @brief Check specify Timer Status
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @retval 0 Timer 24-bit up counter is inactive
- * @retval 1 Timer 24-bit up counter is active
- *
- * @details This macro is used to check if specify Timer counter is inactive or active.
- */
-#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
-
-/**
- * @brief Select Toggle-output Pin
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- * @param[in] u32ToutSel Toggle-output pin selection, valid values are:
- * - \ref TIMER_TOUT_PIN_FROM_TX
- * - \ref TIMER_TOUT_PIN_FROM_TX_EXT
- *
- * @return None
- *
- * @details This macro is used to select timer toggle-output pin is output on Tx or Tx_EXT pin.
- */
-#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
-
-/**
- * @brief Start Timer Counting
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to start Timer counting.
- */
-static __INLINE void TIMER_Start(TIMER_T *timer)
-{
- timer->CTL |= TIMER_CTL_CNTEN_Msk;
-}
-
-/**
- * @brief Stop Timer Counting
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to stop/suspend Timer counting.
- */
-static __INLINE void TIMER_Stop(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
-}
-
-/**
- * @brief Enable Timer Interrupt Wake-up Function
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
- * counter event interrupt or capture trigger interrupt.
- * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
- */
-static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
-{
- timer->CTL |= TIMER_CTL_WKEN_Msk;
-}
-
-/**
- * @brief Disable Timer Wake-up Function
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to disable the timer interrupt wake-up function.
- */
-static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_WKEN_Msk;
-}
-
-/**
- * @brief Enable Capture Pin De-bounce
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to enable the detect de-bounce function of capture pin.
- */
-static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
-{
- timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
-}
-
-/**
- * @brief Disable Capture Pin De-bounce
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to disable the detect de-bounce function of capture pin.
- */
-static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
-}
-
-/**
- * @brief Enable Counter Pin De-bounce
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to enable the detect de-bounce function of counter pin.
- */
-static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
-{
- timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
-}
-
-/**
- * @brief Disable Counter Pin De-bounce
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to disable the detect de-bounce function of counter pin.
- */
-static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
-}
-
-/**
- * @brief Enable Timer Time-out Interrupt
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to enable the timer time-out interrupt function.
- */
-static __INLINE void TIMER_EnableInt(TIMER_T *timer)
-{
- timer->CTL |= TIMER_CTL_INTEN_Msk;
-}
-
-/**
- * @brief Disable Timer Time-out Interrupt
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to disable the timer time-out interrupt function.
- */
-static __INLINE void TIMER_DisableInt(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_INTEN_Msk;
-}
-
-/**
- * @brief Enable Capture Trigger Interrupt
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to enable the timer capture trigger interrupt function.
- */
-static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
-{
- timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
-}
-
-/**
- * @brief Disable Capture Trigger Interrupt
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function is used to disable the timer capture trigger interrupt function.
- */
-static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
-}
-
-/**
- * @brief Get Timer Time-out Interrupt Flag
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @retval 0 Timer time-out interrupt did not occur
- * @retval 1 Timer time-out interrupt occurred
- *
- * @details This function indicates timer time-out interrupt occurred or not.
- */
-static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
-{
- return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0);
-}
-
-/**
- * @brief Clear Timer Time-out Interrupt Flag
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function clears timer time-out interrupt flag to 0.
- */
-static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
-{
- timer->INTSTS = (timer->INTSTS & ~TIMER_INTSTS_TWKF_Msk) | TIMER_INTSTS_TIF_Msk;
-}
-
-/**
- * @brief Get Timer Capture Interrupt Flag
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @retval 0 Timer capture interrupt did not occur
- * @retval 1 Timer capture interrupt occurred
- *
- * @details This function indicates timer capture trigger interrupt occurred or not.
- */
-static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
-{
- return timer->EINTSTS;
-}
-
-/**
- * @brief Clear Timer Capture Interrupt Flag
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function clears timer capture trigger interrupt flag to 0.
- */
-static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
-{
- timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
-}
-
-/**
- * @brief Get Timer Wake-up Flag
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @retval 0 Timer does not cause CPU wake-up
- * @retval 1 Timer interrupt event cause CPU wake-up
- *
- * @details This function indicates timer interrupt event has waked up system or not.
- */
-static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
-{
- return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
-}
-
-/**
- * @brief Clear Timer Wake-up Flag
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return None
- *
- * @details This function clears the timer wake-up system flag to 0.
- */
-static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
-{
- timer->INTSTS = (timer->INTSTS & ~TIMER_INTSTS_TIF_Msk) | TIMER_INTSTS_TWKF_Msk;
-}
-
-/**
- * @brief Get Capture value
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return 24-bit Capture Value
- *
- * @details This function reports the current 24-bit timer capture value.
- */
-static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
-{
- return timer->CAP;
-}
-
-/**
- * @brief Get Counter value
- *
- * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
- *
- * @return 24-bit Counter Value
- *
- * @details This function reports the current 24-bit timer counter value.
- */
-static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
-{
- return timer->CNT;
-}
-
-uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
-void TIMER_Close(TIMER_T *timer);
-void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
-void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
-void TIMER_DisableCapture(TIMER_T *timer);
-void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
-void TIMER_DisableEventCounter(TIMER_T *timer);
-uint32_t TIMER_GetModuleClock(TIMER_T *timer);
-
-/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group TIMER_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__TIMER_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_tk.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,265 +0,0 @@
-/**************************************************************************//**
- * @file tk.c
- * @version V1.00
- * $Revision: 6 $
- * $Date: 15/08/24 4:54p $
- * @brief M451 series TK driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *
-*****************************************************************************/
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup TK_Driver TK Driver
- @{
-*/
-
-
-/** @addtogroup TK_EXPORTED_FUNCTIONS TK Exported Functions
- @{
-*/
-
-
-/**
- * @brief Enable touch key function
- * @param None
- * @return None
- * @note This function will enable touch key function and initial idle and polarity state as GND first for all scan keys
- * \hideinitializer
- */
-
-void TK_Open(void)
-{
- TK->CTL |= TK_CTL_TKEN_Msk;
- //set idle and polarity state as GND
- TK->IDLESEL = 0;
- TK->POLSEL = 0;
- TK->POLCTL &= ~(TK_POLCTL_IDLS16_Msk | TK_POLCTL_POLSEL16_Msk);
-}
-
-/**
- * @brief Disable touch key function
- * @param None
- * @return None
- * \hideinitializer
- */
-void TK_Close(void)
-{
- TK->CTL &= ~TK_CTL_TKEN_Msk;
-}
-
-/**
- * @brief Set touch key scan mode
- * @param[in] u32Mode Single ,periodic or all key scan mode
- * - \ref TK_SCAN_MODE_SINGLE
- * - \ref TK_SCAN_MODE_PERIODIC
- * - \ref TK_SCAN_MODE_ALL_KEY
- * - \ref TK_SCAN_MODE_PERIODIC_ALL_KEY
- * @return None
- * @details This function is used to set touch key scan mode.
- * @note If touch key controller sets as periodic mode, touch key will be trigger scan by Timer0. So Timer0 must be enabled and operated in periodic mode.
- * If touch key controller sets as single scan mode, touch key can be trigger scan by calling TK_START_SCAN().
- * \hideinitializer
- */
-void TK_SetScanMode(uint32_t u32Mode)
-{
- TK->CTL &= ~TK_CTL_TMRTRGEN_Msk;
- TK->REFCTL &= ~TK_REFCTL_SCANALL_Msk;
- if(u32Mode == TK_SCAN_MODE_PERIODIC)
- {
- TK->CTL |= u32Mode;
- }
- else if(u32Mode == TK_SCAN_MODE_ALL_KEY)
- {
- TK->REFCTL |= u32Mode;
- }
- else if(u32Mode == TK_SCAN_MODE_PERIODIC_ALL_KEY)
- {
- TK->CTL |= TK_CTL_TMRTRGEN_Msk;
- TK->REFCTL |= TK_REFCTL_SCANALL_Msk;
- }
-}
-
-/**
- * @brief Configure touch key scan sensitivity
- * @param[in] u32PulseWidth Sensing pulse width
- * - \ref TK_SENSE_PULSE_1
- * - \ref TK_SENSE_PULSE_2
- * - \ref TK_SENSE_PULSE_4
- * - \ref TK_SENSE_PULSE_8
- * @param[in] u32SenseCnt Sensing count
- * - \ref TK_SENSE_CNT_128
- * - \ref TK_SENSE_CNT_255
- * - \ref TK_SENSE_CNT_511
- * - \ref TK_SENSE_CNT_1023
- * @param[in] u32AVCCHSel voltage selection
- * - \ref TK_AVCCH_1_DIV_16
- * - \ref TK_AVCCH_1_DIV_8
- * - \ref TK_AVCCH_3_DIV_16
- * - \ref TK_AVCCH_1_DIV_4
- * - \ref TK_AVCCH_5_DIV_16
- * - \ref TK_AVCCH_3_DIV_8
- * - \ref TK_AVCCH_7_DIV_16
- * - \ref TK_AVCCH_1_DIV_2
- * @return None
- * @details This function is used to configure touch key scan sensitivity.
- * \hideinitializer
- */
-void TK_ConfigSensitivity(uint32_t u32PulseWidth, uint32_t u32SenseCnt, uint32_t u32AVCCHSel)
-{
- TK->REFCTL = (TK->REFCTL & ~(TK_REFCTL_SENPTCTL_Msk | TK_REFCTL_SENTCTL_Msk)) | (u32PulseWidth | u32SenseCnt);
- TK->CTL = (TK->CTL & ~TK_CTL_AVCCHSEL_Msk) | u32AVCCHSel;
-}
-
-/**
- * @brief Set touch key capacitor bank polarity
- * @param[in] u32CapBankPolSel capacitor bank polarity selection
- * - \ref TK_CAP_BANK_POL_SEL_GND
- * - \ref TK_CAP_BANK_POL_SEL_AVCCH
- * - \ref TK_CAP_BANK_POL_SEL_VDD
- * @return None
- * @details This function is used to set touch key capacitor bank polarity.
- * \hideinitializer
- */
-void TK_SetCapBankPol(uint32_t u32CapBankPolSel)
-{
- TK->POLCTL = (TK->POLCTL & ~TK_POLCTL_CBPOLSEL_Msk) | u32CapBankPolSel;
-}
-
-/**
- * @brief Configure touch key polarity
- * @param[in] u32Mask Combination of touch keys which need to be configured
- * @param[in] u32TKnPolSel touch key polarity selection
- * - \ref TK_TKn_POL_SEL_GND
- * - \ref TK_TKn_POL_SEL_AVCCH
- * - \ref TK_TKn_POL_SEL_VDD
- * @return None
- * @details This function is used to configure touch key polarity.
- * \hideinitializer
- */
-void TK_SetTkPol(uint32_t u32Mask, uint32_t u32PolSel)
-{
- uint32_t i;
-
- if((1ul << 16) & u32Mask)
- TK->POLCTL = (TK->POLCTL & ~TK_POLCTL_POLSEL16_Msk) | (u32PolSel << TK_POLCTL_POLSEL16_Pos);
-
- for(i = 0 ; i < 16 ; i++)
- {
- if((1ul << i) & u32Mask)
- TK->POLSEL = (TK->POLSEL & ~(TK_POLSEL_POLSELn_Msk << (i*2))) | (u32PolSel << (i*2));
- }
-}
-
-/**
- * @brief Enable the polarity of specified touch key(s)
- * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key
- * Bit 0 represents touch key 0, bit 1 represents touch key 1...
- * @return None
- * @details This function is used to enable the polarity of specified touch key(s).
- * \hideinitializer
- */
-void TK_EnableTkPolarity(uint32_t u32Mask)
-{
- TK->POLCTL |= (u32Mask << TK_POLCTL_POLEN0_Pos);
-}
-
-/**
- * @brief Disable the polarity of specified touch key(s)
- * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key
- * Bit 0 represents touch key 0, bit 1 represents touch key 1...
- * @return None
- * @details This function is used to disable the polarity of specified touch key(s).
- * \hideinitializer
- */
-void TK_DisableTkPolarity(uint32_t u32Mask)
-{
- TK->POLCTL &= ~(u32Mask << TK_POLCTL_POLEN0_Pos);
-}
-
-/**
- * @brief Set complement capacitor bank data of specified touch key
- * @param[in] u32TKNum Touch key number. The valid value is 0~16.
- * @param[in] u32CapData Complement capacitor bank data. The valid value is 0~0xFF.
- * @return None
- * @details This function is used to set complement capacitor bank data of specified touch key.
- * \hideinitializer
- */
-void TK_SetCompCapBankData(uint32_t u32TKNum, uint32_t u32CapData)
-{
- *(__IO uint32_t *)(&(TK->CCBDAT0) + (u32TKNum >> 2)) &= ~(TK_CCBDAT0_CCBDAT0_Msk << (u32TKNum % 4 * 8));
- *(__IO uint32_t *)(&(TK->CCBDAT0) + (u32TKNum >> 2)) |= (u32CapData << (u32TKNum % 4 * 8));
-}
-
-/**
- * @brief Set complement capacitor bank data of reference touch key
- * @param[in] u32CapData Complement capacitor bank data. The valid value is 0~0xFF.
- * @return None
- * @details This function is used to set complement capacitor bank data of reference touch key.
- * \hideinitializer
- */
-void TK_SetRefKeyCapBankData(uint32_t u32CapData)
-{
- TK->CCBDAT4 = (TK->CCBDAT4 & ~TK_CCBDAT4_REFCBDAT_Msk) | (u32CapData << TK_CCBDAT4_REFCBDAT_Pos);
-}
-
-/**
- * @brief Set high and low threshold of specified touch key for threshold control interrupt
- * @param[in] u32TKNum Touch key number. The valid value is 0~16.
- * @param[in] u32HighLevel High level for touch key threshold control. The valid value is 0~0xFF.
- * @param[in] u32LowLevel Low level for touch key threshold control. The valid value is 0~0xFF.
- * @return None
- * @details This function is used to set high and low threshold of specified touch key for threshold control interrupt.
- * \hideinitializer
- */
-void TK_SetScanThreshold(uint32_t u32TKNum, uint32_t u32HighLevel, uint32_t u32LowLevel)
-{
- *(__IO uint32_t *)(&(TK->TH0_1) + (u32TKNum >> 1)) &= ~((TK_TH0_1_HTH0_Msk | TK_TH0_1_LTH0_Msk) << (u32TKNum % 2 * 16));
- *(__IO uint32_t *)(&(TK->TH0_1) + (u32TKNum >> 1)) |= ((u32HighLevel << TK_TH0_1_HTH0_Pos) | (u32LowLevel << TK_TH0_1_LTH0_Pos)) << (u32TKNum % 2 * 16);
-}
-
-/**
- * @brief Enable touch key scan interrupt
- * @param[in] u32Msk Interrupt type selection.
- * - \ref TK_INT_EN_SCAN_COMPLETE
- * - \ref TK_INT_EN_SCAN_COMPLETE_EDGE_TH
- * - \ref TK_INT_EN_SCAN_COMPLETE_LEVEL_TH
- * @return None
- * @details This function is used to enable touch key scan interrupt.
- * @note It need disable the enabled interrupt type first by TK_DisableInt() before to change enabled interrupt type.
- * \hideinitializer
- */
-void TK_EnableInt(uint32_t u32Msk)
-{
- TK->INTEN |= u32Msk;
-}
-
-/**
- * @brief Disable touch key scan interrupt
- * @param[in] u32Msk Interrupt type selection.
- * - \ref TK_INT_EN_SCAN_COMPLETE
- * - \ref TK_INT_EN_SCAN_COMPLETE_EDGE_TH
- * - \ref TK_INT_EN_SCAN_COMPLETE_LEVEL_TH
- * @return None
- * @details This function is used to disable touch key scan interrupt.
-* @note It need disable the enabled interrupt type first by TK_DisableInt() before to change enabled interrupt type.
- * \hideinitializer
- */
-void TK_DisableInt(uint32_t u32Msk)
-{
- TK->INTEN &= ~u32Msk;
-}
-
-
-/*@}*/ /* end of group TK_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group TK_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_tk.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,302 +0,0 @@
-/**************************************************************************//**
- * @file tk.h
- * @version V1.00
- * $Revision: 6 $
- * $Date: 15/08/24 4:52p $
- * @brief M451 Series TK Driver Header File
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __TK_H__
-#define __TK_H__
-
-#include "M451Series.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup TK_Driver TK Driver
- @{
-*/
-
-/** @addtogroup TK_EXPORTED_CONSTANTS TK Exported Constants
- @{
-*/
-
-#define TK_SCAN_MODE_SINGLE (0UL) /*!< Touch key single scan mode */
-#define TK_SCAN_MODE_PERIODIC (TK_CTL_TMRTRGEN_Msk) /*!< Touch key periodic scan mode */
-#define TK_SCAN_MODE_ALL_KEY (TK_REFCTL_SCANALL_Msk) /*!< Touch key all keys scan mode */
-#define TK_SCAN_MODE_PERIODIC_ALL_KEY (TK_CTL_TMRTRGEN_Msk | TK_REFCTL_SCANALL_Msk) /*!< Touch key periodic with all keys scan mode */
-
-#define TK_SENSE_PULSE_1 (0UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 1us */
-#define TK_SENSE_PULSE_2 (1UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 2us */
-#define TK_SENSE_PULSE_4 (2UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 4us */
-#define TK_SENSE_PULSE_8 (3UL << TK_REFCTL_SENPTCTL_Pos) /*!< Touch key sensing pulse width is 8us */
-
-#define TK_SENSE_CNT_128 (0UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 128 */
-#define TK_SENSE_CNT_255 (1UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 255 */
-#define TK_SENSE_CNT_511 (2UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 511 */
-#define TK_SENSE_CNT_1023 (3UL << TK_REFCTL_SENTCTL_Pos) /*!< Touch key sensing count is 1023 */
-
-#define TK_AVCCH_1_DIV_16 (0UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/16 VDD */
-#define TK_AVCCH_1_DIV_8 (1UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/8 VDD */
-#define TK_AVCCH_3_DIV_16 (2UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 3/16 VDD */
-#define TK_AVCCH_1_DIV_4 (3UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/4 VDD */
-#define TK_AVCCH_5_DIV_16 (4UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 5/16 VDD */
-#define TK_AVCCH_3_DIV_8 (5UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 3/8 VDD */
-#define TK_AVCCH_7_DIV_16 (6UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 7/16 VDD */
-#define TK_AVCCH_1_DIV_2 (7UL << TK_CTL_AVCCHSEL_Pos) /*!< Touch key AVCCH voltage is 1/2 VDD */
-
-#define TK_CAP_BANK_POL_SEL_GND (0UL << TK_POLCTL_CBPOLSEL_Pos) /*!< Touch key capacitor bank polarity is GND */
-#define TK_CAP_BANK_POL_SEL_AVCCH (1UL << TK_POLCTL_CBPOLSEL_Pos) /*!< Touch key capacitor bank polarity is AVCCH */
-#define TK_CAP_BANK_POL_SEL_VDD (2UL << TK_POLCTL_CBPOLSEL_Pos) /*!< Touch key capacitor bank polarity is VDD */
-
-#define TK_TKn_POL_SEL_GND (0UL) /*!< Touch key polarity is GND */
-#define TK_TKn_POL_SEL_AVCCH (1UL) /*!< Touch key polarity is AVCCH */
-#define TK_TKn_POL_SEL_VDD (2UL) /*!< Touch key polarity is VDD */
-
-#define TK_INT_EN_SCAN_COMPLETE (TK_INTEN_SCINTEN_Msk) /*!< Touch key enable scan complete interrupt */
-#define TK_INT_EN_SCAN_COMPLETE_EDGE_TH (TK_INTEN_SCTHIEN_Msk) /*!< Touch key enable scan complete with threshold interrupt of edge trigger mode */
-#define TK_INT_EN_SCAN_COMPLETE_LEVEL_TH (TK_INTEN_THIMOD_Msk | TK_INTEN_SCTHIEN_Msk) /*!< Touch key enable scan complete with threshold interrupt of level trigger mode */
-
-#define TK_INT_SCAN_COMPLETE (TK_STATUS_SCIF_Msk) /*!< Touch key scan complete interrupt */
-#define TK_INT_SCAN_COMPLETE_TH_ALL (0x1FFFF02UL) /*!< Touch key scan complete or all touch keys threshold control interrupt */
-#define TK_INT_SCAN_TH_ALL (0x1FFFF00UL) /*!< ALL Touch key threshold control interrupt */
-#define TK_INT_SCAN_TH_TK0 (TK_STATUS_TKIF0_Msk) /*!< Touch key 0 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK1 (TK_STATUS_TKIF1_Msk) /*!< Touch key 1 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK2 (TK_STATUS_TKIF2_Msk) /*!< Touch key 2 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK3 (TK_STATUS_TKIF3_Msk) /*!< Touch key 3 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK4 (TK_STATUS_TKIF4_Msk) /*!< Touch key 4 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK5 (TK_STATUS_TKIF5_Msk) /*!< Touch key 5 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK6 (TK_STATUS_TKIF6_Msk) /*!< Touch key 6 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK7 (TK_STATUS_TKIF7_Msk) /*!< Touch key 7 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK8 (TK_STATUS_TKIF8_Msk) /*!< Touch key 8 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK9 (TK_STATUS_TKIF9_Msk) /*!< Touch key 9 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK10 (TK_STATUS_TKIF10_Msk) /*!< Touch key 10 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK11 (TK_STATUS_TKIF11_Msk) /*!< Touch key 11 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK12 (TK_STATUS_TKIF12_Msk) /*!< Touch key 12 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK13 (TK_STATUS_TKIF13_Msk) /*!< Touch key 13 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK14 (TK_STATUS_TKIF14_Msk) /*!< Touch key 14 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK15 (TK_STATUS_TKIF15_Msk) /*!< Touch key 15 threshold control interrupt */
-#define TK_INT_SCAN_TH_TK16 (TK_STATUS_TKIF16_Msk) /*!< Touch key 16 threshold control interrupt */
-
-
-/*@}*/ /* end of group TK_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup TK_EXPORTED_FUNCTIONS TK Exported Functions
- @{
-*/
-
-/**
- * @brief Enable scan key(s)
- * @param[in] u32Mask Combination of enabled scan keys. Each bit corresponds to a touch key.
- * Bit 0 represents touch key 0, bit 1 represents touch key 1...
- * @return None
- * @note Touch key 16 is the default reference key, so touch key 16 is enabled.
- * \hideinitializer
- */
-#define TK_ENABLE_SCAN_KEY(u32Mask) (TK->CTL |= (u32Mask))
-
-/**
- * @brief Disable scan key(s)
- * @param[in] u32Mask Combination of disabled scan keys. Each bit corresponds to a touch key.
- * Bit 0 represents touch key 0, bit 1 represents touch key 1...
- * @return None
- * \hideinitializer
- */
-#define TK_DISABLE_SCAN_KEY(u32Mask) (TK->CTL &= ~(u32Mask))
-
-/**
- * @brief Enable reference key(s)
- * @param[in] u32Mask Combination of enabled reference keys. Each bit corresponds to a touch key.
- * Bit 0 represents touch key 0, bit 1 represents touch key 1...
- * @return None
- * @note Touch key 16 is the default reference key, so touch key 16 is enabled.
- * \hideinitializer
- */
-#define TK_ENABLE_REF_KEY(u32Mask) (TK->REFCTL |= (u32Mask))
-
-/**
- * @brief Disable reference key(s)
- * @param[in] u32Mask Combination of disabled reference keys. Each bit corresponds to a touch key.
- * Bit 0 represents touch key 0, bit 1 represents touch key 1...
- * @return None
- * @note It must enable a reference key and touch key 16 is the default reference key.
- * If no any one touch key as reference key except touch key 16, then reference Touch key 16 can't be disable.
- * \hideinitializer
- */
-#define TK_DISABLE_REF_KEY(u32Mask) (TK->REFCTL &= ~(u32Mask))
-
-/**
- * @brief Initiate enabled key(s) scan immediately.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define TK_START_SCAN() (TK->CTL |= TK_CTL_SCAN_Msk)
-
-/**
- * @brief Set touch key Sensing pulse width.
- * @param[in] u32PulseWidth Sensing pulse width.
- * - \ref TK_SENSE_PULSE_1
- * - \ref TK_SENSE_PULSE_2
- * - \ref TK_SENSE_PULSE_4
- * - \ref TK_SENSE_PULSE_8
- * @return None
- * \hideinitializer
- */
-#define TK_SET_PULSE_WIDTH(u32PulseWidth) (TK->REFCTL = (TK->REFCTL & ~TK_REFCTL_SENPTCTL_Msk) | (u32PulseWidth))
-
-/**
- * @brief Set touch key Sensing count.
- * @param[in] u32SenseCnt Sensing count.
- * - \ref TK_SENSE_CNT_128
- * - \ref TK_SENSE_CNT_255
- * - \ref TK_SENSE_CNT_511
- * - \ref TK_SENSE_CNT_1023
- * @return None
- * \hideinitializer
- */
-#define TK_SET_SENSING_CNT(u32SenseCnt) (TK->REFCTL = (TK->REFCTL & ~TK_REFCTL_SENTCTL_Msk) | (u32SenseCnt))
-
-
-/**
- * @brief Set touch key AVCCH voltage.
- * @param[in] u32AVCCHSel voltage selection.
- * - \ref TK_AVCCH_1_DIV_16
- * - \ref TK_AVCCH_1_DIV_8
- * - \ref TK_AVCCH_3_DIV_16
- * - \ref TK_AVCCH_1_DIV_4
- * - \ref TK_AVCCH_5_DIV_16
- * - \ref TK_AVCCH_3_DIV_8
- * - \ref TK_AVCCH_7_DIV_16
- * - \ref TK_AVCCH_1_DIV_2
- * @return None
- * \hideinitializer
- */
-#define TK_SET_AVCCH(u32AVCCHSel) (TK->CTL = (TK->CTL & ~TK_CTL_AVCCHSEL_Msk) | (u32AVCCHSel))
-
-/**
- * @brief Get touch key complement capacitor bank data.
- * @param[in] u32TKNum Touch key number. The valid value is 0~16.
- * @return Complement capacitor bank data
- * \hideinitializer
- */
-#define TK_GET_COMP_CAP_BANK_DATA(u32TKNum) (((*(__IO uint32_t *) (&(TK->CCBDAT0) + ((u32TKNum) >> 2))) >> ((u32TKNum) % 4 * 8) & TK_CCBDAT0_CCBDAT0_Msk))
-
-/**
- * @brief Get touch key sensing result data.
- * @param[in] u32TKNum Touch key number. The valid value is 0~16.
- * @return Sensing result data
- * \hideinitializer
- */
-#define TK_GET_SENSE_DATA(u32TKNum) (((*(__IO uint32_t *) (&(TK->DAT0) + ((u32TKNum) >> 2))) >> ((u32TKNum) % 4 * 8) & TK_DAT0_TKDAT0_Msk))
-
-/**
- * @brief Get touch key busy status.
- * @param None
- * @retval 0 Touch key is scan completed or stopped.
- * @retval 1 Touch key is busy.
- * \hideinitializer
- */
-#define TK_IS_BUSY() ((TK->STATUS & TK_STATUS_BUSY_Msk) ? 1: 0)
-
-/**
- * @brief Get touch key interrupt flag.
- * @param[in] u32Mask Interrupt flag type selection.
- * - \ref TK_INT_SCAN_COMPLETE
- * - \ref TK_INT_SCAN_COMPLETE_TH_ALL
- * - \ref TK_INT_SCAN_TH_ALL
- * - \ref TK_INT_SCAN_TH_TK0
- * - \ref TK_INT_SCAN_TH_TK1
- * - \ref TK_INT_SCAN_TH_TK2
- * - \ref TK_INT_SCAN_TH_TK3
- * - \ref TK_INT_SCAN_TH_TK4
- * - \ref TK_INT_SCAN_TH_TK5
- * - \ref TK_INT_SCAN_TH_TK6
- * - \ref TK_INT_SCAN_TH_TK7
- * - \ref TK_INT_SCAN_TH_TK8
- * - \ref TK_INT_SCAN_TH_TK9
- * - \ref TK_INT_SCAN_TH_TK10
- * - \ref TK_INT_SCAN_TH_TK11
- * - \ref TK_INT_SCAN_TH_TK12
- * - \ref TK_INT_SCAN_TH_TK13
- * - \ref TK_INT_SCAN_TH_TK14
- * - \ref TK_INT_SCAN_TH_TK15
- * - \ref TK_INT_SCAN_TH_TK16
- * @retval 0 Touch key has no interrupt.
- * @retval 1 Touch key is scan completed or threshold control event occurs.
- * \hideinitializer
- */
-#define TK_GET_INT_STATUS(u32Mask) ((TK->STATUS & (u32Mask)) ? 1: 0)
-
-/**
- * @brief Clear touch key interrupt flag.
- * @param[in] u32Mask Interrupt flag type selection.
- * - \ref TK_INT_SCAN_COMPLETE
- * - \ref TK_INT_SCAN_COMPLETE_TH_ALL
- * - \ref TK_INT_SCAN_TH_ALL
- * - \ref TK_INT_SCAN_TH_TK0
- * - \ref TK_INT_SCAN_TH_TK1
- * - \ref TK_INT_SCAN_TH_TK2
- * - \ref TK_INT_SCAN_TH_TK3
- * - \ref TK_INT_SCAN_TH_TK4
- * - \ref TK_INT_SCAN_TH_TK5
- * - \ref TK_INT_SCAN_TH_TK6
- * - \ref TK_INT_SCAN_TH_TK7
- * - \ref TK_INT_SCAN_TH_TK8
- * - \ref TK_INT_SCAN_TH_TK9
- * - \ref TK_INT_SCAN_TH_TK10
- * - \ref TK_INT_SCAN_TH_TK11
- * - \ref TK_INT_SCAN_TH_TK12
- * - \ref TK_INT_SCAN_TH_TK13
- * - \ref TK_INT_SCAN_TH_TK14
- * - \ref TK_INT_SCAN_TH_TK15
- * - \ref TK_INT_SCAN_TH_TK16
- * @return None
- * \hideinitializer
- */
-#define TK_CLR_INT_FLAG(u32Mask) (TK->STATUS = (u32Mask))
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define TK functions prototype */
-/*---------------------------------------------------------------------------------------------------------*/
-void TK_Open(void);
-void TK_Close(void);
-void TK_SetScanMode(uint32_t u32Mode);
-void TK_ConfigSensitivity(uint32_t u32PulseWidth, uint32_t u32SenseCnt, uint32_t u32AVCCHSel);
-void TK_SetCapBankPol(uint32_t u32CapBankPolSel);
-void TK_EnableTkPolarity(uint32_t u32Mask);
-void TK_DisableTkPolarity(uint32_t u32Mask);
-void TK_SetCompCapBankData(uint32_t u32TKNum, uint32_t u32CapData);
-void TK_SetTkPol(uint32_t u32Mask, uint32_t u32PolSel);
-void TK_SetRefKeyCapBankData(uint32_t u32CapData);
-void TK_SetScanThreshold(uint32_t u32TKNum, uint32_t u32HighLevel, uint32_t u32LowLevel);
-void TK_EnableInt(uint32_t u32Msk);
-void TK_DisableInt(uint32_t u32Msk);
-
-
-/*@}*/ /* end of group TK_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group TK_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__TK_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_uart.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,512 +0,0 @@
-/**************************************************************************//**
- * @file uart.c
- * @version V3.00
- * $Revision: 22 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series UART driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include <stdio.h>
-#include "M451Series.h"
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup UART_Driver UART Driver
- @{
-*/
-
-/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
- @{
-*/
-
-/**
- * @brief Clear UART specified interrupt flag
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32InterruptFlag The specified interrupt of UART module.
- * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt
- * - \ref UART_INTSTS_DATWKIF_Msk : Data Wake-up interrupt
- * - \ref UART_INTSTS_CTSWKIF_Msk : CTS Wake-up interrupt
- * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
- * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt
- * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt
- *
- * @return None
- *
- * @details The function is used to clear UART specified interrupt flag.
- */
-
-void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
-{
-
- if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
- {
- uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk;
- uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
- }
-
- if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */
- uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
-
- if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
- {
- uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
- }
-
- if(u32InterruptFlag & UART_INTSTS_CTSWKIF_Msk) /* Clear CTS Wake-up Interrupt */
- {
- uart->INTSTS = UART_INTSTS_CTSWKIF_Msk;
- }
-
- if(u32InterruptFlag & UART_INTSTS_DATWKIF_Msk) /* Clear Data Wake-up Interrupt */
- {
- uart->INTSTS = UART_INTSTS_DATWKIF_Msk;
- }
-
- if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */
- {
- uart->INTSTS = UART_INTSTS_LINIF_Msk;
- uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk |
- UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
- UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ;
- }
-}
-
-
-/**
- * @brief Disable UART interrupt
- *
- * @param[in] uart The pointer of the specified UART module.
- *
- * @return None
- *
- * @details The function is used to disable UART interrupt.
- */
-void UART_Close(UART_T* uart)
-{
- uart->INTEN = 0;
-}
-
-
-/**
- * @brief Disable UART auto flow control function
- *
- * @param[in] uart The pointer of the specified UART module.
- *
- * @return None
- *
- * @details The function is used to disable UART auto flow control.
- */
-void UART_DisableFlowCtrl(UART_T* uart)
-{
- uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
-}
-
-
-/**
- * @brief Disable UART specified interrupt
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32InterruptFlag The specified interrupt of UART module.
- * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wake-up interrupt
- * - \ref UART_INTEN_WKDATIEN_Msk : Data wake-up interrupt
- * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
- *
- * @return None
- *
- * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
- */
-void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)
-{
- /* Disable UART specified interrupt */
- UART_DISABLE_INT(uart, u32InterruptFlag);
-
- /* Disable NVIC UART IRQ */
- if(uart == UART0)
- NVIC_DisableIRQ(UART0_IRQn);
- else if(uart == UART1)
- NVIC_DisableIRQ(UART1_IRQn);
- else if(uart == UART2)
- NVIC_DisableIRQ(UART2_IRQn);
- else
- NVIC_DisableIRQ(UART3_IRQn);
-}
-
-
-/**
- * @brief Enable UART auto flow control function
- *
- * @param[in] uart The pointer of the specified UART module.
- *
- * @return None
- *
- * @details The function is used to Enable UART auto flow control.
- */
-void UART_EnableFlowCtrl(UART_T* uart)
-{
- /* Set RTS pin output is low level active */
- uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
-
- /* Set CTS pin input is low level active */
- uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
-
- /* Set RTS and CTS auto flow control enable */
- uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
-}
-
-
-/**
- * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32InterruptFlag The specified interrupt of UART module:
- * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wake-up interrupt
- * - \ref UART_INTEN_WKDATIEN_Msk : Data wake-up interrupt
- * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt *
- *
- * @return None
- *
- * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
- */
-void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)
-{
-
- /* Enable UART specified interrupt */
- UART_ENABLE_INT(uart, u32InterruptFlag);
-
- /* Enable NVIC UART IRQ */
- if(uart == UART0)
- NVIC_EnableIRQ(UART0_IRQn);
- else if(uart == UART1)
- NVIC_EnableIRQ(UART1_IRQn);
- else if(uart == UART2)
- NVIC_EnableIRQ(UART2_IRQn);
- else
- NVIC_EnableIRQ(UART3_IRQn);
-
-}
-
-
-/**
- * @brief Open and set UART function
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32baudrate The baudrate of UART module.
- *
- * @return None
- *
- * @details This function use to enable UART function and set baud-rate.
- */
-void UART_Open(UART_T* uart, uint32_t u32baudrate)
-{
- uint8_t u8UartClkSrcSel, u8UartClkDivNum;
- uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
- uint32_t u32Baud_Div = 0;
-
- /* Get UART clock source selection */
- u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
-
- /* Get UART clock divider number */
- u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
-
- /* Select UART function */
- uart->FUNCSEL = UART_FUNCSEL_UART;
-
- /* Set UART line configuration */
- uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
-
- /* Set UART Rx and RTS trigger level */
- uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
-
- /* Get PLL clock frequency if UART clock source selection is PLL */
- if(u8UartClkSrcSel == 1)
- u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
-
- /* Set UART baud rate */
- if(u32baudrate != 0)
- {
- u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
-
- if(u32Baud_Div > 0xFFFF)
- uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
- else
- uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
- }
-}
-
-
-/**
- * @brief Read UART data
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
- * @param[in] u32ReadBytes The the read bytes number of data.
- *
- * @return u32Count Receive byte count
- *
- * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
- */
-uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
-{
- uint32_t u32Count, u32delayno;
-
- for(u32Count = 0; u32Count < u32ReadBytes; u32Count++)
- {
- u32delayno = 0;
-
- while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
- {
- u32delayno++;
- if(u32delayno >= 0x40000000)
- return FALSE;
- }
- pu8RxBuf[u32Count] = uart->DAT; /* Get Data from UART RX */
- }
-
- return u32Count;
-
-}
-
-
-/**
- * @brief Set UART line configuration
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32baudrate The register value of baudrate of UART module.
- * If u32baudrate = 0, UART baudrate will not change.
- * @param[in] u32data_width The data length of UART module.
- * - \ref UART_WORD_LEN_5
- * - \ref UART_WORD_LEN_6
- * - \ref UART_WORD_LEN_7
- * - \ref UART_WORD_LEN_8
- * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module.
- * - \ref UART_PARITY_NONE
- * - \ref UART_PARITY_ODD
- * - \ref UART_PARITY_EVEN
- * - \ref UART_PARITY_MARK
- * - \ref UART_PARITY_SPACE
- * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.
- * - \ref UART_STOP_BIT_1
- * - \ref UART_STOP_BIT_1_5
- * - \ref UART_STOP_BIT_2
- *
- * @return None
- *
- * @details This function use to config UART line setting.
- */
-void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
-{
- uint8_t u8UartClkSrcSel, u8UartClkDivNum;
- uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
- uint32_t u32Baud_Div = 0;
-
- /* Get UART clock source selection */
- u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
-
- /* Get UART clock divider number */
- u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
-
- /* Get PLL clock frequency if UART clock source selection is PLL */
- if(u8UartClkSrcSel == 1)
- u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
-
- /* Set UART baud rate */
- if(u32baudrate != 0)
- {
- u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
-
- if(u32Baud_Div > 0xFFFF)
- uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
- else
- uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
- }
-
- /* Set UART line configuration */
- uart->LINE = u32data_width | u32parity | u32stop_bits;
-}
-
-
-/**
- * @brief Set Rx timeout count
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32TOC Rx timeout counter.
- *
- * @return None
- *
- * @details This function use to set Rx timeout count.
- */
-void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
-{
- /* Set time-out interrupt comparator */
- uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
-
- /* Set time-out counter enable */
- uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
-}
-
-
-/**
- * @brief Select and configure IrDA function
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32Buadrate The baudrate of UART module.
- * @param[in] u32Direction The direction of UART module in IrDA mode:
- * - \ref UART_IRDA_TXEN
- * - \ref UART_IRDA_RXEN
- *
- * @return None
- *
- * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
- */
-void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
-{
- uint8_t u8UartClkSrcSel, u8UartClkDivNum;
- uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
- uint32_t u32Baud_Div;
-
- /* Select IrDA function mode */
- uart->FUNCSEL = UART_FUNCSEL_IrDA;
-
- /* Get UART clock source selection */
- u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
-
- /* Get UART clock divider number */
- u8UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos;
-
- /* Get PLL clock frequency if UART clock source selection is PLL */
- if(u8UartClkSrcSel == 1)
- u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
-
- /* Set UART IrDA baud rate in mode 0 */
- if(u32Buadrate != 0)
- {
- u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32Buadrate);
-
- if(u32Baud_Div < 0xFFFF)
- uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
- }
-
- /* Configure IrDA relative settings */
- if(u32Direction == UART_IRDA_RXEN)
- {
- uart->IRDA |= UART_IRDA_RXINV_Msk; //Rx signal is inverse
- uart->IRDA &= ~UART_IRDA_TXEN_Msk;
- }
- else
- {
- uart->IRDA &= ~UART_IRDA_TXINV_Msk; //Tx signal is not inverse
- uart->IRDA |= UART_IRDA_TXEN_Msk;
- }
-
-}
-
-
-/**
- * @brief Select and configure RS485 function
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32Mode The operation mode(NMM/AUD/AAD).
- * - \ref UART_ALTCTL_RS485NMM_Msk
- * - \ref UART_ALTCTL_RS485AUD_Msk
- * - \ref UART_ALTCTL_RS485AAD_Msk
- * @param[in] u32Addr The RS485 address.
- *
- * @return None
- *
- * @details The function is used to set RS485 relative setting.
- */
-void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
-{
- /* Select UART RS485 function mode */
- uart->FUNCSEL = UART_FUNCSEL_RS485;
-
- /* Set RS585 configuration */
- uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
- uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
-}
-
-
-/**
- * @brief Select and configure LIN function
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] u32Mode The LIN direction :
- * - \ref UART_ALTCTL_LINTXEN_Msk
- * - \ref UART_ALTCTL_LINRXEN_Msk
- * @param[in] u32BreakLength The breakfield length.
- *
- * @return None
- *
- * @details The function is used to set LIN relative setting.
- */
-void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
-{
- /* Select LIN function mode */
- uart->FUNCSEL = UART_FUNCSEL_LIN;
-
- /* Select LIN function setting : Tx enable, Rx enable and break field length */
- uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
- uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
-}
-
-
-/**
- * @brief Write UART data
- *
- * @param[in] uart The pointer of the specified UART module.
- * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
- * @param[out] u32WriteBytes The byte number of data.
- *
- * @return u32Count transfer byte count
- *
- * @details The function is to write data into TX buffer to transmit data by UART.
- */
-uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
-{
- uint32_t u32Count, u32delayno;
-
- for(u32Count = 0; u32Count != u32WriteBytes; u32Count++)
- {
- u32delayno = 0;
- while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0) /* Wait Tx empty and Time-out manner */
- {
- u32delayno++;
- if(u32delayno >= 0x40000000)
- return FALSE;
- }
- uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
- }
-
- return u32Count;
-
-}
-
-
-/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group UART_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2012~2015 Nuvoton Technology Corp. ***/
-
-
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_uart.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,460 +0,0 @@
-/******************************************************************************
- * @file uart.h
- * @version V3.00
- * $Revision: 36 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series UART driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __UART_H__
-#define __UART_H__
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup UART_Driver UART Driver
- @{
-*/
-
-/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART FIFO size constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-#define UART0_FIFO_SIZE 16 /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO */
-#define UART1_FIFO_SIZE 16 /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO */
-#define UART2_FIFO_SIZE 16 /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO */
-#define UART3_FIFO_SIZE 16 /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_FIFO constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-#define UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */
-#define UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */
-#define UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */
-#define UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */
-
-#define UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */
-#define UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */
-#define UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */
-#define UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_LINE constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_WORD_LEN_5 (0) /*!< UART_LINE setting to set UART word length to 5 bits */
-#define UART_WORD_LEN_6 (1) /*!< UART_LINE setting to set UART word length to 6 bits */
-#define UART_WORD_LEN_7 (2) /*!< UART_LINE setting to set UART word length to 7 bits */
-#define UART_WORD_LEN_8 (3) /*!< UART_LINE setting to set UART word length to 8 bits */
-
-#define UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */
-#define UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */
-#define UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
-#define UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
-#define UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
-
-#define UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
-#define UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
-#define UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART RTS ACTIVE LEVEL constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active */
-#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_IRDA constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_IRDA_TXEN (0x1 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode */
-#define UART_IRDA_RXEN (0x0 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_FUNCSEL constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_FUNCSEL_UART (0x0 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
-#define UART_FUNCSEL_LIN (0x1 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function */
-#define UART_FUNCSEL_IrDA (0x2 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
-#define UART_FUNCSEL_RS485 (0x3 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_LINCTL constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_LINCTL_BRKFL(x) (((x)-1) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */
-#define UART_LINCTL_BSL(x) (((x)-1) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */
-#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field */
-#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field */
-#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field*/
-#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART BAUDRATE MODE constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_BAUD_MODE0 (0) /*!< Set UART Baudrate Mode is Mode0 */
-#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */
-
-
-/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
- @{
-*/
-
-
-/**
- * @brief Calculate UART baudrate mode0 divider
- *
- * @param[in] u32SrcFreq UART clock frequency
- * @param[in] u32BaudRate Baudrate of UART module
- *
- * @return UART baudrate mode0 divider
- *
- * @details This macro calculate UART baudrate mode0 divider.
- */
-#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8)) / (u32BaudRate) >> 4)-2)
-
-
-/**
- * @brief Calculate UART baudrate mode2 divider
- *
- * @param[in] u32SrcFreq UART clock frequency
- * @param[in] u32BaudRate Baudrate of UART module
- *
- * @return UART baudrate mode2 divider
- *
- * @details This macro calculate UART baudrate mode2 divider.
- */
-#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2)) / (u32BaudRate))-2)
-
-
-/**
- * @brief Write UART data
- *
- * @param[in] uart The pointer of the specified UART module
- * @param[in] u8Data Data byte to transmit.
- *
- * @return None
- *
- * @details This macro write Data to Tx data register.
- */
-#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
-
-
-/**
- * @brief Read UART data
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @return The oldest data byte in RX FIFO.
- *
- * @details This macro read Rx data register.
- */
-#define UART_READ(uart) ((uart)->DAT)
-
-
-/**
- * @brief Get Tx empty
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 0 Tx FIFO is not empty
- * @retval >=1 Tx FIFO is empty
- *
- * @details This macro get Transmitter FIFO empty register value.
- */
-#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
-
-
-/**
- * @brief Get Rx empty
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 0 Rx FIFO is not empty
- * @retval >=1 Rx FIFO is empty
- *
- * @details This macro get Receiver FIFO empty register value.
- */
-#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
-
-
-/**
- * @brief Check specified uart port transmission is over.
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 0 Tx transmission is not over
- * @retval 1 Tx transmission is over
- *
- * @details This macro return Transmitter Empty Flag register bit value.
- * It indicates if specified uart port transmission is over nor not.
- */
-#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
-
-
-/**
- * @brief Wait specified uart port transmission is over
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @return None
- *
- * @details This macro wait specified uart port transmission is over.
- */
-#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
-
-
-/**
- * @brief Check RX is ready or not
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 0 The number of bytes in the RX FIFO is less than the RFITL
- * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
- *
- * @details This macro check receive data available interrupt flag is set or not.
- */
-#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
-
-
-/**
- * @brief Check TX FIFO is full or not
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 1 TX FIFO is full
- * @retval 0 TX FIFO is not full
- *
- * @details This macro check TX FIFO is full or not.
- */
-#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
-
-
-/**
- * @brief Check RX FIFO is full or not
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 1 RX FIFO is full
- * @retval 0 RX FIFO is not full
- *
- * @details This macro check RX FIFO is full or not.
- */
-#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
-
-
-/**
- * @brief Get Tx full register value
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 0 Tx FIFO is not full.
- * @retval >=1 Tx FIFO is full.
- *
- * @details This macro get Tx full register value.
- */
-#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
-
-
-/**
- * @brief Get Rx full register value
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 0 Rx FIFO is not full.
- * @retval >=1 Rx FIFO is full.
- *
- * @details This macro get Rx full register value.
- */
-#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
-
-
-/**
- * @brief Enable specified UART interrupt
- *
- * @param[in] uart The pointer of the specified UART module
- * @param[in] u32eIntSel Interrupt type select
- * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
- * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wakeup interrupt
- * - \ref UART_INTEN_WKDATIEN_Msk : Data wakeup interrupt
- * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
- *
- * @return None
- *
- * @details This macro enable specified UART interrupt.
- */
-#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))
-
-
-/**
- * @brief Disable specified UART interrupt
- *
- * @param[in] uart The pointer of the specified UART module
- * @param[in] u32eIntSel Interrupt type select
- * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
- * - \ref UART_INTEN_WKCTSIEN_Msk : CTS wakeup interrupt
- * - \ref UART_INTEN_WKDATIEN_Msk : Data wakeup interrupt
- * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
- *
- * @return None
- *
- * @details This macro enable specified UART interrupt.
- */
-#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))
-
-
-/**
- * @brief Get specified interrupt flag/status
- *
- * @param[in] uart The pointer of the specified UART module
- * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
- * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator
- * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator
- * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator
- * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator
- * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag
- * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag
- * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag
- * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag
- * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator
- * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
- * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
- * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
- * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
- * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
- * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
- * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag
- * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
- * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
- * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag
- * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
- * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag
- * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag
- *
- * @retval 0 The specified interrupt is not happened.
- * 1 The specified interrupt is happened.
- *
- * @details This macro get specified interrupt flag or interrupt indicator status.
- */
-#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
-
-
-/**
- * @brief Set RTS pin to low
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @return None
- *
- * @details This macro set RTS pin to low.
- */
-__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
-{
- uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
- uart->MODEM &= ~UART_MODEM_RTS_Msk;
-}
-
-
-/**
- * @brief Set RTS pin to high
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @return None
- *
- * @details This macro set RTS pin to high.
- */
-__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
-{
- uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
-}
-
-
-/**
- * @brief Clear RS-485 Address Byte Detection Flag
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @return None
- *
- * @details This macro clear RS-485 address byte detection flag.
- */
-#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
-
-
-/**
- * @brief Get RS-485 Address Byte Detection Flag
- *
- * @param[in] uart The pointer of the specified UART module
- *
- * @retval 0 Receiver detects a data that is not an address bit.
- * @retval 1 Receiver detects a data that is an address bit.
- *
- * @details This macro get RS-485 address byte detection flag.
- */
-#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
-
-
-void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
-void UART_Close(UART_T* uart);
-void UART_DisableFlowCtrl(UART_T* uart);
-void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag);
-void UART_EnableFlowCtrl(UART_T* uart);
-void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag);
-void UART_Open(UART_T* uart, uint32_t u32baudrate);
-uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
-void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
-void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
-void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
-void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
-void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
-uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
-
-
-
-
-/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group UART_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__UART_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_usbd.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,728 +0,0 @@
-/**************************************************************************//**
- * @file usbd.c
- * @version V1.00
- * $Revision: 21 $
- * $Date: 15/08/21 3:34p $
- * @brief M451 series USBD driver source file
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include <string.h>
-#include "M451Series.h"
-
-#if 0
-#define DBG_PRINTF printf
-#else
-#define DBG_PRINTF(...)
-#endif
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup USBD_Driver USBD Driver
- @{
-*/
-
-
-/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
- @{
-*/
-
-/* Global variables for Control Pipe */
-uint8_t g_usbd_SetupPacket[8] = {0}; /*!< Setup packet buffer */
-volatile uint8_t g_usbd_RemoteWakeupEn = 0; /*!< Remote wake up function enable flag */
-
-/**
- * @cond HIDDEN_SYMBOLS
- */
-static volatile uint8_t *g_usbd_CtrlInPointer = 0;
-static volatile uint32_t g_usbd_CtrlInSize = 0;
-static volatile uint8_t *g_usbd_CtrlOutPointer = 0;
-static volatile uint32_t g_usbd_CtrlOutSize = 0;
-static volatile uint32_t g_usbd_CtrlOutSizeLimit = 0;
-static volatile uint32_t g_usbd_UsbAddr = 0;
-static volatile uint32_t g_usbd_UsbConfig = 0;
-static volatile uint32_t g_usbd_CtrlMaxPktSize = 8;
-static volatile uint32_t g_usbd_UsbAltInterface = 0;
-/**
- * @endcond
- */
-
-const S_USBD_INFO_T *g_usbd_sInfo; /*!< A pointer for USB information structure */
-
-VENDOR_REQ g_usbd_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */
-CLASS_REQ g_usbd_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */
-SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */
-SET_CONFIG_CB g_usbd_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */
-uint32_t g_u32EpStallLock = 0; /*!< Bit map flag to lock specified EP when SET_FEATURE */
-
-/**
- * @brief This function makes USBD module to be ready to use
- *
- * @param[in] param The structure of USBD information.
- * @param[in] pfnClassReq USB Class request callback function.
- * @param[in] pfnSetInterface USB Set Interface request callback function.
- *
- * @return None
- *
- * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
- */
-void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
-{
- g_usbd_sInfo = param;
- g_usbd_pfnClassRequest = pfnClassReq;
- g_usbd_pfnSetInterface = pfnSetInterface;
-
- /* get EP0 maximum packet size */
- g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
-
- /* Initial USB engine */
- USBD->ATTR = 0x7D0;
- /* Force SE0 */
- USBD_SET_SE0();
-}
-
-/**
- * @brief This function makes USB host to recognize the device
- *
- * @param None
- *
- * @return None
- *
- * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
- */
-void USBD_Start(void)
-{
- CLK_SysTickDelay(100000);
- /* Disable software-disconnect function */
- USBD_CLR_SE0();
-
- /* Clear USB-related interrupts before enable interrupt */
- USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
-
- /* Enable USB-related interrupts. */
- USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
-}
-
-/**
- * @brief Get the received SETUP packet
- *
- * @param[in] buf A buffer pointer used to store 8-byte SETUP packet.
- *
- * @return None
- *
- * @details Store SETUP packet to a user-specified buffer.
- *
- */
-void USBD_GetSetupPacket(uint8_t *buf)
-{
- USBD_MemCopy(buf, g_usbd_SetupPacket, 8);
-}
-
-/**
- * @brief Process SETUP packet
- *
- * @param None
- *
- * @return None
- *
- * @details Parse SETUP packet and perform the corresponding action.
- *
- */
-void USBD_ProcessSetupPacket(void)
-{
- /* Get SETUP packet from USB buffer */
- USBD_MemCopy(g_usbd_SetupPacket, (uint8_t *)USBD_BUF_BASE, 8);
- /* Check the request type */
- switch(g_usbd_SetupPacket[0] & 0x60)
- {
- case REQ_STANDARD: // Standard
- {
- USBD_StandardRequest();
- break;
- }
- case REQ_CLASS: // Class
- {
- if(g_usbd_pfnClassRequest != NULL)
- {
- g_usbd_pfnClassRequest();
- }
- break;
- }
- case REQ_VENDOR: // Vendor
- {
- if(g_usbd_pfnVendorRequest != NULL)
- {
- g_usbd_pfnVendorRequest();
- }
- break;
- }
- default: // reserved
- {
- /* Setup error, stall the device */
- USBD_SET_EP_STALL(EP0);
- USBD_SET_EP_STALL(EP1);
- break;
- }
- }
-}
-
-/**
- * @brief Process GetDescriptor request
- *
- * @param None
- *
- * @return None
- *
- * @details Parse GetDescriptor request and perform the corresponding action.
- *
- */
-void USBD_GetDescriptor(void)
-{
- uint32_t u32Len;
-
- u32Len = 0;
- u32Len = g_usbd_SetupPacket[7];
- u32Len <<= 8;
- u32Len += g_usbd_SetupPacket[6];
-
- switch(g_usbd_SetupPacket[3])
- {
- // Get Device Descriptor
- case DESC_DEVICE:
- {
- u32Len = Minimum(u32Len, LEN_DEVICE);
- DBG_PRINTF("Get device desc, %d\n", u32Len);
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
-
- break;
- }
- // Get Configuration Descriptor
- case DESC_CONFIG:
- {
- uint32_t u32TotalLen;
-
- u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
- u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
-
- DBG_PRINTF("Get config desc len %d, acture len %d\n", u32Len, u32TotalLen);
- u32Len = Minimum(u32Len, u32TotalLen);
- DBG_PRINTF("Minimum len %d\n", u32Len);
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
-
- break;
- }
- // Get HID Descriptor
- case DESC_HID:
- {
- /* CV3.0 HID Class Descriptor Test,
- Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
- uint32_t u32ConfigDescOffset; // u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index)
- u32Len = Minimum(u32Len, LEN_HID);
- DBG_PRINTF("Get HID desc, %d\n", u32Len);
-
- u32ConfigDescOffset = g_usbd_sInfo->gu32ConfigHidDescIdx[g_usbd_SetupPacket[4]];
- USBD_PrepareCtrlIn((uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
-
- break;
- }
- // Get Report Descriptor
- case DESC_HID_RPT:
- {
- DBG_PRINTF("Get HID report, %d\n", u32Len);
-
- u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[g_usbd_SetupPacket[4]]);
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[g_usbd_SetupPacket[4]], u32Len);
- break;
- }
- // Get String Descriptor
- case DESC_STRING:
- {
- // Get String Descriptor
- if(g_usbd_SetupPacket[2] < 4)
- {
- u32Len = Minimum(u32Len, g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]][0]);
- DBG_PRINTF("Get string desc %d\n", u32Len);
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StringDesc[g_usbd_SetupPacket[2]], u32Len);
-
-
- break;
- }
- else
- {
- // Not support. Reply STALL.
- USBD_SET_EP_STALL(EP0);
- USBD_SET_EP_STALL(EP1);
-
- DBG_PRINTF("Unsupported string desc (%d). Stall ctrl pipe.\n", g_usbd_SetupPacket[2]);
-
- break;
- }
- }
- default:
- // Not support. Reply STALL.
- USBD_SET_EP_STALL(EP0);
- USBD_SET_EP_STALL(EP1);
-
- DBG_PRINTF("Unsupported get desc type. stall ctrl pipe\n");
-
- break;
- }
-}
-
-/**
- * @brief Process standard request
- *
- * @param None
- *
- * @return None
- *
- * @details Parse standard request and perform the corresponding action.
- *
- */
-void USBD_StandardRequest(void)
-{
-
- /* clear global variables for new request */
- g_usbd_CtrlInPointer = 0;
- g_usbd_CtrlInSize = 0;
-
- if(g_usbd_SetupPacket[0] & 0x80) /* request data transfer direction */
- {
- // Device to host
- switch(g_usbd_SetupPacket[1])
- {
- case GET_CONFIGURATION:
- {
- // Return current configuration setting
- /* Data stage */
- M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbConfig;
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 1);
- /* Status stage */
- USBD_PrepareCtrlOut(0,0);
-
- DBG_PRINTF("Get configuration\n");
-
- break;
- }
- case GET_DESCRIPTOR:
- {
- USBD_GetDescriptor();
- USBD_PrepareCtrlOut(0, 0); /* For status stage */
- break;
- }
- case GET_INTERFACE:
- {
- // Return current interface setting
- /* Data stage */
- M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = g_usbd_UsbAltInterface;
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 1);
- /* Status stage */
- USBD_PrepareCtrlOut(0, 0);
-
- DBG_PRINTF("Get interface\n");
-
- break;
- }
- case GET_STATUS:
- {
- // Device
- if(g_usbd_SetupPacket[0] == 0x80)
- {
- uint8_t u8Tmp;
-
- u8Tmp = 0;
- if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x40) u8Tmp |= 1; // Self-Powered/Bus-Powered.
- if(g_usbd_sInfo->gu8ConfigDesc[7] & 0x20) u8Tmp |= (g_usbd_RemoteWakeupEn << 1); // Remote wake up
-
- M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp;
-
- }
- // Interface
- else if(g_usbd_SetupPacket[0] == 0x81)
- M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = 0;
- // Endpoint
- else if(g_usbd_SetupPacket[0] == 0x82)
- {
- uint8_t ep = g_usbd_SetupPacket[4] & 0xF;
- M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = USBD_GetStall(ep) ? 1 : 0;
- }
-
- M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = 0;
- /* Data stage */
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 2);
- /* Status stage */
- USBD_PrepareCtrlOut(0, 0);
-
- DBG_PRINTF("Get status\n");
-
- break;
- }
- default:
- {
- /* Setup error, stall the device */
- USBD_SET_EP_STALL(EP0);
- USBD_SET_EP_STALL(EP1);
-
- DBG_PRINTF("Unknown request. stall ctrl pipe.\n");
-
- break;
- }
- }
- }
- else
- {
- // Host to device
- switch(g_usbd_SetupPacket[1])
- {
- case CLEAR_FEATURE:
- {
- if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
- {
- int32_t epNum, i;
-
- /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
- a flag: g_u32EpStallLock is added to support it */
- epNum = g_usbd_SetupPacket[4] & 0xF;
- for(i = 0; i < USBD_MAX_EP; i++)
- {
- if(((USBD->EP[i].CFG & 0xF) == epNum) && ((g_u32EpStallLock & (1 << i)) == 0))
- {
- USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
- DBG_PRINTF("Clr stall ep%d %x\n", i, USBD->EP[i].CFGP);
- }
- }
- }
- else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
- g_usbd_RemoteWakeupEn = 0;
-
- /* Status stage */
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 0);
-
- DBG_PRINTF("Clear feature op %d\n", g_usbd_SetupPacket[2]);
-
- break;
- }
- case SET_ADDRESS:
- {
- g_usbd_UsbAddr = g_usbd_SetupPacket[2];
- DBG_PRINTF("Set addr to %d\n", g_usbd_UsbAddr);
-
- // DATA IN for end of setup
- /* Status Stage */
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 0);
-
- break;
- }
- case SET_CONFIGURATION:
- {
- g_usbd_UsbConfig = g_usbd_SetupPacket[2];
-
- if(g_usbd_pfnSetConfigCallback)
- g_usbd_pfnSetConfigCallback();
-
- // DATA IN for end of setup
- /* Status stage */
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 0);
-
- DBG_PRINTF("Set config to %d\n", g_usbd_UsbConfig);
-
- break;
- }
- case SET_FEATURE:
- {
- if(g_usbd_SetupPacket[2] == FEATURE_ENDPOINT_HALT)
- {
- USBD_SetStall(g_usbd_SetupPacket[4] & 0xF);
- DBG_PRINTF("Set feature. stall ep %d\n", g_usbd_SetupPacket[4] & 0xF);
- }
- else if(g_usbd_SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
- {
- g_usbd_RemoteWakeupEn = 1;
- DBG_PRINTF("Set feature. enable remote wakeup\n");
- }
-
- /* Status stage */
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 0);
-
-
-
- break;
- }
- case SET_INTERFACE:
- {
- g_usbd_UsbAltInterface = g_usbd_SetupPacket[2];
- if(g_usbd_pfnSetInterface != NULL)
- g_usbd_pfnSetInterface();
- /* Status stage */
- USBD_SET_DATA1(EP0);
- USBD_SET_PAYLOAD_LEN(EP0, 0);
-
- DBG_PRINTF("Set interface to %d\n", g_usbd_UsbAltInterface);
-
- break;
- }
- default:
- {
- /* Setup error, stall the device */
- USBD_SET_EP_STALL(EP0);
- USBD_SET_EP_STALL(EP1);
-
- DBG_PRINTF("Unsupported request. stall ctrl pipe.\n");
-
- break;
- }
- }
- }
-}
-
-/**
- * @brief Prepare the first Control IN pipe
- *
- * @param[in] pu8Buf The pointer of data sent to USB host.
- * @param[in] u32Size The IN transfer size.
- *
- * @return None
- *
- * @details Prepare data for Control IN transfer.
- *
- */
-void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size)
-{
- DBG_PRINTF("Prepare Ctrl In %d\n", u32Size);
- if(u32Size > g_usbd_CtrlMaxPktSize)
- {
- // Data size > MXPLD
- g_usbd_CtrlInPointer = pu8Buf + g_usbd_CtrlMaxPktSize;
- g_usbd_CtrlInSize = u32Size - g_usbd_CtrlMaxPktSize;
- USBD_SET_DATA1(EP0);
- USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, g_usbd_CtrlMaxPktSize);
- USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
- }
- else
- {
- // Data size <= MXPLD
- g_usbd_CtrlInPointer = 0;
- g_usbd_CtrlInSize = 0;
- USBD_SET_DATA1(EP0);
- USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size);
- USBD_SET_PAYLOAD_LEN(EP0, u32Size);
- }
-}
-
-/**
- * @brief Repeat Control IN pipe
- *
- * @param None
- *
- * @return None
- *
- * @details This function processes the remained data of Control IN transfer.
- *
- */
-void USBD_CtrlIn(void)
-{
- static uint8_t u8ZeroFlag = 0;
-
- DBG_PRINTF("Ctrl In Ack. residue %d\n", g_usbd_CtrlInSize);
- if(g_usbd_CtrlInSize)
- {
- // Process remained data
- if(g_usbd_CtrlInSize > g_usbd_CtrlMaxPktSize)
- {
- // Data size > MXPLD
- USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlMaxPktSize);
- USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlMaxPktSize);
- g_usbd_CtrlInPointer += g_usbd_CtrlMaxPktSize;
- g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
- }
- else
- {
- // Data size <= MXPLD
- USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)g_usbd_CtrlInPointer, g_usbd_CtrlInSize);
- USBD_SET_PAYLOAD_LEN(EP0, g_usbd_CtrlInSize);
- if(g_usbd_CtrlInSize == g_usbd_CtrlMaxPktSize)
- u8ZeroFlag = 1;
- g_usbd_CtrlInPointer = 0;
- g_usbd_CtrlInSize = 0;
- }
- }
- else // No more data for IN token
- {
- // In ACK for Set address
- if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS))
- {
- if((USBD_GET_ADDR() != g_usbd_UsbAddr) && (USBD_GET_ADDR() == 0))
- {
- USBD_SET_ADDR(g_usbd_UsbAddr);
- }
- }
-
- /* For the case of data size is integral times maximum packet size */
- if(u8ZeroFlag)
- {
- USBD_SET_PAYLOAD_LEN(EP0, 0);
- u8ZeroFlag = 0;
- }
-
- DBG_PRINTF("Ctrl In done.\n");
-
- }
-}
-
-/**
- * @brief Prepare the first Control OUT pipe
- *
- * @param[in] pu8Buf The pointer of data received from USB host.
- * @param[in] u32Size The OUT transfer size.
- *
- * @return None
- *
- * @details This function is used to prepare the first Control OUT transfer.
- *
- */
-void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
-{
- g_usbd_CtrlOutPointer = pu8Buf;
- g_usbd_CtrlOutSize = 0;
- g_usbd_CtrlOutSizeLimit = u32Size;
- USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
-}
-
-/**
- * @brief Repeat Control OUT pipe
- *
- * @param None
- *
- * @return None
- *
- * @details This function processes the successive Control OUT transfer.
- *
- */
-void USBD_CtrlOut(void)
-{
- uint32_t u32Size;
-
- DBG_PRINTF("Ctrl Out Ack %d\n", g_usbd_CtrlOutSize);
-
- if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
- {
- u32Size = USBD_GET_PAYLOAD_LEN(EP1);
- USBD_MemCopy((uint8_t *)g_usbd_CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size);
- g_usbd_CtrlOutPointer += u32Size;
- g_usbd_CtrlOutSize += u32Size;
-
- if(g_usbd_CtrlOutSize < g_usbd_CtrlOutSizeLimit)
- USBD_SET_PAYLOAD_LEN(EP1, g_usbd_CtrlMaxPktSize);
-
- }
-}
-
-/**
- * @brief Reset software flags
- *
- * @param None
- *
- * @return None
- *
- * @details This function resets all variables for protocol and resets USB device address to 0.
- *
- */
-void USBD_SwReset(void)
-{
- int i;
-
- // Reset all variables for protocol
- g_usbd_CtrlInPointer = 0;
- g_usbd_CtrlInSize = 0;
- g_usbd_CtrlOutPointer = 0;
- g_usbd_CtrlOutSize = 0;
- g_usbd_CtrlOutSizeLimit = 0;
- g_u32EpStallLock = 0;
- memset(g_usbd_SetupPacket, 0, 8);
-
- /* Reset PID DATA0 */
- for(i=0; i<USBD_MAX_EP; i++)
- USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
-
- // Reset USB device address
- USBD_SET_ADDR(0);
-}
-
-/**
- * @brief USBD Set Vendor Request
- *
- * @param[in] pfnVendorReq Vendor Request Callback Function
- *
- * @return None
- *
- * @details This function is used to set USBD vendor request callback function
- */
-void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
-{
- g_usbd_pfnVendorRequest = pfnVendorReq;
-}
-
-/**
- * @brief The callback function which called when get SET CONFIGURATION request
- *
- * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request
- *
- * @return None
- *
- * @details This function is used to set the callback function which will be called at SET CONFIGURATION request.
- */
-void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
-{
- g_usbd_pfnSetConfigCallback = pfnSetConfigCallback;
-}
-
-
-/**
- * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request.
- *
- * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked
- *
- * @return None
- *
- * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE requst.
- * If ep stall locked, user needs to reset USB device or re-configure device to clear it.
- */
-void USBD_LockEpStall(uint32_t u32EpBitmap)
-{
- g_u32EpStallLock = u32EpBitmap;
-}
-
-
-
-
-
-/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group USBD_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_usbd.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,664 +0,0 @@
-/******************************************************************************
- * @file usbd.h
- * @brief M451 series USB driver header file
- * @version 2.0.0
- * @date 10, January, 2014
- *
- * @note
- * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
- ******************************************************************************/
-#ifndef __USBD_H__
-#define __USBD_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup USBD_Driver USBD Driver
- @{
-*/
-
-/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs
- @{
-*/
-typedef struct s_usbd_info
-{
- const uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */
- const uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */
- const uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
- const uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */
- const uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
- const uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
-
-} S_USBD_INFO_T;
-
-extern const S_USBD_INFO_T gsInfo;
-
-/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */
-
-
-
-
-/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
- @{
-*/
-#define USBD_BUF_BASE (USBD_BASE+0x100)
-#define USBD_MAX_EP 8
-
-#define EP0 0 /*!< Endpoint 0 */
-#define EP1 1 /*!< Endpoint 1 */
-#define EP2 2 /*!< Endpoint 2 */
-#define EP3 3 /*!< Endpoint 3 */
-#define EP4 4 /*!< Endpoint 4 */
-#define EP5 5 /*!< Endpoint 5 */
-#define EP6 6 /*!< Endpoint 6 */
-#define EP7 7 /*!< Endpoint 7 */
-
-
-/*!<USB Request Type */
-#define REQ_STANDARD 0x00
-#define REQ_CLASS 0x20
-#define REQ_VENDOR 0x40
-
-/*!<USB Standard Request */
-#define GET_STATUS 0x00
-#define CLEAR_FEATURE 0x01
-#define SET_FEATURE 0x03
-#define SET_ADDRESS 0x05
-#define GET_DESCRIPTOR 0x06
-#define SET_DESCRIPTOR 0x07
-#define GET_CONFIGURATION 0x08
-#define SET_CONFIGURATION 0x09
-#define GET_INTERFACE 0x0A
-#define SET_INTERFACE 0x0B
-#define SYNC_FRAME 0x0C
-
-/*!<USB Descriptor Type */
-#define DESC_DEVICE 0x01
-#define DESC_CONFIG 0x02
-#define DESC_STRING 0x03
-#define DESC_INTERFACE 0x04
-#define DESC_ENDPOINT 0x05
-#define DESC_QUALIFIER 0x06
-#define DESC_OTHERSPEED 0x07
-
-/*!<USB HID Descriptor Type */
-#define DESC_HID 0x21
-#define DESC_HID_RPT 0x22
-
-/*!<USB Descriptor Length */
-#define LEN_DEVICE 18
-#define LEN_CONFIG 9
-#define LEN_INTERFACE 9
-#define LEN_ENDPOINT 7
-#define LEN_HID 9
-#define LEN_CCID 0x36
-
-/*!<USB Endpoint Type */
-#define EP_ISO 0x01
-#define EP_BULK 0x02
-#define EP_INT 0x03
-
-#define EP_INPUT 0x80
-#define EP_OUTPUT 0x00
-
-/*!<USB Feature Selector */
-#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01
-#define FEATURE_ENDPOINT_HALT 0x00
-
-/******************************************************************************/
-/* USB Specific Macros */
-/******************************************************************************/
-
-#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable */
-#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 */
-
-#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable */
-#define USBD_PWRDN USBD_ATTR_PWRDN_Msk /*!< PHY Turn-On */
-#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable */
-#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable */
-
-#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt */
-#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt */
-#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt */
-#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt */
-
-#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status */
-#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status */
-#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status */
-#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status */
-#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event */
-#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event */
-#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event */
-#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event */
-#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event */
-#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event */
-#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event */
-#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event */
-#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event */
-
-#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset */
-#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend */
-#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume */
-#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout */
-
-#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall */
-#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */
-
-#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable */
-#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint */
-#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint */
-#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos) /*!< Isochronous */
-
-
-
-/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
- @{
-*/
-
-/**
- * @brief Compare two input numbers and return maximum one.
- *
- * @param[in] a First number to be compared.
- * @param[in] b Second number to be compared.
- *
- * @return Maximum value between a and b.
- *
- * @details If a > b, then return a. Otherwise, return b.
- */
-#define Maximum(a,b) ((a)>(b) ? (a) : (b))
-
-
-/**
- * @brief Compare two input numbers and return minimum one
- *
- * @param[in] a First number to be compared
- * @param[in] b Second number to be compared
- *
- * @return Minimum value between a and b
- *
- * @details If a < b, then return a. Otherwise, return b.
- */
-#define Minimum(a,b) ((a)<(b) ? (a) : (b))
-
-
-/**
- * @brief Enable USB
- *
- * @param None
- *
- * @return None
- *
- * @details To set USB ATTR control register to enable USB and PHY.
- *
- */
-#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= (USBD_USB_EN|USBD_PHY_EN)))
-
-/**
- * @brief Disable USB
- *
- * @param None
- *
- * @return None
- *
- * @details To set USB ATTR control register to disable USB.
- *
- */
-#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
-
-/**
- * @brief Enable USB PHY
- *
- * @param None
- *
- * @return None
- *
- * @details To set USB ATTR control register to enable USB PHY.
- *
- */
-#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
-
-/**
- * @brief Disable USB PHY
- *
- * @param None
- *
- * @return None
- *
- * @details To set USB ATTR control register to disable USB PHY.
- *
- */
-#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
-
-/**
- * @brief Enable SE0. Force USB PHY transceiver to drive SE0.
- *
- * @param None
- *
- * @return None
- *
- * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
- *
- */
-#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
-
-/**
- * @brief Disable SE0
- *
- * @param None
- *
- * @return None
- *
- * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
- *
- */
-#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
-
-/**
- * @brief Set USB device address
- *
- * @param[in] addr The USB device address.
- *
- * @return None
- *
- * @details Write USB device address to USB_FADDR register.
- *
- */
-#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
-
-/**
- * @brief Get USB device address
- *
- * @param None
- *
- * @return USB device address
- *
- * @details Read USB_FADDR register to get USB device address.
- *
- */
-#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
-
-/**
- * @brief Enable USB interrupt function
- *
- * @param[in] intr The combination of the specified interrupt enable bits.
- * Each bit corresponds to a interrupt enable bit.
- * This parameter decides which interrupts will be enabled.
- * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
- *
- * @return None
- *
- * @details Enable USB related interrupt functions specified by intr parameter.
- *
- */
-#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
-
-/**
- * @brief Get interrupt status
- *
- * @param None
- *
- * @return The value of USB_INTSTS register
- *
- * @details Return all interrupt flags of USB_INTSTS register.
- *
- */
-#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
-
-/**
- * @brief Clear USB interrupt flag
- *
- * @param[in] flag The combination of the specified interrupt flags.
- * Each bit corresponds to a interrupt source.
- * This parameter decides which interrupt flags will be cleared.
- * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
- *
- * @return None
- *
- * @details Clear USB related interrupt flags specified by flag parameter.
- *
- */
-#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag))
-
-/**
- * @brief Get endpoint status
- *
- * @param None
- *
- * @return The value of USB_EPSTS register.
- *
- * @details Return all endpoint status.
- *
- */
-#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
-
-/**
- * @brief Get USB bus state
- *
- * @param None
- *
- * @return The value of USB_ATTR[3:0].
- * Bit 0 indicates USB bus reset status.
- * Bit 1 indicates USB bus suspend status.
- * Bit 2 indicates USB bus resume status.
- * Bit 3 indicates USB bus time-out status.
- *
- * @details Return USB_ATTR[3:0] for USB bus events.
- *
- */
-#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf))
-
-/**
- * @brief Check cable connection state
- *
- * @param None
- *
- * @retval 0 USB cable is not attached.
- * @retval 1 USB cable is attached.
- *
- * @details Check the connection state by FLDET bit of USB_FLDET register.
- *
- */
-#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
-
-/**
- * @brief Stop USB transaction of the specified endpoint ID
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @return None
- *
- * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
- *
- */
-#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
-
-/**
- * @brief Set USB DATA1 PID for the specified endpoint ID
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @return None
- *
- * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
- * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
- *
- */
-#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
-
-/**
- * @brief Set USB DATA0 PID for the specified endpoint ID
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @return None
- *
- * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
- * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
- *
- */
-#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
-
-/**
- * @brief Set USB payload size (IN data)
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @param[in] size The transfer length.
- *
- * @return None
- *
- * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
- *
- */
-#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
-
-/**
- * @brief Get USB payload size (OUT data)
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 endpoint ID. This parameter could be 0 ~ 7.
- *
- * @return The value of USB_MXPLDx register.
- *
- * @details Get the data length of OUT data transaction by reading USB_MXPLDx register.
- *
- */
-#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
-
-/**
- * @brief Configure endpoint
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @param[in] config The USB configuration.
- *
- * @return None
- *
- * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID.
- *
- */
-#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
-
-/**
- * @brief Set USB endpoint buffer
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @param[in] offset The SRAM offset.
- *
- * @return None
- *
- * @details This macro will set the SRAM offset for the specified endpoint ID.
- *
- */
-#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
-
-/**
- * @brief Get the offset of the specified USB endpoint buffer
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @return The offset of the specified endpoint buffer.
- *
- * @details This macro will return the SRAM offset of the specified endpoint ID.
- *
- */
-#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
-
-/**
- * @brief Set USB endpoint stall state
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @return None
- *
- * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
- *
- */
-#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
-
-/**
- * @brief Clear USB endpoint stall state
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @return None
- *
- * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
- */
-#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
-
-/**
- * @brief Get USB endpoint stall state
- *
- * @param[in] ep The USB endpoint ID. M451 Series supports 8 hardware endpoint ID. This parameter could be 0 ~ 7.
- *
- * @retval 0 USB endpoint is not stalled.
- * @retval Others USB endpoint is stalled.
- *
- * @details Get USB endpoint stall state of the specified endpoint ID.
- *
- */
-#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
-
-/**
- * @brief To support byte access between USB SRAM and system SRAM
- *
- * @param[in] dest Destination pointer.
- *
- * @param[in] src Source pointer.
- *
- * @param[in] size Byte count.
- *
- * @return None
- *
- * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
- *
- */
-static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size)
-{
- while(size--) *dest++ = *src++;
-}
-
-
-/**
- * @brief Set USB endpoint stall state
- *
- * @param[in] epnum USB endpoint number
- *
- * @return None
- *
- * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically.
- *
- */
-static __INLINE void USBD_SetStall(uint8_t epnum)
-{
- uint32_t u32CfgAddr;
- uint32_t u32Cfg;
- int i;
-
- for(i = 0; i < USBD_MAX_EP; i++)
- {
- u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
- u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
-
- if((u32Cfg & 0xf) == epnum)
- {
- u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
- u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
-
- *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
- break;
- }
- }
-}
-
-/**
- * @brief Clear USB endpoint stall state
- *
- * @param[in] epnum USB endpoint number
- *
- * @return None
- *
- * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
- */
-static __INLINE void USBD_ClearStall(uint8_t epnum)
-{
- uint32_t u32CfgAddr;
- uint32_t u32Cfg;
- int i;
-
- for(i = 0; i < USBD_MAX_EP; i++)
- {
- u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
- u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
-
- if((u32Cfg & 0xf) == epnum)
- {
- u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
- u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
-
- *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
- break;
- }
- }
-}
-
-/**
- * @brief Get USB endpoint stall state
- *
- * @param[in] epnum USB endpoint number
- *
- * @retval 0 USB endpoint is not stalled.
- * @retval Others USB endpoint is stalled.
- *
- * @details Get USB endpoint stall state.
- *
- */
-static __INLINE uint32_t USBD_GetStall(uint8_t epnum)
-{
- uint32_t u32CfgAddr;
- uint32_t u32Cfg;
- int i;
-
- for(i = 0; i < USBD_MAX_EP; i++)
- {
- u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
- u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
-
- if((u32Cfg & 0xf) == epnum)
- {
- u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
- break;
- }
- }
-
- return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
-}
-
-
-extern volatile uint8_t g_usbd_RemoteWakeupEn;
-
-
-typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */
-typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */
-typedef void (*SET_INTERFACE_REQ)(void); /*!< Functional pointer type declaration for USB set interface request callback handler */
-typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
-
-
-/*--------------------------------------------------------------------*/
-void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
-void USBD_Start(void);
-void USBD_GetSetupPacket(uint8_t *buf);
-void USBD_ProcessSetupPacket(void);
-void USBD_StandardRequest(void);
-void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
-void USBD_CtrlIn(void);
-void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
-void USBD_CtrlOut(void);
-void USBD_SwReset(void);
-void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
-void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
-void USBD_LockEpStall(uint32_t u32EpBitmap);
-
-/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group USBD_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__USBD_H__
-
-/*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wdt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-/**************************************************************************//**
- * @file wdt.c
- * @version V3.00
- * $Revision: 5 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series WDT driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup WDT_Driver WDT Driver
- @{
-*/
-
-/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
- @{
-*/
-
-/**
- * @brief Initialize WDT and start counting
- *
- * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
- * - \ref WDT_TIMEOUT_2POW4
- * - \ref WDT_TIMEOUT_2POW6
- * - \ref WDT_TIMEOUT_2POW8
- * - \ref WDT_TIMEOUT_2POW10
- * - \ref WDT_TIMEOUT_2POW12
- * - \ref WDT_TIMEOUT_2POW14
- * - \ref WDT_TIMEOUT_2POW16
- * - \ref WDT_TIMEOUT_2POW18
- * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are:
- * - \ref WDT_RESET_DELAY_1026CLK
- * - \ref WDT_RESET_DELAY_130CLK
- * - \ref WDT_RESET_DELAY_18CLK
- * - \ref WDT_RESET_DELAY_3CLK
- * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
- * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
- *
- * @return None
- *
- * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
- * enable or disable WDT time-out reset system or wake-up system.
- * @note Please make sure that Register Write-Protection Function has been disabled before using this function.
- */
-void WDT_Open(uint32_t u32TimeoutInterval,
- uint32_t u32ResetDelay,
- uint32_t u32EnableReset,
- uint32_t u32EnableWakeup)
-{
- WDT->ALTCTL = u32ResetDelay;
-
- WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
- (u32EnableReset << WDT_CTL_RSTEN_Pos) |
- (u32EnableWakeup << WDT_CTL_WKEN_Pos);
- return;
-}
-
-/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group WDT_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wdt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,201 +0,0 @@
-/**************************************************************************//**
- * @file wdt.h
- * @version V3.00
- * $Revision: 7 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series WDT driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __WDT_H__
-#define __WDT_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup WDT_Driver WDT Driver
- @{
-*/
-
-/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* WDT Time-out Interval Period Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
-#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
-#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
-#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
-#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
-#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
-#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
-#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* WDT Reset Delay Period Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
-#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
-#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
-#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
-
-/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
- @{
-*/
-
-/**
- * @brief Clear WDT Reset System Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro clears WDT time-out reset system flag.
- */
-#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
-
-/**
- * @brief Clear WDT Time-out Interrupt Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro clears WDT time-out interrupt flag.
- */
-#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
-
-/**
- * @brief Clear WDT Wake-up Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro clears WDT time-out wake-up system flag.
- */
-#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
-
-/**
- * @brief Get WDT Time-out Reset Flag
- *
- * @param None
- *
- * @retval 0 WDT time-out reset system did not occur
- * @retval 1 WDT time-out reset system occurred
- *
- * @details This macro indicates system has been reset by WDT time-out reset or not.
- */
-#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1 : 0)
-
-/**
- * @brief Get WDT Time-out Interrupt Flag
- *
- * @param None
- *
- * @retval 0 WDT time-out interrupt did not occur
- * @retval 1 WDT time-out interrupt occurred
- *
- * @details This macro indicates WDT time-out interrupt occurred or not.
- */
-#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1 : 0)
-
-/**
- * @brief Get WDT Time-out Wake-up Flag
- *
- * @param None
- *
- * @retval 0 WDT time-out interrupt does not cause CPU wake-up
- * @retval 1 WDT time-out interrupt event cause CPU wake-up
- *
- * @details This macro indicates WDT time-out interrupt event has waked up system or not.
- */
-#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1 : 0)
-
-/**
- * @brief Reset WDT Counter
- *
- * @param None
- *
- * @return None
- *
- * @details This macro is used to reset the internal 18-bit WDT up counter value.
- * @note If WDT is activated and time-out reset system function is enabled also, user should \n
- * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
- * reset system before the WDT time-out reset delay period expires.
- */
-#define WDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)
-
-/**
- * @brief Stop WDT Counting
- *
- * @param None
- *
- * @return None
- *
- * @details This function will stop WDT counting and disable WDT module.
- */
-static __INLINE void WDT_Close(void)
-{
- WDT->CTL = 0;
- return;
-}
-
-/**
- * @brief Enable WDT Time-out Interrupt
- *
- * @param None
- *
- * @return None
- *
- * @details This function will enable the WDT time-out interrupt function.
- */
-static __INLINE void WDT_EnableInt(void)
-{
- WDT->CTL |= WDT_CTL_INTEN_Msk;
- return;
-}
-
-/**
- * @brief Disable WDT Time-out Interrupt
- *
- * @param None
- *
- * @return None
- *
- * @details This function will disable the WDT time-out interrupt function.
- */
-static __INLINE void WDT_DisableInt(void)
-{
- // Do not touch another write 1 clear bits
- WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
- return;
-}
-
-void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
-
-/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group WDT_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__WDT_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wwdt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,71 +0,0 @@
-/**************************************************************************//**
- * @file wwdt.c
- * @version V3.00
- * $Revision: 4 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series WWDT driver source file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "M451Series.h"
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup WWDT_Driver WWDT Driver
- @{
-*/
-
-/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
- @{
-*/
-
-/**
- * @brief Open WWDT and start counting
- *
- * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are:
- * - \ref WWDT_PRESCALER_1
- * - \ref WWDT_PRESCALER_2
- * - \ref WWDT_PRESCALER_4
- * - \ref WWDT_PRESCALER_8
- * - \ref WWDT_PRESCALER_16
- * - \ref WWDT_PRESCALER_32
- * - \ref WWDT_PRESCALER_64
- * - \ref WWDT_PRESCALER_128
- * - \ref WWDT_PRESCALER_192
- * - \ref WWDT_PRESCALER_256
- * - \ref WWDT_PRESCALER_384
- * - \ref WWDT_PRESCALER_512
- * - \ref WWDT_PRESCALER_768
- * - \ref WWDT_PRESCALER_1024
- * - \ref WWDT_PRESCALER_1536
- * - \ref WWDT_PRESCALER_2048
- * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F.
- * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.
- *
- * @return None
- *
- * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value.
- * @note This WWDT_CTL register can be write only one time after chip is powered on or reset.
- */
-void WWDT_Open(uint32_t u32PreScale,
- uint32_t u32CmpValue,
- uint32_t u32EnableInt)
-{
- WWDT->CTL = u32PreScale |
- (u32CmpValue << WWDT_CTL_CMPDAT_Pos) |
- ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0) |
- WWDT_CTL_WWDTEN_Msk;
- return;
-}
-
-/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group WWDT_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_wwdt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,148 +0,0 @@
-/**************************************************************************//**
- * @file wwdt.h
- * @version V3.00
- * $Revision: 7 $
- * $Date: 15/08/11 10:26a $
- * @brief M451 series WWDT driver header file
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __WWDT_H__
-#define __WWDT_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup Standard_Driver Standard Driver
- @{
-*/
-
-/** @addtogroup WWDT_Driver WWDT Driver
- @{
-*/
-
-/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* WWDT Prescale Period Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
-#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* WWDT Reload Counter Keyword Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter */
-
-/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
- @{
-*/
-
-/**
- * @brief Clear WWDT Reset System Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro is used to clear WWDT time-out reset system flag.
- */
-#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTIF_Msk) | WWDT_STATUS_WWDTRF_Msk)
-
-/**
- * @brief Clear WWDT Compared Match Interrupt Flag
- *
- * @param None
- *
- * @return None
- *
- * @details This macro is used to clear WWDT compared match interrupt flag.
- */
-#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = (WWDT->STATUS & ~WWDT_STATUS_WWDTRF_Msk) | WWDT_STATUS_WWDTIF_Msk)
-
-/**
- * @brief Get WWDT Reset System Flag
- *
- * @param None
- *
- * @retval 0 WWDT time-out reset system did not occur
- * @retval 1 WWDT time-out reset system occurred
- *
- * @details This macro is used to indicate system has been reset by WWDT time-out reset or not.
- */
-#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
-
-/**
- * @brief Get WWDT Compared Match Interrupt Flag
- *
- * @param None
- *
- * @retval 0 WWDT compare match interrupt did not occur
- * @retval 1 WWDT compare match interrupt occurred
- *
- * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.
- */
-#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
-
-/**
- * @brief Get WWDT Counter
- *
- * @param None
- *
- * @return WWDT Counter Value
- *
- * @details This macro reflects the current WWDT counter value.
- */
-#define WWDT_GET_COUNTER() (WWDT->CNT)
-
-/**
- * @brief Reload WWDT Counter
- *
- * @param None
- *
- * @return None
- *
- * @details This macro is used to reload the WWDT counter value to 0x3F.
- * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
- * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
- * WWDT reset signal will generate immediately to reset system.
- */
-#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
-
-void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
-
-/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group WWDT_Driver */
-
-/*@}*/ /* end of group Standard_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__WWDT_H__
-
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-
-LR_IROM1 0x00000000 {
- ER_IROM1 0x00000000 { ; load address = execution address
- *(RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
-
- ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
- }
-
- ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 64)) { ; Reserve for vectors
- }
-
- RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
- .ANY (+RW +ZI)
- }
-
- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
- }
-}
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000) ; 256 KB APROM
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000) ; 32 KB SRAM
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/sys.cpp Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
-extern char Image$$ARM_LIB_HEAP$$Base[];
-extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-
- struct __initial_stackheap r;
- r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
- r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/M453.sct Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-
-LR_IROM1 0x00000000 {
- ER_IROM1 0x00000000 { ; load address = execution address
- *(RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
-
- ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
- }
-
- ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 64)) { ; Reserve for vectors
- }
-
- RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
- .ANY (+RW +ZI)
- }
-
- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
- }
-}
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00040000) ; 256 KB APROM
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000) ; 32 KB SRAM
-
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
-extern char Image$$ARM_LIB_HEAP$$Base[];
-extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-
- struct __initial_stackheap r;
- r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
- r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/M453.ld Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,255 +0,0 @@
-/*
- * Nuvoton M453 GCC linker script file
- */
-
-StackSize = 0x800;
-
-MEMORY
-{
- VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
- FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
- RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 - 0x00000000
-}
-
-/**
- * Must match cmsis_nvic.h
- */
-__vector_size = 4 * (16 + 64);
-
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .isr_vector :
- {
- __vector_table = .;
- KEEP(*(.vector_table))
- . = ALIGN(4);
- } > VECTORS
-
- /* ensure that uvisor bss is at the beginning of memory */
- .uvisor.bss (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
- . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
- __uvisor_bss_end = .;
- } > RAM_INTERN
-
- .text :
- {
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
-
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- .ARM.exidx :
- {
- __exidx_start = .;
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- __exidx_end = .;
- } > FLASH
-
- /* .stack section doesn't contains any symbols. It is only
- * used for linker to reserve space for the main stack section
- * WARNING: .stack should come immediately after the last secure memory
- * section. This provides stack overflow detection. */
- .stack (NOLOAD):
- {
- __StackLimit = .;
- *(.stack*);
- . += StackSize - (. - __StackLimit);
- } > RAM_INTERN
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ADDR(.stack) + SIZEOF(.stack);
- __StackLimit = ADDR(.stack);
- PROVIDE(__stack = __StackTop);
-
- /* Relocate vector table in SRAM */
- .isr_vector.reloc (NOLOAD) :
- {
- . = ALIGN(1 << LOG2CEIL(__vector_size));
- PROVIDE(__start_vector_table__ = .);
- . += __vector_size;
- PROVIDE(__end_vector_table__ = .);
- } > RAM_INTERN
-
- .data :
- {
- PROVIDE( __etext = LOADADDR(.data) );
-
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- /* All data end */
- . = ALIGN(32);
- __data_end__ = .;
-
- } >RAM_INTERN AT>FLASH
-
- /* uvisor configuration data */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* pointers to uvisor secure boxes configuration tables */
- /* note: no further alignment here, we need to have the exact list of pointers */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* the following symbols are kept for backward compatibility and will be soon
- * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
- * will need to use uVisor 0.8.x or above, or the security assertions will halt the
- * system */
- /************************/
- __uvisor_data_src = .;
- __uvisor_data_start = .;
- __uvisor_data_end = .;
- /************************/
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } >FLASH
-
- .uninitialized (NOLOAD):
- {
- . = ALIGN(32);
- __uninitialized_start = .;
- *(.uninitialized)
- KEEP(*(.keep.uninitialized))
- . = ALIGN(32);
- __uninitialized_end = .;
- } > RAM_INTERN
-
- .bss (NOLOAD):
- {
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- __bss_end__ = .;
- } > RAM_INTERN
-
- .heap (NOLOAD):
- {
- __end__ = .;
- end = __end__;
- *(.heap*);
- . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
- __HeapLimit = .;
- } > RAM_INTERN
- PROVIDE(__heap_size = SIZEOF(.heap));
- PROVIDE(__mbed_sbrk_start = ADDR(.heap));
- PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
-
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM_INTERN);
- __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_GCC_ARM/retarget.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,37 +0,0 @@
-/******************************************************************************
- * @file startup_NUC472_442.c
- * @version V0.10
- * $Revision: 11 $
- * $Date: 15/09/02 10:02a $
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for NUC472/442 MCU
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "M451Series.h"
-#include <errno.h>
-
-extern uint32_t __mbed_sbrk_start;
-extern uint32_t __mbed_krbs_start;
-
-/**
- * The default implementation of _sbrk() (in common/retarget.cpp) for GCC_ARM requires one-region model (heap and stack share one region), which doesn't
- * fit two-region model (heap and stack are two distinct regions), for example, NUMAKER-PFM-NUC472 locates heap on external SRAM. Define __wrap__sbrk() to
- * override the default _sbrk(). It is expected to get called through gcc hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
- */
-void *__wrap__sbrk(int incr)
-{
- static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
- uint32_t heap_ind_old = heap_ind;
- uint32_t heap_ind_new = (heap_ind_old + incr + 7) & ~7;
-
- if (heap_ind_new > &__mbed_krbs_start) {
- errno = ENOMEM;
- return (void *) -1;
- }
-
- heap_ind = heap_ind_new;
-
- return (void *) heap_ind_old;
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_IAR/M453.icf Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00040000;
-define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_IRAM_end__ = 0x20008000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x800;
-define symbol __ICFEDIT_size_heap__ = 0x4000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
-define block IRAMVEC with alignment = 1024, size = 4 * (16 + 64) { };
-
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place at start of IRAM_region { block CSTACK };
-place in IRAM_region { block IRAMVEC };
-place in IRAM_region { readwrite };
-place in IRAM_region { block HEAP };
\ No newline at end of file
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis.h Thu Dec 15 11:48:27 2016 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "M451Series.h" -#include "cmsis_nvic.h" - -// Support linker-generated symbol as start of relocated vector table. -#if defined(__CC_ARM) -extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; -#elif defined(__ICCARM__) - -#elif defined(__GNUC__) -extern uint32_t __start_vector_table__; -#endif - - -#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,39 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "cmsis_nvic.h"
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *) SCB->VTOR;
- uint32_t i;
-
- /* Copy and switch to dynamic vectors if the first time called */
- if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
- uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
- vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
- for (i = 0; i < NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
- }
- SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
- }
- vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *) SCB->VTOR;
- return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/cmsis_nvic.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#define NVIC_USER_IRQ_OFFSET 16
-#define NVIC_USER_IRQ_NUMBER 64
-#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
-
-#if defined(__CC_ARM)
-# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
-#elif defined(__ICCARM__)
-# pragma section = "IRAMVEC"
-# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
-#elif defined(__GNUC__)
-# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
-#endif
-
-
-#define NVIC_FLASH_VECTOR_ADDRESS 0
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Set the ISR for IRQn
- *
- * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
- * the first time this function is called
- * @param[in] IRQn The Interrupt Request number for which a vector will be registered
- * @param[in] vector The ISR vector to register for IRQn
- */
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-
-/** Get the ISR registered for IRQn
- *
- * Reads the Interrupt Service Routine currently registered for IRQn
- * @param[in] IRQn The Interrupt Request number the vector of which will be read
- * @return Returns the ISR registered for IRQn
- */
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,334 +0,0 @@
-/******************************************************************************
- * @file startup_M451Series.c
- * @version V0.10
- * $Revision: 11 $
- * $Date: 15/09/02 10:02a $
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "M451Series.h"
-
-/* Suppress warning messages */
-#if defined(__CC_ARM)
-// Suppress warning message: extended constant initialiser used
-#pragma diag_suppress 1296
-#elif defined(__ICCARM__)
-#elif defined(__GNUC__)
-#endif
-
-/* Macro Definitions */
-#if defined(__CC_ARM)
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias(#f)))
-
-#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
-void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
-
-#elif defined(__ICCARM__)
-//#define STRINGIFY(x) #x
-//#define _STRINGIFY(x) STRINGIFY(x)
-#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
-void FUN(void); \
-_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)))
-#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)
-#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS
-
-#elif defined(__GNUC__)
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias(#f)))
-
-#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
-void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
-
-#endif
-
-
-/* Initialize segments */
-#if defined(__CC_ARM)
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
-extern void __main(void);
-#elif defined(__ICCARM__)
-void __iar_program_start(void);
-#elif defined(__GNUC__)
-extern uint32_t __StackTop;
-extern uint32_t __etext;
-extern uint32_t __data_start__;
-extern uint32_t __data_end__;
-extern uint32_t __bss_start__;
-extern uint32_t __bss_end__;
-
-extern void uvisor_init(void);
-//#if defined(TOOLCHAIN_GCC_ARM)
-//extern void _start(void);
-//#endif
-extern void software_init_hook(void) __attribute__((weak));
-extern void __libc_init_array(void);
-extern int main(void);
-#endif
-
-/* Default empty handler */
-void Default_Handler(void);
-
-/* Reset handler */
-void Reset_Handler(void);
-
-/* Cortex-M4 core handlers */
-WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(MemManage_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(BusFault_Handler , Default_Handler)
-WEAK_ALIAS_FUNC(UsageFault_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(DebugMon_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
-
-/* Peripherals handlers */
-WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection
-WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC
-WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power down wake up
-WEAK_ALIAS_FUNC(RAMPE_IRQHandler, Default_Handler) // 3: RAM parity error
-WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler) // 4: Clock detection fail
- // 5: Reserved
-WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock
-WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler) // 7: Tamper detection
-WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler) // 8: Watchdog timer
-WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler) // 9: Window watchdog timer
-WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler) // 10: External Input 0
-WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler) // 11: External Input 1
-WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler) // 12: External Input 2
-WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler) // 13: External Input 3
-WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler) // 14: External Input 4
-WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler) // 15: External Input 5
-WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler) // 16: GPIO Port A
-WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler) // 17: GPIO Port B
-WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C
-WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D
-WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E
-WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F
-WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 22: SPI0
-WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler) // 23: SPI1
-WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24:
-WEAK_ALIAS_FUNC(PWM0P0_IRQHandler, Default_Handler) // 25:
-WEAK_ALIAS_FUNC(PWM0P1_IRQHandler, Default_Handler) // 26:
-WEAK_ALIAS_FUNC(PWM0P2_IRQHandler, Default_Handler) // 27:
-WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28:
-WEAK_ALIAS_FUNC(PWM1P0_IRQHandler, Default_Handler) // 29:
-WEAK_ALIAS_FUNC(PWM1P1_IRQHandler, Default_Handler) // 30:
-WEAK_ALIAS_FUNC(PWM1P2_IRQHandler, Default_Handler) // 31:
-WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0
-WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1
-WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2
-WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler) // 35: Timer 3
-WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0
-WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1
-WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0
-WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1
-WEAK_ALIAS_FUNC(PDMA_IRQHandler, Default_Handler) // 40: Peripheral DMA
-WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC
-WEAK_ALIAS_FUNC(ADC00_IRQHandler, Default_Handler) // 42: ADC0 interrupt source 0
-WEAK_ALIAS_FUNC(ADC01_IRQHandler, Default_Handler) // 43: ADC0 interrupt source 1
-WEAK_ALIAS_FUNC(ACMP01_IRQHandler, Default_Handler) // 44: ACMP0 and ACMP1
- // 45: Reserved
-WEAK_ALIAS_FUNC(ADC02_IRQHandler, Default_Handler) // 46: ADC0 interrupt source 2
-WEAK_ALIAS_FUNC(ADC03_IRQHandler, Default_Handler) // 47: ADC0 interrupt source 3
-WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler) // 48: UART2
-WEAK_ALIAS_FUNC(UART3_IRQHandler, Default_Handler) // 49: UART3
- // 50: Reserved
-WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler) // 51: SPI2
- // 52: Reserved
-WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler) // 53: USB device
-WEAK_ALIAS_FUNC(USBH_IRQHandler, Default_Handler) // 54: USB host
-WEAK_ALIAS_FUNC(USBOTG_IRQHandler, Default_Handler) // 55: USB OTG
-WEAK_ALIAS_FUNC(CAN0_IRQHandler, Default_Handler) // 56: CAN0
- // 57: Reserved
-WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler) // 58:
- // 59: Reserved.
- // 60:
- // 61:
- // 62:
-WEAK_ALIAS_FUNC(TK_IRQHandler, Default_Handler) // 63:
-
-/* Vector table */
-#if defined(__CC_ARM)
-__attribute__ ((section("RESET")))
-const uint32_t __vector_handlers[] = {
-#elif defined(__ICCARM__)
-extern uint32_t CSTACK$$Limit;
-const uint32_t __vector_table[] @ ".intvec" = {
-#elif defined(__GNUC__)
-__attribute__ ((section(".vector_table")))
-const uint32_t __vector_handlers[] = {
-#endif
-
- /* Configure Initial Stack Pointer, using linker-generated symbols */
-#if defined(__CC_ARM)
- (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
-#elif defined(__ICCARM__)
- //(uint32_t) __sfe("CSTACK"),
- (uint32_t) &CSTACK$$Limit,
-#elif defined(__GNUC__)
- (uint32_t) &__StackTop,
-#endif
-
- (uint32_t) Reset_Handler, // Reset Handler
- (uint32_t) NMI_Handler, // NMI Handler
- (uint32_t) HardFault_Handler, // Hard Fault Handler
- (uint32_t) MemManage_Handler, // MPU Fault Handler
- (uint32_t) BusFault_Handler, // Bus Fault Handler
- (uint32_t) UsageFault_Handler, // Usage Fault Handler
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- (uint32_t) SVC_Handler, // SVCall Handler
- (uint32_t) DebugMon_Handler, // Debug Monitor Handler
- 0, // Reserved
- (uint32_t) PendSV_Handler, // PendSV Handler
- (uint32_t) SysTick_Handler, // SysTick Handler
-
- /* External Interrupts */
- (uint32_t) BOD_IRQHandler, // 0: Brown Out detection
- (uint32_t) IRC_IRQHandler, // 1: Internal RC
- (uint32_t) PWRWU_IRQHandler, // 2: Power down wake up
- (uint32_t) RAMPE_IRQHandler, // 3: RAM parity error
- (uint32_t) CLKFAIL_IRQHandler, // 4: Clock detection fail
- (uint32_t) Default_Handler, // 5: Reserved
- (uint32_t) RTC_IRQHandler, // 6: Real Time Clock
- (uint32_t) TAMPER_IRQHandler, // 7: Tamper detection
- (uint32_t) WDT_IRQHandler, // 8: Watchdog timer
- (uint32_t) WWDT_IRQHandler, // 9: Window watchdog timer
- (uint32_t) EINT0_IRQHandler, // 10: External Input 0
- (uint32_t) EINT1_IRQHandler, // 11: External Input 1
- (uint32_t) EINT2_IRQHandler, // 12: External Input 2
- (uint32_t) EINT3_IRQHandler, // 13: External Input 3
- (uint32_t) EINT4_IRQHandler, // 14: External Input 4
- (uint32_t) EINT5_IRQHandler, // 15: External Input 5
- (uint32_t) GPA_IRQHandler, // 16: GPIO Port A
- (uint32_t) GPB_IRQHandler, // 17: GPIO Port B
- (uint32_t) GPC_IRQHandler, // 18: GPIO Port C
- (uint32_t) GPD_IRQHandler, // 19: GPIO Port D
- (uint32_t) GPE_IRQHandler, // 20: GPIO Port E
- (uint32_t) GPF_IRQHandler, // 21: GPIO Port F
- (uint32_t) SPI0_IRQHandler, // 22: SPI0
- (uint32_t) SPI1_IRQHandler, // 23: SPI1
- (uint32_t) BRAKE0_IRQHandler, // 24:
- (uint32_t) PWM0P0_IRQHandler, // 25:
- (uint32_t) PWM0P1_IRQHandler, // 26:
- (uint32_t) PWM0P2_IRQHandler, // 27:
- (uint32_t) BRAKE1_IRQHandler, // 28:
- (uint32_t) PWM1P0_IRQHandler, // 29:
- (uint32_t) PWM1P1_IRQHandler, // 30:
- (uint32_t) PWM1P2_IRQHandler, // 31:
- (uint32_t) TMR0_IRQHandler, // 32: Timer 0
- (uint32_t) TMR1_IRQHandler, // 33: Timer 1
- (uint32_t) TMR2_IRQHandler, // 34: Timer 2
- (uint32_t) TMR3_IRQHandler, // 35: Timer 3
- (uint32_t) UART0_IRQHandler, // 36: UART0
- (uint32_t) UART1_IRQHandler, // 37: UART1
- (uint32_t) I2C0_IRQHandler, // 38: I2C0
- (uint32_t) I2C1_IRQHandler, // 39: I2C1
- (uint32_t) PDMA_IRQHandler, // 40: Peripheral DMA
- (uint32_t) DAC_IRQHandler, // 41: DAC
- (uint32_t) ADC00_IRQHandler, // 42: ADC0 interrupt source 0
- (uint32_t) ADC01_IRQHandler, // 43: ADC0 interrupt source 1
- (uint32_t) ACMP01_IRQHandler, // 44: ACMP0 and ACMP1
- (uint32_t) Default_Handler, // 45: Reserved
- (uint32_t) ADC02_IRQHandler, // 46: ADC0 interrupt source 2
- (uint32_t) ADC03_IRQHandler, // 47: ADC0 interrupt source 3
- (uint32_t) UART2_IRQHandler, // 48: UART2
- (uint32_t) UART3_IRQHandler, // 49: UART3
- (uint32_t) Default_Handler, // 50: Reserved
- (uint32_t) SPI2_IRQHandler, // 51: SPI2
- (uint32_t) Default_Handler, // 52: Reserved
- (uint32_t) USBD_IRQHandler, // 53: USB device
- (uint32_t) USBH_IRQHandler, // 54: USB host
- (uint32_t) USBOTG_IRQHandler, // 55: USB OTG
- (uint32_t) CAN0_IRQHandler, // 56: CAN0
- (uint32_t) Default_Handler, // 57: Reserved
- (uint32_t) SC0_IRQHandler, // 58:
- (uint32_t) Default_Handler, // 59: Reserved.
- (uint32_t) Default_Handler, // 60:
- (uint32_t) Default_Handler, // 61:
- (uint32_t) Default_Handler, // 62:
- (uint32_t) TK_IRQHandler, // 63:
-};
-
-/**
- * \brief This is the code that gets called on processor reset.
- */
-void Reset_Handler(void)
-{
- /* Disable register write-protection function */
- SYS_UnlockReg();
-
- /* Disable Power-on Reset function */
- SYS_DISABLE_POR();
-
- /* HXT Crystal Type Select: INV */
- CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
-
- /* Enable register write-protection function */
- SYS_LockReg();
-
- /**
- * Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
- */
- SystemInit();
-
-#if defined(__CC_ARM)
- __main();
-
-#elif defined(__ICCARM__)
- __iar_program_start();
-
-#elif defined(__GNUC__)
- uint32_t *src_ind = (uint32_t *) &__etext;
- uint32_t *dst_ind = (uint32_t *) &__data_start__;
- uint32_t *dst_end = (uint32_t *) &__data_end__;
-
- /* Move .data section from ROM to RAM */
- if (src_ind != dst_ind) {
- for (; dst_ind < dst_end;) {
- *dst_ind ++ = *src_ind ++;
- }
- }
-
- /* Initialize .bss section to zero */
- dst_ind = (uint32_t *) &__bss_start__;
- dst_end = (uint32_t *) &__bss_end__;
- if (dst_ind != dst_end) {
- for (; dst_ind < dst_end;) {
- *dst_ind ++ = 0;
- }
- }
-
- //uvisor_init();
-
- if (software_init_hook) {
- /**
- * Give control to the RTOS via software_init_hook() which will also call __libc_init_array().
- * Assume software_init_hook() is defined in libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h.
- */
- software_init_hook();
- }
- else {
- __libc_init_array();
- main();
- }
-#endif
-
- /* Infinite loop */
- while (1);
-}
-
-/**
- * \brief Default interrupt handler for unused IRQs.
- */
-void Default_Handler(void)
-{
- while (1);
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,111 +0,0 @@
-/******************************************************************************
- * @file system_M451Series.c
- * @version V0.10
- * $Revision: 11 $
- * $Date: 15/09/02 10:02a $
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M451 Series MCU
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "M451Series.h"
-
-
-/*----------------------------------------------------------------------------
- DEFINES
- *----------------------------------------------------------------------------*/
-
-
-/*----------------------------------------------------------------------------
- Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
-uint32_t CyclesPerUs = (__HSI / 1000000); /* Cycles per micro second */
-uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
-uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC};
-
-/*----------------------------------------------------------------------------
- Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
-{
-#if 1
- uint32_t u32Freq, u32ClkSrc;
- uint32_t u32HclkDiv;
-
- /* Update PLL Clock */
- PllClock = CLK_GetPLLClockFreq();
-
- u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
-
- if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
- {
- /* Use PLL clock */
- u32Freq = PllClock;
- }
- else
- {
- /* Use the clock sources directly */
- u32Freq = gau32ClkSrcTbl[u32ClkSrc];
- }
-
- u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
-
- /* Update System Core Clock */
- SystemCoreClock = u32Freq / u32HclkDiv;
-
-
- //if(SystemCoreClock == 0)
- // __BKPT(0);
-
- CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
-#endif
-}
-
-/**
- * Initialize the system
- *
- * @param None
- * @return None
- *
- * @brief Setup the microcontroller system.
- * Initialize the System.
- */
-void SystemInit(void)
-{
- /* ToDo: add code to initialize the system
- do not use global variables because this function is called before
- reaching pre-main. RW section maybe overwritten afterwards. */
-
- SYS_UnlockReg();
- /* One-time POR18 */
- if((SYS->PDID >> 12) == 0x945)
- {
- M32(GCR_BASE+0x14) |= BIT7;
- }
- /* Force to use INV type with HXT */
- CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
- SYS_LockReg();
-
-
-#if 0
- // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
- nu_ebi_init();
-#endif
-
- /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10 * 2) | /* set CP10 Full Access */
- (3UL << 11 * 2)); /* set CP11 Full Access */
-#endif
-
-}
-
-#if 0
-void nu_ebi_init(void)
-{
- // TO BE CONTINUED
-}
-#endif
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/******************************************************************************
- * @file system_M451Series.h
- * @version V0.10
- * $Revision: 7 $
- * $Date: 15/09/02 10:02a $
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M451 Series MCU
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#ifndef __SYSTEM_M451SERIES_H__
-#define __SYSTEM_M451SERIES_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Macro Definition */
-/*---------------------------------------------------------------------------------------------------------*/
-#ifndef DEBUG_PORT
-# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
-#endif
-
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-
-#define __HSI (12000000UL) /*!< PLL default output is 72MHz */
-#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
-#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
-#define __HIRC (22118400UL) /*!< Internal 22M RC Oscillator Frequency */
-#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
-#define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */
-
-
-#define __SYSTEM_CLOCK (1*__HXT)
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
-extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
-
-
-/**
- * Initialize the system
- *
- * @param None
- * @return None
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit(void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param None
- * @return None
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_M451SERIES_H__ */
-/*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_M451/dma.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_DMA_H
-#define MBED_DMA_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DMA_CAP_NONE (0 << 0)
-
-#define DMA_EVENT_ABORT (1 << 0)
-#define DMA_EVENT_TRANSFER_DONE (1 << 1)
-#define DMA_EVENT_TIMEOUT (1 << 2)
-#define DMA_EVENT_ALL (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT)
-#define DMA_EVENT_MASK DMA_EVENT_ALL
-
-void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,178 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "dma_api.h"
-#include "string.h"
-#include "cmsis.h"
-#include "mbed_assert.h"
-#include "PeripheralNames.h"
-#include "nu_modutil.h"
-#include "nu_bitutil.h"
-#include "dma.h"
-
-struct nu_dma_chn_s {
- void (*handler)(uint32_t, uint32_t);
- uint32_t id;
- uint32_t event;
-};
-
-static int dma_inited = 0;
-static uint32_t dma_chn_mask = 0;
-static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX];
-
-static void pdma_vec(void);
-static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec};
-
-
-void dma_init(void)
-{
- if (dma_inited) {
- return;
- }
-
- dma_inited = 1;
- dma_chn_mask = 0;
- memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
-
- // Reset this module
- SYS_ResetModule(dma_modinit.rsetidx);
-
- // Enable IP clock
- CLK_EnableModuleClock(dma_modinit.clkidx);
-
- PDMA_Open(0);
-
- NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
- NVIC_EnableIRQ(dma_modinit.irq_n);
-}
-
-int dma_channel_allocate(uint32_t capabilities)
-{
- if (! dma_inited) {
- dma_init();
- }
-
-#if 1
- int i = nu_cto(dma_chn_mask);
- if (i != 32) {
- dma_chn_mask |= 1 << i;
- memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
- return i;
- }
-#else
- int i;
-
- for (i = 0; i < PDMA_CH_MAX; i ++) {
- if ((dma_chn_mask & (1 << i)) == 0) {
- // Channel available
- dma_chn_mask |= 1 << i;
- memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
- return i;
- }
- }
-#endif
-
- // No channel available
- return DMA_ERROR_OUT_OF_CHANNELS;
-}
-
-int dma_channel_free(int channelid)
-{
- if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_chn_mask &= ~(1 << channelid);
- }
-
- return 0;
-}
-
-void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
-{
- MBED_ASSERT(dma_chn_mask & (1 << channelid));
-
- dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler;
- dma_chn_arr[channelid].id = id;
- dma_chn_arr[channelid].event = event;
-
- // Set interrupt vector if someone has removed it.
- NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
- NVIC_EnableIRQ(dma_modinit.irq_n);
-}
-
-static void pdma_vec(void)
-{
- uint32_t intsts = PDMA_GET_INT_STATUS();
-
- // Abort
- if (intsts & PDMA_INTSTS_ABTIF_Msk) {
- uint32_t abtsts = PDMA_GET_ABORT_STS();
- // Clear all Abort flags
- PDMA_CLR_ABORT_FLAG(abtsts);
-
- while (abtsts) {
- int chn_id = nu_ctz(abtsts);
- if (dma_chn_mask & (1 << chn_id)) {
- struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
- if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
- dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
- }
- }
- abtsts &= ~(1 << chn_id);
- }
- }
-
- // Transfer done
- if (intsts & PDMA_INTSTS_TDIF_Msk) {
- uint32_t tdsts = PDMA_GET_TD_STS();
- // Clear all transfer done flags
- PDMA_CLR_TD_FLAG(tdsts);
-
- while (tdsts) {
- int chn_id = nu_ctz(tdsts);
- if (dma_chn_mask & (1 << chn_id)) {
- struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
- if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
- dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
- }
- }
- tdsts &= ~(1 << chn_id);
- }
- }
-
- // Table empty
- if (intsts & PDMA_INTSTS_TEIF_Msk) {
- uint32_t scatsts = PDMA_GET_EMPTY_STS();
- // Clear all table empty flags
- PDMA_CLR_EMPTY_FLAG(scatsts);
- }
-
- // Timeout
- uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk;
- if (reqto) {
- // Clear all Timeout flags
- PDMA->INTSTS = reqto;
-
- while (reqto) {
- int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFn_Pos;
- if (dma_chn_mask & (1 << chn_id)) {
- struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
- if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
- dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
- }
- }
- reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFn_Pos));
- }
- }
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "gpio_api.h"
-#include "mbed_assert.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-uint32_t gpio_set(PinName pin)
-{
- if (pin == (PinName) NC) {
- return 0;
- }
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
-
-#if 1
- pin_function(pin, 0 << NU_MFP_POS(pin_index));
-#else
- pinmap_pinout(pin, PinMap_GPIO);
-#endif
-
- return (uint32_t)(1 << pin_index); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
-
- if (obj->pin == (PinName) NC) {
- return;
- }
-
- obj->mask = gpio_set(pin);
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- if (obj->pin == (PinName) NC) {
- return;
- }
-
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- if (obj->pin == (PinName) NC) {
- return;
- }
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
- switch (direction) {
- case PIN_INPUT:
- mode_intern = GPIO_MODE_INPUT;
- break;
-
- case PIN_OUTPUT:
- mode_intern = GPIO_MODE_OUTPUT;
- break;
-
- default:
- return;
- }
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,226 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "gpio_irq_api.h"
-
-#if DEVICE_INTERRUPTIN
-
-#include "gpio_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_bitutil.h"
-
-#define NU_MAX_PIN_PER_PORT 16
-
-struct nu_gpio_irq_var {
- gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
- IRQn_Type irq_n;
- void (*vec)(void);
-};
-
-static void gpio_irq_0_vec(void);
-static void gpio_irq_1_vec(void);
-static void gpio_irq_2_vec(void);
-static void gpio_irq_3_vec(void);
-static void gpio_irq_4_vec(void);
-static void gpio_irq_5_vec(void);
-static void gpio_irq(struct nu_gpio_irq_var *var);
-
-//EINT0_IRQn
-static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
- {{NULL}, GPA_IRQn, gpio_irq_0_vec},
- {{NULL}, GPB_IRQn, gpio_irq_1_vec},
- {{NULL}, GPC_IRQn, gpio_irq_2_vec},
- {{NULL}, GPD_IRQn, gpio_irq_3_vec},
- {{NULL}, GPE_IRQn, gpio_irq_4_vec},
- {{NULL}, GPF_IRQn, gpio_irq_5_vec}
-};
-
-#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
-
-#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
-#define M451_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_ENABLE
-#else
-#define M451_GPIO_IRQ_DEBOUNCE_ENABLE 0
-#endif
-
-#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
-#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
-#else
-#define M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
-#endif
-
-#ifdef MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
-#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
-#else
-#define M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
-#endif
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
-{
- if (pin == NC) {
- return -1;
- }
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(pin);
- if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
- return -1;
- }
-
- obj->pin = pin;
- obj->irq_handler = (uint32_t) handler;
- obj->irq_id = id;
-
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
- //gpio_set(pin);
-
-#if M451_GPIO_IRQ_DEBOUNCE_ENABLE
- // Configure de-bounce clock source and sampling cycle time
- GPIO_SET_DEBOUNCE_TIME(M451_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, M451_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
- GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
-#else
- GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
-#endif
-
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- var->obj_arr[pin_index] = obj;
-
- // NOTE: InterruptIn requires IRQ enabled by default.
- gpio_irq_enable(obj);
-
- return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj)
-{
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- NVIC_DisableIRQ(var->irq_n);
- NU_PORT_BASE(port_index)->INTEN = 0;
-
- MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
- var->obj_arr[pin_index] = NULL;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
-{
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- switch (event) {
- case IRQ_RISE:
- if (enable) {
- GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
- }
- else {
- gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
- }
- break;
-
- case IRQ_FALL:
- if (enable) {
- GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
- }
- else {
- gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
- }
- break;
- }
-}
-
-void gpio_irq_enable(gpio_irq_t *obj)
-{
- //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
- NVIC_EnableIRQ(var->irq_n);
-}
-
-void gpio_irq_disable(gpio_irq_t *obj)
-{
- //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- NVIC_DisableIRQ(var->irq_n);
-}
-
-static void gpio_irq_0_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 0);
-}
-static void gpio_irq_1_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 1);
-}
-static void gpio_irq_2_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 2);
-}
-static void gpio_irq_3_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 3);
-}
-static void gpio_irq_4_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 4);
-}
-static void gpio_irq_5_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 5);
-}
-
-static void gpio_irq(struct nu_gpio_irq_var *var)
-{
- uint32_t port_index = var->irq_n - GPA_IRQn;
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t intsrc = gpio_base->INTSRC;
- uint32_t inten = gpio_base->INTEN;
- while (intsrc) {
- int pin_index = nu_ctz(intsrc);
- gpio_irq_t *obj = var->obj_arr[pin_index];
- if (inten & (GPIO_INT_RISING << pin_index)) {
- if (GPIO_PIN_DATA(port_index, pin_index)) {
- if (obj->irq_handler) {
- ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
- }
- }
- }
-
- if (inten & (GPIO_INT_FALLING << pin_index)) {
- if (! GPIO_PIN_DATA(port_index, pin_index)) {
- if (obj->irq_handler) {
- ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
- }
- }
- }
-
- intsrc &= ~(1 << pin_index);
- }
- // Clear all interrupt flags
- gpio_base->INTSRC = gpio_base->INTSRC;
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_object.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
-
- GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0;
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
-
- return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1017 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "i2c_api.h"
-
-#if DEVICE_I2C
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "nu_bitutil.h"
-#include "critical.h"
-
-#define NU_I2C_DEBUG 0
-
-#if NU_I2C_DEBUG
-struct i2c_s MY_I2C;
-struct i2c_s MY_I2C_2;
-char MY_I2C_STATUS[64];
-int MY_I2C_STATUS_POS = 0;
-uint32_t MY_I2C_TIMEOUT;
-uint32_t MY_I2C_ELAPSED;
-uint32_t MY_I2C_T1;
-uint32_t MY_I2C_T2;
-#endif
-
-struct nu_i2c_var {
- i2c_t * obj;
- void (*vec)(void);
-};
-
-static void i2c0_vec(void);
-static void i2c1_vec(void);
-static void i2c_irq(i2c_t *obj);
-static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
-
-static struct nu_i2c_var i2c0_var = {
- .obj = NULL,
- .vec = i2c0_vec,
-};
-static struct nu_i2c_var i2c1_var = {
- .obj = NULL,
- .vec = i2c1_vec,
-};
-
-static uint32_t i2c_modinit_mask = 0;
-
-static const struct nu_modinit_s i2c_modinit_tab[] = {
- {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
- {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
-static int i2c_do_write(i2c_t *obj, char data, int naklastdata);
-static int i2c_do_read(i2c_t *obj, char *data, int naklastdata);
-static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
-#define NU_I2C_TIMEOUT_STAT_INT 500000
-#define NU_I2C_TIMEOUT_STOP 500000
-static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
-static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
-//static int i2c_is_stat_int(i2c_t *obj);
-//static int i2c_is_stop_det(i2c_t *obj);
-static int i2c_is_trsn_done(i2c_t *obj);
-static int i2c_is_tran_started(i2c_t *obj);
-static int i2c_addr2data(int address, int read);
-#if DEVICE_I2CSLAVE
-// Convert mbed address to BSP address.
-static int i2c_addr2bspaddr(int address);
-#endif // #if DEVICE_I2CSLAVE
-static void i2c_enable_int(i2c_t *obj);
-static void i2c_disable_int(i2c_t *obj);
-static int i2c_set_int(i2c_t *obj, int inten);
-
-
-#if DEVICE_I2C_ASYNCH
-static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
-static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
-static void i2c_rollback_vector_interrupt(i2c_t *obj);
-#endif
-
-#define TRANCTRL_STARTED (1)
-#define TRANCTRL_NAKLASTDATA (1 << 1)
-
-uint32_t us_ticker_read(void);
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl)
-{
- uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
- uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
- obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
- MBED_ASSERT((int)obj->i2c.i2c != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- pinmap_pinout(sda, PinMap_I2C_SDA);
- pinmap_pinout(scl, PinMap_I2C_SCL);
-
-#if DEVICE_I2C_ASYNCH
- obj->i2c.dma_usage = DMA_USAGE_NEVER;
- obj->i2c.event = 0;
- obj->i2c.stop = 0;
- obj->i2c.address = 0;
-#endif
-
- // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
- I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
- // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL. We cannot control interrupt through
- // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- i2c_base->CTL |= (I2C_CTL_INTEN_Msk | I2C_CTL_I2CEN_Msk);
-
- // Enable sync-moce vector interrupt.
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- var->obj = obj;
- obj->i2c.tran_ctrl = 0;
- obj->i2c.stop = 0;
- i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
-
- // Mark this module to be inited.
- int i = modinit - i2c_modinit_tab;
- i2c_modinit_mask |= 1 << i;
-}
-
-int i2c_start(i2c_t *obj)
-{
- return i2c_do_trsn(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk, 1);
-}
-
-int i2c_stop(i2c_t *obj)
-{
- return i2c_do_trsn(obj, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk, 1);
-}
-
-void i2c_frequency(i2c_t *obj, int hz)
-{
- I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
-}
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
-{
- if (i2c_start(obj)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- if (i2c_do_write(obj, i2c_addr2data(address, 1), 0)) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- // Read in bytes
- length = i2c_do_tran(obj, data, length, 1, 1);
-
- // If not repeated start, send stop.
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
-{
- if (i2c_start(obj)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- if (i2c_do_write(obj, i2c_addr2data(address, 0), 0)) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- // Write out bytes
- length = i2c_do_tran(obj, (char *) data, length, 0, 1);
-
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-void i2c_reset(i2c_t *obj)
-{
- i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last)
-{
- char data = 0;
-
- i2c_do_read(obj, &data, last);
- return data;
-}
-
-int i2c_byte_write(i2c_t *obj, int data)
-{
- return i2c_do_write(obj, (data & 0xFF), 0);
-}
-
-#if DEVICE_I2CSLAVE
-
-// See I2CSlave.h
-#define NoData 0 // the slave has not been addressed
-#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
-#define WriteGeneral 2 // the master is writing to all slave
-#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- i2c_disable_int(obj);
-
- obj->i2c.slaveaddr_state = NoData;
-
- // Switch to not addressed mode
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
-
- i2c_enable_int(obj);
-}
-
-int i2c_slave_receive(i2c_t *obj)
-{
- int slaveaddr_state;
-
- i2c_disable_int(obj);
- slaveaddr_state = obj->i2c.slaveaddr_state;
- i2c_enable_int(obj);
-
- return slaveaddr_state;
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length)
-{
- return i2c_do_tran(obj, data, length, 1, 1);
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length)
-{
- return i2c_do_tran(obj, (char *) data, length, 0, 1);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- i2c_disable_int(obj);
-
- I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_ENABLE);
-
- i2c_enable_int(obj);
-}
-
-static int i2c_addr2bspaddr(int address)
-{
- return (address >> 1);
-}
-
-#endif // #if DEVICE_I2CSLAVE
-
-static void i2c_enable_int(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
-
- core_util_critical_section_enter();
-
- // Enable I2C interrupt
- NVIC_EnableIRQ(modinit->irq_n);
- obj->i2c.inten = 1;
-
- core_util_critical_section_exit();
-}
-
-static void i2c_disable_int(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
-
- core_util_critical_section_enter();
-
- // Disable I2C interrupt
- NVIC_DisableIRQ(modinit->irq_n);
- obj->i2c.inten = 0;
-
- core_util_critical_section_exit();
-}
-
-static int i2c_set_int(i2c_t *obj, int inten)
-{
- int inten_back;
-
- core_util_critical_section_enter();
-
- inten_back = obj->i2c.inten;
-
- core_util_critical_section_exit();
-
- if (inten) {
- i2c_enable_int(obj);
- }
- else {
- i2c_disable_int(obj);
- }
-
- return inten_back;
-}
-
-int i2c_allow_powerdown(void)
-{
- uint32_t modinit_mask = i2c_modinit_mask;
- while (modinit_mask) {
- int i2c_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- if (var->obj) {
- // Disallow entering power-down mode if I2C transfer is enabled.
- if (i2c_active(var->obj)) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << i2c_idx);
- }
-
- return 1;
-}
-
-static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
-{
- int tran_len = 0;
-
- i2c_disable_int(obj);
- obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
- obj->i2c.tran_beg = buf;
- obj->i2c.tran_pos = buf;
- obj->i2c.tran_end = buf + length;
- i2c_enable_int(obj);
-
- if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
-#if NU_I2C_DEBUG
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- }
- else {
- i2c_disable_int(obj);
- obj->i2c.tran_ctrl = 0;
- tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
- obj->i2c.tran_beg = NULL;
- obj->i2c.tran_pos = NULL;
- obj->i2c.tran_end = NULL;
- i2c_enable_int(obj);
- }
-
- return tran_len;
-}
-
-static int i2c_do_write(i2c_t *obj, char data, int naklastdata)
-{
- char data_[1];
- data_[0] = data;
- return i2c_do_tran(obj, data_, 1, 0, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
-}
-
-static int i2c_do_read(i2c_t *obj, char *data, int naklastdata)
-{
- return i2c_do_tran(obj, data, 1, 1, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
-}
-
-static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- int err = 0;
-
- i2c_disable_int(obj);
-
- if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
- err = I2C_ERROR_BUS_BUSY;
-#if NU_I2C_DEBUG
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- }
- else {
-#if 1
- // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
- uint32_t status = I2C_GET_STATUS(i2c_base);
-
- switch (status) {
- case 0x08: // Start
- case 0x10: // Master Repeat Start
- if (i2c_ctl & I2C_CTL_STA_Msk) {
- return 0;
- }
- else {
- break;
- }
- case 0xF8: // Bus Released
- if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) {
- return 0;
- }
- else {
- break;
- }
- }
-#endif
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
- err = I2C_ERROR_BUS_BUSY;
-#if NU_I2C_DEBUG
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- }
- }
-
- i2c_enable_int(obj);
-
- return err;
-}
-
-static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
-{
- uint32_t t1, t2, elapsed = 0;
- int status_assert = 0;
-
- t1 = us_ticker_read();
- while (1) {
- status_assert = is_status(obj);
- if (status_assert) {
- break;
- }
-
- t2 = us_ticker_read();
- elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
- if (elapsed >= timeout) {
-#if NU_I2C_DEBUG
- MY_I2C_T1 = t1;
- MY_I2C_T2 = t2;
- MY_I2C_ELAPSED = elapsed;
- MY_I2C_TIMEOUT = timeout;
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- break;
- }
- }
-
- return (elapsed >= timeout);
-}
-
-static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
-{
- uint32_t t1, t2, elapsed = 0;
- int tran_started;
- char *tran_pos = NULL;
- char *tran_pos2 = NULL;
-
- i2c_disable_int(obj);
- tran_pos = obj->i2c.tran_pos;
- i2c_enable_int(obj);
- t1 = us_ticker_read();
- while (1) {
- i2c_disable_int(obj);
- tran_started = i2c_is_tran_started(obj);
- i2c_enable_int(obj);
- if (! tran_started) { // Transfer completed or stopped
- break;
- }
-
- i2c_disable_int(obj);
- tran_pos2 = obj->i2c.tran_pos;
- i2c_enable_int(obj);
- t2 = us_ticker_read();
- if (tran_pos2 != tran_pos) { // Transfer on-going
- t1 = t2;
- tran_pos = tran_pos2;
- continue;
- }
-
- elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
- if (elapsed >= timeout) { // Transfer idle
-#if NU_I2C_DEBUG
- MY_I2C = obj->i2c;
- MY_I2C_T1 = t1;
- MY_I2C_T2 = t2;
- MY_I2C_ELAPSED = elapsed;
- MY_I2C_TIMEOUT = timeout;
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- break;
- }
- }
-
- return (elapsed >= timeout);
-}
-
-#if 0
-static int i2c_is_stat_int(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
-}
-
-static int i2c_is_stop_det(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
-}
-#endif
-
-static int i2c_is_trsn_done(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- int i2c_int;
- uint32_t status;
- int inten_back;
-
- inten_back = i2c_set_int(obj, 0);
- i2c_int = !! (i2c_base->CTL & I2C_CTL_SI_Msk);
- status = I2C_GET_STATUS(i2c_base);
- i2c_set_int(obj, inten_back);
-
- return (i2c_int || status == 0xF8);
-}
-
-static int i2c_is_tran_started(i2c_t *obj)
-{
- int started;
- int inten_back;
-
- inten_back = i2c_set_int(obj, 0);
- started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
- i2c_set_int(obj, inten_back);
-
- return started;
-}
-
-static int i2c_addr2data(int address, int read)
-{
- return read ? (address | 1) : (address & 0xFE);
-}
-
-static void i2c0_vec(void)
-{
- i2c_irq(i2c0_var.obj);
-}
-static void i2c1_vec(void)
-{
- i2c_irq(i2c1_var.obj);
-}
-
-static void i2c_irq(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- uint32_t status;
-
- if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
- I2C_ClearTimeoutFlag(i2c_base);
- return;
- }
-
- status = I2C_GET_STATUS(i2c_base);
-#if NU_I2C_DEBUG
- if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
- MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
- }
- else {
- memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
- MY_I2C_STATUS_POS = 0;
- }
-#endif
-
- switch (status) {
- // Master Transmit
- case 0x28: // Master Transmit Data ACK
- case 0x18: // Master Transmit Address ACK
- case 0x08: // Start
- case 0x10: // Master Repeat Start
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
- else {
- if (status == 0x18) {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
- case 0x30: // Master Transmit Data NACK
- case 0x20: // Master Transmit Address NACK
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- break;
- case 0x38: // Master Arbitration Lost
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- break;
-
- case 0x48: // Master Receive Address NACK
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- break;
- case 0x40: // Master Receive Address ACK
- case 0x50: // Master Receive Data ACK
- case 0x58: // Master Receive Data NACK
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- if (status == 0x50 || status == 0x58) {
- *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
- }
-
- if (status == 0x58) {
-#if NU_I2C_DEBUG
- if (obj->i2c.tran_pos != obj->i2c.tran_end) {
- MY_I2C = obj->i2c;
- while (1);
- }
-#endif
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- else {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
- if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
-
- //case 0x00: // Bus error
-
- // Slave Transmit
- case 0xB8: // Slave Transmit Data ACK
- case 0xA8: // Slave Transmit Address ACK
- case 0xB0: // Slave Transmit Arbitration Lost
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
-
- I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
- if (obj->i2c.tran_pos == obj->i2c.tran_end &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- obj->i2c.slaveaddr_state = ReadAddressed;
- break;
- //case 0xA0: // Slave Transmit Repeat Start or Stop
- case 0xC0: // Slave Transmit Data NACK
- case 0xC8: // Slave Transmit Last Data ACK
- obj->i2c.slaveaddr_state = NoData;
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- break;
-
- // Slave Receive
- case 0x80: // Slave Receive Data ACK
- case 0x88: // Slave Receive Data NACK
- case 0x60: // Slave Receive Address ACK
- case 0x68: // Slave Receive Arbitration Lost
- obj->i2c.slaveaddr_state = WriteAddressed;
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- if (status == 0x80 || status == 0x88) {
- *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
- }
-
- if (status == 0x88) {
-#if NU_I2C_DEBUG
- if (obj->i2c.tran_pos != obj->i2c.tran_end) {
- MY_I2C = obj->i2c;
- while (1);
- }
-#endif
- obj->i2c.slaveaddr_state = NoData;
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
- else {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
- if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
- //case 0xA0: // Slave Receive Repeat Start or Stop
-
- // GC mode
- //case 0xA0: // GC mode Repeat Start or Stop
- case 0x90: // GC mode Data ACK
- case 0x98: // GC mode Data NACK
- case 0x70: // GC mode Address ACK
- case 0x78: // GC mode Arbitration Lost
- obj->i2c.slaveaddr_state = WriteAddressed;
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- if (status == 0x90 || status == 0x98) {
- *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
- }
-
- if (status == 0x98) {
-#if NU_I2C_DEBUG
- if (obj->i2c.tran_pos != obj->i2c.tran_end) {
- MY_I2C = obj->i2c;
- while (1);
- }
-#endif
- obj->i2c.slaveaddr_state = NoData;
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
- else {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
- if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
-
- case 0xF8: // Bus Released
- break;
-
- default:
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
-}
-
-static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- obj->i2c.stop = 0;
-
- obj->i2c.tran_ctrl = 0;
-
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- obj->i2c.slaveaddr_state = NoData;
-}
-
-#if DEVICE_I2C_ASYNCH
-
-void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
-{
- // NOTE: M451 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
- MBED_ASSERT((address & 0xFFFFFF00) == 0);
-
- // NOTE: First transmit and then receive.
-
- (void) hint;
- obj->i2c.dma_usage = DMA_USAGE_NEVER;
- obj->i2c.stop = stop;
- obj->i2c.address = address;
- obj->i2c.event = event;
- i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
-
- //I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- i2c_enable_vector_interrupt(obj, handler, 1);
- i2c_start(obj);
-}
-
-uint32_t i2c_irq_handler_asynch(i2c_t *obj)
-{
- int event = 0;
-
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- uint32_t status = I2C_GET_STATUS(i2c_base);
- switch (status) {
- case 0x08: // Start
- case 0x10: {// Master Repeat Start
- if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
- I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
- }
- else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
- }
- else {
- event = I2C_EVENT_TRANSFER_COMPLETE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
- break;
- }
-
- case 0x18: // Master Transmit Address ACK
- case 0x28: // Master Transmit Data ACK
- if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
- uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
- I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
- }
- else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- else {
- event = I2C_EVENT_TRANSFER_COMPLETE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
- break;
-
- case 0x20: // Master Transmit Address NACK
- event = I2C_EVENT_ERROR_NO_SLAVE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- break;
-
- case 0x30: // Master Transmit Data NACK
- if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
- event = I2C_EVENT_TRANSFER_EARLY_NACK;
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- else {
- event = I2C_EVENT_TRANSFER_COMPLETE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
- break;
-
- case 0x38: // Master Arbitration Lost
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk); // Enter not addressed SLV mode
- event = I2C_EVENT_ERROR;
- break;
-
- case 0x50: // Master Receive Data ACK
- if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
- rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
- }
- case 0x40: // Master Receive Address ACK
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL_AA_Msk : 0));
- break;
-
- case 0x48: // Master Receive Address NACK
- event = I2C_EVENT_ERROR_NO_SLAVE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- break;
-
- case 0x58: // Master Receive Data NACK
- if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
- rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
- }
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- break;
-
- case 0x00: // Bus error
- event = I2C_EVENT_ERROR;
- i2c_reset(obj);
- break;
-
- default:
- event = I2C_EVENT_ERROR;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
-
- if (event) {
- i2c_rollback_vector_interrupt(obj);
- }
-
- return (event & obj->i2c.event);
-}
-
-uint8_t i2c_active(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- // Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
- uint32_t vec = NVIC_GetVector(modinit->irq_n);
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- return (vec && vec != (uint32_t) var->vec);
-}
-
-void i2c_abort_asynch(i2c_t *obj)
-{
- i2c_rollback_vector_interrupt(obj);
- i2c_stop(obj);
-}
-
-static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
-{
- obj->tx_buff.buffer = (void *) tx;
- obj->tx_buff.length = tx_length;
- obj->tx_buff.pos = 0;
- obj->rx_buff.buffer = rx;
- obj->rx_buff.length = rx_length;
- obj->rx_buff.pos = 0;
-}
-
-static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- if (enable) {
- NVIC_SetVector(modinit->irq_n, handler);
- i2c_enable_int(obj);
- }
- else {
- i2c_disable_int(obj);
- }
-
-}
-
-static void i2c_rollback_vector_interrupt(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
-}
-
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,226 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "lp_ticker_api.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "sleep_api.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "critical.h"
-
-// lp_ticker tick = us = timestamp
-#define US_PER_TICK (1)
-#define US_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR2_INT (US_PER_SEC * 10)
-#define TMR2_CLK_PER_SEC (__LXT)
-#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
-#define TMR3_CLK_PER_SEC (__LXT)
-
-static void tmr2_vec(void);
-static void tmr3_vec(void);
-static void lp_ticker_arm_cd(void);
-
-static int lp_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_clks = 0;
-static volatile uint32_t cd_minor_clks = 0;
-static volatile uint32_t wakeup_tick = (uint32_t) -1;
-
-// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
-// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
-static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
-static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
-
-#define TMR_CMP_MIN 2
-#define TMR_CMP_MAX 0xFFFFFFu
-
-void lp_ticker_init(void)
-{
- if (lp_ticker_inited) {
- return;
- }
- lp_ticker_inited = 1;
-
- counter_major = 0;
- cd_major_minor_clks = 0;
- cd_minor_clks = 0;
- wakeup_tick = (uint32_t) -1;
-
- // Reset module
- SYS_ResetModule(timer2_modinit.rsetidx);
- SYS_ResetModule(timer3_modinit.rsetidx);
-
- // Select IP clock source
- CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
- CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
- // Enable IP clock
- CLK_EnableModuleClock(timer2_modinit.clkidx);
- CLK_EnableModuleClock(timer3_modinit.clkidx);
-
- // Configure clock
- uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
- MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
- uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
- MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
- // Continuous mode
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
-
- // Set vector
- NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
- NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
-
- NVIC_EnableIRQ(timer2_modinit.irq_n);
- NVIC_EnableIRQ(timer3_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
- lp_ticker_set_interrupt(wakeup_tick);
-
- // Start timer
- TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-}
-
-timestamp_t lp_ticker_read()
-{
- if (! lp_ticker_inited) {
- lp_ticker_init();
- }
-
- TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
-
- do {
- uint64_t major_minor_clks;
- uint32_t minor_clks;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_clks = TIMER_GetCounter(timer2_base);
- uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
- major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
- }
- else {
- major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
-
- // Add power-down compensation
- return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
- }
- while (0);
-}
-
-void lp_ticker_set_interrupt(timestamp_t timestamp)
-{
- uint32_t now = lp_ticker_read();
- wakeup_tick = timestamp;
-
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-
- /**
- * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
- * Conditions in which delta is negative:
- * 1. Wrap around
- * 2. Newly scheduled alarm is behind now
- */
- //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
- int delta = (int) (timestamp - now);
- if (delta > 0) {
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
- }
- else {
- cd_major_minor_clks = cd_minor_clks = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
- }
-}
-
-void lp_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-void lp_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-static void tmr2_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- counter_major ++;
-}
-
-static void tmr3_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
- if (cd_major_minor_clks == 0) {
- // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
- lp_ticker_irq_handler();
- }
- else {
- lp_ticker_arm_cd();
- }
-}
-
-static void lp_ticker_arm_cd(void)
-{
- TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
-
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 KHz
- uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
- MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
- timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
-
- cd_minor_clks = cd_major_minor_clks;
- cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
- timer3_base->CMP = cd_minor_clks;
-
- TIMER_EnableInt(timer3_base);
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_Start(timer3_base);
-}
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/mbed_lib.json Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,18 +0,0 @@
-{
- "name": "M451",
- "config": {
- "gpio-irq-debounce-enable": {
- "help": "Enable GPIO IRQ debounce",
- "value": 0
- },
- "gpio-irq-debounce-clock-source": {
- "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
- "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
- },
-
- "gpio-irq-debounce-sample-rate": {
- "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
- "value": "GPIO_DBCTL_DBCLKSEL_16"
- }
- }
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/pinmap.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,83 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "mbed_assert.h"
-#include "pinmap.h"
-#include "PortNames.h"
-#include "mbed_error.h"
-
-/**
- * Configure pin multi-function
- */
-void pin_function(PinName pin, int data)
-{
- MBED_ASSERT(pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(pin);
- __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8);
- //uint32_t MFP_Pos = NU_MFP_POS(pin_index);
- uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
-
- // E.g.: SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ;
- *GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data;
-
- // [TODO] Disconnect JTAG-DP + SW-DP signals.
- // Warning: Need to reconnect under reset
- //if ((pin == PA_13) || (pin == PA_14)) {
- //
- //}
- //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
- //
- //}
-}
-
-/**
- * Configure pin pull-up/pull-down
- */
-void pin_mode(PinName pin, PinMode mode)
-{
- MBED_ASSERT(pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
- switch (mode) {
- case PullUp:
- mode_intern = GPIO_MODE_INPUT;
- break;
-
- case PullDown:
- case PullNone:
- // NOTE: Not support
- return;
-
- case PushPull:
- mode_intern = GPIO_MODE_OUTPUT;
- break;
-
- case OpenDrain:
- mode_intern = GPIO_MODE_OPEN_DRAIN;
- break;
-
- case Quasi:
- mode_intern = GPIO_MODE_QUASI;
- break;
- }
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
-}
--- a/targets/TARGET_NUVOTON/TARGET_M451/port_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,99 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "port_api.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT
-
-PinName port_pin(PortName port, int pin_n)
-{
- return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n);
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
-{
- obj->port = port;
- obj->mask = mask;
- obj->direction = dir;
-
- uint32_t i;
- obj->direction = dir;
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- gpio_set(port_pin(port, i));
- }
- }
-
- port_dir(obj, dir);
-}
-
-void port_dir(port_t *obj, PinDirection dir)
-{
- uint32_t i;
- obj->direction = dir;
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- if (dir == PIN_OUTPUT) {
- GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT);
- } else { // PIN_INPUT
- GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT);
- }
- }
- }
-}
-
-void port_mode(port_t *obj, PinMode mode)
-{
- uint32_t i;
-
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- pin_mode(port_pin(obj->port, i), mode);
- }
- }
-}
-
-void port_write(port_t *obj, int value)
-{
- uint32_t i;
- uint32_t port_index = obj->port;
-
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0;
- }
- }
-}
-
-int port_read(port_t *obj)
-{
- uint32_t i;
- uint32_t port_index = obj->port;
- int value = 0;
-
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- value = value | (GPIO_PIN_DATA(port_index, i) << i);
- }
- }
-
- return value;
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,204 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "pwmout_api.h"
-
-#if DEVICE_PWMOUT
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "nu_bitutil.h"
-
-struct nu_pwm_var {
- uint32_t en_msk;
-};
-
-static struct nu_pwm_var pwm0_var = {
- .en_msk = 0
-};
-
-static struct nu_pwm_var pwm1_var = {
- .en_msk = 0
-};
-
-static uint32_t pwm_modinit_mask = 0;
-
-static const struct nu_modinit_s pwm_modinit_tab[] = {
- {PWM_0_0, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P0_IRQn, &pwm0_var},
- {PWM_0_1, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P0_IRQn, &pwm0_var},
- {PWM_0_2, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P1_IRQn, &pwm0_var},
- {PWM_0_3, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P1_IRQn, &pwm0_var},
- {PWM_0_4, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P2_IRQn, &pwm0_var},
- {PWM_0_5, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0P2_IRQn, &pwm0_var},
-
- {PWM_1_0, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P0_IRQn, &pwm1_var},
- {PWM_1_1, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P0_IRQn, &pwm1_var},
- {PWM_1_2, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P1_IRQn, &pwm1_var},
- {PWM_1_3, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P1_IRQn, &pwm1_var},
- {PWM_1_4, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P2_IRQn, &pwm1_var},
- {PWM_1_5, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1P2_IRQn, &pwm1_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-static void pwmout_config(pwmout_t* obj);
-
-void pwmout_init(pwmout_t* obj, PinName pin)
-{
- obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
- MBED_ASSERT((int) obj->pwm != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->pwm);
-
- // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module.
- if (! ((struct nu_pwm_var *) modinit->var)->en_msk) {
- // Reset this module if no channel enabled
- SYS_ResetModule(modinit->rsetidx);
- }
-
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
- uint32_t chn = NU_MODSUBINDEX(obj->pwm);
-
- // NOTE: Channels 0/1/2/3/4/5 share a clock source.
- if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
- // Select clock source of paired channels
- CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
- // Enable clock of paired channels
- CLK_EnableModuleClock(modinit->clkidx);
- }
-
- // Wire pinout
- pinmap_pinout(pin, PinMap_PWM);
-
- // Default: period = 10 ms, pulse width = 0 ms
- obj->period_us = 1000 * 10;
- obj->pulsewidth_us = 0;
- pwmout_config(obj);
-
- // Enable output of the specified PWM channel
- PWM_EnableOutput(pwm_base, 1 << chn);
- PWM_Start(pwm_base, 1 << chn);
-
- ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
-
- // Mark this module to be inited.
- int i = modinit - pwm_modinit_tab;
- pwm_modinit_mask |= 1 << i;
-}
-
-void pwmout_free(pwmout_t* obj)
-{
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
- uint32_t chn = NU_MODSUBINDEX(obj->pwm);
- PWM_ForceStop(pwm_base, 1 << chn);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->pwm);
- ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
-
-
- if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) {
- CLK_DisableModuleClock(modinit->clkidx);
- }
-
- // Mark this module to be deinited.
- int i = modinit - pwm_modinit_tab;
- pwm_modinit_mask &= ~(1 << i);
-}
-
-void pwmout_write(pwmout_t* obj, float value)
-{
- obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
- pwmout_config(obj);
-}
-
-float pwmout_read(pwmout_t* obj)
-{
- return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds)
-{
- pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms)
-{
- pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us)
-{
- uint32_t period_us_old = obj->period_us;
- uint32_t pulsewidth_us_old = obj->pulsewidth_us;
- obj->period_us = us;
- obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
- pwmout_config(obj);
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds)
-{
- pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
-{
- pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us)
-{
- obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
- pwmout_config(obj);
-}
-
-int pwmout_allow_powerdown(void)
-{
- uint32_t modinit_mask = pwm_modinit_mask;
- while (modinit_mask) {
- int pwm_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
- if (modinit->modname != NC) {
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
- uint32_t chn = NU_MODSUBINDEX(modinit->modname);
- // Disallow entering power-down mode if PWM counter is enabled.
- if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << pwm_idx);
- }
-
- return 1;
-}
-
-static void pwmout_config(pwmout_t* obj)
-{
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
- uint32_t chn = NU_MODSUBINDEX(obj->pwm);
- // NOTE: Support period < 1s
- //PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
- PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "rtc_api.h"
-
-#if DEVICE_RTC
-
-#include "wait_api.h"
-#include "mbed_error.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-
-#define YEAR0 1900
-//#define EPOCH_YR 1970
-static int rtc_inited = 0;
-
-static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
-
-void rtc_init(void)
-{
- if (rtc_inited) {
- return;
- }
- rtc_inited = 1;
-
- // Enable IP clock
- CLK_EnableModuleClock(rtc_modinit.clkidx);
-
- RTC_Open(NULL);
-}
-
-void rtc_free(void)
-{
- // FIXME
-}
-
-int rtc_isenabled(void)
-{
- return rtc_inited;
-}
-
-/*
- struct tm
- tm_sec seconds after the minute 0-61
- tm_min minutes after the hour 0-59
- tm_hour hours since midnight 0-23
- tm_mday day of the month 1-31
- tm_mon months since January 0-11
- tm_year years since 1900
- tm_wday days since Sunday 0-6
- tm_yday days since January 1 0-365
- tm_isdst Daylight Saving Time flag
-*/
-
-time_t rtc_read(void)
-{
- if (! rtc_inited) {
- rtc_init();
- }
-
- S_RTC_TIME_DATA_T rtc_datetime;
- RTC_GetDateAndTime(&rtc_datetime);
-
- struct tm timeinfo;
-
- // Convert struct tm to S_RTC_TIME_DATA_T
- timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
- timeinfo.tm_mon = rtc_datetime.u32Month - 1;
- timeinfo.tm_mday = rtc_datetime.u32Day;
- timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
- timeinfo.tm_hour = rtc_datetime.u32Hour;
- timeinfo.tm_min = rtc_datetime.u32Minute;
- timeinfo.tm_sec = rtc_datetime.u32Second;
-
- // Convert to timestamp
- time_t t = mktime(&timeinfo);
-
- return t;
-}
-
-void rtc_write(time_t t)
-{
- if (! rtc_inited) {
- rtc_init();
- }
-
- // Convert timestamp to struct tm
- struct tm *timeinfo = localtime(&t);
-
- S_RTC_TIME_DATA_T rtc_datetime;
-
- // Convert S_RTC_TIME_DATA_T to struct tm
- rtc_datetime.u32Year = timeinfo->tm_year + YEAR0;
- rtc_datetime.u32Month = timeinfo->tm_mon + 1;
- rtc_datetime.u32Day = timeinfo->tm_mday;
- rtc_datetime.u32DayOfWeek = timeinfo->tm_wday;
- rtc_datetime.u32Hour = timeinfo->tm_hour;
- rtc_datetime.u32Minute = timeinfo->tm_min;
- rtc_datetime.u32Second = timeinfo->tm_sec;
- rtc_datetime.u32TimeScale = RTC_CLOCK_24;
-
- // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
- RTC_SetDateAndTime(&rtc_datetime);
- //nu_nop(6000);
- wait_us(100);
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1071 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "serial_api.h"
-
-#if DEVICE_SERIAL
-
-#include "cmsis.h"
-#include "mbed_error.h"
-#include "mbed_assert.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_bitutil.h"
-
-#if DEVICE_SERIAL_ASYNCH
-#include "dma_api.h"
-#include "dma.h"
-#endif
-
-struct nu_uart_var {
- uint32_t ref_cnt; // Reference count of the H/W module
- serial_t * obj;
- uint32_t fifo_size_tx;
- uint32_t fifo_size_rx;
- void (*vec)(void);
-#if DEVICE_SERIAL_ASYNCH
- void (*vec_async)(void);
- uint8_t pdma_perp_tx;
- uint8_t pdma_perp_rx;
-#endif
-};
-
-static void uart0_vec(void);
-static void uart1_vec(void);
-static void uart2_vec(void);
-static void uart3_vec(void);
-static void uart_irq(serial_t *obj);
-
-#if DEVICE_SERIAL_ASYNCH
-static void uart0_vec_async(void);
-static void uart1_vec_async(void);
-static void uart2_vec_async(void);
-static void uart3_vec_async(void);
-static void uart_irq_async(serial_t *obj);
-
-static void uart_dma_handler_tx(uint32_t id, uint32_t event);
-static void uart_dma_handler_rx(uint32_t id, uint32_t event);
-
-static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
-static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
-static int serial_write_async(serial_t *obj);
-static int serial_read_async(serial_t *obj);
-
-static uint32_t serial_rx_event_check(serial_t *obj);
-static uint32_t serial_tx_event_check(serial_t *obj);
-
-static int serial_is_tx_complete(serial_t *obj);
-static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
-
-static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
-static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
-static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
-static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
-static int serial_is_rx_complete(serial_t *obj);
-
-static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
-static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
-#endif
-
-static struct nu_uart_var uart0_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart0_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart0_vec_async,
- .pdma_perp_tx = PDMA_UART0_TX,
- .pdma_perp_rx = PDMA_UART0_RX
-#endif
-};
-static struct nu_uart_var uart1_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart1_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart1_vec_async,
- .pdma_perp_tx = PDMA_UART1_TX,
- .pdma_perp_rx = PDMA_UART1_RX
-#endif
-};
-static struct nu_uart_var uart2_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart2_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart2_vec_async,
- .pdma_perp_tx = PDMA_UART2_TX,
- .pdma_perp_rx = PDMA_UART2_RX
-#endif
-};
-static struct nu_uart_var uart3_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart3_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart3_vec_async,
- .pdma_perp_tx = PDMA_UART3_TX,
- .pdma_perp_rx = PDMA_UART3_RX
-#endif
-};
-
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-static uint32_t uart_modinit_mask = 0;
-
-static const struct nu_modinit_s uart_modinit_tab[] = {
- {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
- {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
- {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
- {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-extern void mbed_sdk_init(void);
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
- // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
- mbed_sdk_init();
-
- // Determine which UART_x the pins are used for
- uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
- uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
- // Get the peripheral name (UART_x) from the pins and assign it to the object
- obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
- MBED_ASSERT((int)obj->serial.uart != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
-
- if (! var->ref_cnt) {
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Select IP clock source
- CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- pinmap_pinout(tx, PinMap_UART_TX);
- pinmap_pinout(rx, PinMap_UART_RX);
-
- obj->serial.pin_tx = tx;
- obj->serial.pin_rx = rx;
- }
- var->ref_cnt ++;
-
- // Configure the UART module and set its baudrate
- serial_baud(obj, 9600);
- // Configure data bits, parity, and stop bits
- serial_format(obj, 8, ParityNone, 1);
-
- obj->serial.vec = var->vec;
-
-#if DEVICE_SERIAL_ASYNCH
- obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
- obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
- obj->serial.event = 0;
- obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
-#endif
-
- // For stdio management
- if (obj->serial.uart == STDIO_UART) {
- stdio_uart_inited = 1;
- memcpy(&stdio_uart, obj, sizeof(serial_t));
- }
-
- if (var->ref_cnt) {
- // Mark this module to be inited.
- int i = modinit - uart_modinit_tab;
- uart_modinit_mask |= 1 << i;
- }
-}
-
-void serial_free(serial_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
-
- var->ref_cnt --;
- if (! var->ref_cnt) {
-#if DEVICE_SERIAL_ASYNCH
- if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->serial.dma_chn_id_tx);
- obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- }
- if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->serial.dma_chn_id_rx);
- obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-#endif
-
- UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
-
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- NVIC_DisableIRQ(modinit->irq_n);
-
- // Disable IP clock
- CLK_DisableModuleClock(modinit->clkidx);
- }
-
- if (var->obj == obj) {
- var->obj = NULL;
- }
-
- if (obj->serial.uart == STDIO_UART) {
- stdio_uart_inited = 0;
- }
-
- if (! var->ref_cnt) {
- // Mark this module to be deinited.
- int i = modinit - uart_modinit_tab;
- uart_modinit_mask &= ~(1 << i);
- }
-}
-
-void serial_baud(serial_t *obj, int baudrate) {
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- obj->serial.baudrate = baudrate;
- UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- // TODO: Assert for not supported parity and data bits
- obj->serial.databits = data_bits;
- obj->serial.parity = parity;
- obj->serial.stopbits = stop_bits;
-
- uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
- (data_bits == 6) ? UART_WORD_LEN_6 :
- (data_bits == 7) ? UART_WORD_LEN_7 :
- UART_WORD_LEN_8;
- uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
- (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
- UART_PARITY_NONE;
- uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
- UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
- 0, // Don't change baudrate
- databits_intern,
- parity_intern,
- stopbits_intern);
-}
-
-#if DEVICE_SERIAL_FC
-
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- // First, disable flow control completely.
- uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
-
- if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
- // Check if RTS pin matches.
- uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
- MBED_ASSERT(uart_rts == obj->serial.uart);
- // Enable the pin for RTS function
- pinmap_pinout(rxflow, PinMap_UART_RTS);
- // nRTS pin output is high level active
- uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk);
- uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
- // Enable RTS
- uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
- }
-
- if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
- // Check if CTS pin matches.
- uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
- MBED_ASSERT(uart_cts == obj->serial.uart);
- // Enable the pin for CTS function
- pinmap_pinout(txflow, PinMap_UART_CTS);
- // nCTS pin input is high level active
- uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk);
- // Enable CTS
- uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
- }
-}
-
-#endif //DEVICE_SERIAL_FC
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
-{
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- obj->serial.irq_handler = (uint32_t) handler;
- obj->serial.irq_id = id;
-
- // Restore sync-mode vector
- obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
-{
- if (enable) {
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
- NVIC_EnableIRQ(modinit->irq_n);
-
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
- // Multiple serial S/W objects for single UART H/W module possibly.
- // Bind serial S/W object to UART H/W module as interrupt is enabled.
- var->obj = obj;
-
- switch (irq) {
- // NOTE: Setting inten_msk first to avoid race condition
- case RxIrq:
- obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- break;
- case TxIrq:
- obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- break;
- }
- } else { // disable
- switch (irq) {
- case RxIrq:
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
- break;
- case TxIrq:
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
- break;
- }
- }
-}
-
-int serial_getc(serial_t *obj)
-{
- // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
- while (! serial_readable(obj));
- int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
-
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- }
-
- return c;
-}
-
-void serial_putc(serial_t *obj, int c)
-{
- // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
- while (! serial_writable(obj));
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
-
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- }
-}
-
-int serial_readable(serial_t *obj)
-{
- //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
- return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
-}
-
-int serial_writable(serial_t *obj)
-{
- return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
-}
-
-void serial_pinout_tx(PinName tx)
-{
- pinmap_pinout(tx, PinMap_UART_TX);
-}
-
-void serial_break_set(serial_t *obj)
-{
- ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
-}
-
-void serial_break_clear(serial_t *obj)
-{
- ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
-}
-
-static void uart0_vec(void)
-{
- uart_irq(uart0_var.obj);
-}
-
-static void uart1_vec(void)
-{
- uart_irq(uart1_var.obj);
-}
-
-static void uart2_vec(void)
-{
- uart_irq(uart2_var.obj);
-}
-
-static void uart3_vec(void)
-{
- uart_irq(uart3_var.obj);
-}
-
-static void uart_irq(serial_t *obj)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
- UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- if (obj->serial.irq_handler) {
- ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
- }
- }
-
- if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
- UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
- if (obj->serial.irq_handler) {
- ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
- }
- }
-
- // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
- uart_base->INTSTS = uart_base->INTSTS;
- uart_base->FIFOSTS = uart_base->FIFOSTS;
-}
-
-
-#if DEVICE_SERIAL_ASYNCH
-int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
-{
- // NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
- tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
-
- MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
-
- obj->serial.dma_usage_tx = hint;
- serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
-
- // UART IRQ is necessary for both interrupt way and DMA way
- serial_tx_enable_event(obj, event, 1);
- serial_tx_buffer_set(obj, tx, tx_length, tx_width);
- //UART_HAL_DisableTransmitter(obj->serial.address);
- //UART_HAL_FlushTxFifo(obj->serial.address);
- //UART_HAL_EnableTransmitter(obj->serial.address);
-
- int n_word = 0;
- if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
- // Interrupt way
- n_word = serial_write_async(obj);
- serial_tx_enable_interrupt(obj, handler, 1);
- } else {
- // DMA way
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
- ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
- (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- tx_length);
- PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
- (uint32_t) tx, // NOTE:
- // NUC472: End of source address
- // M451: Start of source address
- PDMA_SAR_INC, // Source address incremental
- (uint32_t) obj->serial.uart, // Destination address
- PDMA_DAR_FIX); // Destination address fixed
- PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->serial.dma_chn_id_tx,
- PDMA_INT_TRANS_DONE); // Interrupt type
- // Register DMA event handler
- dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
- serial_tx_enable_interrupt(obj, handler, 1);
- ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
- }
-
- return n_word;
-}
-
-void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
-{
- // NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
- rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
-
- MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
-
- obj->serial.dma_usage_rx = hint;
- serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
- // DMA doesn't support char match, so fall back to IRQ if it is requested.
- if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
- (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
- char_match != SERIAL_RESERVED_CHAR_MATCH) {
- obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
- dma_channel_free(obj->serial.dma_chn_id_rx);
- obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-
- // UART IRQ is necessary for both interrupt way and DMA way
- serial_rx_enable_event(obj, event, 1);
- serial_rx_buffer_set(obj, rx, rx_length, rx_width);
- serial_rx_set_char_match(obj, char_match);
- //UART_HAL_DisableReceiver(obj->serial.address);
- //UART_HAL_FlushRxFifo(obj->serial.address);
- //UART_HAL_EnableReceiver(obj->serial.address);
-
- if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
- // Interrupt way
- serial_rx_enable_interrupt(obj, handler, 1);
- } else {
- // DMA way
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
- ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
- (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- rx_length);
- PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
- (uint32_t) obj->serial.uart, // Source address
- PDMA_SAR_FIX, // Source address fixed
- (uint32_t) rx, // NOTE:
- // NUC472: End of destination address
- // M451: Start of destination address
- PDMA_DAR_INC); // Destination address incremental
- PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->serial.dma_chn_id_rx,
- PDMA_INT_TRANS_DONE); // Interrupt type
- // Register DMA event handler
- dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
- serial_rx_enable_interrupt(obj, handler, 1);
- ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
- }
-}
-
-void serial_tx_abort_asynch(serial_t *obj)
-{
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
- if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE);
- // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->serial.dma_chn_id_tx);
- PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
- }
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
- }
-
- // Necessary for both interrupt way and DMA way
- serial_irq_set(obj, TxIrq, 0);
- // FIXME: more complete abort operation
- //UART_HAL_DisableTransmitter(obj->serial.serial.address);
- //UART_HAL_FlushTxFifo(obj->serial.serial.address);
-}
-
-void serial_rx_abort_asynch(serial_t *obj)
-{
- if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
- if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE);
- // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->serial.dma_chn_id_rx);
- PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
- }
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
- }
-
- // Necessary for both interrupt way and DMA way
- serial_irq_set(obj, RxIrq, 0);
- // FIXME: more complete abort operation
- //UART_HAL_DisableReceiver(obj->serial.serial.address);
- //UART_HAL_FlushRxFifo(obj->serial.serial.address);
-}
-
-uint8_t serial_tx_active(serial_t *obj)
-{
- return serial_is_irq_en(obj, TxIrq);
-}
-
-uint8_t serial_rx_active(serial_t *obj)
-{
- return serial_is_irq_en(obj, RxIrq);
-}
-
-int serial_irq_handler_asynch(serial_t *obj)
-{
- int event_rx = 0;
- int event_tx = 0;
-
- // Necessary for both interrupt way and DMA way
- if (serial_is_irq_en(obj, RxIrq)) {
- event_rx = serial_rx_event_check(obj);
- if (event_rx) {
- serial_rx_abort_asynch(obj);
- }
- }
-
- if (serial_is_irq_en(obj, TxIrq)) {
- event_tx = serial_tx_event_check(obj);
- if (event_tx) {
- serial_tx_abort_asynch(obj);
- }
- }
-
- return (obj->serial.event & (event_rx | event_tx));
-}
-
-int serial_allow_powerdown(void)
-{
- uint32_t modinit_mask = uart_modinit_mask;
- while (modinit_mask) {
- int uart_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
- if (modinit->modname != NC) {
- UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
- // Disallow entering power-down mode if Tx FIFO has data to flush
- if (! UART_IS_TX_EMPTY((uart_base))) {
- return 0;
- }
- // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
- if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
- return 0;
- }
- // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
- if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << uart_idx);
- }
-
- return 1;
-}
-
-static void uart0_vec_async(void)
-{
- uart_irq_async(uart0_var.obj);
-}
-
-static void uart1_vec_async(void)
-{
- uart_irq_async(uart1_var.obj);
-}
-
-static void uart2_vec_async(void)
-{
- uart_irq_async(uart2_var.obj);
-}
-
-static void uart3_vec_async(void)
-{
- uart_irq_async(uart3_var.obj);
-}
-
-static void uart_irq_async(serial_t *obj)
-{
- if (serial_is_irq_en(obj, RxIrq)) {
- (*obj->serial.irq_handler_rx_async)();
- }
- if (serial_is_irq_en(obj, TxIrq)) {
- (*obj->serial.irq_handler_tx_async)();
- }
-}
-
-static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
-{
- obj->char_match = char_match;
- obj->char_found = 0;
-}
-
-static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
-{
- obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
- obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
-
- //if (event & SERIAL_EVENT_TX_COMPLETE) {
- //}
-}
-
-static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
-{
- obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
- obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
-
- //if (event & SERIAL_EVENT_RX_COMPLETE) {
- //}
- //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
- //}
- if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
- }
- if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
- }
- if (event & SERIAL_EVENT_RX_OVERFLOW) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
- }
- //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
- //}
-}
-
-static int serial_is_tx_complete(serial_t *obj)
-{
- // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
- //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
- // FIXME: Premature abort???
- return (obj->tx_buff.pos == obj->tx_buff.length);
-}
-
-static int serial_is_rx_complete(serial_t *obj)
-{
- //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
- return (obj->rx_buff.pos == obj->rx_buff.length);
-}
-
-static uint32_t serial_tx_event_check(serial_t *obj)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
- UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
- }
-
- uint32_t event = 0;
-
- if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
- serial_write_async(obj);
- }
-
- if (serial_is_tx_complete(obj)) {
- event |= SERIAL_EVENT_TX_COMPLETE;
- }
-
- return event;
-}
-
-static uint32_t serial_rx_event_check(serial_t *obj)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
- UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- }
-
- uint32_t event = 0;
-
- if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
- }
- if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
- event |= SERIAL_EVENT_RX_FRAMING_ERROR;
- }
- if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
- event |= SERIAL_EVENT_RX_PARITY_ERROR;
- }
-
- if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
- event |= SERIAL_EVENT_RX_OVERFLOW;
- }
-
- if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
- serial_read_async(obj);
- }
-
- if (serial_is_rx_complete(obj)) {
- event |= SERIAL_EVENT_RX_COMPLETE;
- }
- if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
- event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
- // FIXME: Timing to reset char_found?
- //obj->char_found = 0;
- }
-
- return event;
-}
-
-static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
-{
- serial_t *obj = (serial_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect UART IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->tx_buff.pos = obj->tx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- uart_irq_async(obj);
-}
-
-static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
-{
- serial_t *obj = (serial_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect UART IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->rx_buff.pos = obj->rx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- uart_irq_async(obj);
-}
-
-static int serial_write_async(serial_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
- uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
- if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
- tx_fifo_busy = tx_fifo_max;
- }
- uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
- if (tx_fifo_free == 0) {
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- }
- return 0;
- }
-
- uint32_t bytes_per_word = obj->tx_buff.width / 8;
-
- uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
- int n_words = 0;
- while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
- switch (bytes_per_word) {
- case 4:
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- case 2:
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- case 1:
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- }
-
- n_words ++;
- tx_fifo_free -= bytes_per_word;
- obj->tx_buff.pos ++;
- }
-
- if (n_words) {
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- }
- }
-
- return n_words;
-}
-
-static int serial_read_async(serial_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
- //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
- //if (rx_fifo_free == 0) {
- // return 0;
- //}
-
- uint32_t bytes_per_word = obj->rx_buff.width / 8;
-
- uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
- int n_words = 0;
- while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
- switch (bytes_per_word) {
- case 4:
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- case 2:
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- case 1:
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- }
-
- n_words ++;
- rx_fifo_busy -= bytes_per_word;
- obj->rx_buff.pos ++;
-
- if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
- obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
- uint8_t *rx_cmp = rx;
- switch (bytes_per_word) {
- case 4:
- rx_cmp -= 2;
- case 2:
- rx_cmp --;
- case 1:
- rx_cmp --;
- }
- if (*rx_cmp == obj->char_match) {
- obj->char_found = 1;
- break;
- }
- }
- }
-
- if (n_words) {
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- }
- }
-
- return n_words;
-}
-
-static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
-{
- obj->tx_buff.buffer = (void *) tx;
- obj->tx_buff.length = length;
- obj->tx_buff.pos = 0;
- obj->tx_buff.width = width;
-}
-
-static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
-{
- obj->rx_buff.buffer = rx;
- obj->rx_buff.length = length;
- obj->rx_buff.pos = 0;
- obj->rx_buff.width = width;
-}
-
-static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- // Necessary for both interrupt way and DMA way
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
- // With our own async vector, tx/rx handlers can be different.
- obj->serial.vec = var->vec_async;
- obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
- serial_irq_set(obj, TxIrq, enable);
-}
-
-static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- // Necessary for both interrupt way and DMA way
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
- // With our own async vector, tx/rx handlers can be different.
- obj->serial.vec = var->vec_async;
- obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
- serial_irq_set(obj, RxIrq, enable);
-}
-
-static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
-{
- if (*dma_usage != DMA_USAGE_NEVER) {
- if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
- }
- if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_usage = DMA_USAGE_NEVER;
- }
- }
- else {
- dma_channel_free(*dma_ch);
- *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
- }
-}
-
-static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
-{
- int inten_msk = 0;
-
- switch (irq) {
- case RxIrq:
- inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
- break;
- case TxIrq:
- inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
- break;
- }
-
- return !! inten_msk;
-}
-
-#endif // #if DEVICE_SERIAL_ASYNCH
-#endif // #if DEVICE_SERIAL
--- a/targets/TARGET_NUVOTON/TARGET_M451/sleep.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,118 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "sleep_api.h"
-#include "serial_api.h"
-#include "lp_ticker_api.h"
-
-#if DEVICE_SLEEP
-
-#include "cmsis.h"
-#include "device.h"
-#include "objects.h"
-#include "PeripheralPins.h"
-
-void us_ticker_prepare_sleep(struct sleep_s *obj);
-void us_ticker_wakeup_from_sleep(struct sleep_s *obj);
-static void mbed_enter_sleep(struct sleep_s *obj);
-static void mbed_exit_sleep(struct sleep_s *obj);
-
-int serial_allow_powerdown(void);
-int spi_allow_powerdown(void);
-int i2c_allow_powerdown(void);
-int pwmout_allow_powerdown(void);
-
-/**
- * Enter Idle mode.
- */
-void sleep(void)
-{
- struct sleep_s sleep_obj;
- sleep_obj.powerdown = 0;
- mbed_enter_sleep(&sleep_obj);
- mbed_exit_sleep(&sleep_obj);
-}
-
-/**
- * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
- */
-void deepsleep(void)
-{
- struct sleep_s sleep_obj;
- sleep_obj.powerdown = 1;
- mbed_enter_sleep(&sleep_obj);
- mbed_exit_sleep(&sleep_obj);
-}
-
-
-void mbed_enter_sleep(struct sleep_s *obj)
-{
- // Check if serial allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = serial_allow_powerdown();
- }
- // Check if spi allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = spi_allow_powerdown();
- }
- // Check if i2c allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = i2c_allow_powerdown();
- }
- // Check if pwmout allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = pwmout_allow_powerdown();
- }
- // TODO: Check if other peripherals allow entering power-down mode
-
- obj->start_us = lp_ticker_read();
- // Let us_ticker prepare for power-down or reject it.
- us_ticker_prepare_sleep(obj);
-
- // NOTE(STALE): To pass mbed-drivers test, timer requires to be fine-grained, so its implementation needs HIRC rather than LIRC/LXT as its clock source.
- // But as CLK_PowerDown()/CLK_Idle() is called, HIRC will be disabled and timer cannot keep counting and alarm. To overcome the dilemma,
- // just make CPU halt and compromise power saving.
- // NOTE: As CLK_PowerDown()/CLK_Idle() is called, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
-
- if (obj->powerdown) { // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
- SYS_UnlockReg();
- CLK_PowerDown();
- SYS_LockReg();
- }
- else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
- SYS_UnlockReg();
- CLK_Idle();
- SYS_LockReg();
- }
- __NOP();
- __NOP();
- __NOP();
- __NOP();
-
- obj->end_us = lp_ticker_read();
- obj->period_us = (obj->end_us > obj->start_us) ? (obj->end_us - obj->start_us) : (uint32_t) ((uint64_t) obj->end_us + 0xFFFFFFFFu - obj->start_us);
- // Let us_ticker recover from power-down.
- us_ticker_wakeup_from_sleep(obj);
-}
-
-void mbed_exit_sleep(struct sleep_s *obj)
-{
- // TODO: TO BE CONTINUED
-
- (void)obj;
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,775 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "spi_api.h"
-
-#if DEVICE_SPI
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "nu_bitutil.h"
-
-#if DEVICE_SPI_ASYNCH
-#include "dma_api.h"
-#include "dma.h"
-#endif
-
-#define NU_SPI_FRAME_MIN 8
-#define NU_SPI_FRAME_MAX 32
-#define NU_SPI_FIFO_DEPTH 8
-
-struct nu_spi_var {
-#if DEVICE_SPI_ASYNCH
- uint8_t pdma_perp_tx;
- uint8_t pdma_perp_rx;
-#endif
-};
-
-static struct nu_spi_var spi0_var = {
-#if DEVICE_SPI_ASYNCH
- .pdma_perp_tx = PDMA_SPI0_TX,
- .pdma_perp_rx = PDMA_SPI0_RX
-#endif
-};
-static struct nu_spi_var spi1_var = {
-#if DEVICE_SPI_ASYNCH
- .pdma_perp_tx = PDMA_SPI1_TX,
- .pdma_perp_rx = PDMA_SPI1_RX
-#endif
-};
-static struct nu_spi_var spi2_var = {
-#if DEVICE_SPI_ASYNCH
- .pdma_perp_tx = PDMA_SPI2_TX,
- .pdma_perp_rx = PDMA_SPI2_RX
-#endif
-};
-
-#if DEVICE_SPI_ASYNCH
-static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
-static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable);
-static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
-static uint32_t spi_master_read_asynch(spi_t *obj);
-static uint32_t spi_event_check(spi_t *obj);
-static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
-static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
-static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
-static uint8_t spi_get_data_width(spi_t *obj);
-static int spi_is_tx_complete(spi_t *obj);
-static int spi_is_rx_complete(spi_t *obj);
-static int spi_writeable(spi_t * obj);
-static int spi_readable(spi_t * obj);
-static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
-static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
-#endif
-
-static uint32_t spi_modinit_mask = 0;
-
-static const struct nu_modinit_s spi_modinit_tab[] = {
- {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var},
- {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK1, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var},
- {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK0, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
- // Determine which SPI_x the pins are used for
- uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
- uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
- uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
- uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
- uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
- uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
- obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
- MBED_ASSERT((int)obj->spi.spi != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Select IP clock source
- CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- pinmap_pinout(mosi, PinMap_SPI_MOSI);
- pinmap_pinout(miso, PinMap_SPI_MISO);
- pinmap_pinout(sclk, PinMap_SPI_SCLK);
- pinmap_pinout(ssel, PinMap_SPI_SSEL);
-
- obj->spi.pin_mosi = mosi;
- obj->spi.pin_miso = miso;
- obj->spi.pin_sclk = sclk;
- obj->spi.pin_ssel = ssel;
-
-
- // Configure the SPI data format and frequency
- //spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
- //spi_frequency(obj, 1000000);
-
-#if DEVICE_SPI_ASYNCH
- obj->spi.dma_usage = DMA_USAGE_NEVER;
- obj->spi.event = 0;
- obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
-#endif
-
- // Mark this module to be inited.
- int i = modinit - spi_modinit_tab;
- spi_modinit_mask |= 1 << i;
-}
-
-void spi_free(spi_t *obj)
-{
-#if DEVICE_SPI_ASYNCH
- if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->spi.dma_chn_id_tx);
- obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- }
- if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->spi.dma_chn_id_rx);
- obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-#endif
-
- SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK));
- NVIC_DisableIRQ(modinit->irq_n);
-
- // Disable IP clock
- CLK_DisableModuleClock(modinit->clkidx);
-
- //((struct nu_spi_var *) modinit->var)->obj = NULL;
-
- // Mark this module to be deinited.
- int i = modinit - spi_modinit_tab;
- spi_modinit_mask &= ~(1 << i);
-}
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
- MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
-
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- // NOTE 1: All configurations should be ready before enabling SPI peripheral.
- // NOTE 2: Re-configuration is allowed only as SPI peripheral is idle.
- while (SPI_IS_BUSY(spi_base));
- SPI_DISABLE(spi_base);
-
- SPI_Open(spi_base,
- slave ? SPI_SLAVE : SPI_MASTER,
- (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
- bits,
- SPI_GetBusClock(spi_base));
- // NOTE: Hardcode to be MSB first.
- SPI_SET_MSB_FIRST(spi_base);
-
- if (! slave) {
- // Master
- if (obj->spi.pin_ssel != NC) {
- // Configure SS as low active.
- SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW);
- }
- else {
- SPI_DisableAutoSS(spi_base);
- }
- }
- else {
- // Slave
- // Configure SS as low active.
- spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
- }
-
- // NOTE: M451's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). This will violate judgement of spi_active(). Disable it.
- SPI_DISABLE(spi_base);
-}
-
-void spi_frequency(spi_t *obj, int hz)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- while (SPI_IS_BUSY(spi_base));
- SPI_DISABLE(spi_base);
-
- SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
-}
-
-
-int spi_master_write(spi_t *obj, int value)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- // NOTE: Data in receive FIFO can be read out via ICE.
- SPI_ENABLE(spi_base);
-
- // Wait for tx buffer empty
- while(! spi_writeable(obj));
- SPI_WRITE_TX(spi_base, value);
-
- // Wait for rx buffer full
- while (! spi_readable(obj));
- int value2 = SPI_READ_RX(spi_base);
-
- SPI_DISABLE(spi_base);
-
- return value2;
-}
-
-#if DEVICE_SPISLAVE
-int spi_slave_receive(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- SPI_ENABLE(spi_base);
-
- return spi_readable(obj);
-};
-
-int spi_slave_read(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- SPI_ENABLE(spi_base);
-
- // Wait for rx buffer full
- while (! spi_readable(obj));
- int value = SPI_READ_RX(spi_base);
- return value;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- SPI_ENABLE(spi_base);
-
- // Wait for tx buffer empty
- while(! spi_writeable(obj));
- SPI_WRITE_TX(spi_base, value);
-}
-#endif
-
-#if DEVICE_SPI_ASYNCH
-void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
-{
- //MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
- SPI_SET_DATA_WIDTH(spi_base, bit_width);
-
- obj->spi.dma_usage = hint;
- spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
- uint32_t data_width = spi_get_data_width(obj);
- // Conditions to go DMA way:
- // (1) No DMA support for non-8 multiple data width.
- // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
- if ((data_width % 8) ||
- (tx_length < rx_length)) {
- obj->spi.dma_usage = DMA_USAGE_NEVER;
- dma_channel_free(obj->spi.dma_chn_id_tx);
- obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- dma_channel_free(obj->spi.dma_chn_id_rx);
- obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-
- // SPI IRQ is necessary for both interrupt way and DMA way
- spi_enable_event(obj, event, 1);
- spi_buffer_set(obj, tx, tx_length, rx, rx_length);
-
- SPI_ENABLE(spi_base);
-
- if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
- // Interrupt way
- spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
- spi_enable_vector_interrupt(obj, handler, 1);
- spi_master_enable_interrupt(obj, 1);
- } else {
- // DMA way
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- // Configure tx DMA
- PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
- ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
- (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- tx_length);
- PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
- (uint32_t) tx, // NOTE:
- // NUC472: End of source address
- // M451: Start of source address
- PDMA_SAR_INC, // Source address incremental
- (uint32_t) &spi_base->TX, // Destination address
- PDMA_DAR_FIX); // Destination address fixed
- PDMA_SetBurstType(obj->spi.dma_chn_id_tx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->spi.dma_chn_id_tx,
- PDMA_INT_TRANS_DONE); // Interrupt type
- // Register DMA event handler
- dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
-
- // Configure rx DMA
- PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
- ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
- (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- rx_length);
- PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
- (uint32_t) &spi_base->RX, // Source address
- PDMA_SAR_FIX, // Source address fixed
- (uint32_t) rx, // NOTE:
- // NUC472: End of destination address
- // M451: Start of destination address
- PDMA_DAR_INC); // Destination address incremental
- PDMA_SetBurstType(obj->spi.dma_chn_id_rx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->spi.dma_chn_id_rx,
- PDMA_INT_TRANS_DONE); // Interrupt type
- // Register DMA event handler
- dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
-
- // Start tx/rx DMA transfer
- spi_enable_vector_interrupt(obj, handler, 1);
- // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
- SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
- SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
- spi_master_enable_interrupt(obj, 1);
- }
-}
-
-/**
- * Abort an SPI transfer
- * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
- * transfers
- * @param[in] obj The SPI peripheral to stop
- */
-void spi_abort_asynch(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
- // Receive FIFO Overrun in case of tx length > rx length on DMA way
- if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
- spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
- }
-
- if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0);
- // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->spi.dma_chn_id_tx);
- PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
- }
- SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
-
- if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0);
- // FIXME: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->spi.dma_chn_id_rx);
- PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
- }
- SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
- }
-
- // Necessary for both interrupt way and DMA way
- spi_enable_vector_interrupt(obj, 0, 0);
- spi_master_enable_interrupt(obj, 0);
-
- // FIXME: SPI H/W may get out of state without the busy check.
- while (SPI_IS_BUSY(spi_base));
- SPI_DISABLE(spi_base);
-
- SPI_ClearRxFIFO(spi_base);
- SPI_ClearTxFIFO(spi_base);
-}
-
-/**
- * Handle the SPI interrupt
- * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way,
- * it is unlikely that the RX FIFO will overflow.
- * @param[in] obj The SPI peripheral that generated the interrupt
- * @return
- */
-uint32_t spi_irq_handler_asynch(spi_t *obj)
-{
- // Check for SPI events
- uint32_t event = spi_event_check(obj);
- if (event) {
- spi_abort_asynch(obj);
- }
-
- return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
-}
-
-uint8_t spi_active(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
- // FIXME
- /*
- if ((obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length)
- || (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) ){
- return 1;
- } else {
- // interrupts are disabled, all transaction have been completed
- // TODO: checking rx fifo, it reports data eventhough RFDF is not set
- return DSPI_HAL_GetIntMode(obj->spi.address, kDspiRxFifoDrainRequest);
- }*/
-
- //return SPI_IS_BUSY(spi_base);
- return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
-}
-
-int spi_allow_powerdown(void)
-{
- uint32_t modinit_mask = spi_modinit_mask;
- while (modinit_mask) {
- int spi_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
- if (modinit->modname != NC) {
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
- // Disallow entering power-down mode if SPI transfer is enabled.
- if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << spi_idx);
- }
-
- return 1;
-}
-
-static int spi_writeable(spi_t * obj)
-{
- // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
- //return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))) && (SPI_GET_RX_FIFO_COUNT(((SPI_T *) NU_MODBASE(obj->spi.spi))) < NU_SPI_FIFO_DEPTH);
- return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
-}
-
-static int spi_readable(spi_t * obj)
-{
- return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
-}
-
-static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
-{
- obj->spi.event &= ~SPI_EVENT_ALL;
- obj->spi.event |= (event & SPI_EVENT_ALL);
- if (event & SPI_EVENT_RX_OVERFLOW) {
- SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK);
- }
-}
-
-static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- if (enable) {
- NVIC_SetVector(modinit->irq_n, handler);
- NVIC_EnableIRQ(modinit->irq_n);
- }
- else {
- //NVIC_SetVector(modinit->irq_n, handler);
- NVIC_DisableIRQ(modinit->irq_n);
- }
-}
-
-static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- if (enable) {
- // For SPI0, it could be 0 ~ 7. For SPI1 and SPI2, it could be 0 ~ 3.
- if (spi_base == (SPI_T *) SPI0_BASE) {
- SPI_SetFIFO(spi_base, 4, 4);
- }
- else {
- SPI_SetFIFO(spi_base, 2, 2);
- }
- //SPI_SET_SUSPEND_CYCLE(spi_base, 4);
- // Enable tx/rx FIFO threshold interrupt
- SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
- }
- else {
- SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK);
- }
-}
-
-static uint32_t spi_event_check(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
- uint32_t event = 0;
-
- if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
- uint32_t n_rec = spi_master_read_asynch(obj);
- spi_master_write_asynch(obj, n_rec);
- }
-
- if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
- event |= SPI_EVENT_COMPLETE;
- }
-
- // Receive FIFO Overrun
- if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
- spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
- // In case of tx length > rx length on DMA way
- if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
- event |= SPI_EVENT_RX_OVERFLOW;
- }
- }
-
- // Receive Time-Out
- if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
- spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
- //event |= SPI_EVENT_ERROR;
- }
- // Transmit FIFO Under-Run
- if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
- spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
- event |= SPI_EVENT_ERROR;
- }
-
- return event;
-}
-
-/**
- * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
- * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
- * @param[in] obj The SPI object on which to operate
- * @param[in] tx_limit The maximum number of words to send
- * @return The number of SPI words that have been transfered
- */
-static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
-{
- uint32_t n_words = 0;
- uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
- uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
- uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
- max_tx = NU_MIN(max_tx, tx_limit);
- uint8_t data_width = spi_get_data_width(obj);
- uint8_t bytes_per_word = (data_width + 7) / 8;
- uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- while ((n_words < max_tx) && spi_writeable(obj)) {
- if (spi_is_tx_complete(obj)) {
- // Transmit dummy as transmit buffer is empty
- SPI_WRITE_TX(spi_base, 0);
- }
- else {
- switch (bytes_per_word) {
- case 4:
- SPI_WRITE_TX(spi_base, nu_get32_le(tx));
- tx += 4;
- break;
- case 2:
- SPI_WRITE_TX(spi_base, nu_get16_le(tx));
- tx += 2;
- break;
- case 1:
- SPI_WRITE_TX(spi_base, *((uint8_t *) tx));
- tx += 1;
- break;
- }
-
- obj->tx_buff.pos ++;
- }
- n_words ++;
- }
-
- //Return the number of words that have been sent
- return n_words;
-}
-
-/**
- * Read SPI words out of the RX FIFO
- * Continues reading words out of the RX FIFO until the following condition is met:
- * o There are no more words in the FIFO
- * OR BOTH OF:
- * o At least as many words as the TX buffer have been received
- * o At least as many words as the RX buffer have been received
- * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
- * @param[in] obj The SPI object on which to operate
- * @return Returns the number of words extracted from the RX FIFO
- */
-static uint32_t spi_master_read_asynch(spi_t *obj)
-{
- uint32_t n_words = 0;
- uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
- uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
- uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
- uint8_t data_width = spi_get_data_width(obj);
- uint8_t bytes_per_word = (data_width + 7) / 8;
- uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- while ((n_words < max_rx) && spi_readable(obj)) {
- if (spi_is_rx_complete(obj)) {
- // Disregard as receive buffer is full
- SPI_READ_RX(spi_base);
- }
- else {
- switch (bytes_per_word) {
- case 4: {
- uint32_t val = SPI_READ_RX(spi_base);
- nu_set32_le(rx, val);
- rx += 4;
- break;
- }
- case 2: {
- uint16_t val = SPI_READ_RX(spi_base);
- nu_set16_le(rx, val);
- rx += 2;
- break;
- }
- case 1:
- *rx ++ = SPI_READ_RX(spi_base);
- break;
- }
-
- obj->rx_buff.pos ++;
- }
- n_words ++;
- }
-
- // Return the number of words received
- return n_words;
-}
-
-static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
-{
- obj->tx_buff.buffer = (void *) tx;
- obj->tx_buff.length = tx_length;
- obj->tx_buff.pos = 0;
- obj->tx_buff.width = spi_get_data_width(obj);
- obj->rx_buff.buffer = rx;
- obj->rx_buff.length = rx_length;
- obj->rx_buff.pos = 0;
- obj->rx_buff.width = spi_get_data_width(obj);
-}
-
-static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
-{
- if (*dma_usage != DMA_USAGE_NEVER) {
- if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
- }
- if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
- }
-
- if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_usage = DMA_USAGE_NEVER;
- }
- }
-
- if (*dma_usage == DMA_USAGE_NEVER) {
- dma_channel_free(*dma_ch_tx);
- *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
- dma_channel_free(*dma_ch_rx);
- *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-}
-
-static uint8_t spi_get_data_width(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- return ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
-}
-
-static int spi_is_tx_complete(spi_t *obj)
-{
- // ???: Exclude tx fifo empty check due to no such interrupt on DMA way
- return (obj->tx_buff.pos == obj->tx_buff.length);
- //return (obj->tx_buff.pos == obj->tx_buff.length && SPI_GET_TX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
-}
-
-static int spi_is_rx_complete(spi_t *obj)
-{
- return (obj->rx_buff.pos == obj->rx_buff.length);
-}
-
-static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
-{
- spi_t *obj = (spi_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect SPI IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->tx_buff.pos = obj->tx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
- vec();
-}
-
-static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
-{
- spi_t *obj = (spi_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect SPI IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->rx_buff.pos = obj->rx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
- vec();
-}
-
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,282 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "us_ticker_api.h"
-#include "sleep_api.h"
-#include "mbed_assert.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "critical.h"
-
-// us_ticker tick = us = timestamp
-#define US_PER_TICK 1
-#define US_PER_SEC (1000 * 1000)
-
-#define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1LORES_CLK_PER_SEC (__LIRC)
-
-#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
-#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
-#define US_PER_TMR1LORES_CLK (US_PER_SEC / TMR1LORES_CLK_PER_SEC)
-
-#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
-#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
-
-
-// Determine to use lo-res/hi-res timer according to CD period
-#define US_TMR_SEP_CD 1000
-
-static void tmr0_vec(void);
-static void tmr1_vec(void);
-static void us_ticker_arm_cd(void);
-
-static int us_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t pd_comp_us = 0; // Power-down compenstaion for normal counter
-static volatile uint32_t cd_major_minor_us = 0;
-static volatile uint32_t cd_minor_us = 0;
-static volatile int cd_hires_tmr_armed = 0; // Flag of armed or not of hi-res timer for CD counter
-
-// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
-// NOTE: Choose clock source of timer:
-// 1. HIRC: Be the most accurate but might cause unknown HardFault.
-// 2. HXT: Less accurate and cannot pass mbed-drivers test.
-// 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
-// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
-static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-static const struct nu_modinit_s timer1lores_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
-static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
-
-#define TMR_CMP_MIN 2
-#define TMR_CMP_MAX 0xFFFFFFu
-
-void us_ticker_init(void)
-{
- if (us_ticker_inited) {
- return;
- }
-
- counter_major = 0;
- pd_comp_us = 0;
- cd_major_minor_us = 0;
- cd_minor_us = 0;
- cd_hires_tmr_armed = 0;
- us_ticker_inited = 1;
-
- // Reset IP
- SYS_ResetModule(timer0hires_modinit.rsetidx);
- SYS_ResetModule(timer1lores_modinit.rsetidx);
-
- // Select IP clock source
- CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
- CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
- // Enable IP clock
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- CLK_EnableModuleClock(timer1lores_modinit.clkidx);
-
- // Timer for normal counter
- uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
- MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
- uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
- MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
-
- NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
- NVIC_SetVector(timer1lores_modinit.irq_n, (uint32_t) timer1lores_modinit.var);
-
- NVIC_EnableIRQ(timer0hires_modinit.irq_n);
- NVIC_EnableIRQ(timer1lores_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
-}
-
-uint32_t us_ticker_read()
-{
- if (! us_ticker_inited) {
- us_ticker_init();
- }
-
- TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
-
- do {
- uint32_t major_minor_us;
- uint32_t minor_us;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
- uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
- major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
- }
- else {
- major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
-
- // Add power-down compensation
- return (major_minor_us + pd_comp_us) / US_PER_TICK;
- }
- while (0);
-}
-
-void us_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-}
-
-void us_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-}
-
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
- cd_hires_tmr_armed = 0;
-
- int delta = (int) (timestamp - us_ticker_read());
- if (delta > 0) {
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
- }
- else {
- cd_major_minor_us = cd_minor_us = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer1lores_modinit.irq_n);
- }
-}
-
-void us_ticker_prepare_sleep(struct sleep_s *obj)
-{
- // Reject power-down if hi-res timer (HIRC/HXT) is now armed for CD counter.
- if (obj->powerdown) {
- obj->powerdown = ! cd_hires_tmr_armed;
- }
-
- core_util_critical_section_enter();
-
- if (obj->powerdown) {
- // NOTE: On entering power-down mode, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
- // To not be inconsistent due to above, always disable clock source of normal counter, and then re-enable it and make compensation on wakeup from power-down.
- CLK_DisableModuleClock(timer0hires_modinit.clkidx);
- }
-
- core_util_critical_section_exit();
-}
-
-void us_ticker_wakeup_from_sleep(struct sleep_s *obj)
-{
- core_util_critical_section_enter();
-
- if (obj->powerdown) {
- // Calculate power-down compensation
- pd_comp_us += obj->period_us;
-
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- }
-
- core_util_critical_section_exit();
-}
-
-static void tmr0_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- counter_major ++;
-}
-
-static void tmr1_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
- cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
- cd_hires_tmr_armed = 0;
- if (cd_major_minor_us == 0) {
- // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
- us_ticker_irq_handler();
- }
- else {
- us_ticker_arm_cd();
- }
-}
-
-static void us_ticker_arm_cd(void)
-{
- TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1lores_modinit.modname);
- uint32_t tmr1_clk_per_sec;
- uint32_t us_per_tmr1_clk;
-
- /**
- * Reserve US_TMR_SEP_CD-plus alarm period for hi-res timer
- * 1. period >= US_TMR_SEP_CD * 2. Divide into two rounds:
- * US_TMR_SEP_CD * n (lo-res timer)
- * US_TMR_SEP_CD + period % US_TMR_SEP_CD (hi-res timer)
- * 2. period < US_TMR_SEP_CD * 2. Just one round:
- * period (hi-res timer)
- */
- if (cd_major_minor_us >= US_TMR_SEP_CD * 2) {
- cd_minor_us = cd_major_minor_us - cd_major_minor_us % US_TMR_SEP_CD - US_TMR_SEP_CD;
-
- CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
- tmr1_clk_per_sec = TMR1LORES_CLK_PER_SEC;
- us_per_tmr1_clk = US_PER_TMR1LORES_CLK;
-
- cd_hires_tmr_armed = 0;
- }
- else {
- cd_minor_us = cd_major_minor_us;
-
- CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
- tmr1_clk_per_sec = TMR1HIRES_CLK_PER_SEC;
- us_per_tmr1_clk = US_PER_TMR1HIRES_CLK;
-
- cd_hires_tmr_armed = 1;
- }
-
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 MHz
- uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
- uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_per_sec - 1;
- MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
- MBED_ASSERT((clk_timer1 % tmr1_clk_per_sec) == 0);
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
- timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
-
- uint32_t cmp_timer1 = cd_minor_us / us_per_tmr1_clk;
- cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
- timer1_base->CMP = cmp_timer1;
-
- TIMER_EnableInt(timer1_base);
- TIMER_Start(timer1_base);
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralNames.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,132 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// NOTE: TIMER0_BASE=(APBPERIPH_BASE + 0x10000)
-// TIMER1_BASE=(APBPERIPH_BASE + 0x10020)
-#define NU_MODNAME(MODBASE, SUBINDEX) ((MODBASE) | (SUBINDEX))
-#define NU_MODBASE(MODNAME) ((MODNAME) & 0xFFFFFFE0)
-#define NU_MODSUBINDEX(MODNAME) ((MODNAME) & 0x0000001F)
-
-#if 0
-typedef enum {
- GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0),
- GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 0),
- GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 0),
- GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 0),
- GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 0),
- GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 0),
- GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 0),
- GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 0),
- GPIO_I = (int) NU_MODNAME(GPIOI_BASE, 0)
-} GPIOName;
-#endif
-
-typedef enum {
- ADC_0_0 = (int) NU_MODNAME(ADC_BASE, 0),
- ADC_0_1 = (int) NU_MODNAME(ADC_BASE, 1),
- ADC_0_2 = (int) NU_MODNAME(ADC_BASE, 2),
- ADC_0_3 = (int) NU_MODNAME(ADC_BASE, 3),
- ADC_0_4 = (int) NU_MODNAME(ADC_BASE, 4),
- ADC_0_5 = (int) NU_MODNAME(ADC_BASE, 5),
- ADC_0_6 = (int) NU_MODNAME(ADC_BASE, 6),
- ADC_0_7 = (int) NU_MODNAME(ADC_BASE, 7),
- ADC_0_8 = (int) NU_MODNAME(ADC_BASE, 8),
- ADC_0_9 = (int) NU_MODNAME(ADC_BASE, 9),
- ADC_0_10 = (int) NU_MODNAME(ADC_BASE, 10),
- ADC_0_11 = (int) NU_MODNAME(ADC_BASE, 11)
-} ADCName;
-
-typedef enum {
- UART_0 = (int) NU_MODNAME(UART0_BASE, 0),
- UART_1 = (int) NU_MODNAME(UART1_BASE, 0),
- UART_2 = (int) NU_MODNAME(UART2_BASE, 0),
- UART_3 = (int) NU_MODNAME(UART3_BASE, 0),
- UART_4 = (int) NU_MODNAME(UART4_BASE, 0),
- UART_5 = (int) NU_MODNAME(UART5_BASE, 0),
- // FIXME: board-specific
- STDIO_UART = UART_3
-} UARTName;
-
-typedef enum {
- SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0),
- SPI_1 = (int) NU_MODNAME(SPI1_BASE, 0),
- SPI_2 = (int) NU_MODNAME(SPI2_BASE, 0),
- SPI_3 = (int) NU_MODNAME(SPI3_BASE, 0)
-} SPIName;
-
-typedef enum {
- I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0),
- I2C_1 = (int) NU_MODNAME(I2C1_BASE, 0),
- I2C_2 = (int) NU_MODNAME(I2C2_BASE, 0),
- I2C_3 = (int) NU_MODNAME(I2C3_BASE, 0),
- I2C_4 = (int) NU_MODNAME(I2C4_BASE, 0)
-} I2CName;
-
-typedef enum {
- PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0),
- PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 1),
- PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 2),
- PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 3),
- PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 4),
- PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 5),
-
- PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 0),
- PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1),
- PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 2),
- PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 3),
- PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 4),
- PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 5)
-} PWMName;
-
-typedef enum {
- TIMER_0 = (int) NU_MODNAME(TIMER0_BASE, 0),
- TIMER_1 = (int) NU_MODNAME(TIMER1_BASE, 0),
- TIMER_2 = (int) NU_MODNAME(TIMER2_BASE, 0),
- TIMER_3 = (int) NU_MODNAME(TIMER3_BASE, 0)
-} TIMERName;
-
-typedef enum {
- RTC_0 = (int) NU_MODNAME(RTC_BASE, 0)
-} RTCName;
-
-typedef enum {
- DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0)
-} DMAName;
-
-typedef enum {
- SD_0_0 = (int) NU_MODNAME(SD_BASE, 0),
- SD_0_1 = (int) NU_MODNAME(SD_BASE, 1)
-} SDName;
-
-typedef enum {
- CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0),
- CAN_1 = (int) NU_MODNAME(CAN1_BASE, 0)
-} CANName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,531 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-// If you change them, you will have also to modify the corresponding xxx_api.c file
-// for pwmout, analogin, analogout, ...
-// =====
-
-#if 0
-//*** GPIO ***
-const PinMap PinMap_GPIO[] = {
- // GPIO A MFPL
- {PA_0, GPIO_A, SYS_GPA_MFPL_PA0MFP_GPIO},
- {PA_1, GPIO_A, SYS_GPA_MFPL_PA1MFP_GPIO},
- {PA_2, GPIO_A, SYS_GPA_MFPL_PA2MFP_GPIO},
- {PA_3, GPIO_A, SYS_GPA_MFPL_PA3MFP_GPIO},
- {PA_4, GPIO_A, SYS_GPA_MFPL_PA4MFP_GPIO},
- {PA_5, GPIO_A, SYS_GPA_MFPL_PA5MFP_GPIO},
- {PA_6, GPIO_A, SYS_GPA_MFPL_PA6MFP_GPIO},
- {PA_7, GPIO_A, SYS_GPA_MFPL_PA7MFP_GPIO},
- // GPIO A MFPH
- {PA_8, GPIO_A, SYS_GPA_MFPH_PA8MFP_GPIO},
- {PA_9, GPIO_A, SYS_GPA_MFPH_PA9MFP_GPIO},
- {PA_10, GPIO_A, SYS_GPA_MFPH_PA10MFP_GPIO},
- {PA_11, GPIO_A, SYS_GPA_MFPH_PA11MFP_GPIO},
- {PA_12, GPIO_A, SYS_GPA_MFPH_PA12MFP_GPIO},
- {PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO},
- {PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO},
- {PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO},
-
- // GPIO B MFPL
- {PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO},
- {PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO},
- {PB_2, GPIO_B, SYS_GPB_MFPL_PB2MFP_GPIO},
- {PB_3, GPIO_B, SYS_GPB_MFPL_PB3MFP_GPIO},
- {PB_4, GPIO_B, SYS_GPB_MFPL_PB4MFP_GPIO},
- {PB_5, GPIO_B, SYS_GPB_MFPL_PB5MFP_GPIO},
- {PB_6, GPIO_B, SYS_GPB_MFPL_PB6MFP_GPIO},
- {PB_7, GPIO_B, SYS_GPB_MFPL_PB7MFP_GPIO},
- // GPIO B MFPH
- {PB_8, GPIO_B, SYS_GPB_MFPH_PB8MFP_GPIO},
- {PB_9, GPIO_B, SYS_GPB_MFPH_PB9MFP_GPIO},
- {PB_10, GPIO_B, SYS_GPB_MFPH_PB10MFP_GPIO},
- {PB_11, GPIO_B, SYS_GPB_MFPH_PB11MFP_GPIO},
- {PB_12, GPIO_B, SYS_GPB_MFPH_PB12MFP_GPIO},
- {PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO},
- {PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO},
- {PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO},
-
- // GPIO C MFPL
- {PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO},
- {PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO},
- {PC_2, GPIO_C, SYS_GPC_MFPL_PC2MFP_GPIO},
- {PC_3, GPIO_C, SYS_GPC_MFPL_PC3MFP_GPIO},
- {PC_4, GPIO_C, SYS_GPC_MFPL_PC4MFP_GPIO},
- {PC_5, GPIO_C, SYS_GPC_MFPL_PC5MFP_GPIO},
- {PC_6, GPIO_C, SYS_GPC_MFPL_PC6MFP_GPIO},
- {PC_7, GPIO_C, SYS_GPC_MFPL_PC7MFP_GPIO},
- // GPIO C MFPH
- {PC_8, GPIO_C, SYS_GPC_MFPH_PC8MFP_GPIO},
- {PC_9, GPIO_C, SYS_GPC_MFPH_PC9MFP_GPIO},
- {PC_10, GPIO_C, SYS_GPC_MFPH_PC10MFP_GPIO},
- {PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO},
- {PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO},
- {PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO},
- {PC_14, GPIO_C, SYS_GPC_MFPH_PC14MFP_GPIO},
- {PC_15, GPIO_C, SYS_GPC_MFPH_PC15MFP_GPIO},
-
- // GPIO D MFPL
- {PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO},
- {PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO},
- {PD_2, GPIO_D, SYS_GPD_MFPL_PD2MFP_GPIO},
- {PD_3, GPIO_D, SYS_GPD_MFPL_PD3MFP_GPIO},
- {PD_4, GPIO_D, SYS_GPD_MFPL_PD4MFP_GPIO},
- {PD_5, GPIO_D, SYS_GPD_MFPL_PD5MFP_GPIO},
- {PD_6, GPIO_D, SYS_GPD_MFPL_PD6MFP_GPIO},
- {PD_7, GPIO_D, SYS_GPD_MFPL_PD7MFP_GPIO},
- // GPIO D MFPH
- {PD_8, GPIO_D, SYS_GPD_MFPH_PD8MFP_GPIO},
- {PD_9, GPIO_D, SYS_GPD_MFPH_PD9MFP_GPIO},
- {PD_10, GPIO_D, SYS_GPD_MFPH_PD10MFP_GPIO},
- {PD_11, GPIO_D, SYS_GPD_MFPH_PD11MFP_GPIO},
- {PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO},
- {PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO},
- {PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO},
- {PD_15, GPIO_D, SYS_GPD_MFPH_PD15MFP_GPIO},
-
- // GPIO E MFPL
- {PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO},
- {PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO},
- {PE_2, GPIO_E, SYS_GPE_MFPL_PE2MFP_GPIO},
- {PE_3, GPIO_E, SYS_GPE_MFPL_PE3MFP_GPIO},
- {PE_4, GPIO_E, SYS_GPE_MFPL_PE4MFP_GPIO},
- {PE_5, GPIO_E, SYS_GPE_MFPL_PE5MFP_GPIO},
- {PE_6, GPIO_E, SYS_GPE_MFPL_PE6MFP_GPIO},
- {PE_7, GPIO_E, SYS_GPE_MFPL_PE7MFP_GPIO},
- // GPIO E MFPH
- {PE_8, GPIO_E, SYS_GPE_MFPH_PE8MFP_GPIO},
- {PE_9, GPIO_E, SYS_GPE_MFPH_PE9MFP_GPIO},
- {PE_10, GPIO_E, SYS_GPE_MFPH_PE10MFP_GPIO},
- {PE_11, GPIO_E, SYS_GPE_MFPH_PE11MFP_GPIO},
- {PE_12, GPIO_E, SYS_GPE_MFPH_PE12MFP_GPIO},
- {PE_13, GPIO_E, SYS_GPE_MFPH_PE13MFP_GPIO},
- {PE_14, GPIO_E, SYS_GPE_MFPH_PE14MFP_GPIO},
- {PE_15, GPIO_E, SYS_GPE_MFPH_PE15MFP_GPIO},
-
- // GPIO F MFPL
- {PF_0, GPIO_F, SYS_GPF_MFPL_PF0MFP_GPIO},
- {PF_1, GPIO_F, SYS_GPF_MFPL_PF1MFP_GPIO},
- {PF_2, GPIO_F, SYS_GPF_MFPL_PF2MFP_GPIO},
- {PF_3, GPIO_F, SYS_GPF_MFPL_PF3MFP_GPIO},
- {PF_4, GPIO_F, SYS_GPF_MFPL_PF4MFP_GPIO},
- {PF_5, GPIO_F, SYS_GPF_MFPL_PF5MFP_GPIO},
- {PF_6, GPIO_F, SYS_GPF_MFPL_PF6MFP_GPIO},
- {PF_7, GPIO_F, SYS_GPF_MFPL_PF7MFP_GPIO},
- // GPIO F MFPH
- {PF_8, GPIO_F, SYS_GPF_MFPH_PF8MFP_GPIO},
- {PF_9, GPIO_F, SYS_GPF_MFPH_PF9MFP_GPIO},
- {PF_10, GPIO_F, SYS_GPF_MFPH_PF10MFP_GPIO},
- {PF_11, GPIO_F, SYS_GPF_MFPH_PF11MFP_GPIO},
- {PF_12, GPIO_F, SYS_GPF_MFPH_PF12MFP_GPIO},
- {PF_13, GPIO_F, SYS_GPF_MFPH_PF13MFP_GPIO},
- {PF_14, GPIO_F, SYS_GPF_MFPH_PF14MFP_GPIO},
- {PF_15, GPIO_F, SYS_GPF_MFPH_PF15MFP_GPIO},
-
- // GPIO G MFPL
- {PG_0, GPIO_G, SYS_GPG_MFPL_PG0MFP_GPIO},
- {PG_1, GPIO_G, SYS_GPG_MFPL_PG1MFP_GPIO},
- {PG_2, GPIO_G, SYS_GPG_MFPL_PG2MFP_GPIO},
- {PG_3, GPIO_G, SYS_GPG_MFPL_PG3MFP_GPIO},
- {PG_4, GPIO_G, SYS_GPG_MFPL_PG4MFP_GPIO},
- {PG_5, GPIO_G, SYS_GPG_MFPL_PG5MFP_GPIO},
- {PG_6, GPIO_G, SYS_GPG_MFPL_PG6MFP_GPIO},
- {PG_7, GPIO_G, SYS_GPG_MFPL_PG7MFP_GPIO},
- // GPIO G MFPH
- {PG_8, GPIO_G, SYS_GPG_MFPH_PG8MFP_GPIO},
- {PG_9, GPIO_G, SYS_GPG_MFPH_PG9MFP_GPIO},
- {PG_10, GPIO_G, SYS_GPG_MFPH_PG10MFP_GPIO},
- {PG_11, GPIO_G, SYS_GPG_MFPH_PG11MFP_GPIO},
- {PG_12, GPIO_G, SYS_GPG_MFPH_PG12MFP_GPIO},
- {PG_13, GPIO_G, SYS_GPG_MFPH_PG13MFP_GPIO},
- {PG_14, GPIO_G, SYS_GPG_MFPH_PG14MFP_GPIO},
- {PG_15, GPIO_G, SYS_GPG_MFPH_PG15MFP_GPIO},
-
- // GPIO H MFPL
- {PH_0, GPIO_H, SYS_GPH_MFPL_PH0MFP_GPIO},
- {PH_1, GPIO_H, SYS_GPH_MFPL_PH1MFP_GPIO},
- {PH_2, GPIO_H, SYS_GPH_MFPL_PH2MFP_GPIO},
- {PH_3, GPIO_H, SYS_GPH_MFPL_PH3MFP_GPIO},
- {PH_4, GPIO_H, SYS_GPH_MFPL_PH4MFP_GPIO},
- {PH_5, GPIO_H, SYS_GPH_MFPL_PH5MFP_GPIO},
- {PH_6, GPIO_H, SYS_GPH_MFPL_PH6MFP_GPIO},
- {PH_7, GPIO_H, SYS_GPH_MFPL_PH7MFP_GPIO},
- // GPIO H MFPH
- {PH_8, GPIO_H, SYS_GPH_MFPH_PH8MFP_GPIO},
- {PH_9, GPIO_H, SYS_GPH_MFPH_PH9MFP_GPIO},
- {PH_10, GPIO_H, SYS_GPH_MFPH_PH10MFP_GPIO},
- {PH_11, GPIO_H, SYS_GPH_MFPH_PH11MFP_GPIO},
- {PH_12, GPIO_H, SYS_GPH_MFPH_PH12MFP_GPIO},
- {PH_13, GPIO_H, SYS_GPH_MFPH_PH13MFP_GPIO},
- {PH_14, GPIO_H, SYS_GPH_MFPH_PH14MFP_GPIO},
- {PH_15, GPIO_H, SYS_GPH_MFPH_PH15MFP_GPIO},
-
- // GPIO I MFPL
- {PI_0, GPIO_I, SYS_GPI_MFPL_PI0MFP_GPIO},
- {PI_1, GPIO_I, SYS_GPI_MFPL_PI1MFP_GPIO},
- {PI_2, GPIO_I, SYS_GPI_MFPL_PI2MFP_GPIO},
- {PI_3, GPIO_I, SYS_GPI_MFPL_PI3MFP_GPIO},
- {PI_4, GPIO_I, SYS_GPI_MFPL_PI4MFP_GPIO},
- {PI_5, GPIO_I, SYS_GPI_MFPL_PI5MFP_GPIO},
- {PI_6, GPIO_I, SYS_GPI_MFPL_PI6MFP_GPIO},
- {PI_7, GPIO_I, SYS_GPI_MFPL_PI7MFP_GPIO},
- // GPIO I MFPI
- {PI_8, GPIO_I, SYS_GPI_MFPH_PI8MFP_GPIO},
- {PI_9, GPIO_I, SYS_GPI_MFPH_PI9MFP_GPIO},
- {PI_10, GPIO_I, SYS_GPI_MFPH_PI10MFP_GPIO},
- {PI_11, GPIO_I, SYS_GPI_MFPH_PI11MFP_GPIO},
- {PI_12, GPIO_I, SYS_GPI_MFPH_PI12MFP_GPIO},
- {PI_13, GPIO_I, SYS_GPI_MFPH_PI13MFP_GPIO},
- {PI_14, GPIO_I, SYS_GPI_MFPH_PI14MFP_GPIO},
- {PI_15, GPIO_I, SYS_GPI_MFPH_PI15MFP_GPIO},
-};
-#endif
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
- {PE_0, ADC_0_0, SYS_GPE_MFPL_PE0MFP_ADC0_0}, // ADC0_0
- {PE_1, ADC_0_1, SYS_GPE_MFPL_PE1MFP_ADC0_1}, // ADC0_1
- {PE_2, ADC_0_2, SYS_GPE_MFPL_PE2MFP_ADC0_2}, // ADC0_2
- {PE_3, ADC_0_3, SYS_GPE_MFPL_PE3MFP_ADC0_3}, // ADC0_3
- {PE_4, ADC_0_4, SYS_GPE_MFPL_PE4MFP_ADC0_4}, // ADC0_4
- {PE_5, ADC_0_5, SYS_GPE_MFPL_PE5MFP_ADC0_5}, // ADC0_5
- {PE_6, ADC_0_6, SYS_GPE_MFPL_PE6MFP_ADC0_6}, // ADC0_6
- {PE_7, ADC_0_7, SYS_GPE_MFPL_PE7MFP_ADC0_7}, // ADC0_7
-
- {PE_8, ADC_0_8, SYS_GPE_MFPH_PE8MFP_ADC1_0}, // ADC0_8/ADC1_0
- {PE_9, ADC_0_9, SYS_GPE_MFPH_PE9MFP_ADC1_1}, // ADC0_9/ADC1_1
- {PE_10, ADC_0_10, SYS_GPE_MFPH_PE10MFP_ADC1_2}, // ADC0_10/ADC1_2
- {PE_11, ADC_0_11, SYS_GPE_MFPH_PE11MFP_ADC1_3}, // ADC0_11/ADC1_3
-
- {NC, NC, 0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
- {PB_1, I2C_4, SYS_GPB_MFPL_PB1MFP_I2C4_SDA},
- {PB_7, I2C_2, SYS_GPB_MFPL_PB7MFP_I2C2_SDA},
- {PC_9, I2C_0, SYS_GPC_MFPH_PC9MFP_I2C0_SDA},
- {PD_3, I2C_3, SYS_GPD_MFPL_PD3MFP_I2C3_SDA},
- {PD_9, I2C_0, SYS_GPD_MFPH_PD9MFP_I2C0_SDA},
- {PD_12, I2C_4, SYS_GPD_MFPH_PD12MFP_I2C4_SDA},
- {PG_14, I2C_1, SYS_GPG_MFPH_PG14MFP_I2C1_SDA},
- {PH_1, I2C_1, SYS_GPH_MFPL_PH1MFP_I2C1_SDA},
- {PH_4, I2C_3, SYS_GPH_MFPL_PH4MFP_I2C3_SDA},
- {PI_8, I2C_2, SYS_GPI_MFPH_PI8MFP_I2C2_SDA},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
- {PA_15, I2C_0, SYS_GPA_MFPH_PA15MFP_I2C0_SCL},
- {PB_0, I2C_4, SYS_GPB_MFPL_PB0MFP_I2C4_SCL},
- {PB_6, I2C_2, SYS_GPB_MFPL_PB6MFP_I2C2_SCL},
- {PC_9, I2C_3, SYS_GPC_MFPH_PC9MFP_I2C3_SCL},
- {PD_2, I2C_3, SYS_GPD_MFPL_PD2MFP_I2C3_SCL},
- {PD_8, I2C_0, SYS_GPD_MFPH_PD8MFP_I2C0_SCL},
- {PD_10, I2C_4, SYS_GPD_MFPH_PD10MFP_I2C4_SCL},
- {PG_15, I2C_1, SYS_GPG_MFPH_PG15MFP_I2C1_SCL},
- {PH_0, I2C_1, SYS_GPH_MFPL_PH0MFP_I2C1_SCL},
- {PH_3, I2C_3, SYS_GPH_MFPL_PH3MFP_I2C3_SCL},
- {PI_7, I2C_2, SYS_GPI_MFPL_PI7MFP_I2C2_SCL},
-
- {NC, NC, 0}
-};
-
-//*** PWM ***
-
-const PinMap PinMap_PWM[] = {
- {PA_5, PWM_0_0, SYS_GPA_MFPL_PA5MFP_PWM0_CH0},
- {PA_6, PWM_0_1, SYS_GPA_MFPL_PA6MFP_PWM0_CH1},
- {PA_7, PWM_1_3, SYS_GPA_MFPL_PA7MFP_PWM1_CH3},
- //{PA_7, EPWM_0, SYS_GPA_MFPL_PA7MFP_EPWM0_CH5},
- //{PA_7, EPWM_0, SYS_GPA_MFPL_PA7MFP_EPWM0_CH5},
- {PA_8, PWM_1_2, SYS_GPA_MFPH_PA8MFP_PWM1_CH2},
- //{PA_8, EPWM_0, SYS_GPA_MFPH_PA8MFP_EPWM0_CH4},
- {PA_9, PWM_1_1, SYS_GPA_MFPH_PA9MFP_PWM1_CH1},
- //{PA_9, EPWM_0, SYS_GPA_MFPH_PA9MFP_EPWM0_CH3},
- {PA_10, PWM_1_0, SYS_GPA_MFPH_PA10MFP_PWM1_CH0},
- //{PA_10, EPWM_0, SYS_GPA_MFPH_PA10MFP_EPWM0_CH2},
- {PA_11, PWM_0_5, SYS_GPA_MFPH_PA11MFP_PWM0_CH5},
- //{PA_11, EPWM_0, SYS_GPA_MFPH_PA11MFP_EPWM0_CH1},
- {PA_12, PWM_0_4, SYS_GPA_MFPH_PA12MFP_PWM0_CH4},
- //{PA_12, EPWM_0, SYS_GPA_MFPH_PA12MFP_EPWM0_CH0},
- {PA_13, PWM_1_4, SYS_GPA_MFPH_PA13MFP_PWM1_CH4},
- {PA_14, PWM_1_5, SYS_GPA_MFPH_PA14MFP_PWM1_CH5},
- {PB_6, PWM_1_4, SYS_GPB_MFPL_PB6MFP_PWM1_CH4},
- //{PB_6, EPWM_1, SYS_GPB_MFPL_PB6MFP_EPWM1_CH0},
- {PB_7, PWM_1_5, SYS_GPB_MFPL_PB7MFP_PWM1_CH5},
- //{PB_7, EPWM_1, SYS_GPB_MFPL_PB7MFP_EPWM1_CH1},
- //{PB_8, EPWM_1, SYS_GPB_MFPH_PB8MFP_EPWM1_CH2},
- //{PB_9, EPWM_1, SYS_GPB_MFPH_PB9MFP_EPWM1_CH3},
- //{PB_10, EPWM_1, SYS_GPB_MFPH_PB10MFP_EPWM1_CH4},
- //{PB_11, EPWM_1, SYS_GPB_MFPH_PB11MFP_EPWM1_CH5},
- {PC_10, PWM_0_2, SYS_GPC_MFPH_PC10MFP_PWM0_CH2},
- {PC_11, PWM_0_3, SYS_GPC_MFPH_PC11MFP_PWM0_CH3},
- {PF_9, PWM_0_0, SYS_GPF_MFPH_PF9MFP_PWM0_CH0},
- {PF_10, PWM_0_1, SYS_GPF_MFPH_PF10MFP_PWM0_CH1},
-
- {NC, NC, 0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
- {PA_14, UART_0, SYS_GPA_MFPH_PA14MFP_UART0_TXD},
- {PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD},
- {PB_5, UART_4, SYS_GPB_MFPL_PB5MFP_UART4_TXD},
- {PB_10, UART_5, SYS_GPB_MFPH_PB10MFP_UART5_TXD},
- {PC_1, UART_4, SYS_GPC_MFPL_PC1MFP_UART4_TXD},
- {PC_11, UART_2, SYS_GPC_MFPH_PC11MFP_UART2_TXD},
- {PD_5, UART_3, SYS_GPD_MFPL_PD5MFP_UART3_TXD},
- {PD_15, UART_5, SYS_GPD_MFPH_PD15MFP_UART5_TXD},
- {PF_7, UART_2, SYS_GPF_MFPL_PF7MFP_UART2_TXD},
- {PF_13, UART_1, SYS_GPF_MFPH_PF13MFP_UART1_TXD},
- {PG_2, UART_0, SYS_GPG_MFPL_PG2MFP_UART0_TXD},
- {PH_1, UART_4, SYS_GPH_MFPL_PH1MFP_UART4_TXD},
- {PH_12, UART_3, SYS_GPH_MFPH_PH12MFP_UART3_TXD},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_UART_RX[] = {
- {PA_13, UART_0, SYS_GPA_MFPH_PA13MFP_UART0_RXD},
- {PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD},
- {PB_4, UART_4, SYS_GPB_MFPL_PB4MFP_UART4_RXD},
- {PB_11, UART_5, SYS_GPB_MFPH_PB11MFP_UART5_RXD},
- {PC_0, UART_4, SYS_GPC_MFPL_PC0MFP_UART4_RXD},
- {PC_10, UART_2, SYS_GPC_MFPH_PC10MFP_UART2_RXD},
- {PD_4, UART_3, SYS_GPD_MFPL_PD4MFP_UART3_RXD},
- {PF_0, UART_5, SYS_GPF_MFPL_PF0MFP_UART5_RXD},
- {PF_6, UART_2, SYS_GPF_MFPL_PF6MFP_UART2_RXD},
- {PF_14, UART_1, SYS_GPF_MFPH_PF14MFP_UART1_RXD},
- {PG_1, UART_0, SYS_GPG_MFPL_PG1MFP_UART0_RXD},
- {PH_0, UART_4, SYS_GPH_MFPL_PH0MFP_UART4_RXD},
- {PH_11, UART_3, SYS_GPH_MFPH_PH11MFP_UART3_RXD},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_UART_RTS[] = {
- {PA_11, UART_0, SYS_GPA_MFPH_PA11MFP_UART0_RTS},
- {PA_15, UART_2, SYS_GPA_MFPH_PA15MFP_UART2_RTS},
- {PB_4, UART_1, SYS_GPB_MFPL_PB4MFP_UART1_RTS},
- {PB_6, UART_4, SYS_GPB_MFPL_PB6MFP_UART4_RTS},
- {PB_9, UART_5, SYS_GPB_MFPH_PB9MFP_UART5_RTS},
- {PB_12, UART_4, SYS_GPB_MFPH_PB12MFP_UART4_RTS},
- {PC_2, UART_4, SYS_GPC_MFPL_PC2MFP_UART4_RTS},
- {PD_6, UART_3, SYS_GPD_MFPL_PD6MFP_UART3_RTS},
- {PD_14, UART_5, SYS_GPD_MFPH_PD14MFP_UART5_RTS},
- {PF_8, UART_2, SYS_GPF_MFPH_PF8MFP_UART2_RTS},
- {PF_11, UART_1, SYS_GPF_MFPH_PF11MFP_UART1_RTS},
- {PF_15, UART_0, SYS_GPF_MFPH_PF15MFP_UART0_RTS},
- {PG_8, UART_4, SYS_GPG_MFPH_PG8MFP_UART4_RTS},
- {PH_13, UART_3, SYS_GPH_MFPH_PH13MFP_UART3_RTS},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_UART_CTS[] = {
- {PA_12, UART_0, SYS_GPA_MFPH_PA12MFP_UART0_CTS},
- {PB_5, UART_1, SYS_GPB_MFPL_PB5MFP_UART1_CTS},
- {PB_7, UART_4, SYS_GPB_MFPL_PB7MFP_UART4_CTS},
- {PB_8, UART_5, SYS_GPB_MFPH_PB8MFP_UART5_CTS},
- {PB_13, UART_4, SYS_GPB_MFPH_PB13MFP_UART4_CTS},
- {PC_3, UART_4, SYS_GPC_MFPL_PC3MFP_UART4_CTS},
- {PC_9, UART_2, SYS_GPC_MFPH_PC9MFP_UART2_CTS},
- {PD_7, UART_3, SYS_GPD_MFPL_PD7MFP_UART3_CTS},
- {PD_13, UART_5, SYS_GPD_MFPH_PD13MFP_UART5_CTS},
- {PF_12, UART_1, SYS_GPF_MFPH_PF12MFP_UART1_CTS},
- {PG_0, UART_0, SYS_GPG_MFPL_PG0MFP_UART0_CTS},
- {PG_9, UART_4, SYS_GPG_MFPH_PG9MFP_UART4_CTS},
- {PH_2, UART_2, SYS_GPH_MFPL_PH2MFP_UART2_CTS},
- {PH_14, UART_3, SYS_GPH_MFPH_PH14MFP_UART3_CTS},
-
- {NC, NC, 0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
- {PA_10, SPI_3, SYS_GPA_MFPH_PA10MFP_SPI3_MOSI0},
- {PA_12, SPI_3, SYS_GPA_MFPH_PA12MFP_SPI3_MOSI1},
- {PB_5, SPI_2, SYS_GPB_MFPL_PB5MFP_SPI2_MOSI0},
- {PB_13, SPI_2, SYS_GPB_MFPH_PB13MFP_SPI2_MOSI1},
- {PC_4, SPI_0, SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1},
- {PC_7, SPI_0, SYS_GPC_MFPL_PC7MFP_SPI0_MOSI0},
- {PC_13, SPI_1, SYS_GPC_MFPH_PC13MFP_SPI1_MOSI1},
- {PC_15, SPI_1, SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0},
- {PD_9, SPI_3, SYS_GPD_MFPH_PD9MFP_SPI3_MOSI1},
- {PE_3, SPI_0, SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0},
- {PE_7, SPI_0, SYS_GPE_MFPL_PE7MFP_SPI0_MOSI0},
- {PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI1},
- {PF_0, SPI_1, SYS_GPF_MFPL_PF0MFP_SPI1_MOSI0},
- {PF_1, SPI_2, SYS_GPF_MFPL_PF1MFP_SPI2_MOSI1},
- {PF_5, SPI_3, SYS_GPF_MFPL_PF5MFP_SPI3_MOSI0},
- {PG_8, SPI_2, SYS_GPG_MFPH_PG8MFP_SPI2_MOSI0},
- {PH_8, SPI_2, SYS_GPH_MFPH_PH8MFP_SPI2_MOSI0},
- {PH_10, SPI_2, SYS_GPH_MFPH_PH10MFP_SPI2_MOSI1},
- {PI_6, SPI_3, SYS_GPI_MFPL_PI6MFP_SPI3_MOSI0},
- {PI_8, SPI_3, SYS_GPI_MFPH_PI8MFP_SPI3_MOSI1},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
- {PA_2, SPI_3, SYS_GPA_MFPL_PA2MFP_SPI3_MISO0},
- {PA_9, SPI_3, SYS_GPA_MFPH_PA9MFP_SPI3_MISO0},
- {PA_11, SPI_3, SYS_GPA_MFPH_PA11MFP_SPI3_MISO1},
- {PB_4, SPI_2, SYS_GPB_MFPL_PB4MFP_SPI2_MISO0},
- {PB_12, SPI_2, SYS_GPB_MFPH_PB12MFP_SPI2_MISO1},
- {PC_3, SPI_0, SYS_GPC_MFPL_PC3MFP_SPI0_MISO1},
- {PC_6, SPI_0, SYS_GPC_MFPL_PC6MFP_SPI0_MISO0},
- {PC_14, SPI_1, SYS_GPC_MFPH_PC14MFP_SPI1_MISO1},
- {PD_0, SPI_1, SYS_GPD_MFPL_PD0MFP_SPI1_MISO0},
- {PD_8, SPI_3, SYS_GPD_MFPH_PD8MFP_SPI3_MISO1},
- {PD_15, SPI_1, SYS_GPD_MFPH_PD15MFP_SPI1_MISO0},
- {PE_2, SPI_0, SYS_GPE_MFPL_PE2MFP_SPI0_MISO0},
- {PE_6, SPI_0, SYS_GPE_MFPL_PE6MFP_SPI0_MISO0},
- {PE_10, SPI_0, SYS_GPE_MFPH_PE10MFP_SPI0_MISO1},
- {PF_4, SPI_3, SYS_GPF_MFPL_PF4MFP_SPI3_MISO0},
- {PG_7, SPI_2, SYS_GPG_MFPL_PG7MFP_SPI2_MISO0},
- {PH_7, SPI_2, SYS_GPH_MFPL_PH7MFP_SPI2_MISO0},
- {PH_9, SPI_2, SYS_GPH_MFPH_PH9MFP_SPI2_MISO1},
- {PI_5, SPI_3, SYS_GPI_MFPL_PI5MFP_SPI3_MISO0},
- {PI_7, SPI_3, SYS_GPI_MFPL_PI7MFP_SPI3_MISO1},
- {PI_12, SPI_2, SYS_GPI_MFPH_PI12MFP_SPI2_MISO1},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
- {PA_4, SPI_3, SYS_GPA_MFPL_PA4MFP_SPI3_CLK},
- {PA_8, SPI_3, SYS_GPA_MFPH_PA8MFP_SPI3_CLK},
- {PB_3, SPI_2, SYS_GPB_MFPL_PB3MFP_SPI2_CLK},
- {PC_8, SPI_0, SYS_GPC_MFPH_PC8MFP_SPI0_CLK},
- {PD_1, SPI_1, SYS_GPD_MFPL_PD1MFP_SPI1_CLK},
- {PD_14, SPI_1, SYS_GPD_MFPH_PD14MFP_SPI1_CLK},
- {PE_5, SPI_0, SYS_GPE_MFPL_PE5MFP_SPI0_CLK},
- {PF_3, SPI_3, SYS_GPF_MFPL_PF3MFP_SPI3_CLK},
- {PG_9, SPI_2, SYS_GPG_MFPH_PG9MFP_SPI2_CLK},
- {PH_6, SPI_2, SYS_GPH_MFPL_PH6MFP_SPI2_CLK},
- {PI_4, SPI_3, SYS_GPI_MFPL_PI4MFP_SPI3_CLK},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
- {PA_5, SPI_3, SYS_GPA_MFPL_PA5MFP_SPI3_SS0},
- {PA_7, SPI_3, SYS_GPA_MFPL_PA7MFP_SPI3_SS0},
- {PB_2, SPI_2, SYS_GPB_MFPL_PB2MFP_SPI2_SS0},
- {PC_2, SPI_0, SYS_GPC_MFPL_PC2MFP_SPI0_SS0},
- {PC_12, SPI_1, SYS_GPC_MFPH_PC12MFP_SPI1_SS0},
- {PD_13, SPI_1, SYS_GPD_MFPH_PD13MFP_SPI1_SS0},
- {PE_4, SPI_0, SYS_GPE_MFPL_PE4MFP_SPI0_SS0},
- {PF_2, SPI_3, SYS_GPF_MFPL_PF2MFP_SPI3_SS0},
- {PH_5, SPI_2, SYS_GPH_MFPL_PH5MFP_SPI2_SS0},
- {PI_3, SPI_3, SYS_GPI_MFPL_PI3MFP_SPI3_SS0},
- {PI_11, SPI_2, SYS_GPI_MFPH_PI11MFP_SPI2_SS0},
-
- {NC, NC, 0}
-};
-
-//*** SD ***
-
-const PinMap PinMap_SD_CD[] = {
- {PC_12, SD_0_1, SYS_GPC_MFPH_PC12MFP_SD1_CDn},
- {PD_3, SD_0_0, SYS_GPD_MFPL_PD3MFP_SD0_CDn},
- {PE_5, SD_0_0, SYS_GPE_MFPL_PE5MFP_SD0_CDn},
- {PF_6, SD_0_0, SYS_GPF_MFPL_PF6MFP_SD0_CDn},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SD_CMD[] = {
- {PC_13, SD_0_1, SYS_GPC_MFPH_PC13MFP_SD1_CMD},
- {PD_6, SD_0_0, SYS_GPD_MFPL_PD6MFP_SD0_CMD},
- {PE_6, SD_0_0, SYS_GPE_MFPL_PE6MFP_SD0_CMD},
- {PF_7, SD_0_0, SYS_GPF_MFPL_PF7MFP_SD0_CMD},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SD_CLK[] = {
- {PC_14, SD_0_1, SYS_GPC_MFPH_PC14MFP_SD1_CLK},
- {PD_7, SD_0_0, SYS_GPD_MFPL_PD7MFP_SD0_CLK},
- {PE_7, SD_0_0, SYS_GPE_MFPL_PE7MFP_SD0_CLK},
- {PF_8, SD_0_0, SYS_GPF_MFPH_PF8MFP_SD0_CLK},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SD_DAT0[] = {
- {PC_9, SD_0_1, SYS_GPC_MFPH_PC9MFP_SD1_DAT0},
- {PD_2, SD_0_1, SYS_GPD_MFPL_PD2MFP_SD1_DAT0},
- {PE_11, SD_0_0, SYS_GPE_MFPH_PE11MFP_SD0_DAT0},
- {PF_5, SD_0_0, SYS_GPF_MFPL_PF5MFP_SD0_DAT0},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SD_DAT1[] = {
- {PD_1, SD_0_1, SYS_GPD_MFPL_PD1MFP_SD1_DAT1},
- {PE_10, SD_0_0, SYS_GPE_MFPH_PE10MFP_SD0_DAT1},
- {PF_4, SD_0_0, SYS_GPF_MFPL_PF4MFP_SD0_DAT1},
-
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SD_DAT2[] = {
- {PD_0, SD_0_1, SYS_GPD_MFPL_PD0MFP_SD1_DAT2},
- {PE_9, SD_0_0, SYS_GPE_MFPH_PE9MFP_SD0_DAT2},
- {PF_3, SD_0_0, SYS_GPF_MFPL_PF3MFP_SD0_DAT2},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_SD_DAT3[] = {
- {PC_15, SD_0_1, SYS_GPC_MFPH_PC15MFP_SD1_DAT3},
- {PE_8, SD_0_0, SYS_GPE_MFPH_PE8MFP_SD0_DAT3},
- {PF_2, SD_0_0, SYS_GPF_MFPL_PF2MFP_SD0_DAT3},
-
- {NC, NC, 0}
-};
-
-const PinMap PinMap_CAN_TD[] = {
- {PB_13, CAN_0, SYS_GPB_MFPH_PB13MFP_CAN0_TXD},
- {PA_1, CAN_1, SYS_GPA_MFPL_PA1MFP_CAN1_TXD},
- {PA_6, CAN_1, SYS_GPA_MFPL_PA6MFP_CAN1_TXD},
- {PH_1, CAN_1, SYS_GPH_MFPL_PH1MFP_CAN1_TXD},
-
- {NC, NC, 0}
-};
-
-
-const PinMap PinMap_CAN_RD[] = {
- {PB_12, CAN_0, SYS_GPB_MFPH_PB12MFP_CAN0_RXD},
- {PA_0, CAN_1, SYS_GPA_MFPL_PA0MFP_CAN1_RXD},
- {PH_0, CAN_1, SYS_GPH_MFPL_PH0MFP_CAN1_RXD},
-
- {NC, NC, 0}
-};
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PeripheralPins.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PERIPHERALPINS_H
-#define MBED_PERIPHERALPINS_H
-
-#include "pinmap.h"
-#include "PeripheralNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//*** GPIO ***
-
-extern const PinMap PinMap_GPIO[];
-
-//*** ADC ***
-
-extern const PinMap PinMap_ADC[];
-
-//*** I2C ***
-
-extern const PinMap PinMap_I2C_SDA[];
-extern const PinMap PinMap_I2C_SCL[];
-
-//*** PWM ***
-
-extern const PinMap PinMap_PWM[];
-
-//*** SERIAL ***
-
-extern const PinMap PinMap_UART_TX[];
-extern const PinMap PinMap_UART_RX[];
-extern const PinMap PinMap_UART_RTS[];
-extern const PinMap PinMap_UART_CTS[];
-
-//*** SPI ***
-
-extern const PinMap PinMap_SPI_MOSI[];
-extern const PinMap PinMap_SPI_MISO[];
-extern const PinMap PinMap_SPI_SCLK[];
-extern const PinMap PinMap_SPI_SSEL[];
-
-//*** SD ***
-extern const PinMap PinMap_SD_CD[];
-extern const PinMap PinMap_SD_CMD[];
-extern const PinMap PinMap_SD_CLK[];
-extern const PinMap PinMap_SD_DAT0[];
-extern const PinMap PinMap_SD_DAT1[];
-extern const PinMap PinMap_SD_DAT2[];
-extern const PinMap PinMap_SD_DAT3[];
-
-//*** CAN ***
-extern const PinMap PinMap_CAN_TD[];
-extern const PinMap PinMap_CAN_RD[];
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,116 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NU_PORT_SHIFT 12
-#define NU_PINNAME_TO_PORT(name) ((unsigned int)(name) >> NU_PORT_SHIFT)
-#define NU_PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << NU_PORT_SHIFT))
-#define NU_PORT_N_PIN_TO_PINNAME(port, pin) ((((unsigned int) (port)) << (NU_PORT_SHIFT)) | ((unsigned int) (pin)))
-#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
-#define NU_MFP_POS(pin) ((pin % 8) * 4)
-#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
-
-typedef enum {
- PIN_INPUT,
- PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
- PullNone = 0,
- PullDown,
- PullUp,
-
- PushPull,
- OpenDrain,
- Quasi,
-
- PullDefault = PullUp,
-} PinMode;
-
-typedef enum {
- // Not connected
- NC = (int)0xFFFFFFFF,
-
- // Generic naming
- PA_0 = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
- PB_0 = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
- PC_0 = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14, PC_15,
- PD_0 = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14, PD_15,
- PE_0 = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15,
- PF_0 = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11, PF_12, PF_13, PF_14, PF_15,
- PG_0 = NU_PORT_N_PIN_TO_PINNAME(6, 0), PG_1, PG_2, PG_3, PG_4, PG_5, PG_6, PG_7, PG_8, PG_9, PG_10, PG_11, PG_12, PG_13, PG_14, PG_15,
- PH_0 = NU_PORT_N_PIN_TO_PINNAME(7, 0), PH_1, PH_2, PH_3, PH_4, PH_5, PH_6, PH_7, PH_8, PH_9, PH_10, PH_11, PH_12, PH_13, PH_14, PH_15,
- PI_0 = NU_PORT_N_PIN_TO_PINNAME(8, 0), PI_1, PI_2, PI_3, PI_4, PI_5, PI_6, PI_7, PI_8, PI_9, PI_10, PI_11, PI_12, PI_13, PI_14, PI_15,
-
- // Arduino UNO naming
- A0 = PE_1,
- A1 = PE_2,
- A2 = PE_3,
- A3 = PE_4,
- A4 = PE_5,
- A5 = PE_12,
- A6 = PE_13,
- A7 = PE_14,
-
- D0 = PG_1,
- D1 = PG_2,
- D2 = PF_9,
- D3 = PF_10,
- D4 = PC_10,
- D5 = PC_11,
- D6 = PA_10,
- D7 = PA_9,
- D8 = PD_7,
- D9 = PD_6,
- D10 = PD_3,
- D11 = PD_2,
- D12 = PD_1,
- D13 = PD_0,
- D14 = PD_12,
- D15 = PD_10,
-
- // FIXME: other board-specific naming
- // UART naming
- USBTX = PD_5,
- USBRX = PD_4,
- STDIO_UART_TX = USBTX,
- STDIO_UART_RX = USBRX,
- // LED naming
- LED1 = PD_9,
- LED2 = PA_4,
- LED3 = PD_8,
- LED4 = D0, // No real LED. Just for passing ATS.
- LED_RED = LED1,
- LED_GREEN = LED2,
- LED_BLUE = LED3,
- // Button naming
- SW1 = PC_12,
- SW2 = PC_13,
-
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // MBED_PINNAMES_H
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PortNames.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,39 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/device.h Thu Dec 15 11:48:27 2016 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,24 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_ID_LENGTH 24 - -#include "objects.h" - -#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/mbed_overrides.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "cmsis.h"
-#include "analogin_api.h"
-
-// NOTE: Ensurce mbed_sdk_init() will get called before C++ global object constructor.
-#if defined(__CC_ARM) || defined(__GNUC__)
-void mbed_sdk_init_forced(void) __attribute__((constructor(101)));
-#elif defined(__ICCARM__)
- // FIXME: How to achieve it in IAR?
-#endif
-
-void mbed_sdk_init(void)
-{
- // NOTE: Support singleton semantics to be called from other init functions
- static int inited = 0;
- if (inited) {
- return;
- }
- inited = 1;
-
- /*---------------------------------------------------------------------------------------------------------*/
- /* Init System Clock */
- /*---------------------------------------------------------------------------------------------------------*/
- /* Unlock protected registers */
- SYS_UnlockReg();
-
- /* Enable External XTAL (4~24 MHz) */
- CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
- /* Enable LIRC for lp_ticker */
- CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
- /* Enable LXT for RTC */
- CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
-
- /* Waiting for External XTAL (4~24 MHz) ready */
- CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
- /* Waiting for LIRC ready */
- CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
- /* Waiting for LXT ready */
- CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
-
- /* Switch HCLK clock source to HXT */
- CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
-
- /* Set PLL to power down mode and PLLSTB bit in CLKSTATUS register will be cleared by hardware.*/
- CLK->PLLCTL|= CLK_PLLCTL_PD_Msk;
-
- /* Set PLL frequency */
- CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
-
- /* Waiting for clock ready */
- CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
-
- /* Switch HCLK clock source to PLL */
- CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
-
- /* Enable IP clock */
- //CLK_EnableModuleClock(UART0_MODULE);
-
- /* Select IP clock source */
- //CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_HXT,CLK_CLKDIV0_UART(1));
-
-#if DEVICE_ANALOGIN
- /* Vref connect to AVDD */
- SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD;
-#endif
-
- /* Update System Core Clock */
- /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
- SystemCoreClockUpdate();
-
- /* Lock protected registers */
- SYS_LockReg();
-}
-
-void mbed_sdk_init_forced(void)
-{
- mbed_sdk_init();
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,141 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-#include "dma_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- //IRQn_Type irq_n;
- //uint32_t irq_index;
- //uint32_t event;
-
- PinName pin;
- uint32_t irq_handler;
- uint32_t irq_id;
-};
-
-struct port_s {
- PortName port;
- uint32_t mask;
- PinDirection direction;
-};
-
-struct analogin_s {
- ADCName adc;
- //PinName pin;
-};
-
-struct serial_s {
- UARTName uart;
- PinName pin_tx;
- PinName pin_rx;
-
- uint32_t baudrate;
- uint32_t databits;
- uint32_t parity;
- uint32_t stopbits;
-
- void (*vec)(void);
- uint32_t irq_handler;
- uint32_t irq_id;
- uint32_t inten_msk;
-
- // Async transfer related fields
- DMAUsage dma_usage_tx;
- DMAUsage dma_usage_rx;
- int dma_chn_id_tx;
- int dma_chn_id_rx;
- uint32_t event;
- void (*irq_handler_tx_async)(void);
- void (*irq_handler_rx_async)(void);
-};
-
-struct spi_s {
- SPIName spi;
- PinName pin_miso;
- PinName pin_mosi;
- PinName pin_sclk;
- PinName pin_ssel;
-
- //void (*vec)(void);
-
- // Async transfer related fields
- DMAUsage dma_usage;
- int dma_chn_id_tx;
- int dma_chn_id_rx;
- uint32_t event;
- //void (*irq_handler_tx_async)(void);
- //void (*irq_handler_rx_async)(void);
-};
-
-struct i2c_s {
- I2CName i2c;
- //void (*vec)(void);
- int slaveaddr_state;
-
- uint32_t tran_ctrl;
- char * tran_beg;
- char * tran_pos;
- char * tran_end;
- int inten;
-
-
- // Async transfer related fields
- DMAUsage dma_usage;
- uint32_t event;
- int stop;
- uint32_t address;
-};
-
-struct pwmout_s {
- PWMName pwm;
- //PinName pin;
- uint32_t period_us;
- uint32_t pulsewidth_us;
-};
-
-struct sleep_s {
- uint32_t start_us;
- uint32_t end_us;
- uint32_t period_us;
- int powerdown;
-};
-
-struct trng_s {
- uint8_t dummy;
-};
-
-struct can_s {
- CANName can;
- char index;
-};
-#ifdef __cplusplus
-}
-#endif
-
-#include "gpio_object.h"
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/analogin_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,142 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-
-struct nu_adc_var {
- uint32_t en_msk;
-};
-
-static struct nu_adc_var adc0_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc1_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc2_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc3_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc4_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc5_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc6_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc7_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc8_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc9_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc10_var = {
- .en_msk = 0
-};
-static struct nu_adc_var adc11_var = {
- .en_msk = 0
-};
-
-static const struct nu_modinit_s adc_modinit_tab[] = {
- {ADC_0_0, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc0_var},
- {ADC_0_1, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc1_var},
- {ADC_0_2, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc2_var},
- {ADC_0_3, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc3_var},
- {ADC_0_4, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc4_var},
- {ADC_0_5, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc5_var},
- {ADC_0_6, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc6_var},
- {ADC_0_7, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc7_var},
- {ADC_0_8, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc8_var},
- {ADC_0_9, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc9_var},
- {ADC_0_10, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc10_var},
- {ADC_0_11, ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(1), ADC_RST, ADC_IRQn, &adc11_var}
-};
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
- obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC);
- MBED_ASSERT(obj->adc != (ADCName) NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->adc);
-
- // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
- if (! ((struct nu_adc_var *) modinit->var)->en_msk) {
- // Reset this module if no channel enabled
- SYS_ResetModule(modinit->rsetidx);
-
- // Select clock source of paired channels
- CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
- // Enable clock of paired channels
- CLK_EnableModuleClock(modinit->clkidx);
-
- // Power on ADC
- ADC_POWER_ON(ADC);
- }
-
- ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
- uint32_t chn = NU_MODSUBINDEX(obj->adc);
-
- // Wire pinout
- pinmap_pinout(pin, PinMap_ADC);
-
- // Enable channel 0
- ADC_Open(adc_base,
- ADC_INPUT_MODE_SINGLE_END,
- ADC_OPERATION_MODE_SINGLE,
- 1 << chn); // ADC_CH_0_MASK~ADC_CH_11_MASK
-
- ((struct nu_adc_var *) modinit->var)->en_msk |= 1 << chn;
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
- ADC_T *adc_base = (ADC_T *) NU_MODBASE(obj->adc);
- uint32_t chn = NU_MODSUBINDEX(obj->adc);
-
- ADC_START_CONV(adc_base);
- while (adc_base->CTL & ADC_CTL_SWTRG_Msk);
- uint16_t conv_res_12 = ADC_GET_CONVERSION_DATA(adc_base, chn);
- // Just 12 bits are effective. Convert to 16 bits.
- // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0
- // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8
- uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8);
-
- return conv_res_16;
-}
-
-float analogin_read(analogin_t *obj)
-{
- uint16_t value = analogin_read_u16(obj);
- return (float) value * (1.0f / (float) 0xFFFF);
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,351 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
- #include "can_api.h"
- #include "nuc472_gpio.h"
- #include "nuc472_can.h"
-
- #if DEVICE_CAN
- #include <string.h>
- #include "cmsis.h"
- #include "pinmap.h"
- #include "PeripheralPins.h"
- #include "nu_modutil.h"
- #include "nu_miscutil.h"
- #include "nu_bitutil.h"
- #include "critical.h"
-
- #define NU_CAN_DEBUG 0
- #define CAN_NUM 2
-
- static uint32_t can_irq_ids[CAN_NUM] = {0};
- static can_irq_handler can0_irq_handler;
- static can_irq_handler can1_irq_handler;
-
-
- static const struct nu_modinit_s can_modinit_tab[] = {
- {CAN_0, CAN0_MODULE, 0, 0, CAN0_RST, CAN0_IRQn, NULL},
- {CAN_1, CAN1_MODULE, 0, 0, CAN1_RST, CAN1_IRQn, NULL},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-
- void can_init(can_t *obj, PinName rd, PinName td)
- {
- uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
- uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
- obj->can = (CANName)pinmap_merge(can_td, can_rd);
- MBED_ASSERT((int)obj->can != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->can);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- if(obj->can == CAN_1) {
- obj->index = 1;
- }
- else
- obj->index = 0;
-
- pinmap_pinout(td, PinMap_CAN_TD);
- pinmap_pinout(rd, PinMap_CAN_RD);
-
- /* For NCU 472 mbed Board Transmitter Setting (RS Pin) */
- GPIO_SetMode(PA, BIT2| BIT3, GPIO_MODE_OUTPUT);
- PA2 = 0x00;
- PA3 = 0x00;
-
- CAN_Open((CAN_T *)obj->can, 500000, CAN_NORMAL_MODE);
-
- can_filter(obj, 0, 0, CANStandard, 0);
- }
-
-
-void can_free(can_t *obj)
-{
-
- const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
-
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->can);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- CLK_DisableModuleClock(modinit->clkidx);
-}
-
-int can_frequency(can_t *obj, int hz)
-{
- CAN_SetBaudRate((CAN_T *)obj->can, hz);
-
- return CAN_GetCANBitRate((CAN_T *)obj->can);
-}
-
-static void can_irq(CANName name, int id)
-{
-
- CAN_T *can = (CAN_T *)NU_MODBASE(name);
- uint32_t u8IIDRstatus;
-
- u8IIDRstatus = can->IIDR;
-
- if(u8IIDRstatus == 0x00008000) { /* Check Status Interrupt Flag (Error status Int and Status change Int) */
- /**************************/
- /* Status Change interrupt*/
- /**************************/
- if(can->STATUS & CAN_STATUS_RXOK_Msk) {
- can->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/
- if(id)
- can1_irq_handler(can_irq_ids[id] , IRQ_RX);
- else
- can0_irq_handler(can_irq_ids[id], IRQ_RX);
- }
-
- if(can->STATUS & CAN_STATUS_TXOK_Msk) {
- can->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/
- if(id)
- can1_irq_handler(can_irq_ids[id] , IRQ_TX);
- else
- can0_irq_handler(can_irq_ids[id], IRQ_TX);
-
- }
-
- /**************************/
- /* Error Status interrupt */
- /**************************/
- if(can->STATUS & CAN_STATUS_EWARN_Msk) {
- if(id)
- can1_irq_handler(can_irq_ids[id] , IRQ_ERROR);
- else
- can0_irq_handler(can_irq_ids[id], IRQ_ERROR);
- }
-
- if(can->STATUS & CAN_STATUS_BOFF_Msk) {
- if(id)
- can1_irq_handler(can_irq_ids[id] , IRQ_BUS);
- else
- can0_irq_handler(can_irq_ids[id], IRQ_BUS);
- }
- } else if (u8IIDRstatus!=0) {
-
- if(id)
- can1_irq_handler(can_irq_ids[id] , IRQ_OVERRUN);
- else
- can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN);
-
- CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1)); /* Clear Interrupt Pending */
-
- } else if(can->WU_STATUS == 1) {
-
- can->WU_STATUS = 0; /* Write '0' to clear */
- if(id)
- can1_irq_handler(can_irq_ids[id] , IRQ_WAKEUP);
- else
- can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP);
- }
-}
-
-void CAN0_IRQHandler(void)
-{
- can_irq(CAN_0, 0);
-}
-
-void CAN1_IRQHandler(void)
-{
- can_irq(CAN_1, 1);
-}
-
-void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
-{
- if(obj->index)
- can1_irq_handler = handler;
- else
- can0_irq_handler = handler;
- can_irq_ids[obj->index] = id;
-
-}
-
-void can_irq_free(can_t *obj)
-{
- CAN_DisableInt((CAN_T *)obj->can, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
-
- can_irq_ids[obj->index] = 0;
-
- if(!obj->index)
- NVIC_DisableIRQ(CAN0_IRQn);
- else
- NVIC_DisableIRQ(CAN1_IRQn);
-
-
-}
-
-void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable)
-{
-
- CAN_EnterInitMode((CAN_T*)obj->can);
-
- ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON ) | ((enable != 0 )? CAN_CON_IE_Msk :0);
-
- switch (irq)
- {
- case IRQ_ERROR:
- case IRQ_BUS:
- case IRQ_PASSIVE:
- ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_EIE_Msk;
- ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
- break;
-
- case IRQ_RX:
- case IRQ_TX:
- case IRQ_OVERRUN:
- case IRQ_WAKEUP:
- ((CAN_T *)(obj->can))->CON = (((CAN_T *)(obj->can))->CON) |CAN_CON_SIE_Msk;
- break;
-
- default:
- break;
-
- }
-
- CAN_LeaveInitMode((CAN_T*)obj->can);
-
- if(!obj->index)
- {
- NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler);
- NVIC_EnableIRQ(CAN0_IRQn);
- }
- else
- {
- NVIC_SetVector(CAN1_IRQn, (uint32_t)&CAN1_IRQHandler);
- NVIC_EnableIRQ(CAN1_IRQn);
- }
-
-}
-
-int can_write(can_t *obj, CAN_Message msg, int cc)
-{
- STR_CANMSG_T CMsg;
-
- CMsg.IdType = (uint32_t)msg.format;
- CMsg.FrameType = (uint32_t)!msg.type;
- CMsg.Id = msg.id;
- CMsg.DLC = msg.len;
- memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8);
-
- return CAN_Transmit((CAN_T *)(obj->can), cc, &CMsg);
-}
-
-int can_read(can_t *obj, CAN_Message *msg, int handle)
-{
- STR_CANMSG_T CMsg;
-
- if(!CAN_Receive((CAN_T *)(obj->can), handle, &CMsg))
- return 0;
-
- msg->format = (CANFormat)CMsg.IdType;
- msg->type = (CANType)!CMsg.FrameType;
- msg->id = CMsg.Id;
- msg->len = CMsg.DLC;
- memcpy(&msg->data[0], &CMsg.Data[0], 8);
-
- return 1;
-}
-
-int can_mode(can_t *obj, CanMode mode)
-{
- int success = 0;
- switch (mode)
- {
- case MODE_RESET:
- CAN_LeaveTestMode((CAN_T*)obj->can);
- success = 1;
- break;
-
- case MODE_NORMAL:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_BASIC_Msk);
- success = 1;
- break;
-
- case MODE_SILENT:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk);
- success = 1;
- break;
-
- case MODE_TEST_LOCAL:
- case MODE_TEST_GLOBAL:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_LBACK_Msk);
- success = 1;
- break;
-
- case MODE_TEST_SILENT:
- CAN_EnterTestMode((CAN_T*)(obj->can), CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
- success = 1;
- break;
-
- default:
- success = 0;
- break;
-
- }
-
-
- return success;
-}
-
-int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle)
-{
- return CAN_SetRxMsg((CAN_T *)(obj->can), handle , (uint32_t)format, id);
-}
-
-
-void can_reset(can_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
-
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->can);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
-}
-
-unsigned char can_rderror(can_t *obj)
-{
- CAN_T *can = (CAN_T *)(obj->can);
- return ((can->ERR>>8)&0xFF);
-}
-
-unsigned char can_tderror(can_t *obj)
-{
- CAN_T *can = (CAN_T *)(obj->can);
- return ((can->ERR)&0xFF);
-}
-
-void can_monitor(can_t *obj, int silent)
-{
- CAN_EnterTestMode((CAN_T *)(obj->can), CAN_TEST_SILENT_Msk);
-}
-
-#endif // DEVICE_CAN
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,590 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- * The AES block cipher was designed by Vincent Rijmen and Joan Daemen.
- *
- * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf
- * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_AES_C)
-#if defined(MBEDTLS_AES_ALT)
-
-#include <string.h>
-
-#include "mbedtls/aes.h"
-
-#include "NUC472_442.h"
-#include "toolchain.h"
-#include "mbed_assert.h"
-
-//static int aes_init_done = 0;
-
-
-#define mbedtls_trace(...) //printf(__VA_ARGS__)
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
- volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-
-static uint32_t au32MyAESIV[4] = {
- 0x00000000, 0x00000000, 0x00000000, 0x00000000
-};
-
-extern volatile int g_AES_done;
-
-// Must be a multiple of 16 bytes block size
-#define MAX_DMA_CHAIN_SIZE (16*6)
-static uint8_t au8OutputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4);
-static uint8_t au8InputData[MAX_DMA_CHAIN_SIZE] MBED_ALIGN(4);
-
-static void dumpHex(const unsigned char au8Data[], int len)
-{
- int j;
- for (j = 0; j < len; j++) mbedtls_trace("%02x ", au8Data[j]);
- mbedtls_trace("\r\n");
-}
-
-static void swapInitVector(unsigned char iv[16])
-{
- unsigned int* piv;
- int i;
- // iv SWAP
- piv = (unsigned int*)iv;
- for( i=0; i< 4; i++)
- {
- *piv = (((*piv) & 0x000000FF) << 24) |
- (((*piv) & 0x0000FF00) << 8) |
- (((*piv) & 0x00FF0000) >> 8) |
- (((*piv) & 0xFF000000) >> 24);
- piv++;
- }
-}
-
-//volatile void CRYPTO_IRQHandler()
-//{
-// if (AES_GET_INT_FLAG()) {
-// g_AES_done = 1;
-// AES_CLR_INT_FLAG();
-// }
-//}
-
-// AES available channel 0~3
-static unsigned char channel_flag[4]={0x00,0x00,0x00,0x00}; // 0: idle, 1: busy
-static int channel_alloc()
-{
- int i;
- for(i=0; i< (int)sizeof(channel_flag); i++)
- {
- if( channel_flag[i] == 0x00 )
- {
- channel_flag[i] = 0x01;
- return i;
- }
- }
- return(-1);
-}
-
-static void channel_free(int i)
-{
- if( i >=0 && i < (int)sizeof(channel_flag) )
- channel_flag[i] = 0x00;
-}
-
-
-void mbedtls_aes_init( mbedtls_aes_context *ctx )
-{
- int i =-1;
-
-// sw_mbedtls_aes_init(ctx);
-// return;
-
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
- memset( ctx, 0, sizeof( mbedtls_aes_context ) );
-
- ctx->swapType = AES_IN_OUT_SWAP;
- while( (i = channel_alloc()) < 0 )
- {
- mbed_assert_internal("No available AES channel", __FILE__, __LINE__);
- //osDelay(300);
- }
- ctx->channel = i;
- ctx->iv = au32MyAESIV;
-
- /* Unlock protected registers */
- SYS_UnlockReg();
- CLK_EnableModuleClock(CRPT_MODULE);
- /* Lock protected registers */
- SYS_LockReg();
-
- NVIC_EnableIRQ(CRPT_IRQn);
- AES_ENABLE_INT();
- mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__, (int)ctx->channel);
-}
-
-void mbedtls_aes_free( mbedtls_aes_context *ctx )
-{
-
- mbedtls_trace("=== %s channel[%d]\r\n", __FUNCTION__,(int)ctx->channel);
-
- if( ctx == NULL )
- return;
-
- /* Unlock protected registers */
-// SYS_UnlockReg();
-// CLK_DisableModuleClock(CRPT_MODULE);
- /* Lock protected registers */
-// SYS_LockReg();
-
-// NVIC_DisableIRQ(CRPT_IRQn);
-// AES_DISABLE_INT();
- channel_free(ctx->channel);
- mbedtls_zeroize( ctx, sizeof( mbedtls_aes_context ) );
-}
-
-/*
- * AES key schedule (encryption)
- */
-#if defined(MBEDTLS_AES_SETKEY_ENC_ALT)
-int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
- unsigned int keybits )
-{
- unsigned int i;
-
- mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits);
- dumpHex(key,keybits/8);
-
- switch( keybits )
- {
- case 128:
- ctx->keySize = AES_KEY_SIZE_128;
- break;
- case 192:
- ctx->keySize = AES_KEY_SIZE_192;
- break;
- case 256:
- ctx->keySize = AES_KEY_SIZE_256;
- break;
- default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH );
- }
-
-
-
- // key swap
- for( i = 0; i < ( keybits >> 5 ); i++ )
- {
- ctx->buf[i] = (*(key+i*4) << 24) |
- (*(key+1+i*4) << 16) |
- (*(key+2+i*4) << 8) |
- (*(key+3+i*4) );
- }
- AES_SetKey(ctx->channel, ctx->buf, ctx->keySize);
-
-
- return( 0 );
-}
-#endif /* MBEDTLS_AES_SETKEY_ENC_ALT */
-
-/*
- * AES key schedule (decryption)
- */
-#if defined(MBEDTLS_AES_SETKEY_DEC_ALT)
-int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
- unsigned int keybits )
-{
- int ret;
-
- mbedtls_trace("=== %s keybits[%d]\r\n", __FUNCTION__, keybits);
- dumpHex((uint8_t *)key,keybits/8);
-
- /* Also checks keybits */
- if( ( ret = mbedtls_aes_setkey_enc( ctx, key, keybits ) ) != 0 )
- goto exit;
-
-exit:
-
- return( ret );
-}
-#endif /* MBEDTLS_AES_SETKEY_DEC_ALT */
-
-
-static void __nvt_aes_crypt( mbedtls_aes_context *ctx,
- const unsigned char input[16],
- unsigned char output[16], int dataSize)
-{
- unsigned char* pIn;
- unsigned char* pOut;
-
-// mbedtls_trace("=== %s \r\n", __FUNCTION__);
- dumpHex(input,16);
-
- AES_Open(ctx->channel, ctx->encDec, ctx->opMode, ctx->keySize, ctx->swapType);
- AES_SetInitVect(ctx->channel, ctx->iv);
- if( ((uint32_t)input) & 0x03 )
- {
- memcpy(au8InputData, input, dataSize);
- pIn = au8InputData;
- }else{
- pIn = (unsigned char*)input;
- }
- if( (((uint32_t)output) & 0x03) || (dataSize%4)) // HW CFB output byte count must be multiple of word
- {
- pOut = au8OutputData;
- } else {
- pOut = output;
- }
-
- AES_SetDMATransfer(ctx->channel, (uint32_t)pIn, (uint32_t)pOut, dataSize);
-
- g_AES_done = 0;
- AES_Start(ctx->channel, CRYPTO_DMA_ONE_SHOT);
- while (!g_AES_done);
-
- if( pOut != output ) memcpy(output, au8OutputData, dataSize);
- dumpHex(output,16);
-
-}
-
-/*
- * AES-ECB block encryption
- */
-#if defined(MBEDTLS_AES_ENCRYPT_ALT)
-void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
- const unsigned char input[16],
- unsigned char output[16] )
-{
-
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
-
- ctx->encDec = 1;
- __nvt_aes_crypt(ctx, input, output, 16);
-
-}
-#endif /* MBEDTLS_AES_ENCRYPT_ALT */
-
-/*
- * AES-ECB block decryption
- */
-#if defined(MBEDTLS_AES_DECRYPT_ALT)
-void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
- const unsigned char input[16],
- unsigned char output[16] )
-{
-
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
-
- ctx->encDec = 0;
- __nvt_aes_crypt(ctx, input, output, 16);
-
-
-}
-#endif /* MBEDTLS_AES_DECRYPT_ALT */
-
-/*
- * AES-ECB block encryption/decryption
- */
-int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
- int mode,
- const unsigned char input[16],
- unsigned char output[16] )
-{
-
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
-
- ctx->opMode = AES_MODE_ECB;
- if( mode == MBEDTLS_AES_ENCRYPT )
- mbedtls_aes_encrypt( ctx, input, output );
- else
- mbedtls_aes_decrypt( ctx, input, output );
-
-
- return( 0 );
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * AES-CBC buffer encryption/decryption
- */
-int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
- int mode,
- size_t len,
- unsigned char iv[16],
- const unsigned char *input,
- unsigned char *output )
-{
- unsigned char temp[16];
- int length = len;
- int blockChainLen;
- mbedtls_trace("=== %s [0x%x]\r\n", __FUNCTION__,length);
- if( length % 16 )
- return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH );
-
- if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) )
- {
- blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length );
- } else {
- blockChainLen = length;
- }
-
- while( length > 0 )
- {
- ctx->opMode = AES_MODE_CBC;
- swapInitVector(iv); // iv SWAP
- ctx->iv = (uint32_t *)iv;
-
- if( mode == MBEDTLS_AES_ENCRYPT )
- {
- ctx->encDec = 1;
- __nvt_aes_crypt(ctx, input, output, blockChainLen);
-// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test()
- memcpy( iv, output+blockChainLen-16, 16 );
- }else{
- memcpy( temp, input+blockChainLen-16, 16 );
- ctx->encDec = 0;
- __nvt_aes_crypt(ctx, input, output, blockChainLen);
-// if( blockChainLen == length ) break; // finish last block chain but still need to prepare next iv for mbedtls_aes_self_test()
- memcpy( iv, temp, 16 );
- }
- length -= blockChainLen;
- input += blockChainLen;
- output += blockChainLen;
- if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain
-
- }
-
- return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/*
- * AES-CFB128 buffer encryption/decryption
- */
-/* Support partial block encryption/decryption */
-static int __nvt_aes_crypt_partial_block_cfb128( mbedtls_aes_context *ctx,
- int mode,
- size_t length,
- size_t *iv_off,
- unsigned char iv[16],
- const unsigned char *input,
- unsigned char *output )
-{
- int c;
- size_t n = *iv_off;
- unsigned char iv_tmp[16];
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
- if( mode == MBEDTLS_AES_DECRYPT )
- {
- while( length-- )
- {
- if( n == 0)
- mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
- else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode
- {
- memcpy(iv_tmp, iv, n);
- mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
- memcpy(iv, iv_tmp, n);
- }
-
- c = *input++;
- *output++ = (unsigned char)( c ^ iv[n] );
- iv[n] = (unsigned char) c;
-
- n = ( n + 1 ) & 0x0F;
- }
- }
- else
- {
- while( length-- )
- {
- if( n == 0 )
- mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
- else if( ctx->opMode == AES_MODE_CFB) // For previous cryption is CFB mode
- {
- memcpy(iv_tmp, iv, n);
- mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, ctx->prv_iv, iv );
- memcpy(iv, iv_tmp, n);
- }
-
- iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ );
-
- n = ( n + 1 ) & 0x0F;
- }
- }
-
- *iv_off = n;
-
- return( 0 );
-}
-
-int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
- int mode,
- size_t len,
- size_t *iv_off,
- unsigned char iv[16],
- const unsigned char *input,
- unsigned char *output )
-{
- size_t n = *iv_off;
- unsigned char temp[16];
- int length=len;
- int blockChainLen;
- int remLen=0;
- int ivLen;
-
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
-
- // proceed: start with partial block by ECB mode first
- if( n !=0 ) {
- __nvt_aes_crypt_partial_block_cfb128(ctx, mode, 16 - n , iv_off, iv, input, output);
- input += (16 - n);
- output += (16 - n);
- length -= (16 - n);
- }
-
- // For address or byte count non-word alignment, go through reserved DMA buffer.
- if( (((uint32_t)input) & 0x03) || (((uint32_t)output) & 0x03) ) // Must reserved DMA buffer for each block
- {
- blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? MAX_DMA_CHAIN_SIZE : length );
- } else if(length%4) { // Need reserved DMA buffer once for last chain
- blockChainLen = (( length > MAX_DMA_CHAIN_SIZE ) ? (length - length%16) : length );
- } else { // Not need reserved DMA buffer
- blockChainLen = length;
- }
-
- // proceed: start with block alignment
- while( length > 0 )
- {
-
- ctx->opMode = AES_MODE_CFB;
-
- swapInitVector(iv); // iv SWAP
-
- ctx->iv = (uint32_t *)iv;
- remLen = blockChainLen%16;
- ivLen = (( remLen > 0) ? remLen: 16 );
-
- if( mode == MBEDTLS_AES_DECRYPT )
- {
- memcpy(temp, input+blockChainLen - ivLen, ivLen);
- if(blockChainLen >= 16) memcpy(ctx->prv_iv, input+blockChainLen-remLen-16 , 16);
- ctx->encDec = 0;
- __nvt_aes_crypt(ctx, input, output, blockChainLen);
- memcpy(iv,temp, ivLen);
- }
- else
- {
- ctx->encDec = 1;
- __nvt_aes_crypt(ctx, input, output, blockChainLen);
- if(blockChainLen >= 16) memcpy(ctx->prv_iv, output+blockChainLen-remLen-16 , 16);
- memcpy(iv,output+blockChainLen-ivLen,ivLen);
- }
- length -= blockChainLen;
- input += blockChainLen;
- output += blockChainLen;
- if(length < MAX_DMA_CHAIN_SIZE ) blockChainLen = length; // For last remainder block chain
- }
-
- *iv_off = remLen;
-
- return( 0 );
-}
-
-
-/*
- * AES-CFB8 buffer encryption/decryption
- */
-int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[16],
- const unsigned char *input,
- unsigned char *output )
-{
- unsigned char c;
- unsigned char ov[17];
-
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
- while( length-- )
- {
- memcpy( ov, iv, 16 );
- mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv );
-
- if( mode == MBEDTLS_AES_DECRYPT )
- ov[16] = *input;
-
- c = *output++ = (unsigned char)( iv[0] ^ *input++ );
-
- if( mode == MBEDTLS_AES_ENCRYPT )
- ov[16] = c;
-
- memcpy( iv, ov + 1, 16 );
- }
-
- return( 0 );
-}
-#endif /*MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/*
- * AES-CTR buffer encryption/decryption
- */
-int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
- size_t length,
- size_t *nc_off,
- unsigned char nonce_counter[16],
- unsigned char stream_block[16],
- const unsigned char *input,
- unsigned char *output )
-{
- int c, i;
- size_t n = *nc_off;
-
- mbedtls_trace("=== %s \r\n", __FUNCTION__);
- while( length-- )
- {
- if( n == 0 ) {
- mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block );
-
- for( i = 16; i > 0; i-- )
- if( ++nonce_counter[i - 1] != 0 )
- break;
- }
- c = *input++;
- *output++ = (unsigned char)( c ^ stream_block[n] );
-
- n = ( n + 1 ) & 0x0F;
- }
-
- *nc_off = n;
-
- return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-#endif /* MBEDTLS_AES_ALT */
-
-
-#endif /* MBEDTLS_AES_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/aes/aes_alt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,274 +0,0 @@
-/**
- * \file aes_alt.h
- *
- * \brief AES block cipher
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-#if defined(MBEDTLS_AES_ALT)
-// Regular implementation
-//
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief AES context structure
- *
- * \note buf is able to hold 32 extra bytes, which can be used:
- * - for alignment purposes if VIA padlock is used, and/or
- * - to simplify key expansion in the 256-bit case by
- * generating an extra round key
- */
-typedef struct
-{
- uint32_t keySize;
- uint32_t encDec;
- uint32_t opMode;
- uint32_t channel;
- uint32_t swapType;
- uint32_t *iv;
- unsigned char prv_iv[16];
-#if 1
- uint32_t buf[8];
-/* For comparsion with software AES for correctness */
-#else
- uint32_t buf[68]; /*!< unaligned data */
- int nr; /*!< number of rounds */
- uint32_t *rk; /*!< AES round keys */
-#endif
-}
-mbedtls_aes_context;
-
-/**
- * \brief Initialize AES context
- *
- * \param ctx AES context to be initialized
- */
-void mbedtls_aes_init( mbedtls_aes_context *ctx );
-
-/**
- * \brief Clear AES context
- *
- * \param ctx AES context to be cleared
- */
-void mbedtls_aes_free( mbedtls_aes_context *ctx );
-
-/**
- * \brief AES key schedule (encryption)
- *
- * \param ctx AES context to be initialized
- * \param key encryption key
- * \param keybits must be 128, 192 or 256
- *
- * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
- */
-int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key,
- unsigned int keybits );
-
-/**
- * \brief AES key schedule (decryption)
- *
- * \param ctx AES context to be initialized
- * \param key decryption key
- * \param keybits must be 128, 192 or 256
- *
- * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH
- */
-int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key,
- unsigned int keybits );
-
-/**
- * \brief AES-ECB block encryption/decryption
- *
- * \param ctx AES context
- * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param input 16-byte input block
- * \param output 16-byte output block
- *
- * \return 0 if successful
- */
-int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx,
- int mode,
- const unsigned char input[16],
- unsigned char output[16] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief AES-CBC buffer encryption/decryption
- * Length should be a multiple of the block
- * size (16 bytes)
- *
- * \note Upon exit, the content of the IV is updated so that you can
- * call the function same function again on the following
- * block(s) of data and get the same result as if it was
- * encrypted in one call. This allows a "streaming" usage.
- * If on the other hand you need to retain the contents of the
- * IV, you should either save it manually or use the cipher
- * module instead.
- *
- * \param ctx AES context
- * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param length length of the input data
- * \param iv initialization vector (updated after use)
- * \param input buffer holding the input data
- * \param output buffer holding the output data
- *
- * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH
- */
-int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[16],
- const unsigned char *input,
- unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#if defined(MBEDTLS_CIPHER_MODE_CFB)
-/**
- * \brief AES-CFB128 buffer encryption/decryption.
- *
- * Note: Due to the nature of CFB you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
- *
- * \note Upon exit, the content of the IV is updated so that you can
- * call the function same function again on the following
- * block(s) of data and get the same result as if it was
- * encrypted in one call. This allows a "streaming" usage.
- * If on the other hand you need to retain the contents of the
- * IV, you should either save it manually or use the cipher
- * module instead.
- *
- * \param ctx AES context
- * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param length length of the input data
- * \param iv_off offset in IV (updated after use)
- * \param iv initialization vector (updated after use)
- * \param input buffer holding the input data
- * \param output buffer holding the output data
- *
- * \return 0 if successful
- */
-int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx,
- int mode,
- size_t length,
- size_t *iv_off,
- unsigned char iv[16],
- const unsigned char *input,
- unsigned char *output );
-
-/**
- * \brief AES-CFB8 buffer encryption/decryption.
- *
- * Note: Due to the nature of CFB you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
- *
- * \note Upon exit, the content of the IV is updated so that you can
- * call the function same function again on the following
- * block(s) of data and get the same result as if it was
- * encrypted in one call. This allows a "streaming" usage.
- * If on the other hand you need to retain the contents of the
- * IV, you should either save it manually or use the cipher
- * module instead.
- *
- * \param ctx AES context
- * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT
- * \param length length of the input data
- * \param iv initialization vector (updated after use)
- * \param input buffer holding the input data
- * \param output buffer holding the output data
- *
- * \return 0 if successful
- */
-int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[16],
- const unsigned char *input,
- unsigned char *output );
-#endif /*MBEDTLS_CIPHER_MODE_CFB */
-
-#if defined(MBEDTLS_CIPHER_MODE_CTR)
-/**
- * \brief AES-CTR buffer encryption/decryption
- *
- * Warning: You have to keep the maximum use of your counter in mind!
- *
- * Note: Due to the nature of CTR you should use the same key schedule for
- * both encryption and decryption. So a context initialized with
- * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT.
- *
- * \param ctx AES context
- * \param length The length of the data
- * \param nc_off The offset in the current stream_block (for resuming
- * within current cipher stream). The offset pointer to
- * should be 0 at the start of a stream.
- * \param nonce_counter The 128-bit nonce and counter.
- * \param stream_block The saved stream-block for resuming. Is overwritten
- * by the function.
- * \param input The input data stream
- * \param output The output data stream
- *
- * \return 0 if successful
- */
-int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx,
- size_t length,
- size_t *nc_off,
- unsigned char nonce_counter[16],
- unsigned char stream_block[16],
- const unsigned char *input,
- unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CTR */
-
-/**
- * \brief Internal AES block encryption function
- * (Only exposed to allow overriding it,
- * see MBEDTLS_AES_ENCRYPT_ALT)
- *
- * \param ctx AES context
- * \param input Plaintext block
- * \param output Output (ciphertext) block
- */
-void mbedtls_aes_encrypt( mbedtls_aes_context *ctx,
- const unsigned char input[16],
- unsigned char output[16] );
-
-/**
- * \brief Internal AES block decryption function
- * (Only exposed to allow overriding it,
- * see MBEDTLS_AES_DECRYPT_ALT)
- *
- * \param ctx AES context
- * \param input Ciphertext block
- * \param output Output (plaintext) block
- */
-void mbedtls_aes_decrypt( mbedtls_aes_context *ctx,
- const unsigned char input[16],
- unsigned char output[16] );
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* MBEDTLS_AES_ALT */
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-
-#include "cmsis.h"
-#include "mbed_assert.h"
-#include "nu_modutil.h"
-#include "nu_bitutil.h"
-#include "crypto-misc.h"
-
-static int crypto_inited = 0;
-static int crypto_sha_avail = 1;
-
-void crypto_init(void)
-{
- if (crypto_inited) {
- return;
- }
- crypto_inited = 1;
-
- CLK_EnableModuleClock(CRPT_MODULE);
-}
-
-/* Implementation that should never be optimized out by the compiler */
-void crypto_zeroize(void *v, size_t n)
-{
- volatile unsigned char *p = (unsigned char*) v;
- while (n--) {
- *p++ = 0;
- }
-}
-
-int crypto_sha_acquire(void)
-{
- if (crypto_sha_avail) {
- crypto_sha_avail = 0;
- return 1;
- }
- else {
- return 0;
- }
-
-}
-
-void crypto_sha_release(void)
-{
- if (! crypto_sha_avail) {
- crypto_sha_avail = 1;
- }
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_CRYPTO_MISC_H
-#define MBED_CRYPTO_MISC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void crypto_init(void);
-void crypto_zeroize(void *v, size_t n);
-int crypto_sha_acquire(void);
-void crypto_sha_release(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,410 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_C)
-#if defined(MBEDTLS_DES_ALT)
-
-#include <string.h>
-#include "mbedtls/des.h"
-#include "des_alt.h"
-#include "crypto-misc.h"
-#include "nu_bitutil.h"
-#include "toolchain.h"
-
-// Must be a multiple of 64-bit block size
-#define MAXSIZE_DMABUF (8 * 5)
-static uint8_t dmabuf_in[MAXSIZE_DMABUF] MBED_ALIGN(4);
-static uint8_t dmabuf_out[MAXSIZE_DMABUF] MBED_ALIGN(4);
-
-static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length,
- unsigned char iv[8], const unsigned char *input, unsigned char *output);
-
-void mbedtls_des_init(mbedtls_des_context *ctx)
-{
- crypto_init();
- memset(ctx, 0, sizeof(mbedtls_des_context));
-}
-
-void mbedtls_des_free( mbedtls_des_context *ctx )
-{
- if (ctx == NULL) {
- return;
- }
-
- crypto_zeroize(ctx, sizeof(mbedtls_des_context));
-}
-
-void mbedtls_des3_init( mbedtls_des3_context *ctx )
-{
- crypto_init();
- memset(ctx, 0, sizeof(mbedtls_des3_context));
-}
-
-void mbedtls_des3_free( mbedtls_des3_context *ctx )
-{
- if (ctx == NULL) {
- return;
- }
-
- crypto_zeroize(ctx, sizeof (mbedtls_des3_context));
-}
-
-static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8,
- 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44,
- 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81,
- 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112,
- 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140,
- 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168,
- 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196,
- 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224,
- 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253,
- 254 };
-
-void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE])
-{
- int i;
-
- for (i = 0; i < MBEDTLS_DES_KEY_SIZE; i++) {
- key[i] = odd_parity_table[key[i] / 2];
- }
-}
-
-/*
- * Check the given key's parity, returns 1 on failure, 0 on SUCCESS
- */
-int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- int i;
-
- for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
- if( key[i] != odd_parity_table[key[i] / 2] )
- return( 1 );
-
- return( 0 );
-}
-
-/*
- * Table of weak and semi-weak keys
- *
- * Source: http://en.wikipedia.org/wiki/Weak_key
- *
- * Weak:
- * Alternating ones + zeros (0x0101010101010101)
- * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE)
- * '0xE0E0E0E0F1F1F1F1'
- * '0x1F1F1F1F0E0E0E0E'
- *
- * Semi-weak:
- * 0x011F011F010E010E and 0x1F011F010E010E01
- * 0x01E001E001F101F1 and 0xE001E001F101F101
- * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01
- * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E
- * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E
- * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1
- *
- */
-
-#define WEAK_KEY_COUNT 16
-
-static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] =
-{
- { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 },
- { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
- { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E },
- { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 },
-
- { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E },
- { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 },
- { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 },
- { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 },
- { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE },
- { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 },
- { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 },
- { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E },
- { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE },
- { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E },
- { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE },
- { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 }
-};
-
-int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- int i;
-
- for( i = 0; i < WEAK_KEY_COUNT; i++ )
- if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 )
- return( 1 );
-
- return( 0 );
-}
-
-/*
- * DES key schedule (56-bit, encryption)
- */
-int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- ctx->enc = 1;
- // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3.
- ctx->keyopt = 3;
- memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-
- return 0;
-}
-
-/*
- * DES key schedule (56-bit, decryption)
- */
-int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- ctx->enc = 0;
- // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3.
- ctx->keyopt = 3;
- memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[1], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-
- return 0;
-}
-
-/*
- * Triple-DES key schedule (112-bit, encryption)
- */
-int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
- ctx->enc = 1;
- // Keying option 2: K1 and K2 are independent, and K3 = K1.
- ctx->keyopt = 2;
- memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-
- return 0;
-}
-
-/*
- * Triple-DES key schedule (112-bit, decryption)
- */
-int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
- ctx->enc = 0;
- // Keying option 2: K1 and K2 are independent, and K3 = K1.
- ctx->keyopt = 2;
- memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[2], key, MBEDTLS_DES_KEY_SIZE);
-
- return 0;
-}
-
-/*
- * Triple-DES key schedule (168-bit, encryption)
- */
-int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
- ctx->enc = 1;
- // Keying option 1: All three keys are independent.
- ctx->keyopt = 1;
- memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[2], key + MBEDTLS_DES_KEY_SIZE * 2, MBEDTLS_DES_KEY_SIZE);
-
- return 0;
-}
-
-/*
- * Triple-DES key schedule (168-bit, decryption)
- */
-int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
- ctx->enc = 0;
- // Keying option 1: All three keys are independent.
- ctx->keyopt = 1;
- memcpy(ctx->key[0], key, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[1], key + MBEDTLS_DES_KEY_SIZE, MBEDTLS_DES_KEY_SIZE);
- memcpy(ctx->key[2], key + MBEDTLS_DES_KEY_SIZE * 2, MBEDTLS_DES_KEY_SIZE);
-
- return 0;
-}
-
-/*
- * DES-ECB block encryption/decryption
- */
-int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] )
-{
- unsigned char iv[8] = {0x00};
- return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, DES_MODE_ECB, 8, iv, input, output);
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * DES-CBC buffer encryption/decryption
- */
-int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output )
-{
- return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, DES_MODE_CBC, length, iv, input, output);
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/*
- * 3DES-ECB block encryption/decryption
- */
-int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] )
-{
- unsigned char iv[8] = {0x00};
- return mbedtls_des_docrypt(ctx->keyopt, ctx->key, ctx->enc, TDES_MODE_ECB, 8, iv, input, output);
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * 3DES-CBC buffer encryption/decryption
- */
-int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output )
-{
- return mbedtls_des_docrypt(ctx->keyopt, ctx->key, mode == MBEDTLS_DES_ENCRYPT, TDES_MODE_CBC, length, iv, input, output);
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-
-
-static int mbedtls_des_docrypt(uint16_t keyopt, uint8_t key[3][MBEDTLS_DES_KEY_SIZE], int enc, uint32_t tdes_opmode, size_t length,
- unsigned char iv[8], const unsigned char *input, unsigned char *output)
-{
- if (length % 8) {
- return MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH;
- }
-
- // NOTE: Don't call driver function TDES_Open in BSP because it doesn't support TDES_CTL[3KEYS] setting.
- CRPT->TDES_CTL = (0 << CRPT_TDES_CTL_CHANNEL_Pos) | (enc << CRPT_TDES_CTL_ENCRPT_Pos) |
- tdes_opmode | (TDES_IN_OUT_WHL_SWAP << CRPT_TDES_CTL_BLKSWAP_Pos);
-
- // Keying option 1: All three keys are independent.
- // Keying option 2: K1 and K2 are independent, and K3 = K1.
- // Keying option 3: All three keys are identical, i.e. K1 = K2 = K3.
- if (keyopt == 1) {
- CRPT->TDES_CTL |= CRPT_TDES_CTL_3KEYS_Msk;
- }
- else {
- CRPT->TDES_CTL &= ~CRPT_TDES_CTL_3KEYS_Msk;
- }
-
- // Set DES/TDES keys
- // NOTE: Don't call driver function TDES_SetKey in BSP because it doesn't support endian swap.
- uint32_t val;
- volatile uint32_t *tdes_key = (uint32_t *) ((uint32_t) &CRPT->TDES0_KEY1H + (0x40 * 0));
- val = nu_get32_be(key[0] + 0);
- *tdes_key ++ = val;
- val = nu_get32_be(key[0] + 4);
- *tdes_key ++ = val;
- val = nu_get32_be(key[1] + 0);
- *tdes_key ++ = val;
- val = nu_get32_be(key[1] + 4);
- *tdes_key ++ = val;
- val = nu_get32_be(key[2] + 0);
- *tdes_key ++ = val;
- val = nu_get32_be(key[2] + 4);
- *tdes_key ++ = val;
-
- uint32_t rmn = length;
- const unsigned char *in_pos = input;
- const unsigned char *out_pos = output;
-
- while (rmn) {
- uint32_t data_len = (rmn <= MAXSIZE_DMABUF) ? rmn : MAXSIZE_DMABUF;
-
- uint32_t ivh, ivl;
- ivh = nu_get32_be(iv);
- ivl = nu_get32_be(iv + 4);
- TDES_SetInitVect(0, ivh, ivl);
-
- memcpy(dmabuf_in, in_pos, data_len);
-
- TDES_SetDMATransfer(0, (uint32_t) dmabuf_in, (uint32_t) dmabuf_out, data_len);
-
- // Start enc/dec.
- // NOTE: Don't call driver function TDES_Start in BSP because it will override TDES_CTL[3KEYS] setting.
- CRPT->TDES_CTL |= CRPT_TDES_CTL_START_Msk | (CRYPTO_DMA_ONE_SHOT << CRPT_TDES_CTL_DMALAST_Pos);
- while (CRPT->TDES_STS & CRPT_TDES_STS_BUSY_Msk);
-
- memcpy(out_pos, dmabuf_out, data_len);
- in_pos += data_len;
- out_pos += data_len;
- rmn -= data_len;
-
- // Update IV for next block enc/dec in next function call
- switch (tdes_opmode) {
- case DES_MODE_OFB:
- case TDES_MODE_OFB: {
- // OFB: IV (enc/dec) = output block XOR input block
- uint32_t lbh, lbl;
- // Last block of input data
- lbh = nu_get32_be(dmabuf_in + data_len - 8 + 4);
- lbl = nu_get32_be(dmabuf_in + data_len - 8 + 0);
- // Last block of output data
- ivh = nu_get32_be(dmabuf_out + 4);
- ivl = nu_get32_be(dmabuf_out + 0);
- ivh = ivh ^ lbh;
- ivl = ivl ^ lbl;
- nu_set32_be(iv + 4, ivh);
- nu_set32_be(iv, ivl);
- break;
- }
- case DES_MODE_CBC:
- case DES_MODE_CFB:
- case TDES_MODE_CBC:
- case TDES_MODE_CFB: {
- // CBC/CFB: IV (enc) = output block
- // IV (dec) = input block
- if (enc) {
- memcpy(iv, dmabuf_out + data_len - 8, 8);
- }
- else {
- memcpy(iv, dmabuf_in + data_len - 8, 8);
- }
- }
- }
- }
-
- return 0;
-}
-
-#endif /* MBEDTLS_DES_ALT */
-#endif /* MBEDTLS_DES_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,280 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBEDTLS_DES_ALT_H
-#define MBEDTLS_DES_ALT_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-#include "des.h"
-#include "des_alt_sw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief DES context structure
- */
-typedef struct
-{
- int enc; /*!< 0: dec, 1: enc */
- uint16_t keyopt;
- uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */
-}
-mbedtls_des_context;
-
-/**
- * \brief Triple-DES context structure
- */
-typedef struct
-{
- int enc; /*!< 0: dec, 1: enc */
- uint16_t keyopt;
- uint8_t key[3][MBEDTLS_DES_KEY_SIZE]; /*!< 3DES keys */
-}
-mbedtls_des3_context;
-
-/**
- * \brief Initialize DES context
- *
- * \param ctx DES context to be initialized
- */
-void mbedtls_des_init( mbedtls_des_context *ctx );
-
-/**
- * \brief Clear DES context
- *
- * \param ctx DES context to be cleared
- */
-void mbedtls_des_free( mbedtls_des_context *ctx );
-
-/**
- * \brief Initialize Triple-DES context
- *
- * \param ctx DES3 context to be initialized
- */
-void mbedtls_des3_init( mbedtls_des3_context *ctx );
-
-/**
- * \brief Clear Triple-DES context
- *
- * \param ctx DES3 context to be cleared
- */
-void mbedtls_des3_free( mbedtls_des3_context *ctx );
-
-/**
- * \brief Set key parity on the given key to odd.
- *
- * DES keys are 56 bits long, but each byte is padded with
- * a parity bit to allow verification.
- *
- * \param key 8-byte secret key
- */
-void mbedtls_des_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief Check that key parity on the given key is odd.
- *
- * DES keys are 56 bits long, but each byte is padded with
- * a parity bit to allow verification.
- *
- * \param key 8-byte secret key
- *
- * \return 0 is parity was ok, 1 if parity was not correct.
- */
-int mbedtls_des_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief Check that key is not a weak or semi-weak DES key
- *
- * \param key 8-byte secret key
- *
- * \return 0 if no weak key was found, 1 if a weak key was identified.
- */
-int mbedtls_des_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief DES key schedule (56-bit, encryption)
- *
- * \param ctx DES context to be initialized
- * \param key 8-byte secret key
- *
- * \return 0
- */
-int mbedtls_des_setkey_enc( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief DES key schedule (56-bit, decryption)
- *
- * \param ctx DES context to be initialized
- * \param key 8-byte secret key
- *
- * \return 0
- */
-int mbedtls_des_setkey_dec( mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief Triple-DES key schedule (112-bit, encryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 16-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_set2key_enc( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief Triple-DES key schedule (112-bit, decryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 16-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_set2key_dec( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief Triple-DES key schedule (168-bit, encryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 24-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_set3key_enc( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief Triple-DES key schedule (168-bit, decryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 24-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_set3key_dec( mbedtls_des3_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief DES-ECB block encryption/decryption
- *
- * \param ctx DES context
- * \param input 64-bit input block
- * \param output 64-bit output block
- *
- * \return 0 if successful
- */
-int mbedtls_des_crypt_ecb( mbedtls_des_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief DES-CBC buffer encryption/decryption
- *
- * \note Upon exit, the content of the IV is updated so that you can
- * call the function same function again on the following
- * block(s) of data and get the same result as if it was
- * encrypted in one call. This allows a "streaming" usage.
- * If on the other hand you need to retain the contents of the
- * IV, you should either save it manually or use the cipher
- * module instead.
- *
- * \param ctx DES context
- * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length length of the input data
- * \param iv initialization vector (updated after use)
- * \param input buffer holding the input data
- * \param output buffer holding the output data
- */
-int mbedtls_des_crypt_cbc( mbedtls_des_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief 3DES-ECB block encryption/decryption
- *
- * \param ctx 3DES context
- * \param input 64-bit input block
- * \param output 64-bit output block
- *
- * \return 0 if successful
- */
-int mbedtls_des3_crypt_ecb( mbedtls_des3_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief 3DES-CBC buffer encryption/decryption
- *
- * \note Upon exit, the content of the IV is updated so that you can
- * call the function same function again on the following
- * block(s) of data and get the same result as if it was
- * encrypted in one call. This allows a "streaming" usage.
- * If on the other hand you need to retain the contents of the
- * IV, you should either save it manually or use the cipher
- * module instead.
- *
- * \param ctx 3DES context
- * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length length of the input data
- * \param iv initialization vector (updated after use)
- * \param input buffer holding the input data
- * \param output buffer holding the output data
- *
- * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
- */
-int mbedtls_des3_crypt_cbc( mbedtls_des3_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief Internal function for key expansion.
- * (Only exposed to allow overriding it,
- * see MBEDTLS_DES_SETKEY_ALT)
- *
- * \param SK Round keys
- * \param key Base key
- */
-void mbedtls_des_setkey( uint32_t SK[32],
- const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_DES_ALT */
-
-#endif /* des_alt.h */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,797 +0,0 @@
-/*
- * FIPS-46-3 compliant Triple-DES implementation
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- * DES, on which TDES is based, was originally designed by Horst Feistel
- * at IBM in 1974, and was adopted as a standard by NIST (formerly NBS).
- *
- * http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_C)
-#if defined(MBEDTLS_DES_ALT)
-
-#include "mbedtls/des.h"
-
-#include <string.h>
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
- volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i) \
-{ \
- (n) = ( (uint32_t) (b)[(i) ] << 24 ) \
- | ( (uint32_t) (b)[(i) + 1] << 16 ) \
- | ( (uint32_t) (b)[(i) + 2] << 8 ) \
- | ( (uint32_t) (b)[(i) + 3] ); \
-}
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i) \
-{ \
- (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \
- (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \
- (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \
- (b)[(i) + 3] = (unsigned char) ( (n) ); \
-}
-#endif
-
-/*
- * Expanded DES S-boxes
- */
-static const uint32_t SB1[64] =
-{
- 0x01010400, 0x00000000, 0x00010000, 0x01010404,
- 0x01010004, 0x00010404, 0x00000004, 0x00010000,
- 0x00000400, 0x01010400, 0x01010404, 0x00000400,
- 0x01000404, 0x01010004, 0x01000000, 0x00000004,
- 0x00000404, 0x01000400, 0x01000400, 0x00010400,
- 0x00010400, 0x01010000, 0x01010000, 0x01000404,
- 0x00010004, 0x01000004, 0x01000004, 0x00010004,
- 0x00000000, 0x00000404, 0x00010404, 0x01000000,
- 0x00010000, 0x01010404, 0x00000004, 0x01010000,
- 0x01010400, 0x01000000, 0x01000000, 0x00000400,
- 0x01010004, 0x00010000, 0x00010400, 0x01000004,
- 0x00000400, 0x00000004, 0x01000404, 0x00010404,
- 0x01010404, 0x00010004, 0x01010000, 0x01000404,
- 0x01000004, 0x00000404, 0x00010404, 0x01010400,
- 0x00000404, 0x01000400, 0x01000400, 0x00000000,
- 0x00010004, 0x00010400, 0x00000000, 0x01010004
-};
-
-static const uint32_t SB2[64] =
-{
- 0x80108020, 0x80008000, 0x00008000, 0x00108020,
- 0x00100000, 0x00000020, 0x80100020, 0x80008020,
- 0x80000020, 0x80108020, 0x80108000, 0x80000000,
- 0x80008000, 0x00100000, 0x00000020, 0x80100020,
- 0x00108000, 0x00100020, 0x80008020, 0x00000000,
- 0x80000000, 0x00008000, 0x00108020, 0x80100000,
- 0x00100020, 0x80000020, 0x00000000, 0x00108000,
- 0x00008020, 0x80108000, 0x80100000, 0x00008020,
- 0x00000000, 0x00108020, 0x80100020, 0x00100000,
- 0x80008020, 0x80100000, 0x80108000, 0x00008000,
- 0x80100000, 0x80008000, 0x00000020, 0x80108020,
- 0x00108020, 0x00000020, 0x00008000, 0x80000000,
- 0x00008020, 0x80108000, 0x00100000, 0x80000020,
- 0x00100020, 0x80008020, 0x80000020, 0x00100020,
- 0x00108000, 0x00000000, 0x80008000, 0x00008020,
- 0x80000000, 0x80100020, 0x80108020, 0x00108000
-};
-
-static const uint32_t SB3[64] =
-{
- 0x00000208, 0x08020200, 0x00000000, 0x08020008,
- 0x08000200, 0x00000000, 0x00020208, 0x08000200,
- 0x00020008, 0x08000008, 0x08000008, 0x00020000,
- 0x08020208, 0x00020008, 0x08020000, 0x00000208,
- 0x08000000, 0x00000008, 0x08020200, 0x00000200,
- 0x00020200, 0x08020000, 0x08020008, 0x00020208,
- 0x08000208, 0x00020200, 0x00020000, 0x08000208,
- 0x00000008, 0x08020208, 0x00000200, 0x08000000,
- 0x08020200, 0x08000000, 0x00020008, 0x00000208,
- 0x00020000, 0x08020200, 0x08000200, 0x00000000,
- 0x00000200, 0x00020008, 0x08020208, 0x08000200,
- 0x08000008, 0x00000200, 0x00000000, 0x08020008,
- 0x08000208, 0x00020000, 0x08000000, 0x08020208,
- 0x00000008, 0x00020208, 0x00020200, 0x08000008,
- 0x08020000, 0x08000208, 0x00000208, 0x08020000,
- 0x00020208, 0x00000008, 0x08020008, 0x00020200
-};
-
-static const uint32_t SB4[64] =
-{
- 0x00802001, 0x00002081, 0x00002081, 0x00000080,
- 0x00802080, 0x00800081, 0x00800001, 0x00002001,
- 0x00000000, 0x00802000, 0x00802000, 0x00802081,
- 0x00000081, 0x00000000, 0x00800080, 0x00800001,
- 0x00000001, 0x00002000, 0x00800000, 0x00802001,
- 0x00000080, 0x00800000, 0x00002001, 0x00002080,
- 0x00800081, 0x00000001, 0x00002080, 0x00800080,
- 0x00002000, 0x00802080, 0x00802081, 0x00000081,
- 0x00800080, 0x00800001, 0x00802000, 0x00802081,
- 0x00000081, 0x00000000, 0x00000000, 0x00802000,
- 0x00002080, 0x00800080, 0x00800081, 0x00000001,
- 0x00802001, 0x00002081, 0x00002081, 0x00000080,
- 0x00802081, 0x00000081, 0x00000001, 0x00002000,
- 0x00800001, 0x00002001, 0x00802080, 0x00800081,
- 0x00002001, 0x00002080, 0x00800000, 0x00802001,
- 0x00000080, 0x00800000, 0x00002000, 0x00802080
-};
-
-static const uint32_t SB5[64] =
-{
- 0x00000100, 0x02080100, 0x02080000, 0x42000100,
- 0x00080000, 0x00000100, 0x40000000, 0x02080000,
- 0x40080100, 0x00080000, 0x02000100, 0x40080100,
- 0x42000100, 0x42080000, 0x00080100, 0x40000000,
- 0x02000000, 0x40080000, 0x40080000, 0x00000000,
- 0x40000100, 0x42080100, 0x42080100, 0x02000100,
- 0x42080000, 0x40000100, 0x00000000, 0x42000000,
- 0x02080100, 0x02000000, 0x42000000, 0x00080100,
- 0x00080000, 0x42000100, 0x00000100, 0x02000000,
- 0x40000000, 0x02080000, 0x42000100, 0x40080100,
- 0x02000100, 0x40000000, 0x42080000, 0x02080100,
- 0x40080100, 0x00000100, 0x02000000, 0x42080000,
- 0x42080100, 0x00080100, 0x42000000, 0x42080100,
- 0x02080000, 0x00000000, 0x40080000, 0x42000000,
- 0x00080100, 0x02000100, 0x40000100, 0x00080000,
- 0x00000000, 0x40080000, 0x02080100, 0x40000100
-};
-
-static const uint32_t SB6[64] =
-{
- 0x20000010, 0x20400000, 0x00004000, 0x20404010,
- 0x20400000, 0x00000010, 0x20404010, 0x00400000,
- 0x20004000, 0x00404010, 0x00400000, 0x20000010,
- 0x00400010, 0x20004000, 0x20000000, 0x00004010,
- 0x00000000, 0x00400010, 0x20004010, 0x00004000,
- 0x00404000, 0x20004010, 0x00000010, 0x20400010,
- 0x20400010, 0x00000000, 0x00404010, 0x20404000,
- 0x00004010, 0x00404000, 0x20404000, 0x20000000,
- 0x20004000, 0x00000010, 0x20400010, 0x00404000,
- 0x20404010, 0x00400000, 0x00004010, 0x20000010,
- 0x00400000, 0x20004000, 0x20000000, 0x00004010,
- 0x20000010, 0x20404010, 0x00404000, 0x20400000,
- 0x00404010, 0x20404000, 0x00000000, 0x20400010,
- 0x00000010, 0x00004000, 0x20400000, 0x00404010,
- 0x00004000, 0x00400010, 0x20004010, 0x00000000,
- 0x20404000, 0x20000000, 0x00400010, 0x20004010
-};
-
-static const uint32_t SB7[64] =
-{
- 0x00200000, 0x04200002, 0x04000802, 0x00000000,
- 0x00000800, 0x04000802, 0x00200802, 0x04200800,
- 0x04200802, 0x00200000, 0x00000000, 0x04000002,
- 0x00000002, 0x04000000, 0x04200002, 0x00000802,
- 0x04000800, 0x00200802, 0x00200002, 0x04000800,
- 0x04000002, 0x04200000, 0x04200800, 0x00200002,
- 0x04200000, 0x00000800, 0x00000802, 0x04200802,
- 0x00200800, 0x00000002, 0x04000000, 0x00200800,
- 0x04000000, 0x00200800, 0x00200000, 0x04000802,
- 0x04000802, 0x04200002, 0x04200002, 0x00000002,
- 0x00200002, 0x04000000, 0x04000800, 0x00200000,
- 0x04200800, 0x00000802, 0x00200802, 0x04200800,
- 0x00000802, 0x04000002, 0x04200802, 0x04200000,
- 0x00200800, 0x00000000, 0x00000002, 0x04200802,
- 0x00000000, 0x00200802, 0x04200000, 0x00000800,
- 0x04000002, 0x04000800, 0x00000800, 0x00200002
-};
-
-static const uint32_t SB8[64] =
-{
- 0x10001040, 0x00001000, 0x00040000, 0x10041040,
- 0x10000000, 0x10001040, 0x00000040, 0x10000000,
- 0x00040040, 0x10040000, 0x10041040, 0x00041000,
- 0x10041000, 0x00041040, 0x00001000, 0x00000040,
- 0x10040000, 0x10000040, 0x10001000, 0x00001040,
- 0x00041000, 0x00040040, 0x10040040, 0x10041000,
- 0x00001040, 0x00000000, 0x00000000, 0x10040040,
- 0x10000040, 0x10001000, 0x00041040, 0x00040000,
- 0x00041040, 0x00040000, 0x10041000, 0x00001000,
- 0x00000040, 0x10040040, 0x00001000, 0x00041040,
- 0x10001000, 0x00000040, 0x10000040, 0x10040000,
- 0x10040040, 0x10000000, 0x00040000, 0x10001040,
- 0x00000000, 0x10041040, 0x00040040, 0x10000040,
- 0x10040000, 0x10001000, 0x10001040, 0x00000000,
- 0x10041040, 0x00041000, 0x00041000, 0x00001040,
- 0x00001040, 0x00040040, 0x10000000, 0x10041000
-};
-
-/*
- * PC1: left and right halves bit-swap
- */
-static const uint32_t LHs[16] =
-{
- 0x00000000, 0x00000001, 0x00000100, 0x00000101,
- 0x00010000, 0x00010001, 0x00010100, 0x00010101,
- 0x01000000, 0x01000001, 0x01000100, 0x01000101,
- 0x01010000, 0x01010001, 0x01010100, 0x01010101
-};
-
-static const uint32_t RHs[16] =
-{
- 0x00000000, 0x01000000, 0x00010000, 0x01010000,
- 0x00000100, 0x01000100, 0x00010100, 0x01010100,
- 0x00000001, 0x01000001, 0x00010001, 0x01010001,
- 0x00000101, 0x01000101, 0x00010101, 0x01010101,
-};
-
-/*
- * Initial Permutation macro
- */
-#define DES_IP(X,Y) \
-{ \
- T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \
- T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \
- T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \
- T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \
- Y = ((Y << 1) | (Y >> 31)) & 0xFFFFFFFF; \
- T = (X ^ Y) & 0xAAAAAAAA; Y ^= T; X ^= T; \
- X = ((X << 1) | (X >> 31)) & 0xFFFFFFFF; \
-}
-
-/*
- * Final Permutation macro
- */
-#define DES_FP(X,Y) \
-{ \
- X = ((X << 31) | (X >> 1)) & 0xFFFFFFFF; \
- T = (X ^ Y) & 0xAAAAAAAA; X ^= T; Y ^= T; \
- Y = ((Y << 31) | (Y >> 1)) & 0xFFFFFFFF; \
- T = ((Y >> 8) ^ X) & 0x00FF00FF; X ^= T; Y ^= (T << 8); \
- T = ((Y >> 2) ^ X) & 0x33333333; X ^= T; Y ^= (T << 2); \
- T = ((X >> 16) ^ Y) & 0x0000FFFF; Y ^= T; X ^= (T << 16); \
- T = ((X >> 4) ^ Y) & 0x0F0F0F0F; Y ^= T; X ^= (T << 4); \
-}
-
-/*
- * DES round macro
- */
-#define DES_ROUND(X,Y) \
-{ \
- T = *SK++ ^ X; \
- Y ^= SB8[ (T ) & 0x3F ] ^ \
- SB6[ (T >> 8) & 0x3F ] ^ \
- SB4[ (T >> 16) & 0x3F ] ^ \
- SB2[ (T >> 24) & 0x3F ]; \
- \
- T = *SK++ ^ ((X << 28) | (X >> 4)); \
- Y ^= SB7[ (T ) & 0x3F ] ^ \
- SB5[ (T >> 8) & 0x3F ] ^ \
- SB3[ (T >> 16) & 0x3F ] ^ \
- SB1[ (T >> 24) & 0x3F ]; \
-}
-
-#define SWAP(a,b) { uint32_t t = a; a = b; b = t; t = 0; }
-
-void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx )
-{
- memset( ctx, 0, sizeof( mbedtls_des_sw_context ) );
-}
-
-void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx )
-{
- if( ctx == NULL )
- return;
-
- mbedtls_zeroize( ctx, sizeof( mbedtls_des_sw_context ) );
-}
-
-void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx )
-{
- memset( ctx, 0, sizeof( mbedtls_des3_sw_context ) );
-}
-
-void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx )
-{
- if( ctx == NULL )
- return;
-
- mbedtls_zeroize( ctx, sizeof( mbedtls_des3_sw_context ) );
-}
-
-static const unsigned char odd_parity_table[128] = { 1, 2, 4, 7, 8,
- 11, 13, 14, 16, 19, 21, 22, 25, 26, 28, 31, 32, 35, 37, 38, 41, 42, 44,
- 47, 49, 50, 52, 55, 56, 59, 61, 62, 64, 67, 69, 70, 73, 74, 76, 79, 81,
- 82, 84, 87, 88, 91, 93, 94, 97, 98, 100, 103, 104, 107, 109, 110, 112,
- 115, 117, 118, 121, 122, 124, 127, 128, 131, 133, 134, 137, 138, 140,
- 143, 145, 146, 148, 151, 152, 155, 157, 158, 161, 162, 164, 167, 168,
- 171, 173, 174, 176, 179, 181, 182, 185, 186, 188, 191, 193, 194, 196,
- 199, 200, 203, 205, 206, 208, 211, 213, 214, 217, 218, 220, 223, 224,
- 227, 229, 230, 233, 234, 236, 239, 241, 242, 244, 247, 248, 251, 253,
- 254 };
-
-void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- int i;
-
- for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
- key[i] = odd_parity_table[key[i] / 2];
-}
-
-/*
- * Check the given key's parity, returns 1 on failure, 0 on SUCCESS
- */
-int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- int i;
-
- for( i = 0; i < MBEDTLS_DES_KEY_SIZE; i++ )
- if( key[i] != odd_parity_table[key[i] / 2] )
- return( 1 );
-
- return( 0 );
-}
-
-/*
- * Table of weak and semi-weak keys
- *
- * Source: http://en.wikipedia.org/wiki/Weak_key
- *
- * Weak:
- * Alternating ones + zeros (0x0101010101010101)
- * Alternating 'F' + 'E' (0xFEFEFEFEFEFEFEFE)
- * '0xE0E0E0E0F1F1F1F1'
- * '0x1F1F1F1F0E0E0E0E'
- *
- * Semi-weak:
- * 0x011F011F010E010E and 0x1F011F010E010E01
- * 0x01E001E001F101F1 and 0xE001E001F101F101
- * 0x01FE01FE01FE01FE and 0xFE01FE01FE01FE01
- * 0x1FE01FE00EF10EF1 and 0xE01FE01FF10EF10E
- * 0x1FFE1FFE0EFE0EFE and 0xFE1FFE1FFE0EFE0E
- * 0xE0FEE0FEF1FEF1FE and 0xFEE0FEE0FEF1FEF1
- *
- */
-
-#define WEAK_KEY_COUNT 16
-
-static const unsigned char weak_key_table[WEAK_KEY_COUNT][MBEDTLS_DES_KEY_SIZE] =
-{
- { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 },
- { 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
- { 0x1F, 0x1F, 0x1F, 0x1F, 0x0E, 0x0E, 0x0E, 0x0E },
- { 0xE0, 0xE0, 0xE0, 0xE0, 0xF1, 0xF1, 0xF1, 0xF1 },
-
- { 0x01, 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E },
- { 0x1F, 0x01, 0x1F, 0x01, 0x0E, 0x01, 0x0E, 0x01 },
- { 0x01, 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1 },
- { 0xE0, 0x01, 0xE0, 0x01, 0xF1, 0x01, 0xF1, 0x01 },
- { 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE },
- { 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01, 0xFE, 0x01 },
- { 0x1F, 0xE0, 0x1F, 0xE0, 0x0E, 0xF1, 0x0E, 0xF1 },
- { 0xE0, 0x1F, 0xE0, 0x1F, 0xF1, 0x0E, 0xF1, 0x0E },
- { 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E, 0xFE },
- { 0xFE, 0x1F, 0xFE, 0x1F, 0xFE, 0x0E, 0xFE, 0x0E },
- { 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1, 0xFE },
- { 0xFE, 0xE0, 0xFE, 0xE0, 0xFE, 0xF1, 0xFE, 0xF1 }
-};
-
-int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- int i;
-
- for( i = 0; i < WEAK_KEY_COUNT; i++ )
- if( memcmp( weak_key_table[i], key, MBEDTLS_DES_KEY_SIZE) == 0 )
- return( 1 );
-
- return( 0 );
-}
-
-void mbedtls_des_setkey( uint32_t SK[32], const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- int i;
- uint32_t X, Y, T;
-
- GET_UINT32_BE( X, key, 0 );
- GET_UINT32_BE( Y, key, 4 );
-
- /*
- * Permuted Choice 1
- */
- T = ((Y >> 4) ^ X) & 0x0F0F0F0F; X ^= T; Y ^= (T << 4);
- T = ((Y ) ^ X) & 0x10101010; X ^= T; Y ^= (T );
-
- X = (LHs[ (X ) & 0xF] << 3) | (LHs[ (X >> 8) & 0xF ] << 2)
- | (LHs[ (X >> 16) & 0xF] << 1) | (LHs[ (X >> 24) & 0xF ] )
- | (LHs[ (X >> 5) & 0xF] << 7) | (LHs[ (X >> 13) & 0xF ] << 6)
- | (LHs[ (X >> 21) & 0xF] << 5) | (LHs[ (X >> 29) & 0xF ] << 4);
-
- Y = (RHs[ (Y >> 1) & 0xF] << 3) | (RHs[ (Y >> 9) & 0xF ] << 2)
- | (RHs[ (Y >> 17) & 0xF] << 1) | (RHs[ (Y >> 25) & 0xF ] )
- | (RHs[ (Y >> 4) & 0xF] << 7) | (RHs[ (Y >> 12) & 0xF ] << 6)
- | (RHs[ (Y >> 20) & 0xF] << 5) | (RHs[ (Y >> 28) & 0xF ] << 4);
-
- X &= 0x0FFFFFFF;
- Y &= 0x0FFFFFFF;
-
- /*
- * calculate subkeys
- */
- for( i = 0; i < 16; i++ )
- {
- if( i < 2 || i == 8 || i == 15 )
- {
- X = ((X << 1) | (X >> 27)) & 0x0FFFFFFF;
- Y = ((Y << 1) | (Y >> 27)) & 0x0FFFFFFF;
- }
- else
- {
- X = ((X << 2) | (X >> 26)) & 0x0FFFFFFF;
- Y = ((Y << 2) | (Y >> 26)) & 0x0FFFFFFF;
- }
-
- *SK++ = ((X << 4) & 0x24000000) | ((X << 28) & 0x10000000)
- | ((X << 14) & 0x08000000) | ((X << 18) & 0x02080000)
- | ((X << 6) & 0x01000000) | ((X << 9) & 0x00200000)
- | ((X >> 1) & 0x00100000) | ((X << 10) & 0x00040000)
- | ((X << 2) & 0x00020000) | ((X >> 10) & 0x00010000)
- | ((Y >> 13) & 0x00002000) | ((Y >> 4) & 0x00001000)
- | ((Y << 6) & 0x00000800) | ((Y >> 1) & 0x00000400)
- | ((Y >> 14) & 0x00000200) | ((Y ) & 0x00000100)
- | ((Y >> 5) & 0x00000020) | ((Y >> 10) & 0x00000010)
- | ((Y >> 3) & 0x00000008) | ((Y >> 18) & 0x00000004)
- | ((Y >> 26) & 0x00000002) | ((Y >> 24) & 0x00000001);
-
- *SK++ = ((X << 15) & 0x20000000) | ((X << 17) & 0x10000000)
- | ((X << 10) & 0x08000000) | ((X << 22) & 0x04000000)
- | ((X >> 2) & 0x02000000) | ((X << 1) & 0x01000000)
- | ((X << 16) & 0x00200000) | ((X << 11) & 0x00100000)
- | ((X << 3) & 0x00080000) | ((X >> 6) & 0x00040000)
- | ((X << 15) & 0x00020000) | ((X >> 4) & 0x00010000)
- | ((Y >> 2) & 0x00002000) | ((Y << 8) & 0x00001000)
- | ((Y >> 14) & 0x00000808) | ((Y >> 9) & 0x00000400)
- | ((Y ) & 0x00000200) | ((Y << 7) & 0x00000100)
- | ((Y >> 7) & 0x00000020) | ((Y >> 3) & 0x00000011)
- | ((Y << 2) & 0x00000004) | ((Y >> 21) & 0x00000002);
- }
-}
-
-/*
- * DES key schedule (56-bit, encryption)
- */
-int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- mbedtls_des_setkey( ctx->sk, key );
-
- return( 0 );
-}
-
-/*
- * DES key schedule (56-bit, decryption)
- */
-int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] )
-{
- int i;
-
- mbedtls_des_setkey( ctx->sk, key );
-
- for( i = 0; i < 16; i += 2 )
- {
- SWAP( ctx->sk[i ], ctx->sk[30 - i] );
- SWAP( ctx->sk[i + 1], ctx->sk[31 - i] );
- }
-
- return( 0 );
-}
-
-static void des3_set2key( uint32_t esk[96],
- uint32_t dsk[96],
- const unsigned char key[MBEDTLS_DES_KEY_SIZE*2] )
-{
- int i;
-
- mbedtls_des_setkey( esk, key );
- mbedtls_des_setkey( dsk + 32, key + 8 );
-
- for( i = 0; i < 32; i += 2 )
- {
- dsk[i ] = esk[30 - i];
- dsk[i + 1] = esk[31 - i];
-
- esk[i + 32] = dsk[62 - i];
- esk[i + 33] = dsk[63 - i];
-
- esk[i + 64] = esk[i ];
- esk[i + 65] = esk[i + 1];
-
- dsk[i + 64] = dsk[i ];
- dsk[i + 65] = dsk[i + 1];
- }
-}
-
-/*
- * Triple-DES key schedule (112-bit, encryption)
- */
-int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
- uint32_t sk[96];
-
- des3_set2key( ctx->sk, sk, key );
- mbedtls_zeroize( sk, sizeof( sk ) );
-
- return( 0 );
-}
-
-/*
- * Triple-DES key schedule (112-bit, decryption)
- */
-int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] )
-{
- uint32_t sk[96];
-
- des3_set2key( sk, ctx->sk, key );
- mbedtls_zeroize( sk, sizeof( sk ) );
-
- return( 0 );
-}
-
-static void des3_set3key( uint32_t esk[96],
- uint32_t dsk[96],
- const unsigned char key[24] )
-{
- int i;
-
- mbedtls_des_setkey( esk, key );
- mbedtls_des_setkey( dsk + 32, key + 8 );
- mbedtls_des_setkey( esk + 64, key + 16 );
-
- for( i = 0; i < 32; i += 2 )
- {
- dsk[i ] = esk[94 - i];
- dsk[i + 1] = esk[95 - i];
-
- esk[i + 32] = dsk[62 - i];
- esk[i + 33] = dsk[63 - i];
-
- dsk[i + 64] = esk[30 - i];
- dsk[i + 65] = esk[31 - i];
- }
-}
-
-/*
- * Triple-DES key schedule (168-bit, encryption)
- */
-int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
- uint32_t sk[96];
-
- des3_set3key( ctx->sk, sk, key );
- mbedtls_zeroize( sk, sizeof( sk ) );
-
- return( 0 );
-}
-
-/*
- * Triple-DES key schedule (168-bit, decryption)
- */
-int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] )
-{
- uint32_t sk[96];
-
- des3_set3key( sk, ctx->sk, key );
- mbedtls_zeroize( sk, sizeof( sk ) );
-
- return( 0 );
-}
-
-/*
- * DES-ECB block encryption/decryption
- */
-int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] )
-{
- int i;
- uint32_t X, Y, T, *SK;
-
- SK = ctx->sk;
-
- GET_UINT32_BE( X, input, 0 );
- GET_UINT32_BE( Y, input, 4 );
-
- DES_IP( X, Y );
-
- for( i = 0; i < 8; i++ )
- {
- DES_ROUND( Y, X );
- DES_ROUND( X, Y );
- }
-
- DES_FP( Y, X );
-
- PUT_UINT32_BE( Y, output, 0 );
- PUT_UINT32_BE( X, output, 4 );
-
- return( 0 );
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * DES-CBC buffer encryption/decryption
- */
-int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output )
-{
- int i;
- unsigned char temp[8];
-
- if( length % 8 )
- return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH );
-
- if( mode == MBEDTLS_DES_ENCRYPT )
- {
- while( length > 0 )
- {
- for( i = 0; i < 8; i++ )
- output[i] = (unsigned char)( input[i] ^ iv[i] );
-
- mbedtls_des_sw_crypt_ecb( ctx, output, output );
- memcpy( iv, output, 8 );
-
- input += 8;
- output += 8;
- length -= 8;
- }
- }
- else /* MBEDTLS_DES_DECRYPT */
- {
- while( length > 0 )
- {
- memcpy( temp, input, 8 );
- mbedtls_des_sw_crypt_ecb( ctx, input, output );
-
- for( i = 0; i < 8; i++ )
- output[i] = (unsigned char)( output[i] ^ iv[i] );
-
- memcpy( iv, temp, 8 );
-
- input += 8;
- output += 8;
- length -= 8;
- }
- }
-
- return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/*
- * 3DES-ECB block encryption/decryption
- */
-int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] )
-{
- int i;
- uint32_t X, Y, T, *SK;
-
- SK = ctx->sk;
-
- GET_UINT32_BE( X, input, 0 );
- GET_UINT32_BE( Y, input, 4 );
-
- DES_IP( X, Y );
-
- for( i = 0; i < 8; i++ )
- {
- DES_ROUND( Y, X );
- DES_ROUND( X, Y );
- }
-
- for( i = 0; i < 8; i++ )
- {
- DES_ROUND( X, Y );
- DES_ROUND( Y, X );
- }
-
- for( i = 0; i < 8; i++ )
- {
- DES_ROUND( Y, X );
- DES_ROUND( X, Y );
- }
-
- DES_FP( Y, X );
-
- PUT_UINT32_BE( Y, output, 0 );
- PUT_UINT32_BE( X, output, 4 );
-
- return( 0 );
-}
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/*
- * 3DES-CBC buffer encryption/decryption
- */
-int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output )
-{
- int i;
- unsigned char temp[8];
-
- if( length % 8 )
- return( MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH );
-
- if( mode == MBEDTLS_DES_ENCRYPT )
- {
- while( length > 0 )
- {
- for( i = 0; i < 8; i++ )
- output[i] = (unsigned char)( input[i] ^ iv[i] );
-
- mbedtls_des3_sw_crypt_ecb( ctx, output, output );
- memcpy( iv, output, 8 );
-
- input += 8;
- output += 8;
- length -= 8;
- }
- }
- else /* MBEDTLS_DES_DECRYPT */
- {
- while( length > 0 )
- {
- memcpy( temp, input, 8 );
- mbedtls_des3_sw_crypt_ecb( ctx, input, output );
-
- for( i = 0; i < 8; i++ )
- output[i] = (unsigned char)( output[i] ^ iv[i] );
-
- memcpy( iv, temp, 8 );
-
- input += 8;
- output += 8;
- length -= 8;
- }
- }
-
- return( 0 );
-}
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-#endif /* MBEDTLS_DES_ALT */
-#endif /* MBEDTLS_DES_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/des/des_alt_sw.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,283 +0,0 @@
-/**
- * \file des.h
- *
- * \brief DES block cipher
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_DES_ALT_SW_H
-#define MBEDTLS_DES_ALT_SW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_DES_C)
-#if defined(MBEDTLS_DES_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief DES context structure
- */
-typedef struct
-{
- uint32_t sk[32]; /*!< DES subkeys */
-}
-mbedtls_des_sw_context;
-
-/**
- * \brief Triple-DES context structure
- */
-typedef struct
-{
- uint32_t sk[96]; /*!< 3DES subkeys */
-}
-mbedtls_des3_sw_context;
-
-/**
- * \brief Initialize DES context
- *
- * \param ctx DES context to be initialized
- */
-void mbedtls_des_sw_init( mbedtls_des_sw_context *ctx );
-
-/**
- * \brief Clear DES context
- *
- * \param ctx DES context to be cleared
- */
-void mbedtls_des_sw_free( mbedtls_des_sw_context *ctx );
-
-/**
- * \brief Initialize Triple-DES context
- *
- * \param ctx DES3 context to be initialized
- */
-void mbedtls_des3_sw_init( mbedtls_des3_sw_context *ctx );
-
-/**
- * \brief Clear Triple-DES context
- *
- * \param ctx DES3 context to be cleared
- */
-void mbedtls_des3_sw_free( mbedtls_des3_sw_context *ctx );
-
-/**
- * \brief Set key parity on the given key to odd.
- *
- * DES keys are 56 bits long, but each byte is padded with
- * a parity bit to allow verification.
- *
- * \param key 8-byte secret key
- */
-void mbedtls_des_sw_key_set_parity( unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief Check that key parity on the given key is odd.
- *
- * DES keys are 56 bits long, but each byte is padded with
- * a parity bit to allow verification.
- *
- * \param key 8-byte secret key
- *
- * \return 0 is parity was ok, 1 if parity was not correct.
- */
-int mbedtls_des_sw_key_check_key_parity( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief Check that key is not a weak or semi-weak DES key
- *
- * \param key 8-byte secret key
- *
- * \return 0 if no weak key was found, 1 if a weak key was identified.
- */
-int mbedtls_des_sw_key_check_weak( const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief DES key schedule (56-bit, encryption)
- *
- * \param ctx DES context to be initialized
- * \param key 8-byte secret key
- *
- * \return 0
- */
-int mbedtls_des_sw_setkey_enc( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief DES key schedule (56-bit, decryption)
- *
- * \param ctx DES context to be initialized
- * \param key 8-byte secret key
- *
- * \return 0
- */
-int mbedtls_des_sw_setkey_dec( mbedtls_des_sw_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-/**
- * \brief Triple-DES key schedule (112-bit, encryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 16-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_sw_set2key_enc( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief Triple-DES key schedule (112-bit, decryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 16-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_sw_set2key_dec( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2] );
-
-/**
- * \brief Triple-DES key schedule (168-bit, encryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 24-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_sw_set3key_enc( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief Triple-DES key schedule (168-bit, decryption)
- *
- * \param ctx 3DES context to be initialized
- * \param key 24-byte secret key
- *
- * \return 0
- */
-int mbedtls_des3_sw_set3key_dec( mbedtls_des3_sw_context *ctx,
- const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3] );
-
-/**
- * \brief DES-ECB block encryption/decryption
- *
- * \param ctx DES context
- * \param input 64-bit input block
- * \param output 64-bit output block
- *
- * \return 0 if successful
- */
-int mbedtls_des_sw_crypt_ecb( mbedtls_des_sw_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief DES-CBC buffer encryption/decryption
- *
- * \note Upon exit, the content of the IV is updated so that you can
- * call the function same function again on the following
- * block(s) of data and get the same result as if it was
- * encrypted in one call. This allows a "streaming" usage.
- * If on the other hand you need to retain the contents of the
- * IV, you should either save it manually or use the cipher
- * module instead.
- *
- * \param ctx DES context
- * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length length of the input data
- * \param iv initialization vector (updated after use)
- * \param input buffer holding the input data
- * \param output buffer holding the output data
- */
-int mbedtls_des_sw_crypt_cbc( mbedtls_des_sw_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief 3DES-ECB block encryption/decryption
- *
- * \param ctx 3DES context
- * \param input 64-bit input block
- * \param output 64-bit output block
- *
- * \return 0 if successful
- */
-int mbedtls_des3_sw_crypt_ecb( mbedtls_des3_sw_context *ctx,
- const unsigned char input[8],
- unsigned char output[8] );
-
-#if defined(MBEDTLS_CIPHER_MODE_CBC)
-/**
- * \brief 3DES-CBC buffer encryption/decryption
- *
- * \note Upon exit, the content of the IV is updated so that you can
- * call the function same function again on the following
- * block(s) of data and get the same result as if it was
- * encrypted in one call. This allows a "streaming" usage.
- * If on the other hand you need to retain the contents of the
- * IV, you should either save it manually or use the cipher
- * module instead.
- *
- * \param ctx 3DES context
- * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT
- * \param length length of the input data
- * \param iv initialization vector (updated after use)
- * \param input buffer holding the input data
- * \param output buffer holding the output data
- *
- * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH
- */
-int mbedtls_des3_sw_crypt_cbc( mbedtls_des3_sw_context *ctx,
- int mode,
- size_t length,
- unsigned char iv[8],
- const unsigned char *input,
- unsigned char *output );
-#endif /* MBEDTLS_CIPHER_MODE_CBC */
-
-/**
- * \brief Internal function for key expansion.
- * (Only exposed to allow overriding it,
- * see MBEDTLS_DES_SETKEY_ALT)
- *
- * \param SK Round keys
- * \param key Base key
- */
-void mbedtls_des_sw_setkey( uint32_t SK[32],
- const unsigned char key[MBEDTLS_DES_KEY_SIZE] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_DES_ALT */
-#endif /* MBEDTLS_DES_C */
-
-#endif /* des.h */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,136 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include "sha1_alt.h"
-#include "crypto-misc.h"
-#include "nu_bitutil.h"
-#include "string.h"
-
-void mbedtls_sha1_init(mbedtls_sha1_context *ctx)
-{
- if (crypto_sha_acquire()) {
- ctx->ishw = 1;
- mbedtls_sha1_hw_init(&ctx->hw_ctx);
- }
- else {
- ctx->ishw = 0;
- mbedtls_sha1_sw_init(&ctx->sw_ctx);
- }
-}
-
-void mbedtls_sha1_free(mbedtls_sha1_context *ctx)
-{
- if (ctx == NULL) {
- return;
- }
-
- if (ctx->ishw) {
- mbedtls_sha1_hw_free(&ctx->hw_ctx);
- crypto_sha_release();
- }
- else {
- mbedtls_sha1_sw_free(&ctx->sw_ctx);
- }
-}
-
-void mbedtls_sha1_clone(mbedtls_sha1_context *dst,
- const mbedtls_sha1_context *src)
-{
- if (src->ishw) {
- // Clone S/W ctx from H/W ctx
- dst->ishw = 0;
- dst->sw_ctx.total[0] = src->hw_ctx.total;
- dst->sw_ctx.total[1] = 0;
- {
- unsigned char output[20];
- crypto_sha_getinternstate(output, sizeof (output));
- dst->sw_ctx.state[0] = nu_get32_be(output);
- dst->sw_ctx.state[1] = nu_get32_be(output + 4);
- dst->sw_ctx.state[2] = nu_get32_be(output + 8);
- dst->sw_ctx.state[3] = nu_get32_be(output + 12);
- dst->sw_ctx.state[4] = nu_get32_be(output + 16);
- }
- memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
- if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) {
- mbedtls_sha1_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer);
- }
- }
- else {
- // Clone S/W ctx from S/W ctx
- dst->sw_ctx = src->sw_ctx;
- }
-}
-
-/*
- * SHA-1 context setup
- */
-void mbedtls_sha1_starts(mbedtls_sha1_context *ctx)
-{
- if (ctx->ishw) {
- mbedtls_sha1_hw_starts(&ctx->hw_ctx);
- }
- else {
- mbedtls_sha1_sw_starts(&ctx->sw_ctx);
- }
-}
-
-/*
- * SHA-1 process buffer
- */
-void mbedtls_sha1_update(mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen)
-{
- if (ctx->ishw) {
- mbedtls_sha1_hw_update(&ctx->hw_ctx, input, ilen);
- }
- else {
- mbedtls_sha1_sw_update(&ctx->sw_ctx, input, ilen);
- }
-}
-
-/*
- * SHA-1 final digest
- */
-void mbedtls_sha1_finish(mbedtls_sha1_context *ctx, unsigned char output[20])
-{
- if (ctx->ishw) {
- mbedtls_sha1_hw_finish(&ctx->hw_ctx, output);
- }
- else {
- mbedtls_sha1_sw_finish(&ctx->sw_ctx, output);
- }
-}
-
-void mbedtls_sha1_process(mbedtls_sha1_context *ctx, const unsigned char data[64])
-{
- if (ctx->ishw) {
- mbedtls_sha1_hw_process(&ctx->hw_ctx, data);
- }
- else {
- mbedtls_sha1_sw_process(&ctx->sw_ctx, data);
- }
-}
-
-#endif /* MBEDTLS_SHA1_ALT */
-#endif /* MBEDTLS_SHA1_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,106 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBEDTLS_SHA1_ALT_H
-#define MBEDTLS_SHA1_ALT_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include "sha1.h"
-#include "sha_alt_hw.h"
-#include "sha1_alt_sw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct mbedtls_sha1_context_s;
-
-/**
- * \brief SHA-1 context structure
- */
-typedef struct mbedtls_sha1_context_s
-{
- int ishw;
- crypto_sha_context hw_ctx;
- mbedtls_sha1_sw_context sw_ctx;
-}
-mbedtls_sha1_context;
-
-/**
- * \brief Initialize SHA-1 context
- *
- * \param ctx SHA-1 context to be initialized
- */
-void mbedtls_sha1_init( mbedtls_sha1_context *ctx );
-
-/**
- * \brief Clear SHA-1 context
- *
- * \param ctx SHA-1 context to be cleared
- */
-void mbedtls_sha1_free( mbedtls_sha1_context *ctx );
-
-/**
- * \brief Clone (the state of) a SHA-1 context
- *
- * \param dst The destination context
- * \param src The context to be cloned
- */
-void mbedtls_sha1_clone( mbedtls_sha1_context *dst,
- const mbedtls_sha1_context *src );
-
-/**
- * \brief SHA-1 context setup
- *
- * \param ctx context to be initialized
- */
-void mbedtls_sha1_starts( mbedtls_sha1_context *ctx );
-
-/**
- * \brief SHA-1 process buffer
- *
- * \param ctx SHA-1 context
- * \param input buffer holding the data
- * \param ilen length of the input data
- */
-void mbedtls_sha1_update( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen );
-
-/**
- * \brief SHA-1 final digest
- *
- * \param ctx SHA-1 context
- * \param output SHA-1 checksum result
- */
-void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, unsigned char output[20] );
-
-/* Internal use */
-void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA1_ALT */
-#endif /* MBEDTLS_SHA1_C */
-
-#endif /* sha1_alt.h */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,337 +0,0 @@
-/*
- * FIPS-180-1 compliant SHA-1 implementation
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- * The SHA-1 standard was published by NIST in 1993.
- *
- * http://www.itl.nist.gov/fipspubs/fip180-1.htm
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include "mbedtls/sha1.h"
-
-#include <string.h>
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
- volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0;
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i) \
-{ \
- (n) = ( (uint32_t) (b)[(i) ] << 24 ) \
- | ( (uint32_t) (b)[(i) + 1] << 16 ) \
- | ( (uint32_t) (b)[(i) + 2] << 8 ) \
- | ( (uint32_t) (b)[(i) + 3] ); \
-}
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i) \
-{ \
- (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \
- (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \
- (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \
- (b)[(i) + 3] = (unsigned char) ( (n) ); \
-}
-#endif
-
-void mbedtls_sha1_sw_init( mbedtls_sha1_sw_context *ctx )
-{
- memset( ctx, 0, sizeof( mbedtls_sha1_sw_context ) );
-}
-
-void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx )
-{
- if( ctx == NULL )
- return;
-
- mbedtls_zeroize( ctx, sizeof( mbedtls_sha1_sw_context ) );
-}
-
-void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst,
- const mbedtls_sha1_sw_context *src )
-{
- *dst = *src;
-}
-
-/*
- * SHA-1 context setup
- */
-void mbedtls_sha1_sw_starts( mbedtls_sha1_sw_context *ctx )
-{
- ctx->total[0] = 0;
- ctx->total[1] = 0;
-
- ctx->state[0] = 0x67452301;
- ctx->state[1] = 0xEFCDAB89;
- ctx->state[2] = 0x98BADCFE;
- ctx->state[3] = 0x10325476;
- ctx->state[4] = 0xC3D2E1F0;
-}
-
-void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char data[64] )
-{
- uint32_t temp, W[16], A, B, C, D, E;
-
- GET_UINT32_BE( W[ 0], data, 0 );
- GET_UINT32_BE( W[ 1], data, 4 );
- GET_UINT32_BE( W[ 2], data, 8 );
- GET_UINT32_BE( W[ 3], data, 12 );
- GET_UINT32_BE( W[ 4], data, 16 );
- GET_UINT32_BE( W[ 5], data, 20 );
- GET_UINT32_BE( W[ 6], data, 24 );
- GET_UINT32_BE( W[ 7], data, 28 );
- GET_UINT32_BE( W[ 8], data, 32 );
- GET_UINT32_BE( W[ 9], data, 36 );
- GET_UINT32_BE( W[10], data, 40 );
- GET_UINT32_BE( W[11], data, 44 );
- GET_UINT32_BE( W[12], data, 48 );
- GET_UINT32_BE( W[13], data, 52 );
- GET_UINT32_BE( W[14], data, 56 );
- GET_UINT32_BE( W[15], data, 60 );
-
-#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
-
-#define R(t) \
-( \
- temp = W[( t - 3 ) & 0x0F] ^ W[( t - 8 ) & 0x0F] ^ \
- W[( t - 14 ) & 0x0F] ^ W[ t & 0x0F], \
- ( W[t & 0x0F] = S(temp,1) ) \
-)
-
-#define P(a,b,c,d,e,x) \
-{ \
- e += S(a,5) + F(b,c,d) + K + x; b = S(b,30); \
-}
-
- A = ctx->state[0];
- B = ctx->state[1];
- C = ctx->state[2];
- D = ctx->state[3];
- E = ctx->state[4];
-
-#define F(x,y,z) (z ^ (x & (y ^ z)))
-#define K 0x5A827999
-
- P( A, B, C, D, E, W[0] );
- P( E, A, B, C, D, W[1] );
- P( D, E, A, B, C, W[2] );
- P( C, D, E, A, B, W[3] );
- P( B, C, D, E, A, W[4] );
- P( A, B, C, D, E, W[5] );
- P( E, A, B, C, D, W[6] );
- P( D, E, A, B, C, W[7] );
- P( C, D, E, A, B, W[8] );
- P( B, C, D, E, A, W[9] );
- P( A, B, C, D, E, W[10] );
- P( E, A, B, C, D, W[11] );
- P( D, E, A, B, C, W[12] );
- P( C, D, E, A, B, W[13] );
- P( B, C, D, E, A, W[14] );
- P( A, B, C, D, E, W[15] );
- P( E, A, B, C, D, R(16) );
- P( D, E, A, B, C, R(17) );
- P( C, D, E, A, B, R(18) );
- P( B, C, D, E, A, R(19) );
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0x6ED9EBA1
-
- P( A, B, C, D, E, R(20) );
- P( E, A, B, C, D, R(21) );
- P( D, E, A, B, C, R(22) );
- P( C, D, E, A, B, R(23) );
- P( B, C, D, E, A, R(24) );
- P( A, B, C, D, E, R(25) );
- P( E, A, B, C, D, R(26) );
- P( D, E, A, B, C, R(27) );
- P( C, D, E, A, B, R(28) );
- P( B, C, D, E, A, R(29) );
- P( A, B, C, D, E, R(30) );
- P( E, A, B, C, D, R(31) );
- P( D, E, A, B, C, R(32) );
- P( C, D, E, A, B, R(33) );
- P( B, C, D, E, A, R(34) );
- P( A, B, C, D, E, R(35) );
- P( E, A, B, C, D, R(36) );
- P( D, E, A, B, C, R(37) );
- P( C, D, E, A, B, R(38) );
- P( B, C, D, E, A, R(39) );
-
-#undef K
-#undef F
-
-#define F(x,y,z) ((x & y) | (z & (x | y)))
-#define K 0x8F1BBCDC
-
- P( A, B, C, D, E, R(40) );
- P( E, A, B, C, D, R(41) );
- P( D, E, A, B, C, R(42) );
- P( C, D, E, A, B, R(43) );
- P( B, C, D, E, A, R(44) );
- P( A, B, C, D, E, R(45) );
- P( E, A, B, C, D, R(46) );
- P( D, E, A, B, C, R(47) );
- P( C, D, E, A, B, R(48) );
- P( B, C, D, E, A, R(49) );
- P( A, B, C, D, E, R(50) );
- P( E, A, B, C, D, R(51) );
- P( D, E, A, B, C, R(52) );
- P( C, D, E, A, B, R(53) );
- P( B, C, D, E, A, R(54) );
- P( A, B, C, D, E, R(55) );
- P( E, A, B, C, D, R(56) );
- P( D, E, A, B, C, R(57) );
- P( C, D, E, A, B, R(58) );
- P( B, C, D, E, A, R(59) );
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0xCA62C1D6
-
- P( A, B, C, D, E, R(60) );
- P( E, A, B, C, D, R(61) );
- P( D, E, A, B, C, R(62) );
- P( C, D, E, A, B, R(63) );
- P( B, C, D, E, A, R(64) );
- P( A, B, C, D, E, R(65) );
- P( E, A, B, C, D, R(66) );
- P( D, E, A, B, C, R(67) );
- P( C, D, E, A, B, R(68) );
- P( B, C, D, E, A, R(69) );
- P( A, B, C, D, E, R(70) );
- P( E, A, B, C, D, R(71) );
- P( D, E, A, B, C, R(72) );
- P( C, D, E, A, B, R(73) );
- P( B, C, D, E, A, R(74) );
- P( A, B, C, D, E, R(75) );
- P( E, A, B, C, D, R(76) );
- P( D, E, A, B, C, R(77) );
- P( C, D, E, A, B, R(78) );
- P( B, C, D, E, A, R(79) );
-
-#undef K
-#undef F
-
- ctx->state[0] += A;
- ctx->state[1] += B;
- ctx->state[2] += C;
- ctx->state[3] += D;
- ctx->state[4] += E;
-}
-
-/*
- * SHA-1 process buffer
- */
-void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char *input, size_t ilen )
-{
- size_t fill;
- uint32_t left;
-
- if( ilen == 0 )
- return;
-
- left = ctx->total[0] & 0x3F;
- fill = 64 - left;
-
- ctx->total[0] += (uint32_t) ilen;
- ctx->total[0] &= 0xFFFFFFFF;
-
- if( ctx->total[0] < (uint32_t) ilen )
- ctx->total[1]++;
-
- if( left && ilen >= fill )
- {
- memcpy( (void *) (ctx->buffer + left), input, fill );
- mbedtls_sha1_sw_process( ctx, ctx->buffer );
- input += fill;
- ilen -= fill;
- left = 0;
- }
-
- while( ilen >= 64 )
- {
- mbedtls_sha1_sw_process( ctx, input );
- input += 64;
- ilen -= 64;
- }
-
- if( ilen > 0 )
- memcpy( (void *) (ctx->buffer + left), input, ilen );
-}
-
-static const unsigned char sha1_padding[64] =
-{
- 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * SHA-1 final digest
- */
-void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[20] )
-{
- uint32_t last, padn;
- uint32_t high, low;
- unsigned char msglen[8];
-
- high = ( ctx->total[0] >> 29 )
- | ( ctx->total[1] << 3 );
- low = ( ctx->total[0] << 3 );
-
- PUT_UINT32_BE( high, msglen, 0 );
- PUT_UINT32_BE( low, msglen, 4 );
-
- last = ctx->total[0] & 0x3F;
- padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
-
- mbedtls_sha1_sw_update( ctx, sha1_padding, padn );
- mbedtls_sha1_sw_update( ctx, msglen, 8 );
-
- PUT_UINT32_BE( ctx->state[0], output, 0 );
- PUT_UINT32_BE( ctx->state[1], output, 4 );
- PUT_UINT32_BE( ctx->state[2], output, 8 );
- PUT_UINT32_BE( ctx->state[3], output, 12 );
- PUT_UINT32_BE( ctx->state[4], output, 16 );
-}
-
-#endif /* MBEDTLS_SHA1_ALT */
-
-#endif /* MBEDTLS_SHA1_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha1_alt_sw.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/**
- * \file sha1.h
- *
- * \brief SHA-1 cryptographic hash function
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SHA1_ALT_SW_H
-#define MBEDTLS_SHA1_ALT_SW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA1_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief SHA-1 context structure
- */
-typedef struct
-{
- uint32_t total[2]; /*!< number of bytes processed */
- uint32_t state[5]; /*!< intermediate digest state */
- unsigned char buffer[64]; /*!< data block being processed */
-}
-mbedtls_sha1_sw_context;
-
-/**
- * \brief Initialize SHA-1 context
- *
- * \param ctx SHA-1 context to be initialized
- */
-void mbedtls_sha1_sw_init( mbedtls_sha1_sw_context *ctx );
-
-/**
- * \brief Clear SHA-1 context
- *
- * \param ctx SHA-1 context to be cleared
- */
-void mbedtls_sha1_sw_free( mbedtls_sha1_sw_context *ctx );
-
-/**
- * \brief Clone (the state of) a SHA-1 context
- *
- * \param dst The destination context
- * \param src The context to be cloned
- */
-void mbedtls_sha1_sw_clone( mbedtls_sha1_sw_context *dst,
- const mbedtls_sha1_sw_context *src );
-
-/**
- * \brief SHA-1 context setup
- *
- * \param ctx context to be initialized
- */
-void mbedtls_sha1_sw_starts( mbedtls_sha1_sw_context *ctx );
-
-/**
- * \brief SHA-1 process buffer
- *
- * \param ctx SHA-1 context
- * \param input buffer holding the data
- * \param ilen length of the input data
- */
-void mbedtls_sha1_sw_update( mbedtls_sha1_sw_context *ctx, const unsigned char *input, size_t ilen );
-
-/**
- * \brief SHA-1 final digest
- *
- * \param ctx SHA-1 context
- * \param output SHA-1 checksum result
- */
-void mbedtls_sha1_sw_finish( mbedtls_sha1_sw_context *ctx, unsigned char output[20] );
-
-/* Internal use */
-void mbedtls_sha1_sw_process( mbedtls_sha1_sw_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA1_ALT */
-#endif /* MBEDTLS_SHA1_C */
-
-#endif /* sha1_alt_sw.h */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,140 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include "sha256_alt.h"
-#include "crypto-misc.h"
-#include "nu_bitutil.h"
-#include "string.h"
-
-void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
-{
- if (crypto_sha_acquire()) {
- ctx->ishw = 1;
- mbedtls_sha256_hw_init(&ctx->hw_ctx);
- }
- else {
- ctx->ishw = 0;
- mbedtls_sha256_sw_init(&ctx->sw_ctx);
- }
-}
-
-void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
-{
- if (ctx == NULL) {
- return;
- }
-
- if (ctx->ishw) {
- mbedtls_sha256_hw_free(&ctx->hw_ctx);
- crypto_sha_release();
- }
- else {
- mbedtls_sha256_sw_free(&ctx->sw_ctx);
- }
-}
-
-void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
- const mbedtls_sha256_context *src)
-{
- if (src->ishw) {
- // Clone S/W ctx from H/W ctx
- dst->ishw = 0;
- dst->sw_ctx.total[0] = src->hw_ctx.total;
- dst->sw_ctx.total[1] = 0;
- {
- unsigned char output[32];
- crypto_sha_getinternstate(output, sizeof (output));
- dst->sw_ctx.state[0] = nu_get32_be(output);
- dst->sw_ctx.state[1] = nu_get32_be(output + 4);
- dst->sw_ctx.state[2] = nu_get32_be(output + 8);
- dst->sw_ctx.state[3] = nu_get32_be(output + 12);
- dst->sw_ctx.state[4] = nu_get32_be(output + 16);
- dst->sw_ctx.state[5] = nu_get32_be(output + 20);
- dst->sw_ctx.state[6] = nu_get32_be(output + 24);
- dst->sw_ctx.state[7] = nu_get32_be(output + 28);
- }
- memcpy(dst->sw_ctx.buffer, src->hw_ctx.buffer, src->hw_ctx.buffer_left);
- dst->sw_ctx.is224 = src->hw_ctx.is224;
- if (src->hw_ctx.buffer_left == src->hw_ctx.blocksize) {
- mbedtls_sha256_sw_process(&dst->sw_ctx, dst->sw_ctx.buffer);
- }
- }
- else {
- // Clone S/W ctx from S/W ctx
- dst->sw_ctx = src->sw_ctx;
- }
-}
-
-/*
- * SHA-256 context setup
- */
-void mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224)
-{
- if (ctx->ishw) {
- mbedtls_sha256_hw_starts(&ctx->hw_ctx, is224);
- }
- else {
- mbedtls_sha256_sw_starts(&ctx->sw_ctx, is224);
- }
-}
-
-/*
- * SHA-256 process buffer
- */
-void mbedtls_sha256_update(mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen)
-{
- if (ctx->ishw) {
- mbedtls_sha256_hw_update(&ctx->hw_ctx, input, ilen);
- }
- else {
- mbedtls_sha256_sw_update(&ctx->sw_ctx, input, ilen);
- }
-}
-
-/*
- * SHA-256 final digest
- */
-void mbedtls_sha256_finish(mbedtls_sha256_context *ctx, unsigned char output[32])
-{
- if (ctx->ishw) {
- mbedtls_sha256_hw_finish(&ctx->hw_ctx, output);
- }
- else {
- mbedtls_sha256_sw_finish(&ctx->sw_ctx, output);
- }
-}
-
-void mbedtls_sha256_process(mbedtls_sha256_context *ctx, const unsigned char data[64])
-{
- if (ctx->ishw) {
- mbedtls_sha256_hw_process(&ctx->hw_ctx, data);
- }
- else {
- mbedtls_sha256_sw_process(&ctx->sw_ctx, data);
- }
-}
-
-#endif /* MBEDTLS_SHA256_ALT */
-#endif /* MBEDTLS_SHA256_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,108 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBEDTLS_SHA256_ALT_H
-#define MBEDTLS_SHA256_ALT_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include "sha256.h"
-#include "sha_alt_hw.h"
-#include "sha256_alt_sw.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct mbedtls_sha256_context_s;
-
-/**
- * \brief SHA-256 context structure
- */
-typedef struct mbedtls_sha256_context_s
-{
- int ishw;
- crypto_sha_context hw_ctx;
- mbedtls_sha256_sw_context sw_ctx;
-}
-mbedtls_sha256_context;
-
-/**
- * \brief Initialize SHA-256 context
- *
- * \param ctx SHA-256 context to be initialized
- */
-void mbedtls_sha256_init( mbedtls_sha256_context *ctx );
-
-/**
- * \brief Clear SHA-256 context
- *
- * \param ctx SHA-256 context to be cleared
- */
-void mbedtls_sha256_free( mbedtls_sha256_context *ctx );
-
-/**
- * \brief Clone (the state of) a SHA-256 context
- *
- * \param dst The destination context
- * \param src The context to be cloned
- */
-void mbedtls_sha256_clone( mbedtls_sha256_context *dst,
- const mbedtls_sha256_context *src );
-
-/**
- * \brief SHA-256 context setup
- *
- * \param ctx context to be initialized
- * \param is224 0 = use SHA256, 1 = use SHA224
- */
-void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 );
-
-/**
- * \brief SHA-256 process buffer
- *
- * \param ctx SHA-256 context
- * \param input buffer holding the data
- * \param ilen length of the input data
- */
-void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input,
- size_t ilen );
-
-/**
- * \brief SHA-256 final digest
- *
- * \param ctx SHA-256 context
- * \param output SHA-224/256 checksum result
- */
-void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, unsigned char output[32] );
-
-/* Internal use */
-void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA256_ALT */
-#endif /* MBEDTLS_SHA1_C */
-
-#endif /* sha256_alt.h */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,308 +0,0 @@
-/*
- * FIPS-180-2 compliant SHA-256 implementation
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- * The SHA-256 Secure Hash Standard was published by NIST in 2002.
- *
- * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include "mbedtls/sha256.h"
-
-#include <string.h>
-
-/* Implementation that should never be optimized out by the compiler */
-static void mbedtls_zeroize( void *v, size_t n ) {
- volatile unsigned char *p = v; while( n-- ) *p++ = 0;
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i) \
-do { \
- (n) = ( (uint32_t) (b)[(i) ] << 24 ) \
- | ( (uint32_t) (b)[(i) + 1] << 16 ) \
- | ( (uint32_t) (b)[(i) + 2] << 8 ) \
- | ( (uint32_t) (b)[(i) + 3] ); \
-} while( 0 )
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i) \
-do { \
- (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \
- (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \
- (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \
- (b)[(i) + 3] = (unsigned char) ( (n) ); \
-} while( 0 )
-#endif
-
-void mbedtls_sha256_sw_init( mbedtls_sha256_sw_context *ctx )
-{
- memset( ctx, 0, sizeof( mbedtls_sha256_sw_context ) );
-}
-
-void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx )
-{
- if( ctx == NULL )
- return;
-
- mbedtls_zeroize( ctx, sizeof( mbedtls_sha256_sw_context ) );
-}
-
-void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst,
- const mbedtls_sha256_sw_context *src )
-{
- *dst = *src;
-}
-
-/*
- * SHA-256 context setup
- */
-void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 )
-{
- ctx->total[0] = 0;
- ctx->total[1] = 0;
-
- if( is224 == 0 )
- {
- /* SHA-256 */
- ctx->state[0] = 0x6A09E667;
- ctx->state[1] = 0xBB67AE85;
- ctx->state[2] = 0x3C6EF372;
- ctx->state[3] = 0xA54FF53A;
- ctx->state[4] = 0x510E527F;
- ctx->state[5] = 0x9B05688C;
- ctx->state[6] = 0x1F83D9AB;
- ctx->state[7] = 0x5BE0CD19;
- }
- else
- {
- /* SHA-224 */
- ctx->state[0] = 0xC1059ED8;
- ctx->state[1] = 0x367CD507;
- ctx->state[2] = 0x3070DD17;
- ctx->state[3] = 0xF70E5939;
- ctx->state[4] = 0xFFC00B31;
- ctx->state[5] = 0x68581511;
- ctx->state[6] = 0x64F98FA7;
- ctx->state[7] = 0xBEFA4FA4;
- }
-
- ctx->is224 = is224;
-}
-
-static const uint32_t K[] =
-{
- 0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5,
- 0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5,
- 0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3,
- 0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174,
- 0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC,
- 0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA,
- 0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7,
- 0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967,
- 0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13,
- 0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85,
- 0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3,
- 0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070,
- 0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5,
- 0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3,
- 0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208,
- 0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2,
-};
-
-#define SHR(x,n) ((x & 0xFFFFFFFF) >> n)
-#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
-
-#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3))
-#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10))
-
-#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
-#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
-
-#define F0(x,y,z) ((x & y) | (z & (x | y)))
-#define F1(x,y,z) (z ^ (x & (y ^ z)))
-
-#define R(t) \
-( \
- W[t] = S1(W[t - 2]) + W[t - 7] + \
- S0(W[t - 15]) + W[t - 16] \
-)
-
-#define P(a,b,c,d,e,f,g,h,x,K) \
-{ \
- temp1 = h + S3(e) + F1(e,f,g) + K + x; \
- temp2 = S2(a) + F0(a,b,c); \
- d += temp1; h = temp1 + temp2; \
-}
-
-void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned char data[64] )
-{
- uint32_t temp1, temp2, W[64];
- uint32_t A[8];
- unsigned int i;
-
- for( i = 0; i < 8; i++ )
- A[i] = ctx->state[i];
-
-#if defined(MBEDTLS_SHA256_SMALLER)
- for( i = 0; i < 64; i++ )
- {
- if( i < 16 )
- GET_UINT32_BE( W[i], data, 4 * i );
- else
- R( i );
-
- P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] );
-
- temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3];
- A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1;
- }
-#else /* MBEDTLS_SHA256_SMALLER */
- for( i = 0; i < 16; i++ )
- GET_UINT32_BE( W[i], data, 4 * i );
-
- for( i = 0; i < 16; i += 8 )
- {
- P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] );
- P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] );
- P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] );
- P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i+3], K[i+3] );
- P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i+4], K[i+4] );
- P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i+5], K[i+5] );
- P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i+6], K[i+6] );
- P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] );
- }
-
- for( i = 16; i < 64; i += 8 )
- {
- P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] );
- P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] );
- P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] );
- P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i+3), K[i+3] );
- P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i+4), K[i+4] );
- P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i+5), K[i+5] );
- P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i+6), K[i+6] );
- P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i+7), K[i+7] );
- }
-#endif /* MBEDTLS_SHA256_SMALLER */
-
- for( i = 0; i < 8; i++ )
- ctx->state[i] += A[i];
-}
-
-/*
- * SHA-256 process buffer
- */
-void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input,
- size_t ilen )
-{
- size_t fill;
- uint32_t left;
-
- if( ilen == 0 )
- return;
-
- left = ctx->total[0] & 0x3F;
- fill = 64 - left;
-
- ctx->total[0] += (uint32_t) ilen;
- ctx->total[0] &= 0xFFFFFFFF;
-
- if( ctx->total[0] < (uint32_t) ilen )
- ctx->total[1]++;
-
- if( left && ilen >= fill )
- {
- memcpy( (void *) (ctx->buffer + left), input, fill );
- mbedtls_sha256_sw_process( ctx, ctx->buffer );
- input += fill;
- ilen -= fill;
- left = 0;
- }
-
- while( ilen >= 64 )
- {
- mbedtls_sha256_sw_process( ctx, input );
- input += 64;
- ilen -= 64;
- }
-
- if( ilen > 0 )
- memcpy( (void *) (ctx->buffer + left), input, ilen );
-}
-
-static const unsigned char sha256_padding[64] =
-{
- 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * SHA-256 final digest
- */
-void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char output[32] )
-{
- uint32_t last, padn;
- uint32_t high, low;
- unsigned char msglen[8];
-
- high = ( ctx->total[0] >> 29 )
- | ( ctx->total[1] << 3 );
- low = ( ctx->total[0] << 3 );
-
- PUT_UINT32_BE( high, msglen, 0 );
- PUT_UINT32_BE( low, msglen, 4 );
-
- last = ctx->total[0] & 0x3F;
- padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last );
-
- mbedtls_sha256_sw_update( ctx, sha256_padding, padn );
- mbedtls_sha256_sw_update( ctx, msglen, 8 );
-
- PUT_UINT32_BE( ctx->state[0], output, 0 );
- PUT_UINT32_BE( ctx->state[1], output, 4 );
- PUT_UINT32_BE( ctx->state[2], output, 8 );
- PUT_UINT32_BE( ctx->state[3], output, 12 );
- PUT_UINT32_BE( ctx->state[4], output, 16 );
- PUT_UINT32_BE( ctx->state[5], output, 20 );
- PUT_UINT32_BE( ctx->state[6], output, 24 );
-
- if( ctx->is224 == 0 )
- PUT_UINT32_BE( ctx->state[7], output, 28 );
-}
-
-#endif /* MBEDTLS_SHA1_ALT */
-
-#endif /* MBEDTLS_SHA256_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha256_alt_sw.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/**
- * \file sha256.h
- *
- * \brief SHA-224 and SHA-256 cryptographic hash function
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * This file is part of mbed TLS (https://tls.mbed.org)
- */
-#ifndef MBEDTLS_SHA256_ALT_SW_H
-#define MBEDTLS_SHA256_ALT_SW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief SHA-256 context structure
- */
-typedef struct
-{
- uint32_t total[2]; /*!< number of bytes processed */
- uint32_t state[8]; /*!< intermediate digest state */
- unsigned char buffer[64]; /*!< data block being processed */
- int is224; /*!< 0 => SHA-256, else SHA-224 */
-}
-mbedtls_sha256_sw_context;
-
-/**
- * \brief Initialize SHA-256 context
- *
- * \param ctx SHA-256 context to be initialized
- */
-void mbedtls_sha256_sw_init( mbedtls_sha256_sw_context *ctx );
-
-/**
- * \brief Clear SHA-256 context
- *
- * \param ctx SHA-256 context to be cleared
- */
-void mbedtls_sha256_sw_free( mbedtls_sha256_sw_context *ctx );
-
-/**
- * \brief Clone (the state of) a SHA-256 context
- *
- * \param dst The destination context
- * \param src The context to be cloned
- */
-void mbedtls_sha256_sw_clone( mbedtls_sha256_sw_context *dst,
- const mbedtls_sha256_sw_context *src );
-
-/**
- * \brief SHA-256 context setup
- *
- * \param ctx context to be initialized
- * \param is224 0 = use SHA256, 1 = use SHA224
- */
-void mbedtls_sha256_sw_starts( mbedtls_sha256_sw_context *ctx, int is224 );
-
-/**
- * \brief SHA-256 process buffer
- *
- * \param ctx SHA-256 context
- * \param input buffer holding the data
- * \param ilen length of the input data
- */
-void mbedtls_sha256_sw_update( mbedtls_sha256_sw_context *ctx, const unsigned char *input,
- size_t ilen );
-
-/**
- * \brief SHA-256 final digest
- *
- * \param ctx SHA-256 context
- * \param output SHA-224/256 checksum result
- */
-void mbedtls_sha256_sw_finish( mbedtls_sha256_sw_context *ctx, unsigned char output[32] );
-
-/* Internal use */
-void mbedtls_sha256_sw_process( mbedtls_sha256_sw_context *ctx, const unsigned char data[64] );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA256_ALT */
-#endif /* MBEDTLS_SHA256_C */
-
-#endif /* sha256_alt_sw.h */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,333 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "mbedtls/config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C)
-
-#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT)
-
-#if defined(MBEDTLS_SHA1_ALT)
-#include "sha1_alt.h"
-#endif /* MBEDTLS_SHA1_ALT */
-
-#if defined(MBEDTLS_SHA256_ALT)
-#include "sha256_alt.h"
-#endif /* MBEDTLS_SHA256_ALT */
-
-#if defined(MBEDTLS_SHA512_ALT)
-#include "sha512_alt.h"
-#endif /* MBEDTLS_SHA512_ALT */
-
-#include "nu_bitutil.h"
-#include "mbed_assert.h"
-#include "crypto-misc.h"
-
-#include <string.h>
-
-void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
-void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast);
-void crypto_sha_getinternstate(unsigned char output[], size_t olen);
-
-#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
-
-#if defined(MBEDTLS_SHA1_ALT)
-
-void mbedtls_sha1_hw_init(crypto_sha_context *ctx)
-{
- crypto_init();
- memset(ctx, 0, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha1_hw_free(crypto_sha_context *ctx)
-{
- if (ctx == NULL) {
- return;
- }
-
- crypto_zeroize(ctx, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha1_hw_clone(crypto_sha_context *dst,
- const crypto_sha_context *src)
-{
- *dst = *src;
-}
-
-void mbedtls_sha1_hw_starts(crypto_sha_context *ctx)
-{
- // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it.
- CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
-
- ctx->total = 0;
- ctx->buffer_left = 0;
- ctx->blocksize = 64;
- ctx->blocksize_mask = 0x3F;
-
- SHA_Open(SHA_MODE_SHA1, SHA_NO_SWAP);
-
- // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started.
- CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk;
-
- return;
-}
-
-void mbedtls_sha1_hw_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
-{
- crypto_sha_update(ctx, input, ilen);
-}
-
-void mbedtls_sha1_hw_finish(crypto_sha_context *ctx, unsigned char output[20])
-{
- // H/W SHA cannot handle zero data well. Fall back to S/W SHA.
- if (ctx->total) {
- crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1);
- ctx->buffer_left = 0;
- crypto_sha_getinternstate(output, 20);
-
- CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
- }
- else {
- mbedtls_sha1_sw_context ctx_sw;
-
- mbedtls_sha1_sw_init(&ctx_sw);
- mbedtls_sha1_sw_starts(&ctx_sw);
- mbedtls_sha1_sw_finish(&ctx_sw, output);
- mbedtls_sha1_sw_free(&ctx_sw);
- }
-}
-
-void mbedtls_sha1_hw_process(crypto_sha_context *ctx, const unsigned char data[64])
-{
- mbedtls_sha1_hw_update(ctx, data, 64);
-}
-
-#endif /* MBEDTLS_SHA1_ALT */
-
-#if defined(MBEDTLS_SHA256_ALT)
-
-void mbedtls_sha256_hw_init(crypto_sha_context *ctx)
-{
- crypto_init();
- memset(ctx, 0, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha256_hw_free(crypto_sha_context *ctx)
-{
- if (ctx == NULL) {
- return;
- }
-
- crypto_zeroize(ctx, sizeof(crypto_sha_context));
-}
-
-void mbedtls_sha256_hw_clone(crypto_sha_context *dst,
- const crypto_sha_context *src)
-{
- *dst = *src;
-}
-
-void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224)
-{
- // NOTE: mbedtls may call mbedtls_shaXXX_starts multiple times and then call the ending mbedtls_shaXXX_finish. Guard from it.
- CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
-
- ctx->total = 0;
- ctx->buffer_left = 0;
- ctx->blocksize = 64;
- ctx->blocksize_mask = 0x3F;
- ctx->is224 = is224;
-
- SHA_Open(is224 ? SHA_MODE_SHA224 : SHA_MODE_SHA256, SHA_NO_SWAP);
-
- // Ensure we have correct initial inernal states in SHA_DGST registers even though SHA H/W is not actually started.
- CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk;
-
- return;
-}
-
-void mbedtls_sha256_hw_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
-{
- crypto_sha_update(ctx, input, ilen);
-}
-
-void mbedtls_sha256_hw_finish(crypto_sha_context *ctx, unsigned char output[32])
-{
- // H/W SHA cannot handle zero data well. Fall back to S/W SHA.
- if (ctx->total) {
- crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 1);
- ctx->buffer_left = 0;
- crypto_sha_getinternstate(output, ctx->is224 ? 28 : 32);
-
- CRPT->SHA_CTL |= CRPT_SHA_CTL_STOP_Msk;
- }
- else {
- mbedtls_sha256_sw_context ctx_sw;
-
- mbedtls_sha256_sw_init(&ctx_sw);
- mbedtls_sha256_sw_starts(&ctx_sw, ctx->is224);
- mbedtls_sha256_sw_finish(&ctx_sw, output);
- mbedtls_sha256_sw_free(&ctx_sw);
- }
-}
-
-void mbedtls_sha256_hw_process(crypto_sha_context *ctx, const unsigned char data[64])
-{
- mbedtls_sha256_hw_update(ctx, data, 64);
-}
-
-#endif /* MBEDTLS_SHA256_ALT */
-
-#if defined(MBEDTLS_SHA1_ALT) || defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA512_ALT)
-
-void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen)
-{
- if (ilen == 0) {
- return;
- }
-
- size_t fill = ctx->blocksize - ctx->buffer_left;
-
- ctx->total += (uint32_t) ilen;
-
- if (ctx->buffer_left && ilen >= fill) {
- memcpy((void *) (ctx->buffer + ctx->buffer_left), input, fill);
- input += fill;
- ilen -= fill;
- ctx->buffer_left += fill;
- if (ilen) {
- crypto_sha_update_nobuf(ctx, ctx->buffer, ctx->buffer_left, 0);
- ctx->buffer_left = 0;
- }
- }
-
- while (ilen > ctx->blocksize) {
- crypto_sha_update_nobuf(ctx, input, ctx->blocksize, 0);
- input += ctx->blocksize;
- ilen -= ctx->blocksize;
- }
-
- if (ilen > 0) {
- memcpy((void *) (ctx->buffer + ctx->buffer_left), input, ilen);
- ctx->buffer_left += ilen;
- }
-}
-
-void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast)
-{
- // Accept only:
- // 1. Last block which may be incomplete
- // 2. Non-last block which is complete
- MBED_ASSERT(islast || ilen == ctx->blocksize);
-
- const unsigned char *in_pos = input;
- int rmn = ilen;
- uint32_t sha_ctl_start = (CRPT->SHA_CTL & ~(CRPT_SHA_CTL_DMALAST_Msk | CRPT_SHA_CTL_DMAEN_Msk)) | CRPT_SHA_CTL_START_Msk;
- uint32_t sha_opmode = (CRPT->SHA_CTL & CRPT_SHA_CTL_OPMODE_Msk) >> CRPT_SHA_CTL_OPMODE_Pos;
- uint32_t DGST0_old, DGST1_old, DGST2_old, DGST3_old, DGST4_old, DGST5_old, DGST6_old, DGST7_old;
-
- while (rmn > 0) {
- CRPT->SHA_CTL = sha_ctl_start;
-
- uint32_t data = nu_get32_be(in_pos);
- if (rmn <= 4) { // Last word of a (in)complete block
- if (islast) {
- uint32_t lastblock_size = ctx->total & ctx->blocksize_mask;
- if (lastblock_size == 0) {
- lastblock_size = ctx->blocksize;
- }
- CRPT->SHA_DMACNT = lastblock_size;
- CRPT->SHA_CTL = sha_ctl_start | CRPT_SHA_CTL_DMALAST_Msk;
- }
- else {
- switch (sha_opmode) {
- case SHA_MODE_SHA256:
- DGST7_old = CRPT->SHA_DGST7;
- case SHA_MODE_SHA224:
- DGST5_old = CRPT->SHA_DGST5;
- DGST6_old = CRPT->SHA_DGST6;
- case SHA_MODE_SHA1:
- DGST0_old = CRPT->SHA_DGST0;
- DGST1_old = CRPT->SHA_DGST1;
- DGST2_old = CRPT->SHA_DGST2;
- DGST3_old = CRPT->SHA_DGST3;
- DGST4_old = CRPT->SHA_DGST4;
- }
-
- CRPT->SHA_CTL = sha_ctl_start;
- }
- }
- else { // Non-last word of a complete block
- CRPT->SHA_CTL = sha_ctl_start;
- }
- while (! (CRPT->SHA_STS & CRPT_SHA_STS_DATINREQ_Msk));
- CRPT->SHA_DATIN = data;
-
- in_pos += 4;
- rmn -= 4;
- }
-
- if (islast) { // Finish of last block
- while (CRPT->SHA_STS & CRPT_SHA_STS_BUSY_Msk);
- }
- else { // Finish of non-last block
- // No H/W flag to indicate finish of non-last block process.
- // Values of SHA_DGSTx registers will change as last word of the block is input, so use it for judgement.
- int isfinish = 0;
- while (! isfinish) {
- switch (sha_opmode) {
- case SHA_MODE_SHA256:
- if (DGST7_old != CRPT->SHA_DGST7) {
- isfinish = 1;
- break;
- }
- case SHA_MODE_SHA224:
- if (DGST5_old != CRPT->SHA_DGST5 || DGST6_old != CRPT->SHA_DGST6) {
- isfinish = 1;
- break;
- }
- case SHA_MODE_SHA1:
- if (DGST0_old != CRPT->SHA_DGST0 || DGST1_old != CRPT->SHA_DGST1 || DGST2_old != CRPT->SHA_DGST2 ||
- DGST3_old != CRPT->SHA_DGST3 || DGST4_old != CRPT->SHA_DGST4) {
- isfinish = 1;
- break;
- }
- }
- }
- }
-}
-
-void crypto_sha_getinternstate(unsigned char output[], size_t olen)
-{
- uint32_t *in_pos = (uint32_t *) &CRPT->SHA_DGST0;
- unsigned char *out_pos = output;
- uint32_t rmn = olen;
-
- while (rmn) {
- uint32_t val = *in_pos ++;
- nu_set32_be(out_pos, val);
- out_pos += 4;
- rmn -= 4;
- }
-}
-
-#endif /* MBEDTLS_SHA1_ALT || MBEDTLS_SHA256_ALT || MBEDTLS_SHA512_ALT */
-
-#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/sha/sha_alt_hw.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBEDTLS_SHA_ALT_HW_H
-#define MBEDTLS_SHA_ALT_HW_H
-
-#if !defined(MBEDTLS_CONFIG_FILE)
-#include "config.h"
-#else
-#include MBEDTLS_CONFIG_FILE
-#endif
-
-#if defined(MBEDTLS_SHA1_C) || defined(MBEDTLS_SHA256_C) || defined(MBEDTLS_SHA512_C)
-
-#include <stddef.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief SHA context structure
- */
-typedef struct
-{
- uint32_t total; /*!< number of bytes processed */
- unsigned char buffer[128]; /*!< data block being processed. Max of SHA-1/SHA-256/SHA-512 */
- uint16_t buffer_left;
- uint16_t blocksize; /*!< block size */
- uint32_t blocksize_mask; /*!< block size mask */
-
- int is224; /*!< 0 => SHA-256, else SHA-224 */
-}
-crypto_sha_context;
-
-void crypto_sha_update(crypto_sha_context *ctx, const unsigned char *input, size_t ilen);
-void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input, size_t ilen, int islast);
-void crypto_sha_getinternstate(unsigned char output[], size_t olen);
-
-#if defined(MBEDTLS_SHA1_ALT)
-
-void mbedtls_sha1_hw_init( crypto_sha_context *ctx );
-void mbedtls_sha1_hw_free( crypto_sha_context *ctx );
-void mbedtls_sha1_hw_clone( crypto_sha_context *dst,
- const crypto_sha_context *src );
-void mbedtls_sha1_hw_starts( crypto_sha_context *ctx );
-void mbedtls_sha1_hw_update( crypto_sha_context *ctx, const unsigned char *input, size_t ilen );
-void mbedtls_sha1_hw_finish( crypto_sha_context *ctx, unsigned char output[20] );
-void mbedtls_sha1_hw_process( crypto_sha_context *ctx, const unsigned char data[64] );
-
-#endif /* MBEDTLS_SHA1_ALT */
-
-#if defined(MBEDTLS_SHA256_ALT)
-
-void mbedtls_sha256_hw_init( crypto_sha_context *ctx );
-void mbedtls_sha256_hw_free( crypto_sha_context *ctx );
-void mbedtls_sha256_hw_clone( crypto_sha_context *dst,
- const crypto_sha_context *src );
-void mbedtls_sha256_hw_starts( crypto_sha_context *ctx, int is224 );
-void mbedtls_sha256_hw_update( crypto_sha_context *ctx, const unsigned char *input,
- size_t ilen );
-void mbedtls_sha256_hw_finish( crypto_sha_context *ctx, unsigned char output[32] );
-void mbedtls_sha256_hw_process( crypto_sha_context *ctx, const unsigned char data[64] );
-
-#endif /* MBEDTLS_SHA256_ALT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBEDTLS_SHA1_C || MBEDTLS_SHA256_C || MBEDTLS_SHA512_C*/
-
-#endif /* sha_alt.h */
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32606 +0,0 @@
-/**************************************************************************//**
- * @file NUC472_442.h
- * @version V1.00
- * $Revision: 156 $
- * $Date: 14/10/08 9:26a $
- * @brief NUC472/NUC442 peripheral access layer header file.
- * This file contains all the peripheral register's definitions,
- * bits definitions and memory mapping for NuMicro NUC472/NUC442 MCU.
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-/**
- \mainpage NuMicro NUC472/NUC442 MCU Driver Reference Guide
- *
- * <b>Introduction</b>
- *
- * This user manual describes the usage of NUC472/NUC442 MCU device driver
- *
- * <b>Disclaimer</b>
- *
- * The Software is furnished "AS IS", without warranty as to performance or results, and
- * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
- * warranties, express, implied or otherwise, with regard to the Software, its use, or
- * operation, including without limitation any and all warranties of merchantability, fitness
- * for a particular purpose, and non-infringement of intellectual property rights.
- *
- * <b>Important Notice</b>
- *
- * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
- * any malfunction or failure of which may cause loss of human life, bodily injury or severe
- * property damage. Such applications are deemed, "Insecure Usage".
- *
- * Insecure usage includes, but is not limited to: equipment for surgical implementation,
- * atomic energy control instruments, airplane or spaceship instruments, the control or
- * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
- * instruments, all types of safety devices, and other applications intended to support or
- * sustain life.
- *
- * All Insecure Usage shall be made at customer's risk, and in the event that third parties
- * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
- * the damages and liabilities thus incurred by Nuvoton.
- *
- * Please note that all data and specifications are subject to change without notice. All the
- * trademarks of products and companies mentioned in this document belong to their respective
- * owners.
- *
- * <b>Copyright Notice</b>
- *
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- */
-/**
- * \page pg1 NuMicro NUC472/NUC442 BSP Directory Structure
- * Please refer to Readme.pdf under BSP root directory for the BSP directory structure
- *
- * \page pg2 Revision History
- *
- * <b>Revision 3.01.001</b>
- * \li Removed NVIC_EnableIRQ() function call in I2S_Open() and SD_Open().
- * \li Removed PI definition and add GPI definition.
- * \li Removed uCOS-II and uCOS-III samples.
- * \li Renamed CAN_NOTMAL_MODE to CAN_NORMAL_MODE.
- * \li Renamed UBSD_*() macros to USBD_*().
- * \li Renamed USBH registers and related bit name.
- * \li Renamed PD13MFP_SC3_SS0 to PD13MFP_SPI1_SS0.
- * \li Replaced the USBH_ProcessHubEvents() and usb_hub_events() return type from void to int.
- * \li Updated original USBH HID library with Nuvoton HID library with less footprint.
- * \li Updated bit filed definition of register VREFCTL.
- * \li Enable branch buffer starting from version E MCU.
- * \li Added RTX support.
- * \li Added EADC driver.
- * \li Added Cortex-M4 BitBand and MPU sample codes.
- * \li Added ADC_PDMA, EADC_ADINT_Trigger, EADC_Compare, EADC_STADC_Trigger, EADC_SWTRG_Trigger, EADC_Timer_Trigger, I2S_NAU8822_PDMA, ISP_Updater,
- * USBD_Bulk, USBD_HID_Mouse_Vendor, USBD_HID_MouseKeyboard, USBD_HID_Transfer, USBD_VCOM_SerialEmulator, USBD_VENDOR_LBK, USBH_VENDOR_LBK samples.
- *
- * <b>Revision 3.01.000</b>
- * \li Rename registers and bit fields.
- * \li Added Analog comparator (ACMP) driver
- * \li Added I2S, ACMP ,and USBD sample codes
- * \li Minor bug fix.
- *
- * <b>Revision 3.00.001</b>
- * \li Improved PWM driver performance.
- * \li Renamed EPWM register PWM0/2/4 to PWM_CH0/2/4.
- * \li Updated IAR project files to support Nu-Link IAR driver v6287 or above.
- * \li Removed learning board sample code directory NUC472-LB.
- * \li Added wave player and hard fault sample.
- * \li Minor bug fix.
- *
- * <b>Revision 3.00.000</b>
- * \li Moved Smartcard library one directory level up to "Library\SmartcardLib\".
- * \li Added OTG dual role sample code and Learning Board G-sensor sample code.
- * \li Added FreeRTOS LwIP IAR project file.
- * \li Renamed RTC_GetDatAndTime() to RTC_GetDateAndTime().
- * \li Changed Major number from 1 to 3.
- * \li Minor bug fix.
- *
- * <b>Revision 1.00.000</b>
- * \li Added CAN, SD, SC, SCUART driver and samples.
- * \li Added smartcard 7816-3 library.
- * \li Added NUC472 Tiny Board sample.
- * \li Renamed I2C_GetClockBusFreq() to I2C_GetBusClockFreq().
- * \li Renamed I2C_SetClockBusFreq() to I2C_SetBusClockFreq().
- * \li Renamed I2C_SetSlaveMask() to I2C_SetSlaveAddrMask().
- * \li Minor bug fix.
- *
- * <b>Revision 0.10.000</b>
- * \li Added I2S, PDMA driver.
- * \li Added Learning Board and Standard Driver samples.
- * \li Added FreeRTOS lwIP sample.
- *
- * <b>Revision 0.09.000</b>
- * \li Added CAP, EBI, I2C, PWM, SPI, USBD, USBH drivers and samples.
- * \li Added uCOS-II and uCOS-III samples.
- * \li Added FreeRTOS source code and sample.
- *
- * <b>Revision 0.08.000</b>
- * \li Preliminary release.
-*/
-#ifndef __NUC472_442_H__
-#define __NUC472_442_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/******************************************************************************/
-/* Processor and Core Peripherals */
-/******************************************************************************/
-/** @addtogroup NUC472_442_CMSIS NUC472/NUC442 Device CMSIS Definitions
- Configuration of the Cortex-M4 Processor and Core Peripherals
- @{
-*/
-
-/**
- * @details Interrupt Number Definition.
- */
-typedef enum IRQn {
- /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
-
- /****** NUC472/NUC442 Specific Interrupt Numbers ********************************************************/
-
- BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
- IRC_IRQn = 1, /*!< Internal RC Interrupt */
- PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
- SRAMF_IRQn = 3, /*!< SRAM Parity Check Failed Interrupt */
- CLKF_IRQn = 4, /*!< Clock Detection Failed Interrupt */
- RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
- TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
- EINT0_IRQn = 8, /*!< External Input 0 Interrupt */
- EINT1_IRQn = 9, /*!< External Input 1 Interrupt */
- EINT2_IRQn = 10, /*!< External Input 2 Interrupt */
- EINT3_IRQn = 11, /*!< External Input 3 Interrupt */
- EINT4_IRQn = 12, /*!< External Input 4 Interrupt */
- EINT5_IRQn = 13, /*!< External Input 5 Interrupt */
- EINT6_IRQn = 14, /*!< External Input 6 Interrupt */
- EINT7_IRQn = 15, /*!< External Input 7 Interrupt */
- GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
- GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
- GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
- GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
- GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
- GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
- GPG_IRQn = 22, /*!< GPIO Port G Interrupt */
- GPH_IRQn = 23, /*!< GPIO Port H Interrupt */
- GPI_IRQn = 24, /*!< GPIO Port I Interrupt */
- TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
- TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
- TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
- TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
- PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
- ADC_IRQn = 42, /*!< ADC Interrupt */
- WDT_IRQn = 46, /*!< Watch Dog Timer Interrupt */
- WWDT_IRQn = 47, /*!< Window Watch Dog Timer Interrupt */
- EADC0_IRQn = 48, /*!< Enhanced ADC 0 Interrupt */
- EADC1_IRQn = 49, /*!< Enhanced ADC 1 Interrupt */
- EADC2_IRQn = 50, /*!< Enhanced ADC 2 Interrupt */
- EADC3_IRQn = 51, /*!< Enhanced ADC 3 Interrupt */
- ACMP_IRQn = 56, /*!< Analog Comparator Interrupt */
- OPA0_IRQn = 60, /*!< OPA 0 Interrupt */
- OPA1_IRQn = 61, /*!< OPA 1 Interrupt */
- ICAP0_IRQn = 62, /*!< Input Capture 0 Interrupt */
- ICAP1_IRQn = 63, /*!< Input Capture 1 Interrupt */
- PWM0CH0_IRQn = 64, /*!< PWM 0 Channel 0 Interrupt */
- PWM0CH1_IRQn = 65, /*!< PWM 0 Channel 1 Interrupt */
- PWM0CH2_IRQn = 66, /*!< PWM 0 Channel 2 Interrupt */
- PWM0CH3_IRQn = 67, /*!< PWM 0 Channel 3 Interrupt */
- PWM0CH4_IRQn = 68, /*!< PWM 0 Channel 4 Interrupt */
- PWM0CH5_IRQn = 69, /*!< PWM 0 Channel 5 Interrupt */
- PWM0_BRK_IRQn = 70, /*!< PWM 0 Break Interrupt */
- QEI0_IRQn = 71, /*!< QEI 0 Interrupt */
- PWM1CH0_IRQn = 72, /*!< PWM 1 Channel 0 Interrupt */
- PWM1CH1_IRQn = 73, /*!< PWM 1 Channel 1 Interrupt */
- PWM1CH2_IRQn = 74, /*!< PWM 1 Channel 2 Interrupt */
- PWM1CH3_IRQn = 75, /*!< PWM 1 Channel 3 Interrupt */
- PWM1CH4_IRQn = 76, /*!< PWM 1 Channel 4 Interrupt */
- PWM1CH5_IRQn = 77, /*!< PWM 1 Channel 5 Interrupt */
- PWM1_BRK_IRQn = 78, /*!< PWM 1 Break Interrupt */
- QEI1_IRQn = 79, /*!< QEI 1 Interrupt */
- EPWM0_IRQn = 80, /*!< Enhanced PWM 0 Interrupt */
- EPWM0BRK_IRQn = 81, /*!< Enhanced PWM 0 Break Interrupt */
- EPWM1_IRQn = 82, /*!< Enhanced PWM 1 Interrupt */
- EPWM1BRK_IRQn = 83, /*!< Enhanced PWM 1 Break Interrupt */
- USBD_IRQn = 88, /*!< USB FS Device Interrupt */
- USBH_IRQn = 89, /*!< USB FS Host Interrupt */
- USB_OTG_IRQn = 90, /*!< USB OTG Interrupt */
- EMAC_TX_IRQn = 92, /*!< Ethernet MAC TX Interrupt */
- EMAC_RX_IRQn = 93, /*!< Ethernet MAC RX Interrupt */
- SPI0_IRQn = 96, /*!< SPI 0 Interrupt */
- SPI1_IRQn = 97, /*!< SPI 1 Interrupt */
- SPI2_IRQn = 98, /*!< SPI 2 Interrupt */
- SPI3_IRQn = 99, /*!< SPI 3 Interrupt */
- UART0_IRQn = 104, /*!< UART 0 Interrupt */
- UART1_IRQn = 105, /*!< UART 1 Interrupt */
- UART2_IRQn = 106, /*!< UART 2 Interrupt */
- UART3_IRQn = 107, /*!< UART 3 Interrupt */
- UART4_IRQn = 108, /*!< UART 4 Interrupt */
- UART5_IRQn = 109, /*!< UART 5 Interrupt */
- I2C0_IRQn = 112, /*!< I2C 0 Interrupt */
- I2C1_IRQn = 113, /*!< I2C 1 Interrupt */
- I2C2_IRQn = 114, /*!< I2C 2 Interrupt */
- I2C3_IRQn = 115, /*!< I2C 3 Interrupt */
- I2C4_IRQn = 116, /*!< I2C 4 Interrupt */
- SC0_IRQn = 120, /*!< Smart Card 0 Interrupt */
- SC1_IRQn = 121, /*!< Smart Card 1 Interrupt */
- SC2_IRQn = 122, /*!< Smart Card 2 Interrupt */
- SC3_IRQn = 123, /*!< Smart Card 3 Interrupt */
- SC4_IRQn = 124, /*!< Smart Card 4 Interrupt */
- SC5_IRQn = 125, /*!< Smart Card 5 Interrupt */
- CAN0_IRQn = 128, /*!< CAN 0 Interrupt */
- CAN1_IRQn = 129, /*!< CAN 1 Interrupt */
- I2S0_IRQn = 132, /*!< I2S 0 Interrupt */
- I2S1_IRQn = 133, /*!< I2S 1 Interrupt */
- SD_IRQn = 136, /*!< SD Host Interrupt */
- PS2D_IRQn = 138, /*!< PS/2 device Interrupt */
- CAP_IRQn = 139, /*!< VCAP Interrupt */
- CRPT_IRQn = 140, /*!< Cryptographic Accelerator Interrupt */
- CRC_IRQn = 141, /*!< CRC Interrupt */
-}
-IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M# Processor and Core Peripherals */
-#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
-#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-
-/*@}*/ /* end of group NUC472_442_CMSIS */
-
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_NUC472_442.h" /* NUC472/NUC442 System include file */
-#include <stdint.h>
-
-/******************************************************************************/
-/* Device Specific Peripheral registers structures */
-/******************************************************************************/
-/** @addtogroup NUC472_442_Peripherals NUC472/NUC442 Control Register
- NUC472/NUC442 Device Specific Peripheral registers structures
- @{
-*/
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-
-/*---------------------- Analog Comparator Controller -------------------------*/
-/**
- @addtogroup ACMP Analog Comparator Controller(ACMP)
- Memory Mapped Structure for ACMP Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL0, CTL1, CTL2
- * ===================================================================================================
- * Offset: 0x00~0x08 Analog Comparator 0/1/2 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ACMPEN |Comparator 0 Enable Control
- * | | |0 = Comparator 0 Disabled.
- * | | |1 = Comparator 0 Enabled.
- * | | |Note: The comparator output needs to wait 2 us stable time after ACMPEN is set.
- * |[1] |ACMPIE |Comparator 0 Interrupt Enable Control
- * | | |0 = Comparator 0 interrupt Disabled.
- * | | |1 = Comparator 0 interrupt Enabled.
- * |[2] |HYSEN |Comparator 0 Hysteresis Enable Control
- * | | |0 = Comparator 0 hysteresis Disabled (Default).
- * | | |1 = Comparator 0 hysteresis Enabled (typical range is 20 mV).
- * |[3] |ACMPOINV |Comparator 0 Output Inverse
- * | | |0 = Comparator 0 output inverse Disabled.
- * | | |1 = Comparator 0 output inverse Enabled.
- * |[4] |NEGSEL |Comparator 0 Negative Input Selection
- * | | |0 = The source of comparator 0 negative input is from ACMP0_N pin.
- * | | |1 = The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 0 negative input.
- * |[5:7] |POSSEL |Comparator 0 Positive Input Selection
- * | | |000= Input from ACMP0_P0.
- * | | |001= Input from ACMP0_P1.
- * | | |010= Input from ACMP0_P2.
- * | | |011= Input from ACMP0_P3.
- * | | |100= Input from OPA0.
- * | | |The other options are reserved.
- */
- __IO uint32_t CTL[3];
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x0C Analog Comparator Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ACMPIF0 |Comparator 0 Flag
- * | | |This bit is set by hardware whenever the comparator 0 output changes state.
- * | | |This will cause an interrupt if ACMP_CTL0[1] is set to 1.
- * | | |Write 1 to clear this bit to 0.
- * |[1] |ACMPIF1 |Comparator 1 Flag
- * | | |This bit is set by hardware whenever the comparator 1 output changes state.
- * | | |This will cause an interrupt if ACMP_CTL1[1] is set to 1.
- * | | |Write 1 to clear this bit to 0.
- * |[2] |ACMPIF2 |Comparator 2 Flag
- * | | |This bit is set by hardware whenever the comparator 2 output changes state.
- * | | |This will cause an interrupt if ACMP_CTL2[1] is set to 1.
- * | | |Write 1 to clear this bit to 0.
- * |[3] |ACMPO0 |Comparator 0 Output
- * | | |Synchronized to the APB clock to allow reading by software.
- * | | |Cleared when the comparator 0 is disabled (ACMP_CTL0[0] = 0).
- * |[4] |ACMPO1 |Comparator 1 Output
- * | | |Synchronized to the APB clock to allow reading by software.
- * | | |Cleared when the comparator 1 is disabled (ACMP_CTL1[0] = 0).
- * |[5] |ACMPO2 |Comparator 2 Output
- * | | |Synchronized to the APB clock to allow reading by software.
- * | | |Cleared when the comparator 2 is disabled (ACMP_CTL2[0] = 0).
- */
- __IO uint32_t STATUS;
-
- /**
- * VREF
- * ===================================================================================================
- * Offset: 0x10 Analog Comparator Reference Voltage Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CRVCTL |Comparator Reference Voltage Setting
- * | | |CRV = CRV source voltage * (1/6+VREF[3:0]/24).
- * |[6] |CRVSSEL |CRV Source Voltage Selection
- * | | |0 = VDDA is selected as CRV source voltage.
- * | | |1 = Internal reference voltage is selected as CRV source voltage.
- * |[7] |IREFSEL |Internal Reference Selection
- * | | |0 = Band-gap voltage is selected as internal reference.
- * | | |1 = CRV is selected as internal reference.
- */
- __IO uint32_t VREF;
-
-} ACMP_T;
-
-/**
- @addtogroup ACMP_CONST ACMP Bit Field Definition
- Constant Definitions for ACMP Controller
-@{ */
-
-#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP CTL: ACMPEN Position */
-#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP CTL: ACMPEN Mask */
-
-#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP CTL: ACMPIE Position */
-#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP CTL: ACMPIE Mask */
-
-#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP CTL: HYSEN Position */
-#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP CTL: HYSEN Mask */
-
-#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP CTL: ACMPOINV Position */
-#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP CTL: ACMPOINV Mask */
-
-#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP CTL: NEGSEL Position */
-#define ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP CTL: NEGSEL Mask */
-
-#define ACMP_CTL_POSSEL_Pos (5) /*!< ACMP CTL: POSSEL Position */
-#define ACMP_CTL_POSSEL_Msk (0x7ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP CTL: POSSEL Mask */
-
-#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP STATUS: ACMPIF0 Position */
-#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP STATUS: ACMPIF0 Mask */
-
-#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP STATUS: ACMPIF1 Position */
-#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP STATUS: ACMPIF1 Mask */
-
-#define ACMP_STATUS_ACMPIF2_Pos (2) /*!< ACMP STATUS: ACMPIF2 Position */
-#define ACMP_STATUS_ACMPIF2_Msk (0x1ul << ACMP_STATUS_ACMPIF2_Pos) /*!< ACMP STATUS: ACMPIF2 Mask */
-
-#define ACMP_STATUS_ACMPO0_Pos (3) /*!< ACMP STATUS: ACMPO0 Position */
-#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP STATUS: ACMPO0 Mask */
-
-#define ACMP_STATUS_ACMPO1_Pos (4) /*!< ACMP STATUS: ACMPO1 Position */
-#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP STATUS: ACMPO1 Mask */
-
-#define ACMP_STATUS_ACMPO2_Pos (5) /*!< ACMP STATUS: ACMPO2 Position */
-#define ACMP_STATUS_ACMPO2_Msk (0x1ul << ACMP_STATUS_ACMPO2_Pos) /*!< ACMP STATUS: ACMPO2 Mask */
-
-#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP VREF: CRVCTL Position */
-#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP VREF: CRVCTL Mask */
-
-#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP VREF: CRVSSEL Position */
-#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP VREF: CRVSSEL Mask */
-
-#define ACMP_VREF_IREFSEL_Pos (7) /*!< ACMP VREF: IREFSEL Position */
-#define ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos) /*!< ACMP VREF: IREFSEL Mask */
-
-/**@}*/ /* ACMP_CONST */
-/**@}*/ /* end of ACMP register group */
-
-
-/*---------------------- Analog to Digital Converter -------------------------*/
-/**
- @addtogroup ADC Analog to Digital Converter(ADC)
- Memory Mapped Structure for ADC Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * DAT
- * ===================================================================================================
- * Offset: 0x00~0x34 ADC Data Register 0~13
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RESULT |A/D Conversion Result
- * | | |This field contains conversion result of ADC.
- * | | |When DMOF (ADC_CTL[31]) bit is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
- * | | |When DMOF (ADC_CTL[31]) bit set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
- * |[16] |OV |Overrun Flag (Read Only)
- * | | |0 = Data in RESULT (ADC_DATx[15:0]) is recent conversion result.
- * | | |1 = Data in RESULT (ADC_DATx[15:0]) is overwrite.
- * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone.
- * | | |It is cleared by hardware after ADC_DAT register is read.
- * |[17] |VALID |Valid Flag (Read Only)
- * | | |0 = Data in RESULT (ADC_DATx[15:0]) bits is not valid.
- * | | |1 = Data in RESULT (ADC_DATx[15:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
- */
- __I uint32_t DAT[14];
-
-
- uint32_t RESERVE0[2];
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x40 ADC Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADCEN |ADC Enable Control
- * | | |0 = ADC analog circuit Disabled.
- * | | |1 = ADC analog circuit Enabled.
- * | | |Before disabling ADC clock, this bit should be cleared to 0 by software.
- * |[1] |ADCIEN |ADC Interrupt Enable Control
- * | | |0 = ADC interrupt function Disabled.
- * | | |1 = ADC interrupt function Enabled.
- * | | |A/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1.
- * |[2:3] |OPMODE |ADC Operation Mode
- * | | |00 = Single conversion.
- * | | |01 = Reserved.
- * | | |10 = Single-cycle scan.
- * | | |11 = Continuous scan.
- * | | |When changing the operation mode, software should disable SWTRG (ADC_CTL[11]) bit firstly.
- * |[4:5] |HWTRGSEL |External Hardware Trigger Source
- * | | |00 = A/D conversion is started by external pin (STADC).
- * | | |01 = Reserved.
- * | | |10 = Reserved.
- * | | |11 = PWM0 or PWM1 trigger condition is matched.
- * | | |Software should disable HWTRGCOND (ADC_CTL[8]) and SWTRG (ADC_CTL[11]) before changing HWTRGSEL (ADC_CTL[5:4]).
- * | | |In hardware trigger mode, the SWTRG (ADC_CTL[11]) bit is set by hardware trigger source.
- * |[6:7] |HWTRGCOND |External Pin Trigger Conditions
- * | | |These two bits decide external pin (STADC) trigger event.
- * | | |The signal must be kept at stable state at least 8 system clocks for level trigger and 4 system clocks at high and low state for edge trigger.
- * | | |00 = Low level.
- * | | |01 = High level.
- * | | |10 = Falling edge.
- * | | |11 = Rising edge.
- * |[8] |HWTRGEN |External Hardware Trigger Enable Control
- * | | |Enable or disable hardware triggering of A/D conversion.
- * | | |The hardware trigger source include external pin (STADC) or PWM trigger which is controlled by HWTRGSEL (ADC_CTL[5:4]) register.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |ADC hardware trigger function is only supported in single-cycle scan mode.
- * |[9] |PDMAEN |PDMA Transfer Enable Control
- * | | |0 = PDMA data transfer Disabled.
- * | | |1 = PDMA data transfer in ADC_DATx Enabled.
- * | | |When A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request.
- * | | |When PDMAEN (ADC_CTL[9]) is set to 1, software must set ADCIEN (ADC_CTL[1]) bit to 0 to disable interrupt.
- * |[10] |DIFFEN |Differential Input Mode Enable Control
- * | | |0 = Single-end analog input mode.
- * | | |1 = Differential analog input mode.
- * | | |The A/D analog input ADC0_CH0/ADC0_CH1 consists of a differential pair.
- * | | |So as ADC0_CH2/ADC0_CH3, ADC0_CH4/ADC0_CH5, ADC0_CH6/ADC0_CH7, ADC0_CH8/ADC0_CH9 and ADC0_CH10/ADC0_CH11.
- * | | |The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus).
- * | | |Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus
- * | | |is the analog input; Vminus is the inverted analog input.
- * | | |In differential input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER (ADC_CHEN[11:0]).
- * | | |The conversion result will be placed to the corresponding data register of the enabled channel.
- * |[11] |SWTRG |A/D Conversion Start
- * | | |0 = Conversion stopped and A/D converter enter idle state.
- * | | |1 = Conversion start.
- * | | |The SWTRG (ADC_CTL[11]) bit can be set to 1 from two sources: software and hardware trigger.
- * | | |The SWTRG (ADC_CTL[11]) bit will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode.
- * | | |In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
- * |[16:23] |PWMTRGDLY |PWM Trigger Delay Time
- * | | |Setting this field will delay ADC start conversion time after PWM trigger comes.
- * | | |PWM trigger delay time is 4 * system clock * PWMTRGDLY (ADC_CTL[23:16])
- * |[31] |DMOF |ADC Differential Input Mode Output Format
- * | | |0 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with unsigned format.
- * | | |1 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with 2'complement format.
- */
- __IO uint32_t CTL;
-
- /**
- * CHEN
- * ===================================================================================================
- * Offset: 0x44 ADC Channel Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |CHEN |Analog Input Channel Enable Control
- * | | |Set CHEN (ADC_CHEN[11:0]) to enable the corresponding analog input channel (ADC0_CH1 ~ ADC0_CH11).
- * | | |If DIFFEN bit is set to 1, only the even number channels need to be enabled.
- * | | |0 = ADC input channel Disabled.
- * | | |1 = ADC input channel Enabled.
- * |[16] |ADTSEN |Internal Temperature Sensor Selection
- * | | |0 = Internal temperature sensor is not selected to be the analog input source of ADC.
- * | | |1 = Internal temperature sensor is selected to be the analog input source of ADC.
- * | | |ADC can only work at Single mode when software selects the temperature sensor voltage as the analog input source of ADC
- * |[17] |ADBGEN |Internal Band-Gap Selection
- * | | |0 = Internal band-gap is not selected to be the analog input source of ADC.
- * | | |1 = Internal band-gap is selected to be the analog input source of ADC.
- * | | |ADC can only work at Single mode when software selects the band-gap voltage as the analog input source of ADC
- */
- __IO uint32_t CHEN;
-
- /**
- * CMP
- * ===================================================================================================
- * Offset: 0x48 ADC Compare Register 0/1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADCMPEN |Compare Enable Control
- * | | |0 = Compare function Disabled.
- * | | |1 = Compare function Enabled.
- * | | |Set this bit to 1 to enable ADC controller to compare CMPDAT (ADC_CMPx[27:16]) with the conversion result of the channel specified by CMPCH (ADC_CMPx[6:3]) when the conversion data of the specified channel is loaded into ADC_DATx register.
- * |[1] |ADCMPIE |Compare Interrupt Enable Control
- * | | |0 = Compare function interrupt Disabled.
- * | | |1 = Compare function interrupt Enabled.
- * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT(ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS0[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE (ADC_CMPx[1])is set to 1, a compare interrupt request is generated.
- * |[2] |CMPCOND |Compare Condition
- * | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one.
- * | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one.
- * | | |Note: When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
- * |[3:6] |CMPCH |Compare Channel Selection
- * | | |0000 = Channel 0 conversion result is selected to be compared.
- * | | |0001 = Channel 1 conversion result is selected to be compared.
- * | | |0010 = Channel 2 conversion result is selected to be compared.
- * | | |0011 = Channel 3 conversion result is selected to be compared.
- * | | |0100 = Channel 4 conversion result is selected to be compared.
- * | | |0101 = Channel 5 conversion result is selected to be compared.
- * | | |0110 = Channel 6 conversion result is selected to be compared.
- * | | |0111 = Channel 7 conversion result is selected to be compared.
- * | | |1000 = Channel 8 conversion result is selected to be compared.
- * | | |1001 = Channel 9 conversion result is selected to be compared.
- * | | |1010 = Channel 10 conversion result is selected to be compared.
- * | | |1011 = Channel 11 conversion result is selected to be compared.
- * | | |1100 = band-gap voltage result is selected to be compared.
- * | | |1101 = temperature sensor conversion result is selected to be compared.
- * | | |Others = reserved.
- * |[8:11] |CMPMCNT |Compare Match Count
- * | | |When the specified ADC channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1.
- * | | |When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
- * |[16:27] |CMPDAT |Compared Data
- * | | |When DMOF (ADC_CTL[31]) bit is set to 0, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with unsigned format.
- * | | |CMPDAT (ADC_CTL[27:16]) should be filled in unsigned format.
- * | | |When DMOF (ADC_CTL[31]) bit is set to 1, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with 2'complement format.
- * | | |CMPDAT (ADC_CTL[27:16]) should be filled in 2'complement format.
- */
- __IO uint32_t CMP[2];
-
- /**
- * STATUS0
- * ===================================================================================================
- * Offset: 0x50 ADC Status Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADIF |ADC Interrupt Flag
- * | | |A status flag that indicates the end of A/D conversion.
- * | | |ADIF (ADC_STATUS0[0]) is set to 1 at these two conditions:
- * | | |1. When A/D conversion ends in Single mode
- * | | |2. When A/D conversion ends on all specified channels in Scan mode
- * | | |Note: This flag can be cleared by writing 1 to it.
- * |[1] |ADCMPF0 |Compare Flag
- * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
- * | | |And it is cleared by writing 1 to self.
- * | | |0 = Conversion result in ADC_DATx does not meet ADCMPR0 setting.
- * | | |1 = Conversion result in ADC_DATx meets ADCMPR0 setting.
- * |[2] |ADCMPF1 |Compare Flag
- * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
- * | | |And it is cleared by writing 1 to self.
- * | | |0 = Conversion result in ADC_DATx does not meet ADCMPR1 setting.
- * | | |1 = Conversion result in ADC_DATx meets ADCMPR1 setting.
- * |[3] |BUSY |BUSY/IDLE (Read Only)
- * | | |0 = ADC is in idle state.
- * | | |1 = ADC is doing conversion.
- * | | |This bit is mirror of as SWTRG (ADC_CTL[11]) bit.
- * |[4:7] |CHANNEL |Current Conversion Channel (Read Only)
- * | | |This field reflects the current conversion channel when BUSY (ADC_STATUS0[3]) = 1.
- * | | |When BUSY (ADC_STATUS0[3]) = 0, it shows the number of the next converted channel.
- */
- __IO uint32_t STATUS0;
-
- /**
- * STATUS1
- * ===================================================================================================
- * Offset: 0x54 ADC Status Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:13] |VALID |Data Valid Flag (Read Only)
- * | | |It is a mirror of VALID (ADC_DATx[17]) bit.
- * |[16:29] |OV |Overrun Flag (Read Only)
- * | | |It is a mirror to OV (ADC_DATx[16]) bit.
- */
- __I uint32_t STATUS1;
- uint32_t RESERVE1[2];
-
-
- /**
- * CURDAT
- * ===================================================================================================
- * Offset: 0x60 ADC PDMA Current Transfer Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:17] |CURDAT |ADC PDMA Current Transfer Data Bit (Read Only)
- * | | |When PDMA transferring, read this register can monitor current PDMA transfer data.
- */
- __I uint32_t CURDAT;
-
-} ADC_T;
-
-/**
- @addtogroup ADC_CONST ADC Bit Field Definition
- Constant Definitions for ADC Controller
-@{ */
-
-#define ADC_DAT0_RESULT_Pos (0) /*!< ADC DAT0: RESULT Position */
-#define ADC_DAT0_RESULT_Msk (0xfffful << ADC_DAT0_RESULT_Pos) /*!< ADC DAT0: RESULT Mask */
-
-#define ADC_DAT0_OV_Pos (16) /*!< ADC DAT0: OV Position */
-#define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos) /*!< ADC DAT0: OV Mask */
-
-#define ADC_DAT0_VALID_Pos (17) /*!< ADC DAT0: VALID Position */
-#define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos) /*!< ADC DAT0: VALID Mask */
-
-#define ADC_DAT1_RESULT_Pos (0) /*!< ADC DAT1: RESULT Position */
-#define ADC_DAT1_RESULT_Msk (0xfffful << ADC_DAT1_RESULT_Pos) /*!< ADC DAT1: RESULT Mask */
-
-#define ADC_DAT1_OV_Pos (16) /*!< ADC DAT1: OV Position */
-#define ADC_DAT1_OV_Msk (0x1ul << ADC_DAT1_OV_Pos) /*!< ADC DAT1: OV Mask */
-
-#define ADC_DAT1_VALID_Pos (17) /*!< ADC DAT1: VALID Position */
-#define ADC_DAT1_VALID_Msk (0x1ul << ADC_DAT1_VALID_Pos) /*!< ADC DAT1: VALID Mask */
-
-#define ADC_DAT2_RESULT_Pos (0) /*!< ADC DAT2: RESULT Position */
-#define ADC_DAT2_RESULT_Msk (0xfffful << ADC_DAT2_RESULT_Pos) /*!< ADC DAT2: RESULT Mask */
-
-#define ADC_DAT2_OV_Pos (16) /*!< ADC DAT2: OV Position */
-#define ADC_DAT2_OV_Msk (0x1ul << ADC_DAT2_OV_Pos) /*!< ADC DAT2: OV Mask */
-
-#define ADC_DAT2_VALID_Pos (17) /*!< ADC DAT2: VALID Position */
-#define ADC_DAT2_VALID_Msk (0x1ul << ADC_DAT2_VALID_Pos) /*!< ADC DAT2: VALID Mask */
-
-#define ADC_DAT3_RESULT_Pos (0) /*!< ADC DAT3: RESULT Position */
-#define ADC_DAT3_RESULT_Msk (0xfffful << ADC_DAT3_RESULT_Pos) /*!< ADC DAT3: RESULT Mask */
-
-#define ADC_DAT3_OV_Pos (16) /*!< ADC DAT3: OV Position */
-#define ADC_DAT3_OV_Msk (0x1ul << ADC_DAT3_OV_Pos) /*!< ADC DAT3: OV Mask */
-
-#define ADC_DAT3_VALID_Pos (17) /*!< ADC DAT3: VALID Position */
-#define ADC_DAT3_VALID_Msk (0x1ul << ADC_DAT3_VALID_Pos) /*!< ADC DAT3: VALID Mask */
-
-#define ADC_DAT4_RESULT_Pos (0) /*!< ADC DAT4: RESULT Position */
-#define ADC_DAT4_RESULT_Msk (0xfffful << ADC_DAT4_RESULT_Pos) /*!< ADC DAT4: RESULT Mask */
-
-#define ADC_DAT4_OV_Pos (16) /*!< ADC DAT4: OV Position */
-#define ADC_DAT4_OV_Msk (0x1ul << ADC_DAT4_OV_Pos) /*!< ADC DAT4: OV Mask */
-
-#define ADC_DAT4_VALID_Pos (17) /*!< ADC DAT4: VALID Position */
-#define ADC_DAT4_VALID_Msk (0x1ul << ADC_DAT4_VALID_Pos) /*!< ADC DAT4: VALID Mask */
-
-#define ADC_DAT5_RESULT_Pos (0) /*!< ADC DAT5: RESULT Position */
-#define ADC_DAT5_RESULT_Msk (0xfffful << ADC_DAT5_RESULT_Pos) /*!< ADC DAT5: RESULT Mask */
-
-#define ADC_DAT5_OV_Pos (16) /*!< ADC DAT5: OV Position */
-#define ADC_DAT5_OV_Msk (0x1ul << ADC_DAT5_OV_Pos) /*!< ADC DAT5: OV Mask */
-
-#define ADC_DAT5_VALID_Pos (17) /*!< ADC DAT5: VALID Position */
-#define ADC_DAT5_VALID_Msk (0x1ul << ADC_DAT5_VALID_Pos) /*!< ADC DAT5: VALID Mask */
-
-#define ADC_DAT6_RESULT_Pos (0) /*!< ADC DAT6: RESULT Position */
-#define ADC_DAT6_RESULT_Msk (0xfffful << ADC_DAT6_RESULT_Pos) /*!< ADC DAT6: RESULT Mask */
-
-#define ADC_DAT6_OV_Pos (16) /*!< ADC DAT6: OV Position */
-#define ADC_DAT6_OV_Msk (0x1ul << ADC_DAT6_OV_Pos) /*!< ADC DAT6: OV Mask */
-
-#define ADC_DAT6_VALID_Pos (17) /*!< ADC DAT6: VALID Position */
-#define ADC_DAT6_VALID_Msk (0x1ul << ADC_DAT6_VALID_Pos) /*!< ADC DAT6: VALID Mask */
-
-#define ADC_DAT7_RESULT_Pos (0) /*!< ADC DAT7: RESULT Position */
-#define ADC_DAT7_RESULT_Msk (0xfffful << ADC_DAT7_RESULT_Pos) /*!< ADC DAT7: RESULT Mask */
-
-#define ADC_DAT7_OV_Pos (16) /*!< ADC DAT7: OV Position */
-#define ADC_DAT7_OV_Msk (0x1ul << ADC_DAT7_OV_Pos) /*!< ADC DAT7: OV Mask */
-
-#define ADC_DAT7_VALID_Pos (17) /*!< ADC DAT7: VALID Position */
-#define ADC_DAT7_VALID_Msk (0x1ul << ADC_DAT7_VALID_Pos) /*!< ADC DAT7: VALID Mask */
-
-#define ADC_DAT8_RESULT_Pos (0) /*!< ADC DAT8: RESULT Position */
-#define ADC_DAT8_RESULT_Msk (0xfffful << ADC_DAT8_RESULT_Pos) /*!< ADC DAT8: RESULT Mask */
-
-#define ADC_DAT8_OV_Pos (16) /*!< ADC DAT8: OV Position */
-#define ADC_DAT8_OV_Msk (0x1ul << ADC_DAT8_OV_Pos) /*!< ADC DAT8: OV Mask */
-
-#define ADC_DAT8_VALID_Pos (17) /*!< ADC DAT8: VALID Position */
-#define ADC_DAT8_VALID_Msk (0x1ul << ADC_DAT8_VALID_Pos) /*!< ADC DAT8: VALID Mask */
-
-#define ADC_DAT9_RESULT_Pos (0) /*!< ADC DAT9: RESULT Position */
-#define ADC_DAT9_RESULT_Msk (0xfffful << ADC_DAT9_RESULT_Pos) /*!< ADC DAT9: RESULT Mask */
-
-#define ADC_DAT9_OV_Pos (16) /*!< ADC DAT9: OV Position */
-#define ADC_DAT9_OV_Msk (0x1ul << ADC_DAT9_OV_Pos) /*!< ADC DAT9: OV Mask */
-
-#define ADC_DAT9_VALID_Pos (17) /*!< ADC DAT9: VALID Position */
-#define ADC_DAT9_VALID_Msk (0x1ul << ADC_DAT9_VALID_Pos) /*!< ADC DAT9: VALID Mask */
-
-#define ADC_DAT10_RESULT_Pos (0) /*!< ADC DAT10: RESULT Position */
-#define ADC_DAT10_RESULT_Msk (0xfffful << ADC_DAT10_RESULT_Pos) /*!< ADC DAT10: RESULT Mask */
-
-#define ADC_DAT10_OV_Pos (16) /*!< ADC DAT10: OV Position */
-#define ADC_DAT10_OV_Msk (0x1ul << ADC_DAT10_OV_Pos) /*!< ADC DAT10: OV Mask */
-
-#define ADC_DAT10_VALID_Pos (17) /*!< ADC DAT10: VALID Position */
-#define ADC_DAT10_VALID_Msk (0x1ul << ADC_DAT10_VALID_Pos) /*!< ADC DAT10: VALID Mask */
-
-#define ADC_DAT11_RESULT_Pos (0) /*!< ADC DAT11: RESULT Position */
-#define ADC_DAT11_RESULT_Msk (0xfffful << ADC_DAT11_RESULT_Pos) /*!< ADC DAT11: RESULT Mask */
-
-#define ADC_DAT11_OV_Pos (16) /*!< ADC DAT11: OV Position */
-#define ADC_DAT11_OV_Msk (0x1ul << ADC_DAT11_OV_Pos) /*!< ADC DAT11: OV Mask */
-
-#define ADC_DAT11_VALID_Pos (17) /*!< ADC DAT11: VALID Position */
-#define ADC_DAT11_VALID_Msk (0x1ul << ADC_DAT11_VALID_Pos) /*!< ADC DAT11: VALID Mask */
-
-#define ADC_DAT12_RESULT_Pos (0) /*!< ADC DAT12: RESULT Position */
-#define ADC_DAT12_RESULT_Msk (0xfffful << ADC_DAT12_RESULT_Pos) /*!< ADC DAT12: RESULT Mask */
-
-#define ADC_DAT12_OV_Pos (16) /*!< ADC DAT12: OV Position */
-#define ADC_DAT12_OV_Msk (0x1ul << ADC_DAT12_OV_Pos) /*!< ADC DAT12: OV Mask */
-
-#define ADC_DAT12_VALID_Pos (17) /*!< ADC DAT12: VALID Position */
-#define ADC_DAT12_VALID_Msk (0x1ul << ADC_DAT12_VALID_Pos) /*!< ADC DAT12: VALID Mask */
-
-#define ADC_DAT13_RESULT_Pos (0) /*!< ADC DAT13: RESULT Position */
-#define ADC_DAT13_RESULT_Msk (0xfffful << ADC_DAT13_RESULT_Pos) /*!< ADC DAT13: RESULT Mask */
-
-#define ADC_DAT13_OV_Pos (16) /*!< ADC DAT13: OV Position */
-#define ADC_DAT13_OV_Msk (0x1ul << ADC_DAT13_OV_Pos) /*!< ADC DAT13: OV Mask */
-
-#define ADC_DAT13_VALID_Pos (17) /*!< ADC DAT13: VALID Position */
-#define ADC_DAT13_VALID_Msk (0x1ul << ADC_DAT13_VALID_Pos) /*!< ADC DAT13: VALID Mask */
-
-#define ADC_CTL_ADCEN_Pos (0) /*!< ADC CTL: ADCEN Position */
-#define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) /*!< ADC CTL: ADCEN Mask */
-
-#define ADC_CTL_ADCIEN_Pos (1) /*!< ADC CTL: ADCIEN Position */
-#define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) /*!< ADC CTL: ADCIEN Mask */
-
-#define ADC_CTL_OPMODE_Pos (2) /*!< ADC CTL: OPMODE Position */
-#define ADC_CTL_OPMODE_Msk (0x3ul << ADC_CTL_OPMODE_Pos) /*!< ADC CTL: OPMODE Mask */
-
-#define ADC_CTL_HWTRGSEL_Pos (4) /*!< ADC CTL: HWTRGSEL Position */
-#define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) /*!< ADC CTL: HWTRGSEL Mask */
-
-#define ADC_CTL_HWTRGCOND_Pos (6) /*!< ADC CTL: HWTRGCOND Position */
-#define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos) /*!< ADC CTL: HWTRGCOND Mask */
-
-#define ADC_CTL_HWTRGEN_Pos (8) /*!< ADC CTL: HWTRGEN Position */
-#define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) /*!< ADC CTL: HWTRGEN Mask */
-
-#define ADC_CTL_PDMAEN_Pos (9) /*!< ADC CTL: PDMAEN Position */
-#define ADC_CTL_PDMAEN_Msk (0x1ul << ADC_CTL_PDMAEN_Pos) /*!< ADC CTL: PDMAEN Mask */
-
-#define ADC_CTL_DIFFEN_Pos (10) /*!< ADC CTL: DIFFEN Position */
-#define ADC_CTL_DIFFEN_Msk (0x1ul << ADC_CTL_DIFFEN_Pos) /*!< ADC CTL: DIFFEN Mask */
-
-#define ADC_CTL_SWTRG_Pos (11) /*!< ADC CTL: SWTRG Position */
-#define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) /*!< ADC CTL: SWTRG Mask */
-
-#define ADC_CTL_PWMTRGDLY_Pos (16) /*!< ADC CTL: PWMTRGDLY Position */
-#define ADC_CTL_PWMTRGDLY_Msk (0xfful << ADC_CTL_PWMTRGDLY_Pos) /*!< ADC CTL: PWMTRGDLY Mask */
-
-#define ADC_CTL_DMOF_Pos (31) /*!< ADC CTL: DMOF Position */
-#define ADC_CTL_DMOF_Msk (0x1ul << ADC_CTL_DMOF_Pos) /*!< ADC CTL: DMOF Mask */
-
-#define ADC_CHEN_CHEN_Pos (0) /*!< ADC CHEN: CHEN Position */
-#define ADC_CHEN_CHEN_Msk (0xffful << ADC_CHEN_CHEN_Pos) /*!< ADC CHEN: CHEN Mask */
-
-#define ADC_CHEN_ADTSEN_Pos (16) /*!< ADC CHEN: ADTSEN Position */
-#define ADC_CHEN_ADTSEN_Msk (0x1ul << ADC_CHEN_ADTSEN_Pos) /*!< ADC CHEN: ADTSEN Mask */
-
-#define ADC_CHEN_ADBGEN_Pos (17) /*!< ADC CHEN: ADBGEN Position */
-#define ADC_CHEN_ADBGEN_Msk (0x1ul << ADC_CHEN_ADBGEN_Pos) /*!< ADC CHEN: ADBGEN Mask */
-
-#define ADC_CMP0_ADCMPEN_Pos (0) /*!< ADC CMP0: ADCMPEN Position */
-#define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) /*!< ADC CMP0: ADCMPEN Mask */
-
-#define ADC_CMP0_ADCMPIE_Pos (1) /*!< ADC CMP0: ADCMPIE Position */
-#define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) /*!< ADC CMP0: ADCMPIE Mask */
-
-#define ADC_CMP0_CMPCOND_Pos (2) /*!< ADC CMP0: CMPCOND Position */
-#define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) /*!< ADC CMP0: CMPCOND Mask */
-
-#define ADC_CMP0_CMPCH_Pos (3) /*!< ADC CMP0: CMPCH Position */
-#define ADC_CMP0_CMPCH_Msk (0xful << ADC_CMP0_CMPCH_Pos) /*!< ADC CMP0: CMPCH Mask */
-
-#define ADC_CMP0_CMPMCNT_Pos (8) /*!< ADC CMP0: CMPMCNT Position */
-#define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) /*!< ADC CMP0: CMPMCNT Mask */
-
-#define ADC_CMP0_CMPDAT_Pos (16) /*!< ADC CMP0: CMPDAT Position */
-#define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) /*!< ADC CMP0: CMPDAT Mask */
-
-#define ADC_CMP1_ADCMPEN_Pos (0) /*!< ADC CMP1: ADCMPEN Position */
-#define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) /*!< ADC CMP1: ADCMPEN Mask */
-
-#define ADC_CMP1_ADCMPIE_Pos (1) /*!< ADC CMP1: ADCMPIE Position */
-#define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) /*!< ADC CMP1: ADCMPIE Mask */
-
-#define ADC_CMP1_CMPCOND_Pos (2) /*!< ADC CMP1: CMPCOND Position */
-#define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) /*!< ADC CMP1: CMPCOND Mask */
-
-#define ADC_CMP1_CMPCH_Pos (3) /*!< ADC CMP1: CMPCH Position */
-#define ADC_CMP1_CMPCH_Msk (0xful << ADC_CMP1_CMPCH_Pos) /*!< ADC CMP1: CMPCH Mask */
-
-#define ADC_CMP1_CMPMCNT_Pos (8) /*!< ADC CMP1: CMPMCNT Position */
-#define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) /*!< ADC CMP1: CMPMCNT Mask */
-
-#define ADC_CMP1_CMPDAT_Pos (16) /*!< ADC CMP1: CMPDAT Position */
-#define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) /*!< ADC CMP1: CMPDAT Mask */
-
-#define ADC_STATUS0_ADIF_Pos (0) /*!< ADC STATUS0: ADIF Position */
-#define ADC_STATUS0_ADIF_Msk (0x1ul << ADC_STATUS0_ADIF_Pos) /*!< ADC STATUS0: ADIF Mask */
-
-#define ADC_STATUS0_ADCMPF0_Pos (1) /*!< ADC STATUS0: ADCMPF0 Position */
-#define ADC_STATUS0_ADCMPF0_Msk (0x1ul << ADC_STATUS0_ADCMPF0_Pos) /*!< ADC STATUS0: ADCMPF0 Mask */
-
-#define ADC_STATUS0_ADCMPF1_Pos (2) /*!< ADC STATUS0: ADCMPF1 Position */
-#define ADC_STATUS0_ADCMPF1_Msk (0x1ul << ADC_STATUS0_ADCMPF1_Pos) /*!< ADC STATUS0: ADCMPF1 Mask */
-
-#define ADC_STATUS0_BUSY_Pos (3) /*!< ADC STATUS0: BUSY Position */
-#define ADC_STATUS0_BUSY_Msk (0x1ul << ADC_STATUS0_BUSY_Pos) /*!< ADC STATUS0: BUSY Mask */
-
-#define ADC_STATUS0_CHANNEL_Pos (4) /*!< ADC STATUS0: CHANNEL Position */
-#define ADC_STATUS0_CHANNEL_Msk (0xful << ADC_STATUS0_CHANNEL_Pos) /*!< ADC STATUS0: CHANNEL Mask */
-
-#define ADC_STATUS1_VALID_Pos (0) /*!< ADC STATUS1: VALID Position */
-#define ADC_STATUS1_VALID_Msk (0x3ffful << ADC_STATUS1_VALID_Pos) /*!< ADC STATUS1: VALID Mask */
-
-#define ADC_STATUS1_OV_Pos (16) /*!< ADC STATUS1: OV Position */
-#define ADC_STATUS1_OV_Msk (0x3ffful << ADC_STATUS1_OV_Pos) /*!< ADC STATUS1: OV Mask */
-
-#define ADC_CURDAT_CURDAT_Pos (0) /*!< ADC CURDAT: CURDAT Position */
-#define ADC_CURDAT_CURDAT_Msk (0x3fffful << ADC_CURDAT_CURDAT_Pos) /*!< ADC CURDAT: CURDAT Mask */
-
-/**@}*/ /* ADC_CONST */
-/**@}*/ /* end of ADC register group */
-
-
-/*---------------------- Controller Area Network Controller -------------------------*/
-/**
- @addtogroup CAN Controller Area Network Controller(CAN)
- Memory Mapped Structure for CAN Controller
-@{ */
-
-typedef struct {
-
- /**
- * CAN_IFn_CREQ
- * ===================================================================================================
- * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |MessageNumber|Message Number
- * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
- * | | |RAM is selected for data transfer.
- * | | |0x00: Not a valid Message Number, interpreted as 0x20.
- * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
- * |[15] |Busy |Busy Flag
- * | | |0 = Read/write action has finished.
- * | | |1 = Writing to the IFn Command Request Register is in progress.
- * | | |This bit can only be read by the software.
- */
- __IO uint32_t CREQ;
-
- /**
- * CAN_IFn_CMASK
- * ===================================================================================================
- * Offset: 0x24, 0x84 IFn Command Mask Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DAT_B |Access Data Bytes [7:4]
- * | | |Write Operation:
- * | | |0 = Data Bytes [7:4] unchanged.
- * | | |1 = Transfer Data Bytes [7:4] to Message Object.
- * | | |Read Operation:
- * | | |0 = Data Bytes [7:4] unchanged.
- * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
- * |[1] |DAT_A |Access Data Bytes [3:0]
- * | | |Write Operation:
- * | | |0 = Data Bytes [3:0] unchanged.
- * | | |1 = Transfer Data Bytes [3:0] to Message Object.
- * | | |Read Operation:
- * | | |0 = Data Bytes [3:0] unchanged.
- * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
- * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
- * | | |0 = TxRqst bit unchanged.
- * | | |1 = Set TxRqst bit.
- * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
- * | | |Access New Data Bit when Read Operation.
- * | | |0 = NewDat bit remains unchanged.
- * | | |1 = Clear NewDat bit in the Message Object.
- * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
- * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
- * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
- * | | |Write Operation:
- * | | |When writing to a Message Object, this bit is ignored.
- * | | |Read Operation:
- * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
- * | | |1 = Clear IntPnd bit in the Message Object.
- * |[4] |Control |Control Access Control Bits
- * | | |Write Operation:
- * | | |0 = Control Bits unchanged.
- * | | |1 = Transfer Control Bits to Message Object.
- * | | |Read Operation:
- * | | |0 = Control Bits unchanged.
- * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
- * |[5] |Arb |Access Arbitration Bits
- * | | |Write Operation:
- * | | |0 = Arbitration bits unchanged.
- * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
- * | | |Read Operation:
- * | | |0 = Arbitration bits unchanged.
- * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
- * |[6] |Mask |Access Mask Bits
- * | | |Write Operation:
- * | | |0 = Mask bits unchanged.
- * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
- * | | |Read Operation:
- * | | |0 = Mask bits unchanged.
- * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
- * |[7] |WR_RD |Write / Read Mode
- * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
- * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
- */
- __IO uint32_t CMASK;
-
- /**
- * CAN_IFn_MASK1
- * ===================================================================================================
- * Offset: 0x28, 0x88 IFn Mask 1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |Msk150 |Identifier Mask 15-0
- * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
- * | | |1 = The corresponding identifier bit is used for acceptance filtering.
- */
- __IO uint32_t MASK1;
-
- /**
- * CAN_IFn_MASK2
- * ===================================================================================================
- * Offset: 0x2C, 0x8C IFn Mask 2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:12] |Msk2816 |Identifier Mask 28-16
- * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
- * | | |1 = The corresponding identifier bit is used for acceptance filtering.
- * |[14] |MDir |Mask Message Direction
- * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
- * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
- * |[15] |MXtd |Mask Extended Identifier
- * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
- * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
- * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
- * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
- */
- __IO uint32_t MASK2;
-
- /**
- * CAN_IFn_ARB1
- * ===================================================================================================
- * Offset: 0x30, 0x90 IFn Arbitration 1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |ID150 |Message Identifier 15-0
- * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
- * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
- */
- __IO uint32_t ARB1;
-
- /**
- * CAN_IFn_ARB2
- * ===================================================================================================
- * Offset: 0x34, 0x94 IFn Arbitration 2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:12] |ID2816 |Message Identifier 28-16
- * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
- * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
- * |[13] |Dir |Message Direction
- * | | |0 = Direction is receive.
- * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
- * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
- * | | |1 = Direction is transmit.
- * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
- * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
- * |[14] |Xtd |Extended Identifier
- * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
- * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
- * |[15] |MsgVal |Message Valid
- * | | |0 = The Message Object is ignored by the Message Handler.
- * | | |1 = The Message Object is configured and should be considered by the Message Handler.
- * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
- * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
- */
- __IO uint32_t ARB2;
-
- /**
- * CAN_IFn_MCON
- * ===================================================================================================
- * Offset: 0x38, 0x98 IFn Message Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |DLC |Data Length Code
- * | | |0-8: Data Frame has 0-8 data bytes.
- * | | |9-15: Data Frame has 8 data bytes
- * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
- * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
- * | | |Data 0: 1st data byte of a CAN Data Frame
- * | | |Data 1: 2nd data byte of a CAN Data Frame
- * | | |Data 2: 3rd data byte of a CAN Data Frame
- * | | |Data 3: 4th data byte of a CAN Data Frame
- * | | |Data 4: 5th data byte of a CAN Data Frame
- * | | |Data 5: 6th data byte of a CAN Data Frame
- * | | |Data 6: 7th data byte of a CAN Data Frame
- * | | |Data 7 : 8th data byte of a CAN Data Frame
- * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
- * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
- * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
- * |[7] |EoB |End Of Buffer
- * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
- * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
- * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
- * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
- * |[8] |TxRqst |Transmit Request
- * | | |0 = This Message Object is not waiting for transmission.
- * | | |1 = The transmission of this Message Object is requested and is not yet done.
- * |[9] |RmtEn |Remote Enable Control
- * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
- * | | |1 = At the reception of a Remote Frame, TxRqst is set.
- * |[10] |RxIE |Receive Interrupt Enable Control
- * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
- * | | |1 = IntPnd will be set after a successful reception of a frame.
- * |[11] |TxIE |Transmit Interrupt Enable Control
- * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
- * | | |1 = IntPnd will be set after a successful transmission of a frame.
- * |[12] |UMask |Use Acceptance Mask
- * | | |0 = Mask ignored.
- * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
- * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
- * |[13] |IntPnd |Interrupt Pending
- * | | |0 = This message object is not the source of an interrupt.
- * | | |1 = This message object is the source of an interrupt.
- * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
- * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
- * | | |0 = No message lost since last time this bit was reset by the CPU.
- * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
- * |[15] |NewDat |New Data
- * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
- * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
- */
- __IO uint32_t MCON;
-
- /**
- * CAN_IFn_DAT_A1
- * ===================================================================================================
- * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |Data0 |Data Byte 0
- * | | |1st data byte of a CAN Data Frame
- * |[8:15] |Data1 |Data Byte 1
- * | | |2nd data byte of a CAN Data Frame
- */
- __IO uint32_t DAT_A1;
-
- /**
- * CAN_IFn_DAT_A2
- * ===================================================================================================
- * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |Data2 |Data Byte 2
- * | | |3rd data byte of CAN Data Frame
- * |[8:15] |Data3 |Data Byte 3
- * | | |4th data byte of CAN Data Frame
- */
- __IO uint32_t DAT_A2;
-
- /**
- * CAN_IFn_DAT_B1
- * ===================================================================================================
- * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |Data4 |Data Byte 4
- * | | |5th data byte of CAN Data Frame
- * |[8:15] |Data5 |Data Byte 5
- * | | |6th data byte of CAN Data Frame
- */
- __IO uint32_t DAT_B1;
-
- /**
- * CAN_IFn_DAT_B2
- * ===================================================================================================
- * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |Data6 |Data Byte 6
- * | | |7th data byte of CAN Data Frame.
- * |[8:15] |Data7 |Data Byte 7
- * | | |8th data byte of CAN Data Frame.
- */
- __IO uint32_t DAT_B2;
-
- __I uint32_t RESERVE0[13];
-
-} CAN_IF_T;
-
-typedef struct {
-
- /**
- * CAN_CON
- * ===================================================================================================
- * Offset: 0x00 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |Init |Init Initialization
- * | | |0 = Normal Operation.
- * | | |1 = Initialization is started.
- * |[1] |IE |Module Interrupt Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |SIE |Status Change Interrupt Enable Control
- * | | |0 = Disabled - No Status Change Interrupt will be generated.
- * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
- * |[3] |EIE |Error Interrupt Enable Control
- * | | |0 = Disabled - No Error Status Interrupt will be generated.
- * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
- * |[5] |DAR |Automatic Re-Transmission Disable Control
- * | | |0 = Automatic Retransmission of disturbed messages enabled.
- * | | |1 = Automatic Retransmission disabled.
- * |[6] |CCE |Configuration Change Enable Control
- * | | |0 = No write access to the Bit Timing Register.
- * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
- * |[7] |Test |Test Mode Enable Control
- * | | |0 = Normal Operation.
- * | | |1 = Test Mode.
- */
- __IO uint32_t CON;
-
- /**
- * CAN_STATUS
- * ===================================================================================================
- * Offset: 0x04 Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
- * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
- * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
- * | | |The unused code '7' may be written by the CPU to check for updates.
- * | | |The following table describes the error code.
- * |[3] |TxOK |Transmitted A Message Successfully
- * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
- * | | |This bit is never reset by the CAN Core.
- * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
- * |[4] |RxOK |Received A Message Successfully
- * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
- * | | |This bit is never reset by the CAN Core.
- * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
- * |[5] |EPass |Error Passive (Read Only)
- * | | |0 = The CAN Core is error active.
- * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
- * |[6] |EWarn |Error Warning Status (Read Only)
- * | | |0 = Both error counters are below the error warning limit of 96.
- * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
- * |[7] |BOff |Bus-Off Status (Read Only)
- * | | |0 = The CAN module is not in bus-off state.
- * | | |1 = The CAN module is in bus-off state.
- */
- __IO uint32_t STATUS;
-
- /**
- * CAN_ERR
- * ===================================================================================================
- * Offset: 0x08 Error Counter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |TEC |Transmit Error Counter
- * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
- * |[8:14] |REC |Receive Error Counter
- * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
- * |[15] |RP |Receive Error Passive
- * | | |0 = The Receive Error Counter is below the error passive level.
- * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
- */
- __IO uint32_t ERR;
-
- /**
- * CAN_BTIME
- * ===================================================================================================
- * Offset: 0x0C Bit Timing Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |BRP |Baud Rate Prescaler
- * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
- * | | |The bit time is built up from a multiple of this quanta.
- * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
- * |[6:7] |SJW |(Re)Synchronization Jump Width
- * | | |0x0-0x3: Valid programmed values are [0 ... 3].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
- * |[8:11] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
- * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
- * |[12:14] |TSeg2 |Time Segment After Sample Point
- * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
- * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
- */
- __IO uint32_t BTIME;
-
- /**
- * CAN_IIDR
- * ===================================================================================================
- * Offset: 0x10 Interrupt Identifier Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
- * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
- * | | |An interrupt remains pending until the application software has cleared it.
- * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
- * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
- * | | |The Status Interrupt has the highest priority.
- * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
- * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
- * | | |The Status Interrupt is cleared by reading the Status Register.
- */
- __IO uint32_t IIDR;
-
- /**
- * CAN_TEST
- * ===================================================================================================
- * Offset: 0x14 Test Register (Register Map Note 1)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |Res |Reserved
- * | | |There are reserved bits.
- * | | |These bits are always read as '0' and must always be written with '0'.
- * |[2] |Basic |Basic Mode
- * | | |0 = Basic Mode disabled.
- * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
- * |[3] |Silent |Silent Mode
- * | | |0 = Normal operation.
- * | | |1 = The module is in Silent Mode.
- * |[4] |LBack |Loop Back Mode Enable Control
- * | | |0 = Loop Back Mode is disabled.
- * | | |1 = Loop Back Mode is enabled.
- * |[5:6] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
- * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
- * | | |01 = Sample Point can be monitored at CAN_TX pin.
- * | | |10 = CAN_TX pin drives a dominant ('0') value.
- * | | |11 = CAN_TX pin drives a recessive ('1') value.
- * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
- * | | |0 = The CAN bus is dominant (CAN_RX = '0').
- * | | |1 = The CAN bus is recessive (CAN_RX = '1').
- */
- __IO uint32_t TEST;
-
- /**
- * CAN_BRPE
- * ===================================================================================================
- * Offset: 0x18 Baud Rate Prescaler Extension Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |BRPE |BRPE: Baud Rate Prescaler Extension
- * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
- * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
- */
- __IO uint32_t BRPE;
-
- __I uint32_t RESERVE0[1];
-
- __IO CAN_IF_T IF[2];
-
- __I uint32_t RESERVE1[8];
-
- /**
- * CAN_TXREQ1
- * ===================================================================================================
- * Offset: 0x100 Transmission Request Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TxRqst161 |Transmission Request Bits 16-1 (Of All Message Objects)
- * | | |0 = This Message Object is not waiting for transmission.
- * | | |1 = The transmission of this Message Object is requested and is not yet done.
- * | | |These bits are read only.
- */
- __IO uint32_t TXREQ1;
-
- /**
- * CAN_TXREQ2
- * ===================================================================================================
- * Offset: 0x104 Transmission Request Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TxRqst3217|Transmission Request Bits 32-17 (Of All Message Objects)
- * | | |0 = This Message Object is not waiting for transmission.
- * | | |1 = The transmission of this Message Object is requested and is not yet done.
- * | | |These bits are read only.
- */
- __IO uint32_t TXREQ2;
-
- __I uint32_t RESERVE2[6];
-
- /**
- * CAN_NDAT1
- * ===================================================================================================
- * Offset: 0x120 New Data Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |NewData161|New Data Bits 16-1 (Of All Message Objects)
- * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
- * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
- */
- __IO uint32_t NDAT1;
-
- /**
- * CAN_NDAT2
- * ===================================================================================================
- * Offset: 0x124 New Data Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |NewData3217|New Data Bits 32-17 (Of All Message Objects)
- * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
- * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
- */
- __IO uint32_t NDAT2;
-
- __I uint32_t RESERVE3[6];
-
- /**
- * CAN_IPND1
- * ===================================================================================================
- * Offset: 0x140 Interrupt Pending Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |IntPnd161 |Interrupt Pending Bits 16-1 (Of All Message Objects)
- * | | |0 = This message object is not the source of an interrupt.
- * | | |1 = This message object is the source of an interrupt.
- */
- __IO uint32_t IPND1;
-
- /**
- * CAN_IPND2
- * ===================================================================================================
- * Offset: 0x144 Interrupt Pending Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |IntPnd3217|Interrupt Pending Bits 32-17(Of All Message Objects)
- * | | |0 = This message object is not the source of an interrupt.
- * | | |1 = This message object is the source of an interrupt.
- */
- __IO uint32_t IPND2;
-
- __I uint32_t RESERVE4[6];
-
- /**
- * CAN_MVLD1
- * ===================================================================================================
- * Offset: 0x160 Message Valid Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |MsgVal161 |Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
- * | | |0 = This Message Object is ignored by the Message Handler.
- * | | |1 = This Message Object is configured and should be considered by the Message Handler.
- * | | |Ex.
- * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
- * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
- */
- __IO uint32_t MVLD1;
-
- /**
- * CAN_MVLD2
- * ===================================================================================================
- * Offset: 0x164 Message Valid Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |MsgVal3217|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
- * | | |0 = This Message Object is ignored by the Message Handler.
- * | | |1 = This Message Object is configured and should be considered by the Message Handler.
- * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
- * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
- */
- __IO uint32_t MVLD2;
-
- /**
- * CAN_WU_EN
- * ===================================================================================================
- * Offset: 0x168 Wake-up Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WAKUP_EN |Wake-Up Enable Control
- * | | |0 = The wake-up function Disabled.
- * | | |1 = The wake-up function Enabled.
- * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
- */
- __IO uint32_t WU_EN;
-
- /**
- * CAN_WU_STATUS
- * ===================================================================================================
- * Offset: 0x16C Wake-up Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WAKUP_STS |Wake-Up Status
- * | | |0 = No wake-up event occurred.
- * | | |1 = Wake-up event occurred.
- * | | |Note: This bit can be cleared by writing '0'.
- */
- __IO uint32_t WU_STATUS;
-} CAN_T;
-
-/**
- @addtogroup CAN_CONST CAN Bit Field Definition
- Constant Definitions for CAN Controller
-@{ */
-
-#define CAN_CON_TEST_Pos 7 /*!< CAN CON: TEST Position */
-#define CAN_CON_TEST_Msk (1ul << CAN_CON_TEST_Pos) /*!< CAN CON: TEST Mask */
-
-#define CAN_CON_CCE_Pos 6 /*!< CAN CON: CCE Position */
-#define CAN_CON_CCE_Msk (1ul << CAN_CON_CCE_Pos) /*!< CAN CON: CCE Mask */
-
-#define CAN_CON_DAR_Pos 5 /*!< CAN CON: DAR Position */
-#define CAN_CON_DAR_Msk (1ul << CAN_CON_DAR_Pos) /*!< CAN CON: DAR Mask */
-
-#define CAN_CON_EIE_Pos 3 /*!< CAN CON: EIE Position */
-#define CAN_CON_EIE_Msk (1ul << CAN_CON_EIE_Pos) /*!< CAN CON: EIE Mask */
-
-#define CAN_CON_SIE_Pos 2 /*!< CAN CON: SIE Position */
-#define CAN_CON_SIE_Msk (1ul << CAN_CON_SIE_Pos) /*!< CAN CON: SIE Mask */
-
-#define CAN_CON_IE_Pos 1 /*!< CAN CON: IE Position */
-#define CAN_CON_IE_Msk (1ul << CAN_CON_IE_Pos) /*!< CAN CON: IE Mask */
-
-#define CAN_CON_INIT_Pos 0 /*!< CAN CON: INIT Position */
-#define CAN_CON_INIT_Msk (1ul << CAN_CON_INIT_Pos) /*!< CAN CON: INIT Mask */
-
-#define CAN_STATUS_BOFF_Pos 7 /*!< CAN STATUS: BOFF Position */
-#define CAN_STATUS_BOFF_Msk (1ul << CAN_STATUS_BOFF_Pos) /*!< CAN STATUS: BOFF Mask */
-
-#define CAN_STATUS_EWARN_Pos 6 /*!< CAN STATUS: EWARN Position */
-#define CAN_STATUS_EWARN_Msk (1ul << CAN_STATUS_EWARN_Pos) /*!< CAN STATUS: EWARN Mask */
-
-#define CAN_STATUS_EPASS_Pos 5 /*!< CAN STATUS: EPASS Position */
-#define CAN_STATUS_EPASS_Msk (1ul << CAN_STATUS_EPASS_Pos) /*!< CAN STATUS: EPASS Mask */
-
-#define CAN_STATUS_RXOK_Pos 4 /*!< CAN STATUS: RXOK Position */
-#define CAN_STATUS_RXOK_Msk (1ul << CAN_STATUS_RXOK_Pos) /*!< CAN STATUS: RXOK Mask */
-
-#define CAN_STATUS_TXOK_Pos 3 /*!< CAN STATUS: TXOK Position */
-#define CAN_STATUS_TXOK_Msk (1ul << CAN_STATUS_TXOK_Pos) /*!< CAN STATUS: TXOK Mask */
-
-#define CAN_STATUS_LEC_Pos 0 /*!< CAN STATUS: LEC Position */
-#define CAN_STATUS_LEC_Msk (0x3ul << CAN_STATUS_LEC_Pos) /*!< CAN STATUS: LEC Mask */
-
-#define CAN_ERR_RP_Pos 15 /*!< CAN ERR: RP Position */
-#define CAN_ERR_RP_Msk (1ul << CAN_ERR_RP_Pos) /*!< CAN ERR: RP Mask */
-
-#define CAN_ERR_REC_Pos 8 /*!< CAN ERR: REC Position */
-#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN ERR: REC Mask */
-
-#define CAN_ERR_TEC_Pos 0 /*!< CAN ERR: TEC Position */
-#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN ERR: TEC Mask */
-
-#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN BTIME: TSEG2 Position */
-#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN BTIME: TSEG2 Mask */
-
-#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN BTIME: TSEG1 Position */
-#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN BTIME: TSEG1 Mask */
-
-#define CAN_BTIME_SJW_Pos 6 /*!< CAN BTIME: SJW Position */
-#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN BTIME: SJW Mask */
-
-#define CAN_BTIME_BRP_Pos 0 /*!< CAN BTIME: BRP Position */
-#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN BTIME: BRP Mask */
-
-#define CAN_IIDR_INTID_Pos 0 /*!< CAN IIDR: INTID Position */
-#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN IIDR: INTID Mask */
-
-#define CAN_TEST_RX_Pos 7 /*!< CAN TEST: RX Position */
-#define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) /*!< CAN TEST: RX Mask */
-
-#define CAN_TEST_TX_Pos 5 /*!< CAN TEST: TX Position */
-#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN TEST: TX Mask */
-
-#define CAN_TEST_LBACK_Pos 4 /*!< CAN TEST: LBACK Position */
-#define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) /*!< CAN TEST: LBACK Mask */
-
-#define CAN_TEST_SILENT_Pos 3 /*!< CAN TEST: Silent Position */
-#define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) /*!< CAN TEST: Silent Mask */
-
-#define CAN_TEST_BASIC_Pos 2 /*!< CAN TEST: Basic Position */
-#define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) /*!< CAN TEST: Basic Mask */
-
-#define CAN_BRPE_BRPE_Pos 0 /*!< CAN BRPE: BRPE Position */
-#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN BRPE: BRPE Mask */
-
-#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN IFnCREQ: BUSY Position */
-#define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN IFnCREQ: BUSY Mask */
-
-#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN IFnCREQ: MSGNUM Position */
-#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN IFnCREQ: MSGNUM Mask */
-
-#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN IFnCMASK: WRRD Position */
-#define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN IFnCMASK: WRRD Mask */
-
-#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN IFnCMASK: MASK Position */
-#define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN IFnCMASK: MASK Mask */
-
-#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN IFnCMASK: ARB Position */
-#define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN IFnCMASK: ARB Mask */
-
-#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN IFnCMASK: CONTROL Position */
-#define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN IFnCMASK: CONTROL Mask */
-
-#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN IFnCMASK: CLRINTPND Position */
-#define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN IFnCMASK: CLRINTPND Mask */
-
-#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN IFnCMASK: TXRQSTNEWDAT Position */
-#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN IFnCMASK: TXRQSTNEWDAT Mask */
-
-#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN IFnCMASK: DATAA Position */
-#define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN IFnCMASK: DATAA Mask */
-
-#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN IFnCMASK: DATAB Position */
-#define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN IFnCMASK: DATAB Mask */
-
-#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN IFnMASK1: MSK Position */
-#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN IFnMASK1: MSK Mask */
-
-#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN IFnMASK2: MXTD Position */
-#define CAN_IF_MASK2_MXTD_Msk (1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN IFnMASK2: MXTD Mask */
-
-#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN IFnMASK2: MDIR Position */
-#define CAN_IF_MASK2_MDIR_Msk (1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN IFnMASK2: MDIR Mask */
-
-#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN IFnMASK2: MSK Position */
-#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN IFnMASK2: MSK Mask */
-
-#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN IFnARB1: ID Position */
-#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN IFnARB1: ID Mask */
-
-#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN IFnARB2: MSGVAL Position */
-#define CAN_IF_ARB2_MSGVAL_Msk (1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN IFnARB2: MSGVAL Mask */
-
-#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN IFnARB2: XTD Position */
-#define CAN_IF_ARB2_XTD_Msk (1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN IFnARB2: XTD Mask */
-
-#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN IFnARB2: DIR Position */
-#define CAN_IF_ARB2_DIR_Msk (1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN IFnARB2: DIR Mask */
-
-#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN IFnARB2: ID Position */
-#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN IFnARB2: ID Mask */
-
-#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN IFnMCON: NEWDAT Position */
-#define CAN_IF_MCON_NEWDAT_Msk (1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN IFnMCON: NEWDAT Mask */
-
-#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN IFnMCON: MSGLST Position */
-#define CAN_IF_MCON_MSGLST_Msk (1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN IFnMCON: MSGLST Mask */
-
-#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN IFnMCON: INTPND Position */
-#define CAN_IF_MCON_INTPND_Msk (1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN IFnMCON: INTPND Mask */
-
-#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN IFnMCON: UMASK Position */
-#define CAN_IF_MCON_UMASK_Msk (1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN IFnMCON: UMASK Mask */
-
-#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN IFnMCON: TXIE Position */
-#define CAN_IF_MCON_TXIE_Msk (1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN IFnMCON: TXIE Mask */
-
-#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN IFnMCON: RXIE Position */
-#define CAN_IF_MCON_RXIE_Msk (1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN IFnMCON: RXIE Mask */
-
-#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN IFnMCON: RMTEN Position */
-#define CAN_IF_MCON_RMTEN_Msk (1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN IFnMCON: RMTEN Mask */
-
-#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN IFnMCON: TXRQST Position */
-#define CAN_IF_MCON_TXRQST_Msk (1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN IFnMCON: TXRQST Mask */
-
-#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN IFnMCON: EOB Position */
-#define CAN_IF_MCON_EOB_Msk (1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN IFnMCON: EOB Mask */
-
-#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN IFnMCON: DLC Position */
-#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN IFnMCON: DLC Mask */
-
-#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN IFnDATAA1: DATA1 Position */
-#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN IFnDATAA1: DATA1 Mask */
-
-#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN IFnDATAA1: DATA0 Position */
-#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN IFnDATAA1: DATA0 Mask */
-
-#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN IFnDATAA1: DATA3 Position */
-#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN IFnDATAA1: DATA3 Mask */
-
-#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN IFnDATAA1: DATA2 Position */
-#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN IFnDATAA1: DATA2 Mask */
-
-#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN IFnDATAB1: DATA5 Position */
-#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN IFnDATAB1: DATA5 Mask */
-
-#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN IFnDATAB1: DATA4 Position */
-#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN IFnDATAB1: DATA4 Mask */
-
-#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN IFnDATAB2: DATA7 Position */
-#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN IFnDATAB2: DATA7 Mask */
-
-#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN IFnDATAB2: DATA6 Position */
-#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN IFnDATAB2: DATA6 Mask */
-
-#define CAN_IF_TXRQST1_TXRQST_Pos 0 /*!< CAN IFnTXRQST1: TXRQST Position */
-#define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /*!< CAN IFnTXRQST1: TXRQST Mask */
-
-#define CAN_IF_TXRQST2_TXRQST_Pos 0 /*!< CAN IFnTXRQST2: TXRQST Position */
-#define CAN_IF_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST2_TXRQST_Pos) /*!< CAN IFnTXRQST2: TXRQST Mask */
-
-#define CAN_IF_NDAT1_NEWDATA_Pos 0 /*!< CAN IFnNDAT1: NEWDATA Position */
-#define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /*!< CAN IFnNDAT1: NEWDATA Mask */
-
-#define CAN_IF_NDAT2_NEWDATA_Pos 0 /*!< CAN IFnNDAT2: NEWDATA Position */
-#define CAN_IF_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT2_NEWDATA_Pos) /*!< CAN IFnNDAT2: NEWDATA Mask */
-
-#define CAN_IF_IPND1_INTPND_Pos 0 /*!< CAN IFnIPND1: INTPND Position */
-#define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /*!< CAN IFnIPND1: INTPND Mask */
-
-#define CAN_IF_IPND2_INTPND_Pos 0 /*!< CAN IFnIPND2: INTPND Position */
-#define CAN_IF_IPND2_INTPND_Msk (0xFFFFul << CAN_IF_IPND2_INTPND_Pos) /*!< CAN IFnIPND2: INTPND Mask */
-
-#define CAN_IF_MVLD1_MSGVAL_Pos 0 /*!< CAN IFnMVLD1: MSGVAL Position */
-#define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /*!< CAN IFnMVLD1: MSGVAL Mask */
-
-#define CAN_IF_MVLD2_MSGVAL_Pos 0 /*!< CAN IFnMVLD2: MSGVAL Position */
-#define CAN_IF_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD2_MSGVAL_Pos) /*!< CAN IFnMVLD2: MSGVAL Mask */
-
-#define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN WUEN: WAKUP_EN Position */
-#define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN WUEN: WAKUP_EN Mask */
-
-#define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN WUSTATUS: WAKUP_STS Position */
-#define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN WUSTATUS: WAKUP_STS Mask */
-
-/**@}*/ /* CAN_CONST */
-/**@}*/ /* end of CAN register group */
-
-
-/*---------------------- Capture Engine -------------------------*/
-/**
- @addtogroup CAP Capture Engine(CAP)
- Memory Mapped Structure for CAP Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 Image Capture Interface Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CAPEN |Image Capture Interface Enable
- * | | |0 = Image Capture Interface Disabled.
- * | | |1 = Image Capture Interface Enabled.
- * |[3] |ADDRSW |Packet Buffer Address Switch
- * | | |0 = Packet buffer address switch Disabled.
- * | | |1 = Packet buffer address switch Enabled.
- * |[5] |PLNEN |Planar Output Enable
- * | | |0 = Planar output Disabled.
- * | | |1 = Planar output Enabled.
- * |[6] |PKTEN |Packet Output Enable
- * | | |0 = Packet output Disabled.
- * | | |1 = Packet output Enabled.
- * |[16] |SHUTTER |Image Capture Interface Automatically Disable The Capture Inteface After A Frame Had Been Captured
- * | | |0 = Shutter Disabled.
- * | | |1 = Shutter Enabled.
- * |[20] |UPDATE |Update Register At New Frame
- * | | |0 = Update register at new frame Disabled.
- * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
- * |[24] |VPRST |Capture Interface Reset
- * | | |0 = Capture interface reset Disabled.
- * | | |1 = Capture interface reset Enabled.
- */
- __IO uint32_t CTL;
-
- /**
- * PAR
- * ===================================================================================================
- * Offset: 0x04 Image Capture Interface Parameter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |INFMT |Sensor Input Data Format
- * | | |0 = YCbCr422.
- * | | |1 = RGB565.
- * |[1] |SENTYPE |Sensor Input Type
- * | | |0 = CCIR601.
- * | | |1 = CCIR656, VSync & Hsync embedded in the data signal.
- * |[2:3] |INDATORD |Sensor Input Data Order
- * | | |If INFMT = 0 (YCbCr),.
- * | | | Byte 0 1 2 3
- * | | |00 = Y0 U0 Y1 V0.
- * | | |01 = Y0 V0 Y1 U0.
- * | | |10 = U0 Y0 V0 Y1.
- * | | |11 = V0 Y0 U0 Y1.
- * | | |If INFMT = 1 (RGB565),.
- * | | |00
- * | | |Byte 0
- * | | |R[4:0] G[5:3]
- * | | |Byte 1
- * | | |G[2:0] B[4:0]
- * | | |01
- * | | |Byte 0
- * | | |B[4:0] G[5:3]
- * | | |Byte 1
- * | | |G[2:0] R[4:0]
- * | | |10
- * | | |Byte 0
- * | | |G[2:0] B[4:0]
- * | | |Byte 1
- * | | |R[4:0] G[5:3]
- * | | |11
- * | | |Byte 0
- * | | |G[2:0] R[4:0]
- * | | |Byte 1
- * | | |R[4:0] G[5:3]
- * |[4:5] |OUTFMT |Image Data Format Output To System Memory
- * | | |00 = YCbCr422.
- * | | |01 = Only output Y.
- * | | |10 = RGB555.
- * | | |11 = RGB565.
- * |[6] |RANGE |Scale Input YUV CCIR601 Color Range To Full Range
- * | | |0 = default.
- * | | |1 = Scale to full range.
- * |[7] |PLNFMT |Planar Output YUV Format
- * | | |0 = YUV422.
- * | | |1 = YUV420.
- * |[8] |PCLKP |Sensor Pixel Clock Polarity
- * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock.
- * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock.
- * |[9] |HSP |Sensor Hsync Polarity
- * | | |0 = Sync Low.
- * | | |1 = Sync High.
- * |[10] |VSP |Sensor Vsync Polarity
- * | | |0 = Sync Low.
- * | | |1 = Sync High.
- * |[11:12] |COLORCTL |Special COLORCTL Processing
- * | | |00 = Normal Color.
- * | | |01 = Sepia effect, corresponding U,V component value is set at register CAP_SEPIA.
- * | | |10 = Negative picture.
- * | | |11 = Posterize image, the Y, U, V components posterizing factor are set at register CAP_POSTERIZE.
- * |[18] |FBB |Field By Blank
- * | | |Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in ccir-656 mode.
- * | | |0 = Field by blank Disabled.
- * | | |1 = Field by blank Enabled.
- */
- __IO uint32_t PAR;
-
- /**
- * INT
- * ===================================================================================================
- * Offset: 0x08 Image Capture Interface Interrupt Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |VINTF |Video Frame End Interrupt
- * | | |If this bit shows 1, receiving a frame completed.
- * | | |Write 1 to clear it.
- * |[1] |MEINTF |Bus Master Transfer Error Interrupt
- * | | |If this bit shows 1, Transfer Error occurred. Write 1 to clear it.
- * |[3] |ADDRMINTF |Memory Address Match Interrupt
- * | | |If this bit shows 1, Memory Address Match Interrupt occurred.
- * | | |Write 1 to clear it.
- * |[4] |MDINTF |Motion Detection Output Finish Interrupt
- * | | |If this bit shows 1, Motion Detection Output Finish Interrupt occurred.
- * | | |Write 1 to clear it.
- * |[16] |VIEN |Video Frame End Interrupt Enable
- * | | |0 = Video frame end interrupt Disabled.
- * | | |1 = Video frame end interrupt Enabled.
- * |[17] |MEIEN |System Memory Error Interrupt Enable
- * | | |0 = System memory error interrupt Disabled.
- * | | |1 = System memory error interrupt Enabled.
- * |[19] |ADDRMIEN |Address Match Interrupt Enable
- * | | |0 = Address match interrupt Disabled.
- * | | |1 = Address match interrupt Enabled.
- * |[20] |MDIEN |Motion Detection Output Finish Interrupt Enable
- * | | |0 = CAP_MD finish interrupt Disabled.
- * | | |1 = CAP_MD finish interrupt Enabled.
- */
- __IO uint32_t INT;
-
- /**
- * POSTERIZE
- * ===================================================================================================
- * Offset: 0x0C YUV Component Posterizing Factor Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |VCOMP |V Component Posterizing Factor
- * | | |Final_V_Out = Original_V[7:0] & V_Posterizing_Factor.
- * |[8:15] |UCOMP |U Component Posterizing Factor
- * | | |Final_U_Out = Original_U[7:0] & U_Posterizing_Factor.
- * |[16:23] |YCOMP |Y Component Posterizing Factor
- * | | |Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor.
- */
- __IO uint32_t POSTERIZE;
-
- /**
- * MD
- * ===================================================================================================
- * Offset: 0x10 Motion Detection Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |MDEN |Motion Detection Enable
- * | | |0 = CAP_MD Disabled.
- * | | |1 = CAP_MD Enabled.
- * |[8] |MDBS |Motion Detection Block Size
- * | | |0 = 16x16.
- * | | |1 = 8x8.
- * |[9] |MDSM |Motion Detection Save Mode
- * | | |0 = 1 bit DIFF + 7 bit Y Differential.
- * | | |1 = 1 bit DIFF only.
- * |[10:11] |MDDF |Motion Detection Detect Frequency
- * | | |00 = Each frame.
- * | | |01 = Every 2 frame.
- * | | |10 = Every 3 frame.
- * | | |11 = Every 4 frame.
- * |[16:20] |MDTHR |Motion Detection Differential Threshold
- */
- __IO uint32_t MD;
-
- /**
- * MDADDR
- * ===================================================================================================
- * Offset: 0x14 Motion Detection Output Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |MDADDR |Motion Detection Output Address Register (Word Alignment)
- */
- __IO uint32_t MDADDR;
-
- /**
- * MDYADDR
- * ===================================================================================================
- * Offset: 0x18 Motion Detection Temp Y Output Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |MDYADDR |Motion Detection Temp Y Output Address Register (Word Alignment)
- */
- __IO uint32_t MDYADDR;
-
- /**
- * SEPIA
- * ===================================================================================================
- * Offset: 0x1C Sepia Effect Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |VCOMP |Define the constant V component while Sepia color effect is turned on.
- * |[8:15] |UCOMP |Define the constant U component while Sepia color effect is turned on.
- */
- __IO uint32_t SEPIA;
-
- /**
- * CWSP
- * ===================================================================================================
- * Offset: 0x20 Cropping Window Starting Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |CWSADDRH |Cropping Window Horizontal Starting Address
- * |[16:26] |CWSADDRV |Cropping Window Vertical Starting Address
- */
- __IO uint32_t CWSP;
-
- /**
- * CWS
- * ===================================================================================================
- * Offset: 0x24 Cropping Window Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |CIWW |Cropping Image Window Width
- * |[16:26] |CIWH |Cropping Image Window Height
- */
- __IO uint32_t CWS;
-
- /**
- * PKTSL
- * ===================================================================================================
- * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |PKTSHML |Packet Scaling Horizontal Factor M (Lower 8-Bit)
- * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
- * | | |The output image width will be equal to the image width * N/M.
- * | | |Note: The value of N must be equal to or less than M.
- * |[8:15] |PKTSHNL |Packet Scaling Horizontal Factor N (Lower 8-Bit)
- * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
- * |[16:23] |PKTSVML |Packet Scaling Vertical Factor M (Lower 8-Bit)
- * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
- * | | |The output image width will be equal to the image height * N/M.
- * | | |Note: The value of N must be equal to or less than M.
- * |[24:31] |PKTSVNL |Packet Scaling Vertical Factor N (Lower 8-Bit)
- * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor
- */
- __IO uint32_t PKTSL;
-
- /**
- * PLNSL
- * ===================================================================================================
- * Offset: 0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |PLNSHML |Planar Scaling Horizontal Factor M (Lower 8-Bit)
- * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor.
- * | | |The output image width will be equal to the image width * N/M.
- * | | |Note: The value of N must be equal to or less than M.
- * |[8:15] |PLNSHNL |Planar Scaling Horizontal Factor N (Lower 8-Bit)
- * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor.
- * |[16:23] |PLNSVML |Planar Scaling Vertical Factor M (Lower 8-Bit)
- * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor.
- * | | |The output image width will be equal to the image height * N/M.
- * | | |Note: The value of N must be equal to or less than M.
- * |[24:31] |PLNSVNL |Planar Scaling Vertical Factor N (Lower 8-Bit)
- * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
- * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor.
- */
- __IO uint32_t PLNSL;
-
- /**
- * FRCTL
- * ===================================================================================================
- * Offset: 0x30 Scaling Frame Rate Factor Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |FRM |Scaling Frame Rate Factor M
- * | | |Specify the denominator part (M) of the frame rate scaling factor.
- * | | |The output image frame rate will be equal to input image frame rate * (N/M).
- * | | |Note: The value of N must be equal to or less than M.
- * |[8:13] |FRN |Scaling Frame Rate Factor N
- * | | |Specify the denominator part (N) of the frame rate scaling factor.
- */
- __IO uint32_t FRCTL;
-
- /**
- * STRIDE
- * ===================================================================================================
- * Offset: 0x34 Frame Output Pixel Stride Width Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:13] |PKTSTRIDE |Packet Frame Output Pixel Stride Width
- * | | |The output pixel stride size of packet pipe.
- * |[16:29] |PLNSTRIDE |Planar Frame Output Pixel Stride Width
- * | | |The output pixel stride size of planar pipe.
- */
- __IO uint32_t STRIDE;
- uint32_t RESERVE0[1];
-
-
- /**
- * FIFOTH
- * ===================================================================================================
- * Offset: 0x3C FIFO Threshold Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PLNVFTH |Planar V FIFO Threshold
- * |[8:11] |PLNUFTH |Planar U FIFO Threshold
- * |[16:20] |PLNYFTH |Planar Y FIFO Threshold
- * |[24:28] |PKTFTH |Packet FIFO Threshold
- * |[31] |OVF |FIFO Overflow Flag
- */
- __IO uint32_t FIFOTH;
-
- /**
- * CMPADDR
- * ===================================================================================================
- * Offset: 0x40 Compare Memory Base Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CMPADDR |Compare Memory Base Address
- * | | |Word aligns address; ignore the bits [1:0].
- */
- __IO uint32_t CMPADDR;
- uint32_t RESERVE1[1];
-
-
- /**
- * PKTSM
- * ===================================================================================================
- * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |PKTSHMH |Packet Scaling Horizontal Factor M (Higher 8-Bit)
- * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
- * | | |Please refer to the register CAP_PKTSL?for the detailed operation.
- * |[8:15] |PKTSHNH |Packet Scaling Horizontal Factor N (Higher 8-Bit)
- * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
- * | | |Please refer to the register CAP_PKTSL for the detailed operation.
- * |[16:23] |PKTSVMH |Packet Scaling Vertical Factor M (Higher 8-Bit)
- * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
- * | | |Please refer to the register CAP_PKTSL to check the cooperation between these two registers.
- * |[24:31] |PKTSVNH |Packet Scaling Vertical Factor N (Higher 8-Bit)
- * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
- * | | |Please refer to the register CAP_PKTSL?to check the cooperation between these two registers.
- */
- __IO uint32_t PKTSM;
-
- /**
- * PLNSM
- * ===================================================================================================
- * Offset: 0x4C Planar Scaling Vertical/Horizontal Factor Register (MSB)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |PLNSHMH |Planar Scaling Horizontal Factor M (Higher 8-Bit)
- * | | |Specifies the higher 8-bit of denominator part (M) of the horizontal scaling factor
- * | | |For detailed programming, please refer to the register CAP_PLNSL?
- * |[8:15] |PLNSHNH |Planar Scaling Horizontal Factor N (Higher 8-Bit)
- * | | |Specifies the higher 8-bit of numerator part (N) of the horizontal scaling factor.
- * | | |For detailed programming, please refer to the register CAP_PLNSL?
- * |[16:23] |PLNSVMH |Planar Scaling Vertical Factor M (Higher 8-Bit)
- * | | |Specifies the lower 8-bit of denominator part (M) of the vertical scaling factor.
- * | | |For detailed programming, please refer to the register CAP_PLNSL?
- * |[24:31] |PLNSVNH |Planar Scaling Vertical Factor N (Higher 8-Bit)
- * | | |Specifies the higher 8-bit of numerator part (N) of the vertical scaling factor.
- * | | |For detailed programming, please refer to the register CAP_PLNSL?
- */
- __IO uint32_t PLNSM;
-
- /**
- * CURADDRP
- * ===================================================================================================
- * Offset: 0x50 Current Packet System Memory Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CURADDR |Current Packet Output Memory Address
- */
- __I uint32_t CURADDRP;
-
- /**
- * CURADDRY
- * ===================================================================================================
- * Offset: 0x54 Current Planar Y System Memory Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CURADDR |Current Planar Y Output Memory Address
- */
- __I uint32_t CURADDRY;
-
- /**
- * CURADDRU
- * ===================================================================================================
- * Offset: 0x58 Current Planar U System Memory Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CURADDR |Current Planar U Output Memory Address
- */
- __I uint32_t CURADDRU;
-
- /**
- * CURVADDR
- * ===================================================================================================
- * Offset: 0x5C Current Planar V System Memory Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CURADDR |Current Planar V Output Memory Address
- */
- __I uint32_t CURVADDR;
-
- /**
- * PKTBA0
- * ===================================================================================================
- * Offset: 0x60 System Memory Packet Base Address 0 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |BASEADDR |System Memory Packet Base Address 0
- * | | |Word aligns address; ignore the bits [1:0].
- */
- __IO uint32_t PKTBA0;
-
- /**
- * PKTBA1
- * ===================================================================================================
- * Offset: 0x64 System Memory Packet Base Address 1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |BASEADDR |System Memory Packet Base Address 1
- * | | |Word aligns address; ignore the bits [1:0].
- */
- __IO uint32_t PKTBA1;
- uint32_t RESERVE2[6];
-
-
- /**
- * YBA
- * ===================================================================================================
- * Offset: 0x80 System Memory Planar Y Base Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |BASEADDR |System Memory Planar Y Base Address
- * | | |Word aligns address; ignore the bits [1:0].
- */
- __IO uint32_t YBA;
-
- /**
- * UBA
- * ===================================================================================================
- * Offset: 0x84 System Memory Planar U Base Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |BASEADDR |System Memory Planar U Base Address
- * | | |Word aligns address; ignore the bits [1:0].
- */
- __IO uint32_t UBA;
-
- /**
- * VBA
- * ===================================================================================================
- * Offset: 0x88 System Memory Planar V Base Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |BASEADDR |System Memory Planar V Base Address
- * | | |Word aligns address; ignore the bits [1:0].
- */
- __IO uint32_t VBA;
-
-} CAP_T;
-
-/**
- @addtogroup CAP_CONST CAP Bit Field Definition
- Constant Definitions for CAP Controller
-@{ */
-
-#define CAP_CTL_CAPEN_Pos (0) /*!< CAP CTL: CAPEN Position */
-#define CAP_CTL_CAPEN_Msk (0x1ul << CAP_CTL_CAPEN_Pos) /*!< CAP CTL: CAPEN Mask */
-
-#define CAP_CTL_ADDRSW_Pos (3) /*!< CAP CTL: ADDRSW Position */
-#define CAP_CTL_ADDRSW_Msk (0x1ul << CAP_CTL_ADDRSW_Pos) /*!< CAP CTL: ADDRSW Mask */
-
-#define CAP_CTL_PLNEN_Pos (5) /*!< CAP CTL: PLNEN Position */
-#define CAP_CTL_PLNEN_Msk (0x1ul << CAP_CTL_PLNEN_Pos) /*!< CAP CTL: PLNEN Mask */
-
-#define CAP_CTL_PKTEN_Pos (6) /*!< CAP CTL: PKTEN Position */
-#define CAP_CTL_PKTEN_Msk (0x1ul << CAP_CTL_PKTEN_Pos) /*!< CAP CTL: PKTEN Mask */
-
-#define CAP_CTL_SHUTTER_Pos (16) /*!< CAP CTL: SHUTTER Position */
-#define CAP_CTL_SHUTTER_Msk (0x1ul << CAP_CTL_SHUTTER_Pos) /*!< CAP CTL: SHUTTER Mask */
-
-#define CAP_CTL_UPDATE_Pos (20) /*!< CAP CTL: UPDATE Position */
-#define CAP_CTL_UPDATE_Msk (0x1ul << CAP_CTL_UPDATE_Pos) /*!< CAP CTL: UPDATE Mask */
-
-#define CAP_CTL_VPRST_Pos (24) /*!< CAP CTL: VPRST Position */
-#define CAP_CTL_VPRST_Msk (0x1ul << CAP_CTL_VPRST_Pos) /*!< CAP CTL: VPRST Mask */
-
-#define CAP_PAR_INFMT_Pos (0) /*!< CAP PAR: INFMT Position */
-#define CAP_PAR_INFMT_Msk (0x1ul << CAP_PAR_INFMT_Pos) /*!< CAP PAR: INFMT Mask */
-
-#define CAP_PAR_SENTYPE_Pos (1) /*!< CAP PAR: SENTYPE Position */
-#define CAP_PAR_SENTYPE_Msk (0x1ul << CAP_PAR_SENTYPE_Pos) /*!< CAP PAR: SENTYPE Mask */
-
-#define CAP_PAR_INDATORD_Pos (2) /*!< CAP PAR: INDATORD Position */
-#define CAP_PAR_INDATORD_Msk (0x3ul << CAP_PAR_INDATORD_Pos) /*!< CAP PAR: INDATORD Mask */
-
-#define CAP_PAR_OUTFMT_Pos (4) /*!< CAP PAR: OUTFMT Position */
-#define CAP_PAR_OUTFMT_Msk (0x3ul << CAP_PAR_OUTFMT_Pos) /*!< CAP PAR: OUTFMT Mask */
-
-#define CAP_PAR_RANGE_Pos (6) /*!< CAP PAR: RANGE Position */
-#define CAP_PAR_RANGE_Msk (0x1ul << CAP_PAR_RANGE_Pos) /*!< CAP PAR: RANGE Mask */
-
-#define CAP_PAR_PLNFMT_Pos (7) /*!< CAP PAR: PLNFMT Position */
-#define CAP_PAR_PLNFMT_Msk (0x1ul << CAP_PAR_PLNFMT_Pos) /*!< CAP PAR: PLNFMT Mask */
-
-#define CAP_PAR_PCLKP_Pos (8) /*!< CAP PAR: PCLKP Position */
-#define CAP_PAR_PCLKP_Msk (0x1ul << CAP_PAR_PCLKP_Pos) /*!< CAP PAR: PCLKP Mask */
-
-#define CAP_PAR_HSP_Pos (9) /*!< CAP PAR: HSP Position */
-#define CAP_PAR_HSP_Msk (0x1ul << CAP_PAR_HSP_Pos) /*!< CAP PAR: HSP Mask */
-
-#define CAP_PAR_VSP_Pos (10) /*!< CAP PAR: VSP Position */
-#define CAP_PAR_VSP_Msk (0x1ul << CAP_PAR_VSP_Pos) /*!< CAP PAR: VSP Mask */
-
-#define CAP_PAR_COLORCTL_Pos (11) /*!< CAP PAR: COLORCTL Position */
-#define CAP_PAR_COLORCTL_Msk (0x3ul << CAP_PAR_COLORCTL_Pos) /*!< CAP PAR: COLORCTL Mask */
-
-#define CAP_PAR_FBB_Pos (18) /*!< CAP PAR: FBB Position */
-#define CAP_PAR_FBB_Msk (0x1ul << CAP_PAR_FBB_Pos) /*!< CAP PAR: FBB Mask */
-
-#define CAP_INT_VINTF_Pos (0) /*!< CAP INT: VINTF Position */
-#define CAP_INT_VINTF_Msk (0x1ul << CAP_INT_VINTF_Pos) /*!< CAP INT: VINTF Mask */
-
-#define CAP_INT_MEINTF_Pos (1) /*!< CAP INT: MEINTF Position */
-#define CAP_INT_MEINTF_Msk (0x1ul << CAP_INT_MEINTF_Pos) /*!< CAP INT: MEINTF Mask */
-
-#define CAP_INT_ADDRMINTF_Pos (3) /*!< CAP INT: ADDRMINTF Position */
-#define CAP_INT_ADDRMINTF_Msk (0x1ul << CAP_INT_ADDRMINTF_Pos) /*!< CAP INT: ADDRMINTF Mask */
-
-#define CAP_INT_MDINTF_Pos (4) /*!< CAP INT: MDINTF Position */
-#define CAP_INT_MDINTF_Msk (0x1ul << CAP_INT_MDINTF_Pos) /*!< CAP INT: MDINTF Mask */
-
-#define CAP_INT_VIEN_Pos (16) /*!< CAP INT: VIEN Position */
-#define CAP_INT_VIEN_Msk (0x1ul << CAP_INT_VIEN_Pos) /*!< CAP INT: VIEN Mask */
-
-#define CAP_INT_MEIEN_Pos (17) /*!< CAP INT: MEIEN Position */
-#define CAP_INT_MEIEN_Msk (0x1ul << CAP_INT_MEIEN_Pos) /*!< CAP INT: MEIEN Mask */
-
-#define CAP_INT_ADDRMIEN_Pos (19) /*!< CAP INT: ADDRMIEN Position */
-#define CAP_INT_ADDRMIEN_Msk (0x1ul << CAP_INT_ADDRMIEN_Pos) /*!< CAP INT: ADDRMIEN Mask */
-
-#define CAP_INT_MDIEN_Pos (20) /*!< CAP INT: MDIEN Position */
-#define CAP_INT_MDIEN_Msk (0x1ul << CAP_INT_MDIEN_Pos) /*!< CAP INT: MDIEN Mask */
-
-#define CAP_POSTERIZE_VCOMP_Pos (0) /*!< CAP POSTERIZE: VCOMP Position */
-#define CAP_POSTERIZE_VCOMP_Msk (0xfful << CAP_POSTERIZE_VCOMP_Pos) /*!< CAP POSTERIZE: VCOMP Mask */
-
-#define CAP_POSTERIZE_UCOMP_Pos (8) /*!< CAP POSTERIZE: UCOMP Position */
-#define CAP_POSTERIZE_UCOMP_Msk (0xfful << CAP_POSTERIZE_UCOMP_Pos) /*!< CAP POSTERIZE: UCOMP Mask */
-
-#define CAP_POSTERIZE_YCOMP_Pos (16) /*!< CAP POSTERIZE: YCOMP Position */
-#define CAP_POSTERIZE_YCOMP_Msk (0xfful << CAP_POSTERIZE_YCOMP_Pos) /*!< CAP POSTERIZE: YCOMP Mask */
-
-#define CAP_MD_MDEN_Pos (0) /*!< CAP MD: MDEN Position */
-#define CAP_MD_MDEN_Msk (0x1ul << CAP_MD_MDEN_Pos) /*!< CAP MD: MDEN Mask */
-
-#define CAP_MD_MDBS_Pos (8) /*!< CAP MD: MDBS Position */
-#define CAP_MD_MDBS_Msk (0x1ul << CAP_MD_MDBS_Pos) /*!< CAP MD: MDBS Mask */
-
-#define CAP_MD_MDSM_Pos (9) /*!< CAP MD: MDSM Position */
-#define CAP_MD_MDSM_Msk (0x1ul << CAP_MD_MDSM_Pos) /*!< CAP MD: MDSM Mask */
-
-#define CAP_MD_MDDF_Pos (10) /*!< CAP MD: MDDF Position */
-#define CAP_MD_MDDF_Msk (0x3ul << CAP_MD_MDDF_Pos) /*!< CAP MD: MDDF Mask */
-
-#define CAP_MD_MDTHR_Pos (16) /*!< CAP MD: MDTHR Position */
-#define CAP_MD_MDTHR_Msk (0x1ful << CAP_MD_MDTHR_Pos) /*!< CAP MD: MDTHR Mask */
-
-#define CAP_MDADDR_MDADDR_Pos (0) /*!< CAP MDADDR: MDADDR Position */
-#define CAP_MDADDR_MDADDR_Msk (0xfffffffful << CAP_MDADDR_MDADDR_Pos) /*!< CAP MDADDR: MDADDR Mask */
-
-#define CAP_MDYADDR_MDYADDR_Pos (0) /*!< CAP MDYADDR: MDYADDR Position */
-#define CAP_MDYADDR_MDYADDR_Msk (0xfffffffful << CAP_MDYADDR_MDYADDR_Pos) /*!< CAP MDYADDR: MDYADDR Mask */
-
-#define CAP_SEPIA_VCOMP_Pos (0) /*!< CAP SEPIA: VCOMP Position */
-#define CAP_SEPIA_VCOMP_Msk (0xfful << CAP_SEPIA_VCOMP_Pos) /*!< CAP SEPIA: VCOMP Mask */
-
-#define CAP_SEPIA_UCOMP_Pos (8) /*!< CAP SEPIA: UCOMP Position */
-#define CAP_SEPIA_UCOMP_Msk (0xfful << CAP_SEPIA_UCOMP_Pos) /*!< CAP SEPIA: UCOMP Mask */
-
-#define CAP_CWSP_CWSADDRH_Pos (0) /*!< CAP CWSP: CWSADDRH Position */
-#define CAP_CWSP_CWSADDRH_Msk (0xffful << CAP_CWSP_CWSADDRH_Pos) /*!< CAP CWSP: CWSADDRH Mask */
-
-#define CAP_CWSP_CWSADDRV_Pos (16) /*!< CAP CWSP: CWSADDRV Position */
-#define CAP_CWSP_CWSADDRV_Msk (0x7fful << CAP_CWSP_CWSADDRV_Pos) /*!< CAP CWSP: CWSADDRV Mask */
-
-#define CAP_CWS_CWW_Pos (0) /*!< CAP CWS: CWW Position */
-#define CAP_CWS_CWW_Msk (0xffful << CAP_CWS_CWW_Pos) /*!< CAP CWS: CWW Mask */
-
-#define CAP_CWS_CWH_Pos (16) /*!< CAP CWS: CIWH Position */
-#define CAP_CWS_CWH_Msk (0x7fful << CAP_CWS_CWH_Pos) /*!< CAP CWS: CIWH Mask */
-
-#define CAP_PKTSL_PKTSHML_Pos (0) /*!< CAP PKTSL: PKTSHML Position */
-#define CAP_PKTSL_PKTSHML_Msk (0xfful << CAP_PKTSL_PKTSHML_Pos) /*!< CAP PKTSL: PKTSHML Mask */
-
-#define CAP_PKTSL_PKTSHNL_Pos (8) /*!< CAP PKTSL: PKTSHNL Position */
-#define CAP_PKTSL_PKTSHNL_Msk (0xfful << CAP_PKTSL_PKTSHNL_Pos) /*!< CAP PKTSL: PKTSHNL Mask */
-
-#define CAP_PKTSL_PKTSVML_Pos (16) /*!< CAP PKTSL: PKTSVML Position */
-#define CAP_PKTSL_PKTSVML_Msk (0xfful << CAP_PKTSL_PKTSVML_Pos) /*!< CAP PKTSL: PKTSVML Mask */
-
-#define CAP_PKTSL_PKTSVNL_Pos (24) /*!< CAP PKTSL: PKTSVNL Position */
-#define CAP_PKTSL_PKTSVNL_Msk (0xfful << CAP_PKTSL_PKTSVNL_Pos) /*!< CAP PKTSL: PKTSVNL Mask */
-
-#define CAP_PLNSL_PLNSHML_Pos (0) /*!< CAP PLNSL: PLNSHML Position */
-#define CAP_PLNSL_PLNSHML_Msk (0xfful << CAP_PLNSL_PLNSHML_Pos) /*!< CAP PLNSL: PLNSHML Mask */
-
-#define CAP_PLNSL_PLNSHNL_Pos (8) /*!< CAP PLNSL: PLNSHNL Position */
-#define CAP_PLNSL_PLNSHNL_Msk (0xfful << CAP_PLNSL_PLNSHNL_Pos) /*!< CAP PLNSL: PLNSHNL Mask */
-
-#define CAP_PLNSL_PLNSVML_Pos (16) /*!< CAP PLNSL: PLNSVML Position */
-#define CAP_PLNSL_PLNSVML_Msk (0xfful << CAP_PLNSL_PLNSVML_Pos) /*!< CAP PLNSL: PLNSVML Mask */
-
-#define CAP_PLNSL_PLNSVNL_Pos (24) /*!< CAP PLNSL: PLNSVNL Position */
-#define CAP_PLNSL_PLNSVNL_Msk (0xfful << CAP_PLNSL_PLNSVNL_Pos) /*!< CAP PLNSL: PLNSVNL Mask */
-
-#define CAP_FRCTL_FRM_Pos (0) /*!< CAP FRCTL: FRM Position */
-#define CAP_FRCTL_FRM_Msk (0x3ful << CAP_FRCTL_FRM_Pos) /*!< CAP FRCTL: FRM Mask */
-
-#define CAP_FRCTL_FRN_Pos (8) /*!< CAP FRCTL: FRN Position */
-#define CAP_FRCTL_FRN_Msk (0x3ful << CAP_FRCTL_FRN_Pos) /*!< CAP FRCTL: FRN Mask */
-
-#define CAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CAP STRIDE: PKTSTRIDE Position */
-#define CAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CAP_STRIDE_PKTSTRIDE_Pos) /*!< CAP STRIDE: PKTSTRIDE Mask */
-
-#define CAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CAP STRIDE: PLNSTRIDE Position */
-#define CAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CAP_STRIDE_PLNSTRIDE_Pos) /*!< CAP STRIDE: PLNSTRIDE Mask */
-
-#define CAP_FIFOTH_PLNVFTH_Pos (0) /*!< CAP FIFOTH: PLNVFTH Position */
-#define CAP_FIFOTH_PLNVFTH_Msk (0xful << CAP_FIFOTH_PLNVFTH_Pos) /*!< CAP FIFOTH: PLNVFTH Mask */
-
-#define CAP_FIFOTH_PLNUFTH_Pos (8) /*!< CAP FIFOTH: PLNUFTH Position */
-#define CAP_FIFOTH_PLNUFTH_Msk (0xful << CAP_FIFOTH_PLNUFTH_Pos) /*!< CAP FIFOTH: PLNUFTH Mask */
-
-#define CAP_FIFOTH_PLNYFTH_Pos (16) /*!< CAP FIFOTH: PLNYFTH Position */
-#define CAP_FIFOTH_PLNYFTH_Msk (0x1ful << CAP_FIFOTH_PLNYFTH_Pos) /*!< CAP FIFOTH: PLNYFTH Mask */
-
-#define CAP_FIFOTH_PKTFTH_Pos (24) /*!< CAP FIFOTH: PKTFTH Position */
-#define CAP_FIFOTH_PKTFTH_Msk (0x1ful << CAP_FIFOTH_PKTFTH_Pos) /*!< CAP FIFOTH: PKTFTH Mask */
-
-#define CAP_FIFOTH_OVF_Pos (31) /*!< CAP FIFOTH: OVF Position */
-#define CAP_FIFOTH_OVF_Msk (0x1ul << CAP_FIFOTH_OVF_Pos) /*!< CAP FIFOTH: OVF Mask */
-
-#define CAP_CMPADDR_CMPADDR_Pos (0) /*!< CAP CMPADDR: CMPADDR Position */
-#define CAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CAP_CMPADDR_CMPADDR_Pos) /*!< CAP CMPADDR: CMPADDR Mask */
-
-#define CAP_PKTSM_PKTSHMH_Pos (0) /*!< CAP PKTSM: PKTSHMH Position */
-#define CAP_PKTSM_PKTSHMH_Msk (0xfful << CAP_PKTSM_PKTSHMH_Pos) /*!< CAP PKTSM: PKTSHMH Mask */
-
-#define CAP_PKTSM_PKTSHNH_Pos (8) /*!< CAP PKTSM: PKTSHNH Position */
-#define CAP_PKTSM_PKTSHNH_Msk (0xfful << CAP_PKTSM_PKTSHNH_Pos) /*!< CAP PKTSM: PKTSHNH Mask */
-
-#define CAP_PKTSM_PKTSVMH_Pos (16) /*!< CAP PKTSM: PKTSVMH Position */
-#define CAP_PKTSM_PKTSVMH_Msk (0xfful << CAP_PKTSM_PKTSVMH_Pos) /*!< CAP PKTSM: PKTSVMH Mask */
-
-#define CAP_PKTSM_PKTSVNH_Pos (24) /*!< CAP PKTSM: PKTSVNH Position */
-#define CAP_PKTSM_PKTSVNH_Msk (0xfful << CAP_PKTSM_PKTSVNH_Pos) /*!< CAP PKTSM: PKTSVNH Mask */
-
-#define CAP_PLNSM_PLNSHMH_Pos (0) /*!< CAP PLNSM: PLNSHMH Position */
-#define CAP_PLNSM_PLNSHMH_Msk (0xfful << CAP_PLNSM_PLNSHMH_Pos) /*!< CAP PLNSM: PLNSHMH Mask */
-
-#define CAP_PLNSM_PLNSHNH_Pos (8) /*!< CAP PLNSM: PLNSHNH Position */
-#define CAP_PLNSM_PLNSHNH_Msk (0xfful << CAP_PLNSM_PLNSHNH_Pos) /*!< CAP PLNSM: PLNSHNH Mask */
-
-#define CAP_PLNSM_PLNSVMH_Pos (16) /*!< CAP PLNSM: PLNSVMH Position */
-#define CAP_PLNSM_PLNSVMH_Msk (0xfful << CAP_PLNSM_PLNSVMH_Pos) /*!< CAP PLNSM: PLNSVMH Mask */
-
-#define CAP_PLNSM_PLNSVNH_Pos (24) /*!< CAP PLNSM: PLNSVNH Position */
-#define CAP_PLNSM_PLNSVNH_Msk (0xfful << CAP_PLNSM_PLNSVNH_Pos) /*!< CAP PLNSM: PLNSVNH Mask */
-
-#define CAP_CURADDRP_CURADDR_Pos (0) /*!< CAP CURADDRP: CURADDR Position */
-#define CAP_CURADDRP_CURADDR_Msk (0xfffffffful << CAP_CURADDRP_CURADDR_Pos) /*!< CAP CURADDRP: CURADDR Mask */
-
-#define CAP_CURADDRY_CURADDR_Pos (0) /*!< CAP CURADDRY: CURADDR Position */
-#define CAP_CURADDRY_CURADDR_Msk (0xfffffffful << CAP_CURADDRY_CURADDR_Pos) /*!< CAP CURADDRY: CURADDR Mask */
-
-#define CAP_CURADDRU_CURADDR_Pos (0) /*!< CAP CURADDRU: CURADDR Position */
-#define CAP_CURADDRU_CURADDR_Msk (0xfffffffful << CAP_CURADDRU_CURADDR_Pos) /*!< CAP CURADDRU: CURADDR Mask */
-
-#define CAP_CURVADDR_CURADDR_Pos (0) /*!< CAP CURVADDR: CURADDR Position */
-#define CAP_CURVADDR_CURADDR_Msk (0xfffffffful << CAP_CURVADDR_CURADDR_Pos) /*!< CAP CURVADDR: CURADDR Mask */
-
-#define CAP_PKTBA0_BASEADDR_Pos (0) /*!< CAP PKTBA0: BASEADDR Position */
-#define CAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CAP_PKTBA0_BASEADDR_Pos) /*!< CAP PKTBA0: BASEADDR Mask */
-
-#define CAP_PKTBA1_BASEADDR_Pos (0) /*!< CAP PKTBA1: BASEADDR Position */
-#define CAP_PKTBA1_BASEADDR_Msk (0xfffffffful << CAP_PKTBA1_BASEADDR_Pos) /*!< CAP PKTBA1: BASEADDR Mask */
-
-#define CAP_YBA_BASEADDR_Pos (0) /*!< CAP YBA: BASEADDR Position */
-#define CAP_YBA_BASEADDR_Msk (0xfffffffful << CAP_YBA_BASEADDR_Pos) /*!< CAP YBA: BASEADDR Mask */
-
-#define CAP_UBA_BASEADDR_Pos (0) /*!< CAP UBA: BASEADDR Position */
-#define CAP_UBA_BASEADDR_Msk (0xfffffffful << CAP_UBA_BASEADDR_Pos) /*!< CAP UBA: BASEADDR Mask */
-
-#define CAP_VBA_BASEADDR_Pos (0) /*!< CAP VBA: BASEADDR Position */
-#define CAP_VBA_BASEADDR_Msk (0xfffffffful << CAP_VBA_BASEADDR_Pos) /*!< CAP VBA: BASEADDR Mask */
-
-/**@}*/ /* CAP_CONST */
-/**@}*/ /* end of CAP register group */
-
-
-/*---------------------- Enhanced Input Capture Timer -------------------------*/
-/**
- @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
- Memory Mapped Structure for ECAP Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CNT
- * ===================================================================================================
- * Offset: 0x00 Input Capture Counter (24-bit up counter)
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |VAL |Input Capture Timer/Counter
- * | | |The input Capture Timer/Counter is a 24-bit up-counting counter.
- * | | |The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
- */
- __IO uint32_t CNT;
-
- /**
- * HOLD0
- * ===================================================================================================
- * Offset: 0x04 Input Capture Counter Hold Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |VAL |Input Capture Counter Hold Register
- * | | |When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
- * | | |Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
- */
- __IO uint32_t HOLD0;
-
- /**
- * HOLD1
- * ===================================================================================================
- * Offset: 0x08 Input Capture Counter Hold Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |VAL |Input Capture Counter Hold Register
- * | | |When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
- * | | |Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
- */
- __IO uint32_t HOLD1;
-
- /**
- * HOLD2
- * ===================================================================================================
- * Offset: 0x0C Input Capture Counter Hold Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |VAL |Input Capture Counter Hold Register
- * | | |When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
- * | | |Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
- */
- __IO uint32_t HOLD2;
-
- /**
- * CNTCMP
- * ===================================================================================================
- * Offset: 0x10 Input Capture Counter Compare Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |VAL |Input Capture Counter Compare Register
- * | | |If the compare function is enabled (CMPEN = 1), the compare register is loaded with the value that the compare function compares the capture counter (ECAP_CNT) with.
- * | | |If the reload control is enabled (RLDEN = 1), an overflow event or capture events will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.
- */
- __IO uint32_t CNTCMP;
-
- /**
- * CTL0
- * ===================================================================================================
- * Offset: 0x14 Input Capture Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |NFDIS |Noise Filter Clock Pre-Divide Selection
- * | | |To determine the sampling frequency of the Noise Filter clock
- * | | |00 = CAP_CLK.
- * | | |01 = CAP_CLK/2.
- * | | |10 = CAP_CLK/4.
- * | | |11 = CAP_CLK/16.
- * |[3] |CAPNF_DIS |Input Capture Noise Filter Disable Control
- * | | |0 = Noise filter of Input Capture Enabled.
- * | | |1 = Noise filter of Input Capture Disabled.
- * |[4] |CAPEN0 |Port Pin IC0 Input To Input Capture Unit Enable Control
- * | | |0 = IC0 input to Input Capture Unit Disabled.
- * | | |1 = IC0 input to Input Capture Unit Enabled.
- * |[5] |CAPEN1 |Port Pin IC1 Input To Input Capture Unit Enable Control
- * | | |0 = IC1 input to Input Capture Unit Disabled.
- * | | |1 = IC1 input to Input Capture Unit Enabled.
- * |[6] |CAPEN2 |Port Pin IC2 Input To Input Capture Unit Enable Control
- * | | |0 = IC2 input to Input Capture Unit Disabled.
- * | | |1 = IC2 input to Input Capture Unit Enabled.
- * |[8:9] |CAPSEL0 |CAP0 Input Source Selection
- * | | |00 = CAP0 input is from port pin IC0.
- * | | |01 = CAP0 input is from signal CPO0 (Analog comparator 0 output).
- * | | |10 = CAP0 input is from signal CHA of QEI controller unit x.
- * | | |11 = CAP0 input is from signal OPDO0 (OP0 digital output).
- * | | |Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
- * |[10:11] |CAPSEL1 |CAP1 Input Source Selection
- * | | |00 = CAP1 input is from port pin IC1.
- * | | |01 = CAP1 input is from signal CPO1 (Analog comparator 1 output).
- * | | |10 = CAP1 input is from signal CHB of QEI controller unit x.
- * | | |11 = CAP1 input is from signal OPDO1 (OP1 digital output).
- * | | |Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
- * |[12:13] |CAPSEL2 |CAP2 Input Source Selection
- * | | |00 = CAP2 input is from port pin IC2.
- * | | |01 = CAP2 input is from signal CPO2 (Analog comparator 2 output).
- * | | |10 = CAP2 input is from signal CHX of QEI controller unit x.
- * | | |11 = CAP2 input is from signal ADCMPOx (ADC compare output x).
- * | | |Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
- * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
- * | | |0 = The flag CAPF0 can trigger Input Capture interrupt Disabled.
- * | | |1 = The flag CAPF0 can trigger Input Capture interrupt Enabled.
- * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
- * | | |0 = The flag CAPF1 can trigger Input Capture interrupt Disabled.
- * | | |1 = The flag CAPF1 can trigger Input Capture interrupt Enabled.
- * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
- * | | |0 = The flag CAPF2 can trigger Input Capture interrupt Disabled.
- * | | |1 = The flag CAPF2 can trigger Input Capture interrupt Enabled.
- * |[20] |OVIEN |OVF Trigger Input Capture Interrupt Enable Control
- * | | |0 = The flag OVUNF can trigger Input Capture interrupt Disabled.
- * | | |1 = The flag OVUNF can trigger Input Capture interrupt Enabled.
- * |[21] |CMPIEN |CMPF Trigger Input Capture Interrupt Enable Control
- * | | |0 = The flag CMPF can trigger Input Capture interrupt Disabled.
- * | | |1 = The flag CMPF can trigger Input Capture interrupt Enabled.
- * |[24] |CNTEN |Input Capture Counter Start
- * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK).
- * | | |0 = ECAP_CNT stop counting.
- * | | |1 = ECAP_CNT starts up-counting.
- * |[25] |CMPCLR |Input Capture Counter Cleared By Compare-Match Control
- * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAMCMPF = 1) occurs.
- * | | |0 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled.
- * | | |1 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled.
- * |[26] |CPTCLR |Input Capture Counter Cleared By Capture Events Control
- * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs.
- * | | |0 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled.
- * | | |1 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled.
- * |[27] |RLDEN |Reload Function Enable Control
- * | | |Setting this bit to enable the reload function.
- * | | |If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.
- * | | |0 = The reload function Disabled.
- * | | |1 = The reload function Enabled.
- * |[28] |CMPEN |Compare Function Enable Control
- * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set.
- * | | |0 = The compare function Disabled.
- * | | |1 = The compare function Enabled.
- * |[29] |CAPEN |Input Capture Timer/Counter Enable Control
- * | | |0 = Input Capture function Disabled.
- * | | |1 = Input Capture function Enabled.
- */
- __IO uint32_t CTL0;
-
- /**
- * CTL1
- * ===================================================================================================
- * Offset: 0x18 Input Capture Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |EDGESEL0 |Channel 0 Captured Edge Selection
- * | | |Input capture can detect falling edge change only, rising edge change only or one of both edge change
- * | | |00 = Detect rising edge.
- * | | |01 = Detect falling edge.
- * | | |1x = Detect either rising or falling edge.
- * |[2:3] |EDGESEL1 |Channel 1 Captured Edge Selection
- * | | |Input capture can detect falling edge change only, rising edge change only or one of both edge change
- * | | |00 = Detect rising edge.
- * | | |01 = Detect falling edge.
- * | | |1x = Detect either rising or falling edge.
- * |[4:5] |EDGESEL2 |Channel 2 Captured Edge Selection
- * | | |Input capture can detect falling edge change or rising edge change only, or one of both edge changes.
- * | | |00 = Detect rising edge.
- * | | |01 = Detect falling edge.
- * | | |1x = Detect either rising or falling edge.
- * |[8:10] |RLDSEL |ECAP_CNT Reload Trigger Source Selection
- * | | |If the reload function is enabled RLDEN (ECAP_CTL0[27]) = 1, when a reload trigger event comes, the ECAP_CNT is reloaded with ECAP_CNTCMP.
- * | | |RLDSEL[2:0] determines the ECAP_CNT reload trigger source
- * | | |000 = CAPF0.
- * | | |001 = CAPF1.
- * | | |010 = CAPF2.
- * | | |100 = OVF.
- * | | |Others = Reserved.
- * |[12:14] |CLKSEL |Capture Timer Clock Divide Selection
- * | | |The capture timer clock has a pre-divider with four divided options controlled by CLKSEL[1:0].
- * | | |000 = CAP_CLK/1.
- * | | |001 = CAP_CLK/4.
- * | | |010 = CAP_CLK/16.
- * | | |011 = CAP_CLK/32.
- * | | |100 = CAP_CLK/64.
- * | | |101 = CAP_CLK/96.
- * | | |110 = CAP_CLK/112.
- * | | |111 = CAP_CLK/128.
- * |[16:17] |SRCSEL |Capture Timer/Counter Clock Source Selection
- * | | |Select the capture timer/counter clock source.
- * | | |00 = CAP_CLK (default).
- * | | |01 = CAP0.
- * | | |10 = CAP1.
- * | | |11 = CAP2.
- */
- __IO uint32_t CTL1;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x1C Input Capture Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CAPF0 |Input Capture Channel 0 Captured Flag
- * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high.
- * | | |0 = No valid edge change is detected at CAP0 input.
- * | | |1 = A valid edge change is detected at CAP0 input.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[1] |CAPF1 |Input Capture Channel 1 Captured Flag
- * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high.
- * | | |0 = No valid edge change is detected at CAP1 input.
- * | | |1 = A valid edge change is detected at CAP1 input.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[2] |CAPF2 |Input Capture Channel 2 Captured Flag
- * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high.
- * | | |0 = No valid edge change is detected at CAP2 input.
- * | | |1 = A valid edge change is detected at CAP2 input.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[4] |CMPF |Input Capture Compare-Match Flag
- * | | |If the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.
- * | | |0 = ECAP_CNT does not match with ECAP_CNTCMP value.
- * | | |1 = ECAP_CNT counts to the same as ECAP_CNTCMP value.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[5] |OVF |Input Capture Counter Overflow Flag
- * | | |Flag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
- * | | |0 = No overflow occurs in ECAP_CNT.
- * | | |1 = ECAP_CNT overflows.
- * | | |Note: This bit is only cleared by writing 1 to it.
- */
- __IO uint32_t STATUS;
-
-} ECAP_T;
-
-/**
- @addtogroup ECAP_CONST ECAP Bit Field Definition
- Constant Definitions for ECAP Controller
-@{ */
-
-#define ECAP_CNT_VAL_Pos (0) /*!< ECAP CNT: VAL Position */
-#define ECAP_CNT_VAL_Msk (0xfffffful << ECAP_CNT_VAL_Pos) /*!< ECAP CNT: VAL Mask */
-
-#define ECAP_HOLD0_VAL_Pos (0) /*!< ECAP HOLD0: VAL Position */
-#define ECAP_HOLD0_VAL_Msk (0xfffffful << ECAP_HOLD0_VAL_Pos) /*!< ECAP HOLD0: VAL Mask */
-
-#define ECAP_HOLD1_VAL_Pos (0) /*!< ECAP HOLD1: VAL Position */
-#define ECAP_HOLD1_VAL_Msk (0xfffffful << ECAP_HOLD1_VAL_Pos) /*!< ECAP HOLD1: VAL Mask */
-
-#define ECAP_HOLD2_VAL_Pos (0) /*!< ECAP HOLD2: VAL Position */
-#define ECAP_HOLD2_VAL_Msk (0xfffffful << ECAP_HOLD2_VAL_Pos) /*!< ECAP HOLD2: VAL Mask */
-
-#define ECAP_CNTCMP_VAL_Pos (0) /*!< ECAP CNTCMP: VAL Position */
-#define ECAP_CNTCMP_VAL_Msk (0xfffffful << ECAP_CNTCMP_VAL_Pos) /*!< ECAP CNTCMP: VAL Mask */
-
-#define ECAP_CTL0_NFDIS_Pos (0) /*!< ECAP CTL0: NFDIS Position */
-#define ECAP_CTL0_NFDIS_Msk (0x3ul << ECAP_CTL0_NFDIS_Pos) /*!< ECAP CTL0: NFDIS Mask */
-
-#define ECAP_CTL0_CAPNF_DIS_Pos (3) /*!< ECAP CTL0: CAPNF_DIS Position */
-#define ECAP_CTL0_CAPNF_DIS_Msk (0x1ul << ECAP_CTL0_CAPNF_DIS_Pos) /*!< ECAP CTL0: CAPNF_DIS Mask */
-
-#define ECAP_CTL0_CAPEN0_Pos (4) /*!< ECAP CTL0: CAPEN0 Position */
-#define ECAP_CTL0_CAPEN0_Msk (0x1ul << ECAP_CTL0_CAPEN0_Pos) /*!< ECAP CTL0: CAPEN0 Mask */
-
-#define ECAP_CTL0_CAPEN1_Pos (5) /*!< ECAP CTL0: CAPEN1 Position */
-#define ECAP_CTL0_CAPEN1_Msk (0x1ul << ECAP_CTL0_CAPEN1_Pos) /*!< ECAP CTL0: CAPEN1 Mask */
-
-#define ECAP_CTL0_CAPEN2_Pos (6) /*!< ECAP CTL0: CAPEN2 Position */
-#define ECAP_CTL0_CAPEN2_Msk (0x1ul << ECAP_CTL0_CAPEN2_Pos) /*!< ECAP CTL0: CAPEN2 Mask */
-
-#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP CTL0: CAPSEL0 Position */
-#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP CTL0: CAPSEL0 Mask */
-
-#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP CTL0: CAPSEL1 Position */
-#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP CTL0: CAPSEL1 Mask */
-
-#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP CTL0: CAPSEL2 Position */
-#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP CTL0: CAPSEL2 Mask */
-
-#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP CTL0: CAPIEN0 Position */
-#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP CTL0: CAPIEN0 Mask */
-
-#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP CTL0: CAPIEN1 Position */
-#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP CTL0: CAPIEN1 Mask */
-
-#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP CTL0: CAPIEN2 Position */
-#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP CTL0: CAPIEN2 Mask */
-
-#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP CTL0: OVIEN Position */
-#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP CTL0: OVIEN Mask */
-
-#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP CTL0: CMPIEN Position */
-#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP CTL0: CMPIEN Mask */
-
-#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP CTL0: CNTEN Position */
-#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP CTL0: CNTEN Mask */
-
-#define ECAP_CTL0_CMPCLR_Pos (25) /*!< ECAP CTL0: CMPCLR Position */
-#define ECAP_CTL0_CMPCLR_Msk (0x1ul << ECAP_CTL0_CMPCLR_Pos) /*!< ECAP CTL0: CMPCLR Mask */
-
-#define ECAP_CTL0_CPTCLR_Pos (26) /*!< ECAP CTL0: CPTCLR Position */
-#define ECAP_CTL0_CPTCLR_Msk (0x1ul << ECAP_CTL0_CPTCLR_Pos) /*!< ECAP CTL0: CPTCLR Mask */
-
-#define ECAP_CTL0_RLDEN_Pos (27) /*!< ECAP CTL0: RLDEN Position */
-#define ECAP_CTL0_RLDEN_Msk (0x1ul << ECAP_CTL0_RLDEN_Pos) /*!< ECAP CTL0: RLDEN Mask */
-
-#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP CTL0: CMPEN Position */
-#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP CTL0: CMPEN Mask */
-
-#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP CTL0: CAPEN Position */
-#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP CTL0: CAPEN Mask */
-
-#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP CTL1: EDGESEL0 Position */
-#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP CTL1: EDGESEL0 Mask */
-
-#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP CTL1: EDGESEL1 Position */
-#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP CTL1: EDGESEL1 Mask */
-
-#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP CTL1: EDGESEL2 Position */
-#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP CTL1: EDGESEL2 Mask */
-
-#define ECAP_CTL1_RLDSEL_Pos (8) /*!< ECAP CTL1: RLDSEL Position */
-#define ECAP_CTL1_RLDSEL_Msk (0x7ul << ECAP_CTL1_RLDSEL_Pos) /*!< ECAP CTL1: RLDSEL Mask */
-
-#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP CTL1: CLKSEL Position */
-#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP CTL1: CLKSEL Mask */
-
-#define ECAP_CTL1_SRCSEL_Pos (16) /*!< ECAP CTL1: SRCSEL Position */
-#define ECAP_CTL1_SRCSEL_Msk (0x3ul << ECAP_CTL1_SRCSEL_Pos) /*!< ECAP CTL1: SRCSEL Mask */
-
-#define ECAP_STATUS_CAPF0_Pos (0) /*!< ECAP STATUS: CAPF0 Position */
-#define ECAP_STATUS_CAPF0_Msk (0x1ul << ECAP_STATUS_CAPF0_Pos) /*!< ECAP STATUS: CAPF0 Mask */
-
-#define ECAP_STATUS_CAPF1_Pos (1) /*!< ECAP STATUS: CAPF1 Position */
-#define ECAP_STATUS_CAPF1_Msk (0x1ul << ECAP_STATUS_CAPF1_Pos) /*!< ECAP STATUS: CAPF1 Mask */
-
-#define ECAP_STATUS_CAPF2_Pos (2) /*!< ECAP STATUS: CAPF2 Position */
-#define ECAP_STATUS_CAPF2_Msk (0x1ul << ECAP_STATUS_CAPF2_Pos) /*!< ECAP STATUS: CAPF2 Mask */
-
-#define ECAP_STATUS_CMPF_Pos (4) /*!< ECAP STATUS: CMPF Position */
-#define ECAP_STATUS_CMPF_Msk (0x1ul << ECAP_STATUS_CMPF_Pos) /*!< ECAP STATUS: CMPF Mask */
-
-#define ECAP_STATUS_OVF_Pos (5) /*!< ECAP STATUS: OVF Position */
-#define ECAP_STATUS_OVF_Msk (0x1ul << ECAP_STATUS_OVF_Pos) /*!< ECAP STATUS: OVF Mask */
-
-/**@}*/ /* ECAP_CONST */
-/**@}*/ /* end of ECAP register group */
-
-
-/*---------------------- System Clock Controller -------------------------*/
-/**
- @addtogroup CLK System Clock Controller(CLK)
- Memory Mapped Structure for CLK Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * PWRCTL
- * ===================================================================================================
- * Offset: 0x00 System Power-down Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HXTEN |4~24 MHz External High-Speed Crystal Enable Control (Write Protect)
- * | | |The bit default value is set by flash controller user configuration register config0 [26:24].
- * | | |When the default clock source is from 4~24 MHz external high-speed crystal, this bit is set to 1 automatically
- * | | |0 = HXT Disabled.
- * | | |1 = HXT Enabled.
- * |[1] |LXTEN |LXT Enable Control (Write Protect)
- * | | |0 = LXT Disabled.
- * | | |1 = LXT (Normal operation) Enabled.
- * |[2] |HIRCEN |HIRC Enable Control (Write Protect)
- * | | |0 = HIRC Disabled.
- * | | |1 = HIRC Enabled.
- * |[3] |LIRCEN |10 KHz Internal Low-Speed Oscillator Enable Control (Write Protect)
- * | | |0 = LIRC Disabled.
- * | | |1 = LIRC Enabled (default 1).
- * |[4] |PDWKDLY |Wake-Up Delay Counter Enable Control (Write Protect)
- * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
- * | | |The delayed clock cycle is 4096 clock cycles when chip work at HXT, and 256 clock cycles when chip works at HIRC.
- * | | |0 = Clock cycles delay Disabled.
- * | | |1 = Clock cycles delay Enabled.
- * |[5] |PDWKIEN |Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)
- * | | |0 = Power-down Mode Wake-up Interrupt Disabled.
- * | | |1 = Power-down Mode Wake-up Interrupt Enabled.
- * | | |Note: The interrupt will occur when both PDWKIF and PDWKIEN are high.
- * |[6] |PDWKIF |Power-Down Mode Wake-Up Interrupt Status
- * | | |Set by "power-down wake-up event", it indicates that resume from Power-down mode"
- * | | |The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD, RTC or SDHOST wake-up occurred
- * | | |Note1: Write 1 to clear the bit to 0.
- * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
- * |[7] |PDEN |System Power-Down Enable Control (Write Protect)
- * | | |When this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PDEN bit.
- * | | |(a) If the PDEN is 0, then the chip enters Power-down mode immediately after
- * | | |the PWR_DOWN_EN bit set. ( default)
- * | | |(b) if the PDEN is 1, then the chip keeps active till the CPU sleep mode is also
- * | | |active and then the chip enters Power-down mode
- * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set
- * | | |this bit again for next power-down.
- * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but the LXT and
- * | | |LIRC are not controlled by Power-down mode.
- * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock
- * | | |source selection. The clocks of peripheral are not controlled by Power-down mode, if the
- * | | |peripheral clock source is from LXT or the LIRC.
- * | | |0 = Chip operating normally or chip in idle mode by WFI command.
- * | | |1 = Chip enters Power-down mode instant or waits CPU sleep command WFI.
- * |[8] |PDWTCPU |This Bit Control The Power-Down Entry Condition (Write Protect)
- * | | |0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1.
- * | | |1 = Chip enters Power-down mode when the both PDEN and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction.
- * |[9] |DBPDEN |Chip Entering Power-Down Even ICE Connected
- * | | |0 = Chip enters power-down disabled in Debug mode.
- * | | |1 = Chip enters power-down enabled in Debug mode.
- */
- __IO uint32_t PWRCTL;
-
- /**
- * AHBCLK
- * ===================================================================================================
- * Offset: 0x04 AHB Devices Clock Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |PDMACKEN |PDMA Controller Clock Enable Control
- * | | |0 = PDMA engine clock Disabled.
- * | | |1 = PDMA engine clock Enabled.
- * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Control
- * | | |0 = Flash ISP engine clock Disabled.
- * | | |1 = Flash ISP engine clock Enabled.
- * |[3] |EBICKEN |EBI Controller Clock Enable Control
- * | | |0 = EBI engine clock Disabled.
- * | | |1 = EBI engine clock Enabled.
- * |[4] |USBHCKEN |USB HOST Controller Clock Enable Control
- * | | |0 = USB HOST engine clock Disabled.
- * | | |1 = USB HOST engine clock Enabled.
- * |[5] |EMACCKEN |Ethernet Controller Clock Enable Control (NUC472 Only)
- * | | |0 = Ethernet Controller engine clock Disabled.
- * | | |1 = Ethernet Controller engine clock Enabled.
- * |[6] |SDHCKEN |SDHOST Controller Clock Enable Control
- * | | |0 = SDHOST engine clock Disabled.
- * | | |1 = SDHOST engine clock Enabled.
- * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Control
- * | | |0 = CRC engine clock Disabled.
- * | | |1 = CRC engine clock Enabled.
- * |[8] |CAPCKEN |Image Capture Interface Controller Clock Enable Control
- * | | |0 = CAP controller's clock Disabled.
- * | | |1 = CAP controller's clock Enabled.
- * |[9] |SENCKEN |Sensor Clock Enable Control
- * | | |0 = Sensor clock Disabled.
- * | | |1 = Sensor clock Enabled.
- * |[10] |USBDCKEN |USB 2.0 Device Clock Enable Control
- * | | |0 = USB device controller's clock Disabled.
- * | | |1 = USB device controller's clock Enabled.
- * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Control
- * | | |0 = Cryptographic Accelerator clock Disabled.
- * | | |1 = Cryptographic Accelerator clock Enabled.
- */
- __IO uint32_t AHBCLK;
-
- /**
- * APBCLK0
- * ===================================================================================================
- * Offset: 0x08 APB Devices Clock Enable Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WDTCKEN |Watchdog Timer Clock Enable Control (Write Protect)
- * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |0 = Watchdog Timer Clock Disabled.
- * | | |1 = Watchdog Timer Clock Enabled.
- * |[1] |RTCCKEN |Real-Time-Clock APB Interface Clock Enable Control
- * | | |This bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32.768 kHz external low-speed crystal.
- * | | |0 = RTC Clock Disabled.
- * | | |1 = RTC Clock Enabled.
- * |[2] |TMR0CKEN |Timer0 Clock Enable Control
- * | | |0 = Timer0 Clock Disabled.
- * | | |1 = Timer0 Clock Enabled.
- * |[3] |TMR1CKEN |Timer1 Clock Enable Control
- * | | |0 = Timer1 Clock Disabled.
- * | | |1 = Timer1 Clock Enabled.
- * |[4] |TMR2CKEN |Timer2 Clock Enable Control
- * | | |0 = Timer2 Clock Disabled.
- * | | |1 = Timer2 Clock Enabled.
- * |[5] |TMR3CKEN |Timer3 Clock Enable Control
- * | | |0 = Timer3 Clock Disabled.
- * | | |1 = Timer3 Clock Enabled.
- * |[6] |CLKOCKEN |Clock Output Enable Control
- * | | |0 = Clock Output Disabled.
- * | | |1 = Clock Output Enabled.
- * |[7] |ACMPCKEN |Analog Comparator Clock Enable Control
- * | | |0 = Analog Comparator Clock Disabled.
- * | | |1 = Analog Comparator Clock Enabled.
- * |[8] |I2C0CKEN |I2C0 Clock Enable Control
- * | | |0 = I2C0 Clock Disabled.
- * | | |1 = I2C0 Clock Enabled.
- * |[9] |I2C1CKEN |I2C1 Clock Enable Control
- * | | |0 = I2C1 Clock Disabled.
- * | | |1 = I2C1 Clock Enabled.
- * |[10] |I2C2CKEN |I2C2 Clock Enable Control
- * | | |0 = I2C2 Clock Disabled.
- * | | |1 = I2C2 Clock Enabled.
- * |[11] |I2C3CKEN |I2C3 Clock Enable Control
- * | | |0 = I2C3 Clock Disabled.
- * | | |1 = I2C3 Clock Enabled.
- * |[12] |SPI0CKEN |SPI0 Clock Enable Control
- * | | |0 = SPI0 Clock Disabled.
- * | | |1= SPI0 Clock Enabled.
- * |[13] |SPI1CKEN |SPI1 Clock Enable Control
- * | | |0 = SPI1 Clock Disabled.
- * | | |1 = SPI1 Clock Enabled.
- * |[14] |SPI2CKEN |SPI2 Clock Enable Control
- * | | |0 = SPI2 Clock Disabled.
- * | | |1 = SPI2 Clock Enabled.
- * |[15] |SPI3CKEN |SPI3 Clock Enable Control
- * | | |0 = SPI3 Clock Disabled.
- * | | |1 = SPI3 Clock Enabled.
- * |[16] |UART0CKEN |UART0 Clock Enable Control
- * | | |0 = UART0 clock Disabled.
- * | | |1 = UART0 clock Enabled.
- * |[17] |UART1CKEN |UART1 Clock Enable Control
- * | | |0 = UART1 clock Disabled.
- * | | |1 = UART1 clock Enabled.
- * |[18] |UART2CKEN |UART2 Clock Enable Control
- * | | |0 = UART2 clock Disabled.
- * | | |1 = UART2 clock Enabled.
- * |[19] |UART3CKEN |UART3 Clock Enable Control
- * | | |0 = UART3 clock Disabled.
- * | | |1 = UART3 clock Enabled.
- * |[20] |UART4CKEN |UART4 Clock Enable Control
- * | | |0 = UART4 clock Disabled.
- * | | |1 = UART4 clock Enabled.
- * |[21] |UART5CKEN |UART5 Clock Enable Control
- * | | |0 = UART5 clock Disabled.
- * | | |1 = UART5 clock Enabled.
- * |[24] |CAN0CKEN |CAN Bus Controller-0 Clock Enable Control
- * | | |0 = CAN0 clock Disabled.
- * | | |1 = CAN0 clock Enabled.
- * |[25] |CAN1CKEN |CAN Bus Controller-1 Clock Enable Control
- * | | |0 = CAN1 clock Disabled.
- * | | |1 = CAN1 clock Enabled.
- * |[26] |OTGCKEN |USB 2.0 OTG Device Controller Clock Enable Control
- * | | |0 = OTG clock Disabled.
- * | | |1 = OTG clock Enabled.
- * |[28] |ADCCKEN |Analog-Digital-Converter (ADC) Clock Enable Control
- * | | |0 = ADC clock Disabled.
- * | | |1 = ADC clock Enabled.
- * |[29] |I2S0CKEN |I2S0 Clock Enable Control
- * | | |0 = I2S Clock Disabled.
- * | | |1 = I2S Clock Enabled.
- * |[30] |I2S1CKEN |I2S1 Clock Enable Control
- * | | |0 = I2S1 Clock Disabled.
- * | | |1 = I2S1 Clock Enabled.
- * |[31] |PS2CKEN |PS/2 Clock Enable Control
- * | | |0 = PS/2 clock Disabled.
- * | | |1 = PS/2 clock Enabled.
- */
- __IO uint32_t APBCLK0;
-
- /**
- * APBCLK1
- * ===================================================================================================
- * Offset: 0x0C APB Devices Clock Enable Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SC0CKEN |SC0 Clock Enable Control
- * | | |0 = SC0 Clock Disabled.
- * | | |1 = SC0 Clock Enabled.
- * |[1] |SC1CKEN |SC1 Clock Enable Control
- * | | |0 = SC1 Clock Disabled.
- * | | |1 = SC1 Clock Enabled.
- * |[2] |SC2CKEN |SC2 Clock Enable Control
- * | | |0 = SC2 Clock Disabled.
- * | | |1 = SC2 Clock Enabled.
- * |[3] |SC3CKEN |SC3 Clock Enable Control
- * | | |0 = SC3 Clock Disabled.
- * | | |1 = SC3 Clock Enabled.
- * |[4] |SC4CKEN |SC4 Clock Enable Control
- * | | |0 = SC4 Clock Disabled.
- * | | |1 = SC4 Clock Enabled.
- * |[5] |SC5CKEN |SC5 Clock Enable Control
- * | | |0 = SC5 Clock Disabled.
- * | | |1 = SC5 Clock Enabled.
- * |[8] |I2C4CKEN |I2C4 Clock Enable Control
- * | | |0 = I2C4 Clock Disabled.
- * | | |1 = I2C4 Clock Enabled.
- * |[16] |PWM0CH01CKEN|PWM0_01 Clock Enable Control
- * | | |0 = PWM0_01 Clock Disabled.
- * | | |1 = PWM0_01 Clock Enabled.
- * |[17] |PWM0CH23CKEN|PWM0_23 Clock Enable Control
- * | | |0 = PWM0_23 Clock Disabled.
- * | | |1 = PWM0_23 Clock Enabled.
- * |[18] |PWM0CH45CKEN|PWM0_45 Clock Enable Control
- * | | |0 = PWM0_45 Clock Disabled.
- * | | |1 = PWM0_45 Clock Enabled.
- * |[19] |PWM1CH01CKEN|PWM1_01 Clock Enable Control
- * | | |0 = PWM1_01 Clock Disabled.
- * | | |1 = PWM1_01 Clock Enabled.
- * |[20] |PWM1CH23CKEN|PWM1_23 Clock Enable Control
- * | | |0 = PWM1_23 Clock Disabled.
- * | | |1 = PWM1_23 Clock Enabled.
- * |[21] |PWM1CH45CKEN|PWM1_45 Clock Enable Control
- * | | |0 = PWM1_45 Clock Disabled.
- * | | |1 = PWM1_45 Clock Enabled.
- * |[22] |QEI0CKEN |Quadrature Encoder Interface (QEI0) Clock Enable Control
- * | | |0 = QEI0 clock Disabled.
- * | | |1 = QEI0 clock Enabled.
- * |[23] |QEI1CKEN |Quadrature Encoder Interface (QEI1) Clock Enable Control
- * | | |0 = QEI1 clock Disabled.
- * | | |1 = QEI1 clock Enabled.
- * |[26] |ECAP0CKEN |Enhance CAP (ECAP0) Clock Enable Control
- * | | |0 = ECAP0 clock Disabled.
- * | | |1 = ECAP0 clock Enabled.
- * |[27] |ECAP1CKEN |Enhance CAP (ECAP1) Clock Enable Control
- * | | |0 = ECAP1 clock Disabled.
- * | | |1 = ECAP1 clock Enabled.
- * |[28] |EPWM0CKEN |Enhance PWM0 (EPWM) Clock Enable Control
- * | | |0 = EPWM0 clock Disabled.
- * | | |1 = EPWM0 clock Enabled.
- * |[29] |EPWM1CKEN |Enhance PWM1 (EPWM) Clock Enable Control
- * | | |0 = EPWM1 clock Disabled.
- * | | |1 = EPWM1 clock Enabled.
- * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Control
- * | | |0 = OPA clock Disabled.
- * | | |1 = OPA clock Enabled.
- * |[31] |EADCCKEN |Enhance Analog-Digital-Converter (E ADC) Clock Enable Control
- * | | |0 = EADC clock Disabled.
- * | | |1 = EADC clock Enabled.
- */
- __IO uint32_t APBCLK1;
-
- /**
- * CLKSEL0
- * ===================================================================================================
- * Offset: 0x10 Clock Source Select Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
- * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on
- * | | |1.
- * | | |The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset.
- * | | |Therefore the default value is either 000b or 111b.
- * | | |2.
- * | | |These bits are protected bit, it means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PLL clock.
- * | | |011 = Clock source from LIRC clock.
- * | | |100 = Clock source from PLL2 clock.
- * | | |111 = Clock source from HIRC clock.
- * | | |Other = Reserved.
- * |[3:5] |STCLKSEL |Cortex(TM)-M4 SysTick Clock Source Selection (Write Protect)
- * | | |If SYST_CSR[2]=0, SysTick uses listed clock source below.
- * | | |These bits are protected bit.
- * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from HXT clock/2.
- * | | |011 = Clock source from HCLK/2.
- * | | |111 = Clock source from HIRC clock/2.
- * |[6] |PCLKSEL |PCLK Clock Source Selection (Write Protect)
- * | | |These bits are protected bit.
- * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |0 = Clock source from HCLK.
- * | | |1 = Clock source from HCLK/2.
- * |[8] |USBHSEL |USB Host Clock Source Selection (Write Protect)
- * | | |These bits are protected bit.
- * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |0 = Clock source from PLL2.
- * | | |1 = Clock source from PLL.
- * |[16:17] |CAPSEL |Image Capture Interface Clock Source Selection
- * | | |These bits are protected bit.
- * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from HCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[20:21] |SDHSEL |SDHOST Engine Clock Source Selection
- * | | |These bits are protected bit.
- * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from HCLK.
- * | | |11 = Clock source from HIRC clock.
- */
- __IO uint32_t CLKSEL0;
-
- /**
- * CLKSEL1
- * ===================================================================================================
- * Offset: 0x14 Clock Source Select Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
- * | | |These bits are protected bit,and programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- * | | |00 = Clock source from 4~24 MHz external high-speed crystal clock.
- * | | |01 = Clock source from LXT clock.
- * | | |10 = Clock source from HCLK/2048 clock.
- * | | |11 = Clock source from LIRC clock.
- * |[2:3] |EADCSEL |ADC Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[4] |SPI0SEL |SPI0 Clock Source Selection
- * | | |0 = Clock source from PLL clock.
- * | | |1 = Clock source from PCLK.
- * |[5] |SPI1SEL |SPI1 Clock Source Selection
- * | | |0 = Clock source from PLL clock.
- * | | |1 = Clock source from PCLK.
- * |[6] |SPI2SEL |SPI2 Clock Source Selection
- * | | |0 = Clock source from PLL clock.
- * | | |1 = Clock source from PCLK.
- * |[7] |SPI3SEL |SPI3 Clock Source Selection
- * | | |0 = Clock source from PLL clock.
- * | | |1 = Clock source from PCLK.
- * |[8:10] |TMR0SEL |TIMER0 Clock Source Selection
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from external trigger.
- * | | |101 = Clock source from LIRC clock.
- * | | |111 = Clock source from HIRC clock.
- * | | |Others = reserved.
- * |[12:14] |TMR1SEL |TIMER1 Clock Source Selection
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from external trigger.
- * | | |101 = Clock source from LIRC clock.
- * | | |111 = Clock source from HIRC clock.
- * | | |Others = reserved.
- * |[16:18] |TMR2SEL |TIMER2 Clock Source Selection
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from external trigger.
- * | | |101 = Clock source from LIRC clock.
- * | | |111 = Clock source from HIRC clock.
- * | | |Others = reserved.
- * |[20:22] |TMR3SEL |TIMER3 Clock Source Selection
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from external trigger.
- * | | |101 = Clock source from LIRC clock.
- * | | |111 = Clock source from HIRC clock.
- * | | |Others = reserved.
- * |[24:25] |UARTSEL |UART Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10/11 = Clock source from HIRC clock.
- * |[28:29] |CLKOSEL |Clock Divider Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from LXT clock.
- * | | |10 = Clock source from HCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[30:31] |WWDTSEL |Window Watchdog Timer Clock Source Selection
- * | | |00 = Reserved.
- * | | |01 = Reserved.
- * | | |10 = Clock source from HCLK/2048 clock.
- * | | |11 = Clock source from LIRC clock.
- */
- __IO uint32_t CLKSEL1;
-
- /**
- * CLKSEL2
- * ===================================================================================================
- * Offset: 0x18 Clock Source Select Control Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |PWM0CH01SEL|PWM0_0 And PWM0_1 Clock Source Selection
- * | | |PWM0_0 and PWM0_1 uses the same Engine clock source, both of them use the same prescaler.
- * | | |The Engine clock source of PWM0_0 and PWM0_1 is defined by PWM0CH01SEL[2:0].
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from HIRC clock.
- * | | |100 = Clock source from LIRC clock.
- * | | |Other = Reserved.
- * |[4:6] |PPWM0CH23SEL|PWM0_2 And PWM0_3 Clock Source Selection
- * | | |PWM0_2 and PWM0_3 uses the same Engine clock source, both of them use the same prescaler.
- * | | |The Engine clock source of PWM0_2 and PWM0_3 is defined by PPWM0CH23SEL[2:0].
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from HIRC clock.
- * | | |100 = Clock source from LIRC clock.
- * | | |Other = Reserved.
- * |[8:10] |PWM0CH45SEL|PWM0_4 And PWM0_5 Clock Source Selection
- * | | |PWM0_4 and PWM0_5 used the same Engine clock source; both of them use the same prescaler.
- * | | |The Engine clock source of PWM0_4 and PWM0_5 is defined by PWM0CH45SEL[2:0].
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from HIRC clock.
- * | | |100 = Clock source from LIRC clock.
- * | | |Other = Reserved.
- * |[12:14] |PWM1CH01SEL|PWM1_0 And PWM1_1 Clock Source Selection
- * | | |PWM1_0 and PWM1_1 uses the same Engine clock source, both of them use the same prescaler.
- * | | |The Engine clock source of PWM1_0 and PWM1_1 is defined by PWM1CH01SEL[2:0].
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from HIRC clock.
- * | | |100 = Clock source from LIRC clock.
- * | | |Other = Reserved.
- * |[16:18] |PWM1CH23SEL|PWM1_2 And PWM1_3 Clock Source Selection
- * | | |PWM1_2 and PWM1_3 uses the same Engine clock source, both of them use the same prescaler.
- * | | |The Engine clock source of PWM1_2 and PWM1_3 is defined by PWM1CH23SEL[2:0].
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from HIRC clock.
- * | | |100= Clock source from LIRC clock.
- * | | |Other = Reserved.
- * |[20:22] |PWM1CH45SEL|PWM1_4 And PWM1_5 Clock Source Selection
- * | | |PWM1_4 and PWM1_5 used the same Engine clock source; both of them use the same prescaler.
- * | | |The Engine clock source of PWM1_4 and PWM1_5 is defined by PWM1CH45SEL[2:0].
- * | | |000 = Clock source from HXT clock.
- * | | |001 = Clock source from LXT clock.
- * | | |010 = Clock source from PCLK.
- * | | |011 = Clock source from HIRC clock.
- * | | |100 = Clock source from LIRC clock.
- * | | |Other = Reserved.
- */
- __IO uint32_t CLKSEL2;
-
- /**
- * CLKSEL3
- * ===================================================================================================
- * Offset: 0x1C Clock Source Select Control Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |SC0SEL |SC0 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[2:3] |SC1SEL |SC1 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[4:5] |SC2SEL |SC2 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[6:7] |SC3SEL |SC3 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[8:9] |SC4SEL |SC4 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[10:11] |SC5SEL |SC5 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[16:17] |I2S0SEL |I2S0 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from PCLK.
- * | | |11 = Clock source from HIRC clock.
- * |[18:19] |I2S1SEL |I2S1 Clock Source Selection
- * | | |00 = Clock source from HXT clock.
- * | | |01 = Clock source from PLL clock.
- * | | |10 = Clock source from PCLK.
- * | | |11 = Clock source from HIRC clock.
- */
- __IO uint32_t CLKSEL3;
-
- /**
- * CLKDIV0
- * ===================================================================================================
- * Offset: 0x20 Clock Divider Number Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
- * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
- * |[4:7] |USBHDIV |USB Host Clock Divide Number From PLL Clock
- * | | |USB Host clock frequency = (PLL frequency) / (USBHDIV + 1).
- * |[8:11] |UARTDIV |UART Clock Divide Number From UART Clock Source
- * | | |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
- * |[16:23] |ADCDIV |ADC Clock Divide Number From ADC Clock Source
- * | | |ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1).
- * |[24:31] |SDHDIV |SDHOST Clock Divide Number From SDHOST Clock Source
- * | | |SDHOST clock frequency = (SDHOST clock source frequency) / (SDHDIV + 1).
- */
- __IO uint32_t CLKDIV0;
-
- /**
- * CLKDIV1
- * ===================================================================================================
- * Offset: 0x24 Clock Divider Number Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
- * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV+ 1).
- * |[8:15] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source
- * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
- * |[16:23] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source
- * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
- * |[24:31] |SC3DIV |SC3 Clock Divide Number From SC3 Clock Source
- * | | |SC3 clock frequency = (SC3 clock source frequency ) / (SC3DIV+ 1).
- */
- __IO uint32_t CLKDIV1;
-
- /**
- * CLKDIV2
- * ===================================================================================================
- * Offset: 0x28 Clock Divider Number Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SC4DIV |SC4 Clock Divide Number From SC4 Clock Source
- * | | |SC4 clock frequency = (SC4 clock source frequency ) / (SC4DIV + 1).
- * |[8:15] |SC5DIV |SC5 Clock Divide Number From SC5 Clock Source
- * | | |SC5 clock frequency = (SC5 clock source frequency ) / (SC5DIV + 1).
- */
- __IO uint32_t CLKDIV2;
-
- /**
- * CLKDIV3
- * ===================================================================================================
- * Offset: 0x2C Clock Divider Number Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |CAPDIV |Image Capture Seneor Clock Divide Number From ICAP Clock Source
- * | | |Image sensor clock frequency = (ICAP clock source frequency) / (ICAPDIV + 1).
- * |[8:15] |VSENSEDIV |Video Pixel Clock Divide Number From ICAP Clock Source
- * | | |Video pixel clock frequency = (ICAP clock source frequency) / (VSENSEDIV + 1).
- * |[16:23] |EMACDIV |Ethernet Clock Divide Number Form HCLK (NUC472 Only)
- * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
- */
- __IO uint32_t CLKDIV3;
- uint32_t RESERVE0[4];
-
-
- /**
- * PLLCTL
- * ===================================================================================================
- * Offset: 0x40 PLL Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:8] |FBDIV |PLL Feedback Divider Control Pins
- * | | |Refer to the formulas below the table.
- * |[9:13] |INDIV |PLL Input Divider Control Pins
- * | | |Refer to the formulas below the table.
- * |[14:15] |OUTDV |PLL Output Divider Control Pins
- * | | |Refer to the formulas below the table.
- * |[16] |PD |Power-Down Mode
- * | | |If set the PWR_DOWN_EN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
- * | | |0 = PLL is in normal mode.
- * | | |1 = PLL is in Power-down mode (default).
- * |[17] |BP |PLL Bypass Control
- * | | |0 = PLL is in normal mode (default).
- * | | |1 = PLL clock output is same as clock input (XTALin).
- * |[18] |OE |PLL OE (FOUT Enable) Pin Control
- * | | |0 = PLL FOUT Enabled.
- * | | |1 = PLL FOUT is fixed low.
- * |[19] |PLLSRC |PLL Source Clock Selection
- * | | |0 = PLL source clock from HXT.
- * | | |1 = PLL source clock from HIRC.
- * |[20] |PLLREMAP |PLL Remap Enable Bit
- * | | |0 = PLL remap enable.
- * | | |1 = PLL remap disable.
- */
- __IO uint32_t PLLCTL;
-
- /**
- * PLL2CTL
- * ===================================================================================================
- * Offset: 0x44 PLL2 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |PLL2DIV |PLL2 Divider Control
- * | | |PLL2 clock frequency = (480 MHz) / 2 / (PLL2DIV + 1).
- * | | |Note: Max. PLL frequency 240 MHz when XTL12M.
- * |[8] |PLL2CKEN |USB OHY 480 MHz Enable Control
- * | | |This bit enables USB PHY PLL (480 MHz), and user needs to care extend 12 MHz source.
- * | | |0 = USB PHY PLL (480 MHz) Disabled.
- * | | |1 = USB PHY PLL (480 MHz) Enabled.
- */
- __IO uint32_t PLL2CTL;
- uint32_t RESERVE1[2];
-
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x50 Clock Status Monitor Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HXTSTB |4~24 MHz External High-Speed Crystal Clock(HXT) Source Stable Flag
- * | | |0 = HXT clock is not stable or disabled.
- * | | |1 = HXT clock is stable.
- * | | |Note: This bit is read only.
- * |[1] |LXTSTB |32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag
- * | | |0 = LXT clock is not stable or disabled.
- * | | |1 = LXT clock is stabled.
- * | | |Note: This is read only.
- * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag
- * | | |0 = Internal PLL clock is not stable or disabled.
- * | | |1 = Internal PLL clock is stable.
- * | | |Note: This bit is read only.
- * |[3] |LIRCSTB |10 KHz Internal Low-Speed Oscillator Clock (LIRC)Source Stable Flag
- * | | |0 = LIRC clock is not stable or disabled.
- * | | |1 = LIRC clock is stable.
- * | | |Note: This bit is read only.
- * |[4] |HIRCSTB |22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Clock Source Stable Flag
- * | | |0 = HIRC clock is not stable or disabled.
- * | | |1 = HIRC clock is stable.
- * | | |Note: This bit is read only.
- * |[5] |PLL2STB |Internal PLL2 Clock Source Stable Flag
- * | | |0 = Internal PLL2 clock is not stable or disabled.
- * | | |1 = Internal PLL2 clock is stable.
- * | | |Note: This bit is read only.
- * |[7] |CLKSFAIL |Clock Switching Fail Flag
- * | | |0 = Clock switching success.
- * | | |1 = Clock switching failure.
- * | | |Note1: This bit is updated when software switches system clock source.
- * | | |If switch target clock is stable, this bit will be set to 0.
- * | | |If switch target clock is not stable, this bit will be set to 1.
- * | | |Note2: Write 1 to clear the bit to 0.
- */
- __IO uint32_t STATUS;
- uint32_t RESERVE2[3];
-
-
- /**
- * CLKOCTL
- * ===================================================================================================
- * Offset: 0x60 Frequency Divider Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |FSEL |Divider Output Frequency Selection
- * | | |The formula of output frequency is:
- * | | |Fout = Fin/2(N+1).
- * | | |Fin is the input clock frequency.
- * | | |Fout is the frequency of divider output clock.
- * | | |N is the 4-bit value of FSEL[3:0].
- * |[4] |CLKOEN |Clock Output Enable Control
- * | | |0 = Clock Output disabled.
- * | | |1 = Clock Output enabled.
- * |[5] |DIV1EN |Frequency Divider 1 Enable Control
- * | | |0 = Divider output frequency is dependent on FSEL value when FDIVEN is enabled.
- * | | |1 = Divider output frequency is input clock frequency.
- */
- __IO uint32_t CLKOCTL;
- uint32_t RESERVE3[3];
-
-
- /**
- * CLKDCTL
- * ===================================================================================================
- * Offset: 0x70 Clock Fail Detector Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SYSFDEN |System Clock Detector Enable Control
- * | | |0 = system clock fail interrupt disabled.
- * | | |1 = system clock fail interrupt enabled.
- * |[1] |SYSFIEN |System Clock Detector Interrupt Enable Control
- * | | |0 = system clock fail interrupt disabled.
- * | | |1 = system clock fail interrupt enabled.
- * |[2] |SYSFIF |System Clock Detect Fail Flag
- * | | |0 = System clock normal.
- * | | |1 = System clock abnormal (write " 1" to clear).
- * |[8] |IRCDEN |Internal RC Clock Detector Enable Control
- * | | |0 = IRC clock fail interrupt disabled.
- * | | |1 = IRC clock fail interrupt enabled.
- * |[9] |IRCFIEN |Internal RC Clock Detector Interrupt Enable Control
- * | | |0 = IRC clock fail interrupt disabled.
- * | | |1 = IRC clock fail interrupt enabled.
- * |[10] |IRCFIF |Internal RC Clock Fail Flag
- * | | |0 = IRC clock normal.
- * | | |1 = IRC abnormal (write "1" to clear) .
- */
- __IO uint32_t CLKDCTL;
-
-} CLK_T;
-
-/**
- @addtogroup CLK_CONST CLK Bit Field Definition
- Constant Definitions for CLK Controller
-@{ */
-
-#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK PWRCTL: HXTEN Position */
-#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK PWRCTL: HXTEN Mask */
-
-#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK PWRCTL: LXTEN Position */
-#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK PWRCTL: LXTEN Mask */
-
-#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK PWRCTL: HIRCEN Position */
-#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK PWRCTL: HIRCEN Mask */
-
-#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK PWRCTL: LIRCEN Position */
-#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK PWRCTL: LIRCEN Mask */
-
-#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK PWRCTL: PDWKDLY Position */
-#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK PWRCTL: PDWKDLY Mask */
-
-#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK PWRCTL: PDWKIEN Position */
-#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK PWRCTL: PDWKIEN Mask */
-
-#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK PWRCTL: PDWKIF Position */
-#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK PWRCTL: PDWKIF Mask */
-
-#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK PWRCTL: PDEN Position */
-#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK PWRCTL: PDEN Mask */
-
-#define CLK_PWRCTL_PDWTCPU_Pos (8) /*!< CLK PWRCTL: PDWTCPU Position */
-#define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /*!< CLK PWRCTL: PDWTCPU Mask */
-
-#define CLK_PWRCTL_DBPDEN_Pos (9) /*!< CLK PWRCTL: DBPDEN Position */
-#define CLK_PWRCTL_DBPDEN_Msk (0x1ul << CLK_PWRCTL_DBPDEN_Pos) /*!< CLK PWRCTL: DBPDEN Mask */
-
-#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK AHBCLK: PDMACKEN Position */
-#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK AHBCLK: PDMACKEN Mask */
-
-#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK AHBCLK: ISPCKEN Position */
-#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK AHBCLK: ISPCKEN Mask */
-
-#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK AHBCLK: EBICKEN Position */
-#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK AHBCLK: EBICKEN Mask */
-
-#define CLK_AHBCLK_USBHCKEN_Pos (4) /*!< CLK AHBCLK: USBHCKEN Position */
-#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK AHBCLK: USBHCKEN Mask */
-
-#define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK AHBCLK: EMACCKEN Position */
-#define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK AHBCLK: EMACCKEN Mask */
-
-#define CLK_AHBCLK_SDHCKEN_Pos (6) /*!< CLK AHBCLK: SDHCKEN Position */
-#define CLK_AHBCLK_SDHCKEN_Msk (0x1ul << CLK_AHBCLK_SDHCKEN_Pos) /*!< CLK AHBCLK: SDHCKEN Mask */
-
-#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK AHBCLK: CRCCKEN Position */
-#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK AHBCLK: CRCCKEN Mask */
-
-#define CLK_AHBCLK_CAPCKEN_Pos (8) /*!< CLK AHBCLK: CAPCKEN Position */
-#define CLK_AHBCLK_CAPCKEN_Msk (0x1ul << CLK_AHBCLK_CAPCKEN_Pos) /*!< CLK AHBCLK: CAPCKEN Mask */
-
-#define CLK_AHBCLK_SENCKEN_Pos (9) /*!< CLK AHBCLK: SENCKEN Position */
-#define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) /*!< CLK AHBCLK: SENCKEN Mask */
-
-#define CLK_AHBCLK_USBDCKEN_Pos (10) /*!< CLK AHBCLK: USBDCKEN Position */
-#define CLK_AHBCLK_USBDCKEN_Msk (0x1ul << CLK_AHBCLK_USBDCKEN_Pos) /*!< CLK AHBCLK: USBDCKEN Mask */
-
-#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK AHBCLK: CRPTCKEN Position */
-#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK AHBCLK: CRPTCKEN Mask */
-
-#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK APBCLK0: WDTCKEN Position */
-#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK APBCLK0: WDTCKEN Mask */
-
-#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK APBCLK0: RTCCKEN Position */
-#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK APBCLK0: RTCCKEN Mask */
-
-#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK APBCLK0: TMR0CKEN Position */
-#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK APBCLK0: TMR0CKEN Mask */
-
-#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK APBCLK0: TMR1CKEN Position */
-#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK APBCLK0: TMR1CKEN Mask */
-
-#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK APBCLK0: TMR2CKEN Position */
-#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK APBCLK0: TMR2CKEN Mask */
-
-#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK APBCLK0: TMR3CKEN Position */
-#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK APBCLK0: TMR3CKEN Mask */
-
-#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK APBCLK0: CLKOCKEN Position */
-#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK APBCLK0: CLKOCKEN Mask */
-
-#define CLK_APBCLK0_ACMPCKEN_Pos (7) /*!< CLK APBCLK0: ACMPCKEN Position */
-#define CLK_APBCLK0_ACMPCKEN_Msk (0x1ul << CLK_APBCLK0_ACMPCKEN_Pos) /*!< CLK APBCLK0: ACMPCKEN Mask */
-
-#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK APBCLK0: I2C0CKEN Position */
-#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK APBCLK0: I2C0CKEN Mask */
-
-#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK APBCLK0: I2C1CKEN Position */
-#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK APBCLK0: I2C1CKEN Mask */
-
-#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK APBCLK0: I2C2CKEN Position */
-#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK APBCLK0: I2C2CKEN Mask */
-
-#define CLK_APBCLK0_I2C3CKEN_Pos (11) /*!< CLK APBCLK0: I2C3CKEN Position */
-#define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) /*!< CLK APBCLK0: I2C3CKEN Mask */
-
-#define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK APBCLK0: SPI0CKEN Position */
-#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK APBCLK0: SPI0CKEN Mask */
-
-#define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK APBCLK0: SPI1CKEN Position */
-#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK APBCLK0: SPI1CKEN Mask */
-
-#define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK APBCLK0: SPI2CKEN Position */
-#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK APBCLK0: SPI2CKEN Mask */
-
-#define CLK_APBCLK0_SPI3CKEN_Pos (15) /*!< CLK APBCLK0: SPI3CKEN Position */
-#define CLK_APBCLK0_SPI3CKEN_Msk (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos) /*!< CLK APBCLK0: SPI3CKEN Mask */
-
-#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK APBCLK0: UART0CKEN Position */
-#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK APBCLK0: UART0CKEN Mask */
-
-#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK APBCLK0: UART1CKEN Position */
-#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK APBCLK0: UART1CKEN Mask */
-
-#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK APBCLK0: UART2CKEN Position */
-#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK APBCLK0: UART2CKEN Mask */
-
-#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK APBCLK0: UART3CKEN Position */
-#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK APBCLK0: UART3CKEN Mask */
-
-#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK APBCLK0: UART4CKEN Position */
-#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK APBCLK0: UART4CKEN Mask */
-
-#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK APBCLK0: UART5CKEN Position */
-#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK APBCLK0: UART5CKEN Mask */
-
-#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK APBCLK0: CAN0CKEN Position */
-#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK APBCLK0: CAN0CKEN Mask */
-
-#define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK APBCLK0: CAN1CKEN Position */
-#define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK APBCLK0: CAN1CKEN Mask */
-
-#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK APBCLK0: OTGCKEN Position */
-#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK APBCLK0: OTGCKEN Mask */
-
-#define CLK_APBCLK0_ADCCKEN_Pos (28) /*!< CLK APBCLK0: ADCCKEN Position */
-#define CLK_APBCLK0_ADCCKEN_Msk (0x1ul << CLK_APBCLK0_ADCCKEN_Pos) /*!< CLK APBCLK0: ADCCKEN Mask */
-
-#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK APBCLK0: I2S0CKEN Position */
-#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK APBCLK0: I2S0CKEN Mask */
-
-#define CLK_APBCLK0_I2S1CKEN_Pos (30) /*!< CLK APBCLK0: I2S1CKEN Position */
-#define CLK_APBCLK0_I2S1CKEN_Msk (0x1ul << CLK_APBCLK0_I2S1CKEN_Pos) /*!< CLK APBCLK0: I2S1CKEN Mask */
-
-#define CLK_APBCLK0_PS2CKEN_Pos (31) /*!< CLK APBCLK0: PS2CKEN Position */
-#define CLK_APBCLK0_PS2CKEN_Msk (0x1ul << CLK_APBCLK0_PS2CKEN_Pos) /*!< CLK APBCLK0: PS2CKEN Mask */
-
-#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK APBCLK1: SC0CKEN Position */
-#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK APBCLK1: SC0CKEN Mask */
-
-#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK APBCLK1: SC1CKEN Position */
-#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK APBCLK1: SC1CKEN Mask */
-
-#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK APBCLK1: SC2CKEN Position */
-#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK APBCLK1: SC2CKEN Mask */
-
-#define CLK_APBCLK1_SC3CKEN_Pos (3) /*!< CLK APBCLK1: SC3CKEN Position */
-#define CLK_APBCLK1_SC3CKEN_Msk (0x1ul << CLK_APBCLK1_SC3CKEN_Pos) /*!< CLK APBCLK1: SC3CKEN Mask */
-
-#define CLK_APBCLK1_SC4CKEN_Pos (4) /*!< CLK APBCLK1: SC4CKEN Position */
-#define CLK_APBCLK1_SC4CKEN_Msk (0x1ul << CLK_APBCLK1_SC4CKEN_Pos) /*!< CLK APBCLK1: SC4CKEN Mask */
-
-#define CLK_APBCLK1_SC5CKEN_Pos (5) /*!< CLK APBCLK1: SC5CKEN Position */
-#define CLK_APBCLK1_SC5CKEN_Msk (0x1ul << CLK_APBCLK1_SC5CKEN_Pos) /*!< CLK APBCLK1: SC5CKEN Mask */
-
-#define CLK_APBCLK1_I2C4CKEN_Pos (8) /*!< CLK APBCLK1: I2C4CKEN Position */
-#define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) /*!< CLK APBCLK1: I2C4CKEN Mask */
-
-#define CLK_APBCLK1_PWM0CH01CKEN_Pos (16) /*!< CLK APBCLK1: PWM0CH01CKEN Position */
-#define CLK_APBCLK1_PWM0CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH01CKEN_Pos) /*!< CLK APBCLK1: PWM0CH01CKEN Mask */
-
-#define CLK_APBCLK1_PWM0CH23CKEN_Pos (17) /*!< CLK APBCLK1: PWM0CH23CKEN Position */
-#define CLK_APBCLK1_PWM0CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH23CKEN_Pos) /*!< CLK APBCLK1: PWM0CH23CKEN Mask */
-
-#define CLK_APBCLK1_PWM0CH45CKEN_Pos (18) /*!< CLK APBCLK1: PWM0CH45CKEN Position */
-#define CLK_APBCLK1_PWM0CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH45CKEN_Pos) /*!< CLK APBCLK1: PWM0CH45CKEN Mask */
-
-#define CLK_APBCLK1_PWM1CH01CKEN_Pos (19) /*!< CLK APBCLK1: PWM1CH01CKEN Position */
-#define CLK_APBCLK1_PWM1CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH01CKEN_Pos) /*!< CLK APBCLK1: PWM1CH01CKEN Mask */
-
-#define CLK_APBCLK1_PWM1CH23CKEN_Pos (20) /*!< CLK APBCLK1: PWM1CH23CKEN Position */
-#define CLK_APBCLK1_PWM1CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH23CKEN_Pos) /*!< CLK APBCLK1: PWM1CH23CKEN Mask */
-
-#define CLK_APBCLK1_PWM1CH45CKEN_Pos (21) /*!< CLK APBCLK1: PWM1CH45CKEN Position */
-#define CLK_APBCLK1_PWM1CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH45CKEN_Pos) /*!< CLK APBCLK1: PWM1CH45CKEN Mask */
-
-#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK APBCLK1: QEI0CKEN Position */
-#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK APBCLK1: QEI0CKEN Mask */
-
-#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK APBCLK1: QEI1CKEN Position */
-#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK APBCLK1: QEI1CKEN Mask */
-
-#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK APBCLK1: ECAP0CKEN Position */
-#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK APBCLK1: ECAP0CKEN Mask */
-
-#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK APBCLK1: ECAP1CKEN Position */
-#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK APBCLK1: ECAP1CKEN Mask */
-
-#define CLK_APBCLK1_EPWM0CKEN_Pos (28) /*!< CLK APBCLK1: EPWM0CKEN Position */
-#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK APBCLK1: EPWM0CKEN Mask */
-
-#define CLK_APBCLK1_EPWM1CKEN_Pos (29) /*!< CLK APBCLK1: EPWM1CKEN Position */
-#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK APBCLK1: EPWM1CKEN Mask */
-
-#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK APBCLK1: OPACKEN Position */
-#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK APBCLK1: OPACKEN Mask */
-
-#define CLK_APBCLK1_EADCCKEN_Pos (31) /*!< CLK APBCLK1: EADCCKEN Position */
-#define CLK_APBCLK1_EADCCKEN_Msk (0x1ul << CLK_APBCLK1_EADCCKEN_Pos) /*!< CLK APBCLK1: EADCCKEN Mask */
-
-#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK CLKSEL0: HCLKSEL Position */
-#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK CLKSEL0: HCLKSEL Mask */
-
-#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK CLKSEL0: STCLKSEL Position */
-#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK CLKSEL0: STCLKSEL Mask */
-
-#define CLK_CLKSEL0_PCLKSEL_Pos (6) /*!< CLK CLKSEL0: PCLKSEL Position */
-#define CLK_CLKSEL0_PCLKSEL_Msk (0x1ul << CLK_CLKSEL0_PCLKSEL_Pos) /*!< CLK CLKSEL0: PCLKSEL Mask */
-
-#define CLK_CLKSEL0_USBHSEL_Pos (8) /*!< CLK CLKSEL0: USBHSEL Position */
-#define CLK_CLKSEL0_USBHSEL_Msk (0x1ul << CLK_CLKSEL0_USBHSEL_Pos) /*!< CLK CLKSEL0: USBHSEL Mask */
-
-#define CLK_CLKSEL0_CAPSEL_Pos (16) /*!< CLK CLKSEL0: CAPSEL Position */
-#define CLK_CLKSEL0_CAPSEL_Msk (0x3ul << CLK_CLKSEL0_CAPSEL_Pos) /*!< CLK CLKSEL0: CAPSEL Mask */
-
-#define CLK_CLKSEL0_SDHSEL_Pos (20) /*!< CLK CLKSEL0: SDHSEL Position */
-#define CLK_CLKSEL0_SDHSEL_Msk (0x3ul << CLK_CLKSEL0_SDHSEL_Pos) /*!< CLK CLKSEL0: SDHSEL Mask */
-
-#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK CLKSEL1: WDTSEL Position */
-#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK CLKSEL1: WDTSEL Mask */
-
-#define CLK_CLKSEL1_ADCSEL_Pos (2) /*!< CLK CLKSEL1: ADCSEL Position */
-#define CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos) /*!< CLK CLKSEL1: ADCSEL Mask */
-
-#define CLK_CLKSEL1_SPI0SEL_Pos (4) /*!< CLK CLKSEL1: SPI0SEL Position */
-#define CLK_CLKSEL1_SPI0SEL_Msk (0x1ul << CLK_CLKSEL1_SPI0SEL_Pos) /*!< CLK CLKSEL1: SPI0SEL Mask */
-
-#define CLK_CLKSEL1_SPI1SEL_Pos (5) /*!< CLK CLKSEL1: SPI1SEL Position */
-#define CLK_CLKSEL1_SPI1SEL_Msk (0x1ul << CLK_CLKSEL1_SPI1SEL_Pos) /*!< CLK CLKSEL1: SPI1SEL Mask */
-
-#define CLK_CLKSEL1_SPI2SEL_Pos (6) /*!< CLK CLKSEL1: SPI2SEL Position */
-#define CLK_CLKSEL1_SPI2SEL_Msk (0x1ul << CLK_CLKSEL1_SPI2SEL_Pos) /*!< CLK CLKSEL1: SPI2SEL Mask */
-
-#define CLK_CLKSEL1_SPI3SEL_Pos (7) /*!< CLK CLKSEL1: SPI3SEL Position */
-#define CLK_CLKSEL1_SPI3SEL_Msk (0x1ul << CLK_CLKSEL1_SPI3SEL_Pos) /*!< CLK CLKSEL1: SPI3SEL Mask */
-
-#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK CLKSEL1: TMR0SEL Position */
-#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK CLKSEL1: TMR0SEL Mask */
-
-#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK CLKSEL1: TMR1SEL Position */
-#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK CLKSEL1: TMR1SEL Mask */
-
-#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK CLKSEL1: TMR2SEL Position */
-#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK CLKSEL1: TMR2SEL Mask */
-
-#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK CLKSEL1: TMR3SEL Position */
-#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK CLKSEL1: TMR3SEL Mask */
-
-#define CLK_CLKSEL1_UARTSEL_Pos (24) /*!< CLK CLKSEL1: UARTSEL Position */
-#define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /*!< CLK CLKSEL1: UARTSEL Mask */
-
-#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK CLKSEL1: CLKOSEL Position */
-#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK CLKSEL1: CLKOSEL Mask */
-
-#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK CLKSEL1: WWDTSEL Position */
-#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK CLKSEL1: WWDTSEL Mask */
-
-#define CLK_CLKSEL2_PWM0CH01SEL_Pos (0) /*!< CLK CLKSEL2: PWM0CH01SEL Position */
-#define CLK_CLKSEL2_PWM0CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< CLK CLKSEL2: PWM0CH01SEL Mask */
-
-#define CLK_CLKSEL2_PWM0CH23SEL_Pos (4) /*!< CLK CLKSEL2: PWM0CH23SEL Position */
-#define CLK_CLKSEL2_PWM0CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< CLK CLKSEL2: PWM0CH23SEL Mask */
-
-#define CLK_CLKSEL2_PWM0CH45SEL_Pos (8) /*!< CLK CLKSEL2: PWM0CH45SEL Position */
-#define CLK_CLKSEL2_PWM0CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< CLK CLKSEL2: PWM0CH45SEL Mask */
-
-#define CLK_CLKSEL2_PWM1CH01SEL_Pos (12) /*!< CLK CLKSEL2: PWM1CH01SEL Position */
-#define CLK_CLKSEL2_PWM1CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< CLK CLKSEL2: PWM1CH01SEL Mask */
-
-#define CLK_CLKSEL2_PWM1CH23SEL_Pos (16) /*!< CLK CLKSEL2: PWM1CH23SEL Position */
-#define CLK_CLKSEL2_PWM1CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< CLK CLKSEL2: PWM1CH23SEL Mask */
-
-#define CLK_CLKSEL2_PWM1CH45SEL_Pos (20) /*!< CLK CLKSEL2: PWM1CH45SEL Position */
-#define CLK_CLKSEL2_PWM1CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< CLK CLKSEL2: PWM1CH45SEL Mask */
-
-#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK CLKSEL3: SC0SEL Position */
-#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK CLKSEL3: SC0SEL Mask */
-
-#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK CLKSEL3: SC1SEL Position */
-#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK CLKSEL3: SC1SEL Mask */
-
-#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK CLKSEL3: SC2SEL Position */
-#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK CLKSEL3: SC2SEL Mask */
-
-#define CLK_CLKSEL3_SC3SEL_Pos (6) /*!< CLK CLKSEL3: SC3SEL Position */
-#define CLK_CLKSEL3_SC3SEL_Msk (0x3ul << CLK_CLKSEL3_SC3SEL_Pos) /*!< CLK CLKSEL3: SC3SEL Mask */
-
-#define CLK_CLKSEL3_SC4SEL_Pos (8) /*!< CLK CLKSEL3: SC4SEL Position */
-#define CLK_CLKSEL3_SC4SEL_Msk (0x3ul << CLK_CLKSEL3_SC4SEL_Pos) /*!< CLK CLKSEL3: SC4SEL Mask */
-
-#define CLK_CLKSEL3_SC5SEL_Pos (10) /*!< CLK CLKSEL3: SC5SEL Position */
-#define CLK_CLKSEL3_SC5SEL_Msk (0x3ul << CLK_CLKSEL3_SC5SEL_Pos) /*!< CLK CLKSEL3: SC5SEL Mask */
-
-#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK CLKSEL3: I2S0SEL Position */
-#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK CLKSEL3: I2S0SEL Mask */
-
-#define CLK_CLKSEL3_I2S1SEL_Pos (18) /*!< CLK CLKSEL3: I2S1SEL Position */
-#define CLK_CLKSEL3_I2S1SEL_Msk (0x3ul << CLK_CLKSEL3_I2S1SEL_Pos) /*!< CLK CLKSEL3: I2S1SEL Mask */
-
-#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK CLKDIV0: HCLKDIV Position */
-#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK CLKDIV0: HCLKDIV Mask */
-
-#define CLK_CLKDIV0_USBHDIV_Pos (4) /*!< CLK CLKDIV0: USBHDIV Position */
-#define CLK_CLKDIV0_USBHDIV_Msk (0xful << CLK_CLKDIV0_USBHDIV_Pos) /*!< CLK CLKDIV0: USBHDIV Mask */
-
-#define CLK_CLKDIV0_UARTDIV_Pos (8) /*!< CLK CLKDIV0: UARTDIV Position */
-#define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLK CLKDIV0: UARTDIV Mask */
-
-#define CLK_CLKDIV0_ADCDIV_Pos (16) /*!< CLK CLKDIV0: ADCDIV Position */
-#define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) /*!< CLK CLKDIV0: ADCDIV Mask */
-
-#define CLK_CLKDIV0_SDHDIV_Pos (24) /*!< CLK CLKDIV0: SDHDIV Position */
-#define CLK_CLKDIV0_SDHDIV_Msk (0xfful << CLK_CLKDIV0_SDHDIV_Pos) /*!< CLK CLKDIV0: SDHDIV Mask */
-
-#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK CLKDIV1: SC0DIV Position */
-#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK CLKDIV1: SC0DIV Mask */
-
-#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK CLKDIV1: SC1DIV Position */
-#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK CLKDIV1: SC1DIV Mask */
-
-#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK CLKDIV1: SC2DIV Position */
-#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK CLKDIV1: SC2DIV Mask */
-
-#define CLK_CLKDIV1_SC3DIV_Pos (24) /*!< CLK CLKDIV1: SC3DIV Position */
-#define CLK_CLKDIV1_SC3DIV_Msk (0xfful << CLK_CLKDIV1_SC3DIV_Pos) /*!< CLK CLKDIV1: SC3DIV Mask */
-
-#define CLK_CLKDIV2_SC4DIV_Pos (0) /*!< CLK CLKDIV2: SC4DIV Position */
-#define CLK_CLKDIV2_SC4DIV_Msk (0xfful << CLK_CLKDIV2_SC4DIV_Pos) /*!< CLK CLKDIV2: SC4DIV Mask */
-
-#define CLK_CLKDIV2_SC5DIV_Pos (8) /*!< CLK CLKDIV2: SC5DIV Position */
-#define CLK_CLKDIV2_SC5DIV_Msk (0xfful << CLK_CLKDIV2_SC5DIV_Pos) /*!< CLK CLKDIV2: SC5DIV Mask */
-
-#define CLK_CLKDIV3_CAPDIV_Pos (0) /*!< CLK CLKDIV3: CAPDIV Position */
-#define CLK_CLKDIV3_CAPDIV_Msk (0xfful << CLK_CLKDIV3_CAPDIV_Pos) /*!< CLK CLKDIV3: CAPDIV Mask */
-
-#define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK CLKDIV3: VSENSEDIV Position */
-#define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK CLKDIV3: VSENSEDIV Mask */
-
-#define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK CLKDIV3: EMACDIV Position */
-#define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK CLKDIV3: EMACDIV Mask */
-
-#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK PLLCTL: FBDIV Position */
-#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK PLLCTL: FBDIV Mask */
-
-#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK PLLCTL: INDIV Position */
-#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK PLLCTL: INDIV Mask */
-
-#define CLK_PLLCTL_OUTDV_Pos (14) /*!< CLK PLLCTL: OUTDV Position */
-#define CLK_PLLCTL_OUTDV_Msk (0x3ul << CLK_PLLCTL_OUTDV_Pos) /*!< CLK PLLCTL: OUTDV Mask */
-
-#define CLK_PLLCTL_PD_Pos (16) /*!< CLK PLLCTL: PD Position */
-#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK PLLCTL: PD Mask */
-
-#define CLK_PLLCTL_BP_Pos (17) /*!< CLK PLLCTL: BP Position */
-#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK PLLCTL: BP Mask */
-
-#define CLK_PLLCTL_OE_Pos (18) /*!< CLK PLLCTL: OE Position */
-#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK PLLCTL: OE Mask */
-
-#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK PLLCTL: PLLSRC Position */
-#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK PLLCTL: PLLSRC Mask */
-
-#define CLK_PLLCTL_PLLREMAP_Pos (20) /*!< CLK PLLCTL: PLLREMAP Position */
-#define CLK_PLLCTL_PLLREMAP_Msk (0x1ul << CLK_PLLCTL_PLLREMAP_Pos) /*!< CLK PLLCTL: PLLREMAP Mask */
-
-#define CLK_PLL2CTL_PLL2DIV_Pos (0) /*!< CLK PLL2CTL: PLL2DIV Position */
-#define CLK_PLL2CTL_PLL2DIV_Msk (0xfful << CLK_PLL2CTL_PLL2DIV_Pos) /*!< CLK PLL2CTL: PLL2DIV Mask */
-
-#define CLK_PLL2CTL_PLL2CKEN_Pos (8) /*!< CLK PLL2CTL: PLL2CKEN Position */
-#define CLK_PLL2CTL_PLL2CKEN_Msk (0x1ul << CLK_PLL2CTL_PLL2CKEN_Pos) /*!< CLK PLL2CTL: PLL2CKEN Mask */
-
-#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK STATUS: HXTSTB Position */
-#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK STATUS: HXTSTB Mask */
-
-#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK STATUS: LXTSTB Position */
-#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK STATUS: LXTSTB Mask */
-
-#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK STATUS: PLLSTB Position */
-#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK STATUS: PLLSTB Mask */
-
-#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK STATUS: LIRCSTB Position */
-#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK STATUS: LIRCSTB Mask */
-
-#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK STATUS: HIRCSTB Position */
-#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK STATUS: HIRCSTB Mask */
-
-#define CLK_STATUS_PLL2STB_Pos (5) /*!< CLK STATUS: PLL2STB Position */
-#define CLK_STATUS_PLL2STB_Msk (0x1ul << CLK_STATUS_PLL2STB_Pos) /*!< CLK STATUS: PLL2STB Mask */
-
-#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK STATUS: CLKSFAIL Position */
-#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK STATUS: CLKSFAIL Mask */
-
-#define CLK_CLKOCTL_FSEL_Pos (0) /*!< CLK CLKOCTL: FSEL Position */
-#define CLK_CLKOCTL_FSEL_Msk (0xful << CLK_CLKOCTL_FSEL_Pos) /*!< CLK CLKOCTL: FSEL Mask */
-
-#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK CLKOCTL: CLKOEN Position */
-#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK CLKOCTL: CLKOEN Mask */
-
-#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK CLKOCTL: DIV1EN Position */
-#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK CLKOCTL: DIV1EN Mask */
-
-#define CLK_CLKDCTL_SYSFDEN_Pos (0) /*!< CLK CLKDCTL: SYSFDEN Position */
-#define CLK_CLKDCTL_SYSFDEN_Msk (0x1ul << CLK_CLKDCTL_SYSFDEN_Pos) /*!< CLK CLKDCTL: SYSFDEN Mask */
-
-#define CLK_CLKDCTL_SYSFIEN_Pos (1) /*!< CLK CLKDCTL: SYSFIEN Position */
-#define CLK_CLKDCTL_SYSFIEN_Msk (0x1ul << CLK_CLKDCTL_SYSFIEN_Pos) /*!< CLK CLKDCTL: SYSFIEN Mask */
-
-#define CLK_CLKDCTL_SYSFIF_Pos (2) /*!< CLK CLKDCTL: SYSFIF Position */
-#define CLK_CLKDCTL_SYSFIF_Msk (0x1ul << CLK_CLKDCTL_SYSFIF_Pos) /*!< CLK CLKDCTL: SYSFIF Mask */
-
-#define CLK_CLKDCTL_IRCDEN_Pos (8) /*!< CLK CLKDCTL: IRCDEN Position */
-#define CLK_CLKDCTL_IRCDEN_Msk (0x1ul << CLK_CLKDCTL_IRCDEN_Pos) /*!< CLK CLKDCTL: IRCDEN Mask */
-
-#define CLK_CLKDCTL_IRCFIEN_Pos (9) /*!< CLK CLKDCTL: IRCFIEN Position */
-#define CLK_CLKDCTL_IRCFIEN_Msk (0x1ul << CLK_CLKDCTL_IRCFIEN_Pos) /*!< CLK CLKDCTL: IRCFIEN Mask */
-
-#define CLK_CLKDCTL_IRCFIF_Pos (10) /*!< CLK CLKDCTL: IRCFIF Position */
-#define CLK_CLKDCTL_IRCFIF_Msk (0x1ul << CLK_CLKDCTL_IRCFIF_Pos) /*!< CLK CLKDCTL: IRCFIF Mask */
-
-/**@}*/ /* CLK_CONST */
-/**@}*/ /* end of CLK register group */
-
-
-/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
-/**
- @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
- Memory Mapped Structure for CRC Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 CRC Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CRCEN |CRC Channel Enable Control
- * | | |0 = CRC function Disabled.
- * | | |1 = CRC function Enabled.
- * |[1] |CRCRST |CRC Engine Reset
- * | | |0 = No effect.
- * | | |1 = Reset the internal CRC state machine and internal buffer.
- * | | |The contents of control register will not be cleared.
- * | | |This bit will automatically be cleared after few clock cycles.
- * | | |Note: Setting this bit will reload the initial seed value.
- * |[24] |DATREV |Write Data Order Reverse
- * | | |0 = No bit order reversed for CRC write data in.
- * | | |1 = Bit order reversed for CRC write data in (per byte).
- * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
- * |[25] |CHKSREV |Checksum Reverse
- * | | |0 = No bit order reverse for CRC checksum.
- * | | |1 = Bit order reverse for CRC checksum.
- * | | |Note: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.
- * |[26] |DATFMT |Write Data Complement
- * | | |0 = No bit order reversed for CRC write data in.
- * | | |1 = 1's complement for CRC write data in.
- * |[27] |CHKSFMT |Checksum Complement
- * | | |0 = No bit order reverse for CRC checksum.
- * | | |1 = 1's complement for CRC checksum.
- * |[28:29] |DATLEN |CPU Write Data Length
- * | | |This field indicates the write data length.
- * | | |00 = Data length is 8-bit mode.
- * | | |01 = Data length is 16-bit mode.
- * | | |1x = Data length is 32-bit mode.
- * | | |Note: When the data length is 8-bit mode, the valid data is DATA [7:0]; if the data length is 16-bit mode, the valid data is DATA [15:0].
- * |[30:31] |CRCMODE |CRC Polynomial Mode Selection
- * | | |00 = CRC-CCITT Polynomial mode.
- * | | |01 = CRC-8 Polynomial mode.
- * | | |10 = CRC-16 Polynomial mode.
- * | | |11 = CRC-32 Polynomial mode.
- */
- __IO uint32_t CTL;
-
- /**
- * DAT
- * ===================================================================================================
- * Offset: 0x04 CRC Write Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DATA |CRC Write Data Bits
- * | | |Software can write data to this field to perform CRC operation, or uses PDMA function to get the data from memory
- * | | |Note1: The CRC_CTL [DATFMT] and CRC_CTL [DATREV] bit setting will affect this field; for example, if DATREV = 1, if the write data in DATA register is 0xAABBCCDD, the read data from DATA register will be 0x55DD33BB.
- */
- __IO uint32_t DAT;
-
- /**
- * SEED
- * ===================================================================================================
- * Offset: 0x08 CRC Seed Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SEED |CRC Seed Bits
- * | | |This field indicates the CRC seed value.
- */
- __IO uint32_t SEED;
-
- /**
- * CHECKSUM
- * ===================================================================================================
- * Offset: 0x0C CRC Checksum Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CHECKSUM |CRC Checksum Bits
- * | | |This field indicates the CRC checksum.
- */
- __I uint32_t CHECKSUM;
-
-} CRC_T;
-
-/**
- @addtogroup CRC_CONST CRC Bit Field Definition
- Constant Definitions for CRC Controller
-@{ */
-
-#define CRC_CTL_CRCEN_Pos (0) /*!< CRC CTL: CRCEN Position */
-#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC CTL: CRCEN Mask */
-
-#define CRC_CTL_CRCRST_Pos (1) /*!< CRC CTL: CRCRST Position */
-#define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /*!< CRC CTL: CRCRST Mask */
-
-#define CRC_CTL_DATREV_Pos (24) /*!< CRC CTL: DATREV Position */
-#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC CTL: DATREV Mask */
-
-#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC CTL: CHKSREV Position */
-#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC CTL: CHKSREV Mask */
-
-#define CRC_CTL_DATFMT_Pos (26) /*!< CRC CTL: DATFMT Position */
-#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC CTL: DATFMT Mask */
-
-#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC CTL: CHKSFMT Position */
-#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC CTL: CHKSFMT Mask */
-
-#define CRC_CTL_DATLEN_Pos (28) /*!< CRC CTL: DATLEN Position */
-#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC CTL: DATLEN Mask */
-
-#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC CTL: CRCMODE Position */
-#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC CTL: CRCMODE Mask */
-
-#define CRC_DAT_DATA_Pos (0) /*!< CRC DAT: DATA Position */
-#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC DAT: DATA Mask */
-
-#define CRC_SEED_SEED_Pos (0) /*!< CRC SEED: SEED Position */
-#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC SEED: SEED Mask */
-
-#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC CHECKSUM: CHECKSUM Position */
-#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC CHECKSUM: CHECKSUM Mask */
-
-/**@}*/ /* CRC_CONST */
-/**@}*/ /* end of CRC register group */
-
-
-/*---------------------- Cryptographic Accelerator -------------------------*/
-/**
- @addtogroup CRPT Cryptographic Accelerator(CRPT)
- Memory Mapped Structure for CRPT Controller
-@{ */
-
-typedef struct {
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x00 Crypto Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |AESIEN |AES Interrupt Enable Control
- * | | |0 = AES interrupt Disabled.
- * | | |1 = AES interrupt Enabled.
- * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
- * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
- * |[1] |AESERRIEN |AES Error Flag Enable Control
- * | | |0 = AES error interrupt flag Disabled.
- * | | |1 = AES error interrupt flag Enabled.
- * |[8] |TDESIEN |TDES/DES Interrupt Enable Control
- * | | |0 = TDES/DES interrupt Disabled.
- * | | |1 = TDES/DES interrupt Enabled.
- * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
- * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
- * |[9] |TDESERRIEN|TDES/DES Error Flag Enable Control
- * | | |0 = TDES/DES error interrupt flag Disabled.
- * | | |1 = TDES/DES error interrupt flag Enabled.
- * |[16] |PRNGIEN |PRNG Interrupt Enable Control
- * | | |0 = PRNG interrupt Disabled.
- * | | |1 = PRNG interrupt Enabled.
- * |[24] |SHAIEN |SHA Interrupt Enable Control
- * | | |0 = SHA interrupt Disabled.
- * | | |1 = SHA interrupt Enabled.
- * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine.
- * | | |In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
- * |[25] |SHAERRIEN |SHA Error Interrupt Enable Control
- * | | |0 = SHA error interrupt flag Disabled.
- * | | |1 = SHA error interrupt flag Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x04 Crypto Interrupt Flag
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |AESIF |AES Finish Interrupt Flag
- * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
- * | | |0 = No AES interrupt.
- * | | |1 = AES encryption/decryption done interrupt.
- * |[1] |AESERRIF |AES Error Flag
- * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
- * | | |0 = No AES error.
- * | | |1 = AES encryption/decryption done interrupt.
- * |[8] |TDESIF |TDES/DES Finish Interrupt Flag
- * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
- * | | |0 = No TDES/DES interrupt.
- * | | |1 = TDES/DES encryption/decryption done interrupt.
- * |[9] |TDESERRIF |TDES/DES Error Flag
- * | | |This bit includes the operating and setting error.
- * | | |The detailed flag is shown in the TDES _FLAG register.
- * | | |This includes operating and setting error.
- * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
- * | | |0 = No TDES/DES error.
- * | | |1 = TDES/DES encryption/decryption error interrupt.
- * |[16] |PRNGIF |PRNG Finish Interrupt Flag
- * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
- * | | |0 = No PRNG interrupt.
- * | | |1 = PRNG key generation done interrupt.
- * |[24] |SHAIF |SHA Finish Interrupt Flag
- * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
- * | | |0 = No SHA interrupt.
- * | | |1 = SHA operation done interrupt.
- * |[25] |SHAERRIF |SHA Error Flag
- * | | |This register includes operating and setting error. The detail flag is shown in SHA _FLAG register.
- * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
- * | | |0 = No SHA error.
- * | | |1 = SHA error interrupt.
- */
- __IO uint32_t INTSTS;
-
- /**
- * PRNG_CTL
- * ===================================================================================================
- * Offset: 0x08 PRNG Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |START |Start PRNG Engine
- * | | |0 = Stop PRNG engine.
- * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
- * |[1] |SEEDRLD |Reload New Seed For PRNG Engine
- * | | |0 = Generating key based on the current seed.
- * | | |1 = Reload new seed.
- * |[2:3] |KEYSZ |PRNG Generate Key Size
- * | | |00 = 64 bits.
- * | | |01 = 128 bits.
- * | | |10 = 192 bits.
- * | | |11 = 256 bits.
- * |[8] |BUSY |PRNG Busy (Read Only)
- * | | |0 = PRNG engine is idle.
- * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
- */
- __IO uint32_t PRNG_CTL;
-
- /**
- * PRNG_SEED
- * ===================================================================================================
- * Offset: 0x0C Seed for PRNG
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CRPT_PRNG_SEED|Seed For PRNG (Write Only)
- * | | |The bits store the seed for PRNG engine.
- */
- __O uint32_t PRNG_SEED;
-
- /**
- * PRNG_KEY0
- * ===================================================================================================
- * Offset: 0x10 PRNG Generated Key0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY0;
-
- /**
- * PRNG_KEY1
- * ===================================================================================================
- * Offset: 0x14 PRNG Generated Key1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY1;
-
- /**
- * PRNG_KEY2
- * ===================================================================================================
- * Offset: 0x18 PRNG Generated Key2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY2;
-
- /**
- * PRNG_KEY3
- * ===================================================================================================
- * Offset: 0x1C PRNG Generated Key3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY3;
-
- /**
- * PRNG_KEY4
- * ===================================================================================================
- * Offset: 0x20 PRNG Generated Key4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY4;
-
- /**
- * PRNG_KEY5
- * ===================================================================================================
- * Offset: 0x24 PRNG Generated Key5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY5;
-
- /**
- * PRNG_KEY6
- * ===================================================================================================
- * Offset: 0x28 PRNG Generated Key6
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY6;
-
- /**
- * PRNG_KEY7
- * ===================================================================================================
- * Offset: 0x2C PRNG Generated Key7
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
- * | | |The bits store the key that is generated by PRNG.
- */
- __I uint32_t PRNG_KEY7;
- uint32_t RESERVE0[8];
-
-
- /**
- * AES_FDBCK0
- * ===================================================================================================
- * Offset: 0x50 AES Engine Output Feedback Data after Cryptographic Operation
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |FDBCK |AES Feedback Information
- * | | |The feedback value is 128 bits in size.
- * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
- * | | |The AES engine outputs feedback information for IV in the next block's operation.
- * | | |Software can use this feedback information to implement more than four DMA channels.
- * | | |Software can store that feedback value temporarily.
- * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
- */
- __I uint32_t AES_FDBCK0;
-
- /**
- * AES_FDBCK1
- * ===================================================================================================
- * Offset: 0x54 AES Engine Output Feedback Data after Cryptographic Operation
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |FDBCK |AES Feedback Information
- * | | |The feedback value is 128 bits in size.
- * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
- * | | |The AES engine outputs feedback information for IV in the next block's operation.
- * | | |Software can use this feedback information to implement more than four DMA channels.
- * | | |Software can store that feedback value temporarily.
- * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
- */
- __I uint32_t AES_FDBCK1;
-
- /**
- * AES_FDBCK2
- * ===================================================================================================
- * Offset: 0x58 AES Engine Output Feedback Data after Cryptographic Operation
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |FDBCK |AES Feedback Information
- * | | |The feedback value is 128 bits in size.
- * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
- * | | |The AES engine outputs feedback information for IV in the next block's operation.
- * | | |Software can use this feedback information to implement more than four DMA channels.
- * | | |Software can store that feedback value temporarily.
- * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
- */
- __I uint32_t AES_FDBCK2;
-
- /**
- * AES_FDBCK3
- * ===================================================================================================
- * Offset: 0x5C AES Engine Output Feedback Data after Cryptographic Operation
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |FDBCK |AES Feedback Information
- * | | |The feedback value is 128 bits in size.
- * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
- * | | |The AES engine outputs feedback information for IV in the next block's operation.
- * | | |Software can use this feedback information to implement more than four DMA channels.
- * | | |Software can store that feedback value temporarily.
- * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
- */
- __I uint32_t AES_FDBCK3;
-
- /**
- * TDES_FDBCKH
- * ===================================================================================================
- * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |FDBCK |TDES/DES Feedback
- * | | |The feedback value is 64 bits in size.
- * | | |The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode.
- * | | |The feedback register is for CBC, CFB, and OFB mode.
- * | | |TDES/DES engine outputs feedback information for IV in the next block's operation.
- * | | |Software can use this feedback information to implement more than four DMA channels.
- * | | |Software can store that feedback value temporarily.
- * | | |After switching back, fill the stored feedback value to this register in the same channel operation.
- * | | |Then can continue the operation with the original setting.
- */
- __I uint32_t TDES_FDBCKH;
-
- /**
- * TDES_FDBCKL
- * ===================================================================================================
- * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |FDBCK |TDES/DES Feedback
- * | | |The feedback value is 64 bits in size.
- * | | |The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode.
- * | | |The feedback register is for CBC, CFB, and OFB mode.
- * | | |TDES/DES engine outputs feedback information for IV in the next block's operation.
- * | | |Software can use this feedback information to implement more than four DMA channels.
- * | | |Software can store that feedback value temporarily.
- * | | |After switching back, fill the stored feedback value to this register in the same channel operation.
- * | | |Then can continue the operation with the original setting.
- */
- __I uint32_t TDES_FDBCKL;
- uint32_t RESERVE1[38];
-
-
- /**
- * AES_CTL
- * ===================================================================================================
- * Offset: 0x100 AES Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |START |AES Engine Start
- * | | |0 = No effect.
- * | | |1 = Start AES engine. BUSY flag will be set.
- * | | |Note: This bit is always 0 when it's read back.
- * |[1] |STOP |AES Engine Stop
- * | | |0 = No effect.
- * | | |1 = Stop AES engine.
- * | | |Note: This bit is always 0 when it's read back.
- * |[2:3] |KEYSZ |AES Key Size
- * | | |This bit defines three different key size for AES operation.
- * | | |2'b00 = 128 bits key.
- * | | |2'b01 = 192 bits key.
- * | | |2'b10 = 256 bits key.
- * | | |2'b11 = Reserved.
- * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
- * |[5] |DMALAST |AES Last Block
- * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
- * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
- * | | |This bit is always 0 when it's read back. Must be written again once START is triggered.
- * |[6] |DMACSCAD |AES Engine DMA With Cascade Mode
- * | | |0 = DMA cascade function Disabled.
- * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
- * |[7] |DMAEN |AES Engine DMA Enable Control
- * | | |0 = AES DMA engine Disabled.
- * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
- * | | |1 = AES DMA engine Enabled.
- * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
- * |[8:15] |OPMODE |AES Engine Operation Modes
- * | | |0x00 = ECB (Electronic Codebook Mode)
- * | | |0x01 = CBC (Cipher Block Chaining Mode).
- * | | |0x02 = CFB (Cipher Feedback Mode).
- * | | |0x03 = OFB (Output Feedback Mode).
- * | | |0x04 = CTR (Counter Mode).
- * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
- * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
- * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
- * |[16] |ENCRPT |AES Encryption/Decryption
- * | | |0 = AES engine executes decryption operation.
- * | | |1 = AES engine executes encryption operation.
- * |[22] |OUTSWAP |AES Engine Output Data Swap
- * | | |0 = Keep the original order.
- * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
- * |[23] |INSWAP |AES Engine Input Data Swap
- * | | |0 = Keep the original order.
- * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
- * |[24:25] |CHANNEL |AES Engine Working Channel
- * | | |00 = Current control register setting is for channel 0.
- * | | |01 = Current control register setting is for channel 1.
- * | | |10 = Current control register setting is for channel 2.
- * | | |11 = Current control register setting is for channel 3.
- * |[26:30] |KEYUNPRT |Unprotect Key
- * | | |Writing 0 to CRPT_AES_CTL [31] and "10110" to CRPT_AES_CTL [30:26] is to unprotect the AES key.
- * | | |The KEYUNPRT can be read and written.
- * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
- * |[31] |KEYPRT |Protect Key
- * | | |Read as a flag to reflect KEYPRT.
- * | | |0 = No effect.
- * | | |1 = Protect the content of the AES key from reading.
- * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx.
- * | | |Once it is set, it can be cleared by asserting KEYUNPRT.
- * | | |And the key content would be cleared as well.
- */
- __IO uint32_t AES_CTL;
-
- /**
- * AES_STS
- * ===================================================================================================
- * Offset: 0x104 AES Engine Flag
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSY |AES Engine Busy
- * | | |0 = The AES engine is idle or finished.
- * | | |1 = The AES engine is under processing.
- * |[8] |INBUFEMPTY|AES Input Buffer Empty
- * | | |0 = There are some data in input buffer waiting for the AES engine to process.
- * | | |1 = AES input buffer is empty.
- * | | |Software needs to feed data to the AES engine.
- * | | |Otherwise, the AES engine will be pending to wait for input data.
- * |[9] |INBUFFULL |AES Input Buffer Full Flag
- * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine.
- * | | |1 = AES input buffer is full.
- * | | |Software cannot feed data to the AES engine.
- * | | |Otherwise, the flag INBUFERR will be set to 1.
- * |[10] |INBUFERR |AES Input Buffer Error Flag
- * | | |0 = No error.
- * | | |1 = Error happens during feeding data to the AES engine.
- * |[12] |CNTERR |AES_CNT Setting Error
- * | | |0 = No error in AES_CNT setting.
- * | | |1 = AES_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
- * |[16] |OUTBUFEMPTY|AES Out Buffer Empty
- * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
- * | | |1 = AES output buffer is empty.
- * | | |Software cannot get data from AES_DATA_OUT.
- * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
- * |[17] |OUTBUFFULL|AES Out Buffer Full Flag
- * | | |0 = AES output buffer is not full.
- * | | |1 = AES output buffer is full, and software needs to get data from AES_DATA_OUT.
- * | | |Otherwise, the AES engine will be pending since the output buffer is full.
- * |[18] |OUTBUFERR |AES Out Buffer Error Flag
- * | | |0 = No error.
- * | | |1 = Error happens during getting the result from AES engine.
- * |[20] |BUSERR |AES DMA Access Bus Error Flag
- * | | |0 = No error.
- * | | |1 = Bus error will stop DMA operation and AES engine.
- */
- __I uint32_t AES_STS;
-
- /**
- * AES_DATIN
- * ===================================================================================================
- * Offset: 0x108 AES Engine Data Input Port Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DATIN |AES Engine Input Port
- * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
- */
- __IO uint32_t AES_DATIN;
-
- /**
- * AES_DATOUT
- * ===================================================================================================
- * Offset: 0x10C AES Engine Data Output Port Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DATOUT |AES Engine Output Port
- * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS.
- * | | |Get data as OUTBUFEMPTY is 0.
- */
- __I uint32_t AES_DATOUT;
-
- /**
- * AES0_KEY0
- * ===================================================================================================
- * Offset: 0x110 AES Key Word 0 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY0;
-
- /**
- * AES0_KEY1
- * ===================================================================================================
- * Offset: 0x114 AES Key Word 1 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY1;
-
- /**
- * AES0_KEY2
- * ===================================================================================================
- * Offset: 0x118 AES Key Word 2 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY2;
-
- /**
- * AES0_KEY3
- * ===================================================================================================
- * Offset: 0x11C AES Key Word 3 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY3;
-
- /**
- * AES0_KEY4
- * ===================================================================================================
- * Offset: 0x120 AES Key Word 4 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY4;
-
- /**
- * AES0_KEY5
- * ===================================================================================================
- * Offset: 0x124 AES Key Word 5 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY5;
-
- /**
- * AES0_KEY6
- * ===================================================================================================
- * Offset: 0x128 AES Key Word 6 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY6;
-
- /**
- * AES0_KEY7
- * ===================================================================================================
- * Offset: 0x12C AES Key Word 7 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES0_KEY7;
-
- /**
- * AES0_IV0
- * ===================================================================================================
- * Offset: 0x130 AES Initial Vector Word 0 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES0_IV0;
-
- /**
- * AES0_IV1
- * ===================================================================================================
- * Offset: 0x134 AES Initial Vector Word 1 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES0_IV1;
-
- /**
- * AES0_IV2
- * ===================================================================================================
- * Offset: 0x138 AES Initial Vector Word 2 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES0_IV2;
-
- /**
- * AES0_IV3
- * ===================================================================================================
- * Offset: 0x13C AES Initial Vector Word 3 Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES0_IV3;
-
- /**
- * AES0_SADDR
- * ===================================================================================================
- * Offset: 0x140 AES DMA Source Address Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |AES DMA Source Address
- * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
- * | | |AES_SADR can be read and written.
- * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_SADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES0_SADDR;
-
- /**
- * AES0_DADDR
- * ===================================================================================================
- * Offset: 0x144 AES DMA Destination Address Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |AES DMA Destination Address
- * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
- * | | |AES_DADR can be read and written.
- * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_DADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES0_DADDR;
-
- /**
- * AES0_CNT
- * ===================================================================================================
- * Offset: 0x148 AES Byte Count Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |AES Byte Count
- * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
- * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |AES_CNT can be read and written.
- * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next AES operation.
- * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
- * | | |Operations that are less than one block will output unexpected result.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
- */
- __IO uint32_t AES0_CNT;
-
- /**
- * AES1_KEY0
- * ===================================================================================================
- * Offset: 0x14C AES Key Word 0 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY0;
-
- /**
- * AES1_KEY1
- * ===================================================================================================
- * Offset: 0x150 AES Key Word 1 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY1;
-
- /**
- * AES1_KEY2
- * ===================================================================================================
- * Offset: 0x154 AES Key Word 2 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY2;
-
- /**
- * AES1_KEY3
- * ===================================================================================================
- * Offset: 0x158 AES Key Word 3 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY3;
-
- /**
- * AES1_KEY4
- * ===================================================================================================
- * Offset: 0x15C AES Key Word 4 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY4;
-
- /**
- * AES1_KEY5
- * ===================================================================================================
- * Offset: 0x160 AES Key Word 5 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY5;
-
- /**
- * AES1_KEY6
- * ===================================================================================================
- * Offset: 0x164 AES Key Word 6 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY6;
-
- /**
- * AES1_KEY7
- * ===================================================================================================
- * Offset: 0x168 AES Key Word 7 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES1_KEY7;
-
- /**
- * AES1_IV0
- * ===================================================================================================
- * Offset: 0x16C AES Initial Vector Word 0 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES1_IV0;
-
- /**
- * AES1_IV1
- * ===================================================================================================
- * Offset: 0x170 AES Initial Vector Word 1 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES1_IV1;
-
- /**
- * AES1_IV2
- * ===================================================================================================
- * Offset: 0x174 AES Initial Vector Word 2 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES1_IV2;
-
- /**
- * AES1_IV3
- * ===================================================================================================
- * Offset: 0x178 AES Initial Vector Word 3 Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES1_IV3;
-
- /**
- * AES1_SADDR
- * ===================================================================================================
- * Offset: 0x17C AES DMA Source Address Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |AES DMA Source Address
- * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
- * | | |AES_SADR can be read and written.
- * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_SADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES1_SADDR;
-
- /**
- * AES1_DADDR
- * ===================================================================================================
- * Offset: 0x180 AES DMA Destination Address Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |AES DMA Destination Address
- * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
- * | | |AES_DADR can be read and written.
- * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_DADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES1_DADDR;
-
- /**
- * AES1_CNT
- * ===================================================================================================
- * Offset: 0x184 AES Byte Count Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |AES Byte Count
- * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
- * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |AES_CNT can be read and written.
- * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next AES operation.
- * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
- * | | |Operations that are less than one block will output unexpected result.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
- */
- __IO uint32_t AES1_CNT;
-
- /**
- * AES2_KEY0
- * ===================================================================================================
- * Offset: 0x188 AES Key Word 0 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY0;
-
- /**
- * AES2_KEY1
- * ===================================================================================================
- * Offset: 0x18C AES Key Word 1 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY1;
-
- /**
- * AES2_KEY2
- * ===================================================================================================
- * Offset: 0x190 AES Key Word 2 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY2;
-
- /**
- * AES2_KEY3
- * ===================================================================================================
- * Offset: 0x194 AES Key Word 3 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY3;
-
- /**
- * AES2_KEY4
- * ===================================================================================================
- * Offset: 0x198 AES Key Word 4 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY4;
-
- /**
- * AES2_KEY5
- * ===================================================================================================
- * Offset: 0x19C AES Key Word 5 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY5;
-
- /**
- * AES2_KEY6
- * ===================================================================================================
- * Offset: 0x1A0 AES Key Word 6 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY6;
-
- /**
- * AES2_KEY7
- * ===================================================================================================
- * Offset: 0x1A4 AES Key Word 7 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES2_KEY7;
-
- /**
- * AES2_IV0
- * ===================================================================================================
- * Offset: 0x1A8 AES Initial Vector Word 0 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES2_IV0;
-
- /**
- * AES2_IV1
- * ===================================================================================================
- * Offset: 0x1AC AES Initial Vector Word 1 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES2_IV1;
-
- /**
- * AES2_IV2
- * ===================================================================================================
- * Offset: 0x1B0 AES Initial Vector Word 2 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES2_IV2;
-
- /**
- * AES2_IV3
- * ===================================================================================================
- * Offset: 0x1B4 AES Initial Vector Word 3 Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES2_IV3;
-
- /**
- * AES2_SADDR
- * ===================================================================================================
- * Offset: 0x1B8 AES DMA Source Address Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |AES DMA Source Address
- * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
- * | | |AES_SADR can be read and written.
- * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_SADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES2_SADDR;
-
- /**
- * AES2_DADDR
- * ===================================================================================================
- * Offset: 0x1BC AES DMA Destination Address Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |AES DMA Destination Address
- * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
- * | | |AES_DADR can be read and written.
- * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_DADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES2_DADDR;
-
- /**
- * AES2_CNT
- * ===================================================================================================
- * Offset: 0x1C0 AES Byte Count Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |AES Byte Count
- * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
- * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |AES_CNT can be read and written.
- * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next AES operation.
- * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
- * | | |Operations that are less than one block will output unexpected result.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
- */
- __IO uint32_t AES2_CNT;
-
- /**
- * AES3_KEY0
- * ===================================================================================================
- * Offset: 0x1C4 AES Key Word 0 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY0;
-
- /**
- * AES3_KEY1
- * ===================================================================================================
- * Offset: 0x1C8 AES Key Word 1 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY1;
-
- /**
- * AES3_KEY2
- * ===================================================================================================
- * Offset: 0x1CC AES Key Word 2 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY2;
-
- /**
- * AES3_KEY3
- * ===================================================================================================
- * Offset: 0x1D0 AES Key Word 3 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY3;
-
- /**
- * AES3_KEY4
- * ===================================================================================================
- * Offset: 0x1D4 AES Key Word 4 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY4;
-
- /**
- * AES3_KEY5
- * ===================================================================================================
- * Offset: 0x1D8 AES Key Word 5 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY5;
-
- /**
- * AES3_KEY6
- * ===================================================================================================
- * Offset: 0x1DC AES Key Word 6 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY6;
-
- /**
- * AES3_KEY7
- * ===================================================================================================
- * Offset: 0x1E0 AES Key Word 7 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |AES Key X
- * | | |The KEY keeps the security key for AES operation.
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..7.
- * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
- * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
- * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
- * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
- */
- __IO uint32_t AES3_KEY7;
-
- /**
- * AES3_IV0
- * ===================================================================================================
- * Offset: 0x1E4 AES Initial Vector Word 0 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES3_IV0;
-
- /**
- * AES3_IV1
- * ===================================================================================================
- * Offset: 0x1E8 AES Initial Vector Word 1 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES3_IV1;
-
- /**
- * AES3_IV2
- * ===================================================================================================
- * Offset: 0x1EC AES Initial Vector Word 2 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES3_IV2;
-
- /**
- * AES3_IV3
- * ===================================================================================================
- * Offset: 0x1F0 AES Initial Vector Word 3 Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IV |AES Initial Vector Word X
- * | | |n = 0, 1..3.
- * | | |x = 0, 1..3.
- * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
- * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
- */
- __IO uint32_t AES3_IV3;
-
- /**
- * AES3_SADDR
- * ===================================================================================================
- * Offset: 0x1F4 AES DMA Source Address Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |AES DMA Source Address
- * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
- * | | |AES_SADR can be read and written.
- * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_SADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES3_SADDR;
-
- /**
- * AES3_DADDR
- * ===================================================================================================
- * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |AES DMA Destination Address
- * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
- * | | |AES_DADR can be read and written.
- * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next AES operation.
- * | | |In DMA mode, software can update the next AES_DADR before triggering START.
- * | | |The value of AES_SADR and AES_DADR can be the same.
- */
- __IO uint32_t AES3_DADDR;
-
- /**
- * AES3_CNT
- * ===================================================================================================
- * Offset: 0x1FC AES Byte Count Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |AES Byte Count
- * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
- * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |AES_CNT can be read and written.
- * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
- * | | |But the value of AES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next AES operation.
- * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
- * | | |Operations that are less than one block will output unexpected result.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
- */
- __IO uint32_t AES3_CNT;
-
- /**
- * TDES_CTL
- * ===================================================================================================
- * Offset: 0x200 TDES/DES Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |START |TDES/DES Engine Start
- * | | |0 = No effect.
- * | | |1 = Start TDES/DES engine. The flag BUSY would be set.
- * | | |Note: The bit is always 0 when it's read back.
- * |[1] |STOP |TDES/DES Engine Stop
- * | | |0 = No effect.
- * | | |1 = Stop TDES/DES engine.
- * | | |Note: The bit is always 0 when it's read back.
- * |[2] |TMODE |TDES/DES Engine Operating Mode
- * | | |0 = Set DES mode for TDES/DES engine.
- * | | |1 = Set Triple DES mode for TDES/DES engine.
- * |[3] |3KEYS |TDES/DES Key Number
- * | | |0 = Select KEY1 and KEY2 in TDES/DES engine.
- * | | |1 = Triple keys in TDES/DES engine Enabled.
- * |[5] |DMALAST |TDES/DES Engine Start For The Last Block
- * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
- * | | |In Non-DMA mode, this bit must be set as feeding in last block of data.
- * |[6] |DMACSCAD |TDES/DES Engine DMA With Cascade Mode
- * | | |0 = DMA cascade function Disabled.
- * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
- * |[7] |DMAEN |TDES/DES Engine DMA Enable Control
- * | | |0 = TDES_DMA engine Disabled.
- * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
- * | | |1 = TDES_DMA engine Enabled.
- * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
- * |[8:10] |OPMODE |TDES/DES Engine Operation Mode
- * | | |0x00 = ECB (Electronic Codebook Mode).
- * | | |0x01 = CBC (Cipher Block Chaining Mode).
- * | | |0x02 = CFB (Cipher Feedback Mode).
- * | | |0x03 = OFB (Output Feedback Mode).
- * | | |0x04 = CTR (Counter Mode).
- * | | |Others = CTR (Counter Mode).
- * |[16] |ENCRPT |TDES/DES Encryption/Decryption
- * | | |0 = TDES engine executes decryption operation.
- * | | |1 = TDES engine executes encryption operation.
- * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap
- * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}.
- * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
- * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap
- * | | |0 = Keep the original order.
- * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
- * |[23] |INSWAP |TDES/DES Engine Input Data Swap
- * | | |0 = Keep the original order.
- * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
- * |[24:25] |CHANNEL |TDES/DES Engine Working Channel
- * | | |00 = Current control register setting is for channel 0.
- * | | |01 = Current control register setting is for channel 1.
- * | | |10 = Current control register setting is for channel 2.
- * | | |11 = Current control register setting is for channel 3.
- * |[26:30] |KEYUNPRT |Unprotect Key
- * | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
- * | | |The KEYUNPRT can be read and written.
- * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
- * |[31] |KEYPRT |Protect Key
- * | | |Read as a flag to reflect KEYPRT.
- * | | |0 = No effect.
- * | | |1 = This bit is to protect the content of TDES key from reading.
- * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L.
- * | | |Once it is set, it can be cleared by asserting KEYUNPRT.
- * | | |The key content would be cleared as well.
- */
- __IO uint32_t TDES_CTL;
-
- /**
- * TDES_STS
- * ===================================================================================================
- * Offset: 0x204 TDES/DES Engine Flag
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSY |TDES/DES Engine Busy
- * | | |0 = TDES/DES engine is idle or finished.
- * | | |1 = TDES/DES engine is under processing.
- * |[8] |INBUFEMPTY|TDES/DES In Buffer Empty
- * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process.
- * | | |1 = TDES/DES input buffer is empty.
- * | | |Software needs to feed data to the TDES/DES engine.
- * | | |Otherwise, the TDES/DES engine will be pending to wait for input data.
- * |[9] |INBUFFULL |TDES/DES In Buffer Full Flag
- * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
- * | | |1 = TDES input buffer is full.
- * | | |Software cannot feed data to the TDES/DES engine.
- * | | |Otherwise, the flag INBUFERR will be set to 1.
- * |[10] |INBUFERR |TDES/DES In Buffer Error Flag
- * | | |0 = No error.
- * | | |1 = Error happens during feeding data to the TDES/DES engine.
- * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag
- * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
- * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT.
- * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
- * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag
- * | | |0 = TDES/DES output buffer is not full.
- * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT.
- * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full.
- * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag
- * | | |0 = No error.
- * | | |1 = Error happens during getting test result from TDES/DES engine.
- * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag
- * | | |0 = No error.
- * | | |1 = Bus error will stop DMA operation and TDES/DES engine.
- */
- __I uint32_t TDES_STS;
-
- /**
- * TDES0_KEY1H
- * ===================================================================================================
- * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES0_KEY1H;
-
- /**
- * TDES0_KEY1L
- * ===================================================================================================
- * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES0_KEY1L;
-
- /**
- * TDES0_KEY2H
- * ===================================================================================================
- * Offset: 0x210 TDES Key 2 High Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES0_KEY2H;
-
- /**
- * TDES0_KEY2L
- * ===================================================================================================
- * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES0_KEY2L;
-
- /**
- * TDES0_KEY3H
- * ===================================================================================================
- * Offset: 0x218 TDES Key 3 High Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES0_KEY3H;
-
- /**
- * TDES0_KEY3L
- * ===================================================================================================
- * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES0_KEY3L;
-
- /**
- * TDES0_IVH
- * ===================================================================================================
- * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES0_IVH;
-
- /**
- * TDES0_IVL
- * ===================================================================================================
- * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES0_IVL;
-
- /**
- * TDES0_SADDR
- * ===================================================================================================
- * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |TDES/DES DMA Source Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
- * | | |TDES_SADR can be read and written.
- * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES0_SADDR;
-
- /**
- * TDES0_DADDR
- * ===================================================================================================
- * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |TDES/DES DMA Destination Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
- * | | |TDES_DADR can be read and written.
- * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES0_DADDR;
-
- /**
- * TDES0_CNT
- * ===================================================================================================
- * Offset: 0x230 TDES/DES Byte Count Register for Channel 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |TDES/DES Byte Count
- * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
- * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |TDES_CNT can be read and written.
- * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- */
- __IO uint32_t TDES0_CNT;
-
- /**
- * TDES_DATIN
- * ===================================================================================================
- * Offset: 0x234 TDES/DES Engine Input data Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DATIN |TDES/DES Engine Input Port
- * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS.
- * | | |Feed data as INBUFFULL is 0.
- */
- __IO uint32_t TDES_DATIN;
-
- /**
- * TDES_DATOUT
- * ===================================================================================================
- * Offset: 0x238 TDES/DES Engine Output data Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DATOUT |TDES/DES Engine Output Port
- * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS.
- * | | |Get data as OUTBUFEMPTY is 0.
- */
- __I uint32_t TDES_DATOUT;
- uint32_t RESERVE2[3];
-
-
- /**
- * TDES1_KEY1H
- * ===================================================================================================
- * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES1_KEY1H;
-
- /**
- * TDES1_KEY1L
- * ===================================================================================================
- * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES1_KEY1L;
-
- /**
- * TDES1_KEY2H
- * ===================================================================================================
- * Offset: 0x250 TDES Key 2 High Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES1_KEY2H;
-
- /**
- * TDES1_KEY2L
- * ===================================================================================================
- * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES1_KEY2L;
-
- /**
- * TDES1_KEY3H
- * ===================================================================================================
- * Offset: 0x258 TDES Key 3 High Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES1_KEY3H;
-
- /**
- * TDES1_KEY3L
- * ===================================================================================================
- * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES1_KEY3L;
-
- /**
- * TDES1_IVH
- * ===================================================================================================
- * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES1_IVH;
-
- /**
- * TDES1_IVL
- * ===================================================================================================
- * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES1_IVL;
-
- /**
- * TDES1_SADDR
- * ===================================================================================================
- * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |TDES/DES DMA Source Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
- * | | |TDES_SADR can be read and written.
- * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES1_SADDR;
-
- /**
- * TDES1_DADDR
- * ===================================================================================================
- * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |TDES/DES DMA Destination Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
- * | | |TDES_DADR can be read and written.
- * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES1_DADDR;
-
- /**
- * TDES1_CNT
- * ===================================================================================================
- * Offset: 0x270 TDES/DES Byte Count Register for Channel 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |TDES/DES Byte Count
- * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
- * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |TDES_CNT can be read and written.
- * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- */
- __IO uint32_t TDES1_CNT;
- uint32_t RESERVE3[5];
-
-
- /**
- * TDES2_KEY1H
- * ===================================================================================================
- * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES2_KEY1H;
-
- /**
- * TDES2_KEY1L
- * ===================================================================================================
- * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES2_KEY1L;
-
- /**
- * TDES2_KEY2H
- * ===================================================================================================
- * Offset: 0x290 TDES Key 2 High Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES2_KEY2H;
-
- /**
- * TDES2_KEY2L
- * ===================================================================================================
- * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES2_KEY2L;
-
- /**
- * TDES2_KEY3H
- * ===================================================================================================
- * Offset: 0x298 TDES Key 3 High Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES2_KEY3H;
-
- /**
- * TDES2_KEY3L
- * ===================================================================================================
- * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES2_KEY3L;
-
- /**
- * TDES2_IVH
- * ===================================================================================================
- * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES2_IVH;
-
- /**
- * TDES2_IVL
- * ===================================================================================================
- * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES2_IVL;
-
- /**
- * TDES2_SADDR
- * ===================================================================================================
- * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |TDES/DES DMA Source Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
- * | | |TDES_SADR can be read and written.
- * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES2_SADDR;
-
- /**
- * TDES2_DADDR
- * ===================================================================================================
- * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |TDES/DES DMA Destination Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
- * | | |TDES_DADR can be read and written.
- * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES2_DADDR;
-
- /**
- * TDES2_CNT
- * ===================================================================================================
- * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |TDES/DES Byte Count
- * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
- * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |TDES_CNT can be read and written.
- * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- */
- __IO uint32_t TDES2_CNT;
- uint32_t RESERVE4[5];
-
-
- /**
- * TDES3_KEY1H
- * ===================================================================================================
- * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES3_KEY1H;
-
- /**
- * TDES3_KEY1L
- * ===================================================================================================
- * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES3_KEY1L;
-
- /**
- * TDES3_KEY2H
- * ===================================================================================================
- * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES3_KEY2H;
-
- /**
- * TDES3_KEY2L
- * ===================================================================================================
- * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES3_KEY2L;
-
- /**
- * TDES3_KEY3H
- * ===================================================================================================
- * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES3_KEY3H;
-
- /**
- * TDES3_KEY3L
- * ===================================================================================================
- * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
- * | | |The key registers for TDES/DES algorithm calculation
- * | | |The security key for the TDES/DES accelerator is 64 bits.
- * | | |Thus, it needs two 32-bit registers to store a security key.
- * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
- */
- __IO uint32_t TDES3_KEY3L;
-
- /**
- * TDES3_IVH
- * ===================================================================================================
- * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES3_IVH;
-
- /**
- * TDES3_IVL
- * ===================================================================================================
- * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
- * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
- * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
- */
- __IO uint32_t TDES3_IVL;
-
- /**
- * TDES3_SADDR
- * ===================================================================================================
- * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |TDES/DES DMA Source Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
- * | | |TDES_SADR can be read and written.
- * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_SADR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES3_SADDR;
-
- /**
- * TDES3_DADDR
- * ===================================================================================================
- * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DADDR |TDES/DES DMA Destination Address
- * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
- * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
- * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
- * | | |The start of destination address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
- * | | |TDES_DADR can be read and written.
- * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_DADR will be updated later on.
- * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
- * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t TDES3_DADDR;
-
- /**
- * TDES3_CNT
- * ===================================================================================================
- * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CNT |TDES/DES Byte Count
- * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
- * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |TDES_CNT can be read and written.
- * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
- * | | |But the value of TDES_CNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
- * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
- */
- __IO uint32_t TDES3_CNT;
- uint32_t RESERVE5[3];
-
-
- /**
- * SHA_CTL
- * ===================================================================================================
- * Offset: 0x300 SHA Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |START |SHA Engine Start
- * | | |0 = No effect.
- * | | |1 = Start SHA engine. BUSY flag will be set.
- * | | |Note: This bit is always 0 when it's read back.
- * |[1] |STOP |SHA Engine Stop
- * | | |0 = No effect.
- * | | |1 = Stop SHA engine.
- * | | |Note: This bit is always 0 when it's read back.
- * |[5] |DMALAST |SHA Last Block
- * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
- * | | |In Non-DMA mode, this bit must be set as feeding in last byte of data.
- * |[7] |DMAEN |SHA Engine DMA Enable Control
- * | | |0 = SHA_DMA engine Disabled.
- * | | |The SHA engine operates in Non-DMA mode, and gets data from the port CRPT_SHA_DATIN.
- * | | |1 = SHA_DMA engine Enabled.
- * | | |The SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
- * |[8:10] |OPMODE |SHA Engine Operation Modes
- * | | |000 = SHA160.
- * | | |100 = SHA256.
- * | | |101 = SHA224.
- * | | |Note: These bits can be read and written, but writing to them wouldn't take effect as BUSY is 1.
- * |[22] |OUTSWAP |SHA Engine Output Data Swap
- * | | |0 = Keep the original order.
- * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
- * |[23] |INSWAP |SHA Engine Input Data Swap
- * | | |0 = Keep the original order.
- * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
- */
- __IO uint32_t SHA_CTL;
-
- /**
- * SHA_STS
- * ===================================================================================================
- * Offset: 0x304 SHA Status Flag
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSY |SHA Engine Busy
- * | | |0 = SHA engine is idle or finished.
- * | | |1 = SHA engine is busy.
- * |[1] |DMABUSY |SHA Engine DMA Busy Flag
- * | | |0 = SHA DMA engine is idle or finished.
- * | | |1 = SHA DMA engine is busy.
- * |[8] |DMAERR |SHA Engine DMA Error Flag
- * | | |0 = Show the SHA engine access normal.
- * | | |1 = Show the SHA engine access error.
- * |[16] |DATINREQ |SHA Non-DMA Mode Data Input Request
- * | | |0 = No effect.
- * | | |1 = Request SHA Non-DMA mode data input.
- */
- __I uint32_t SHA_STS;
-
- /**
- * SHA_DGST0
- * ===================================================================================================
- * Offset: 0x308 SHA Digest Message 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST0;
-
- /**
- * SHA_DGST1
- * ===================================================================================================
- * Offset: 0x30C SHA Digest Message 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST1;
-
- /**
- * SHA_DGST2
- * ===================================================================================================
- * Offset: 0x310 SHA Digest Message 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST2;
-
- /**
- * SHA_DGST3
- * ===================================================================================================
- * Offset: 0x314 SHA Digest Message 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST3;
-
- /**
- * SHA_DGST4
- * ===================================================================================================
- * Offset: 0x318 SHA Digest Message 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST4;
-
- /**
- * SHA_DGST5
- * ===================================================================================================
- * Offset: 0x31C SHA Digest Message 5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST5;
-
- /**
- * SHA_DGST6
- * ===================================================================================================
- * Offset: 0x320 SHA Digest Message 6
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST6;
-
- /**
- * SHA_DGST7
- * ===================================================================================================
- * Offset: 0x324 SHA Digest Message 7
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DGST |SHA Digest Message Word
- * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
- * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
- * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
- */
- __I uint32_t SHA_DGST7;
- uint32_t RESERVE6[8];
-
-
- /**
- * SHA_KEYCNT
- * ===================================================================================================
- * Offset: 0x348 SHA Key Byte Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEYCNT |SHA Key Byte Count
- * | | |The CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates.
- * | | |The register is 32-bit and the maximum byte count is 4G bytes.
- * | | |It can be read and written.
- * | | |Writing to the register CRPT_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation.
- * | | |But the value of SHA _KEY_CNT will be updated later on.
- * | | |Consequently, software can prepare the key count for the next SHA operation.
- */
- __IO uint32_t SHA_KEYCNT;
-
- /**
- * SHA_SADDR
- * ===================================================================================================
- * Offset: 0x34C SHA DMA Source Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SADDR |SHA DMA Source Address
- * | | |The SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
- * | | |The CRPT_SHA_SADDR keeps the source address of the data buffer where the source text is stored.
- * | | |Based on the source address, the SHA accelerator can read the plain text from system memory and do SHA operation.
- * | | |The start of source address should be located at word boundary.
- * | | |In other words, bit 1 and 0 of CRPT_SHA_SADDR are ignored.
- * | | |CRPT_SHA_SADDR can be read and written.
- * | | |Writing to CRPT_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation.
- * | | |But the value of CRPT_SHA_SADDR will be updated later on.
- * | | |Consequently, software can prepare the DMA source address for the next SHA operation.
- * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
- * | | |TDES_SADR and TDES_DADR can be the same in the value.
- */
- __IO uint32_t SHA_SADDR;
-
- /**
- * SHA_DMACNT
- * ===================================================================================================
- * Offset: 0x350 SHA Byte Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DMACNT |SHA Operation Byte Count
- * | | |The CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode.
- * | | |The CRPT_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
- * | | |CRPT_SHA_DMACNT can be read and written.
- * | | |Writing to CRPT_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation.
- * | | |But the value of CRPT_SHA_DMACNT will be updated later on.
- * | | |Consequently, software can prepare the byte count of data for the next SHA operation.
- * | | |In Non-DMA mode, CRPT_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
- */
- __IO uint32_t SHA_DMACNT;
-
- /**
- * SHA_DATIN
- * ===================================================================================================
- * Offset: 0x354 SHA Engine Non-DMA Mode Data Input Port Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DATIN |SHA Engine Input Port
- * | | |CPU feeds data to SHA engine through this port by checking CRPT_SHA_STS. Feed data as DATINREQ is 1.
- */
- __IO uint32_t SHA_DATIN;
-
-} CRPT_T;
-
-/**
- @addtogroup CRPT_CONST CRPT Bit Field Definition
- Constant Definitions for CRPT Controller
-@{ */
-
-#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT INTEN: AESIEN Position */
-#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT INTEN: AESIEN Mask */
-
-#define CRPT_INTEN_AESERRIEN_Pos (1) /*!< CRPT INTEN: AESERRIEN Position */
-#define CRPT_INTEN_AESERRIEN_Msk (0x1ul << CRPT_INTEN_AESERRIEN_Pos) /*!< CRPT INTEN: AESERRIEN Mask */
-
-#define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT INTEN: TDESIEN Position */
-#define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT INTEN: TDESIEN Mask */
-
-#define CRPT_INTEN_TDESERRIEN_Pos (9) /*!< CRPT INTEN: TDESERRIEN Position */
-#define CRPT_INTEN_TDESERRIEN_Msk (0x1ul << CRPT_INTEN_TDESERRIEN_Pos) /*!< CRPT INTEN: TDESERRIEN Mask */
-
-#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT INTEN: PRNGIEN Position */
-#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT INTEN: PRNGIEN Mask */
-
-#define CRPT_INTEN_SHAIEN_Pos (24) /*!< CRPT INTEN: SHAIEN Position */
-#define CRPT_INTEN_SHAIEN_Msk (0x1ul << CRPT_INTEN_SHAIEN_Pos) /*!< CRPT INTEN: SHAIEN Mask */
-
-#define CRPT_INTEN_SHAERRIEN_Pos (25) /*!< CRPT INTEN: SHAERRIEN Position */
-#define CRPT_INTEN_SHAERRIEN_Msk (0x1ul << CRPT_INTEN_SHAERRIEN_Pos) /*!< CRPT INTEN: SHAERRIEN Mask */
-
-#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT INTSTS: AESIF Position */
-#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT INTSTS: AESIF Mask */
-
-#define CRPT_INTSTS_AESERRIF_Pos (1) /*!< CRPT INTSTS: AESERRIF Position */
-#define CRPT_INTSTS_AESERRIF_Msk (0x1ul << CRPT_INTSTS_AESERRIF_Pos) /*!< CRPT INTSTS: AESERRIF Mask */
-
-#define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT INTSTS: TDESIF Position */
-#define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT INTSTS: TDESIF Mask */
-
-#define CRPT_INTSTS_TDESERRIF_Pos (9) /*!< CRPT INTSTS: TDESERRIF Position */
-#define CRPT_INTSTS_TDESERRIF_Msk (0x1ul << CRPT_INTSTS_TDESERRIF_Pos) /*!< CRPT INTSTS: TDESERRIF Mask */
-
-#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT INTSTS: PRNGIF Position */
-#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT INTSTS: PRNGIF Mask */
-
-#define CRPT_INTSTS_SHAIF_Pos (24) /*!< CRPT INTSTS: SHAIF Position */
-#define CRPT_INTSTS_SHAIF_Msk (0x1ul << CRPT_INTSTS_SHAIF_Pos) /*!< CRPT INTSTS: SHAIF Mask */
-
-#define CRPT_INTSTS_SHAERRIF_Pos (25) /*!< CRPT INTSTS: SHAERRIF Position */
-#define CRPT_INTSTS_SHAERRIF_Msk (0x1ul << CRPT_INTSTS_SHAERRIF_Pos) /*!< CRPT INTSTS: SHAERRIF Mask */
-
-#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT PRNG_CTL: START Position */
-#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT PRNG_CTL: START Mask */
-
-#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT PRNG_CTL: SEEDRLD Position */
-#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT PRNG_CTL: SEEDRLD Mask */
-
-#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT PRNG_CTL: KEYSZ Position */
-#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT PRNG_CTL: KEYSZ Mask */
-
-#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT PRNG_CTL: BUSY Position */
-#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT PRNG_CTL: BUSY Mask */
-
-#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT PRNG_SEED: SEED Position */
-#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT PRNG_SEED: SEED Mask */
-
-#define CRPT_PRNG_KEY0_KEY_Pos (0) /*!< CRPT PRNG_KEY0: KEY Position */
-#define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /*!< CRPT PRNG_KEY0: KEY Mask */
-
-#define CRPT_PRNG_KEY1_KEY_Pos (0) /*!< CRPT PRNG_KEY1: KEY Position */
-#define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /*!< CRPT PRNG_KEY1: KEY Mask */
-
-#define CRPT_PRNG_KEY2_KEY_Pos (0) /*!< CRPT PRNG_KEY2: KEY Position */
-#define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /*!< CRPT PRNG_KEY2: KEY Mask */
-
-#define CRPT_PRNG_KEY3_KEY_Pos (0) /*!< CRPT PRNG_KEY3: KEY Position */
-#define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /*!< CRPT PRNG_KEY3: KEY Mask */
-
-#define CRPT_PRNG_KEY4_KEY_Pos (0) /*!< CRPT PRNG_KEY4: KEY Position */
-#define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /*!< CRPT PRNG_KEY4: KEY Mask */
-
-#define CRPT_PRNG_KEY5_KEY_Pos (0) /*!< CRPT PRNG_KEY5: KEY Position */
-#define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /*!< CRPT PRNG_KEY5: KEY Mask */
-
-#define CRPT_PRNG_KEY6_KEY_Pos (0) /*!< CRPT PRNG_KEY6: KEY Position */
-#define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /*!< CRPT PRNG_KEY6: KEY Mask */
-
-#define CRPT_PRNG_KEY7_KEY_Pos (0) /*!< CRPT PRNG_KEY7: KEY Position */
-#define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /*!< CRPT PRNG_KEY7: KEY Mask */
-
-#define CRPT_AES_FDBCK0_FDBCK_Pos (0) /*!< CRPT AES_FDBCK0: FDBCK Position */
-#define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /*!< CRPT AES_FDBCK0: FDBCK Mask */
-
-#define CRPT_AES_FDBCK1_FDBCK_Pos (0) /*!< CRPT AES_FDBCK1: FDBCK Position */
-#define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /*!< CRPT AES_FDBCK1: FDBCK Mask */
-
-#define CRPT_AES_FDBCK2_FDBCK_Pos (0) /*!< CRPT AES_FDBCK2: FDBCK Position */
-#define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /*!< CRPT AES_FDBCK2: FDBCK Mask */
-
-#define CRPT_AES_FDBCK3_FDBCK_Pos (0) /*!< CRPT AES_FDBCK3: FDBCK Position */
-#define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /*!< CRPT AES_FDBCK3: FDBCK Mask */
-
-#define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT TDES_FDBCKH: FDBCK Position */
-#define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT TDES_FDBCKH: FDBCK Mask */
-
-#define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT TDES_FDBCKL: FDBCK Position */
-#define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT TDES_FDBCKL: FDBCK Mask */
-
-#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT AES_CTL: START Position */
-#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT AES_CTL: START Mask */
-
-#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT AES_CTL: STOP Position */
-#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT AES_CTL: STOP Mask */
-
-#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT AES_CTL: KEYSZ Position */
-#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT AES_CTL: KEYSZ Mask */
-
-#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT AES_CTL: DMALAST Position */
-#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT AES_CTL: DMALAST Mask */
-
-#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT AES_CTL: DMACSCAD Position */
-#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT AES_CTL: DMACSCAD Mask */
-
-#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT AES_CTL: DMAEN Position */
-#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT AES_CTL: DMAEN Mask */
-
-#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT AES_CTL: OPMODE Position */
-#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT AES_CTL: OPMODE Mask */
-
-#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT AES_CTL: ENCRPT Position */
-#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT AES_CTL: ENCRPT Mask */
-
-#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT AES_CTL: OUTSWAP Position */
-#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT AES_CTL: OUTSWAP Mask */
-
-#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT AES_CTL: INSWAP Position */
-#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT AES_CTL: INSWAP Mask */
-
-#define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT AES_CTL: CHANNEL Position */
-#define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT AES_CTL: CHANNEL Mask */
-
-#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT AES_CTL: KEYUNPRT Position */
-#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT AES_CTL: KEYUNPRT Mask */
-
-#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT AES_CTL: KEYPRT Position */
-#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT AES_CTL: KEYPRT Mask */
-
-#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT AES_STS: BUSY Position */
-#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT AES_STS: BUSY Mask */
-
-#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT AES_STS: INBUFEMPTY Position */
-#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT AES_STS: INBUFEMPTY Mask */
-
-#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT AES_STS: INBUFFULL Position */
-#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT AES_STS: INBUFFULL Mask */
-
-#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT AES_STS: INBUFERR Position */
-#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT AES_STS: INBUFERR Mask */
-
-#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT AES_STS: CNTERR Position */
-#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT AES_STS: CNTERR Mask */
-
-#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT AES_STS: OUTBUFEMPTY Position */
-#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT AES_STS: OUTBUFEMPTY Mask */
-
-#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT AES_STS: OUTBUFFULL Position */
-#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT AES_STS: OUTBUFFULL Mask */
-
-#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT AES_STS: OUTBUFERR Position */
-#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT AES_STS: OUTBUFERR Mask */
-
-#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT AES_STS: BUSERR Position */
-#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT AES_STS: BUSERR Mask */
-
-#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT AES_DATIN: DATIN Position */
-#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT AES_DATIN: DATIN Mask */
-
-#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT AES_DATOUT: DATOUT Position */
-#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT AES_DATOUT: DATOUT Mask */
-
-#define CRPT_AES0_KEY0_KEY_Pos (0) /*!< CRPT AES0_KEY0: KEY Position */
-#define CRPT_AES0_KEY0_KEY_Msk (0xfffffffful << CRPT_AES0_KEY0_KEY_Pos) /*!< CRPT AES0_KEY0: KEY Mask */
-
-#define CRPT_AES0_KEY1_KEY_Pos (0) /*!< CRPT AES0_KEY1: KEY Position */
-#define CRPT_AES0_KEY1_KEY_Msk (0xfffffffful << CRPT_AES0_KEY1_KEY_Pos) /*!< CRPT AES0_KEY1: KEY Mask */
-
-#define CRPT_AES0_KEY2_KEY_Pos (0) /*!< CRPT AES0_KEY2: KEY Position */
-#define CRPT_AES0_KEY2_KEY_Msk (0xfffffffful << CRPT_AES0_KEY2_KEY_Pos) /*!< CRPT AES0_KEY2: KEY Mask */
-
-#define CRPT_AES0_KEY3_KEY_Pos (0) /*!< CRPT AES0_KEY3: KEY Position */
-#define CRPT_AES0_KEY3_KEY_Msk (0xfffffffful << CRPT_AES0_KEY3_KEY_Pos) /*!< CRPT AES0_KEY3: KEY Mask */
-
-#define CRPT_AES0_KEY4_KEY_Pos (0) /*!< CRPT AES0_KEY4: KEY Position */
-#define CRPT_AES0_KEY4_KEY_Msk (0xfffffffful << CRPT_AES0_KEY4_KEY_Pos) /*!< CRPT AES0_KEY4: KEY Mask */
-
-#define CRPT_AES0_KEY5_KEY_Pos (0) /*!< CRPT AES0_KEY5: KEY Position */
-#define CRPT_AES0_KEY5_KEY_Msk (0xfffffffful << CRPT_AES0_KEY5_KEY_Pos) /*!< CRPT AES0_KEY5: KEY Mask */
-
-#define CRPT_AES0_KEY6_KEY_Pos (0) /*!< CRPT AES0_KEY6: KEY Position */
-#define CRPT_AES0_KEY6_KEY_Msk (0xfffffffful << CRPT_AES0_KEY6_KEY_Pos) /*!< CRPT AES0_KEY6: KEY Mask */
-
-#define CRPT_AES0_KEY7_KEY_Pos (0) /*!< CRPT AES0_KEY7: KEY Position */
-#define CRPT_AES0_KEY7_KEY_Msk (0xfffffffful << CRPT_AES0_KEY7_KEY_Pos) /*!< CRPT AES0_KEY7: KEY Mask */
-
-#define CRPT_AES0_IV0_IV_Pos (0) /*!< CRPT AES0_IV0: IV Position */
-#define CRPT_AES0_IV0_IV_Msk (0xfffffffful << CRPT_AES0_IV0_IV_Pos) /*!< CRPT AES0_IV0: IV Mask */
-
-#define CRPT_AES0_IV1_IV_Pos (0) /*!< CRPT AES0_IV1: IV Position */
-#define CRPT_AES0_IV1_IV_Msk (0xfffffffful << CRPT_AES0_IV1_IV_Pos) /*!< CRPT AES0_IV1: IV Mask */
-
-#define CRPT_AES0_IV2_IV_Pos (0) /*!< CRPT AES0_IV2: IV Position */
-#define CRPT_AES0_IV2_IV_Msk (0xfffffffful << CRPT_AES0_IV2_IV_Pos) /*!< CRPT AES0_IV2: IV Mask */
-
-#define CRPT_AES0_IV3_IV_Pos (0) /*!< CRPT AES0_IV3: IV Position */
-#define CRPT_AES0_IV3_IV_Msk (0xfffffffful << CRPT_AES0_IV3_IV_Pos) /*!< CRPT AES0_IV3: IV Mask */
-
-#define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT AES0_SADDR: SADDR Position */
-#define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT AES0_SADDR: SADDR Mask */
-
-#define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT AES0_DADDR: DADDR Position */
-#define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT AES0_DADDR: DADDR Mask */
-
-#define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT AES0_CNT: CNT Position */
-#define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT AES0_CNT: CNT Mask */
-
-#define CRPT_AES1_KEY0_KEY_Pos (0) /*!< CRPT AES1_KEY0: KEY Position */
-#define CRPT_AES1_KEY0_KEY_Msk (0xfffffffful << CRPT_AES1_KEY0_KEY_Pos) /*!< CRPT AES1_KEY0: KEY Mask */
-
-#define CRPT_AES1_KEY1_KEY_Pos (0) /*!< CRPT AES1_KEY1: KEY Position */
-#define CRPT_AES1_KEY1_KEY_Msk (0xfffffffful << CRPT_AES1_KEY1_KEY_Pos) /*!< CRPT AES1_KEY1: KEY Mask */
-
-#define CRPT_AES1_KEY2_KEY_Pos (0) /*!< CRPT AES1_KEY2: KEY Position */
-#define CRPT_AES1_KEY2_KEY_Msk (0xfffffffful << CRPT_AES1_KEY2_KEY_Pos) /*!< CRPT AES1_KEY2: KEY Mask */
-
-#define CRPT_AES1_KEY3_KEY_Pos (0) /*!< CRPT AES1_KEY3: KEY Position */
-#define CRPT_AES1_KEY3_KEY_Msk (0xfffffffful << CRPT_AES1_KEY3_KEY_Pos) /*!< CRPT AES1_KEY3: KEY Mask */
-
-#define CRPT_AES1_KEY4_KEY_Pos (0) /*!< CRPT AES1_KEY4: KEY Position */
-#define CRPT_AES1_KEY4_KEY_Msk (0xfffffffful << CRPT_AES1_KEY4_KEY_Pos) /*!< CRPT AES1_KEY4: KEY Mask */
-
-#define CRPT_AES1_KEY5_KEY_Pos (0) /*!< CRPT AES1_KEY5: KEY Position */
-#define CRPT_AES1_KEY5_KEY_Msk (0xfffffffful << CRPT_AES1_KEY5_KEY_Pos) /*!< CRPT AES1_KEY5: KEY Mask */
-
-#define CRPT_AES1_KEY6_KEY_Pos (0) /*!< CRPT AES1_KEY6: KEY Position */
-#define CRPT_AES1_KEY6_KEY_Msk (0xfffffffful << CRPT_AES1_KEY6_KEY_Pos) /*!< CRPT AES1_KEY6: KEY Mask */
-
-#define CRPT_AES1_KEY7_KEY_Pos (0) /*!< CRPT AES1_KEY7: KEY Position */
-#define CRPT_AES1_KEY7_KEY_Msk (0xfffffffful << CRPT_AES1_KEY7_KEY_Pos) /*!< CRPT AES1_KEY7: KEY Mask */
-
-#define CRPT_AES1_IV0_IV_Pos (0) /*!< CRPT AES1_IV0: IV Position */
-#define CRPT_AES1_IV0_IV_Msk (0xfffffffful << CRPT_AES1_IV0_IV_Pos) /*!< CRPT AES1_IV0: IV Mask */
-
-#define CRPT_AES1_IV1_IV_Pos (0) /*!< CRPT AES1_IV1: IV Position */
-#define CRPT_AES1_IV1_IV_Msk (0xfffffffful << CRPT_AES1_IV1_IV_Pos) /*!< CRPT AES1_IV1: IV Mask */
-
-#define CRPT_AES1_IV2_IV_Pos (0) /*!< CRPT AES1_IV2: IV Position */
-#define CRPT_AES1_IV2_IV_Msk (0xfffffffful << CRPT_AES1_IV2_IV_Pos) /*!< CRPT AES1_IV2: IV Mask */
-
-#define CRPT_AES1_IV3_IV_Pos (0) /*!< CRPT AES1_IV3: IV Position */
-#define CRPT_AES1_IV3_IV_Msk (0xfffffffful << CRPT_AES1_IV3_IV_Pos) /*!< CRPT AES1_IV3: IV Mask */
-
-#define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT AES1_SADDR: SADDR Position */
-#define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT AES1_SADDR: SADDR Mask */
-
-#define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT AES1_DADDR: DADDR Position */
-#define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT AES1_DADDR: DADDR Mask */
-
-#define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT AES1_CNT: CNT Position */
-#define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT AES1_CNT: CNT Mask */
-
-#define CRPT_AES2_KEY0_KEY_Pos (0) /*!< CRPT AES2_KEY0: KEY Position */
-#define CRPT_AES2_KEY0_KEY_Msk (0xfffffffful << CRPT_AES2_KEY0_KEY_Pos) /*!< CRPT AES2_KEY0: KEY Mask */
-
-#define CRPT_AES2_KEY1_KEY_Pos (0) /*!< CRPT AES2_KEY1: KEY Position */
-#define CRPT_AES2_KEY1_KEY_Msk (0xfffffffful << CRPT_AES2_KEY1_KEY_Pos) /*!< CRPT AES2_KEY1: KEY Mask */
-
-#define CRPT_AES2_KEY2_KEY_Pos (0) /*!< CRPT AES2_KEY2: KEY Position */
-#define CRPT_AES2_KEY2_KEY_Msk (0xfffffffful << CRPT_AES2_KEY2_KEY_Pos) /*!< CRPT AES2_KEY2: KEY Mask */
-
-#define CRPT_AES2_KEY3_KEY_Pos (0) /*!< CRPT AES2_KEY3: KEY Position */
-#define CRPT_AES2_KEY3_KEY_Msk (0xfffffffful << CRPT_AES2_KEY3_KEY_Pos) /*!< CRPT AES2_KEY3: KEY Mask */
-
-#define CRPT_AES2_KEY4_KEY_Pos (0) /*!< CRPT AES2_KEY4: KEY Position */
-#define CRPT_AES2_KEY4_KEY_Msk (0xfffffffful << CRPT_AES2_KEY4_KEY_Pos) /*!< CRPT AES2_KEY4: KEY Mask */
-
-#define CRPT_AES2_KEY5_KEY_Pos (0) /*!< CRPT AES2_KEY5: KEY Position */
-#define CRPT_AES2_KEY5_KEY_Msk (0xfffffffful << CRPT_AES2_KEY5_KEY_Pos) /*!< CRPT AES2_KEY5: KEY Mask */
-
-#define CRPT_AES2_KEY6_KEY_Pos (0) /*!< CRPT AES2_KEY6: KEY Position */
-#define CRPT_AES2_KEY6_KEY_Msk (0xfffffffful << CRPT_AES2_KEY6_KEY_Pos) /*!< CRPT AES2_KEY6: KEY Mask */
-
-#define CRPT_AES2_KEY7_KEY_Pos (0) /*!< CRPT AES2_KEY7: KEY Position */
-#define CRPT_AES2_KEY7_KEY_Msk (0xfffffffful << CRPT_AES2_KEY7_KEY_Pos) /*!< CRPT AES2_KEY7: KEY Mask */
-
-#define CRPT_AES2_IV0_IV_Pos (0) /*!< CRPT AES2_IV0: IV Position */
-#define CRPT_AES2_IV0_IV_Msk (0xfffffffful << CRPT_AES2_IV0_IV_Pos) /*!< CRPT AES2_IV0: IV Mask */
-
-#define CRPT_AES2_IV1_IV_Pos (0) /*!< CRPT AES2_IV1: IV Position */
-#define CRPT_AES2_IV1_IV_Msk (0xfffffffful << CRPT_AES2_IV1_IV_Pos) /*!< CRPT AES2_IV1: IV Mask */
-
-#define CRPT_AES2_IV2_IV_Pos (0) /*!< CRPT AES2_IV2: IV Position */
-#define CRPT_AES2_IV2_IV_Msk (0xfffffffful << CRPT_AES2_IV2_IV_Pos) /*!< CRPT AES2_IV2: IV Mask */
-
-#define CRPT_AES2_IV3_IV_Pos (0) /*!< CRPT AES2_IV3: IV Position */
-#define CRPT_AES2_IV3_IV_Msk (0xfffffffful << CRPT_AES2_IV3_IV_Pos) /*!< CRPT AES2_IV3: IV Mask */
-
-#define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT AES2_SADDR: SADDR Position */
-#define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT AES2_SADDR: SADDR Mask */
-
-#define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT AES2_DADDR: DADDR Position */
-#define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT AES2_DADDR: DADDR Mask */
-
-#define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT AES2_CNT: CNT Position */
-#define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT AES2_CNT: CNT Mask */
-
-#define CRPT_AES3_KEY0_KEY_Pos (0) /*!< CRPT AES3_KEY0: KEY Position */
-#define CRPT_AES3_KEY0_KEY_Msk (0xfffffffful << CRPT_AES3_KEY0_KEY_Pos) /*!< CRPT AES3_KEY0: KEY Mask */
-
-#define CRPT_AES3_KEY1_KEY_Pos (0) /*!< CRPT AES3_KEY1: KEY Position */
-#define CRPT_AES3_KEY1_KEY_Msk (0xfffffffful << CRPT_AES3_KEY1_KEY_Pos) /*!< CRPT AES3_KEY1: KEY Mask */
-
-#define CRPT_AES3_KEY2_KEY_Pos (0) /*!< CRPT AES3_KEY2: KEY Position */
-#define CRPT_AES3_KEY2_KEY_Msk (0xfffffffful << CRPT_AES3_KEY2_KEY_Pos) /*!< CRPT AES3_KEY2: KEY Mask */
-
-#define CRPT_AES3_KEY3_KEY_Pos (0) /*!< CRPT AES3_KEY3: KEY Position */
-#define CRPT_AES3_KEY3_KEY_Msk (0xfffffffful << CRPT_AES3_KEY3_KEY_Pos) /*!< CRPT AES3_KEY3: KEY Mask */
-
-#define CRPT_AES3_KEY4_KEY_Pos (0) /*!< CRPT AES3_KEY4: KEY Position */
-#define CRPT_AES3_KEY4_KEY_Msk (0xfffffffful << CRPT_AES3_KEY4_KEY_Pos) /*!< CRPT AES3_KEY4: KEY Mask */
-
-#define CRPT_AES3_KEY5_KEY_Pos (0) /*!< CRPT AES3_KEY5: KEY Position */
-#define CRPT_AES3_KEY5_KEY_Msk (0xfffffffful << CRPT_AES3_KEY5_KEY_Pos) /*!< CRPT AES3_KEY5: KEY Mask */
-
-#define CRPT_AES3_KEY6_KEY_Pos (0) /*!< CRPT AES3_KEY6: KEY Position */
-#define CRPT_AES3_KEY6_KEY_Msk (0xfffffffful << CRPT_AES3_KEY6_KEY_Pos) /*!< CRPT AES3_KEY6: KEY Mask */
-
-#define CRPT_AES3_KEY7_KEY_Pos (0) /*!< CRPT AES3_KEY7: KEY Position */
-#define CRPT_AES3_KEY7_KEY_Msk (0xfffffffful << CRPT_AES3_KEY7_KEY_Pos) /*!< CRPT AES3_KEY7: KEY Mask */
-
-#define CRPT_AES3_IV0_IV_Pos (0) /*!< CRPT AES3_IV0: IV Position */
-#define CRPT_AES3_IV0_IV_Msk (0xfffffffful << CRPT_AES3_IV0_IV_Pos) /*!< CRPT AES3_IV0: IV Mask */
-
-#define CRPT_AES3_IV1_IV_Pos (0) /*!< CRPT AES3_IV1: IV Position */
-#define CRPT_AES3_IV1_IV_Msk (0xfffffffful << CRPT_AES3_IV1_IV_Pos) /*!< CRPT AES3_IV1: IV Mask */
-
-#define CRPT_AES3_IV2_IV_Pos (0) /*!< CRPT AES3_IV2: IV Position */
-#define CRPT_AES3_IV2_IV_Msk (0xfffffffful << CRPT_AES3_IV2_IV_Pos) /*!< CRPT AES3_IV2: IV Mask */
-
-#define CRPT_AES3_IV3_IV_Pos (0) /*!< CRPT AES3_IV3: IV Position */
-#define CRPT_AES3_IV3_IV_Msk (0xfffffffful << CRPT_AES3_IV3_IV_Pos) /*!< CRPT AES3_IV3: IV Mask */
-
-#define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT AES3_SADDR: SADDR Position */
-#define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT AES3_SADDR: SADDR Mask */
-
-#define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT AES3_DADDR: DADDR Position */
-#define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT AES3_DADDR: DADDR Mask */
-
-#define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT AES3_CNT: CNT Position */
-#define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT AES3_CNT: CNT Mask */
-
-#define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT TDES_CTL: START Position */
-#define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT TDES_CTL: START Mask */
-
-#define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT TDES_CTL: STOP Position */
-#define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT TDES_CTL: STOP Mask */
-
-#define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT TDES_CTL: TMODE Position */
-#define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT TDES_CTL: TMODE Mask */
-
-#define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT TDES_CTL: 3KEYS Position */
-#define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT TDES_CTL: 3KEYS Mask */
-
-#define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT TDES_CTL: DMALAST Position */
-#define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT TDES_CTL: DMALAST Mask */
-
-#define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT TDES_CTL: DMACSCAD Position */
-#define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT TDES_CTL: DMACSCAD Mask */
-
-#define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT TDES_CTL: DMAEN Position */
-#define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT TDES_CTL: DMAEN Mask */
-
-#define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT TDES_CTL: OPMODE Position */
-#define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT TDES_CTL: OPMODE Mask */
-
-#define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT TDES_CTL: ENCRPT Position */
-#define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT TDES_CTL: ENCRPT Mask */
-
-#define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT TDES_CTL: BLKSWAP Position */
-#define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT TDES_CTL: BLKSWAP Mask */
-
-#define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT TDES_CTL: OUTSWAP Position */
-#define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT TDES_CTL: OUTSWAP Mask */
-
-#define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT TDES_CTL: INSWAP Position */
-#define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT TDES_CTL: INSWAP Mask */
-
-#define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT TDES_CTL: CHANNEL Position */
-#define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT TDES_CTL: CHANNEL Mask */
-
-#define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT TDES_CTL: KEYUNPRT Position */
-#define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT TDES_CTL: KEYUNPRT Mask */
-
-#define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT TDES_CTL: KEYPRT Position */
-#define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT TDES_CTL: KEYPRT Mask */
-
-#define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT TDES_STS: BUSY Position */
-#define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT TDES_STS: BUSY Mask */
-
-#define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT TDES_STS: INBUFEMPTY Position */
-#define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT TDES_STS: INBUFEMPTY Mask */
-
-#define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT TDES_STS: INBUFFULL Position */
-#define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT TDES_STS: INBUFFULL Mask */
-
-#define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT TDES_STS: INBUFERR Position */
-#define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT TDES_STS: INBUFERR Mask */
-
-#define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT TDES_STS: OUTBUFEMPTY Position */
-#define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT TDES_STS: OUTBUFEMPTY Mask */
-
-#define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT TDES_STS: OUTBUFFULL Position */
-#define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT TDES_STS: OUTBUFFULL Mask */
-
-#define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT TDES_STS: OUTBUFERR Position */
-#define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT TDES_STS: OUTBUFERR Mask */
-
-#define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT TDES_STS: BUSERR Position */
-#define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT TDES_STS: BUSERR Mask */
-
-#define CRPT_TDES0_KEY1H_KEY_Pos (0) /*!< CRPT TDES0_KEY1H: KEY Position */
-#define CRPT_TDES0_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1H_KEY_Pos) /*!< CRPT TDES0_KEY1H: KEY Mask */
-
-#define CRPT_TDES0_KEY1L_KEY_Pos (0) /*!< CRPT TDES0_KEY1L: KEY Position */
-#define CRPT_TDES0_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1L_KEY_Pos) /*!< CRPT TDES0_KEY1L: KEY Mask */
-
-#define CRPT_TDES0_KEY2H_KEY_Pos (0) /*!< CRPT TDES0_KEY2H: KEY Position */
-#define CRPT_TDES0_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2H_KEY_Pos) /*!< CRPT TDES0_KEY2H: KEY Mask */
-
-#define CRPT_TDES0_KEY2L_KEY_Pos (0) /*!< CRPT TDES0_KEY2L: KEY Position */
-#define CRPT_TDES0_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2L_KEY_Pos) /*!< CRPT TDES0_KEY2L: KEY Mask */
-
-#define CRPT_TDES0_KEY3H_KEY_Pos (0) /*!< CRPT TDES0_KEY3H: KEY Position */
-#define CRPT_TDES0_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3H_KEY_Pos) /*!< CRPT TDES0_KEY3H: KEY Mask */
-
-#define CRPT_TDES0_KEY3L_KEY_Pos (0) /*!< CRPT TDES0_KEY3L: KEY Position */
-#define CRPT_TDES0_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3L_KEY_Pos) /*!< CRPT TDES0_KEY3L: KEY Mask */
-
-#define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT TDES0_IVH: IV Position */
-#define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT TDES0_IVH: IV Mask */
-
-#define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT TDES0_IVL: IV Position */
-#define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT TDES0_IVL: IV Mask */
-
-#define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT TDES0_SADDR: SADDR Position */
-#define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT TDES0_SADDR: SADDR Mask */
-
-#define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT TDES0_DADDR: DADDR Position */
-#define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT TDES0_DADDR: DADDR Mask */
-
-#define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT TDES0_CNT: CNT Position */
-#define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT TDES0_CNT: CNT Mask */
-
-#define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT TDES_DATIN: DATIN Position */
-#define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT TDES_DATIN: DATIN Mask */
-
-#define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT TDES_DATOUT: DATOUT Position */
-#define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT TDES_DATOUT: DATOUT Mask */
-
-#define CRPT_TDES1_KEY1H_KEY_Pos (0) /*!< CRPT TDES1_KEY1H: KEY Position */
-#define CRPT_TDES1_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1H_KEY_Pos) /*!< CRPT TDES1_KEY1H: KEY Mask */
-
-#define CRPT_TDES1_KEY1L_KEYL_Pos (0) /*!< CRPT TDES1_KEY1L: KEY Position */
-#define CRPT_TDES1_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT TDES1_KEY1L: KEY Mask */
-
-#define CRPT_TDES1_KEY2H_KEY_Pos (0) /*!< CRPT TDES1_KEY2H: KEY Position */
-#define CRPT_TDES1_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2H_KEY_Pos) /*!< CRPT TDES1_KEY2H: KEY Mask */
-
-#define CRPT_TDES1_KEY2L_KEY_Pos (0) /*!< CRPT TDES1_KEY2L: KEY Position */
-#define CRPT_TDES1_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2L_KEY_Pos) /*!< CRPT TDES1_KEY2L: KEY Mask */
-
-#define CRPT_TDES1_KEY3H_KEY_Pos (0) /*!< CRPT TDES1_KEY3H: KEY Position */
-#define CRPT_TDES1_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3H_KEY_Pos) /*!< CRPT TDES1_KEY3H: KEY Mask */
-
-#define CRPT_TDES1_KEY3L_KEY_Pos (0) /*!< CRPT TDES1_KEY3L: KEY Position */
-#define CRPT_TDES1_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3L_KEY_Pos) /*!< CRPT TDES1_KEY3L: KEY Mask */
-
-#define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT TDES1_IVH: IV Position */
-#define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT TDES1_IVH: IV Mask */
-
-#define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT TDES1_IVL: IV Position */
-#define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT TDES1_IVL: IV Mask */
-
-#define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT TDES1_SADDR: SADDR Position */
-#define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT TDES1_SADDR: SADDR Mask */
-
-#define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT TDES1_DADDR: DADDR Position */
-#define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT TDES1_DADDR: DADDR Mask */
-
-#define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT TDES1_CNT: CNT Position */
-#define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT TDES1_CNT: CNT Mask */
-
-#define CRPT_TDES2_KEY1H_KEY_Pos (0) /*!< CRPT TDES2_KEY1H: KEY Position */
-#define CRPT_TDES2_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1H_KEY_Pos) /*!< CRPT TDES2_KEY1H: KEY Mask */
-
-#define CRPT_TDES2_KEY1L_KEY_Pos (0) /*!< CRPT TDES2_KEY1L: KEY Position */
-#define CRPT_TDES2_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1L_KEY_Pos) /*!< CRPT TDES2_KEY1L: KEY Mask */
-
-#define CRPT_TDES2_KEY2H_KEY_Pos (0) /*!< CRPT TDES2_KEY2H: KEY Position */
-#define CRPT_TDES2_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2H_KEY_Pos) /*!< CRPT TDES2_KEY2H: KEY Mask */
-
-#define CRPT_TDES2_KEY2L_KEY_Pos (0) /*!< CRPT TDES2_KEY2L: KEY Position */
-#define CRPT_TDES2_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2L_KEY_Pos) /*!< CRPT TDES2_KEY2L: KEY Mask */
-
-#define CRPT_TDES2_KEY3H_KEY_Pos (0) /*!< CRPT TDES2_KEY3H: KEY Position */
-#define CRPT_TDES2_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3H_KEY_Pos) /*!< CRPT TDES2_KEY3H: KEY Mask */
-
-#define CRPT_TDES2_KEY3L_KEY_Pos (0) /*!< CRPT TDES2_KEY3L: KEY Position */
-#define CRPT_TDES2_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3L_KEY_Pos) /*!< CRPT TDES2_KEY3L: KEY Mask */
-
-#define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT TDES2_IVH: IV Position */
-#define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT TDES2_IVH: IV Mask */
-
-#define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT TDES2_IVL: IV Position */
-#define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT TDES2_IVL: IV Mask */
-
-#define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT TDES2_SADDR: SADDR Position */
-#define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT TDES2_SADDR: SADDR Mask */
-
-#define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT TDES2_DADDR: DADDR Position */
-#define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT TDES2_DADDR: DADDR Mask */
-
-#define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT TDES2_CNT: CNT Position */
-#define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT TDES2_CNT: CNT Mask */
-
-#define CRPT_TDES3_KEY1H_KEY_Pos (0) /*!< CRPT TDES3_KEY1H: KEY Position */
-#define CRPT_TDES3_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1H_KEY_Pos) /*!< CRPT TDES3_KEY1H: KEY Mask */
-
-#define CRPT_TDES3_KEY1L_KEY_Pos (0) /*!< CRPT TDES3_KEY1L: KEY Position */
-#define CRPT_TDES3_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1L_KEY_Pos) /*!< CRPT TDES3_KEY1L: KEY Mask */
-
-#define CRPT_TDES3_KEY2H_KEY_Pos (0) /*!< CRPT TDES3_KEY2H: KEY Position */
-#define CRPT_TDES3_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2H_KEY_Pos) /*!< CRPT TDES3_KEY2H: KEY Mask */
-
-#define CRPT_TDES3_KEY2L_KEY_Pos (0) /*!< CRPT TDES3_KEY2L: KEY Position */
-#define CRPT_TDES3_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2L_KEY_Pos) /*!< CRPT TDES3_KEY2L: KEY Mask */
-
-#define CRPT_TDES3_KEY3H_KEY_Pos (0) /*!< CRPT TDES3_KEY3H: KEY Position */
-#define CRPT_TDES3_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3H_KEY_Pos) /*!< CRPT TDES3_KEY3H: KEY Mask */
-
-#define CRPT_TDES3_KEY3L_KEY_Pos (0) /*!< CRPT TDES3_KEY3L: KEY Position */
-#define CRPT_TDES3_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3L_KEY_Pos) /*!< CRPT TDES3_KEY3L: KEY Mask */
-
-#define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT TDES3_IVH: IV Position */
-#define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT TDES3_IVH: IV Mask */
-
-#define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT TDES3_IVL: IV Position */
-#define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT TDES3_IVL: IV Mask */
-
-#define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT TDES3_SADDR: SADDR Position */
-#define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT TDES3_SADDR: SADDR Mask */
-
-#define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT TDES3_DADDR: DADDR Position */
-#define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT TDES3_DADDR: DADDR Mask */
-
-#define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT TDES3_CNT: CNT Position */
-#define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT TDES3_CNT: CNT Mask */
-
-#define CRPT_SHA_CTL_START_Pos (0) /*!< CRPT SHA_CTL: START Position */
-#define CRPT_SHA_CTL_START_Msk (0x1ul << CRPT_SHA_CTL_START_Pos) /*!< CRPT SHA_CTL: START Mask */
-
-#define CRPT_SHA_CTL_STOP_Pos (1) /*!< CRPT SHA_CTL: STOP Position */
-#define CRPT_SHA_CTL_STOP_Msk (0x1ul << CRPT_SHA_CTL_STOP_Pos) /*!< CRPT SHA_CTL: STOP Mask */
-
-#define CRPT_SHA_CTL_DMALAST_Pos (5) /*!< CRPT SHA_CTL: DMALAST Position */
-#define CRPT_SHA_CTL_DMALAST_Msk (0x1ul << CRPT_SHA_CTL_DMALAST_Pos) /*!< CRPT SHA_CTL: DMALAST Mask */
-
-#define CRPT_SHA_CTL_DMAEN_Pos (7) /*!< CRPT SHA_CTL: DMAEN Position */
-#define CRPT_SHA_CTL_DMAEN_Msk (0x1ul << CRPT_SHA_CTL_DMAEN_Pos) /*!< CRPT SHA_CTL: DMAEN Mask */
-
-#define CRPT_SHA_CTL_OPMODE_Pos (8) /*!< CRPT SHA_CTL: OPMODE Position */
-#define CRPT_SHA_CTL_OPMODE_Msk (0x7ul << CRPT_SHA_CTL_OPMODE_Pos) /*!< CRPT SHA_CTL: OPMODE Mask */
-
-#define CRPT_SHA_CTL_OUTSWAP_Pos (22) /*!< CRPT SHA_CTL: OUTSWAP Position */
-#define CRPT_SHA_CTL_OUTSWAP_Msk (0x1ul << CRPT_SHA_CTL_OUTSWAP_Pos) /*!< CRPT SHA_CTL: OUTSWAP Mask */
-
-#define CRPT_SHA_CTL_INSWAP_Pos (23) /*!< CRPT SHA_CTL: INSWAP Position */
-#define CRPT_SHA_CTL_INSWAP_Msk (0x1ul << CRPT_SHA_CTL_INSWAP_Pos) /*!< CRPT SHA_CTL: INSWAP Mask */
-
-#define CRPT_SHA_STS_BUSY_Pos (0) /*!< CRPT SHA_STS: BUSY Position */
-#define CRPT_SHA_STS_BUSY_Msk (0x1ul << CRPT_SHA_STS_BUSY_Pos) /*!< CRPT SHA_STS: BUSY Mask */
-
-#define CRPT_SHA_STS_DMABUSY_Pos (1) /*!< CRPT SHA_STS: DMABUSY Position */
-#define CRPT_SHA_STS_DMABUSY_Msk (0x1ul << CRPT_SHA_STS_DMABUSY_Pos) /*!< CRPT SHA_STS: DMABUSY Mask */
-
-#define CRPT_SHA_STS_DMAERR_Pos (8) /*!< CRPT SHA_STS: DMAERR Position */
-#define CRPT_SHA_STS_DMAERR_Msk (0x1ul << CRPT_SHA_STS_DMAERR_Pos) /*!< CRPT SHA_STS: DMAERR Mask */
-
-#define CRPT_SHA_STS_DATINREQ_Pos (16) /*!< CRPT SHA_STS: DATINREQ Position */
-#define CRPT_SHA_STS_DATINREQ_Msk (0x1ul << CRPT_SHA_STS_DATINREQ_Pos) /*!< CRPT SHA_STS: DATINREQ Mask */
-
-#define CRPT_SHA_DGST0_DGST_Pos (0) /*!< CRPT SHA_DGST0: DGST Position */
-#define CRPT_SHA_DGST0_DGST_Msk (0xfffffffful << CRPT_SHA_DGST0_DGST_Pos) /*!< CRPT SHA_DGST0: DGST Mask */
-
-#define CRPT_SHA_DGST1_DGST_Pos (0) /*!< CRPT SHA_DGST1: DGST Position */
-#define CRPT_SHA_DGST1_DGST_Msk (0xfffffffful << CRPT_SHA_DGST1_DGST_Pos) /*!< CRPT SHA_DGST1: DGST Mask */
-
-#define CRPT_SHA_DGST2_DGST_Pos (0) /*!< CRPT SHA_DGST2: DGST Position */
-#define CRPT_SHA_DGST2_DGST_Msk (0xfffffffful << CRPT_SHA_DGST2_DGST_Pos) /*!< CRPT SHA_DGST2: DGST Mask */
-
-#define CRPT_SHA_DGST3_DGST_Pos (0) /*!< CRPT SHA_DGST3: DGST Position */
-#define CRPT_SHA_DGST3_DGST_Msk (0xfffffffful << CRPT_SHA_DGST3_DGST_Pos) /*!< CRPT SHA_DGST3: DGST Mask */
-
-#define CRPT_SHA_DGST4_DGST_Pos (0) /*!< CRPT SHA_DGST4: DGST Position */
-#define CRPT_SHA_DGST4_DGST_Msk (0xfffffffful << CRPT_SHA_DGST4_DGST_Pos) /*!< CRPT SHA_DGST4: DGST Mask */
-
-#define CRPT_SHA_DGST5_DGST_Pos (0) /*!< CRPT SHA_DGST5: DGST Position */
-#define CRPT_SHA_DGST5_DGST_Msk (0xfffffffful << CRPT_SHA_DGST5_DGST_Pos) /*!< CRPT SHA_DGST5: DGST Mask */
-
-#define CRPT_SHA_DGST6_DGST_Pos (0) /*!< CRPT SHA_DGST6: DGST Position */
-#define CRPT_SHA_DGST6_DGST_Msk (0xfffffffful << CRPT_SHA_DGST6_DGST_Pos) /*!< CRPT SHA_DGST6: DGST Mask */
-
-#define CRPT_SHA_DGST7_DGST_Pos (0) /*!< CRPT SHA_DGST7: DGST Position */
-#define CRPT_SHA_DGST7_DGST_Msk (0xfffffffful << CRPT_SHA_DGST7_DGST_Pos) /*!< CRPT SHA_DGST7: DGST Mask */
-
-#define CRPT_SHA_KEYCNT_KEYCNT_Pos (0) /*!< CRPT SHA_KEYCNT: KEYCNT Position */
-#define CRPT_SHA_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_SHA_KEYCNT_KEYCNT_Pos) /*!< CRPT SHA_KEYCNT: KEYCNT Mask */
-
-#define CRPT_SHA_SADDR_SADDR_Pos (0) /*!< CRPT SHA_SADDR: SADDR Position */
-#define CRPT_SHA_SADDR_SADDR_Msk (0xfffffffful << CRPT_SHA_SADDR_SADDR_Pos) /*!< CRPT SHA_SADDR: SADDR Mask */
-
-#define CRPT_SHA_DMACNT_DMACNT_Pos (0) /*!< CRPT SHA_DMACNT: DMACNT Position */
-#define CRPT_SHA_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_SHA_DMACNT_DMACNT_Pos) /*!< CRPT SHA_DMACNT: DMACNT Mask */
-
-#define CRPT_SHA_DATIN_DATIN_Pos (0) /*!< CRPT SHA_DATIN: DATIN Position */
-#define CRPT_SHA_DATIN_DATIN_Msk (0xfffffffful << CRPT_SHA_DATIN_DATIN_Pos) /*!< CRPT SHA_DATIN: DATIN Mask */
-
-/**@}*/ /* CRPT_CONST */
-/**@}*/ /* end of CRPT register group */
-
-
-/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
-/**
- @addtogroup EADC Enhanced Analog to Digital Converter(EADC)
- Memory Mapped Structure for EADC Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * AD0DAT0
- * ===================================================================================================
- * Offset: 0x00 A/D Data Register 0 for SAMPLE00
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT0;
-
- /**
- * AD0DAT1
- * ===================================================================================================
- * Offset: 0x04 A/D Data Register 1 for SAMPLE01
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT1;
-
- /**
- * AD0DAT2
- * ===================================================================================================
- * Offset: 0x08 A/D Data Register 2 for SAMPLE02
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT2;
-
- /**
- * AD0DAT3
- * ===================================================================================================
- * Offset: 0x0C A/D Data Register 3 for SAMPLE03
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT3;
-
- /**
- * AD0DAT4
- * ===================================================================================================
- * Offset: 0x10 A/D Data Register 4 for SAMPLE04
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT4;
-
- /**
- * AD0DAT5
- * ===================================================================================================
- * Offset: 0x14 A/D Data Register 5 for SAMPLE05
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT5;
-
- /**
- * AD0DAT6
- * ===================================================================================================
- * Offset: 0x18 A/D Data Register 6 for SAMPLE06
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT6;
-
- /**
- * AD0DAT7
- * ===================================================================================================
- * Offset: 0x1C A/D Data Register 7 for SAMPLE07
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DAT7;
-
- /**
- * AD1DAT0
- * ===================================================================================================
- * Offset: 0x20 A/D Data Register 8 for SAMPLE10
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT0;
-
- /**
- * AD1DAT1
- * ===================================================================================================
- * Offset: 0x24 A/D Data Register 9 for SAMPLE11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT1;
-
- /**
- * AD1DAT2
- * ===================================================================================================
- * Offset: 0x28 A/D Data Register 10 for SAMPLE12
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT2;
-
- /**
- * AD1DAT3
- * ===================================================================================================
- * Offset: 0x2C A/D Data Register 11 for SAMPLE13
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT3;
-
- /**
- * AD1DAT4
- * ===================================================================================================
- * Offset: 0x30 A/D Data Register 12 for SAMPLE14
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT4;
-
- /**
- * AD1DAT5
- * ===================================================================================================
- * Offset: 0x34 A/D Data Register 13 for SAMPLE15
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT5;
-
- /**
- * AD1DAT6
- * ===================================================================================================
- * Offset: 0x38 A/D Data Register 14 for SAMPLE16
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT6;
-
- /**
- * AD1DAT7
- * ===================================================================================================
- * Offset: 0x3C A/D Data Register 15 for SAMPLE17
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |OV |Overrun Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
- * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
- * | | |It is cleared by hardware after EADC_ADnDATx register is read.
- * |[17] |VALID |Valid Flag
- * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
- * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DAT7;
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x40 A/D Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADCEN |A/D Converter Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |Before starting A/D conversion function, this bit should be set to 1.
- * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
- * |[1] |ADCRST |ADC0, ADC1 A/D Converter Control Circuits Reset
- * | | |0 = No effect.
- * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
- * | | |The ADCRST (EADC_CTL [1]) bit remains 1 during ADC reset, when ADC reset end, the ADCRST (EADC_CTL [1]) bit is automatically cleared to 0.
- * |[2] |ADCIEN0 |Specific SAMPLE A/D ADINT0 Interrupt Enable Control
- * | | |0 = Specific SAMPLE A/D ADINT0 interrupt function Disabled.
- * | | |1 = Specific SAMPLE A/D ADINT0 interrupt function Enabled.
- * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [0]) flag upon the end of specific SAMPLE A/D conversion.
- * | | |If ADCIEN0 (EADC_CTL [2]) bit is set then conversion end interrupt request ADINT0 is generated.
- * |[3] |ADCIEN1 |Specific SAMPLE A/D ADINT1 Interrupt Enable Control
- * | | |0 = Specific SAMPLE A/D ADINT1 interrupt function Disabled.
- * | | |1 = Specific SAMPLE A/D ADINT1 interrupt function Enabled.
- * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [1]) flag upon the end of specific SAMPLE A/D conversion.
- * | | |If ADCIEN1 EADC_CTL [3]) bit is set then conversion end interrupt request ADINT1 is generated.
- * |[4] |ADCIEN2 |Specific SAMPLE A/D ADINT2 Interrupt Enable Control
- * | | |0 = Specific SAMPLE A/D ADINT2 interrupt function Disabled.
- * | | |1 = Specific SAMPLE A/D ADINT2 interrupt function Enabled.
- * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS1 [2]) flag upon the end of specific SAMPLE A/D conversion.
- * | | |If ADCIEN2 (EADC_CTL [4]) bit is set then conversion end interrupt request ADINT2 is generated.
- * |[5] |ADCIEN3 |Specific SAMPLE A/D ADINT3 Interrupt Enable Control
- * | | |0 = Specific SAMPLE A/D ADINT3 interrupt function Disabled.
- * | | |1 = Specific SAMPLE A/D ADINT3 interrupt function Enabled.
- * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS1 [3]) flag upon the end of specific SAMPLE A/D conversion.
- * | | |If ADCIEN3 (EADC_CTL [5]) bit is set then conversion end interrupt request ADINT3 is generated.
- */
- __IO uint32_t CTL;
- uint32_t RESERVE0[1];
-
-
- /**
- * SWTRG
- * ===================================================================================================
- * Offset: 0x48 A/D SAMPLE Software Start Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SWTRG7_0 |A/D SAMPLE07~SAMPLE00 Software Force To Start ADC Conversion
- * | | |0 = No effect.
- * | | |1 = Start an ADC conversion when the priority is given to SAMPLE0x.
- * | | |Note: x = 0~7.
- * |[8:15] |SWTRG15_8 |A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion
- * | | |0 = No effect.
- * | | |1 = Start an ADC conversion when the priority is given to SAMPLE1x.
- * | | |Note: x = 0~7.
- */
- __O uint32_t SWTRG;
-
- /**
- * PENDSTS
- * ===================================================================================================
- * Offset: 0x4C A/D Start of Conversion Pending Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |STPF7_0 |A/D SAMPLE07~SAMPLE00 Start Of Conversion Pending Flag
- * | | |0 = There is no pending conversion for SAMPLE0x.
- * | | |1 = SAMPLE0x ADC start of conversion is pending.
- * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0.
- * | | |Note: x = 0~7.
- * |[8:15] |STPF15_8 |A/D SAMPLE17~SAMPLE10 Start Of Conversion Pending Flag
- * | | |0 = There is no pending conversion for SAMPLE1x.
- * | | |1 = SAMPLE1x ADC start of conversion is pending.
- * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0.
- * | | |Note: x = 0~7.
- */
- __I uint32_t PENDSTS;
-
- /**
- * ADIFOV
- * ===================================================================================================
- * Offset: 0x50 A/D ADINT3~0 Interrupt Flag Overrun Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADFOV0 |A/D ADINT0 Interrupt Flag Overrun
- * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT0 interrupt flag is overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[1] |ADFOV1 |A/D ADINT1 Interrupt Flag Overrun
- * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT1 interrupt flag is overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[2] |ADFOV2 |A/D ADINT2 Interrupt Flag Overrun
- * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT2 interrupt flag is overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[3] |ADFOV3 |A/D ADINT3 Interrupt Flag Overrun
- * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
- * | | |1 = ADINT3 interrupt flag is overwritten to 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- */
- __IO uint32_t ADIFOV;
-
- /**
- * OVSTS
- * ===================================================================================================
- * Offset: 0x54 A/D SAMPLE Start of Conversion Overrun Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SPOVF7_0 |A/D SAMPLE07~SAMPLE00 Start Of Conversion Overrun Flag
- * | | |0 = No SAMPLE0x event overrun.
- * | | |1 = Indicates a new SAMPLE0x event is generated while an old one event is pending.
- * | | |If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * | | |Note: x = 0~7.
- * |[8:15] |SPOVF15_8 |A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag
- * | | |0 = No SAMPLE1x event overrun.
- * | | |1 = Indicates a new SAMPLE1x event is generated while an old one event is pending.
- * | | |If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1.
- * | | |Note: This bit is cleared by writing 1 to it.
- * | | |Note: x = 0~7.
- */
- __IO uint32_t OVSTS;
-
- /**
- * AD0SPCTL0
- * ===================================================================================================
- * Offset: 0x58 A/D SAMPLE00 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL0;
-
- /**
- * AD0SPCTL1
- * ===================================================================================================
- * Offset: 0x5C A/D SAMPLE01 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL1;
-
- /**
- * AD0SPCTL2
- * ===================================================================================================
- * Offset: 0x60 A/D SAMPLE02 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL2;
-
- /**
- * AD0SPCTL3
- * ===================================================================================================
- * Offset: 0x64 A/D SAMPLE03 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL3;
-
- /**
- * AD0SPCTL4
- * ===================================================================================================
- * Offset: 0x68 A/D SAMPLE04 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL4;
-
- /**
- * AD0SPCTL5
- * ===================================================================================================
- * Offset: 0x6C A/D SAMPLE05 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL5;
-
- /**
- * AD0SPCTL6
- * ===================================================================================================
- * Offset: 0x70 A/D SAMPLE06 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL6;
-
- /**
- * AD0SPCTL7
- * ===================================================================================================
- * Offset: 0x74 A/D SAMPLE07 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD0SPCTL7;
-
- /**
- * AD1SPCTL0
- * ===================================================================================================
- * Offset: 0x78 A/D SAMPLE10 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL0;
-
- /**
- * AD1SPCTL1
- * ===================================================================================================
- * Offset: 0x7C A/D SAMPLE11 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL1;
-
- /**
- * AD1SPCTL2
- * ===================================================================================================
- * Offset: 0x80 A/D SAMPLE12 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL2;
-
- /**
- * AD1SPCTL3
- * ===================================================================================================
- * Offset: 0x84 A/D SAMPLE13 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |0000 = Disable hardware trigger.
- * | | |0001 = External pin (STADC) trigger.
- * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |0100 = Timer0 overflow pulse trigger.
- * | | |0101 = Timer1 overflow pulse trigger.
- * | | |0110 = Timer2 overflow pulse trigger.
- * | | |0111 = Timer3 overflow pulse trigger.
- * | | |1000 = EPWM0_CH0 trigger.
- * | | |1001 = EPWM0_CH2 trigger.
- * | | |1010 = EPWM0_CH4 trigger.
- * | | |1011 = EPWM1_CH0 trigger.
- * | | |1100 = EPWM1_CH2 trigger.
- * | | |1101 = EPWM1_CH4 trigger.
- * | | |1110 = PWM0_CH0 trigger.
- * | | |1111 = PWM0_CH1 trigger.
- * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
- * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
- * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
- * | | |Trigger delay clock frequency:
- * | | |00 = ADC_CLK/1.
- * | | |01 = ADC_CLK/2.
- * | | |10 = ADC_CLK/4.
- * | | |11 = ADC_CLK/16.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL3;
-
- /**
- * AD1SPCTL4
- * ===================================================================================================
- * Offset: 0x88 A/D SAMPLE14 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL4;
-
- /**
- * AD1SPCTL5
- * ===================================================================================================
- * Offset: 0x8C A/D SAMPLE15 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL5;
-
- /**
- * AD1SPCTL6
- * ===================================================================================================
- * Offset: 0x90 A/D SAMPLE16 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL6;
-
- /**
- * AD1SPCTL7
- * ===================================================================================================
- * Offset: 0x94 A/D SAMPLE17 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
- * | | |0000 = ADCn_CH0.
- * | | |0001 = ADCn_CH1.
- * | | |0010 = ADCn_CH2.
- * | | |0011 = ADCn_CH3.
- * | | |0100 = ADCn_CH4.
- * | | |0101 = ADCn_CH5.
- * | | |0110 = ADCn_CH6.
- * | | |0111 = ADCn_CH7.
- * | | |For SAMPLE0
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OP0.
- * | | |For SAMPLE1
- * | | |1000= OP1.
- * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
- * | | |000 = Disable hardware trigger.
- * | | |001 = External pin (STADC) trigger.
- * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
- * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
- * | | |100 = Timer0 overflow pulse trigger.
- * | | |101 = Timer1 overflow pulse trigger.
- * | | |110 = Timer2 overflow pulse trigger.
- * | | |111 = Timer3 overflow pulse trigger.
- * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
- * | | |0 = A/D external pin rising edge trigger Disabled.
- * | | |1 = A/D external pin rising edge trigger Enabled.
- * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
- * | | |0 = A/D external pin falling edge trigger Disabled.
- * | | |1 = A/D external pin falling edge trigger Enabled.
- */
- __IO uint32_t AD1SPCTL7;
- uint32_t RESERVE1[3];
-
-
- /**
- * SIMUSEL
- * ===================================================================================================
- * Offset: 0xA4 A/D SAMPLE Simultaneous Sampling Mode Select Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SIMUSEL0 |A/D SAMPLE00, SAMPLE10 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE00, SAMPLE10 are in single sampling mode, both SAMPLE00 and SAMPLE10's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE00, SAMPLE10 are in simultaneous sampling mode, Only SAMPLE00 can trigger the both ADC conversions of SAMPLE00 and SAMPLE10, SAMPLE10 trigger select TRGSEL is ignored.
- * | | |If SAMPLE00's CHSEL = 1, and SAMPLE10's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- * |[1] |SIMUSEL1 |A/D SAMPLE01, SAMPLE11 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE01, SAMPLE11 are in single sampling mode, both SAMPLE01 and SAMPLE11's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE01, SAMPLE11 are in simultaneous sampling mode, Only SAMPLE01 can trigger the both ADC conversions of SAMPLE01 and SAMPLE11, SAMPLE11 trigger select TRGSEL is ignored.
- * | | |If SAMPLE01's CHSEL = 1, and SAMPLE11's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- * |[2] |SIMUSEL2 |A/D SAMPLE02, SAMPLE12 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE02, SAMPLE12 are in single sampling mode, both SAMPLE02 and SAMPLE12's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE02, SAMPLE12 are in simultaneous sampling mode, Only SAMPLE02 can trigger the both ADC conversions of SAMPLE02 and SAMPLE12, SAMPLE12 trigger select TRGSEL is ignored.
- * | | |If SAMPLE02's CHSEL = 1, and SAMPLE12's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- * |[3] |SIMUSEL3 |A/D SAMPLE03, SAMPLE13 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE03, SAMPLE13 are in single sampling mode, both SAMPLE03 and SAMPLE13's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE03, SAMPLE13 are in simultaneous sampling mode, Only SAMPLE03 can trigger the both ADC conversions of SAMPLE03 and SAMPLE13, SAMPLE13 trigger select TRGSEL is ignored.
- * | | |If SAMPLE03's CHSEL = 1, and SAMPLE13's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- * |[4] |SIMUSEL4 |A/D SAMPLE04, SAMPLE14 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE04, SAMPLE14 are in single sampling mode, both SAMPLE04 and SAMPLE14's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE04, SAMPLE14 are in simultaneous sampling mode, Only SAMPLE04 can trigger the both ADC conversions of SAMPLE04 and SAMPLE14, SAMPLE14 trigger select TRGSEL is ignored.
- * | | |If SAMPLE04's CHSEL = 1, and SAMPLE14's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- * |[5] |SIMUSEL5 |A/D SAMPLE05, SAMPLE15 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE05, SAMPLE15 are in single sampling mode, both SAMPLE05 and SAMPLE15's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE05, SAMPLE15 are in simultaneous sampling mode, Only SAMPLE05 can trigger the both ADC conversions of SAMPLE05 and SAMPLE15, SAMPLE15 trigger select TRGSEL is ignored.
- * | | |if SAMPLE05's CHSEL = 1, and SAMPLE15's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- * |[6] |SIMUSEL6 |A/D SAMPLE06, SAMPLE16 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE06, SAMPLE16 are in single sampling mode, both SAMPLE06 and SAMPLE16's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE06, SAMPLE16 are in simultaneous sampling mode, Only SAMPLE06 can trigger the both ADC conversions of SAMPLE06 and SAMPLE16, SAMPLE16 trigger select TRGSEL is ignored.
- * | | |If SAMPLE06's CHSEL = 1, and SAMPLE16's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- * |[7] |SIMUSEL7 |A/D SAMPLE07, SAMPLE17 Simultaneous Sampling Mode Selection
- * | | |0 = SAMPLE07, SAMPLE17 are in single sampling mode, both SAMPLE07 and SAMPLE17's 3 bits of CHSEL define the ADC channels to be converted.
- * | | |1 = SAMPLE07, SAMPLE17 are in simultaneous sampling mode, Only SAMPLE07 can trigger the both ADC conversions of SAMPLE07 and SAMPLE17, SAMPLE17 trigger select TRGSEL is ignored.
- * | | |If SAMPLE07's CHSEL = 1, SAMPLE17's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
- */
- __IO uint32_t SIMUSEL;
-
- /**
- * CMP0/1
- * ===================================================================================================
- * Offset: 0xA8 A/D Result Compare Register 0
- * Offset: 0xAC A/D Result Compare Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADCMPEN |A/D Result Compare Enable Control
- * | | |0 = Compare Disabled.
- * | | |1 = Compare Enabled.
- * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPx[27:16]) with specified SAMPLE conversion result when converted data is loaded into ADDR register.
- * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Control
- * | | |0 = Compare function interrupt Disabled.
- * | | |1 = Compare function interrupt Enabled.
- * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPx[2]) and CMPMCNT (EADC_CMPx[11:8]), ADCMPF (EADC_STATUS1 [7:6]) bit will be asserted, in the meanwhile, if ADCMPIE (EADC_CMPx[1]) is set to 1, a compare interrupt request is generated.
- * |[2] |CMPCOND |Compare Condition
- * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one.
- * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one.
- * | | |Note: When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8]) + 1, the CMPF bit will be set.
- * |[3:5] |CMPSPL |Compare SAMPLE Selection
- * | | |000 = SAMPLE00 conversion result EADC_AD0DAT0 is selected to be compared.
- * | | |001 = SAMPLE01 conversion result EADC_AD0DAT1 is selected to be compared.
- * | | |010 = SAMPLE02 conversion result EADC_AD0DAT2 is selected to be compared.
- * | | |011 = SAMPLE03 conversion result EADC_AD0DAT3 is selected to be compared.
- * | | |100 = SAMPLE10 conversion result EADC_AD1DAT0 is selected to be compared.
- * | | |101 = SAMPLE11 conversion result EADC_AD1DAT1 is selected to be compared.
- * | | |110 = SAMPLE12 conversion result EADC_AD1DAT2 is selected to be compared.
- * | | |111 = SAMPLE13 conversion result EADC_AD1DAT3 is selected to be compared.
- * |[8:11] |CMPMCNT |Compare Match Count
- * | | |When the specified A/D SAMPLE analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPx[2]), the internal match counter will increase 1.
- * | | |When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8] + 1, the ADCMPF (EADC_STATUS1 [7:6]) bit will be set.
- * |[16:27] |CMPDAT |Compared Data
- * | | |The 12 bits data is used to compare with conversion result of specified SAMPLE.
- * | | |Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
- */
- __IO uint32_t CMP[2];
-
- /**
- * STATUS0
- * ===================================================================================================
- * Offset: 0xB0 A/D Status Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |VALID7_0 |ADDR07~ ADDR00 Data Valid Flag (Read Only)
- * | | |It is a mirror of VALID bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.
- * | | |Note: x = 0~7.
- * |[8:15] |VALID15_8 |ADDR17~ ADDR10 Data Valid Flag (Read Only)
- * | | |It is a mirror of VALID bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.
- * | | |Note: x = 0~7.
- * |[16:23] |OV7_0 |ADDR07~ ADDR00 Overrun Flag (Read Only)
- * | | |It is a mirror to OV bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.
- * | | |Note: x = 0~7.
- * |[24:31] |OV15_8 |ADDR17~ADDR10 Overrun Flag (Read Only)
- * | | |It is a mirror to OV bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.
- * | | |Note: x = 0~7.
- */
- __I uint32_t STATUS0;
-
- /**
- * STATUS1
- * ===================================================================================================
- * Offset: 0xB4 A/D Status Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
- * | | |0 = No ADINT0 interrupt pulse received.
- * | | |1 = ADINT0 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
- * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
- * | | |0 = No ADINT1 interrupt pulse received.
- * | | |1 = ADINT1 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
- * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
- * | | |0 = no ADINT2 interrupt pulse received.
- * | | |1 = ADINT2 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
- * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
- * | | |0 = No ADINT3 interrupt pulse received.
- * | | |1 = ADINT3 interrupt pulse has been received.
- * | | |Note1: This bit is cleared by writing 1 to it.
- * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
- * |[4] |ADCMPO0 |ADC Compare 0 Output Status
- * | | |The 12 bits compare0 data CMPDAT EADC_CMP0 [27:16]) is used to compare with conversion result of specified SAMPLE.
- * | | |Software can use it to monitor the external analog input pin voltage status.
- * | | |0 = Conversion result in ADDR less than CMPDAT (EADC_CMP0 [27:16]) setting.
- * | | |1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP0 [27:16]) setting.
- * |[5] |ADCMPO1 |ADC Compare 1 Output Status
- * | | |The 12 bits compare1 data CMPDAT (EADC_CMP1 [27:16]) is used to compare with conversion result of specified SAMPLE.
- * | | |Software can use it to monitor the external analog input pin voltage status.
- * | | |0 = Conversion result in ADDR less than CMPDAT EADC_CMP1 [27:16]) setting.
- * | | |1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP1 [27:16]) setting.
- * |[6] |ADCMPF0 |ADC Compare 0 Flag
- * | | |When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
- * | | |0 = Conversion result in ADDR does not meet EADC_CMP0 setting.
- * | | |1 = Conversion result in ADDR meets EADC_CMP0 setting.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[7] |ADCMPF1 |ADC Compare 1 Flag
- * | | |When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
- * | | |0 = Conversion result in ADDR does not meet EADC_CMP1 setting.
- * | | |1 = Conversion result in ADDR meets EADC_CMP1 setting.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[8] |BUSY0 |Busy/Idle (Read Only)
- * | | |0 = A/D converter 0 (ADC0) is in idle state.
- * | | |1 = A/D converter 0 (ADC0) is doing conversion.
- * |[12:15] |CHANNEL0 |Current Conversion Channel (Read Only)
- * | | |This filed reflects ADC0 current conversion channel when BUSY0 (EADC_STATUS1 [8]) = 1.
- * | | |When BUSY0 (EADC_STATUS1 [8]) = 0, it shows the last converted channel.
- * | | |0000 = ADC0_CH0.
- * | | |0001 = ADC0_CH1.
- * | | |0010 = ADC0_CH2.
- * | | |0011 = ADC0_CH3.
- * | | |0100 = ADC0_CH4.
- * | | |0100 = ADC0_CH5.
- * | | |0110 = ADC0_CH6.
- * | | |0111 = ADC0_CH7.
- * | | |1000 = VBG.
- * | | |1001 = VTEMP.
- * | | |1010 = AVSS.
- * | | |1011 = OPA0_O.
- * | | |Other = reserved.
- * |[16] |BUSY1 |Busy/Idle
- * | | |0 = A/D converter 1 (ADC1) is in idle state.
- * | | |1 = A/D converter 1 (ADC1) is doing conversion.
- * |[20:23] |CHANNEL1 |Current Conversion Channel (Read Only)
- * | | |This filed reflects ADC1 current conversion channel when BUSY1 (EADC_STATUS1 [16]) = 1.
- * | | |When BUSY1 (EADC_STATUS1 [16]) = 0, it shows the last converted channel.
- * | | |0000 = ADC1_CH0.
- * | | |0001 = ADC1_CH1.
- * | | |0010 = ADC1_CH2.
- * | | |0011 = ADC1_CH3.
- * | | |0100 = ADC1_CH4.
- * | | |0101 = ADC1_CH5.
- * | | |0110 = ADC1_CH6.
- * | | |0111 = ADC1_CH7.
- * | | |1000 = OPA1_O.
- * | | |Other = reversed.
- * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
- * | | |0 = None of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1.
- * | | |1 = Any one of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1.
- * | | |Note: This bit will keep 1 when any ADFOVx (ADIFOVR [15:0]) Flag is equal to 1.
- * |[25] |STOVF |For All A/D SAMPLE Start Of Conversion Overrun Flags Check
- * | | |0 = None of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1.
- * | | |1 = Any one of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1.
- * | | |Note: This bit will keep 1 when any SPOVFx (ADSPOVFR [15:0]) Flag is equal to 1.
- * |[26] |AVALID |For All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check
- * | | |0 = None of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1.
- * | | |1 = Any one of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1.
- * | | |Note: This bit will keep 1 when any VALIDx (EADC_ADnDATx[17]) Flag is equal to 1.
- * |[27] |AOV |For All SAMPLE A/D Result Data Register Overrun Flags Check
- * | | |0 = None of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1.
- * | | |1 = Any one of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1.
- * | | |Note: This bit will keep 1 when any OVx (EADC_ADnDATx[16]) Flag is equal to 1.
- */
- __IO uint32_t STATUS1;
-
- /**
- * EXTSMPT
- * ===================================================================================================
- * Offset: 0xB8 A/D Timing Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EXTSMPT0 |ADC0 Extend Sampling Time
- * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
- * | | |The range of start delay time is from 0~255 ADC clock.
- * |[16:23] |EXTSMPT1 |ADC1 Extend Sampling Time
- * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
- * | | |The range of start delay time is from 0~255 ADC clock.
- */
- __IO uint32_t EXTSMPT;
- uint32_t RESERVE2[17];
-
-
- /**
- * AD0DDAT0
- * ===================================================================================================
- * Offset: 0x100 A/D double Data Register 0 for SAMPLE00
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DDAT0;
-
- /**
- * AD0DDAT1
- * ===================================================================================================
- * Offset: 0x104 A/D double Data Register 1 for SAMPLE01
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DDAT1;
-
- /**
- * AD0DDAT2
- * ===================================================================================================
- * Offset: 0x108 A/D double Data Register 2 for SAMPLE02
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DDAT2;
-
- /**
- * AD0DDAT3
- * ===================================================================================================
- * Offset: 0x10C A/D double Data Register 3 for SAMPLE03
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD0DDAT3;
- uint32_t RESERVE3[4];
-
-
- /**
- * AD1DDAT0
- * ===================================================================================================
- * Offset: 0x120 A/D double Data Register 0 for SAMPLE10
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DDAT0;
-
- /**
- * AD1DDAT1
- * ===================================================================================================
- * Offset: 0x124 A/D double Data Register 1 for SAMPLE11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DDAT1;
-
- /**
- * AD1DDAT2
- * ===================================================================================================
- * Offset: 0x128 A/D double Data Register 2 for SAMPLE12
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DDAT2;
-
- /**
- * AD1DDAT3
- * ===================================================================================================
- * Offset: 0x12C A/D double Data Register 3 for SAMPLE13
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |RESULT |A/D Conversion Result
- * | | |This field contains 12 bits conversion result.
- * |[16] |VALID |Valid Flag
- * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
- * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
- * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
- */
- __I uint32_t AD1DDAT3;
-
- /**
- * DBMEN
- * ===================================================================================================
- * Offset: 0x130 A/D Double Buffer Mode select
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |AD0DBM0 |Double Buffer Mode For SAMPLE00
- * | | |0 = SAMPLE00 has one sample result register. (default).
- * | | |1 =SAMPLE00 has two sample result registers.
- * |[1] |AD0DBM1 |Double Buffer Mode For SAMPLE01
- * | | |0 = SAMPLE01 has one sample result register. (default).
- * | | |1 = SAMPLE01 has two sample result registers.
- * |[2] |AD0DBM2 |Double Buffer Mode For SAMPLE02
- * | | |0 = SAMPLE02 has one sample result register. (default).
- * | | |1 =SAMPLE02 has two sample result registers.
- * |[3] |AD0DBM3 |Double Buffer Mode For SAMPLE03
- * | | |0 = SAMPLE03 has one sample result register. (default).
- * | | |1 =SAMPLE03 has two sample result registers.
- * |[8] |AD1DBM0 |Double Buffer Mode For SAMPLE10
- * | | |0 = SAMPLE10 has one sample result register. (default)
- * | | |1 =SAMPLE10 has two sample result registers.
- * |[9] |AD1DBM1 |Double Buffer Mode For SAMPLE11
- * | | |0 = SAMPLE11 has one sample result register. (default).
- * | | |1 =SAMPLE11 has two sample result registers.
- * |[10] |AD1DBM2 |Double Buffer Mode For SAMPLE12
- * | | |0 = SAMPLE12 has one sample result register. (default).
- * | | |1 =SAMPLE12 has two sample result registers.
- * |[11] |AD1DBM3 |Double Buffer Mode For SAMPLE13
- * | | |0 = SAMPLE13 has one sample result register. (default)
- * | | |1 =SAMPLE13 has two sample result registers.
- */
- __IO uint32_t DBMEN;
-
- /**
- * INTSRC0
- * ===================================================================================================
- * Offset: 0x134 A/D Interrupt 0 Source Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |AD0SPIE0 |SAMPLE00 Interrupt Mask Enable Control
- * | | |0 = SAMPLE00 interrupt mask Disabled.
- * | | |1 = SAMPLE00 interrupt mask Enabled.
- * |[1] |AD0SPIE1 |SAMPLE01 Interrupt Mask Enable Control
- * | | |0 = SAMPLE01 interrupt mask Disabled.
- * | | |1 = SAMPLE01 interrupt mask Enabled.
- * |[2] |AD0SPIE2 |SAMPLE02 Interrupt Mask Enable Control
- * | | |0 = SAMPLE02 interrupt mask Disabled.
- * | | |1 = SAMPLE02 interrupt mask Enabled.
- * |[3] |AD0SPIE3 |SAMPLE03 Interrupt Mask Enable Control
- * | | |0 = SAMPLE03 interrupt mask Disabled.
- * | | |1 = SAMPLE03 interrupt mask Enabled.
- * |[4] |AD0SPIE4 |SAMPLE04 Interrupt Mask Enable Control
- * | | |0 = SAMPLE04 interrupt mask Disabled.
- * | | |1 = SAMPLE04 interrupt mask Enabled.
- * |[5] |AD0SPIE5 |SAMPLE05 Interrupt Mask Enable Control
- * | | |0 = SAMPLE05 interrupt mask Disabled.
- * | | |1 = SAMPLE05 interrupt mask Enabled.
- * |[6] |AD0SPIE6 |SAMPLE06 Interrupt Mask Enable Control
- * | | |0 = SAMPLE06 interrupt mask Disabled.
- * | | |1 = SAMPLE06 interrupt mask Enabled.
- * |[7] |AD0SPIE7 |SAMPLE07 Interrupt Mask Enable Control
- * | | |0 = SAMPLE07 interrupt mask Disabled.
- * | | |1 = SAMPLE07 interrupt mask Enabled.
- * |[8] |AD1SPIE0 |SAMPLE10 Interrupt Mask Enable Control
- * | | |0 = SAMPLE10 interrupt mask Disabled.
- * | | |1 = SAMPLE10 interrupt mask Enabled.
- * |[9] |AD1SPIE1 |SAMPLE11 Interrupt Mask Enable Control
- * | | |0 = SAMPLE11 interrupt mask Disabled.
- * | | |1 = SAMPLE11 interrupt mask Enabled.
- * |[10] |AD1SPIE2 |SAMPLE12 Interrupt Mask Enable Control
- * | | |0 = SAMPLE12 interrupt mask Disabled.
- * | | |1 = SAMPLE12 interrupt mask Enabled.
- * |[11] |AD1SPIE3 |SAMPLE13 Interrupt Mask Enable Control
- * | | |0 = SAMPLE13 interrupt mask Disabled.
- * | | |1 = SAMPLE13 interrupt mask Enabled.
- * |[12] |AD1SPIE4 |SAMPLE14 Interrupt Mask Enable Control
- * | | |0 = SAMPLE14 interrupt mask Disabled.
- * | | |1 = SAMPLE14 interrupt mask Enabled.
- * |[13] |AD1SPIE5 |SAMPLE15 Interrupt Mask Enable Control
- * | | |0 = SAMPLE15 interrupt mask Disabled.
- * | | |1 = SAMPLE15 interrupt mask Enabled.
- * |[14] |AD1SPIE6 |SAMPLE16 Interrupt Mask Enable Control
- * | | |0 = SAMPLE16 interrupt mask Disabled.
- * | | |1 = SAMPLE16 interrupt mask Enabled.
- * |[15] |AD1SPIE7 |SAMPLE17 Interrupt Mask Enable Control
- * | | |0 = SAMPLE17 interrupt mask Disabled.
- * | | |1 = SAMPLE17 interrupt mask Enabled.
- */
- __IO uint32_t INTSRC[4];
-
- /**
- * AD0TRGEN0
- * ===================================================================================================
- * Offset: 0x144 A/D trigger condition for SAMPLE00
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD0TRGEN0;
-
- /**
- * AD0TRGEN1
- * ===================================================================================================
- * Offset: 0x148 A/D trigger condition for SAMPLE01
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD0TRGEN1;
-
- /**
- * AD0TRGEN2
- * ===================================================================================================
- * Offset: 0x14C A/D trigger condition for SAMPLE02
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD0TRGEN2;
-
- /**
- * AD0TRGEN3
- * ===================================================================================================
- * Offset: 0x150 A/D trigger condition for SAMPLE03
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD0TRGEN3;
-
- /**
- * AD1TRGEN0
- * ===================================================================================================
- * Offset: 0x154 A/D trigger condition for SAMPLE10
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD1TRGEN0;
-
- /**
- * AD1TRGEN1
- * ===================================================================================================
- * Offset: 0x158 A/D trigger condition for SAMPLE11
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD1TRGEN1;
-
- /**
- * AD1TRGEN2
- * ===================================================================================================
- * Offset: 0x15C A/D trigger condition for SAMPLE12
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD1TRGEN2;
-
- /**
- * AD1TRGEN3
- * ===================================================================================================
- * Offset: 0x160 A/D trigger condition for SAMPLE13
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- */
- __IO uint32_t AD1TRGEN3;
-
-} EADC_T;
-
-/**
- @addtogroup EADC_CONST EADC Bit Field Definition
- Constant Definitions for EADC Controller
-@{ */
-
-#define EADC_AD0DAT0_RESULT_Pos (0) /*!< EADC AD0DAT0: RESULT Position */
-#define EADC_AD0DAT0_RESULT_Msk (0xffful << EADC_AD0DAT0_RESULT_Pos) /*!< EADC AD0DAT0: RESULT Mask */
-
-#define EADC_AD0DAT0_OV_Pos (16) /*!< EADC AD0DAT0: OV Position */
-#define EADC_AD0DAT0_OV_Msk (0x1ul << EADC_AD0DAT0_OV_Pos) /*!< EADC AD0DAT0: OV Mask */
-
-#define EADC_AD0DAT0_VALID_Pos (17) /*!< EADC AD0DAT0: VALID Position */
-#define EADC_AD0DAT0_VALID_Msk (0x1ul << EADC_AD0DAT0_VALID_Pos) /*!< EADC AD0DAT0: VALID Mask */
-
-#define EADC_AD0DAT1_RESULT_Pos (0) /*!< EADC AD0DAT1: RESULT Position */
-#define EADC_AD0DAT1_RESULT_Msk (0xffful << EADC_AD0DAT1_RESULT_Pos) /*!< EADC AD0DAT1: RESULT Mask */
-
-#define EADC_AD0DAT1_OV_Pos (16) /*!< EADC AD0DAT1: OV Position */
-#define EADC_AD0DAT1_OV_Msk (0x1ul << EADC_AD0DAT1_OV_Pos) /*!< EADC AD0DAT1: OV Mask */
-
-#define EADC_AD0DAT1_VALID_Pos (17) /*!< EADC AD0DAT1: VALID Position */
-#define EADC_AD0DAT1_VALID_Msk (0x1ul << EADC_AD0DAT1_VALID_Pos) /*!< EADC AD0DAT1: VALID Mask */
-
-#define EADC_AD0DAT2_RESULT_Pos (0) /*!< EADC AD0DAT2: RESULT Position */
-#define EADC_AD0DAT2_RESULT_Msk (0xffful << EADC_AD0DAT2_RESULT_Pos) /*!< EADC AD0DAT2: RESULT Mask */
-
-#define EADC_AD0DAT2_OV_Pos (16) /*!< EADC AD0DAT2: OV Position */
-#define EADC_AD0DAT2_OV_Msk (0x1ul << EADC_AD0DAT2_OV_Pos) /*!< EADC AD0DAT2: OV Mask */
-
-#define EADC_AD0DAT2_VALID_Pos (17) /*!< EADC AD0DAT2: VALID Position */
-#define EADC_AD0DAT2_VALID_Msk (0x1ul << EADC_AD0DAT2_VALID_Pos) /*!< EADC AD0DAT2: VALID Mask */
-
-#define EADC_AD0DAT3_RESULT_Pos (0) /*!< EADC AD0DAT3: RESULT Position */
-#define EADC_AD0DAT3_RESULT_Msk (0xffful << EADC_AD0DAT3_RESULT_Pos) /*!< EADC AD0DAT3: RESULT Mask */
-
-#define EADC_AD0DAT3_OV_Pos (16) /*!< EADC AD0DAT3: OV Position */
-#define EADC_AD0DAT3_OV_Msk (0x1ul << EADC_AD0DAT3_OV_Pos) /*!< EADC AD0DAT3: OV Mask */
-
-#define EADC_AD0DAT3_VALID_Pos (17) /*!< EADC AD0DAT3: VALID Position */
-#define EADC_AD0DAT3_VALID_Msk (0x1ul << EADC_AD0DAT3_VALID_Pos) /*!< EADC AD0DAT3: VALID Mask */
-
-#define EADC_AD0DAT4_RESULT_Pos (0) /*!< EADC AD0DAT4: RESULT Position */
-#define EADC_AD0DAT4_RESULT_Msk (0xffful << EADC_AD0DAT4_RESULT_Pos) /*!< EADC AD0DAT4: RESULT Mask */
-
-#define EADC_AD0DAT4_OV_Pos (16) /*!< EADC AD0DAT4: OV Position */
-#define EADC_AD0DAT4_OV_Msk (0x1ul << EADC_AD0DAT4_OV_Pos) /*!< EADC AD0DAT4: OV Mask */
-
-#define EADC_AD0DAT4_VALID_Pos (17) /*!< EADC AD0DAT4: VALID Position */
-#define EADC_AD0DAT4_VALID_Msk (0x1ul << EADC_AD0DAT4_VALID_Pos) /*!< EADC AD0DAT4: VALID Mask */
-
-#define EADC_AD0DAT5_RESULT_Pos (0) /*!< EADC AD0DAT5: RESULT Position */
-#define EADC_AD0DAT5_RESULT_Msk (0xffful << EADC_AD0DAT5_RESULT_Pos) /*!< EADC AD0DAT5: RESULT Mask */
-
-#define EADC_AD0DAT5_OV_Pos (16) /*!< EADC AD0DAT5: OV Position */
-#define EADC_AD0DAT5_OV_Msk (0x1ul << EADC_AD0DAT5_OV_Pos) /*!< EADC AD0DAT5: OV Mask */
-
-#define EADC_AD0DAT5_VALID_Pos (17) /*!< EADC AD0DAT5: VALID Position */
-#define EADC_AD0DAT5_VALID_Msk (0x1ul << EADC_AD0DAT5_VALID_Pos) /*!< EADC AD0DAT5: VALID Mask */
-
-#define EADC_AD0DAT6_RESULT_Pos (0) /*!< EADC AD0DAT6: RESULT Position */
-#define EADC_AD0DAT6_RESULT_Msk (0xffful << EADC_AD0DAT6_RESULT_Pos) /*!< EADC AD0DAT6: RESULT Mask */
-
-#define EADC_AD0DAT6_OV_Pos (16) /*!< EADC AD0DAT6: OV Position */
-#define EADC_AD0DAT6_OV_Msk (0x1ul << EADC_AD0DAT6_OV_Pos) /*!< EADC AD0DAT6: OV Mask */
-
-#define EADC_AD0DAT6_VALID_Pos (17) /*!< EADC AD0DAT6: VALID Position */
-#define EADC_AD0DAT6_VALID_Msk (0x1ul << EADC_AD0DAT6_VALID_Pos) /*!< EADC AD0DAT6: VALID Mask */
-
-#define EADC_AD0DAT7_RESULT_Pos (0) /*!< EADC AD0DAT7: RESULT Position */
-#define EADC_AD0DAT7_RESULT_Msk (0xffful << EADC_AD0DAT7_RESULT_Pos) /*!< EADC AD0DAT7: RESULT Mask */
-
-#define EADC_AD0DAT7_OV_Pos (16) /*!< EADC AD0DAT7: OV Position */
-#define EADC_AD0DAT7_OV_Msk (0x1ul << EADC_AD0DAT7_OV_Pos) /*!< EADC AD0DAT7: OV Mask */
-
-#define EADC_AD0DAT7_VALID_Pos (17) /*!< EADC AD0DAT7: VALID Position */
-#define EADC_AD0DAT7_VALID_Msk (0x1ul << EADC_AD0DAT7_VALID_Pos) /*!< EADC AD0DAT7: VALID Mask */
-
-#define EADC_AD1DAT0_RESULT_Pos (0) /*!< EADC AD1DAT0: RESULT Position */
-#define EADC_AD1DAT0_RESULT_Msk (0xffful << EADC_AD1DAT0_RESULT_Pos) /*!< EADC AD1DAT0: RESULT Mask */
-
-#define EADC_AD1DAT0_OV_Pos (16) /*!< EADC AD1DAT0: OV Position */
-#define EADC_AD1DAT0_OV_Msk (0x1ul << EADC_AD1DAT0_OV_Pos) /*!< EADC AD1DAT0: OV Mask */
-
-#define EADC_AD1DAT0_VALID_Pos (17) /*!< EADC AD1DAT0: VALID Position */
-#define EADC_AD1DAT0_VALID_Msk (0x1ul << EADC_AD1DAT0_VALID_Pos) /*!< EADC AD1DAT0: VALID Mask */
-
-#define EADC_AD1DAT1_RESULT_Pos (0) /*!< EADC AD1DAT1: RESULT Position */
-#define EADC_AD1DAT1_RESULT_Msk (0xffful << EADC_AD1DAT1_RESULT_Pos) /*!< EADC AD1DAT1: RESULT Mask */
-
-#define EADC_AD1DAT1_OV_Pos (16) /*!< EADC AD1DAT1: OV Position */
-#define EADC_AD1DAT1_OV_Msk (0x1ul << EADC_AD1DAT1_OV_Pos) /*!< EADC AD1DAT1: OV Mask */
-
-#define EADC_AD1DAT1_VALID_Pos (17) /*!< EADC AD1DAT1: VALID Position */
-#define EADC_AD1DAT1_VALID_Msk (0x1ul << EADC_AD1DAT1_VALID_Pos) /*!< EADC AD1DAT1: VALID Mask */
-
-#define EADC_AD1DAT2_RESULT_Pos (0) /*!< EADC AD1DAT2: RESULT Position */
-#define EADC_AD1DAT2_RESULT_Msk (0xffful << EADC_AD1DAT2_RESULT_Pos) /*!< EADC AD1DAT2: RESULT Mask */
-
-#define EADC_AD1DAT2_OV_Pos (16) /*!< EADC AD1DAT2: OV Position */
-#define EADC_AD1DAT2_OV_Msk (0x1ul << EADC_AD1DAT2_OV_Pos) /*!< EADC AD1DAT2: OV Mask */
-
-#define EADC_AD1DAT2_VALID_Pos (17) /*!< EADC AD1DAT2: VALID Position */
-#define EADC_AD1DAT2_VALID_Msk (0x1ul << EADC_AD1DAT2_VALID_Pos) /*!< EADC AD1DAT2: VALID Mask */
-
-#define EADC_AD1DAT3_RESULT_Pos (0) /*!< EADC AD1DAT3: RESULT Position */
-#define EADC_AD1DAT3_RESULT_Msk (0xffful << EADC_AD1DAT3_RESULT_Pos) /*!< EADC AD1DAT3: RESULT Mask */
-
-#define EADC_AD1DAT3_OV_Pos (16) /*!< EADC AD1DAT3: OV Position */
-#define EADC_AD1DAT3_OV_Msk (0x1ul << EADC_AD1DAT3_OV_Pos) /*!< EADC AD1DAT3: OV Mask */
-
-#define EADC_AD1DAT3_VALID_Pos (17) /*!< EADC AD1DAT3: VALID Position */
-#define EADC_AD1DAT3_VALID_Msk (0x1ul << EADC_AD1DAT3_VALID_Pos) /*!< EADC AD1DAT3: VALID Mask */
-
-#define EADC_AD1DAT4_RESULT_Pos (0) /*!< EADC AD1DAT4: RESULT Position */
-#define EADC_AD1DAT4_RESULT_Msk (0xffful << EADC_AD1DAT4_RESULT_Pos) /*!< EADC AD1DAT4: RESULT Mask */
-
-#define EADC_AD1DAT4_OV_Pos (16) /*!< EADC AD1DAT4: OV Position */
-#define EADC_AD1DAT4_OV_Msk (0x1ul << EADC_AD1DAT4_OV_Pos) /*!< EADC AD1DAT4: OV Mask */
-
-#define EADC_AD1DAT4_VALID_Pos (17) /*!< EADC AD1DAT4: VALID Position */
-#define EADC_AD1DAT4_VALID_Msk (0x1ul << EADC_AD1DAT4_VALID_Pos) /*!< EADC AD1DAT4: VALID Mask */
-
-#define EADC_AD1DAT5_RESULT_Pos (0) /*!< EADC AD1DAT5: RESULT Position */
-#define EADC_AD1DAT5_RESULT_Msk (0xffful << EADC_AD1DAT5_RESULT_Pos) /*!< EADC AD1DAT5: RESULT Mask */
-
-#define EADC_AD1DAT5_OV_Pos (16) /*!< EADC AD1DAT5: OV Position */
-#define EADC_AD1DAT5_OV_Msk (0x1ul << EADC_AD1DAT5_OV_Pos) /*!< EADC AD1DAT5: OV Mask */
-
-#define EADC_AD1DAT5_VALID_Pos (17) /*!< EADC AD1DAT5: VALID Position */
-#define EADC_AD1DAT5_VALID_Msk (0x1ul << EADC_AD1DAT5_VALID_Pos) /*!< EADC AD1DAT5: VALID Mask */
-
-#define EADC_AD1DAT6_RESULT_Pos (0) /*!< EADC AD1DAT6: RESULT Position */
-#define EADC_AD1DAT6_RESULT_Msk (0xffful << EADC_AD1DAT6_RESULT_Pos) /*!< EADC AD1DAT6: RESULT Mask */
-
-#define EADC_AD1DAT6_OV_Pos (16) /*!< EADC AD1DAT6: OV Position */
-#define EADC_AD1DAT6_OV_Msk (0x1ul << EADC_AD1DAT6_OV_Pos) /*!< EADC AD1DAT6: OV Mask */
-
-#define EADC_AD1DAT6_VALID_Pos (17) /*!< EADC AD1DAT6: VALID Position */
-#define EADC_AD1DAT6_VALID_Msk (0x1ul << EADC_AD1DAT6_VALID_Pos) /*!< EADC AD1DAT6: VALID Mask */
-
-#define EADC_AD1DAT7_RESULT_Pos (0) /*!< EADC AD1DAT7: RESULT Position */
-#define EADC_AD1DAT7_RESULT_Msk (0xffful << EADC_AD1DAT7_RESULT_Pos) /*!< EADC AD1DAT7: RESULT Mask */
-
-#define EADC_AD1DAT7_OV_Pos (16) /*!< EADC AD1DAT7: OV Position */
-#define EADC_AD1DAT7_OV_Msk (0x1ul << EADC_AD1DAT7_OV_Pos) /*!< EADC AD1DAT7: OV Mask */
-
-#define EADC_AD1DAT7_VALID_Pos (17) /*!< EADC AD1DAT7: VALID Position */
-#define EADC_AD1DAT7_VALID_Msk (0x1ul << EADC_AD1DAT7_VALID_Pos) /*!< EADC AD1DAT7: VALID Mask */
-
-#define EADC_CTL_ADCEN_Pos (0) /*!< EADC CTL: ADCEN Position */
-#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC CTL: ADCEN Mask */
-
-#define EADC_CTL_ADCRST_Pos (1) /*!< EADC CTL: ADCRST Position */
-#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC CTL: ADCRST Mask */
-
-#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC CTL: ADCIEN0 Position */
-#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC CTL: ADCIEN0 Mask */
-
-#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC CTL: ADCIEN1 Position */
-#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC CTL: ADCIEN1 Mask */
-
-#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC CTL: ADCIEN2 Position */
-#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC CTL: ADCIEN2 Mask */
-
-#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC CTL: ADCIEN3 Position */
-#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC CTL: ADCIEN3 Mask */
-
-#define EADC_SWTRG_SWTRG7_0_Pos (0) /*!< EADC SWTRG: SWTRG7_0 Position */
-#define EADC_SWTRG_SWTRG7_0_Msk (0xfful << EADC_SWTRG_SWTRG7_0_Pos) /*!< EADC SWTRG: SWTRG7_0 Mask */
-
-#define EADC_SWTRG_SWTRG15_8_Pos (8) /*!< EADC SWTRG: SWTRG15_8 Position */
-#define EADC_SWTRG_SWTRG15_8_Msk (0xfful << EADC_SWTRG_SWTRG15_8_Pos) /*!< EADC SWTRG: SWTRG15_8 Mask */
-
-#define EADC_PENDSTS_STPF7_0_Pos (0) /*!< EADC PENDSTS: STPF7_0 Position */
-#define EADC_PENDSTS_STPF7_0_Msk (0xfful << EADC_PENDSTS_STPF7_0_Pos) /*!< EADC PENDSTS: STPF7_0 Mask */
-
-#define EADC_PENDSTS_STPF15_8_Pos (8) /*!< EADC PENDSTS: STPF15_8 Position */
-#define EADC_PENDSTS_STPF15_8_Msk (0xfful << EADC_PENDSTS_STPF15_8_Pos) /*!< EADC PENDSTS: STPF15_8 Mask */
-
-#define EADC_ADIFOV_ADFOV0_Pos (0) /*!< EADC ADIFOV: ADFOV0 Position */
-#define EADC_ADIFOV_ADFOV0_Msk (0x1ul << EADC_ADIFOV_ADFOV0_Pos) /*!< EADC ADIFOV: ADFOV0 Mask */
-
-#define EADC_ADIFOV_ADFOV1_Pos (1) /*!< EADC ADIFOV: ADFOV1 Position */
-#define EADC_ADIFOV_ADFOV1_Msk (0x1ul << EADC_ADIFOV_ADFOV1_Pos) /*!< EADC ADIFOV: ADFOV1 Mask */
-
-#define EADC_ADIFOV_ADFOV2_Pos (2) /*!< EADC ADIFOV: ADFOV2 Position */
-#define EADC_ADIFOV_ADFOV2_Msk (0x1ul << EADC_ADIFOV_ADFOV2_Pos) /*!< EADC ADIFOV: ADFOV2 Mask */
-
-#define EADC_ADIFOV_ADFOV3_Pos (3) /*!< EADC ADIFOV: ADFOV3 Position */
-#define EADC_ADIFOV_ADFOV3_Msk (0x1ul << EADC_ADIFOV_ADFOV3_Pos) /*!< EADC ADIFOV: ADFOV3 Mask */
-
-#define EADC_OVSTS_SPOVF7_0_Pos (0) /*!< EADC OVSTS: SPOVF7_0 Position */
-#define EADC_OVSTS_SPOVF7_0_Msk (0xfful << EADC_OVSTS_SPOVF7_0_Pos) /*!< EADC OVSTS: SPOVF7_0 Mask */
-
-#define EADC_OVSTS_SPOVF15_8_Pos (8) /*!< EADC OVSTS: SPOVF15_8 Position */
-#define EADC_OVSTS_SPOVF15_8_Msk (0xfful << EADC_OVSTS_SPOVF15_8_Pos) /*!< EADC OVSTS: SPOVF15_8 Mask */
-
-#define EADC_AD0SPCTL0_CHSEL_Pos (0) /*!< EADC AD0SPCTL0: CHSEL Position */
-#define EADC_AD0SPCTL0_CHSEL_Msk (0xful << EADC_AD0SPCTL0_CHSEL_Pos) /*!< EADC AD0SPCTL0: CHSEL Mask */
-
-#define EADC_AD0SPCTL0_TRGSEL_Pos (4) /*!< EADC AD0SPCTL0: TRGSEL Position */
-#define EADC_AD0SPCTL0_TRGSEL_Msk (0xful << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EADC AD0SPCTL0: TRGSEL Mask */
-
-#define EADC_AD0SPCTL0_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL0: TRGDLYCNT Position */
-#define EADC_AD0SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL0_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL0: TRGDLYCNT Mask */
-
-#define EADC_AD0SPCTL0_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL0: TRGDLYDIV Position */
-#define EADC_AD0SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL0: TRGDLYDIV Mask */
-
-#define EADC_AD0SPCTL0_EXTREN_Pos (20) /*!< EADC AD0SPCTL0: EXTREN Position */
-#define EADC_AD0SPCTL0_EXTREN_Msk (0x1ul << EADC_AD0SPCTL0_EXTREN_Pos) /*!< EADC AD0SPCTL0: EXTREN Mask */
-
-#define EADC_AD0SPCTL0_EXTFEN_Pos (21) /*!< EADC AD0SPCTL0: EXTFEN Position */
-#define EADC_AD0SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL0_EXTFEN_Pos) /*!< EADC AD0SPCTL0: EXTFEN Mask */
-
-#define EADC_AD0SPCTL1_CHSEL_Pos (0) /*!< EADC AD0SPCTL1: CHSEL Position */
-#define EADC_AD0SPCTL1_CHSEL_Msk (0xful << EADC_AD0SPCTL1_CHSEL_Pos) /*!< EADC AD0SPCTL1: CHSEL Mask */
-
-#define EADC_AD0SPCTL1_TRGSEL_Pos (4) /*!< EADC AD0SPCTL1: TRGSEL Position */
-#define EADC_AD0SPCTL1_TRGSEL_Msk (0xful << EADC_AD0SPCTL1_TRGSEL_Pos) /*!< EADC AD0SPCTL1: TRGSEL Mask */
-
-#define EADC_AD0SPCTL1_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL1: TRGDLYCNT Position */
-#define EADC_AD0SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL1_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL1: TRGDLYCNT Mask */
-
-#define EADC_AD0SPCTL1_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL1: TRGDLYDIV Position */
-#define EADC_AD0SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL1_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL1: TRGDLYDIV Mask */
-
-#define EADC_AD0SPCTL1_EXTREN_Pos (20) /*!< EADC AD0SPCTL1: EXTREN Position */
-#define EADC_AD0SPCTL1_EXTREN_Msk (0x1ul << EADC_AD0SPCTL1_EXTREN_Pos) /*!< EADC AD0SPCTL1: EXTREN Mask */
-
-#define EADC_AD0SPCTL1_EXTFEN_Pos (21) /*!< EADC AD0SPCTL1: EXTFEN Position */
-#define EADC_AD0SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL1_EXTFEN_Pos) /*!< EADC AD0SPCTL1: EXTFEN Mask */
-
-#define EADC_AD0SPCTL2_CHSEL_Pos (0) /*!< EADC AD0SPCTL2: CHSEL Position */
-#define EADC_AD0SPCTL2_CHSEL_Msk (0xful << EADC_AD0SPCTL2_CHSEL_Pos) /*!< EADC AD0SPCTL2: CHSEL Mask */
-
-#define EADC_AD0SPCTL2_TRGSEL_Pos (4) /*!< EADC AD0SPCTL2: TRGSEL Position */
-#define EADC_AD0SPCTL2_TRGSEL_Msk (0xful << EADC_AD0SPCTL2_TRGSEL_Pos) /*!< EADC AD0SPCTL2: TRGSEL Mask */
-
-#define EADC_AD0SPCTL2_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL2: TRGDLYCNT Position */
-#define EADC_AD0SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL2_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL2: TRGDLYCNT Mask */
-
-#define EADC_AD0SPCTL2_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL2: TRGDLYDIV Position */
-#define EADC_AD0SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL2_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL2: TRGDLYDIV Mask */
-
-#define EADC_AD0SPCTL2_EXTREN_Pos (20) /*!< EADC AD0SPCTL2: EXTREN Position */
-#define EADC_AD0SPCTL2_EXTREN_Msk (0x1ul << EADC_AD0SPCTL2_EXTREN_Pos) /*!< EADC AD0SPCTL2: EXTREN Mask */
-
-#define EADC_AD0SPCTL2_EXTFEN_Pos (21) /*!< EADC AD0SPCTL2: EXTFEN Position */
-#define EADC_AD0SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL2_EXTFEN_Pos) /*!< EADC AD0SPCTL2: EXTFEN Mask */
-
-#define EADC_AD0SPCTL3_CHSEL_Pos (0) /*!< EADC AD0SPCTL3: CHSEL Position */
-#define EADC_AD0SPCTL3_CHSEL_Msk (0xful << EADC_AD0SPCTL3_CHSEL_Pos) /*!< EADC AD0SPCTL3: CHSEL Mask */
-
-#define EADC_AD0SPCTL3_TRGSEL_Pos (4) /*!< EADC AD0SPCTL3: TRGSEL Position */
-#define EADC_AD0SPCTL3_TRGSEL_Msk (0xful << EADC_AD0SPCTL3_TRGSEL_Pos) /*!< EADC AD0SPCTL3: TRGSEL Mask */
-
-#define EADC_AD0SPCTL3_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL3: TRGDLYCNT Position */
-#define EADC_AD0SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL3_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL3: TRGDLYCNT Mask */
-
-#define EADC_AD0SPCTL3_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL3: TRGDLYDIV Position */
-#define EADC_AD0SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL3_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL3: TRGDLYDIV Mask */
-
-#define EADC_AD0SPCTL3_EXTREN_Pos (20) /*!< EADC AD0SPCTL3: EXTREN Position */
-#define EADC_AD0SPCTL3_EXTREN_Msk (0x1ul << EADC_AD0SPCTL3_EXTREN_Pos) /*!< EADC AD0SPCTL3: EXTREN Mask */
-
-#define EADC_AD0SPCTL3_EXTFEN_Pos (21) /*!< EADC AD0SPCTL3: EXTFEN Position */
-#define EADC_AD0SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL3_EXTFEN_Pos) /*!< EADC AD0SPCTL3: EXTFEN Mask */
-
-#define EADC_AD0SPCTL4_CHSEL_Pos (0) /*!< EADC AD0SPCTL4: CHSEL Position */
-#define EADC_AD0SPCTL4_CHSEL_Msk (0xful << EADC_AD0SPCTL4_CHSEL_Pos) /*!< EADC AD0SPCTL4: CHSEL Mask */
-
-#define EADC_AD0SPCTL4_TRGSEL_Pos (4) /*!< EADC AD0SPCTL4: TRGSEL Position */
-#define EADC_AD0SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL4_TRGSEL_Pos) /*!< EADC AD0SPCTL4: TRGSEL Mask */
-
-#define EADC_AD0SPCTL4_EXTREN_Pos (20) /*!< EADC AD0SPCTL4: EXTREN Position */
-#define EADC_AD0SPCTL4_EXTREN_Msk (0x1ul << EADC_AD0SPCTL4_EXTREN_Pos) /*!< EADC AD0SPCTL4: EXTREN Mask */
-
-#define EADC_AD0SPCTL4_EXTFEN_Pos (21) /*!< EADC AD0SPCTL4: EXTFEN Position */
-#define EADC_AD0SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL4_EXTFEN_Pos) /*!< EADC AD0SPCTL4: EXTFEN Mask */
-
-#define EADC_AD0SPCTL5_CHSEL_Pos (0) /*!< EADC AD0SPCTL5: CHSEL Position */
-#define EADC_AD0SPCTL5_CHSEL_Msk (0xful << EADC_AD0SPCTL5_CHSEL_Pos) /*!< EADC AD0SPCTL5: CHSEL Mask */
-
-#define EADC_AD0SPCTL5_TRGSEL_Pos (4) /*!< EADC AD0SPCTL5: TRGSEL Position */
-#define EADC_AD0SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL5_TRGSEL_Pos) /*!< EADC AD0SPCTL5: TRGSEL Mask */
-
-#define EADC_AD0SPCTL5_EXTREN_Pos (20) /*!< EADC AD0SPCTL5: EXTREN Position */
-#define EADC_AD0SPCTL5_EXTREN_Msk (0x1ul << EADC_AD0SPCTL5_EXTREN_Pos) /*!< EADC AD0SPCTL5: EXTREN Mask */
-
-#define EADC_AD0SPCTL5_EXTFEN_Pos (21) /*!< EADC AD0SPCTL5: EXTFEN Position */
-#define EADC_AD0SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL5_EXTFEN_Pos) /*!< EADC AD0SPCTL5: EXTFEN Mask */
-
-#define EADC_AD0SPCTL6_CHSEL_Pos (0) /*!< EADC AD0SPCTL6: CHSEL Position */
-#define EADC_AD0SPCTL6_CHSEL_Msk (0xful << EADC_AD0SPCTL6_CHSEL_Pos) /*!< EADC AD0SPCTL6: CHSEL Mask */
-
-#define EADC_AD0SPCTL6_TRGSEL_Pos (4) /*!< EADC AD0SPCTL6: TRGSEL Position */
-#define EADC_AD0SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL6_TRGSEL_Pos) /*!< EADC AD0SPCTL6: TRGSEL Mask */
-
-#define EADC_AD0SPCTL6_EXTREN_Pos (20) /*!< EADC AD0SPCTL6: EXTREN Position */
-#define EADC_AD0SPCTL6_EXTREN_Msk (0x1ul << EADC_AD0SPCTL6_EXTREN_Pos) /*!< EADC AD0SPCTL6: EXTREN Mask */
-
-#define EADC_AD0SPCTL6_EXTFEN_Pos (21) /*!< EADC AD0SPCTL6: EXTFEN Position */
-#define EADC_AD0SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL6_EXTFEN_Pos) /*!< EADC AD0SPCTL6: EXTFEN Mask */
-
-#define EADC_AD0SPCTL7_CHSEL_Pos (0) /*!< EADC AD0SPCTL7: CHSEL Position */
-#define EADC_AD0SPCTL7_CHSEL_Msk (0xful << EADC_AD0SPCTL7_CHSEL_Pos) /*!< EADC AD0SPCTL7: CHSEL Mask */
-
-#define EADC_AD0SPCTL7_TRGSEL_Pos (4) /*!< EADC AD0SPCTL7: TRGSEL Position */
-#define EADC_AD0SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL7_TRGSEL_Pos) /*!< EADC AD0SPCTL7: TRGSEL Mask */
-
-#define EADC_AD0SPCTL7_EXTREN_Pos (20) /*!< EADC AD0SPCTL7: EXTREN Position */
-#define EADC_AD0SPCTL7_EXTREN_Msk (0x1ul << EADC_AD0SPCTL7_EXTREN_Pos) /*!< EADC AD0SPCTL7: EXTREN Mask */
-
-#define EADC_AD0SPCTL7_EXTFEN_Pos (21) /*!< EADC AD0SPCTL7: EXTFEN Position */
-#define EADC_AD0SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL7_EXTFEN_Pos) /*!< EADC AD0SPCTL7: EXTFEN Mask */
-
-#define EADC_AD1SPCTL0_CHSEL_Pos (0) /*!< EADC AD1SPCTL0: CHSEL Position */
-#define EADC_AD1SPCTL0_CHSEL_Msk (0xful << EADC_AD1SPCTL0_CHSEL_Pos) /*!< EADC AD1SPCTL0: CHSEL Mask */
-
-#define EADC_AD1SPCTL0_TRGSEL_Pos (4) /*!< EADC AD1SPCTL0: TRGSEL Position */
-#define EADC_AD1SPCTL0_TRGSEL_Msk (0xful << EADC_AD1SPCTL0_TRGSEL_Pos) /*!< EADC AD1SPCTL0: TRGSEL Mask */
-
-#define EADC_AD1SPCTL0_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL0: TRGDLYCNT Position */
-#define EADC_AD1SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL0_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL0: TRGDLYCNT Mask */
-
-#define EADC_AD1SPCTL0_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL0: TRGDLYDIV Position */
-#define EADC_AD1SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL0_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL0: TRGDLYDIV Mask */
-
-#define EADC_AD1SPCTL0_EXTREN_Pos (20) /*!< EADC AD1SPCTL0: EXTREN Position */
-#define EADC_AD1SPCTL0_EXTREN_Msk (0x1ul << EADC_AD1SPCTL0_EXTREN_Pos) /*!< EADC AD1SPCTL0: EXTREN Mask */
-
-#define EADC_AD1SPCTL0_EXTFEN_Pos (21) /*!< EADC AD1SPCTL0: EXTFEN Position */
-#define EADC_AD1SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL0_EXTFEN_Pos) /*!< EADC AD1SPCTL0: EXTFEN Mask */
-
-#define EADC_AD1SPCTL1_CHSEL_Pos (0) /*!< EADC AD1SPCTL1: CHSEL Position */
-#define EADC_AD1SPCTL1_CHSEL_Msk (0xful << EADC_AD1SPCTL1_CHSEL_Pos) /*!< EADC AD1SPCTL1: CHSEL Mask */
-
-#define EADC_AD1SPCTL1_TRGSEL_Pos (4) /*!< EADC AD1SPCTL1: TRGSEL Position */
-#define EADC_AD1SPCTL1_TRGSEL_Msk (0xful << EADC_AD1SPCTL1_TRGSEL_Pos) /*!< EADC AD1SPCTL1: TRGSEL Mask */
-
-#define EADC_AD1SPCTL1_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL1: TRGDLYCNT Position */
-#define EADC_AD1SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL1_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL1: TRGDLYCNT Mask */
-
-#define EADC_AD1SPCTL1_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL1: TRGDLYDIV Position */
-#define EADC_AD1SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL1_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL1: TRGDLYDIV Mask */
-
-#define EADC_AD1SPCTL1_EXTREN_Pos (20) /*!< EADC AD1SPCTL1: EXTREN Position */
-#define EADC_AD1SPCTL1_EXTREN_Msk (0x1ul << EADC_AD1SPCTL1_EXTREN_Pos) /*!< EADC AD1SPCTL1: EXTREN Mask */
-
-#define EADC_AD1SPCTL1_EXTFEN_Pos (21) /*!< EADC AD1SPCTL1: EXTFEN Position */
-#define EADC_AD1SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL1_EXTFEN_Pos) /*!< EADC AD1SPCTL1: EXTFEN Mask */
-
-#define EADC_AD1SPCTL2_CHSEL_Pos (0) /*!< EADC AD1SPCTL2: CHSEL Position */
-#define EADC_AD1SPCTL2_CHSEL_Msk (0xful << EADC_AD1SPCTL2_CHSEL_Pos) /*!< EADC AD1SPCTL2: CHSEL Mask */
-
-#define EADC_AD1SPCTL2_TRGSEL_Pos (4) /*!< EADC AD1SPCTL2: TRGSEL Position */
-#define EADC_AD1SPCTL2_TRGSEL_Msk (0xful << EADC_AD1SPCTL2_TRGSEL_Pos) /*!< EADC AD1SPCTL2: TRGSEL Mask */
-
-#define EADC_AD1SPCTL2_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL2: TRGDLYCNT Position */
-#define EADC_AD1SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL2_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL2: TRGDLYCNT Mask */
-
-#define EADC_AD1SPCTL2_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL2: TRGDLYDIV Position */
-#define EADC_AD1SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL2_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL2: TRGDLYDIV Mask */
-
-#define EADC_AD1SPCTL2_EXTREN_Pos (20) /*!< EADC AD1SPCTL2: EXTREN Position */
-#define EADC_AD1SPCTL2_EXTREN_Msk (0x1ul << EADC_AD1SPCTL2_EXTREN_Pos) /*!< EADC AD1SPCTL2: EXTREN Mask */
-
-#define EADC_AD1SPCTL2_EXTFEN_Pos (21) /*!< EADC AD1SPCTL2: EXTFEN Position */
-#define EADC_AD1SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL2_EXTFEN_Pos) /*!< EADC AD1SPCTL2: EXTFEN Mask */
-
-#define EADC_AD1SPCTL3_CHSEL_Pos (0) /*!< EADC AD1SPCTL3: CHSEL Position */
-#define EADC_AD1SPCTL3_CHSEL_Msk (0xful << EADC_AD1SPCTL3_CHSEL_Pos) /*!< EADC AD1SPCTL3: CHSEL Mask */
-
-#define EADC_AD1SPCTL3_TRGSEL_Pos (4) /*!< EADC AD1SPCTL3: TRGSEL Position */
-#define EADC_AD1SPCTL3_TRGSEL_Msk (0xful << EADC_AD1SPCTL3_TRGSEL_Pos) /*!< EADC AD1SPCTL3: TRGSEL Mask */
-
-#define EADC_AD1SPCTL3_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL3: TRGDLYCNT Position */
-#define EADC_AD1SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL3_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL3: TRGDLYCNT Mask */
-
-#define EADC_AD1SPCTL3_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL3: TRGDLYDIV Position */
-#define EADC_AD1SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL3_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL3: TRGDLYDIV Mask */
-
-#define EADC_AD1SPCTL3_EXTREN_Pos (20) /*!< EADC AD1SPCTL3: EXTREN Position */
-#define EADC_AD1SPCTL3_EXTREN_Msk (0x1ul << EADC_AD1SPCTL3_EXTREN_Pos) /*!< EADC AD1SPCTL3: EXTREN Mask */
-
-#define EADC_AD1SPCTL3_EXTFEN_Pos (21) /*!< EADC AD1SPCTL3: EXTFEN Position */
-#define EADC_AD1SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL3_EXTFEN_Pos) /*!< EADC AD1SPCTL3: EXTFEN Mask */
-
-#define EADC_AD1SPCTL4_CHSEL_Pos (0) /*!< EADC AD1SPCTL4: CHSEL Position */
-#define EADC_AD1SPCTL4_CHSEL_Msk (0xful << EADC_AD1SPCTL4_CHSEL_Pos) /*!< EADC AD1SPCTL4: CHSEL Mask */
-
-#define EADC_AD1SPCTL4_TRGSEL_Pos (4) /*!< EADC AD1SPCTL4: TRGSEL Position */
-#define EADC_AD1SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL4_TRGSEL_Pos) /*!< EADC AD1SPCTL4: TRGSEL Mask */
-
-#define EADC_AD1SPCTL4_EXTREN_Pos (20) /*!< EADC AD1SPCTL4: EXTREN Position */
-#define EADC_AD1SPCTL4_EXTREN_Msk (0x1ul << EADC_AD1SPCTL4_EXTREN_Pos) /*!< EADC AD1SPCTL4: EXTREN Mask */
-
-#define EADC_AD1SPCTL4_EXTFEN_Pos (21) /*!< EADC AD1SPCTL4: EXTFEN Position */
-#define EADC_AD1SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL4_EXTFEN_Pos) /*!< EADC AD1SPCTL4: EXTFEN Mask */
-
-#define EADC_AD1SPCTL5_CHSEL_Pos (0) /*!< EADC AD1SPCTL5: CHSEL Position */
-#define EADC_AD1SPCTL5_CHSEL_Msk (0xful << EADC_AD1SPCTL5_CHSEL_Pos) /*!< EADC AD1SPCTL5: CHSEL Mask */
-
-#define EADC_AD1SPCTL5_TRGSEL_Pos (4) /*!< EADC AD1SPCTL5: TRGSEL Position */
-#define EADC_AD1SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL5_TRGSEL_Pos) /*!< EADC AD1SPCTL5: TRGSEL Mask */
-
-#define EADC_AD1SPCTL5_EXTREN_Pos (20) /*!< EADC AD1SPCTL5: EXTREN Position */
-#define EADC_AD1SPCTL5_EXTREN_Msk (0x1ul << EADC_AD1SPCTL5_EXTREN_Pos) /*!< EADC AD1SPCTL5: EXTREN Mask */
-
-#define EADC_AD1SPCTL5_EXTFEN_Pos (21) /*!< EADC AD1SPCTL5: EXTFEN Position */
-#define EADC_AD1SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL5_EXTFEN_Pos) /*!< EADC AD1SPCTL5: EXTFEN Mask */
-
-#define EADC_AD1SPCTL6_CHSEL_Pos (0) /*!< EADC AD1SPCTL6: CHSEL Position */
-#define EADC_AD1SPCTL6_CHSEL_Msk (0xful << EADC_AD1SPCTL6_CHSEL_Pos) /*!< EADC AD1SPCTL6: CHSEL Mask */
-
-#define EADC_AD1SPCTL6_TRGSEL_Pos (4) /*!< EADC AD1SPCTL6: TRGSEL Position */
-#define EADC_AD1SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL6_TRGSEL_Pos) /*!< EADC AD1SPCTL6: TRGSEL Mask */
-
-#define EADC_AD1SPCTL6_EXTREN_Pos (20) /*!< EADC AD1SPCTL6: EXTREN Position */
-#define EADC_AD1SPCTL6_EXTREN_Msk (0x1ul << EADC_AD1SPCTL6_EXTREN_Pos) /*!< EADC AD1SPCTL6: EXTREN Mask */
-
-#define EADC_AD1SPCTL6_EXTFEN_Pos (21) /*!< EADC AD1SPCTL6: EXTFEN Position */
-#define EADC_AD1SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL6_EXTFEN_Pos) /*!< EADC AD1SPCTL6: EXTFEN Mask */
-
-#define EADC_AD1SPCTL7_CHSEL_Pos (0) /*!< EADC AD1SPCTL7: CHSEL Position */
-#define EADC_AD1SPCTL7_CHSEL_Msk (0xful << EADC_AD1SPCTL7_CHSEL_Pos) /*!< EADC AD1SPCTL7: CHSEL Mask */
-
-#define EADC_AD1SPCTL7_TRGSEL_Pos (4) /*!< EADC AD1SPCTL7: TRGSEL Position */
-#define EADC_AD1SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL7_TRGSEL_Pos) /*!< EADC AD1SPCTL7: TRGSEL Mask */
-
-#define EADC_AD1SPCTL7_EXTREN_Pos (20) /*!< EADC AD1SPCTL7: EXTREN Position */
-#define EADC_AD1SPCTL7_EXTREN_Msk (0x1ul << EADC_AD1SPCTL7_EXTREN_Pos) /*!< EADC AD1SPCTL7: EXTREN Mask */
-
-#define EADC_AD1SPCTL7_EXTFEN_Pos (21) /*!< EADC AD1SPCTL7: EXTFEN Position */
-#define EADC_AD1SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL7_EXTFEN_Pos) /*!< EADC AD1SPCTL7: EXTFEN Mask */
-
-#define EADC_SIMUSEL_SIMUSEL0_Pos (0) /*!< EADC SIMUSEL: SIMUSEL0 Position */
-#define EADC_SIMUSEL_SIMUSEL0_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL0_Pos) /*!< EADC SIMUSEL: SIMUSEL0 Mask */
-
-#define EADC_SIMUSEL_SIMUSEL1_Pos (1) /*!< EADC SIMUSEL: SIMUSEL1 Position */
-#define EADC_SIMUSEL_SIMUSEL1_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL1_Pos) /*!< EADC SIMUSEL: SIMUSEL1 Mask */
-
-#define EADC_SIMUSEL_SIMUSEL2_Pos (2) /*!< EADC SIMUSEL: SIMUSEL2 Position */
-#define EADC_SIMUSEL_SIMUSEL2_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL2_Pos) /*!< EADC SIMUSEL: SIMUSEL2 Mask */
-
-#define EADC_SIMUSEL_SIMUSEL3_Pos (3) /*!< EADC SIMUSEL: SIMUSEL3 Position */
-#define EADC_SIMUSEL_SIMUSEL3_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL3_Pos) /*!< EADC SIMUSEL: SIMUSEL3 Mask */
-
-#define EADC_SIMUSEL_SIMUSEL4_Pos (4) /*!< EADC SIMUSEL: SIMUSEL4 Position */
-#define EADC_SIMUSEL_SIMUSEL4_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL4_Pos) /*!< EADC SIMUSEL: SIMUSEL4 Mask */
-
-#define EADC_SIMUSEL_SIMUSEL5_Pos (5) /*!< EADC SIMUSEL: SIMUSEL5 Position */
-#define EADC_SIMUSEL_SIMUSEL5_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL5_Pos) /*!< EADC SIMUSEL: SIMUSEL5 Mask */
-
-#define EADC_SIMUSEL_SIMUSEL6_Pos (6) /*!< EADC SIMUSEL: SIMUSEL6 Position */
-#define EADC_SIMUSEL_SIMUSEL6_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL6_Pos) /*!< EADC SIMUSEL: SIMUSEL6 Mask */
-
-#define EADC_SIMUSEL_SIMUSEL7_Pos (7) /*!< EADC SIMUSEL: SIMUSEL7 Position */
-#define EADC_SIMUSEL_SIMUSEL7_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL7_Pos) /*!< EADC SIMUSEL: SIMUSEL7 Mask */
-
-#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC CMP0: ADCMPEN Position */
-#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC CMP0: ADCMPEN Mask */
-
-#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC CMP0: ADCMPIE Position */
-#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC CMP0: ADCMPIE Mask */
-
-#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC CMP0: CMPCOND Position */
-#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC CMP0: CMPCOND Mask */
-
-#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC CMP0: CMPSPL Position */
-#define EADC_CMP0_CMPSPL_Msk (0x7ul << EADC_CMP0_CMPSPL_Pos) /*!< EADC CMP0: CMPSPL Mask */
-
-#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC CMP0: CMPMCNT Position */
-#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC CMP0: CMPMCNT Mask */
-
-#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC CMP0: CMPDAT Position */
-#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC CMP0: CMPDAT Mask */
-
-#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC CMP1: ADCMPEN Position */
-#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC CMP1: ADCMPEN Mask */
-
-#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC CMP1: ADCMPIE Position */
-#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC CMP1: ADCMPIE Mask */
-
-#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC CMP1: CMPCOND Position */
-#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC CMP1: CMPCOND Mask */
-
-#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC CMP1: CMPSPL Position */
-#define EADC_CMP1_CMPSPL_Msk (0x7ul << EADC_CMP1_CMPSPL_Pos) /*!< EADC CMP1: CMPSPL Mask */
-
-#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC CMP1: CMPMCNT Position */
-#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC CMP1: CMPMCNT Mask */
-
-#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC CMP1: CMPDAT Position */
-#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC CMP1: CMPDAT Mask */
-
-#define EADC_STATUS0_VALID_Pos (0) /*!< EADC STATUS0: VALID Position */
-#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC STATUS0: VALID Mask */
-
-#define EADC_STATUS0_OV_Pos (16) /*!< EADC STATUS0: OV Position */
-#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC STATUS0: OV Mask */
-
-#define EADC_STATUS1_ADIF0_Pos (0) /*!< EADC STATUS1: ADIF0 Position */
-#define EADC_STATUS1_ADIF0_Msk (0x1ul << EADC_STATUS1_ADIF0_Pos) /*!< EADC STATUS1: ADIF0 Mask */
-
-#define EADC_STATUS1_ADIF1_Pos (1) /*!< EADC STATUS1: ADIF1 Position */
-#define EADC_STATUS1_ADIF1_Msk (0x1ul << EADC_STATUS1_ADIF1_Pos) /*!< EADC STATUS1: ADIF1 Mask */
-
-#define EADC_STATUS1_ADIF2_Pos (2) /*!< EADC STATUS1: ADIF2 Position */
-#define EADC_STATUS1_ADIF2_Msk (0x1ul << EADC_STATUS1_ADIF2_Pos) /*!< EADC STATUS1: ADIF2 Mask */
-
-#define EADC_STATUS1_ADIF3_Pos (3) /*!< EADC STATUS1: ADIF3 Position */
-#define EADC_STATUS1_ADIF3_Msk (0x1ul << EADC_STATUS1_ADIF3_Pos) /*!< EADC STATUS1: ADIF3 Mask */
-
-#define EADC_STATUS1_ADCMPO0_Pos (4) /*!< EADC STATUS1: ADCMPO0 Position */
-#define EADC_STATUS1_ADCMPO0_Msk (0x1ul << EADC_STATUS1_ADCMPO0_Pos) /*!< EADC STATUS1: ADCMPO0 Mask */
-
-#define EADC_STATUS1_ADCMPO1_Pos (5) /*!< EADC STATUS1: ADCMPO1 Position */
-#define EADC_STATUS1_ADCMPO1_Msk (0x1ul << EADC_STATUS1_ADCMPO1_Pos) /*!< EADC STATUS1: ADCMPO1 Mask */
-
-#define EADC_STATUS1_ADCMPF0_Pos (6) /*!< EADC STATUS1: ADCMPF0 Position */
-#define EADC_STATUS1_ADCMPF0_Msk (0x1ul << EADC_STATUS1_ADCMPF0_Pos) /*!< EADC STATUS1: ADCMPF0 Mask */
-
-#define EADC_STATUS1_ADCMPF1_Pos (7) /*!< EADC STATUS1: ADCMPF1 Position */
-#define EADC_STATUS1_ADCMPF1_Msk (0x1ul << EADC_STATUS1_ADCMPF1_Pos) /*!< EADC STATUS1: ADCMPF1 Mask */
-
-#define EADC_STATUS1_BUSY0_Pos (8) /*!< EADC STATUS1: BUSY0 Position */
-#define EADC_STATUS1_BUSY0_Msk (0x1ul << EADC_STATUS1_BUSY0_Pos) /*!< EADC STATUS1: BUSY0 Mask */
-
-#define EADC_STATUS1_CHANNEL0_Pos (12) /*!< EADC STATUS1: CHANNEL0 Position */
-#define EADC_STATUS1_CHANNEL0_Msk (0xful << EADC_STATUS1_CHANNEL0_Pos) /*!< EADC STATUS1: CHANNEL0 Mask */
-
-#define EADC_STATUS1_BUSY1_Pos (16) /*!< EADC STATUS1: BUSY1 Position */
-#define EADC_STATUS1_BUSY1_Msk (0x1ul << EADC_STATUS1_BUSY1_Pos) /*!< EADC STATUS1: BUSY1 Mask */
-
-#define EADC_STATUS1_CHANNEL1_Pos (20) /*!< EADC STATUS1: CHANNEL1 Position */
-#define EADC_STATUS1_CHANNEL1_Msk (0xful << EADC_STATUS1_CHANNEL1_Pos) /*!< EADC STATUS1: CHANNEL1 Mask */
-
-#define EADC_STATUS1_ADOVIF_Pos (24) /*!< EADC STATUS1: ADOVIF Position */
-#define EADC_STATUS1_ADOVIF_Msk (0x1ul << EADC_STATUS1_ADOVIF_Pos) /*!< EADC STATUS1: ADOVIF Mask */
-
-#define EADC_STATUS1_STOVF_Pos (25) /*!< EADC STATUS1: STOVF Position */
-#define EADC_STATUS1_STOVF_Msk (0x1ul << EADC_STATUS1_STOVF_Pos) /*!< EADC STATUS1: STOVF Mask */
-
-#define EADC_STATUS1_AVALID_Pos (26) /*!< EADC STATUS1: AVALID Position */
-#define EADC_STATUS1_AVALID_Msk (0x1ul << EADC_STATUS1_AVALID_Pos) /*!< EADC STATUS1: AVALID Mask */
-
-#define EADC_STATUS1_AOV_Pos (27) /*!< EADC STATUS1: AOV Position */
-#define EADC_STATUS1_AOV_Msk (0x1ul << EADC_STATUS1_AOV_Pos) /*!< EADC STATUS1: AOV Mask */
-
-#define EADC_EXTSMPT_EXTSMPT0_Pos (0) /*!< EADC EXTSMPT: EXTSMPT0 Position */
-#define EADC_EXTSMPT_EXTSMPT0_Msk (0xfful << EADC_EXTSMPT_EXTSMPT0_Pos) /*!< EADC EXTSMPT: EXTSMPT0 Mask */
-
-#define EADC_EXTSMPT_EXTSMPT1_Pos (16) /*!< EADC EXTSMPT: EXTSMPT1 Position */
-#define EADC_EXTSMPT_EXTSMPT1_Msk (0xfful << EADC_EXTSMPT_EXTSMPT1_Pos) /*!< EADC EXTSMPT: EXTSMPT1 Mask */
-
-#define EADC_AD0DDAT0_RESULT_Pos (0) /*!< EADC AD0DDAT0: RESULT Position */
-#define EADC_AD0DDAT0_RESULT_Msk (0xffful << EADC_AD0DDAT0_RESULT_Pos) /*!< EADC AD0DDAT0: RESULT Mask */
-
-#define EADC_AD0DDAT0_VALID_Pos (16) /*!< EADC AD0DDAT0: VALID Position */
-#define EADC_AD0DDAT0_VALID_Msk (0x1ul << EADC_AD0DDAT0_VALID_Pos) /*!< EADC AD0DDAT0: VALID Mask */
-
-#define EADC_AD0DDAT1_RESULT_Pos (0) /*!< EADC AD0DDAT1: RESULT Position */
-#define EADC_AD0DDAT1_RESULT_Msk (0xffful << EADC_AD0DDAT1_RESULT_Pos) /*!< EADC AD0DDAT1: RESULT Mask */
-
-#define EADC_AD0DDAT1_VALID_Pos (16) /*!< EADC AD0DDAT1: VALID Position */
-#define EADC_AD0DDAT1_VALID_Msk (0x1ul << EADC_AD0DDAT1_VALID_Pos) /*!< EADC AD0DDAT1: VALID Mask */
-
-#define EADC_AD0DDAT2_RESULT_Pos (0) /*!< EADC AD0DDAT2: RESULT Position */
-#define EADC_AD0DDAT2_RESULT_Msk (0xffful << EADC_AD0DDAT2_RESULT_Pos) /*!< EADC AD0DDAT2: RESULT Mask */
-
-#define EADC_AD0DDAT2_VALID_Pos (16) /*!< EADC AD0DDAT2: VALID Position */
-#define EADC_AD0DDAT2_VALID_Msk (0x1ul << EADC_AD0DDAT2_VALID_Pos) /*!< EADC AD0DDAT2: VALID Mask */
-
-#define EADC_AD0DDAT3_RESULT_Pos (0) /*!< EADC AD0DDAT3: RESULT Position */
-#define EADC_AD0DDAT3_RESULT_Msk (0xffful << EADC_AD0DDAT3_RESULT_Pos) /*!< EADC AD0DDAT3: RESULT Mask */
-
-#define EADC_AD0DDAT3_VALID_Pos (16) /*!< EADC AD0DDAT3: VALID Position */
-#define EADC_AD0DDAT3_VALID_Msk (0x1ul << EADC_AD0DDAT3_VALID_Pos) /*!< EADC AD0DDAT3: VALID Mask */
-
-#define EADC_AD1DDAT0_RESULT_Pos (0) /*!< EADC AD1DDAT0: RESULT Position */
-#define EADC_AD1DDAT0_RESULT_Msk (0xffful << EADC_AD1DDAT0_RESULT_Pos) /*!< EADC AD1DDAT0: RESULT Mask */
-
-#define EADC_AD1DDAT0_VALID_Pos (16) /*!< EADC AD1DDAT0: VALID Position */
-#define EADC_AD1DDAT0_VALID_Msk (0x1ul << EADC_AD1DDAT0_VALID_Pos) /*!< EADC AD1DDAT0: VALID Mask */
-
-#define EADC_AD1DDAT1_RESULT_Pos (0) /*!< EADC AD1DDAT1: RESULT Position */
-#define EADC_AD1DDAT1_RESULT_Msk (0xffful << EADC_AD1DDAT1_RESULT_Pos) /*!< EADC AD1DDAT1: RESULT Mask */
-
-#define EADC_AD1DDAT1_VALID_Pos (16) /*!< EADC AD1DDAT1: VALID Position */
-#define EADC_AD1DDAT1_VALID_Msk (0x1ul << EADC_AD1DDAT1_VALID_Pos) /*!< EADC AD1DDAT1: VALID Mask */
-
-#define EADC_AD1DDAT2_RESULT_Pos (0) /*!< EADC AD1DDAT2: RESULT Position */
-#define EADC_AD1DDAT2_RESULT_Msk (0xffful << EADC_AD1DDAT2_RESULT_Pos) /*!< EADC AD1DDAT2: RESULT Mask */
-
-#define EADC_AD1DDAT2_VALID_Pos (16) /*!< EADC AD1DDAT2: VALID Position */
-#define EADC_AD1DDAT2_VALID_Msk (0x1ul << EADC_AD1DDAT2_VALID_Pos) /*!< EADC AD1DDAT2: VALID Mask */
-
-#define EADC_AD1DDAT3_RESULT_Pos (0) /*!< EADC AD1DDAT3: RESULT Position */
-#define EADC_AD1DDAT3_RESULT_Msk (0xffful << EADC_AD1DDAT3_RESULT_Pos) /*!< EADC AD1DDAT3: RESULT Mask */
-
-#define EADC_AD1DDAT3_VALID_Pos (16) /*!< EADC AD1DDAT3: VALID Position */
-#define EADC_AD1DDAT3_VALID_Msk (0x1ul << EADC_AD1DDAT3_VALID_Pos) /*!< EADC AD1DDAT3: VALID Mask */
-
-#define EADC_DBMEN_AD0DBM0_Pos (0) /*!< EADC DBMEN: AD0DBM0 Position */
-#define EADC_DBMEN_AD0DBM0_Msk (0x1ul << EADC_DBMEN_AD0DBM0_Pos) /*!< EADC DBMEN: AD0DBM0 Mask */
-
-#define EADC_DBMEN_AD0DBM1_Pos (1) /*!< EADC DBMEN: AD0DBM1 Position */
-#define EADC_DBMEN_AD0DBM1_Msk (0x1ul << EADC_DBMEN_AD0DBM1_Pos) /*!< EADC DBMEN: AD0DBM1 Mask */
-
-#define EADC_DBMEN_AD0DBM2_Pos (2) /*!< EADC DBMEN: AD0DBM2 Position */
-#define EADC_DBMEN_AD0DBM2_Msk (0x1ul << EADC_DBMEN_AD0DBM2_Pos) /*!< EADC DBMEN: AD0DBM2 Mask */
-
-#define EADC_DBMEN_AD0DBM3_Pos (3) /*!< EADC DBMEN: AD0DBM3 Position */
-#define EADC_DBMEN_AD0DBM3_Msk (0x1ul << EADC_DBMEN_AD0DBM3_Pos) /*!< EADC DBMEN: AD0DBM3 Mask */
-
-#define EADC_DBMEN_AD1DBM0_Pos (8) /*!< EADC DBMEN: AD1DBM0 Position */
-#define EADC_DBMEN_AD1DBM0_Msk (0x1ul << EADC_DBMEN_AD1DBM0_Pos) /*!< EADC DBMEN: AD1DBM0 Mask */
-
-#define EADC_DBMEN_AD1DBM1_Pos (9) /*!< EADC DBMEN: AD1DBM1 Position */
-#define EADC_DBMEN_AD1DBM1_Msk (0x1ul << EADC_DBMEN_AD1DBM1_Pos) /*!< EADC DBMEN: AD1DBM1 Mask */
-
-#define EADC_DBMEN_AD1DBM2_Pos (10) /*!< EADC DBMEN: AD1DBM2 Position */
-#define EADC_DBMEN_AD1DBM2_Msk (0x1ul << EADC_DBMEN_AD1DBM2_Pos) /*!< EADC DBMEN: AD1DBM2 Mask */
-
-#define EADC_DBMEN_AD1DBM3_Pos (11) /*!< EADC DBMEN: AD1DBM3 Position */
-#define EADC_DBMEN_AD1DBM3_Msk (0x1ul << EADC_DBMEN_AD1DBM3_Pos) /*!< EADC DBMEN: AD1DBM3 Mask */
-
-#define EADC_INTSRC0_AD0SPIE0_Pos (0) /*!< EADC INTSRC0: AD0SPIE0 Position */
-#define EADC_INTSRC0_AD0SPIE0_Msk (0x1ul << EADC_INTSRC0_AD0SPIE0_Pos) /*!< EADC INTSRC0: AD0SPIE0 Mask */
-
-#define EADC_INTSRC0_AD0SPIE1_Pos (1) /*!< EADC INTSRC0: AD0SPIE1 Position */
-#define EADC_INTSRC0_AD0SPIE1_Msk (0x1ul << EADC_INTSRC0_AD0SPIE1_Pos) /*!< EADC INTSRC0: AD0SPIE1 Mask */
-
-#define EADC_INTSRC0_AD0SPIE2_Pos (2) /*!< EADC INTSRC0: AD0SPIE2 Position */
-#define EADC_INTSRC0_AD0SPIE2_Msk (0x1ul << EADC_INTSRC0_AD0SPIE2_Pos) /*!< EADC INTSRC0: AD0SPIE2 Mask */
-
-#define EADC_INTSRC0_AD0SPIE3_Pos (3) /*!< EADC INTSRC0: AD0SPIE3 Position */
-#define EADC_INTSRC0_AD0SPIE3_Msk (0x1ul << EADC_INTSRC0_AD0SPIE3_Pos) /*!< EADC INTSRC0: AD0SPIE3 Mask */
-
-#define EADC_INTSRC0_AD0SPIE4_Pos (4) /*!< EADC INTSRC0: AD0SPIE4 Position */
-#define EADC_INTSRC0_AD0SPIE4_Msk (0x1ul << EADC_INTSRC0_AD0SPIE4_Pos) /*!< EADC INTSRC0: AD0SPIE4 Mask */
-
-#define EADC_INTSRC0_AD0SPIE5_Pos (5) /*!< EADC INTSRC0: AD0SPIE5 Position */
-#define EADC_INTSRC0_AD0SPIE5_Msk (0x1ul << EADC_INTSRC0_AD0SPIE5_Pos) /*!< EADC INTSRC0: AD0SPIE5 Mask */
-
-#define EADC_INTSRC0_AD0SPIE6_Pos (6) /*!< EADC INTSRC0: AD0SPIE6 Position */
-#define EADC_INTSRC0_AD0SPIE6_Msk (0x1ul << EADC_INTSRC0_AD0SPIE6_Pos) /*!< EADC INTSRC0: AD0SPIE6 Mask */
-
-#define EADC_INTSRC0_AD0SPIE7_Pos (7) /*!< EADC INTSRC0: AD0SPIE7 Position */
-#define EADC_INTSRC0_AD0SPIE7_Msk (0x1ul << EADC_INTSRC0_AD0SPIE7_Pos) /*!< EADC INTSRC0: AD0SPIE7 Mask */
-
-#define EADC_INTSRC0_AD1SPIE0_Pos (8) /*!< EADC INTSRC0: AD1SPIE0 Position */
-#define EADC_INTSRC0_AD1SPIE0_Msk (0x1ul << EADC_INTSRC0_AD1SPIE0_Pos) /*!< EADC INTSRC0: AD1SPIE0 Mask */
-
-#define EADC_INTSRC0_AD1SPIE1_Pos (9) /*!< EADC INTSRC0: AD1SPIE1 Position */
-#define EADC_INTSRC0_AD1SPIE1_Msk (0x1ul << EADC_INTSRC0_AD1SPIE1_Pos) /*!< EADC INTSRC0: AD1SPIE1 Mask */
-
-#define EADC_INTSRC0_AD1SPIE2_Pos (10) /*!< EADC INTSRC0: AD1SPIE2 Position */
-#define EADC_INTSRC0_AD1SPIE2_Msk (0x1ul << EADC_INTSRC0_AD1SPIE2_Pos) /*!< EADC INTSRC0: AD1SPIE2 Mask */
-
-#define EADC_INTSRC0_AD1SPIE3_Pos (11) /*!< EADC INTSRC0: AD1SPIE3 Position */
-#define EADC_INTSRC0_AD1SPIE3_Msk (0x1ul << EADC_INTSRC0_AD1SPIE3_Pos) /*!< EADC INTSRC0: AD1SPIE3 Mask */
-
-#define EADC_INTSRC0_AD1SPIE4_Pos (12) /*!< EADC INTSRC0: AD1SPIE4 Position */
-#define EADC_INTSRC0_AD1SPIE4_Msk (0x1ul << EADC_INTSRC0_AD1SPIE4_Pos) /*!< EADC INTSRC0: AD1SPIE4 Mask */
-
-#define EADC_INTSRC0_AD1SPIE5_Pos (13) /*!< EADC INTSRC0: AD1SPIE5 Position */
-#define EADC_INTSRC0_AD1SPIE5_Msk (0x1ul << EADC_INTSRC0_AD1SPIE5_Pos) /*!< EADC INTSRC0: AD1SPIE5 Mask */
-
-#define EADC_INTSRC0_AD1SPIE6_Pos (14) /*!< EADC INTSRC0: AD1SPIE6 Position */
-#define EADC_INTSRC0_AD1SPIE6_Msk (0x1ul << EADC_INTSRC0_AD1SPIE6_Pos) /*!< EADC INTSRC0: AD1SPIE6 Mask */
-
-#define EADC_INTSRC0_AD1SPIE7_Pos (15) /*!< EADC INTSRC0: AD1SPIE7 Position */
-#define EADC_INTSRC0_AD1SPIE7_Msk (0x1ul << EADC_INTSRC0_AD1SPIE7_Pos) /*!< EADC INTSRC0: AD1SPIE7 Mask */
-
-#define EADC_INTSRC1_AD0SPIE0_Pos (0) /*!< EADC INTSRC1: AD0SPIE0 Position */
-#define EADC_INTSRC1_AD0SPIE0_Msk (0x1ul << EADC_INTSRC1_AD0SPIE0_Pos) /*!< EADC INTSRC1: AD0SPIE0 Mask */
-
-#define EADC_INTSRC1_AD0SPIE1_Pos (1) /*!< EADC INTSRC1: AD0SPIE1 Position */
-#define EADC_INTSRC1_AD0SPIE1_Msk (0x1ul << EADC_INTSRC1_AD0SPIE1_Pos) /*!< EADC INTSRC1: AD0SPIE1 Mask */
-
-#define EADC_INTSRC1_AD0SPIE2_Pos (2) /*!< EADC INTSRC1: AD0SPIE2 Position */
-#define EADC_INTSRC1_AD0SPIE2_Msk (0x1ul << EADC_INTSRC1_AD0SPIE2_Pos) /*!< EADC INTSRC1: AD0SPIE2 Mask */
-
-#define EADC_INTSRC1_AD0SPIE3_Pos (3) /*!< EADC INTSRC1: AD0SPIE3 Position */
-#define EADC_INTSRC1_AD0SPIE3_Msk (0x1ul << EADC_INTSRC1_AD0SPIE3_Pos) /*!< EADC INTSRC1: AD0SPIE3 Mask */
-
-#define EADC_INTSRC1_AD0SPIE4_Pos (4) /*!< EADC INTSRC1: AD0SPIE4 Position */
-#define EADC_INTSRC1_AD0SPIE4_Msk (0x1ul << EADC_INTSRC1_AD0SPIE4_Pos) /*!< EADC INTSRC1: AD0SPIE4 Mask */
-
-#define EADC_INTSRC1_AD0SPIE5_Pos (5) /*!< EADC INTSRC1: AD0SPIE5 Position */
-#define EADC_INTSRC1_AD0SPIE5_Msk (0x1ul << EADC_INTSRC1_AD0SPIE5_Pos) /*!< EADC INTSRC1: AD0SPIE5 Mask */
-
-#define EADC_INTSRC1_AD0SPIE6_Pos (6) /*!< EADC INTSRC1: AD0SPIE6 Position */
-#define EADC_INTSRC1_AD0SPIE6_Msk (0x1ul << EADC_INTSRC1_AD0SPIE6_Pos) /*!< EADC INTSRC1: AD0SPIE6 Mask */
-
-#define EADC_INTSRC1_AD0SPIE7_Pos (7) /*!< EADC INTSRC1: AD0SPIE7 Position */
-#define EADC_INTSRC1_AD0SPIE7_Msk (0x1ul << EADC_INTSRC1_AD0SPIE7_Pos) /*!< EADC INTSRC1: AD0SPIE7 Mask */
-
-#define EADC_INTSRC1_AD1SPIE0_Pos (8) /*!< EADC INTSRC1: AD1SPIE0 Position */
-#define EADC_INTSRC1_AD1SPIE0_Msk (0x1ul << EADC_INTSRC1_AD1SPIE0_Pos) /*!< EADC INTSRC1: AD1SPIE0 Mask */
-
-#define EADC_INTSRC1_AD1SPIE1_Pos (9) /*!< EADC INTSRC1: AD1SPIE1 Position */
-#define EADC_INTSRC1_AD1SPIE1_Msk (0x1ul << EADC_INTSRC1_AD1SPIE1_Pos) /*!< EADC INTSRC1: AD1SPIE1 Mask */
-
-#define EADC_INTSRC1_AD1SPIE2_Pos (10) /*!< EADC INTSRC1: AD1SPIE2 Position */
-#define EADC_INTSRC1_AD1SPIE2_Msk (0x1ul << EADC_INTSRC1_AD1SPIE2_Pos) /*!< EADC INTSRC1: AD1SPIE2 Mask */
-
-#define EADC_INTSRC1_AD1SPIE3_Pos (11) /*!< EADC INTSRC1: AD1SPIE3 Position */
-#define EADC_INTSRC1_AD1SPIE3_Msk (0x1ul << EADC_INTSRC1_AD1SPIE3_Pos) /*!< EADC INTSRC1: AD1SPIE3 Mask */
-
-#define EADC_INTSRC1_AD1SPIE4_Pos (12) /*!< EADC INTSRC1: AD1SPIE4 Position */
-#define EADC_INTSRC1_AD1SPIE4_Msk (0x1ul << EADC_INTSRC1_AD1SPIE4_Pos) /*!< EADC INTSRC1: AD1SPIE4 Mask */
-
-#define EADC_INTSRC1_AD1SPIE5_Pos (13) /*!< EADC INTSRC1: AD1SPIE5 Position */
-#define EADC_INTSRC1_AD1SPIE5_Msk (0x1ul << EADC_INTSRC1_AD1SPIE5_Pos) /*!< EADC INTSRC1: AD1SPIE5 Mask */
-
-#define EADC_INTSRC1_AD1SPIE6_Pos (14) /*!< EADC INTSRC1: AD1SPIE6 Position */
-#define EADC_INTSRC1_AD1SPIE6_Msk (0x1ul << EADC_INTSRC1_AD1SPIE6_Pos) /*!< EADC INTSRC1: AD1SPIE6 Mask */
-
-#define EADC_INTSRC1_AD1SPIE7_Pos (15) /*!< EADC INTSRC1: AD1SPIE7 Position */
-#define EADC_INTSRC1_AD1SPIE7_Msk (0x1ul << EADC_INTSRC1_AD1SPIE7_Pos) /*!< EADC INTSRC1: AD1SPIE7 Mask */
-
-#define EADC_INTSRC2_AD0SPIE0_Pos (0) /*!< EADC INTSRC2: AD0SPIE0 Position */
-#define EADC_INTSRC2_AD0SPIE0_Msk (0x1ul << EADC_INTSRC2_AD0SPIE0_Pos) /*!< EADC INTSRC2: AD0SPIE0 Mask */
-
-#define EADC_INTSRC2_AD0SPIE1_Pos (1) /*!< EADC INTSRC2: AD0SPIE1 Position */
-#define EADC_INTSRC2_AD0SPIE1_Msk (0x1ul << EADC_INTSRC2_AD0SPIE1_Pos) /*!< EADC INTSRC2: AD0SPIE1 Mask */
-
-#define EADC_INTSRC2_AD0SPIE2_Pos (2) /*!< EADC INTSRC2: AD0SPIE2 Position */
-#define EADC_INTSRC2_AD0SPIE2_Msk (0x1ul << EADC_INTSRC2_AD0SPIE2_Pos) /*!< EADC INTSRC2: AD0SPIE2 Mask */
-
-#define EADC_INTSRC2_AD0SPIE3_Pos (3) /*!< EADC INTSRC2: AD0SPIE3 Position */
-#define EADC_INTSRC2_AD0SPIE3_Msk (0x1ul << EADC_INTSRC2_AD0SPIE3_Pos) /*!< EADC INTSRC2: AD0SPIE3 Mask */
-
-#define EADC_INTSRC2_AD0SPIE4_Pos (4) /*!< EADC INTSRC2: AD0SPIE4 Position */
-#define EADC_INTSRC2_AD0SPIE4_Msk (0x1ul << EADC_INTSRC2_AD0SPIE4_Pos) /*!< EADC INTSRC2: AD0SPIE4 Mask */
-
-#define EADC_INTSRC2_AD0SPIE5_Pos (5) /*!< EADC INTSRC2: AD0SPIE5 Position */
-#define EADC_INTSRC2_AD0SPIE5_Msk (0x1ul << EADC_INTSRC2_AD0SPIE5_Pos) /*!< EADC INTSRC2: AD0SPIE5 Mask */
-
-#define EADC_INTSRC2_AD0SPIE6_Pos (6) /*!< EADC INTSRC2: AD0SPIE6 Position */
-#define EADC_INTSRC2_AD0SPIE6_Msk (0x1ul << EADC_INTSRC2_AD0SPIE6_Pos) /*!< EADC INTSRC2: AD0SPIE6 Mask */
-
-#define EADC_INTSRC2_AD0SPIE7_Pos (7) /*!< EADC INTSRC2: AD0SPIE7 Position */
-#define EADC_INTSRC2_AD0SPIE7_Msk (0x1ul << EADC_INTSRC2_AD0SPIE7_Pos) /*!< EADC INTSRC2: AD0SPIE7 Mask */
-
-#define EADC_INTSRC2_AD1SPIE0_Pos (8) /*!< EADC INTSRC2: AD1SPIE0 Position */
-#define EADC_INTSRC2_AD1SPIE0_Msk (0x1ul << EADC_INTSRC2_AD1SPIE0_Pos) /*!< EADC INTSRC2: AD1SPIE0 Mask */
-
-#define EADC_INTSRC2_AD1SPIE1_Pos (9) /*!< EADC INTSRC2: AD1SPIE1 Position */
-#define EADC_INTSRC2_AD1SPIE1_Msk (0x1ul << EADC_INTSRC2_AD1SPIE1_Pos) /*!< EADC INTSRC2: AD1SPIE1 Mask */
-
-#define EADC_INTSRC2_AD1SPIE2_Pos (10) /*!< EADC INTSRC2: AD1SPIE2 Position */
-#define EADC_INTSRC2_AD1SPIE2_Msk (0x1ul << EADC_INTSRC2_AD1SPIE2_Pos) /*!< EADC INTSRC2: AD1SPIE2 Mask */
-
-#define EADC_INTSRC2_AD1SPIE3_Pos (11) /*!< EADC INTSRC2: AD1SPIE3 Position */
-#define EADC_INTSRC2_AD1SPIE3_Msk (0x1ul << EADC_INTSRC2_AD1SPIE3_Pos) /*!< EADC INTSRC2: AD1SPIE3 Mask */
-
-#define EADC_INTSRC2_AD1SPIE4_Pos (12) /*!< EADC INTSRC2: AD1SPIE4 Position */
-#define EADC_INTSRC2_AD1SPIE4_Msk (0x1ul << EADC_INTSRC2_AD1SPIE4_Pos) /*!< EADC INTSRC2: AD1SPIE4 Mask */
-
-#define EADC_INTSRC2_AD1SPIE5_Pos (13) /*!< EADC INTSRC2: AD1SPIE5 Position */
-#define EADC_INTSRC2_AD1SPIE5_Msk (0x1ul << EADC_INTSRC2_AD1SPIE5_Pos) /*!< EADC INTSRC2: AD1SPIE5 Mask */
-
-#define EADC_INTSRC2_AD1SPIE6_Pos (14) /*!< EADC INTSRC2: AD1SPIE6 Position */
-#define EADC_INTSRC2_AD1SPIE6_Msk (0x1ul << EADC_INTSRC2_AD1SPIE6_Pos) /*!< EADC INTSRC2: AD1SPIE6 Mask */
-
-#define EADC_INTSRC2_AD1SPIE7_Pos (15) /*!< EADC INTSRC2: AD1SPIE7 Position */
-#define EADC_INTSRC2_AD1SPIE7_Msk (0x1ul << EADC_INTSRC2_AD1SPIE7_Pos) /*!< EADC INTSRC2: AD1SPIE7 Mask */
-
-#define EADC_INTSRC3_AD0SPIE0_Pos (0) /*!< EADC INTSRC3: AD0SPIE0 Position */
-#define EADC_INTSRC3_AD0SPIE0_Msk (0x1ul << EADC_INTSRC3_AD0SPIE0_Pos) /*!< EADC INTSRC3: AD0SPIE0 Mask */
-
-#define EADC_INTSRC3_AD0SPIE1_Pos (1) /*!< EADC INTSRC3: AD0SPIE1 Position */
-#define EADC_INTSRC3_AD0SPIE1_Msk (0x1ul << EADC_INTSRC3_AD0SPIE1_Pos) /*!< EADC INTSRC3: AD0SPIE1 Mask */
-
-#define EADC_INTSRC3_AD0SPIE2_Pos (2) /*!< EADC INTSRC3: AD0SPIE2 Position */
-#define EADC_INTSRC3_AD0SPIE2_Msk (0x1ul << EADC_INTSRC3_AD0SPIE2_Pos) /*!< EADC INTSRC3: AD0SPIE2 Mask */
-
-#define EADC_INTSRC3_AD0SPIE3_Pos (3) /*!< EADC INTSRC3: AD0SPIE3 Position */
-#define EADC_INTSRC3_AD0SPIE3_Msk (0x1ul << EADC_INTSRC3_AD0SPIE3_Pos) /*!< EADC INTSRC3: AD0SPIE3 Mask */
-
-#define EADC_INTSRC3_AD0SPIE4_Pos (4) /*!< EADC INTSRC3: AD0SPIE4 Position */
-#define EADC_INTSRC3_AD0SPIE4_Msk (0x1ul << EADC_INTSRC3_AD0SPIE4_Pos) /*!< EADC INTSRC3: AD0SPIE4 Mask */
-
-#define EADC_INTSRC3_AD0SPIE5_Pos (5) /*!< EADC INTSRC3: AD0SPIE5 Position */
-#define EADC_INTSRC3_AD0SPIE5_Msk (0x1ul << EADC_INTSRC3_AD0SPIE5_Pos) /*!< EADC INTSRC3: AD0SPIE5 Mask */
-
-#define EADC_INTSRC3_AD0SPIE6_Pos (6) /*!< EADC INTSRC3: AD0SPIE6 Position */
-#define EADC_INTSRC3_AD0SPIE6_Msk (0x1ul << EADC_INTSRC3_AD0SPIE6_Pos) /*!< EADC INTSRC3: AD0SPIE6 Mask */
-
-#define EADC_INTSRC3_AD0SPIE7_Pos (7) /*!< EADC INTSRC3: AD0SPIE7 Position */
-#define EADC_INTSRC3_AD0SPIE7_Msk (0x1ul << EADC_INTSRC3_AD0SPIE7_Pos) /*!< EADC INTSRC3: AD0SPIE7 Mask */
-
-#define EADC_INTSRC3_AD1SPIE0_Pos (8) /*!< EADC INTSRC3: AD1SPIE0 Position */
-#define EADC_INTSRC3_AD1SPIE0_Msk (0x1ul << EADC_INTSRC3_AD1SPIE0_Pos) /*!< EADC INTSRC3: AD1SPIE0 Mask */
-
-#define EADC_INTSRC3_AD1SPIE1_Pos (9) /*!< EADC INTSRC3: AD1SPIE1 Position */
-#define EADC_INTSRC3_AD1SPIE1_Msk (0x1ul << EADC_INTSRC3_AD1SPIE1_Pos) /*!< EADC INTSRC3: AD1SPIE1 Mask */
-
-#define EADC_INTSRC3_AD1SPIE2_Pos (10) /*!< EADC INTSRC3: AD1SPIE2 Position */
-#define EADC_INTSRC3_AD1SPIE2_Msk (0x1ul << EADC_INTSRC3_AD1SPIE2_Pos) /*!< EADC INTSRC3: AD1SPIE2 Mask */
-
-#define EADC_INTSRC3_AD1SPIE3_Pos (11) /*!< EADC INTSRC3: AD1SPIE3 Position */
-#define EADC_INTSRC3_AD1SPIE3_Msk (0x1ul << EADC_INTSRC3_AD1SPIE3_Pos) /*!< EADC INTSRC3: AD1SPIE3 Mask */
-
-#define EADC_INTSRC3_AD1SPIE4_Pos (12) /*!< EADC INTSRC3: AD1SPIE4 Position */
-#define EADC_INTSRC3_AD1SPIE4_Msk (0x1ul << EADC_INTSRC3_AD1SPIE4_Pos) /*!< EADC INTSRC3: AD1SPIE4 Mask */
-
-#define EADC_INTSRC3_AD1SPIE5_Pos (13) /*!< EADC INTSRC3: AD1SPIE5 Position */
-#define EADC_INTSRC3_AD1SPIE5_Msk (0x1ul << EADC_INTSRC3_AD1SPIE5_Pos) /*!< EADC INTSRC3: AD1SPIE5 Mask */
-
-#define EADC_INTSRC3_AD1SPIE6_Pos (14) /*!< EADC INTSRC3: AD1SPIE6 Position */
-#define EADC_INTSRC3_AD1SPIE6_Msk (0x1ul << EADC_INTSRC3_AD1SPIE6_Pos) /*!< EADC INTSRC3: AD1SPIE6 Mask */
-
-#define EADC_INTSRC3_AD1SPIE7_Pos (15) /*!< EADC INTSRC3: AD1SPIE7 Position */
-#define EADC_INTSRC3_AD1SPIE7_Msk (0x1ul << EADC_INTSRC3_AD1SPIE7_Pos) /*!< EADC INTSRC3: AD1SPIE7 Mask */
-
-#define EADC_AD0TRGEN0_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN0: EPWM00REN Position */
-#define EADC_AD0TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00REN_Pos) /*!< EADC AD0TRGEN0: EPWM00REN Mask */
-
-#define EADC_AD0TRGEN0_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN0: EPWM00FEN Position */
-#define EADC_AD0TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00FEN_Pos) /*!< EADC AD0TRGEN0: EPWM00FEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN0: EPWM00PEN Position */
-#define EADC_AD0TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00PEN_Pos) /*!< EADC AD0TRGEN0: EPWM00PEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN0: EPWM00CEN Position */
-#define EADC_AD0TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00CEN_Pos) /*!< EADC AD0TRGEN0: EPWM00CEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN0: EPWM02REN Position */
-#define EADC_AD0TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02REN_Pos) /*!< EADC AD0TRGEN0: EPWM02REN Mask */
-
-#define EADC_AD0TRGEN0_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN0: EPWM02FEN Position */
-#define EADC_AD0TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02FEN_Pos) /*!< EADC AD0TRGEN0: EPWM02FEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN0: EPWM02PEN Position */
-#define EADC_AD0TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02PEN_Pos) /*!< EADC AD0TRGEN0: EPWM02PEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN0: EPWM02CEN Position */
-#define EADC_AD0TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02CEN_Pos) /*!< EADC AD0TRGEN0: EPWM02CEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN0: EPWM04REN Position */
-#define EADC_AD0TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04REN_Pos) /*!< EADC AD0TRGEN0: EPWM04REN Mask */
-
-#define EADC_AD0TRGEN0_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN0: EPWM04FEN Position */
-#define EADC_AD0TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04FEN_Pos) /*!< EADC AD0TRGEN0: EPWM04FEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN0: EPWM04PEN Position */
-#define EADC_AD0TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04PEN_Pos) /*!< EADC AD0TRGEN0: EPWM04PEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN0: EPWM04CEN Position */
-#define EADC_AD0TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04CEN_Pos) /*!< EADC AD0TRGEN0: EPWM04CEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN0: EPWM10REN Position */
-#define EADC_AD0TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10REN_Pos) /*!< EADC AD0TRGEN0: EPWM10REN Mask */
-
-#define EADC_AD0TRGEN0_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN0: EPWM10FEN Position */
-#define EADC_AD0TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10FEN_Pos) /*!< EADC AD0TRGEN0: EPWM10FEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN0: EPWM10PEN Position */
-#define EADC_AD0TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10PEN_Pos) /*!< EADC AD0TRGEN0: EPWM10PEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN0: EPWM10CEN Position */
-#define EADC_AD0TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10CEN_Pos) /*!< EADC AD0TRGEN0: EPWM10CEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN0: EPWM12REN Position */
-#define EADC_AD0TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12REN_Pos) /*!< EADC AD0TRGEN0: EPWM12REN Mask */
-
-#define EADC_AD0TRGEN0_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN0: EPWM120FEN Position */
-#define EADC_AD0TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM120FEN_Pos) /*!< EADC AD0TRGEN0: EPWM120FEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN0: EPWM12PEN Position */
-#define EADC_AD0TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12PEN_Pos) /*!< EADC AD0TRGEN0: EPWM12PEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN0: EPWM12CEN Position */
-#define EADC_AD0TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12CEN_Pos) /*!< EADC AD0TRGEN0: EPWM12CEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN0: EPWM14REN Position */
-#define EADC_AD0TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14REN_Pos) /*!< EADC AD0TRGEN0: EPWM14REN Mask */
-
-#define EADC_AD0TRGEN0_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN0: EPWM14FEN Position */
-#define EADC_AD0TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14FEN_Pos) /*!< EADC AD0TRGEN0: EPWM14FEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN0: EPWM14PEN Position */
-#define EADC_AD0TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14PEN_Pos) /*!< EADC AD0TRGEN0: EPWM14PEN Mask */
-
-#define EADC_AD0TRGEN0_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN0: EPWM14CEN Position */
-#define EADC_AD0TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14CEN_Pos) /*!< EADC AD0TRGEN0: EPWM14CEN Mask */
-
-#define EADC_AD0TRGEN0_PWM00REN_Pos (24) /*!< EADC AD0TRGEN0: PWM00REN Position */
-#define EADC_AD0TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00REN_Pos) /*!< EADC AD0TRGEN0: PWM00REN Mask */
-
-#define EADC_AD0TRGEN0_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN0: PWM00FEN Position */
-#define EADC_AD0TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00FEN_Pos) /*!< EADC AD0TRGEN0: PWM00FEN Mask */
-
-#define EADC_AD0TRGEN0_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN0: PWM00PEN Position */
-#define EADC_AD0TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00PEN_Pos) /*!< EADC AD0TRGEN0: PWM00PEN Mask */
-
-#define EADC_AD0TRGEN0_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN0: PWM00CEN Position */
-#define EADC_AD0TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00CEN_Pos) /*!< EADC AD0TRGEN0: PWM00CEN Mask */
-
-#define EADC_AD0TRGEN0_PWM01REN_Pos (28) /*!< EADC AD0TRGEN0: PWM01REN Position */
-#define EADC_AD0TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01REN_Pos) /*!< EADC AD0TRGEN0: PWM01REN Mask */
-
-#define EADC_AD0TRGEN0_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN0: PWM01FEN Position */
-#define EADC_AD0TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01FEN_Pos) /*!< EADC AD0TRGEN0: PWM01FEN Mask */
-
-#define EADC_AD0TRGEN0_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN0: PWM01PEN Position */
-#define EADC_AD0TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01PEN_Pos) /*!< EADC AD0TRGEN0: PWM01PEN Mask */
-
-#define EADC_AD0TRGEN0_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN0: PWM01CEN Position */
-#define EADC_AD0TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01CEN_Pos) /*!< EADC AD0TRGEN0: PWM01CEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN1: EPWM00REN Position */
-#define EADC_AD0TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00REN_Pos) /*!< EADC AD0TRGEN1: EPWM00REN Mask */
-
-#define EADC_AD0TRGEN1_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN1: EPWM00FEN Position */
-#define EADC_AD0TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00FEN_Pos) /*!< EADC AD0TRGEN1: EPWM00FEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN1: EPWM00PEN Position */
-#define EADC_AD0TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00PEN_Pos) /*!< EADC AD0TRGEN1: EPWM00PEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN1: EPWM00CEN Position */
-#define EADC_AD0TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00CEN_Pos) /*!< EADC AD0TRGEN1: EPWM00CEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN1: EPWM02REN Position */
-#define EADC_AD0TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02REN_Pos) /*!< EADC AD0TRGEN1: EPWM02REN Mask */
-
-#define EADC_AD0TRGEN1_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN1: EPWM02FEN Position */
-#define EADC_AD0TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02FEN_Pos) /*!< EADC AD0TRGEN1: EPWM02FEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN1: EPWM02PEN Position */
-#define EADC_AD0TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02PEN_Pos) /*!< EADC AD0TRGEN1: EPWM02PEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN1: EPWM02CEN Position */
-#define EADC_AD0TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02CEN_Pos) /*!< EADC AD0TRGEN1: EPWM02CEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN1: EPWM04REN Position */
-#define EADC_AD0TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04REN_Pos) /*!< EADC AD0TRGEN1: EPWM04REN Mask */
-
-#define EADC_AD0TRGEN1_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN1: EPWM04FEN Position */
-#define EADC_AD0TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04FEN_Pos) /*!< EADC AD0TRGEN1: EPWM04FEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN1: EPWM04PEN Position */
-#define EADC_AD0TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04PEN_Pos) /*!< EADC AD0TRGEN1: EPWM04PEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN1: EPWM04CEN Position */
-#define EADC_AD0TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04CEN_Pos) /*!< EADC AD0TRGEN1: EPWM04CEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN1: EPWM10REN Position */
-#define EADC_AD0TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10REN_Pos) /*!< EADC AD0TRGEN1: EPWM10REN Mask */
-
-#define EADC_AD0TRGEN1_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN1: EPWM10FEN Position */
-#define EADC_AD0TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10FEN_Pos) /*!< EADC AD0TRGEN1: EPWM10FEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN1: EPWM10PEN Position */
-#define EADC_AD0TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10PEN_Pos) /*!< EADC AD0TRGEN1: EPWM10PEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN1: EPWM10CEN Position */
-#define EADC_AD0TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10CEN_Pos) /*!< EADC AD0TRGEN1: EPWM10CEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN1: EPWM12REN Position */
-#define EADC_AD0TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12REN_Pos) /*!< EADC AD0TRGEN1: EPWM12REN Mask */
-
-#define EADC_AD0TRGEN1_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN1: EPWM120FEN Position */
-#define EADC_AD0TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM120FEN_Pos) /*!< EADC AD0TRGEN1: EPWM120FEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN1: EPWM12PEN Position */
-#define EADC_AD0TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12PEN_Pos) /*!< EADC AD0TRGEN1: EPWM12PEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN1: EPWM12CEN Position */
-#define EADC_AD0TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12CEN_Pos) /*!< EADC AD0TRGEN1: EPWM12CEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN1: EPWM14REN Position */
-#define EADC_AD0TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14REN_Pos) /*!< EADC AD0TRGEN1: EPWM14REN Mask */
-
-#define EADC_AD0TRGEN1_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN1: EPWM14FEN Position */
-#define EADC_AD0TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14FEN_Pos) /*!< EADC AD0TRGEN1: EPWM14FEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN1: EPWM14PEN Position */
-#define EADC_AD0TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14PEN_Pos) /*!< EADC AD0TRGEN1: EPWM14PEN Mask */
-
-#define EADC_AD0TRGEN1_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN1: EPWM14CEN Position */
-#define EADC_AD0TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14CEN_Pos) /*!< EADC AD0TRGEN1: EPWM14CEN Mask */
-
-#define EADC_AD0TRGEN1_PWM00REN_Pos (24) /*!< EADC AD0TRGEN1: PWM00REN Position */
-#define EADC_AD0TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00REN_Pos) /*!< EADC AD0TRGEN1: PWM00REN Mask */
-
-#define EADC_AD0TRGEN1_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN1: PWM00FEN Position */
-#define EADC_AD0TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00FEN_Pos) /*!< EADC AD0TRGEN1: PWM00FEN Mask */
-
-#define EADC_AD0TRGEN1_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN1: PWM00PEN Position */
-#define EADC_AD0TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00PEN_Pos) /*!< EADC AD0TRGEN1: PWM00PEN Mask */
-
-#define EADC_AD0TRGEN1_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN1: PWM00CEN Position */
-#define EADC_AD0TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00CEN_Pos) /*!< EADC AD0TRGEN1: PWM00CEN Mask */
-
-#define EADC_AD0TRGEN1_PWM01REN_Pos (28) /*!< EADC AD0TRGEN1: PWM01REN Position */
-#define EADC_AD0TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01REN_Pos) /*!< EADC AD0TRGEN1: PWM01REN Mask */
-
-#define EADC_AD0TRGEN1_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN1: PWM01FEN Position */
-#define EADC_AD0TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01FEN_Pos) /*!< EADC AD0TRGEN1: PWM01FEN Mask */
-
-#define EADC_AD0TRGEN1_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN1: PWM01PEN Position */
-#define EADC_AD0TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01PEN_Pos) /*!< EADC AD0TRGEN1: PWM01PEN Mask */
-
-#define EADC_AD0TRGEN1_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN1: PWM01CEN Position */
-#define EADC_AD0TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01CEN_Pos) /*!< EADC AD0TRGEN1: PWM01CEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN2: EPWM00REN Position */
-#define EADC_AD0TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00REN_Pos) /*!< EADC AD0TRGEN2: EPWM00REN Mask */
-
-#define EADC_AD0TRGEN2_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN2: EPWM00FEN Position */
-#define EADC_AD0TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00FEN_Pos) /*!< EADC AD0TRGEN2: EPWM00FEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN2: EPWM00PEN Position */
-#define EADC_AD0TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00PEN_Pos) /*!< EADC AD0TRGEN2: EPWM00PEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN2: EPWM00CEN Position */
-#define EADC_AD0TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00CEN_Pos) /*!< EADC AD0TRGEN2: EPWM00CEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN2: EPWM02REN Position */
-#define EADC_AD0TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02REN_Pos) /*!< EADC AD0TRGEN2: EPWM02REN Mask */
-
-#define EADC_AD0TRGEN2_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN2: EPWM02FEN Position */
-#define EADC_AD0TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02FEN_Pos) /*!< EADC AD0TRGEN2: EPWM02FEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN2: EPWM02PEN Position */
-#define EADC_AD0TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02PEN_Pos) /*!< EADC AD0TRGEN2: EPWM02PEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN2: EPWM02CEN Position */
-#define EADC_AD0TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02CEN_Pos) /*!< EADC AD0TRGEN2: EPWM02CEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN2: EPWM04REN Position */
-#define EADC_AD0TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04REN_Pos) /*!< EADC AD0TRGEN2: EPWM04REN Mask */
-
-#define EADC_AD0TRGEN2_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN2: EPWM04FEN Position */
-#define EADC_AD0TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04FEN_Pos) /*!< EADC AD0TRGEN2: EPWM04FEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN2: EPWM04PEN Position */
-#define EADC_AD0TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04PEN_Pos) /*!< EADC AD0TRGEN2: EPWM04PEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN2: EPWM04CEN Position */
-#define EADC_AD0TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04CEN_Pos) /*!< EADC AD0TRGEN2: EPWM04CEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN2: EPWM10REN Position */
-#define EADC_AD0TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10REN_Pos) /*!< EADC AD0TRGEN2: EPWM10REN Mask */
-
-#define EADC_AD0TRGEN2_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN2: EPWM10FEN Position */
-#define EADC_AD0TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10FEN_Pos) /*!< EADC AD0TRGEN2: EPWM10FEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN2: EPWM10PEN Position */
-#define EADC_AD0TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10PEN_Pos) /*!< EADC AD0TRGEN2: EPWM10PEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN2: EPWM10CEN Position */
-#define EADC_AD0TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10CEN_Pos) /*!< EADC AD0TRGEN2: EPWM10CEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN2: EPWM12REN Position */
-#define EADC_AD0TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12REN_Pos) /*!< EADC AD0TRGEN2: EPWM12REN Mask */
-
-#define EADC_AD0TRGEN2_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN2: EPWM120FEN Position */
-#define EADC_AD0TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM120FEN_Pos) /*!< EADC AD0TRGEN2: EPWM120FEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN2: EPWM12PEN Position */
-#define EADC_AD0TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12PEN_Pos) /*!< EADC AD0TRGEN2: EPWM12PEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN2: EPWM12CEN Position */
-#define EADC_AD0TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12CEN_Pos) /*!< EADC AD0TRGEN2: EPWM12CEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN2: EPWM14REN Position */
-#define EADC_AD0TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14REN_Pos) /*!< EADC AD0TRGEN2: EPWM14REN Mask */
-
-#define EADC_AD0TRGEN2_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN2: EPWM14FEN Position */
-#define EADC_AD0TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14FEN_Pos) /*!< EADC AD0TRGEN2: EPWM14FEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN2: EPWM14PEN Position */
-#define EADC_AD0TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14PEN_Pos) /*!< EADC AD0TRGEN2: EPWM14PEN Mask */
-
-#define EADC_AD0TRGEN2_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN2: EPWM14CEN Position */
-#define EADC_AD0TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14CEN_Pos) /*!< EADC AD0TRGEN2: EPWM14CEN Mask */
-
-#define EADC_AD0TRGEN2_PWM00REN_Pos (24) /*!< EADC AD0TRGEN2: PWM00REN Position */
-#define EADC_AD0TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00REN_Pos) /*!< EADC AD0TRGEN2: PWM00REN Mask */
-
-#define EADC_AD0TRGEN2_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN2: PWM00FEN Position */
-#define EADC_AD0TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00FEN_Pos) /*!< EADC AD0TRGEN2: PWM00FEN Mask */
-
-#define EADC_AD0TRGEN2_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN2: PWM00PEN Position */
-#define EADC_AD0TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00PEN_Pos) /*!< EADC AD0TRGEN2: PWM00PEN Mask */
-
-#define EADC_AD0TRGEN2_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN2: PWM00CEN Position */
-#define EADC_AD0TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00CEN_Pos) /*!< EADC AD0TRGEN2: PWM00CEN Mask */
-
-#define EADC_AD0TRGEN2_PWM01REN_Pos (28) /*!< EADC AD0TRGEN2: PWM01REN Position */
-#define EADC_AD0TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01REN_Pos) /*!< EADC AD0TRGEN2: PWM01REN Mask */
-
-#define EADC_AD0TRGEN2_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN2: PWM01FEN Position */
-#define EADC_AD0TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01FEN_Pos) /*!< EADC AD0TRGEN2: PWM01FEN Mask */
-
-#define EADC_AD0TRGEN2_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN2: PWM01PEN Position */
-#define EADC_AD0TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01PEN_Pos) /*!< EADC AD0TRGEN2: PWM01PEN Mask */
-
-#define EADC_AD0TRGEN2_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN2: PWM01CEN Position */
-#define EADC_AD0TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01CEN_Pos) /*!< EADC AD0TRGEN2: PWM01CEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN3: EPWM00REN Position */
-#define EADC_AD0TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00REN_Pos) /*!< EADC AD0TRGEN3: EPWM00REN Mask */
-
-#define EADC_AD0TRGEN3_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN3: EPWM00FEN Position */
-#define EADC_AD0TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00FEN_Pos) /*!< EADC AD0TRGEN3: EPWM00FEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN3: EPWM00PEN Position */
-#define EADC_AD0TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00PEN_Pos) /*!< EADC AD0TRGEN3: EPWM00PEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN3: EPWM00CEN Position */
-#define EADC_AD0TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00CEN_Pos) /*!< EADC AD0TRGEN3: EPWM00CEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN3: EPWM02REN Position */
-#define EADC_AD0TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02REN_Pos) /*!< EADC AD0TRGEN3: EPWM02REN Mask */
-
-#define EADC_AD0TRGEN3_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN3: EPWM02FEN Position */
-#define EADC_AD0TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02FEN_Pos) /*!< EADC AD0TRGEN3: EPWM02FEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN3: EPWM02PEN Position */
-#define EADC_AD0TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02PEN_Pos) /*!< EADC AD0TRGEN3: EPWM02PEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN3: EPWM02CEN Position */
-#define EADC_AD0TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02CEN_Pos) /*!< EADC AD0TRGEN3: EPWM02CEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN3: EPWM04REN Position */
-#define EADC_AD0TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04REN_Pos) /*!< EADC AD0TRGEN3: EPWM04REN Mask */
-
-#define EADC_AD0TRGEN3_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN3: EPWM04FEN Position */
-#define EADC_AD0TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04FEN_Pos) /*!< EADC AD0TRGEN3: EPWM04FEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN3: EPWM04PEN Position */
-#define EADC_AD0TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04PEN_Pos) /*!< EADC AD0TRGEN3: EPWM04PEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN3: EPWM04CEN Position */
-#define EADC_AD0TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04CEN_Pos) /*!< EADC AD0TRGEN3: EPWM04CEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN3: EPWM10REN Position */
-#define EADC_AD0TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10REN_Pos) /*!< EADC AD0TRGEN3: EPWM10REN Mask */
-
-#define EADC_AD0TRGEN3_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN3: EPWM10FEN Position */
-#define EADC_AD0TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10FEN_Pos) /*!< EADC AD0TRGEN3: EPWM10FEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN3: EPWM10PEN Position */
-#define EADC_AD0TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10PEN_Pos) /*!< EADC AD0TRGEN3: EPWM10PEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN3: EPWM10CEN Position */
-#define EADC_AD0TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10CEN_Pos) /*!< EADC AD0TRGEN3: EPWM10CEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN3: EPWM12REN Position */
-#define EADC_AD0TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12REN_Pos) /*!< EADC AD0TRGEN3: EPWM12REN Mask */
-
-#define EADC_AD0TRGEN3_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN3: EPWM120FEN Position */
-#define EADC_AD0TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM120FEN_Pos) /*!< EADC AD0TRGEN3: EPWM120FEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN3: EPWM12PEN Position */
-#define EADC_AD0TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12PEN_Pos) /*!< EADC AD0TRGEN3: EPWM12PEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN3: EPWM12CEN Position */
-#define EADC_AD0TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12CEN_Pos) /*!< EADC AD0TRGEN3: EPWM12CEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN3: EPWM14REN Position */
-#define EADC_AD0TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14REN_Pos) /*!< EADC AD0TRGEN3: EPWM14REN Mask */
-
-#define EADC_AD0TRGEN3_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN3: EPWM14FEN Position */
-#define EADC_AD0TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14FEN_Pos) /*!< EADC AD0TRGEN3: EPWM14FEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN3: EPWM14PEN Position */
-#define EADC_AD0TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14PEN_Pos) /*!< EADC AD0TRGEN3: EPWM14PEN Mask */
-
-#define EADC_AD0TRGEN3_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN3: EPWM14CEN Position */
-#define EADC_AD0TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14CEN_Pos) /*!< EADC AD0TRGEN3: EPWM14CEN Mask */
-
-#define EADC_AD0TRGEN3_PWM00REN_Pos (24) /*!< EADC AD0TRGEN3: PWM00REN Position */
-#define EADC_AD0TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00REN_Pos) /*!< EADC AD0TRGEN3: PWM00REN Mask */
-
-#define EADC_AD0TRGEN3_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN3: PWM00FEN Position */
-#define EADC_AD0TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00FEN_Pos) /*!< EADC AD0TRGEN3: PWM00FEN Mask */
-
-#define EADC_AD0TRGEN3_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN3: PWM00PEN Position */
-#define EADC_AD0TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00PEN_Pos) /*!< EADC AD0TRGEN3: PWM00PEN Mask */
-
-#define EADC_AD0TRGEN3_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN3: PWM00CEN Position */
-#define EADC_AD0TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00CEN_Pos) /*!< EADC AD0TRGEN3: PWM00CEN Mask */
-
-#define EADC_AD0TRGEN3_PWM01REN_Pos (28) /*!< EADC AD0TRGEN3: PWM01REN Position */
-#define EADC_AD0TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01REN_Pos) /*!< EADC AD0TRGEN3: PWM01REN Mask */
-
-#define EADC_AD0TRGEN3_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN3: PWM01FEN Position */
-#define EADC_AD0TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01FEN_Pos) /*!< EADC AD0TRGEN3: PWM01FEN Mask */
-
-#define EADC_AD0TRGEN3_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN3: PWM01PEN Position */
-#define EADC_AD0TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01PEN_Pos) /*!< EADC AD0TRGEN3: PWM01PEN Mask */
-
-#define EADC_AD0TRGEN3_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN3: PWM01CEN Position */
-#define EADC_AD0TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01CEN_Pos) /*!< EADC AD0TRGEN3: PWM01CEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN0: EPWM00REN Position */
-#define EADC_AD1TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00REN_Pos) /*!< EADC AD1TRGEN0: EPWM00REN Mask */
-
-#define EADC_AD1TRGEN0_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN0: EPWM00FEN Position */
-#define EADC_AD1TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00FEN_Pos) /*!< EADC AD1TRGEN0: EPWM00FEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN0: EPWM00PEN Position */
-#define EADC_AD1TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00PEN_Pos) /*!< EADC AD1TRGEN0: EPWM00PEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN0: EPWM00CEN Position */
-#define EADC_AD1TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00CEN_Pos) /*!< EADC AD1TRGEN0: EPWM00CEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN0: EPWM02REN Position */
-#define EADC_AD1TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02REN_Pos) /*!< EADC AD1TRGEN0: EPWM02REN Mask */
-
-#define EADC_AD1TRGEN0_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN0: EPWM02FEN Position */
-#define EADC_AD1TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02FEN_Pos) /*!< EADC AD1TRGEN0: EPWM02FEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN0: EPWM02PEN Position */
-#define EADC_AD1TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02PEN_Pos) /*!< EADC AD1TRGEN0: EPWM02PEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN0: EPWM02CEN Position */
-#define EADC_AD1TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02CEN_Pos) /*!< EADC AD1TRGEN0: EPWM02CEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN0: EPWM04REN Position */
-#define EADC_AD1TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04REN_Pos) /*!< EADC AD1TRGEN0: EPWM04REN Mask */
-
-#define EADC_AD1TRGEN0_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN0: EPWM04FEN Position */
-#define EADC_AD1TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04FEN_Pos) /*!< EADC AD1TRGEN0: EPWM04FEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN0: EPWM04PEN Position */
-#define EADC_AD1TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04PEN_Pos) /*!< EADC AD1TRGEN0: EPWM04PEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN0: EPWM04CEN Position */
-#define EADC_AD1TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04CEN_Pos) /*!< EADC AD1TRGEN0: EPWM04CEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN0: EPWM10REN Position */
-#define EADC_AD1TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10REN_Pos) /*!< EADC AD1TRGEN0: EPWM10REN Mask */
-
-#define EADC_AD1TRGEN0_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN0: EPWM10FEN Position */
-#define EADC_AD1TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10FEN_Pos) /*!< EADC AD1TRGEN0: EPWM10FEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN0: EPWM10PEN Position */
-#define EADC_AD1TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10PEN_Pos) /*!< EADC AD1TRGEN0: EPWM10PEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN0: EPWM10CEN Position */
-#define EADC_AD1TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10CEN_Pos) /*!< EADC AD1TRGEN0: EPWM10CEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN0: EPWM12REN Position */
-#define EADC_AD1TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12REN_Pos) /*!< EADC AD1TRGEN0: EPWM12REN Mask */
-
-#define EADC_AD1TRGEN0_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN0: EPWM120FEN Position */
-#define EADC_AD1TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM120FEN_Pos) /*!< EADC AD1TRGEN0: EPWM120FEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN0: EPWM12PEN Position */
-#define EADC_AD1TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12PEN_Pos) /*!< EADC AD1TRGEN0: EPWM12PEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN0: EPWM12CEN Position */
-#define EADC_AD1TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12CEN_Pos) /*!< EADC AD1TRGEN0: EPWM12CEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN0: EPWM14REN Position */
-#define EADC_AD1TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14REN_Pos) /*!< EADC AD1TRGEN0: EPWM14REN Mask */
-
-#define EADC_AD1TRGEN0_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN0: EPWM14FEN Position */
-#define EADC_AD1TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14FEN_Pos) /*!< EADC AD1TRGEN0: EPWM14FEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN0: EPWM14PEN Position */
-#define EADC_AD1TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14PEN_Pos) /*!< EADC AD1TRGEN0: EPWM14PEN Mask */
-
-#define EADC_AD1TRGEN0_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN0: EPWM14CEN Position */
-#define EADC_AD1TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14CEN_Pos) /*!< EADC AD1TRGEN0: EPWM14CEN Mask */
-
-#define EADC_AD1TRGEN0_PWM00REN_Pos (24) /*!< EADC AD1TRGEN0: PWM00REN Position */
-#define EADC_AD1TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00REN_Pos) /*!< EADC AD1TRGEN0: PWM00REN Mask */
-
-#define EADC_AD1TRGEN0_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN0: PWM00FEN Position */
-#define EADC_AD1TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00FEN_Pos) /*!< EADC AD1TRGEN0: PWM00FEN Mask */
-
-#define EADC_AD1TRGEN0_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN0: PWM00PEN Position */
-#define EADC_AD1TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00PEN_Pos) /*!< EADC AD1TRGEN0: PWM00PEN Mask */
-
-#define EADC_AD1TRGEN0_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN0: PWM00CEN Position */
-#define EADC_AD1TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00CEN_Pos) /*!< EADC AD1TRGEN0: PWM00CEN Mask */
-
-#define EADC_AD1TRGEN0_PWM01REN_Pos (28) /*!< EADC AD1TRGEN0: PWM01REN Position */
-#define EADC_AD1TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01REN_Pos) /*!< EADC AD1TRGEN0: PWM01REN Mask */
-
-#define EADC_AD1TRGEN0_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN0: PWM01FEN Position */
-#define EADC_AD1TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01FEN_Pos) /*!< EADC AD1TRGEN0: PWM01FEN Mask */
-
-#define EADC_AD1TRGEN0_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN0: PWM01PEN Position */
-#define EADC_AD1TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01PEN_Pos) /*!< EADC AD1TRGEN0: PWM01PEN Mask */
-
-#define EADC_AD1TRGEN0_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN0: PWM01CEN Position */
-#define EADC_AD1TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01CEN_Pos) /*!< EADC AD1TRGEN0: PWM01CEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN1: EPWM00REN Position */
-#define EADC_AD1TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00REN_Pos) /*!< EADC AD1TRGEN1: EPWM00REN Mask */
-
-#define EADC_AD1TRGEN1_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN1: EPWM00FEN Position */
-#define EADC_AD1TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00FEN_Pos) /*!< EADC AD1TRGEN1: EPWM00FEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN1: EPWM00PEN Position */
-#define EADC_AD1TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00PEN_Pos) /*!< EADC AD1TRGEN1: EPWM00PEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN1: EPWM00CEN Position */
-#define EADC_AD1TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00CEN_Pos) /*!< EADC AD1TRGEN1: EPWM00CEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN1: EPWM02REN Position */
-#define EADC_AD1TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02REN_Pos) /*!< EADC AD1TRGEN1: EPWM02REN Mask */
-
-#define EADC_AD1TRGEN1_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN1: EPWM02FEN Position */
-#define EADC_AD1TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02FEN_Pos) /*!< EADC AD1TRGEN1: EPWM02FEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN1: EPWM02PEN Position */
-#define EADC_AD1TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02PEN_Pos) /*!< EADC AD1TRGEN1: EPWM02PEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN1: EPWM02CEN Position */
-#define EADC_AD1TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02CEN_Pos) /*!< EADC AD1TRGEN1: EPWM02CEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN1: EPWM04REN Position */
-#define EADC_AD1TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04REN_Pos) /*!< EADC AD1TRGEN1: EPWM04REN Mask */
-
-#define EADC_AD1TRGEN1_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN1: EPWM04FEN Position */
-#define EADC_AD1TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04FEN_Pos) /*!< EADC AD1TRGEN1: EPWM04FEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN1: EPWM04PEN Position */
-#define EADC_AD1TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04PEN_Pos) /*!< EADC AD1TRGEN1: EPWM04PEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN1: EPWM04CEN Position */
-#define EADC_AD1TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04CEN_Pos) /*!< EADC AD1TRGEN1: EPWM04CEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN1: EPWM10REN Position */
-#define EADC_AD1TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10REN_Pos) /*!< EADC AD1TRGEN1: EPWM10REN Mask */
-
-#define EADC_AD1TRGEN1_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN1: EPWM10FEN Position */
-#define EADC_AD1TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10FEN_Pos) /*!< EADC AD1TRGEN1: EPWM10FEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN1: EPWM10PEN Position */
-#define EADC_AD1TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10PEN_Pos) /*!< EADC AD1TRGEN1: EPWM10PEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN1: EPWM10CEN Position */
-#define EADC_AD1TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10CEN_Pos) /*!< EADC AD1TRGEN1: EPWM10CEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN1: EPWM12REN Position */
-#define EADC_AD1TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12REN_Pos) /*!< EADC AD1TRGEN1: EPWM12REN Mask */
-
-#define EADC_AD1TRGEN1_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN1: EPWM120FEN Position */
-#define EADC_AD1TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM120FEN_Pos) /*!< EADC AD1TRGEN1: EPWM120FEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN1: EPWM12PEN Position */
-#define EADC_AD1TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12PEN_Pos) /*!< EADC AD1TRGEN1: EPWM12PEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN1: EPWM12CEN Position */
-#define EADC_AD1TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12CEN_Pos) /*!< EADC AD1TRGEN1: EPWM12CEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN1: EPWM14REN Position */
-#define EADC_AD1TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14REN_Pos) /*!< EADC AD1TRGEN1: EPWM14REN Mask */
-
-#define EADC_AD1TRGEN1_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN1: EPWM14FEN Position */
-#define EADC_AD1TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14FEN_Pos) /*!< EADC AD1TRGEN1: EPWM14FEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN1: EPWM14PEN Position */
-#define EADC_AD1TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14PEN_Pos) /*!< EADC AD1TRGEN1: EPWM14PEN Mask */
-
-#define EADC_AD1TRGEN1_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN1: EPWM14CEN Position */
-#define EADC_AD1TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14CEN_Pos) /*!< EADC AD1TRGEN1: EPWM14CEN Mask */
-
-#define EADC_AD1TRGEN1_PWM00REN_Pos (24) /*!< EADC AD1TRGEN1: PWM00REN Position */
-#define EADC_AD1TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00REN_Pos) /*!< EADC AD1TRGEN1: PWM00REN Mask */
-
-#define EADC_AD1TRGEN1_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN1: PWM00FEN Position */
-#define EADC_AD1TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00FEN_Pos) /*!< EADC AD1TRGEN1: PWM00FEN Mask */
-
-#define EADC_AD1TRGEN1_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN1: PWM00PEN Position */
-#define EADC_AD1TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00PEN_Pos) /*!< EADC AD1TRGEN1: PWM00PEN Mask */
-
-#define EADC_AD1TRGEN1_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN1: PWM00CEN Position */
-#define EADC_AD1TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00CEN_Pos) /*!< EADC AD1TRGEN1: PWM00CEN Mask */
-
-#define EADC_AD1TRGEN1_PWM01REN_Pos (28) /*!< EADC AD1TRGEN1: PWM01REN Position */
-#define EADC_AD1TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01REN_Pos) /*!< EADC AD1TRGEN1: PWM01REN Mask */
-
-#define EADC_AD1TRGEN1_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN1: PWM01FEN Position */
-#define EADC_AD1TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01FEN_Pos) /*!< EADC AD1TRGEN1: PWM01FEN Mask */
-
-#define EADC_AD1TRGEN1_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN1: PWM01PEN Position */
-#define EADC_AD1TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01PEN_Pos) /*!< EADC AD1TRGEN1: PWM01PEN Mask */
-
-#define EADC_AD1TRGEN1_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN1: PWM01CEN Position */
-#define EADC_AD1TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01CEN_Pos) /*!< EADC AD1TRGEN1: PWM01CEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN2: EPWM00REN Position */
-#define EADC_AD1TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00REN_Pos) /*!< EADC AD1TRGEN2: EPWM00REN Mask */
-
-#define EADC_AD1TRGEN2_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN2: EPWM00FEN Position */
-#define EADC_AD1TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00FEN_Pos) /*!< EADC AD1TRGEN2: EPWM00FEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN2: EPWM00PEN Position */
-#define EADC_AD1TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00PEN_Pos) /*!< EADC AD1TRGEN2: EPWM00PEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN2: EPWM00CEN Position */
-#define EADC_AD1TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00CEN_Pos) /*!< EADC AD1TRGEN2: EPWM00CEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN2: EPWM02REN Position */
-#define EADC_AD1TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02REN_Pos) /*!< EADC AD1TRGEN2: EPWM02REN Mask */
-
-#define EADC_AD1TRGEN2_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN2: EPWM02FEN Position */
-#define EADC_AD1TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02FEN_Pos) /*!< EADC AD1TRGEN2: EPWM02FEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN2: EPWM02PEN Position */
-#define EADC_AD1TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02PEN_Pos) /*!< EADC AD1TRGEN2: EPWM02PEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN2: EPWM02CEN Position */
-#define EADC_AD1TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02CEN_Pos) /*!< EADC AD1TRGEN2: EPWM02CEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN2: EPWM04REN Position */
-#define EADC_AD1TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04REN_Pos) /*!< EADC AD1TRGEN2: EPWM04REN Mask */
-
-#define EADC_AD1TRGEN2_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN2: EPWM04FEN Position */
-#define EADC_AD1TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04FEN_Pos) /*!< EADC AD1TRGEN2: EPWM04FEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN2: EPWM04PEN Position */
-#define EADC_AD1TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04PEN_Pos) /*!< EADC AD1TRGEN2: EPWM04PEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN2: EPWM04CEN Position */
-#define EADC_AD1TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04CEN_Pos) /*!< EADC AD1TRGEN2: EPWM04CEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN2: EPWM10REN Position */
-#define EADC_AD1TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10REN_Pos) /*!< EADC AD1TRGEN2: EPWM10REN Mask */
-
-#define EADC_AD1TRGEN2_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN2: EPWM10FEN Position */
-#define EADC_AD1TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10FEN_Pos) /*!< EADC AD1TRGEN2: EPWM10FEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN2: EPWM10PEN Position */
-#define EADC_AD1TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10PEN_Pos) /*!< EADC AD1TRGEN2: EPWM10PEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN2: EPWM10CEN Position */
-#define EADC_AD1TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10CEN_Pos) /*!< EADC AD1TRGEN2: EPWM10CEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN2: EPWM12REN Position */
-#define EADC_AD1TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12REN_Pos) /*!< EADC AD1TRGEN2: EPWM12REN Mask */
-
-#define EADC_AD1TRGEN2_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN2: EPWM120FEN Position */
-#define EADC_AD1TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM120FEN_Pos) /*!< EADC AD1TRGEN2: EPWM120FEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN2: EPWM12PEN Position */
-#define EADC_AD1TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12PEN_Pos) /*!< EADC AD1TRGEN2: EPWM12PEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN2: EPWM12CEN Position */
-#define EADC_AD1TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12CEN_Pos) /*!< EADC AD1TRGEN2: EPWM12CEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN2: EPWM14REN Position */
-#define EADC_AD1TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14REN_Pos) /*!< EADC AD1TRGEN2: EPWM14REN Mask */
-
-#define EADC_AD1TRGEN2_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN2: EPWM14FEN Position */
-#define EADC_AD1TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14FEN_Pos) /*!< EADC AD1TRGEN2: EPWM14FEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN2: EPWM14PEN Position */
-#define EADC_AD1TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14PEN_Pos) /*!< EADC AD1TRGEN2: EPWM14PEN Mask */
-
-#define EADC_AD1TRGEN2_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN2: EPWM14CEN Position */
-#define EADC_AD1TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14CEN_Pos) /*!< EADC AD1TRGEN2: EPWM14CEN Mask */
-
-#define EADC_AD1TRGEN2_PWM00REN_Pos (24) /*!< EADC AD1TRGEN2: PWM00REN Position */
-#define EADC_AD1TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00REN_Pos) /*!< EADC AD1TRGEN2: PWM00REN Mask */
-
-#define EADC_AD1TRGEN2_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN2: PWM00FEN Position */
-#define EADC_AD1TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00FEN_Pos) /*!< EADC AD1TRGEN2: PWM00FEN Mask */
-
-#define EADC_AD1TRGEN2_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN2: PWM00PEN Position */
-#define EADC_AD1TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00PEN_Pos) /*!< EADC AD1TRGEN2: PWM00PEN Mask */
-
-#define EADC_AD1TRGEN2_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN2: PWM00CEN Position */
-#define EADC_AD1TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00CEN_Pos) /*!< EADC AD1TRGEN2: PWM00CEN Mask */
-
-#define EADC_AD1TRGEN2_PWM01REN_Pos (28) /*!< EADC AD1TRGEN2: PWM01REN Position */
-#define EADC_AD1TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01REN_Pos) /*!< EADC AD1TRGEN2: PWM01REN Mask */
-
-#define EADC_AD1TRGEN2_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN2: PWM01FEN Position */
-#define EADC_AD1TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01FEN_Pos) /*!< EADC AD1TRGEN2: PWM01FEN Mask */
-
-#define EADC_AD1TRGEN2_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN2: PWM01PEN Position */
-#define EADC_AD1TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01PEN_Pos) /*!< EADC AD1TRGEN2: PWM01PEN Mask */
-
-#define EADC_AD1TRGEN2_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN2: PWM01CEN Position */
-#define EADC_AD1TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01CEN_Pos) /*!< EADC AD1TRGEN2: PWM01CEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN3: EPWM00REN Position */
-#define EADC_AD1TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00REN_Pos) /*!< EADC AD1TRGEN3: EPWM00REN Mask */
-
-#define EADC_AD1TRGEN3_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN3: EPWM00FEN Position */
-#define EADC_AD1TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00FEN_Pos) /*!< EADC AD1TRGEN3: EPWM00FEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN3: EPWM00PEN Position */
-#define EADC_AD1TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00PEN_Pos) /*!< EADC AD1TRGEN3: EPWM00PEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN3: EPWM00CEN Position */
-#define EADC_AD1TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00CEN_Pos) /*!< EADC AD1TRGEN3: EPWM00CEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN3: EPWM02REN Position */
-#define EADC_AD1TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02REN_Pos) /*!< EADC AD1TRGEN3: EPWM02REN Mask */
-
-#define EADC_AD1TRGEN3_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN3: EPWM02FEN Position */
-#define EADC_AD1TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02FEN_Pos) /*!< EADC AD1TRGEN3: EPWM02FEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN3: EPWM02PEN Position */
-#define EADC_AD1TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02PEN_Pos) /*!< EADC AD1TRGEN3: EPWM02PEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN3: EPWM02CEN Position */
-#define EADC_AD1TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02CEN_Pos) /*!< EADC AD1TRGEN3: EPWM02CEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN3: EPWM04REN Position */
-#define EADC_AD1TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04REN_Pos) /*!< EADC AD1TRGEN3: EPWM04REN Mask */
-
-#define EADC_AD1TRGEN3_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN3: EPWM04FEN Position */
-#define EADC_AD1TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04FEN_Pos) /*!< EADC AD1TRGEN3: EPWM04FEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN3: EPWM04PEN Position */
-#define EADC_AD1TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04PEN_Pos) /*!< EADC AD1TRGEN3: EPWM04PEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN3: EPWM04CEN Position */
-#define EADC_AD1TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04CEN_Pos) /*!< EADC AD1TRGEN3: EPWM04CEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN3: EPWM10REN Position */
-#define EADC_AD1TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10REN_Pos) /*!< EADC AD1TRGEN3: EPWM10REN Mask */
-
-#define EADC_AD1TRGEN3_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN3: EPWM10FEN Position */
-#define EADC_AD1TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10FEN_Pos) /*!< EADC AD1TRGEN3: EPWM10FEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN3: EPWM10PEN Position */
-#define EADC_AD1TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10PEN_Pos) /*!< EADC AD1TRGEN3: EPWM10PEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN3: EPWM10CEN Position */
-#define EADC_AD1TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10CEN_Pos) /*!< EADC AD1TRGEN3: EPWM10CEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN3: EPWM12REN Position */
-#define EADC_AD1TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12REN_Pos) /*!< EADC AD1TRGEN3: EPWM12REN Mask */
-
-#define EADC_AD1TRGEN3_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN3: EPWM120FEN Position */
-#define EADC_AD1TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM120FEN_Pos) /*!< EADC AD1TRGEN3: EPWM120FEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN3: EPWM12PEN Position */
-#define EADC_AD1TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12PEN_Pos) /*!< EADC AD1TRGEN3: EPWM12PEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN3: EPWM12CEN Position */
-#define EADC_AD1TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12CEN_Pos) /*!< EADC AD1TRGEN3: EPWM12CEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN3: EPWM14REN Position */
-#define EADC_AD1TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14REN_Pos) /*!< EADC AD1TRGEN3: EPWM14REN Mask */
-
-#define EADC_AD1TRGEN3_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN3: EPWM14FEN Position */
-#define EADC_AD1TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14FEN_Pos) /*!< EADC AD1TRGEN3: EPWM14FEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN3: EPWM14PEN Position */
-#define EADC_AD1TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14PEN_Pos) /*!< EADC AD1TRGEN3: EPWM14PEN Mask */
-
-#define EADC_AD1TRGEN3_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN3: EPWM14CEN Position */
-#define EADC_AD1TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14CEN_Pos) /*!< EADC AD1TRGEN3: EPWM14CEN Mask */
-
-#define EADC_AD1TRGEN3_PWM00REN_Pos (24) /*!< EADC AD1TRGEN3: PWM00REN Position */
-#define EADC_AD1TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00REN_Pos) /*!< EADC AD1TRGEN3: PWM00REN Mask */
-
-#define EADC_AD1TRGEN3_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN3: PWM00FEN Position */
-#define EADC_AD1TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00FEN_Pos) /*!< EADC AD1TRGEN3: PWM00FEN Mask */
-
-#define EADC_AD1TRGEN3_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN3: PWM00PEN Position */
-#define EADC_AD1TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00PEN_Pos) /*!< EADC AD1TRGEN3: PWM00PEN Mask */
-
-#define EADC_AD1TRGEN3_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN3: PWM00CEN Position */
-#define EADC_AD1TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00CEN_Pos) /*!< EADC AD1TRGEN3: PWM00CEN Mask */
-
-#define EADC_AD1TRGEN3_PWM01REN_Pos (28) /*!< EADC AD1TRGEN3: PWM01REN Position */
-#define EADC_AD1TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01REN_Pos) /*!< EADC AD1TRGEN3: PWM01REN Mask */
-
-#define EADC_AD1TRGEN3_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN3: PWM01FEN Position */
-#define EADC_AD1TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01FEN_Pos) /*!< EADC AD1TRGEN3: PWM01FEN Mask */
-
-#define EADC_AD1TRGEN3_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN3: PWM01PEN Position */
-#define EADC_AD1TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01PEN_Pos) /*!< EADC AD1TRGEN3: PWM01PEN Mask */
-
-#define EADC_AD1TRGEN3_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN3: PWM01CEN Position */
-#define EADC_AD1TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01CEN_Pos) /*!< EADC AD1TRGEN3: PWM01CEN Mask */
-
-/**@}*/ /* EADC_CONST */
-/**@}*/ /* end of EADC register group */
-
-
-/*---------------------- External Bus Interface Controller -------------------------*/
-/**
- @addtogroup EBI External Bus Interface Controller(EBI)
- Memory Mapped Structure for EBI Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 External Bus Interface General Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8:10] |MCLKDIV |External Output Clock Divider
- * | | |The frequency of EBI output clock is controlled by MCLKDIV as below:
- * | | |000 = HCLK/1.
- * | | |001 = HCLK/2.
- * | | |010 = HCLK/4.
- * | | |011 = HCLK/8.
- * | | |100 = HCLK/16.
- * | | |101 = HCLK/32.
- * | | |11x = Default.
- * | | |Note: Default value of output clock is HCLK/1
- * |[24:27] |CRYPTOEN |Encrypt/Decrypt Function Enable Control (For 4 Individual Chip Select)
- * | | |0 = Encrypt/Decrypt function Disabled.
- * | | |1 = Encrypt/Decrypt function Enabled.
- * |[28:31] |CSPOLINV |Reverse Chip Select
- * | | |The original design Chip Select is active low nCS.
- * | | |"Chip Select Active High" can be specified by customers-Bit[28+n] is for nCS[n], where n=0~3.
- * | | |0 = nCS (chip select active low).
- * | | |1 = CS (chip select active high).
- */
- __IO uint32_t CTL;
-
- /**
- * TCTL
- * ===================================================================================================
- * Offset: 0x04 - 0x10 External Bus Interface Bank0~3 Timing Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |TALE |Bank Expand Time Of ALE
- * | | |The ALE width (tALE) to latch the address can be controlled by TALE.
- * | | |tALE = (TALE+1)*MCLK.
- * |[3:7] |TACC |EBI Bank Data Access Time
- * | | |TACC define data access time (tACC).
- * | | |tACC = (TACC +1) * MCLK.
- * |[8:10] |TAHD |EBI Bank Data Access Hold Time
- * | | |TAHD define data access hold time (tAHD).
- * | | |tAHD = (TAHD +1) * MCLK.
- * |[12:15] |W2X |Bank Idle State Cycle After Write
- * | | |When write action is finish, idle state is inserted and nCS[0] return to high if W2X is not zero.
- * | | |Idle state cycle = (W2X*MCLK).
- * | | |0 = reserved.
- * |[16:19] |R2W |Bank Idle State Cycle Between Read-Write
- * | | |When read action is finish and next action is going to write, idle state is inserted and nCS[0] return to high if R2W is not zero.
- * | | |Idle state cycle = (R2W*MCLK).
- * | | |0 = reserved.
- * |[24:27] |R2R |Bank Idle State Cycle Between Read-Read
- * | | |When read action is finish and next action is going to read, idle state is inserted and nCS[0] return to high if R2R is not zero.
- * | | |Idle state cycle = (R2R*MCLK).
- * | | |0 = reserved.
- * |[28] |CSEN |EBI Bank Enable Control
- * | | |This bit is the functional enable bit for EBI.
- * | | |0 = EBI function Disabled.
- * | | |1 = EBI function Enabled.
- * |[29] |DW16 |EBI Bank Data Width 16-Bit
- * | | |This bit defines if the data bus is 8-bit or 16-bit.
- * | | |0 = EBI data width is 8-bit.
- * | | |1 = EBI data width is 16-bit.
- * |[30] |SEPEN |EBI Bank Address/Data Bus Separating Enable Control
- * | | |0 = Address/Data Bus Separating Disabled.
- * | | |1 = Address/Data Bus Separating Enabled.
- */
- __IO uint32_t TCTL[3];
-
- /**
- * KEY0
- * ===================================================================================================
- * Offset: 0x14 External Bus Interface Crypto Key Word 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY0 |Crypto Key Word 0 (key[31:0]).
- */
- __IO uint32_t KEY0;
-
- /**
- * KEY1
- * ===================================================================================================
- * Offset: 0x18 External Bus Interface Crypto Key Word 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |Crypto Key Word 1 (key[63:32]).
- */
- __IO uint32_t KEY1;
-
- /**
- * KEY2
- * ===================================================================================================
- * Offset: 0x1C External Bus Interface Crypto Key Word 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |Crypto Key Word 2 (key[95:64]).
- */
- __IO uint32_t KEY2;
-
- /**
- * KEY3
- * ===================================================================================================
- * Offset: 0x20 External Bus Interface Crypto Key Word 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |KEY |Crypto Key Word 3 (key[127:96]).
- */
- __IO uint32_t KEY3;
-
-} EBI_T;
-
-/**
- @addtogroup EBI_CONST EBI Bit Field Definition
- Constant Definitions for EBI Controller
-@{ */
-
-#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI CTL: MCLKDIV Position */
-#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI CTL: MCLKDIV Mask */
-
-#define EBI_CTL_CRYPTOEN_Pos (24) /*!< EBI CTL: CRYPTOEN Position */
-#define EBI_CTL_CRYPTOEN_Msk (0xful << EBI_CTL_CRYPTOEN_Pos) /*!< EBI CTL: CRYPTOEN Mask */
-
-#define EBI_CTL_CSPOLINV_Pos (28) /*!< EBI CTL: CSPOLINV Position */
-#define EBI_CTL_CSPOLINV_Msk (0xful << EBI_CTL_CSPOLINV_Pos) /*!< EBI CTL: CSPOLINV Mask */
-
-#define EBI_TCTL_TALE_Pos (0) /*!< EBI TCTL: TALE Position */
-#define EBI_TCTL_TALE_Msk (0x7ul << EBI_TCTL_TALE_Pos) /*!< EBI TCTL: TALE Mask */
-
-#define EBI_TCTL_TACC_Pos (3) /*!< EBI TCTL: TACC Position */
-#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI TCTL: TACC Mask */
-
-#define EBI_TCTL_TAHD_Pos (8) /*!< EBI TCTL: TAHD Position */
-#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI TCTL: TAHD Mask */
-
-#define EBI_TCTL_W2X_Pos (12) /*!< EBI TCTL: W2X Position */
-#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI TCTL: W2X Mask */
-
-#define EBI_TCTL_R2W_Pos (16) /*!< EBI TCTL: R2W Position */
-#define EBI_TCTL_R2W_Msk (0xful << EBI_TCTL_R2W_Pos) /*!< EBI TCTL: R2W Mask */
-
-#define EBI_TCTL_R2R_Pos (24) /*!< EBI TCTL: R2R Position */
-#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI TCTL: R2R Mask */
-
-#define EBI_TCTL_CSEN_Pos (28) /*!< EBI TCTL: CSEN Position */
-#define EBI_TCTL_CSEN_Msk (0x1ul << EBI_TCTL_CSEN_Pos) /*!< EBI TCTL: CSEN Mask */
-
-#define EBI_TCTL_DW16_Pos (29) /*!< EBI TCTL: DW16 Position */
-#define EBI_TCTL_DW16_Msk (0x1ul << EBI_TCTL_DW16_Pos) /*!< EBI TCTL: DW16 Mask */
-
-#define EBI_TCTL_SEPEN_Pos (30) /*!< EBI TCTL: SEPEN Position */
-#define EBI_TCTL_SEPEN_Msk (0x1ul << EBI_TCTL_SEPEN_Pos) /*!< EBI TCTL: SEPEN Mask */
-
-#define EBI_KEY0_KEY_Pos (0) /*!< EBI KEY0: KEY Position */
-#define EBI_KEY0_KEY_Msk (0xfffffffful << EBI_KEY0_KEY_Pos) /*!< EBI KEY0: KEY Mask */
-
-#define EBI_KEY1_KEY_Pos (0) /*!< EBI KEY1: KEY Position */
-#define EBI_KEY1_KEY_Msk (0xfffffffful << EBI_KEY1_KEY_Pos) /*!< EBI KEY1: KEY Mask */
-
-#define EBI_KEY2_KEY_Pos (0) /*!< EBI KEY2: KEY Position */
-#define EBI_KEY2_KEY_Msk (0xfffffffful << EBI_KEY2_KEY_Pos) /*!< EBI KEY2: KEY Mask */
-
-#define EBI_KEY3_KEY_Pos (0) /*!< EBI KEY3: KEY Position */
-#define EBI_KEY3_KEY_Msk (0xfffffffful << EBI_KEY3_KEY_Pos) /*!< EBI KEY3: KEY Mask */
-
-/**@}*/ /* EBI_CONST */
-/**@}*/ /* end of EBI register group */
-
-
-/*---------------------- Ethernet MAC Controller -------------------------*/
-/**
- @addtogroup EMAC Ethernet MAC Controller(EMAC)
- Memory Mapped Structure for EMAC Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CAMCTL
- * ===================================================================================================
- * Offset: 0x00 CAM Comparison Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |AUP |Accept Unicast Packet
- * | | |The AUP controls the unicast packet reception.
- * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
- * | | |0 = EMAC receives packet depends on the CAM comparison result.
- * | | |1 = EMAC receives all unicast packets.
- * |[1] |AMP |Accept Multicast Packet
- * | | |The AMP controls the multicast packet reception.
- * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
- * | | |0 = EMAC receives packet depends on the CAM comparison result.
- * | | |1 = EMAC receives all multicast packets.
- * |[2] |ABP |Accept Broadcast Packet
- * | | |The ABP controls the broadcast packet reception.
- * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
- * | | |0 = EMAC receives packet depends on the CAM comparison result.
- * | | |1 = EMAC receives all broadcast packets.
- * |[3] |COMPEN |Complement CAM Comparison Enable
- * | | |The COMPEN controls the complement of the CAM comparison result.
- * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped.
- * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
- * | | |0 = The CAM comparison result does not complement.
- * | | |1 = The CAM comparison result complemented.
- * |[4] |CMPEN |CAM Compare Enable
- * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition.
- * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
- * | | |0 = CAM comparison function for destination MAC address recognition disabled.
- * | | |1 = CAM comparison function for destination MAC address recognition enabled.
- */
- __IO uint32_t CAMCTL;
-
- /**
- * CAMEN
- * ===================================================================================================
- * Offset: 0x04 CAM Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CAMxEN |CAM Entry X Enable Control
- * | | |The CAMxEN controls the validation of CAM entry x.
- * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission.
- * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first.
- * | | |0 = CAM entry x Disabled.
- * | | |1 = CAM entry x Enabled.
- */
- __IO uint32_t CAMEN;
-
- /**
- * CAM0M
- * ===================================================================================================
- * Offset: 0x08 CAM0 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM0M;
-
- /**
- * CAM0L
- * ===================================================================================================
- * Offset: 0x0C CAM0 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM0L;
-
- /**
- * CAM1M
- * ===================================================================================================
- * Offset: 0x10 CAM1 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM1M;
-
- /**
- * CAM1L
- * ===================================================================================================
- * Offset: 0x14 CAM1 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM1L;
-
- /**
- * CAM2M
- * ===================================================================================================
- * Offset: 0x18 CAM2 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM2M;
-
- /**
- * CAM2L
- * ===================================================================================================
- * Offset: 0x1C CAM2 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM2L;
-
- /**
- * CAM3M
- * ===================================================================================================
- * Offset: 0x20 CAM3 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM3M;
-
- /**
- * CAM3L
- * ===================================================================================================
- * Offset: 0x24 CAM3 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM3L;
-
- /**
- * CAM4M
- * ===================================================================================================
- * Offset: 0x28 CAM4 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM4M;
-
- /**
- * CAM4L
- * ===================================================================================================
- * Offset: 0x2C CAM4 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM4L;
-
- /**
- * CAM5M
- * ===================================================================================================
- * Offset: 0x30 CAM5 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM5M;
-
- /**
- * CAM5L
- * ===================================================================================================
- * Offset: 0x34 CAM5 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM5L;
-
- /**
- * CAM6M
- * ===================================================================================================
- * Offset: 0x38 CAM6 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM6M;
-
- /**
- * CAM6L
- * ===================================================================================================
- * Offset: 0x3C CAM6 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM6L;
-
- /**
- * CAM7M
- * ===================================================================================================
- * Offset: 0x40 CAM7 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM7M;
-
- /**
- * CAM7L
- * ===================================================================================================
- * Offset: 0x44 CAM7 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM7L;
-
- /**
- * CAM8M
- * ===================================================================================================
- * Offset: 0x48 CAM8 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM8M;
-
- /**
- * CAM8L
- * ===================================================================================================
- * Offset: 0x4C CAM8 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM8L;
-
- /**
- * CAM9M
- * ===================================================================================================
- * Offset: 0x50 CAM9 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM9M;
-
- /**
- * CAM9L
- * ===================================================================================================
- * Offset: 0x54 CAM9 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM9L;
-
- /**
- * CAM10M
- * ===================================================================================================
- * Offset: 0x58 CAM10 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM10M;
-
- /**
- * CAM10L
- * ===================================================================================================
- * Offset: 0x5C CAM10 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM10L;
-
- /**
- * CAM11M
- * ===================================================================================================
- * Offset: 0x60 CAM11 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM11M;
-
- /**
- * CAM11L
- * ===================================================================================================
- * Offset: 0x64 CAM11 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM11L;
-
- /**
- * CAM12M
- * ===================================================================================================
- * Offset: 0x68 CAM12 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM12M;
-
- /**
- * CAM12L
- * ===================================================================================================
- * Offset: 0x6C CAM12 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM12L;
-
- /**
- * CAM13M
- * ===================================================================================================
- * Offset: 0x70 CAM13 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM13M;
-
- /**
- * CAM13L
- * ===================================================================================================
- * Offset: 0x74 CAM13 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM13L;
-
- /**
- * CAM14M
- * ===================================================================================================
- * Offset: 0x78 CAM14 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |MACADDR2 |MAC Address Byte 2
- * |[8:15] |MACADDR3 |MAC Address Byte 3
- * |[16:23] |MACADDR4 |MAC Address Byte 4
- * |[24:31] |MACADDR5 |MAC Address Byte 5
- * | | |The CAMxM keeps the bit 47~16 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM14M;
-
- /**
- * CAM14L
- * ===================================================================================================
- * Offset: 0x7C CAM14 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:23] |MACADDR0 |MAC Address Byte 0
- * |[24:31] |MACADDR1 |MAC Address Byte 1
- * | | |The CAMxL keeps the bit 15~0 of MAC address.
- * | | |The x can be the 0~14.
- * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
- * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
- */
- __IO uint32_t CAM14L;
-
- /**
- * CAM15MSB
- * ===================================================================================================
- * Offset: 0x80 CAM15 Most Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |OPCODE |OP Code Field of PAUSE Control Frame
- * | | |In the PAUSE control frame, an op code field defined and is 0x0001.
- * |[16:31] |LENGTH |LENGTH Field of PAUSE Control Frame
- * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
- */
- __IO uint32_t CAM15MSB;
-
- /**
- * CAM15LSB
- * ===================================================================================================
- * Offset: 0x84 CAM15 Least Significant Word Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[24:31] |OPERAND |Pause Parameter
- * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination Ethernet MAC Controller paused.
- * | | |The unit of the OPERAND is a slot time, the 512 bits time.
- */
- __IO uint32_t CAM15LSB;
-
- /**
- * TXDSA
- * ===================================================================================================
- * Offset: 0x88 Transmit Descriptor Link List Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |TXDSA |Transmit Descriptor Link-List Start Address
- * | | |The TXDSA keeps the start address of transmit descriptor link-list.
- * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the current transmit descriptor start address register (EMAC_CTXDSA).
- * | | |The TXDSA does not be updated by EMAC.
- * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA.
- * | | |This means that each TX descriptor always must locate at word boundary memory address.
- */
- __IO uint32_t TXDSA;
-
- /**
- * RXDSA
- * ===================================================================================================
- * Offset: 0x8C Receive Descriptor Link List Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |RXDSA |Receive Descriptor Link-List Start Address
- * | | |The RXDSA keeps the start address of receive descriptor link-list.
- * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current receive descriptor start address register (EMAC_CRXDSA).
- * | | |The RXDSA does not be updated by EMAC.
- * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA.
- * | | |This means that each RX descriptor always must locate at word boundary memory address.
- */
- __IO uint32_t RXDSA;
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x90 MAC Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXON |Frame Reception ON
- * | | |The RXON controls the normal packet reception of EMAC.
- * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX descriptor fetching, packet reception and RX descriptor modification.
- * | | |It is necessary to finish EMAC initial sequence before enable RXON.
- * | | |Otherwise, the EMAC operation is undefined.
- * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet reception process after the current packet reception finished.
- * | | |0 = Packet reception process stopped.
- * | | |1 = Packet reception process started.
- * |[1] |ALP |Accept Long Packet
- * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception.
- * | | |If the ALP is set to high, the EMAC will accept the long packet.
- * | | |Otherwise, the long packet will be dropped.
- * | | |0 = Ethernet MAC controller dropped the long packet.
- * | | |1 = Ethernet MAC controller received the long packet.
- * |[2] |ARP |Accept Runt Packet
- * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception.
- * | | |If the ARP is set to high, the EMAC will accept the runt packet.
- * | | |Otherwise, the runt packet will be dropped.
- * | | |0 = Ethernet MAC controller dropped the runt packet.
- * | | |1 = Ethernet MAC controller received the runt packet.
- * |[3] |ACP |Accept Control Packet
- * | | |The ACP controls the control frame reception.
- * | | |If the ACP is set to high, the EMAC will accept the control frame.
- * | | |Otherwise, the control frame will be dropped.
- * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
- * | | |0 = Ethernet MAC controller dropped the control frame.
- * | | |1 = Ethernet MAC controller received the control frame.
- * |[4] |AEP |Accept CRC Error Packet
- * | | |The AEP controls the EMAC accepts or drops the CRC error packet.
- * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
- * | | |0 = Ethernet MAC controller dropped the CRC error packet.
- * | | |1 = Ethernet MAC controller received the CRC error packet.
- * |[5] |STRIPCRC |Strip CRC Checksum
- * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum.
- * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
- * | | |0 = The 4 bytes CRC checksum is included in packet length calculation.
- * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
- * |[6] |WOLEN |Wake On LAN Enable
- * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode.
- * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller would generate a wakeup event to wake system up from Power-down mode.
- * | | |0 = Wake-up by Magic Packet function Disabled.
- * | | |1 = Wake-up by Magic Packet function Enabled.
- * |[8] |TXON |Frame Transmission ON
- * | | |The TXON controls the normal packet transmission of EMAC.
- * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX descriptor fetching, packet transmission and TX descriptor modification.
- * | | |It is must to finish EMAC initial sequence before enable TXON.
- * | | |Otherwise, the EMAC operation is undefined.
- * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet transmission process after the current packet transmission finished.
- * | | |0 = Packet transmission process stopped.
- * | | |1 = Packet transmission process started.
- * |[9] |NODEF |No Deferral
- * | | |The NODEF controls the enable of deferral exceed counter.
- * | | |If NODEF is set to high, the deferral exceed counter is disabled.
- * | | |The NODEF is only useful while EMAC is operating on half duplex mode.
- * | | |0 = The deferral exceed counter Enabled.
- * | | |1 = The deferral exceed counter Disabled.
- * |[16] |SDPZ |Send PAUSE Frame
- * | | |The SDPZ controls the PAUSE control frame transmission.
- * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set.
- * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
- * | | |The SDPZ is a self-clear bit.
- * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
- * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
- * | | |0 = PAUSE control frame transmission completed.
- * | | |1 = PAUSE control frame transmission Enabled.
- * |[17] |SQECHKEN |SQE Checking Enable
- * | | |The SQECHKEN controls the enable of SQE checking.
- * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode.
- * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100M bps or full duplex mode.
- * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
- * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
- * |[18] |FUDUP |Full Duplex Mode Selection
- * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode.
- * | | |0 = EMAC operates in half duplex mode.
- * | | |1 = EMAC operates in full duplex mode.
- * |[19] |RMIIRXCTL |RMII RX Control
- * | | |The RMIIRXCTL control the receive data sample in RMII mode.
- * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
- * | | |0 = RMII RX control disabled.
- * | | |1 = RMII RX control enabled.
- * |[20] |OPMODE |Operation Mode Selection
- * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode.
- * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value.
- * | | |0 = EMAC operates in 10Mbps mode.
- * | | |1 = EMAC operates in 100Mbps mode.
- * |[22] |RMIIEN |RMII Mode Enable
- * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII interface or RMII interface.
- * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
- * | | |0 = Ethernet MAC controller MII mode Enabled.
- * | | |1 = Ethernet MAC controller RMII mode Enabled.
- * |[24] |RST |Software Reset
- * | | |The RST implements a reset function to make the EMAC return default state.
- * | | |The RST is a self-clear bit.
- * | | |This means after the software reset finished, the RST will be cleared automatically.
- * | | |Enable RST can also reset all control and status registers, exclusive of the control bits RMIIEN (EMAC_CTL[22]), LOOPBK (EMAC_CTL[21]) and OPMODE (EMAC_CTL[20]).
- * | | |The EMAC re-initial is necessary after the software reset completed.
- * | | |0 = Software reset completed.
- * | | |1 = Software reset Enabled.
- */
- __IO uint32_t CTL;
-
- /**
- * MIIMDAT
- * ===================================================================================================
- * Offset: 0x94 MII Management Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATA |MII Management Data
- * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command.
- */
- __IO uint32_t MIIMDAT;
-
- /**
- * MIIMCTL
- * ===================================================================================================
- * Offset: 0x98 MII Management Control and Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:4] |PHYREG |PHY Register Address
- * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command.
- * |[8:12] |PHYADDR |PHY Address
- * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
- * |[16] |WRITE |Write Command
- * | | |The Write defines the MII management command is a read or write.
- * | | |0 = MII management command is a read command.
- * | | |1 = MII management command is a write command.
- * |[17] |BUSY |Busy Bit
- * | | |The BUSY controls the enable of the MII management frame generation.
- * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates the MII management frame to external PHY through MII Management I/F.
- * | | |The BUSY is a self-clear bit.
- * | | |This means the BUSY will be cleared automatically after the MII management command finished.
- * | | |0 = MII management command generation finished.
- * | | |1 = MII management command generation Enabled.
- * |[18] |PREAMSP |Preamble Suppress
- * | | |The PREAMSP controls the preamble field generation of MII management frame.
- * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
- * | | |0 = Preamble field generation of MII management frame not skipped.
- * | | |1 = Preamble field generation of MII management frame skipped.
- * |[19] |MDCON |MDC Clock ON Always
- * | | |The MDC controls the MDC clock generation.
- * | | |If the MDCON is set to high, the MDC clock actives always.
- * | | |Otherwise, the MDC will only active while S/W issues a MII management command.
- * | | |0 = MDC clock only actives while S/W issues a MII management command.
- * | | |1 = MDC clock actives always.
- */
- __IO uint32_t MIIMCTL;
-
- /**
- * FIFOCTL
- * ===================================================================================================
- * Offset: 0x9C FIFO Threshold Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |RXFIFOTH |RXFIFO Low Threshold
- * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory.
- * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold.
- * | | |The low threshold is the half of high threshold always.
- * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to transfer frame data from RXFIFO to system memory.
- * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame data to system memory.
- * | | |00 = Depend on the burst length setting.
- * | | |If the burst length is 8 words, high threshold is 8 words, too.
- * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B.
- * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B.
- * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B.
- * |[8:9] |TXFIFOTH |TXFIFO Low Threshold
- * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO.
- * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold.
- * | | |The high threshold is the twice of low threshold always.During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops generate request to transfer frame data from system memory to TXFIFO.
- * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data from system memory to TXFIFO.
- * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network.
- * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold during the transmission of the frame.
- * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame out after the frame data are all inside the TXFIFO.
- * | | |00 = Undefined.
- * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B.
- * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B.
- * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B.
- * |[20:21] |BURSTLEN |DMA Burst Length
- * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
- * | | |00 = 16 words.
- * | | |01 = 16 words.
- * | | |10 = 8 words.
- * | | |11 = 4 words.
- */
- __IO uint32_t FIFOCTL;
-
- /**
- * TXST
- * ===================================================================================================
- * Offset: 0xA0 Transmit Start Demand Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |TXST |Transmit Start Demand
- * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted.
- * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
- * | | |The EMAC_TXST is a write only register and read from this register is undefined.
- * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
- */
- __O uint32_t TXST;
-
- /**
- * RXST
- * ===================================================================================================
- * Offset: 0xA4 Receive Start Demand Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |RXST |Receive Start Demand
- * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted.
- * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
- * | | |The EMAC_RXST is a write only register and read from this register is undefined.
- * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
- */
- __O uint32_t RXST;
-
- /**
- * MRFL
- * ===================================================================================================
- * Offset: 0xA8 Maximum Receive Frame Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |MRFL |Maximum Receive Frame Length
- * | | |The MRFL defines the maximum frame length for received frame.
- * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
- * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes.
- */
- __IO uint32_t MRFL;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0xAC MAC Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXIEN |Receive Interrupt Enable Control
- * | | |The RXIEN controls the RX interrupt generation.
- * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU.
- * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] is set and the corresponding bit of EMAC_INTEN is enabled.
- * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled.
- * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
- * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
- * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
- * |[1] |CRCEIEN |CRC Error Interrupt Enable Control
- * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation.
- * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CRCEIF (EMAC_INTSTS[1]) is set.
- * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
- * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
- * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Control
- * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation.
- * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXOVIF (EMAC_INTSTS[2]) is set.
- * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
- * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
- * |[3] |LPIEN |Long Packet Interrupt Enable
- * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation.
- * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF (EMAC_INTSTS[3]) is set.
- * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
- * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
- * |[4] |RXGDIEN |Receive Good Interrupt Enable Control
- * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation.
- * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXGDIF (EMAC_INTSTS[4]) is set.
- * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
- * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
- * |[5] |ALIEIEN |Alignment Error Interrupt Enable Control
- * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation.
- * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the ALIEIF (EMAC_INTSTS[5]) is set.
- * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
- * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
- * |[6] |RPIEN |Runt Packet Interrupt Enable Control
- * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation.
- * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RPIF (EMAC_INTSTS[6]) is set.
- * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
- * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
- * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable
- * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation.
- * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MPCOVIF (EMAC_INTSTS[7]) is set.
- * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
- * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
- * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable
- * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation.
- * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MFLEIF (EMAC_INTSTS[8]) is set.
- * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
- * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
- * |[9] |DENIEN |DMA Early Notification Interrupt Enable Control
- * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation.
- * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the DENIF (EMAC_INTSTS[9]) is set.
- * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
- * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
- * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Control
- * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation.
- * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RDUIF (EMAC_MIOSTA[10]) register is set.
- * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
- * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
- * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Control
- * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation.
- * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXBEIF (EMAC_INTSTS[11]) is set.
- * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
- * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
- * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Control
- * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation.
- * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CFRIF (EMAC_INTSTS[14]) register is set.
- * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
- * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
- * |[15] |WOLIEN |Wake On LAN Interrupt Enable
- * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation.
- * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
- * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the WOLIF (EMAC_INTSTS[15]) is set.
- * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
- * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
- * |[16] |TXIEN |Transmit Interrupt Enable Control
- * | | |The TXIEN controls the TX interrupt generation.
- * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU.
- * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled.
- * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled.
- * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
- * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
- * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
- * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Control
- * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation.
- * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXUDIF (EMAC_INTSTS[17]) is set.
- * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
- * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
- * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Control
- * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation.
- * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXCPIF (EMAC_INTSTS[18]) is set.
- * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
- * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
- * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Control
- * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation.
- * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the EXDEFIF (EMAC_INTSTS[19]) is set.
- * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
- * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
- * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Control
- * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation.
- * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the NCSIF (EMAC_INTSTS[20]) is set.
- * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
- * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
- * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Control
- * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation.
- * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXABTIF (EMAC_INTSTS[21]) is set.
- * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
- * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
- * |[22] |LCIEN |Late Collision Interrupt Enable Control
- * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation.
- * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the LCIF (EMAC_INTSTS[22]) is set.
- * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
- * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
- * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Control
- * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation.
- * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TDUIF (EMAC_INTSTS[23]) is set.
- * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
- * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
- * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Control
- * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation.
- * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXBEIF (EMAC_INTSTS[24]) is set.
- * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
- * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
- * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Control
- * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation.
- * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the EMAC generates the TX interrupt to CPU.
- * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the TXTSALMIF (EMAC_INTEN[28]) is set.
- * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
- * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0xB0 MAC Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXIF |Receive Interrupt
- * | | |The RXIF indicates the RX interrupt status.
- * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates the EMAC generates RX interrupt to CPU.
- * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
- * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1].
- * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
- * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
- * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
- * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in EMAC_INTEN[15:1] is enabled, too.
- * |[1] |CRCEIF |CRC Error Interrupt
- * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped.
- * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and CRCEIF will not be set.
- * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the CRCEIF status.
- * | | |0 = The frame does not incur CRC error.
- * | | |1 = The frame incurred CRC error.
- * |[2] |RXOVIF |Receive FIFO Overflow Interrupt
- * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception.
- * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer.
- * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, the RXFIFOTH of FFTCR register, to higher level.
- * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the RXOVIF status.
- * | | |0 = No RXFIFO overflow occurred during packet reception.
- * | | |1 = RXFIFO overflow occurred during packet reception.
- * |[3] |LPIF |Long Packet Interrupt Flag
- * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped.
- * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
- * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the LPIF status.
- * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
- * | | |1 = The incoming frame is a long frame and dropped.
- * |[4] |RXGDIF |Receive Good Interrupt
- * | | |The RXGDIF high indicates the frame reception has completed.
- * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the RXGDIF status.
- * | | |0 = The frame reception has not complete yet.
- * | | |1 = The frame reception has completed.
- * |[5] |ALIEIF |Alignment Error Interrupt
- * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte.
- * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the ALIEIF status.
- * | | |0 = The frame length is a multiple of byte.
- * | | |1 = The frame length is not a multiple of byte.
- * |[6] |RPIF |Runt Packet Interrupt
- * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped.
- * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
- * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the RPIF status.
- * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
- * | | |1 = The incoming frame is a short frame and dropped.
- * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag
- * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow.
- * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the MPCOVIF status.
- * | | |0 = The MPCNT has not rolled over yet.
- * | | |1 = The MPCNT has rolled over yet.
- * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag
- * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped.
- * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the MFLEIF status.
- * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
- * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
- * |[9] |DENIF |DMA Early Notification Interrupt
- * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
- * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the DENIF status.
- * | | |0 = The LENGTH field of incoming packet has not received yet.
- * | | |1 = The LENGTH field of incoming packet has received.
- * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt
- * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state.
- * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to make RXDMA leave Halt state while new RX descriptor is available.
- * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the RDUIF status.
- * | | |0 = RX descriptor is available.
- * | | |1 = RX descriptor is unavailable.
- * |[11] |RXBEIF |Receive Bus Error Interrupt
- * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through RXDMA during packet reception process.
- * | | |Reset EMAC is recommended while RXBEIF status is high.
- * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the RXBEIF status.
- * | | |0 = No ERROR response is received.
- * | | |1 = ERROR response is received.
- * |[14] |CFRIF |Control Frame Receive Interrupt
- * | | |The CFRIF high indicates EMAC receives a flow control frame.
- * | | |The CFRIF only available while EMAC is operating on full duplex mode.
- * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the CFRIF status.
- * | | |0 = The EMAC does not receive the flow control frame.
- * | | |1 = The EMAC receives a flow control frame.
- * |[15] |WOLIF |Wake On LAN Interrupt Flag
- * | | |The WOLIF high indicates EMAC receives a Magic Packet.
- * | | |The CFRIF only available while system is in power down mode and WOLEN is set high.
- * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high.
- * | | |Write 1 to this bit clears the WOLIF status.
- * | | |0 = The EMAC does not receive the Magic Packet.
- * | | |1 = The EMAC receives a Magic Packet.
- * |[16] |TXIF |Transmit Interrupt
- * | | |The TXIF indicates the TX interrupt status.
- * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates the EMAC generates TX interrupt to CPU.
- * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
- * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17].
- * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit in EMAC_INTEN[28:17] is also enabled, the TXIF will be high.
- * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
- * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
- * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit in EMAC_INTEN[28:17] is enabled, too.
- * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt
- * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission.
- * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically without S/W intervention.
- * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, the TXFIFOTH of FFTCR register, to higher level.
- * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the TXUDIF status.
- * | | |0 = No TXFIFO underflow occurred during packet transmission.
- * | | |1 = TXFIFO underflow occurred during packet transmission.
- * |[18] |TXCPIF |Transmit Completion Interrupt
- * | | |The TXCPIF indicates the packet transmission has completed correctly.
- * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the TXCPIF status.
- * | | |0 = The packet transmission not completed.
- * | | |1 = The packet transmission has completed.
- * |[19] |EXDEFIF |Defer Exceed Interrupt
- * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode.
- * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC is operating on half-duplex mode.
- * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the EXDEFIF status.
- * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
- * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
- * |[20] |NCSIF |No Carrier Sense Interrupt
- * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during the packet transmission.
- * | | |The NCSIF is only available while EMAC is operating on half-duplex mode.
- * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the NCSIF status.
- * | | |0 = CRS signal actives correctly.
- * | | |1 = CRS signal does not active at the start of or during the packet transmission.
- * |[21] |TXABTIF |Transmit Abort Interrupt
- * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted.
- * | | |The transmission abort is only available while EMAC is operating on half-duplex mode.
- * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the TXABTIF status.
- * | | |0 = Packet does not incur 16 consecutive collisions during transmission.
- * | | |1 = Packet incurred 16 consecutive collisions during transmission.
- * |[22] |LCIF |Late Collision Interrupt
- * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window.
- * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision still occurred.
- * | | |The late collision check will only be done while EMAC is operating on half-duplex mode.
- * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the LCIF status.
- * | | |0 = No collision occurred in the outside of 64 bytes collision window.
- * | | |1 = Collision occurred in the outside of 64 bytes collision window.
- * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt
- * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state.
- * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make TXDMA leave Halt state while new TX descriptor is available.
- * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the TDUIF status.
- * | | |0 = TX descriptor is available.
- * | | |1 = TX descriptor is unavailable.
- * |[24] |TXBEIF |Transmit Bus Error Interrupt
- * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through TXDMA during packet transmission process.
- * | | |Reset EMAC is recommended while TXBEIF status is high.
- * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the TXBEIF status.
- * | | |0 = No ERROR response is received.
- * | | |1 = ERROR response is received.
- * |[28] |TSALMIF |Time Stamp Alarm Interrupt
- * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and EMAC_TSSUBSEC register value equals to register EMAC_TSMLSR.
- * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
- * | | |Write 1 to this bit clears the TSALMIF status.
- * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
- * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
- */
- __IO uint32_t INTSTS;
-
- /**
- * GENSTS
- * ===================================================================================================
- * Offset: 0xB4 MAC General Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CFRIF |Control Frame Received
- * | | |The CFRIF high indicates EMAC receives a flow control frame.
- * | | |The CFRIF only available while EMAC is operating on full duplex mode.
- * | | |0 = The EMAC does not receive the flow control frame.
- * | | |1 = The EMAC receives a flow control frame.
- * |[1] |RXHALT |Receive Halted
- * | | |The RXHALT high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W.
- * | | |0 = Next normal packet reception process will go on.
- * | | |1 = Next normal packet reception process will be halted.
- * |[2] |RXFFULL |RXFIFO Full
- * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO and the following incoming packet will be dropped.
- * | | |0 = The RXFIFO is not full.
- * | | |1 = The RXFIFO is full and the following incoming packet will be dropped.
- * |[4:7] |COLCNT |Collision Count
- * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission.
- * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be 0 and bit TXABTIF will be set to 1.
- * |[8] |DEF |Deferred Transmission
- * | | |The DEF high indicates the packet transmission has deferred once.
- * | | |The DEF is only available while EMAC is operating on half-duplex mode.
- * | | |0 = Packet transmission does not defer.
- * | | |1 = Packet transmission has deferred once.
- * |[9] |TXPAUSED |Transmission Paused
- * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame.
- * | | |0 = Next normal packet transmission process will go on.
- * | | |1 = Next normal packet transmission process will be paused.
- * |[10] |SQE |Signal Quality Error
- * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode.
- * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC is operating on 10Mbps half-duplex mode.
- * | | |0 = No SQE error found at end of packet transmission.
- * | | |1 = SQE error found at end of packet transmission.
- * |[11] |TXHALT |Transmission Halted
- * | | |The TXHALT high indicates the next normal packet transmission process will be halted because the bit TXON (EMAC_CTL[8]) is disabled be S/W.
- * | | |0 = Next normal packet transmission process will go on.
- * | | |1 = Next normal packet transmission process will be halted.
- * |[12] |RPSTS |Remote Pause Status
- * | | |The RPSTS indicates that remote pause counter down counting actives.
- * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause counter down counting.
- * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet transmission until the down counting done.
- * | | |0 = Remote pause counter down counting done.
- * | | |1 = Remote pause counter down counting actives.
- */
- __IO uint32_t GENSTS;
-
- /**
- * MPCNT
- * ===================================================================================================
- * Offset: 0xB8 Missed Packet Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |MPCNT |Miss Packet Count
- * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors.
- * | | |The following type of receiving error makes missed packet counter increase:.
- * | | |1. Incoming packet is incurred RXFIFO overflow.
- * | | |2. Incoming packet is dropped due to RXON is disabled.
- * | | |3. Incoming packet is incurred CRC error.
- */
- __IO uint32_t MPCNT;
-
- /**
- * RPCNT
- * ===================================================================================================
- * Offset: 0xBC MAC Receive Pause Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RPCNT |MAC Receive Pause Count
- * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame.
- * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
- */
- __I uint32_t RPCNT;
- uint32_t RESERVE0[2];
-
-
- /**
- * FRSTS
- * ===================================================================================================
- * Offset: 0xC8 DMA Receive Frame Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RXFLT |Receive Frame LENGTH
- * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet.
- * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
- * | | |And, the content of LENGTH field will be stored in RXFLT.
- */
- __IO uint32_t FRSTS;
-
- /**
- * CTXDSA
- * ===================================================================================================
- * Offset: 0xCC Current Transmit Descriptor Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CTXDSA |Current Transmit Descriptor Start Address
- * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently.
- * | | |The CTXDSA is read only and write to this register has no effect.
- */
- __I uint32_t CTXDSA;
-
- /**
- * CTXBSA
- * ===================================================================================================
- * Offset: 0xD0 Current Transmit Buffer Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CTXBSA |Current Transmit Buffer Start Address
- * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently.
- * | | |The CTXBSA is read only and write to this register has no effect.
- */
- __I uint32_t CTXBSA;
-
- /**
- * CRXDSA
- * ===================================================================================================
- * Offset: 0xD4 Current Receive Descriptor Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CRXDSA |Current Receive Descriptor Start Address
- * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently.
- * | | |The CRXDSA is read only and write to this register has no effect.
- */
- __I uint32_t CRXDSA;
-
- /**
- * CRXBSA
- * ===================================================================================================
- * Offset: 0xD8 Current Receive Buffer Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |CRXBSA |Current Receive Buffer Start Address
- * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently.
- * | | |The CRXBSA is read only and write to this register has no effect.
- */
- __I uint32_t CRXBSA;
- uint32_t RESERVE1[9];
-
-
- /**
- * TSCTL
- * ===================================================================================================
- * Offset: 0x100 Time Stamp Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TSEN |Time Stamp Function Enable Control
- * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
- * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low to disable IEEE 1588 PTP time stamp function.
- * | | |0 = I EEE 1588 PTP time stamp function Disabled.
- * | | |1 = IEEE 1588 PTP time stamp function Enabled.
- * |[1] |TSIEN |Time Stamp Counter Initialization Enable Control
- * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stampe counter.
- * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
- * | | |0 = Time stamp counter initialization done.
- * | | |1 = Time stamp counter initialization Enabled.
- * |[2] |TSMODE |Time Stamp Fine Update Enable Control
- * | | |This bit chooses the time stamp counter update mode.
- * | | |0 = Time stamp counter is in coarse update mode.
- * | | |1 = Time stamp counter is in fine update mode.
- * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Control
- * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter.
- * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
- * | | |0 = No action.
- * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
- * |[5] |TSALMEN |Time Stamp Alarm Enable Control
- * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
- * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
- * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
- */
- __IO uint32_t TSCTL;
- uint32_t RESERVE2[3];
-
-
- /**
- * TSSEC
- * ===================================================================================================
- * Offset: 0x110 Time Stamp Most Significant Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SEC |Time Stamp Counter Second
- * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter.
- * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
- */
- __I uint32_t TSSEC;
-
- /**
- * TSSUBSEC
- * ===================================================================================================
- * Offset: 0x114 Time Stamp Least Significant Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SUBSEC |Time Stamp Counter Sub-Second
- * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter.
- * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
- */
- __I uint32_t TSSUBSEC;
-
- /**
- * TSINC
- * ===================================================================================================
- * Offset: 0x118 Time Stamp Increment Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |CNTINC |Time Stamp Counter Increment
- * | | |Time stamp counter increment value.
- * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every time when it wants to increase the EMAC_TSSUBSEC value.
- */
- __IO uint32_t TSINC;
-
- /**
- * TSADDEND
- * ===================================================================================================
- * Offset: 0x11C Time Stamp Addend Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ADDEND |Time Stamp Counter Addend
- * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
- * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator with this 32-bit value in each HCLK.
- * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit value kept in register EMAC_TSINC.
- */
- __IO uint32_t TSADDEND;
-
- /**
- * UPDSEC
- * ===================================================================================================
- * Offset: 0x120 Time Stamp Most Significant Update Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SEC |Time Stamp Counter Second Update
- * | | |When TSIEN (EMAC_TSCTL[1]) is high.
- * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly.
- * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
- */
- __IO uint32_t UPDSEC;
-
- /**
- * UPDSUBSEC
- * ===================================================================================================
- * Offset: 0x124 Time Stamp Least Significant Update Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SUBSEC |Time Stamp Counter Sub-Second Update
- * | | |When TSIEN (EMAC_TSCTL[1]) is high.
- * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly.
- * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
- */
- __IO uint32_t UPDSUBSEC;
-
- /**
- * ALMSEC
- * ===================================================================================================
- * Offset: 0x128 Time Stamp Most Significant Alarm Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SEC |Time Stamp Counter Second Alarm
- * | | |Time stamp counter second part alarm value.
- * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high.
- * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
- */
- __IO uint32_t ALMSEC;
-
- /**
- * ALMSUBSEC
- * ===================================================================================================
- * Offset: 0x12C Time Stamp Least Significant Alarm Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SUBSEC |Time Stamp Counter Sub-Second Alarm
- * | | |Time stamp counter sub-second part alarm value.
- * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high.
- * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
- */
- __IO uint32_t ALMSUBSEC;
-
-} EMAC_T;
-
-/**
- @addtogroup EMAC_CONST EMAC Bit Field Definition
- Constant Definitions for EMAC Controller
-@{ */
-
-#define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC CAMCTL: AUP Position */
-#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC CAMCTL: AUP Mask */
-
-#define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC CAMCTL: AMP Position */
-#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC CAMCTL: AMP Mask */
-
-#define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC CAMCTL: ABP Position */
-#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC CAMCTL: ABP Mask */
-
-#define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC CAMCTL: COMPEN Position */
-#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC CAMCTL: COMPEN Mask */
-
-#define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC CAMCTL: CMPEN Position */
-#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC CAMCTL: CMPEN Mask */
-
-#define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC CAMEN: CAMxEN Position */
-#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC CAMEN: CAMxEN Mask */
-
-#define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC CAM0M: MACADDR2 Position */
-#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC CAM0M: MACADDR2 Mask */
-
-#define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC CAM0M: MACADDR3 Position */
-#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC CAM0M: MACADDR3 Mask */
-
-#define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC CAM0M: MACADDR4 Position */
-#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC CAM0M: MACADDR4 Mask */
-
-#define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC CAM0M: MACADDR5 Position */
-#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC CAM0M: MACADDR5 Mask */
-
-#define EMAC_CAM0L_Rserved_Pos (0) /*!< EMAC CAM0L: Rserved Position */
-#define EMAC_CAM0L_Rserved_Msk (0xfffful << EMAC_CAM0L_Rserved_Pos) /*!< EMAC CAM0L: Rserved Mask */
-
-#define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC CAM0L: MACADDR0 Position */
-#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC CAM0L: MACADDR0 Mask */
-
-#define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC CAM0L: MACADDR1 Position */
-#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC CAM0L: MACADDR1 Mask */
-
-#define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC CAM1M: MACADDR2 Position */
-#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC CAM1M: MACADDR2 Mask */
-
-#define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC CAM1M: MACADDR3 Position */
-#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC CAM1M: MACADDR3 Mask */
-
-#define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC CAM1M: MACADDR4 Position */
-#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC CAM1M: MACADDR4 Mask */
-
-#define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC CAM1M: MACADDR5 Position */
-#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC CAM1M: MACADDR5 Mask */
-
-#define EMAC_CAM1L_Rserved_Pos (0) /*!< EMAC CAM1L: Rserved Position */
-#define EMAC_CAM1L_Rserved_Msk (0xfffful << EMAC_CAM1L_Rserved_Pos) /*!< EMAC CAM1L: Rserved Mask */
-
-#define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC CAM1L: MACADDR0 Position */
-#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC CAM1L: MACADDR0 Mask */
-
-#define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC CAM1L: MACADDR1 Position */
-#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC CAM1L: MACADDR1 Mask */
-
-#define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC CAM2M: MACADDR2 Position */
-#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC CAM2M: MACADDR2 Mask */
-
-#define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC CAM2M: MACADDR3 Position */
-#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC CAM2M: MACADDR3 Mask */
-
-#define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC CAM2M: MACADDR4 Position */
-#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC CAM2M: MACADDR4 Mask */
-
-#define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC CAM2M: MACADDR5 Position */
-#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC CAM2M: MACADDR5 Mask */
-
-#define EMAC_CAM2L_Rserved_Pos (0) /*!< EMAC CAM2L: Rserved Position */
-#define EMAC_CAM2L_Rserved_Msk (0xfffful << EMAC_CAM2L_Rserved_Pos) /*!< EMAC CAM2L: Rserved Mask */
-
-#define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC CAM2L: MACADDR0 Position */
-#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC CAM2L: MACADDR0 Mask */
-
-#define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC CAM2L: MACADDR1 Position */
-#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC CAM2L: MACADDR1 Mask */
-
-#define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC CAM3M: MACADDR2 Position */
-#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC CAM3M: MACADDR2 Mask */
-
-#define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC CAM3M: MACADDR3 Position */
-#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC CAM3M: MACADDR3 Mask */
-
-#define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC CAM3M: MACADDR4 Position */
-#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC CAM3M: MACADDR4 Mask */
-
-#define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC CAM3M: MACADDR5 Position */
-#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC CAM3M: MACADDR5 Mask */
-
-#define EMAC_CAM3L_Rserved_Pos (0) /*!< EMAC CAM3L: Rserved Position */
-#define EMAC_CAM3L_Rserved_Msk (0xfffful << EMAC_CAM3L_Rserved_Pos) /*!< EMAC CAM3L: Rserved Mask */
-
-#define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC CAM3L: MACADDR0 Position */
-#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC CAM3L: MACADDR0 Mask */
-
-#define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC CAM3L: MACADDR1 Position */
-#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC CAM3L: MACADDR1 Mask */
-
-#define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC CAM4M: MACADDR2 Position */
-#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC CAM4M: MACADDR2 Mask */
-
-#define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC CAM4M: MACADDR3 Position */
-#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC CAM4M: MACADDR3 Mask */
-
-#define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC CAM4M: MACADDR4 Position */
-#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC CAM4M: MACADDR4 Mask */
-
-#define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC CAM4M: MACADDR5 Position */
-#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC CAM4M: MACADDR5 Mask */
-
-#define EMAC_CAM4L_Rserved_Pos (0) /*!< EMAC CAM4L: Rserved Position */
-#define EMAC_CAM4L_Rserved_Msk (0xfffful << EMAC_CAM4L_Rserved_Pos) /*!< EMAC CAM4L: Rserved Mask */
-
-#define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC CAM4L: MACADDR0 Position */
-#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC CAM4L: MACADDR0 Mask */
-
-#define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC CAM4L: MACADDR1 Position */
-#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC CAM4L: MACADDR1 Mask */
-
-#define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC CAM5M: MACADDR2 Position */
-#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC CAM5M: MACADDR2 Mask */
-
-#define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC CAM5M: MACADDR3 Position */
-#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC CAM5M: MACADDR3 Mask */
-
-#define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC CAM5M: MACADDR4 Position */
-#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC CAM5M: MACADDR4 Mask */
-
-#define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC CAM5M: MACADDR5 Position */
-#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC CAM5M: MACADDR5 Mask */
-
-#define EMAC_CAM5L_Rserved_Pos (0) /*!< EMAC CAM5L: Rserved Position */
-#define EMAC_CAM5L_Rserved_Msk (0xfffful << EMAC_CAM5L_Rserved_Pos) /*!< EMAC CAM5L: Rserved Mask */
-
-#define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC CAM5L: MACADDR0 Position */
-#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC CAM5L: MACADDR0 Mask */
-
-#define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC CAM5L: MACADDR1 Position */
-#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC CAM5L: MACADDR1 Mask */
-
-#define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC CAM6M: MACADDR2 Position */
-#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC CAM6M: MACADDR2 Mask */
-
-#define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC CAM6M: MACADDR3 Position */
-#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC CAM6M: MACADDR3 Mask */
-
-#define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC CAM6M: MACADDR4 Position */
-#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC CAM6M: MACADDR4 Mask */
-
-#define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC CAM6M: MACADDR5 Position */
-#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC CAM6M: MACADDR5 Mask */
-
-#define EMAC_CAM6L_Rserved_Pos (0) /*!< EMAC CAM6L: Rserved Position */
-#define EMAC_CAM6L_Rserved_Msk (0xfffful << EMAC_CAM6L_Rserved_Pos) /*!< EMAC CAM6L: Rserved Mask */
-
-#define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC CAM6L: MACADDR0 Position */
-#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC CAM6L: MACADDR0 Mask */
-
-#define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC CAM6L: MACADDR1 Position */
-#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC CAM6L: MACADDR1 Mask */
-
-#define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC CAM7M: MACADDR2 Position */
-#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC CAM7M: MACADDR2 Mask */
-
-#define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC CAM7M: MACADDR3 Position */
-#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC CAM7M: MACADDR3 Mask */
-
-#define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC CAM7M: MACADDR4 Position */
-#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC CAM7M: MACADDR4 Mask */
-
-#define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC CAM7M: MACADDR5 Position */
-#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC CAM7M: MACADDR5 Mask */
-
-#define EMAC_CAM7L_Rserved_Pos (0) /*!< EMAC CAM7L: Rserved Position */
-#define EMAC_CAM7L_Rserved_Msk (0xfffful << EMAC_CAM7L_Rserved_Pos) /*!< EMAC CAM7L: Rserved Mask */
-
-#define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC CAM7L: MACADDR0 Position */
-#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC CAM7L: MACADDR0 Mask */
-
-#define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC CAM7L: MACADDR1 Position */
-#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC CAM7L: MACADDR1 Mask */
-
-#define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC CAM8M: MACADDR2 Position */
-#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC CAM8M: MACADDR2 Mask */
-
-#define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC CAM8M: MACADDR3 Position */
-#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC CAM8M: MACADDR3 Mask */
-
-#define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC CAM8M: MACADDR4 Position */
-#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC CAM8M: MACADDR4 Mask */
-
-#define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC CAM8M: MACADDR5 Position */
-#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC CAM8M: MACADDR5 Mask */
-
-#define EMAC_CAM8L_Rserved_Pos (0) /*!< EMAC CAM8L: Rserved Position */
-#define EMAC_CAM8L_Rserved_Msk (0xfffful << EMAC_CAM8L_Rserved_Pos) /*!< EMAC CAM8L: Rserved Mask */
-
-#define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC CAM8L: MACADDR0 Position */
-#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC CAM8L: MACADDR0 Mask */
-
-#define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC CAM8L: MACADDR1 Position */
-#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC CAM8L: MACADDR1 Mask */
-
-#define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC CAM9M: MACADDR2 Position */
-#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC CAM9M: MACADDR2 Mask */
-
-#define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC CAM9M: MACADDR3 Position */
-#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC CAM9M: MACADDR3 Mask */
-
-#define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC CAM9M: MACADDR4 Position */
-#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC CAM9M: MACADDR4 Mask */
-
-#define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC CAM9M: MACADDR5 Position */
-#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC CAM9M: MACADDR5 Mask */
-
-#define EMAC_CAM9L_Rserved_Pos (0) /*!< EMAC CAM9L: Rserved Position */
-#define EMAC_CAM9L_Rserved_Msk (0xfffful << EMAC_CAM9L_Rserved_Pos) /*!< EMAC CAM9L: Rserved Mask */
-
-#define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC CAM9L: MACADDR0 Position */
-#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC CAM9L: MACADDR0 Mask */
-
-#define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC CAM9L: MACADDR1 Position */
-#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC CAM9L: MACADDR1 Mask */
-
-#define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC CAM10M: MACADDR2 Position */
-#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC CAM10M: MACADDR2 Mask */
-
-#define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC CAM10M: MACADDR3 Position */
-#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC CAM10M: MACADDR3 Mask */
-
-#define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC CAM10M: MACADDR4 Position */
-#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC CAM10M: MACADDR4 Mask */
-
-#define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC CAM10M: MACADDR5 Position */
-#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC CAM10M: MACADDR5 Mask */
-
-#define EMAC_CAM10L_Rserved_Pos (0) /*!< EMAC CAM10L: Rserved Position */
-#define EMAC_CAM10L_Rserved_Msk (0xfffful << EMAC_CAM10L_Rserved_Pos) /*!< EMAC CAM10L: Rserved Mask */
-
-#define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC CAM10L: MACADDR0 Position */
-#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC CAM10L: MACADDR0 Mask */
-
-#define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC CAM10L: MACADDR1 Position */
-#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC CAM10L: MACADDR1 Mask */
-
-#define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC CAM11M: MACADDR2 Position */
-#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC CAM11M: MACADDR2 Mask */
-
-#define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC CAM11M: MACADDR3 Position */
-#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC CAM11M: MACADDR3 Mask */
-
-#define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC CAM11M: MACADDR4 Position */
-#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC CAM11M: MACADDR4 Mask */
-
-#define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC CAM11M: MACADDR5 Position */
-#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC CAM11M: MACADDR5 Mask */
-
-#define EMAC_CAM11L_Rserved_Pos (0) /*!< EMAC CAM11L: Rserved Position */
-#define EMAC_CAM11L_Rserved_Msk (0xfffful << EMAC_CAM11L_Rserved_Pos) /*!< EMAC CAM11L: Rserved Mask */
-
-#define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC CAM11L: MACADDR0 Position */
-#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC CAM11L: MACADDR0 Mask */
-
-#define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC CAM11L: MACADDR1 Position */
-#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC CAM11L: MACADDR1 Mask */
-
-#define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC CAM12M: MACADDR2 Position */
-#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC CAM12M: MACADDR2 Mask */
-
-#define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC CAM12M: MACADDR3 Position */
-#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC CAM12M: MACADDR3 Mask */
-
-#define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC CAM12M: MACADDR4 Position */
-#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC CAM12M: MACADDR4 Mask */
-
-#define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC CAM12M: MACADDR5 Position */
-#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC CAM12M: MACADDR5 Mask */
-
-#define EMAC_CAM12L_Rserved_Pos (0) /*!< EMAC CAM12L: Rserved Position */
-#define EMAC_CAM12L_Rserved_Msk (0xfffful << EMAC_CAM12L_Rserved_Pos) /*!< EMAC CAM12L: Rserved Mask */
-
-#define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC CAM12L: MACADDR0 Position */
-#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC CAM12L: MACADDR0 Mask */
-
-#define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC CAM12L: MACADDR1 Position */
-#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC CAM12L: MACADDR1 Mask */
-
-#define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC CAM13M: MACADDR2 Position */
-#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC CAM13M: MACADDR2 Mask */
-
-#define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC CAM13M: MACADDR3 Position */
-#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC CAM13M: MACADDR3 Mask */
-
-#define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC CAM13M: MACADDR4 Position */
-#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC CAM13M: MACADDR4 Mask */
-
-#define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC CAM13M: MACADDR5 Position */
-#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC CAM13M: MACADDR5 Mask */
-
-#define EMAC_CAM13L_Rserved_Pos (0) /*!< EMAC CAM13L: Rserved Position */
-#define EMAC_CAM13L_Rserved_Msk (0xfffful << EMAC_CAM13L_Rserved_Pos) /*!< EMAC CAM13L: Rserved Mask */
-
-#define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC CAM13L: MACADDR0 Position */
-#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC CAM13L: MACADDR0 Mask */
-
-#define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC CAM13L: MACADDR1 Position */
-#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC CAM13L: MACADDR1 Mask */
-
-#define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC CAM14M: MACADDR2 Position */
-#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC CAM14M: MACADDR2 Mask */
-
-#define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC CAM14M: MACADDR3 Position */
-#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC CAM14M: MACADDR3 Mask */
-
-#define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC CAM14M: MACADDR4 Position */
-#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC CAM14M: MACADDR4 Mask */
-
-#define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC CAM14M: MACADDR5 Position */
-#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC CAM14M: MACADDR5 Mask */
-
-#define EMAC_CAM14L_Rserved_Pos (0) /*!< EMAC CAM14L: Rserved Position */
-#define EMAC_CAM14L_Rserved_Msk (0xfffful << EMAC_CAM14L_Rserved_Pos) /*!< EMAC CAM14L: Rserved Mask */
-
-#define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC CAM14L: MACADDR0 Position */
-#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC CAM14L: MACADDR0 Mask */
-
-#define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC CAM14L: MACADDR1 Position */
-#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC CAM14L: MACADDR1 Mask */
-
-#define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC CAM15MSB: OPCODE Position */
-#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC CAM15MSB: OPCODE Mask */
-
-#define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC CAM15MSB: LENGTH Position */
-#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC CAM15MSB: LENGTH Mask */
-
-#define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC CAM15LSB: OPERAND Position */
-#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC CAM15LSB: OPERAND Mask */
-
-#define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC TXDSA: TXDSA Position */
-#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC TXDSA: TXDSA Mask */
-
-#define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC RXDSA: RXDSA Position */
-#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC RXDSA: RXDSA Mask */
-
-#define EMAC_CTL_RXON_Pos (0) /*!< EMAC CTL: RXON Position */
-#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC CTL: RXON Mask */
-
-#define EMAC_CTL_ALP_Pos (1) /*!< EMAC CTL: ALP Position */
-#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC CTL: ALP Mask */
-
-#define EMAC_CTL_ARP_Pos (2) /*!< EMAC CTL: ARP Position */
-#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC CTL: ARP Mask */
-
-#define EMAC_CTL_ACP_Pos (3) /*!< EMAC CTL: ACP Position */
-#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC CTL: ACP Mask */
-
-#define EMAC_CTL_AEP_Pos (4) /*!< EMAC CTL: AEP Position */
-#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC CTL: AEP Mask */
-
-#define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC CTL: STRIPCRC Position */
-#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC CTL: STRIPCRC Mask */
-
-#define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC CTL: WOLEN Position */
-#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC CTL: WOLEN Mask */
-
-#define EMAC_CTL_TXON_Pos (8) /*!< EMAC CTL: TXON Position */
-#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC CTL: TXON Mask */
-
-#define EMAC_CTL_NODEF_Pos (9) /*!< EMAC CTL: NODEF Position */
-#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC CTL: NODEF Mask */
-
-#define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC CTL: SDPZ Position */
-#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC CTL: SDPZ Mask */
-
-#define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC CTL: SQECHKEN Position */
-#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC CTL: SQECHKEN Mask */
-
-#define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC CTL: FUDUP Position */
-#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC CTL: FUDUP Mask */
-
-#define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC CTL: RMIIRXCTL Position */
-#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC CTL: RMIIRXCTL Mask */
-
-#define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC CTL: OPMODE Position */
-#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC CTL: OPMODE Mask */
-
-#define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC CTL: RMIIEN Position */
-#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC CTL: RMIIEN Mask */
-
-#define EMAC_CTL_RST_Pos (24) /*!< EMAC CTL: RST Position */
-#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC CTL: RST Mask */
-
-#define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC MIIMDAT: DATA Position */
-#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC MIIMDAT: DATA Mask */
-
-#define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC MIIMCTL: PHYREG Position */
-#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC MIIMCTL: PHYREG Mask */
-
-#define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC MIIMCTL: PHYADDR Position */
-#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC MIIMCTL: PHYADDR Mask */
-
-#define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC MIIMCTL: WRITE Position */
-#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC MIIMCTL: WRITE Mask */
-
-#define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC MIIMCTL: BUSY Position */
-#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC MIIMCTL: BUSY Mask */
-
-#define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC MIIMCTL: PREAMSP Position */
-#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC MIIMCTL: PREAMSP Mask */
-
-#define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC MIIMCTL: MDCON Position */
-#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC MIIMCTL: MDCON Mask */
-
-#define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC FIFOCTL: RXFIFOTH Position */
-#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC FIFOCTL: RXFIFOTH Mask */
-
-#define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC FIFOCTL: TXFIFOTH Position */
-#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC FIFOCTL: TXFIFOTH Mask */
-
-#define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC FIFOCTL: BURSTLEN Position */
-#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC FIFOCTL: BURSTLEN Mask */
-
-#define EMAC_TXST_TXST_Pos (0) /*!< EMAC TXST: TXST Position */
-#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC TXST: TXST Mask */
-
-#define EMAC_RXST_RXST_Pos (0) /*!< EMAC RXST: RXST Position */
-#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC RXST: RXST Mask */
-
-#define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC MRFL: MRFL Position */
-#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC MRFL: MRFL Mask */
-
-#define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC INTEN: RXIEN Position */
-#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC INTEN: RXIEN Mask */
-
-#define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC INTEN: CRCEIEN Position */
-#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC INTEN: CRCEIEN Mask */
-
-#define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC INTEN: RXOVIEN Position */
-#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC INTEN: RXOVIEN Mask */
-
-#define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC INTEN: LPIEN Position */
-#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC INTEN: LPIEN Mask */
-
-#define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC INTEN: RXGDIEN Position */
-#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC INTEN: RXGDIEN Mask */
-
-#define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC INTEN: ALIEIEN Position */
-#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC INTEN: ALIEIEN Mask */
-
-#define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC INTEN: RPIEN Position */
-#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC INTEN: RPIEN Mask */
-
-#define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC INTEN: MPCOVIEN Position */
-#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC INTEN: MPCOVIEN Mask */
-
-#define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC INTEN: MFLEIEN Position */
-#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC INTEN: MFLEIEN Mask */
-
-#define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC INTEN: DENIEN Position */
-#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC INTEN: DENIEN Mask */
-
-#define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC INTEN: RDUIEN Position */
-#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC INTEN: RDUIEN Mask */
-
-#define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC INTEN: RXBEIEN Position */
-#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC INTEN: RXBEIEN Mask */
-
-#define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC INTEN: CFRIEN Position */
-#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC INTEN: CFRIEN Mask */
-
-#define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC INTEN: WOLIEN Position */
-#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC INTEN: WOLIEN Mask */
-
-#define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC INTEN: TXIEN Position */
-#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC INTEN: TXIEN Mask */
-
-#define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC INTEN: TXUDIEN Position */
-#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC INTEN: TXUDIEN Mask */
-
-#define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC INTEN: TXCPIEN Position */
-#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC INTEN: TXCPIEN Mask */
-
-#define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC INTEN: EXDEFIEN Position */
-#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC INTEN: EXDEFIEN Mask */
-
-#define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC INTEN: NCSIEN Position */
-#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC INTEN: NCSIEN Mask */
-
-#define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC INTEN: TXABTIEN Position */
-#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC INTEN: TXABTIEN Mask */
-
-#define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC INTEN: LCIEN Position */
-#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC INTEN: LCIEN Mask */
-
-#define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC INTEN: TDUIEN Position */
-#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC INTEN: TDUIEN Mask */
-
-#define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC INTEN: TXBEIEN Position */
-#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC INTEN: TXBEIEN Mask */
-
-#define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC INTEN: TSALMIEN Position */
-#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC INTEN: TSALMIEN Mask */
-
-#define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC INTSTS: RXIF Position */
-#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC INTSTS: RXIF Mask */
-
-#define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC INTSTS: CRCEIF Position */
-#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC INTSTS: CRCEIF Mask */
-
-#define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC INTSTS: RXOVIF Position */
-#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC INTSTS: RXOVIF Mask */
-
-#define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC INTSTS: LPIF Position */
-#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC INTSTS: LPIF Mask */
-
-#define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC INTSTS: RXGDIF Position */
-#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC INTSTS: RXGDIF Mask */
-
-#define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC INTSTS: ALIEIF Position */
-#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC INTSTS: ALIEIF Mask */
-
-#define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC INTSTS: RPIF Position */
-#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC INTSTS: RPIF Mask */
-
-#define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC INTSTS: MPCOVIF Position */
-#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC INTSTS: MPCOVIF Mask */
-
-#define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC INTSTS: MFLEIF Position */
-#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC INTSTS: MFLEIF Mask */
-
-#define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC INTSTS: DENIF Position */
-#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC INTSTS: DENIF Mask */
-
-#define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC INTSTS: RDUIF Position */
-#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC INTSTS: RDUIF Mask */
-
-#define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC INTSTS: RXBEIF Position */
-#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC INTSTS: RXBEIF Mask */
-
-#define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC INTSTS: CFRIF Position */
-#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC INTSTS: CFRIF Mask */
-
-#define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC INTSTS: WOLIF Position */
-#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC INTSTS: WOLIF Mask */
-
-#define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC INTSTS: TXIF Position */
-#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC INTSTS: TXIF Mask */
-
-#define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC INTSTS: TXUDIF Position */
-#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC INTSTS: TXUDIF Mask */
-
-#define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC INTSTS: TXCPIF Position */
-#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC INTSTS: TXCPIF Mask */
-
-#define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC INTSTS: EXDEFIF Position */
-#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC INTSTS: EXDEFIF Mask */
-
-#define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC INTSTS: NCSIF Position */
-#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC INTSTS: NCSIF Mask */
-
-#define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC INTSTS: TXABTIF Position */
-#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC INTSTS: TXABTIF Mask */
-
-#define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC INTSTS: LCIF Position */
-#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC INTSTS: LCIF Mask */
-
-#define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC INTSTS: TDUIF Position */
-#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC INTSTS: TDUIF Mask */
-
-#define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC INTSTS: TXBEIF Position */
-#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC INTSTS: TXBEIF Mask */
-
-#define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC INTSTS: TSALMIF Position */
-#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC INTSTS: TSALMIF Mask */
-
-#define EMAC_GENSTS_CFRIF_Pos (0) /*!< EMAC GENSTS: CFRIF Position */
-#define EMAC_GENSTS_CFRIF_Msk (0x1ul << EMAC_GENSTS_CFRIF_Pos) /*!< EMAC GENSTS: CFRIF Mask */
-
-#define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC GENSTS: RXHALT Position */
-#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC GENSTS: RXHALT Mask */
-
-#define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC GENSTS: RXFFULL Position */
-#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC GENSTS: RXFFULL Mask */
-
-#define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC GENSTS: COLCNT Position */
-#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC GENSTS: COLCNT Mask */
-
-#define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC GENSTS: DEF Position */
-#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC GENSTS: DEF Mask */
-
-#define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC GENSTS: TXPAUSED Position */
-#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC GENSTS: TXPAUSED Mask */
-
-#define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC GENSTS: SQE Position */
-#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC GENSTS: SQE Mask */
-
-#define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC GENSTS: TXHALT Position */
-#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC GENSTS: TXHALT Mask */
-
-#define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC GENSTS: RPSTS Position */
-#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC GENSTS: RPSTS Mask */
-
-#define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC MPCNT: MPCNT Position */
-#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC MPCNT: MPCNT Mask */
-
-#define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC RPCNT: RPCNT Position */
-#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC RPCNT: RPCNT Mask */
-
-#define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC FRSTS: RXFLT Position */
-#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC FRSTS: RXFLT Mask */
-
-#define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC CTXDSA: CTXDSA Position */
-#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC CTXDSA: CTXDSA Mask */
-
-#define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC CTXBSA: CTXBSA Position */
-#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC CTXBSA: CTXBSA Mask */
-
-#define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC CRXDSA: CRXDSA Position */
-#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC CRXDSA: CRXDSA Mask */
-
-#define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC CRXBSA: CRXBSA Position */
-#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC CRXBSA: CRXBSA Mask */
-
-#define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC TSCTL: TSEN Position */
-#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC TSCTL: TSEN Mask */
-
-#define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC TSCTL: TSIEN Position */
-#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC TSCTL: TSIEN Mask */
-
-#define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC TSCTL: TSMODE Position */
-#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC TSCTL: TSMODE Mask */
-
-#define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC TSCTL: TSUPDATE Position */
-#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC TSCTL: TSUPDATE Mask */
-
-#define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC TSCTL: TSALMEN Position */
-#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC TSCTL: TSALMEN Mask */
-
-#define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC TSSEC: SEC Position */
-#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC TSSEC: SEC Mask */
-
-#define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC TSSUBSEC: SUBSEC Position */
-#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC TSSUBSEC: SUBSEC Mask */
-
-#define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC TSINC: CNTINC Position */
-#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC TSINC: CNTINC Mask */
-
-#define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC TSADDEND: ADDEND Position */
-#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC TSADDEND: ADDEND Mask */
-
-#define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC UPDSEC: SEC Position */
-#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC UPDSEC: SEC Mask */
-
-#define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC UPDSUBSEC: SUBSEC Position */
-#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC UPDSUBSEC: SUBSEC Mask */
-
-#define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC ALMSEC: SEC Position */
-#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC ALMSEC: SEC Mask */
-
-#define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC ALMSUBSEC: SUBSEC Position */
-#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC ALMSUBSEC: SUBSEC Mask */
-
-/**@}*/ /* EMAC_CONST */
-/**@}*/ /* end of EMAC register group */
-
-
-/*---------------------- Enhanced PWM Generator -------------------------*/
-/**
- @addtogroup EPWM Enhanced PWM Generator(EPWM)
- Memory Mapped Structure for EPWM Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 PWM Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |MODE |PWM Mode Selection
- * | | |00 = Independent mode.
- * | | |01 = Pair/Complementary mode.
- * | | |10 = Synchronized mode.
- * | | |11 = Reserved.
- * |[2:3] |CLKDIV |PWM Clock Pre-Divider Selection
- * | | |00 = PWM clock = EPWMx_CLK.
- * | | |01 = PWM clock = EPWMx_CLK/2.
- * | | |10 = PWM clock = EPWMx_CLK/4.
- * | | |11 = PWM clock = EPWMx_CLK/16.
- * |[4] |PWMIEN |PWM Interrupt Enable Control
- * | | |0 = Disabling flag PIF to trigger PWM interrupt.
- * | | |1 = Enabling flag PIF can trigger PWM interrupt.
- * |[5] |BRKIEN |Brake0 And Brak1 Interrupt Enable Control
- * | | |0 = Disabling flags BFK0 and BFK1 to trigger PWM interrupt.
- * | | |1 = Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt.
- * |[6] |LOAD |Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Duty Registers (PWM0~3) Control
- * | | |0 = No action if written with 0.
- * | | |The value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) are not loaded to PWM counter and Comparator registers.
- * | | |1 = Hardware will update the value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) to PWM Counter and Comparator register at the time of PWM Counter matches PERIOD in edge and central aligned modes or at the time of PWM Counter down counts with underflow in central aligned mode.
- * | | |Note1: n=0-1 for PWM unit0-1.
- * | | |Note2: This bit is software write, hardware clear and always read zero.
- * |[7] |CNTEN |Start CNTEN Control
- * | | |0 = The PWM stops running.
- * | | |1 = The PWM counter starts running.
- * |[8] |INTTYPE |PWM Interrupt Type Selection
- * | | |0 = PIF will be set if PWM counter underflow.
- * | | |1 = PIF will be set if PWM counter matches EPWM_PERIOD register.
- * | | |Note: This bit is effective when PWM in central align mode only.
- * |[9] |PINV |Inverse PWM Comparator Output
- * | | |When PINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.
- * | | |0 = Not inverse PWM comparator output.
- * | | |1 = Inverse PWM comparator output.
- * |[11] |CNTCLR |Clear PWM Counter Control
- * | | |1 = Clear 16-bit PWM counter to 000H.
- * | | |Note: It is automatically cleared by hardware.
- * |[12] |CNTTYPE |PWM Aligned Type Selection
- * | | |0 = Edge-aligned type.
- * | | |1 = Centre-aligned type.
- * |[13] |GROUPEN |Group Bit
- * | | |0 = The signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 are independent.
- * | | |1 = Unify the signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 in the same phase which is controlled by EPWM_CMPDAT0.
- * |[14] |BRKP0INV |Inverse BKP0 State
- * | | |0 = The state of pin BKPx0 is passed to the negative edge detector.
- * | | |1 = The inversed state of pin BKPx0 is passed to the negative edge detector.
- * |[15] |BRKP1INV |Inverse BKP1 State
- * | | |0 = The state of pin BKPx1 is passed to the negative edge detector.
- * | | |1 = The inversed state of pin BKPx1 is passed to the negative edge detector.
- * |[16] |BRKP0EN |BKPx0 Pin Trigger Brake Function0 Enable Control
- * | | |0 = PWMx Brake Function 0 Disabled.
- * | | |1 = PWMx Brake Function 0 Enabled.
- * | | |Note: x=0~1 for PWM unit0~1.
- * |[17] |BRKP1EN |BKPx1 Pin Trigger Brake Function Enable Control
- * | | |0 = PWMx Brake Function 1 Disabled.
- * | | |1 = PWMx Brake Function 1 Enabled.
- * | | |Note: x=0~1 for PWM unit0~1.
- * |[18:19] |BRK1SEL |Brake Function 1 Source Selection
- * | | |00 = From external pin BKPx1 (x=0~1 for unit0~1).
- * | | |01 = From analog comparator 0 output (CPO0).
- * | | |10 = From analog comparator 1 output (CPO1).
- * | | |11 = From analog comparator 2 output (CPO2).
- * |[20:21] |BRK0NFSEL |Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection
- * | | |00 = Filter clock = HCLK.
- * | | |01 = Filter clock = HCLK/2.
- * | | |10 = Filter clock = HCLK/4.
- * | | |11 = Filter clock = HCLK/16.
- * |[22:23] |BRK1NFSEL |Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection
- * | | |00 = Filter clock = HCLK.
- * | | |01 =Filter clock = HCLK/2.
- * | | |10 = Filter clock = HCLK/4.
- * | | |11 = Filter clock = HCLK/16.
- * |[24] |CPO0BKEN |CPO0 Digital Output As Brake0 Source Enable Control
- * | | |1 = CPO0 as one brake source in Brake 0 Enabled.
- * | | |0 = CPO0 as one brake source in Brake 0 Disabled.
- * |[25] |CPO1BKEN |CPO1 Digital Output As Brake 0 Source Enable Control
- * | | |0 = CPO1 as one brake source in Brake 0 Disabled.
- * | | |1 = CPO1 as one brake source in Brake 0 Enabled.
- * |[26] |CPO2BKEN |CPO2 Digital Output As Brake 0 Source Enable Control
- * | | |0 = CPO2 as one brake source in Brake 0 Disabled.
- * | | |1 = CPO2 as one brake source in Brake 0 Enabled.
- * |[27] |LVDBKEN |Low-Level Detection Trigger PWM Brake Function 1 Enable Control
- * | | |0 = Brake Function 1 triggered by Low-level detection Disabled.
- * | | |1 = Brake Function 1 triggered by Low-level detection Enabled.
- * |[28] |BRK0NFDIS |PWM Brake 0 Noise Filter Disable Control
- * | | |0 = Noise filter of PWM Brake 0 Enabled.
- * | | |1 = Noise filter of PWM Brake 0 Disabled.
- * |[29] |BRK1NFDIS |PWM Brake 1 Noise Filter Disable Control
- * | | |0 = Noise filter of PWM Brake 1 Enabled.
- * | | |1 = Noise filter of PWM Brake 1 Disabled.
- * |[31] |CTRLD |Center Reload Mode Enable Control
- * | | |0 = EPWM reload duty register at the period point of PWM counter.
- * | | |1 = EPWM reload duty register at the center point of PWM counter.
- * | | |This bit only work when EPWM operation at center aligned mode.
- */
- __IO uint32_t CTL;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x04 PWM Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BRKIF0 |PWM Brake0 Flag
- * | | |0 = PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one.
- * | | |1 = When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[1] |BRKIF1 |PWM Brake1 Flag
- * | | |0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one.
- * | | |1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[2] |PIF |PWM Period Flag
- * | | |0 = PWM Counter has not up counted to the value of PERIOD or down counted with underflow.
- * | | |1 = Hardware will set this flag to high at the time of PWM Counter matches PERIOD in edge and Centre aligned modes or at the time of PWM Counter down counts with underflow in Centre aligned mode.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[4] |EIF0 |PWMx0 Edge Flag
- * | | |0 = The PWMx0 doesn't toggle.
- * | | |1 = Hardware will set this flag to high at the time of PWMx0 rising or falling.
- * | | |If EINTTYPE0 = 0, this bit is set when PWMx0 falling is detected.
- * | | |If EINTTYPE0 = 1, this bit is set when PWMx0 rising is detected.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[5] |EIF2 |PWMx2 Edge Flag
- * | | |0 = The PWMx2 doesn't toggle.
- * | | |1 = Hardware will set this flag to high at the time of PWMx2 rising or falling.
- * | | |If EINTTYPE2 = 0, this bit is set when PWMx2 falling is detected.
- * | | |If EINTTYPE2 = 1, this bit is set when PWMx2 rising is detected.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[6] |EIF4 |PWMx4 Edge Flag
- * | | |0 = The PWMx4 doesn't toggle.
- * | | |1 = Hardware will set this flag to high at the time of PWMx4 rising or falling.
- * | | |If EINTTYPE4 = 0, this bit is set when PWMx4 falling is detected.
- * | | |If EINTTYPE4 = 1, this bit is set when PWMx4 rising is detected.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[8] |BRK0LOCK |PWM Brake0 Locked
- * | | |0 = Brake 0 state is released.
- * | | |1 = When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[24] |BRK0STS |Brake 0 Status (Read Only)
- * | | |0 = PWM had been out of Brake 0 state.
- * | | |1 = PWM is in Brake 0 state.
- * |[25] |BRK1STS |Brake 1 Status (Read Only)
- * | | |0 = PWM had been out of Brake 1 state.
- * | | |1 = PWM is in Brake 1 state.
- */
- __IO uint32_t STATUS;
-
- /**
- * PERIOD
- * ===================================================================================================
- * Offset: 0x08 PWM Period Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |PERIOD |PWM Period Register
- * | | |Edge aligned:
- * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
- * | | |Centre aligned:
- * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
- */
- __IO uint32_t PERIOD;
-
- /**
- * CMPDAT0
- * ===================================================================================================
- * Offset: 0x0C EPWM_CMPDAT0 Duty Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CMP |PWM Duty Register
- * | | |Edge aligned:
- * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
- * | | |Centre aligned:
- * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
- */
- __IO uint32_t CMPDAT0;
-
- /**
- * CMPDAT2
- * ===================================================================================================
- * Offset: 0x10 EPWM_CMPDAT2 Duty Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CMP |PWM Duty Register
- * | | |Edge aligned:
- * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
- * | | |Centre aligned:
- * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
- */
- __IO uint32_t CMPDAT2;
-
- /**
- * CMPDAT4
- * ===================================================================================================
- * Offset: 0x14 EPWM_CMPDAT4 Duty Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CMP |PWM Duty Register
- * | | |Edge aligned:
- * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
- * | | |Centre aligned:
- * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
- * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
- */
- __IO uint32_t CMPDAT4;
-
- /**
- * MSKEN
- * ===================================================================================================
- * Offset: 0x18 PWM Mask Mode Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |MSKEN |PWM Mask Enable Control
- * | | |The PWM generator signal will be masked when this bit is enabled.
- * | | |The corresponding PWMn channel will be output with PMD.n data.
- * | | |0 = PWM generator signal is output to next stage.
- * | | |1 = PWM generator signal is masked and PMD.n is output to next stage.
- * | | |Note: n = 0~5.
- */
- __IO uint32_t MSKEN;
-
- /**
- * MSK
- * ===================================================================================================
- * Offset: 0x1C PWM Mask Mode Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |MSKDAT |PWM Mask Data Bit
- * | | |This data bit control the state of PWMn output pin, if the corresponding PME.n = 1.
- * | | |0 = Output logic low to PWMn.
- * | | |1 = Output logic high to PWMn.
- * | | |Note: n = 0~5.
- */
- __IO uint32_t MSK;
-
- /**
- * ASYMCMP0
- * ===================================================================================================
- * Offset: 0x20 Asymmetric EPWM_CMPDAT0 Duty Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CMP |Asymmetric PWM Duty Register
- * | | |When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
- */
- __IO uint32_t ASYMCMP0;
-
- /**
- * ASYMCMP2
- * ===================================================================================================
- * Offset: 0x24 Asymmetric EPWM_CMPDAT2 Duty Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CMP |Asymmetric PWM Duty Register
- * | | |When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
- */
- __IO uint32_t ASYMCMP2;
-
- /**
- * ASYMCMP4
- * ===================================================================================================
- * Offset: 0x28 Asymmetric EPWM_CMPDAT4 Duty Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CMP |Asymmetric PWM Duty Register
- * | | |When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
- */
- __IO uint32_t ASYMCMP4;
-
- /**
- * DTCTL
- * ===================================================================================================
- * Offset: 0x2C PWM Dead-time Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |DTCNT |Dead-Time Counter
- * | | |The dead-time can be calculated from the following formula:
- * | | |Dead-time = EPWMx_CLK period * (DTCNT.[10:0]+1).
- * |[16] |DTEN0 |Dead-Time Insertion Enable Control For PWMx Pair (PWM0, PWM1)
- * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
- * | | |If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-time insertion Disabled on the pin pair (PWM0, PWM1).
- * | | |1 = Dead-time insertion Enabled on the pin pair (PWM0, PWM1).
- * | | |Note: x=0~1 for PWM unit0~1.
- * |[17] |DTEN2 |Dead-Time Insertion Enable Control For PWMx Pair (PWM2, PWM3)
- * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
- * | | |If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-time insertion Disabled on the pin pair (PWM2, PWM3).
- * | | |1 = Dead-time insertion Enabled on the pin pair (PWM2, PWM3).
- * | | |Note: x=0~1 for PWM unit0~1.
- * |[18] |DTEN4 |Dead-Time Insertion Enable Control For PWMx Pair (PWM4, PWM5)
- * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
- * | | |If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-time insertion Disabled on the pin pair (PWM4, PWM5).
- * | | |1 = Dead-time insertion Enabled on the pin pair (PWM4, PWM5).
- * | | |Note: x=0~1 for PWM unit0~1.
- */
- __IO uint32_t DTCTL;
-
- /**
- * BRKOUT
- * ===================================================================================================
- * Offset: 0x30 PWM Brake Output
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |BRKOUT |PWM Brake Output
- * | | |When PWM Brake is asserted, the PWM0~5 output state before polarity control will follow PWM1 bit0~5 setting, respectively.
- * | | |0 = The PWMn output before polarity control is low when Brake is asserted.
- * | | |1 = The PWMn output before polarity control is high when Brake is asserted.
- * | | |Note: n = 0~5.
- */
- __IO uint32_t BRKOUT;
-
- /**
- * NPCTL
- * ===================================================================================================
- * Offset: 0x34 PWM Negative Polarity Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |NEGPOLAR |PWM Negative Polarity Control
- * | | |The register bit controls polarity/active state of real PWM output.
- * | | |0 = PWMn output is active high.
- * | | |1 = PWMn output is active low.
- * | | |Note: n = 0~5.
- */
- __IO uint32_t NPCTL;
-
- /**
- * ASYMCTL
- * ===================================================================================================
- * Offset: 0x38 Asymmetric PWM Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ASYMEN |Asymmetric PWM Enable Control
- * | | |0 = Asymmetric PWM function Disabled.
- * | | |1 = Asymmetric PWM function Enabled.
- * | | |Note: This control bit is only valid when PWM module is set in Centre-aligned mode.
- * |[8:9] |ASYMMODE0 |Asymmetric PWMx0 Reload Mode Setting
- * | | |00 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle.
- * | | |01 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle.
- * | | | 5. PWMx0 must be less than ASPWMx0
- * | | |10 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle.
- * | | | 5. PWMx0 must be greater than ASPWMx0.
- * | | |11 = Reserved.
- * | | |Note1: x=0~1 for PWM unit 0~1.
- * | | |Note2: This bit field is available only when ASYMEN=1.
- * | | |Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
- * |[16:17] |ASYMMODE2 |Asymmetric PWMx2 Reload Mode Setting
- * | | |00 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle.
- * | | |01 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register2 is reloaded with CMP (ASPWMx2[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle.
- * | | | 5. PWMx2 must be less than ASPWMx2
- * | | |10 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle.
- * | | | 5. PWMx2 must be greater than ASPWMx2.
- * | | |11 = Reserved.
- * | | |Note1: x=0~1 for PWM unit 0~1.
- * | | |Note2: This bit field is available only when ASYMEN=1.
- * | | |Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
- * |[24:25] |ASYMMODE4 |Asymmetric PWMx4 Reload Mode Setting
- * | | |00 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle.
- * | | |01 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx4[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle.
- * | | | 5. PWMx4 must be less than ASPWMx4.
- * | | |10 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
- * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle
- * | | |3.
- * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]).
- * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle.
- * | | | 5. PWMx4 must be greater than ASPWMx4.
- * | | |11= Reserved.
- * | | |Note1: x=0~1 for PWM unit 0~1.
- * | | |Note2: This bit field is available only when ASYMEN=1.
- * | | |Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
- */
- __IO uint32_t ASYMCTL;
-
- /**
- * PERIODCNT
- * ===================================================================================================
- * Offset: 0x3C PIF Compared Counter
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PERIODCNT |PIF Compared Counter
- * | | |The register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt.
- * | | |PIF will be set in every (1 + PERIODCNT[3:0]) times of PWM period or center point defined by INTTYPE when EPWM_CTL [8] occurred.
- */
- __IO uint32_t PERIODCNT;
-
- /**
- * EINTCTL
- * ===================================================================================================
- * Offset: 0x40 PWM Edge Interrupt Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EDGEIEN0 |PWMx0 Edge Interrupt Enable Control
- * | | |0 = Disabling flag EIF0 to trigger PWM interrupt.
- * | | |1 = Enabling flag EIF0 can trigger PWM interrupt.
- * |[1] |EDGEIEN2 |PWMx2 Edge Interrupt Enable Control
- * | | |0 = Disabling flag EIF2 can trigger PWM interrupt.
- * | | |1 = Enabling flag EIF2 can trigger PWM interrupt.
- * |[2] |EDGEIEN4 |PWMx4 Edge Interrupt Enable Control
- * | | |0 = Disable flag EIF4 to trigger PWM interrupt.
- * | | |1 = Enabling flag EIF4 can trigger PWM interrupt.
- * |[8] |EINTTYPE0 |PWMx0 Edge Interrupt Type
- * | | |0 = EIF0 will be set if falling edge is detected at PWMx0.
- * | | |1 = EIF0 will be set if rising edge is detected at PWMx0.
- * |[9] |EINTTYPE2 |PWMx2 Edge Interrupt Type
- * | | |0 = EIF2 will be set if falling edge is detected at PWMx2.
- * | | |1 = EIF2 will be set if rising edge is detected at PWMx2.
- * |[10] |EINTTYPE4 |PWMx4 Edge Interrupt Type
- * | | |0 = EIF4 will be set if falling edge is detected at PWMx4.
- * | | |1 = EIF4 will be set if rising edge is detected at PWMx4.
- */
- __IO uint32_t EINTCTL;
-
- /**
- * OUTEN0
- * ===================================================================================================
- * Offset: 0x44 PWM Output Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EVENOUTEN |PWM Even Ports Output Enable Control
- * | | |0 = PWM even ports output Disabled (PWM even ports at tri-state).
- * | | |1 = PWM even ports output Enabled.
- * |[1] |ODDOUTEN |PWM Odd Ports Output Enable Control
- * | | |0 = PWM odd ports output Disabled (PWM even ports at tri-state).
- * | | |1 = PWM odd ports output Enabled.
- */
- __IO uint32_t OUTEN0;
-
-} EPWM_T;
-
-/**
- @addtogroup EPWM_CONST EPWM Bit Field Definition
- Constant Definitions for EPWM Controller
-@{ */
-
-#define EPWM_CTL_MODE_Pos (0) /*!< EPWM CTL: MODE Position */
-#define EPWM_CTL_MODE_Msk (0x3ul << EPWM_CTL_MODE_Pos) /*!< EPWM CTL: MODE Mask */
-
-#define EPWM_CTL_CLKDIV_Pos (2) /*!< EPWM CTL: CLKDIV Position */
-#define EPWM_CTL_CLKDIV_Msk (0x3ul << EPWM_CTL_CLKDIV_Pos) /*!< EPWM CTL: CLKDIV Mask */
-
-#define EPWM_CTL_PWMIEN_Pos (4) /*!< EPWM CTL: PWMIEN Position */
-#define EPWM_CTL_PWMIEN_Msk (0x1ul << EPWM_CTL_PWMIEN_Pos) /*!< EPWM CTL: PWMIEN Mask */
-
-#define EPWM_CTL_BRKIEN_Pos (5) /*!< EPWM CTL: BRKIEN Position */
-#define EPWM_CTL_BRKIEN_Msk (0x1ul << EPWM_CTL_BRKIEN_Pos) /*!< EPWM CTL: BRKIEN Mask */
-
-#define EPWM_CTL_LOAD_Pos (6) /*!< EPWM CTL: LOAD Position */
-#define EPWM_CTL_LOAD_Msk (0x1ul << EPWM_CTL_LOAD_Pos) /*!< EPWM CTL: LOAD Mask */
-
-#define EPWM_CTL_CNTEN_Pos (7) /*!< EPWM CTL: CNTEN Position */
-#define EPWM_CTL_CNTEN_Msk (0x1ul << EPWM_CTL_CNTEN_Pos) /*!< EPWM CTL: CNTEN Mask */
-
-#define EPWM_CTL_INTTYPE_Pos (8) /*!< EPWM CTL: INTTYPE Position */
-#define EPWM_CTL_INTTYPE_Msk (0x1ul << EPWM_CTL_INTTYPE_Pos) /*!< EPWM CTL: INTTYPE Mask */
-
-#define EPWM_CTL_PINV_Pos (9) /*!< EPWM CTL: PINV Position */
-#define EPWM_CTL_PINV_Msk (0x1ul << EPWM_CTL_PINV_Pos) /*!< EPWM CTL: PINV Mask */
-
-#define EPWM_CTL_CNTCLR_Pos (11) /*!< EPWM CTL: CNTCLR Position */
-#define EPWM_CTL_CNTCLR_Msk (0x1ul << EPWM_CTL_CNTCLR_Pos) /*!< EPWM CTL: CNTCLR Mask */
-
-#define EPWM_CTL_CNTTYPE_Pos (12) /*!< EPWM CTL: CNTTYPE Position */
-#define EPWM_CTL_CNTTYPE_Msk (0x1ul << EPWM_CTL_CNTTYPE_Pos) /*!< EPWM CTL: CNTTYPE Mask */
-
-#define EPWM_CTL_GROUPEN_Pos (13) /*!< EPWM CTL: GROUPEN Position */
-#define EPWM_CTL_GROUPEN_Msk (0x1ul << EPWM_CTL_GROUPEN_Pos) /*!< EPWM CTL: GROUPEN Mask */
-
-#define EPWM_CTL_BRKP0INV_Pos (14) /*!< EPWM CTL: BRKP0INV Position */
-#define EPWM_CTL_BRKP0INV_Msk (0x1ul << EPWM_CTL_BRKP0INV_Pos) /*!< EPWM CTL: BRKP0INV Mask */
-
-#define EPWM_CTL_BRKP1INV_Pos (15) /*!< EPWM CTL: BRKP1INV Position */
-#define EPWM_CTL_BRKP1INV_Msk (0x1ul << EPWM_CTL_BRKP1INV_Pos) /*!< EPWM CTL: BRKP1INV Mask */
-
-#define EPWM_CTL_BRKP0EN_Pos (16) /*!< EPWM CTL: BRKP0EN Position */
-#define EPWM_CTL_BRKP0EN_Msk (0x1ul << EPWM_CTL_BRKP0EN_Pos) /*!< EPWM CTL: BRKP0EN Mask */
-
-#define EPWM_CTL_BRKP1EN_Pos (17) /*!< EPWM CTL: BRKP1EN Position */
-#define EPWM_CTL_BRKP1EN_Msk (0x1ul << EPWM_CTL_BRKP1EN_Pos) /*!< EPWM CTL: BRKP1EN Mask */
-
-#define EPWM_CTL_BRK1SEL_Pos (18) /*!< EPWM CTL: BRK1SEL Position */
-#define EPWM_CTL_BRK1SEL_Msk (0x3ul << EPWM_CTL_BRK1SEL_Pos) /*!< EPWM CTL: BRK1SEL Mask */
-
-#define EPWM_CTL_BRK0NFSEL_Pos (20) /*!< EPWM CTL: BRK0NFSEL Position */
-#define EPWM_CTL_BRK0NFSEL_Msk (0x3ul << EPWM_CTL_BRK0NFSEL_Pos) /*!< EPWM CTL: BRK0NFSEL Mask */
-
-#define EPWM_CTL_BRK1NFSEL_Pos (22) /*!< EPWM CTL: BRK1NFSEL Position */
-#define EPWM_CTL_BRK1NFSEL_Msk (0x3ul << EPWM_CTL_BRK1NFSEL_Pos) /*!< EPWM CTL: BRK1NFSEL Mask */
-
-#define EPWM_CTL_CPO0BKEN_Pos (24) /*!< EPWM CTL: CPO0BKEN Position */
-#define EPWM_CTL_CPO0BKEN_Msk (0x1ul << EPWM_CTL_CPO0BKEN_Pos) /*!< EPWM CTL: CPO0BKEN Mask */
-
-#define EPWM_CTL_CPO1BKEN_Pos (25) /*!< EPWM CTL: CPO1BKEN Position */
-#define EPWM_CTL_CPO1BKEN_Msk (0x1ul << EPWM_CTL_CPO1BKEN_Pos) /*!< EPWM CTL: CPO1BKEN Mask */
-
-#define EPWM_CTL_CPO2BKEN_Pos (26) /*!< EPWM CTL: CPO2BKEN Position */
-#define EPWM_CTL_CPO2BKEN_Msk (0x1ul << EPWM_CTL_CPO2BKEN_Pos) /*!< EPWM CTL: CPO2BKEN Mask */
-
-#define EPWM_CTL_LVDBKEN_Pos (27) /*!< EPWM CTL: LVDBKEN Position */
-#define EPWM_CTL_LVDBKEN_Msk (0x1ul << EPWM_CTL_LVDBKEN_Pos) /*!< EPWM CTL: LVDBKEN Mask */
-
-#define EPWM_CTL_BRK0NFDIS_Pos (28) /*!< EPWM CTL: BRK0NFDIS Position */
-#define EPWM_CTL_BRK0NFDIS_Msk (0x1ul << EPWM_CTL_BRK0NFDIS_Pos) /*!< EPWM CTL: BRK0NFDIS Mask */
-
-#define EPWM_CTL_BRK1NFDIS_Pos (29) /*!< EPWM CTL: BRK1NFDIS Position */
-#define EPWM_CTL_BRK1NFDIS_Msk (0x1ul << EPWM_CTL_BRK1NFDIS_Pos) /*!< EPWM CTL: BRK1NFDIS Mask */
-
-#define EPWM_CTL_CTRLD_Pos (31) /*!< EPWM CTL: CTRLD Position */
-#define EPWM_CTL_CTRLD_Msk (0x1ul << EPWM_CTL_CTRLD_Pos) /*!< EPWM CTL: CTRLD Mask */
-
-#define EPWM_STATUS_BRKIF0_Pos (0) /*!< EPWM STATUS: BRKIF0 Position */
-#define EPWM_STATUS_BRKIF0_Msk (0x1ul << EPWM_STATUS_BRKIF0_Pos) /*!< EPWM STATUS: BRKIF0 Mask */
-
-#define EPWM_STATUS_BRKIF1_Pos (1) /*!< EPWM STATUS: BRKIF1 Position */
-#define EPWM_STATUS_BRKIF1_Msk (0x1ul << EPWM_STATUS_BRKIF1_Pos) /*!< EPWM STATUS: BRKIF1 Mask */
-
-#define EPWM_STATUS_PIF_Pos (2) /*!< EPWM STATUS: PIF Position */
-#define EPWM_STATUS_PIF_Msk (0x1ul << EPWM_STATUS_PIF_Pos) /*!< EPWM STATUS: PIF Mask */
-
-#define EPWM_STATUS_EIF0_Pos (4) /*!< EPWM STATUS: EIF0 Position */
-#define EPWM_STATUS_EIF0_Msk (0x1ul << EPWM_STATUS_EIF0_Pos) /*!< EPWM STATUS: EIF0 Mask */
-
-#define EPWM_STATUS_EIF2_Pos (5) /*!< EPWM STATUS: EIF2 Position */
-#define EPWM_STATUS_EIF2_Msk (0x1ul << EPWM_STATUS_EIF2_Pos) /*!< EPWM STATUS: EIF2 Mask */
-
-#define EPWM_STATUS_EIF4_Pos (6) /*!< EPWM STATUS: EIF4 Position */
-#define EPWM_STATUS_EIF4_Msk (0x1ul << EPWM_STATUS_EIF4_Pos) /*!< EPWM STATUS: EIF4 Mask */
-
-#define EPWM_STATUS_BRK0LOCK_Pos (8) /*!< EPWM STATUS: BRK0LOCK Position */
-#define EPWM_STATUS_BRK0LOCK_Msk (0x1ul << EPWM_STATUS_BRK0LOCK_Pos) /*!< EPWM STATUS: BRK0LOCK Mask */
-
-#define EPWM_STATUS_BRK0STS_Pos (24) /*!< EPWM STATUS: BRK0STS Position */
-#define EPWM_STATUS_BRK0STS_Msk (0x1ul << EPWM_STATUS_BRK0STS_Pos) /*!< EPWM STATUS: BRK0STS Mask */
-
-#define EPWM_STATUS_BRK1STS_Pos (25) /*!< EPWM STATUS: BRK1STS Position */
-#define EPWM_STATUS_BRK1STS_Msk (0x1ul << EPWM_STATUS_BRK1STS_Pos) /*!< EPWM STATUS: BRK1STS Mask */
-
-#define EPWM_PERIOD_PERIOD_Pos (0) /*!< EPWM PERIOD: PERIOD Position */
-#define EPWM_PERIOD_PERIOD_Msk (0xfffful << EPWM_PERIOD_PERIOD_Pos) /*!< EPWM PERIOD: PERIOD Mask */
-
-#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM CMPDAT0: CMP Position */
-#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM CMPDAT0: CMP Mask */
-
-#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM CMPDAT2: CMP Position */
-#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM CMPDAT2: CMP Mask */
-
-#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM CMPDAT4: CMP Position */
-#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM CMPDAT4: CMP Mask */
-
-#define EPWM_MSKEN_MSKEN_Pos (0) /*!< EPWM MSKEN: MSKEN Position */
-#define EPWM_MSKEN_MSKEN_Msk (0x3ful << EPWM_MSKEN_MSKEN_Pos) /*!< EPWM MSKEN: MSKEN Mask */
-
-#define EPWM_MSK_MSKDAT_Pos (0) /*!< EPWM MSK: MSKDAT Position */
-#define EPWM_MSK_MSKDAT_Msk (0x3ful << EPWM_MSK_MSKDAT_Pos) /*!< EPWM MSK: MSKDAT Mask */
-
-#define EPWM_ASYMCMP0_CMP_Pos (0) /*!< EPWM ASYMCMP0: CMP Position */
-#define EPWM_ASYMCMP0_CMP_Msk (0xfffful << EPWM_ASYMCMP0_CMP_Pos) /*!< EPWM ASYMCMP0: CMP Mask */
-
-#define EPWM_ASYMCMP2_CMP_Pos (0) /*!< EPWM ASYMCMP2: CMP Position */
-#define EPWM_ASYMCMP2_CMP_Msk (0xfffful << EPWM_ASYMCMP2_CMP_Pos) /*!< EPWM ASYMCMP2: CMP Mask */
-
-#define EPWM_ASYMCMP4_CMP_Pos (0) /*!< EPWM ASYMCMP4: CMP Position */
-#define EPWM_ASYMCMP4_CMP_Msk (0xfffful << EPWM_ASYMCMP4_CMP_Pos) /*!< EPWM ASYMCMP4: CMP Mask */
-
-#define EPWM_DTCTL_DTCNT_Pos (0) /*!< EPWM DTCTL: DTCNT Position */
-#define EPWM_DTCTL_DTCNT_Msk (0x7fful << EPWM_DTCTL_DTCNT_Pos) /*!< EPWM DTCTL: DTCNT Mask */
-
-#define EPWM_DTCTL_DTEN0_Pos (16) /*!< EPWM DTCTL: DTEN0 Position */
-#define EPWM_DTCTL_DTEN0_Msk (0x1ul << EPWM_DTCTL_DTEN0_Pos) /*!< EPWM DTCTL: DTEN0 Mask */
-
-#define EPWM_DTCTL_DTEN2_Pos (17) /*!< EPWM DTCTL: DTEN2 Position */
-#define EPWM_DTCTL_DTEN2_Msk (0x1ul << EPWM_DTCTL_DTEN2_Pos) /*!< EPWM DTCTL: DTEN2 Mask */
-
-#define EPWM_DTCTL_DTEN4_Pos (18) /*!< EPWM DTCTL: DTEN4 Position */
-#define EPWM_DTCTL_DTEN4_Msk (0x1ul << EPWM_DTCTL_DTEN4_Pos) /*!< EPWM DTCTL: DTEN4 Mask */
-
-#define EPWM_BRKOUT_BRKOUT_Pos (0) /*!< EPWM BRKOUT: BRKOUT Position */
-#define EPWM_BRKOUT_BRKOUT_Msk (0x3ful << EPWM_BRKOUT_BRKOUT_Pos) /*!< EPWM BRKOUT: BRKOUT Mask */
-
-#define EPWM_NPCTL_NEGPOLAR_Pos (0) /*!< EPWM NPCTL: NEGPOLAR Position */
-#define EPWM_NPCTL_NEGPOLAR_Msk (0x3ful << EPWM_NPCTL_NEGPOLAR_Pos) /*!< EPWM NPCTL: NEGPOLAR Mask */
-
-#define EPWM_ASYMCTL_ASYMEN_Pos (0) /*!< EPWM ASYMCTL: ASYMEN Position */
-#define EPWM_ASYMCTL_ASYMEN_Msk (0x1ul << EPWM_ASYMCTL_ASYMEN_Pos) /*!< EPWM ASYMCTL: ASYMEN Mask */
-
-#define EPWM_ASYMCTL_ASYMMODE0_Pos (8) /*!< EPWM ASYMCTL: ASYMMODE0 Position */
-#define EPWM_ASYMCTL_ASYMMODE0_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE0_Pos) /*!< EPWM ASYMCTL: ASYMMODE0 Mask */
-
-#define EPWM_ASYMCTL_ASYMMODE2_Pos (16) /*!< EPWM ASYMCTL: ASYMMODE2 Position */
-#define EPWM_ASYMCTL_ASYMMODE2_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE2_Pos) /*!< EPWM ASYMCTL: ASYMMODE2 Mask */
-
-#define EPWM_ASYMCTL_ASYMMODE4_Pos (24) /*!< EPWM ASYMCTL: ASYMMODE4 Position */
-#define EPWM_ASYMCTL_ASYMMODE4_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE4_Pos) /*!< EPWM ASYMCTL: ASYMMODE4 Mask */
-
-#define EPWM_PERIODCNT_PERIODCNT_Pos (0) /*!< EPWM PERIODCNT: PERIODCNT Position */
-#define EPWM_PERIODCNT_PERIODCNT_Msk (0xful << EPWM_PERIODCNT_PERIODCNT_Pos) /*!< EPWM PERIODCNT: PERIODCNT Mask */
-
-#define EPWM_EINTCTL_EDGEIEN0_Pos (0) /*!< EPWM EINTCTL: EDGEIEN0 Position */
-#define EPWM_EINTCTL_EDGEIEN0_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN0_Pos) /*!< EPWM EINTCTL: EDGEIEN0 Mask */
-
-#define EPWM_EINTCTL_EDGEIEN2_Pos (1) /*!< EPWM EINTCTL: EDGEIEN2 Position */
-#define EPWM_EINTCTL_EDGEIEN2_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN2_Pos) /*!< EPWM EINTCTL: EDGEIEN2 Mask */
-
-#define EPWM_EINTCTL_EDGEIEN4_Pos (2) /*!< EPWM EINTCTL: EDGEIEN4 Position */
-#define EPWM_EINTCTL_EDGEIEN4_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN4_Pos) /*!< EPWM EINTCTL: EDGEIEN4 Mask */
-
-#define EPWM_EINTCTL_EINTTYPE0_Pos (8) /*!< EPWM EINTCTL: EINTTYPE0 Position */
-#define EPWM_EINTCTL_EINTTYPE0_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE0_Pos) /*!< EPWM EINTCTL: EINTTYPE0 Mask */
-
-#define EPWM_EINTCTL_EINTTYPE2_Pos (9) /*!< EPWM EINTCTL: EINTTYPE2 Position */
-#define EPWM_EINTCTL_EINTTYPE2_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE2_Pos) /*!< EPWM EINTCTL: EINTTYPE2 Mask */
-
-#define EPWM_EINTCTL_EINTTYPE4_Pos (10) /*!< EPWM EINTCTL: EINTTYPE4 Position */
-#define EPWM_EINTCTL_EINTTYPE4_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE4_Pos) /*!< EPWM EINTCTL: EINTTYPE4 Mask */
-
-#define EPWM_OUTEN0_EVENOUTEN_Pos (0) /*!< EPWM OUTEN0: EVENOUTEN Position */
-#define EPWM_OUTEN0_EVENOUTEN_Msk (0x1ul << EPWM_OUTEN0_EVENOUTEN_Pos) /*!< EPWM OUTEN0: EVENOUTEN Mask */
-
-#define EPWM_OUTEN0_ODDOUTEN_Pos (1) /*!< EPWM OUTEN0: ODDOUTEN Position */
-#define EPWM_OUTEN0_ODDOUTEN_Msk (0x1ul << EPWM_OUTEN0_ODDOUTEN_Pos) /*!< EPWM OUTEN0: ODDOUTEN Mask */
-
-/**@}*/ /* EPWM_CONST */
-/**@}*/ /* end of EPWM register group */
-
-
-/*---------------------- Flash Memory Controller -------------------------*/
-/**
- @addtogroup FMC Flash Memory Controller(FMC)
- Memory Mapped Structure for FMC Controller
-@{ */
-
-typedef struct {
- /**
- * ISPCTL
- * ===================================================================================================
- * Offset: 0x00 ISP Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ISPEN |ISP Enable Control (Write Protect)
- * | | |ISP function enable bit. Set this bit to enable ISP function.
- * | | |0 = ISP function Disabled.
- * | | |1 = ISP function Enabled.
- * |[1] |BS |Boot Select (Write Protect)
- * | | |Set/clear this bit to select next booting from LDROM/APROM, respectively.
- * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
- * | | |This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
- * | | |0 = Boot from APROM.
- * | | |1 = Boot from LDROM.
- * |[3] |APUEN |APROM Update Enable Control (Write Protect)
- * | | |0 = APROM cannot be updated when the chip runs in APROM.
- * | | |1 = APROM can be updated when the chip runs in APROM.
- * |[4] |CFGUEN |Config-Bits Update By ISP (Write Protect) Enable Control
- * | | |0 = ISP Disabled to update config-bits.
- * | | |1 = ISP Enabled to update config-bits at KEYMATCH flag active (bit7 of ISPSTS).
- * | | |Note: This bit is fixed to 0 in Secure mode.
- * |[5] |LDUEN |LDROM Update Enable Control (Write Protect)
- * | | |LDROM update enable bit.
- * | | |0 = LDROM cannot be updated.
- * | | |1 = LDROM can be updated at KEYMATCH flag active (bit7 of ISPSTS).
- * | | |Note: This bit is fixed to 0 in Secure mode.
- * |[6] |ISPFF |ISP Fail Flag (Write Protect)
- * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
- * | | |(1) APROM writes to itself if APUEN is set to 0.
- * | | |(2) LDROM writes to itself if LDUEN is set to 0.
- * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
- * | | |(4) Destination address is illegal, such as over an available range.
- * | | |Note: This bit needs to be cleared by writing 1 to it.
- */
- __IO uint32_t ISPCTL;
-
- /**
- * ISPADDR
- * ===================================================================================================
- * Offset: 0x04 ISP Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ISPADR |ISP Address
- * | | |The NUC442/NUC472 series is equipped with an embedded flash and supports word program only.
- * | | |ISPADR[1:0] must be kept 00b for ISP operation.
- */
- __IO uint32_t ISPADDR;
-
- /**
- * ISPDAT
- * ===================================================================================================
- * Offset: 0x08 ISP Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ISPDAT |ISP Data
- * | | |Write data to this register before ISP program operation.
- * | | |Read data from this register after ISP read operation.
- */
- __IO uint32_t ISPDAT;
-
- /**
- * ISPCMD
- * ===================================================================================================
- * Offset: 0x0C ISP Command Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |CMD |ISP Command
- * | | |Please check the table below for ISP commands.
- */
- __IO uint32_t ISPCMD;
-
- /**
- * ISPTRG
- * ===================================================================================================
- * Offset: 0x10 ISP Trigger Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ISPGO |ISP Start Trigger
- * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
- * | | |0 = ISP operation is finished.
- * | | |1 = ISP is progressed.
- * | | |This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- */
- __IO uint32_t ISPTRG;
-
- /**
- * DFBA
- * ===================================================================================================
- * Offset: 0x14 Data Flash Base Address
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DFBA |Data Flash Base Address
- * | | |This register indicates data flash start address. It is a read only register.
- * | | |The data flash is shared with APROM and data flash size is defined by user configuration and the content of this register is loaded from Config1.
- */
- __I uint32_t DFBA;
-
- /**
- * FTCTL
- * ===================================================================================================
- * Offset: 0x18 Flash Access Time Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:6] |FOM |Frequency Optimization Mode (Write Protect)
- * | | |When chip operation frequency is lower, chip can work more efficiently by setting FOM bits
- * | | |FOM[2:0]
- * | | |Optimized Frequency (OF)
- * | | |001
- * | | |0 MHz < OF <= 24 MHz
- * | | |010
- * | | |24 MHz < OF <= 48 MHz
- * | | |011
- * | | |48 MHz < OF <= 72 MHz
- * | | |others
- * | | |Reserved
- */
- __IO uint32_t FTCTL;
- uint32_t RESERVE0[9];
-
- /**
- * ISPSTS
- * ===================================================================================================
- * Offset: 0x40 Flash Access Time Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ISPBUSY |ISP busy flag
- * | | |0 = ISP operation is finished.
- * | | |1 = ISP is progressed.
- * |[2:1] |CBS |Chip boot selection mode
- * | | |This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
- * |[6] |ISPFF |ISP Fail Flag (Write Protect)
- * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
- * | | |(1) APROM writes to itself if APUEN is set to 0.
- * | | |(2) LDROM writes to itself if LDUEN is set to 0.
- * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
- * | | |(4) Destination address is illegal, such as over an available range.
- * | | |Note: This bit needs to be cleared by writing 1 to it.
- * |[20:9] |VECMAP |Vector Page Mapping Address (Read Only)
- * | | |The current flash address space 0x0000_0000~0x0000_07FF is mapping to
- * | | |address {VECMAP[11:2], 11¡¦h000} ~ {VECMAP[11:2], 11¡¦h7FF}
- * | | |VECMAP[1:0] is needed to set 0.
- * |[26] |CFGCRCF |User-Configuration CRC Check Flag (Read Only)
- * | | |This bit is set by hardware when detecting CONFIG CRC checksum is error
- * | | |0 = CONFIG CRC checksum is OK.
- * | | |1 = CONFIG CRC checksum error and force chip into LOCK mode.
- */
- __IO uint32_t ISPSTS;
-
- /**
- * FBWP
- * ===================================================================================================
- * Offset: 0x44 Flash Block Write Protect Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |BWP |Flash Block Write Protect Control
- * | | |If BWP.N bit is set to 0, the APROM memory relative region cannot program and erase by ISP. (N=0~31).
- * | | |Bit Block Protect Region
- * | | |BWP0 0x00_0000 ~ 0x00_3FFF
- * | | |BWP1 0x00_4000 ~ 0x00_7FFF
- * | | |BWP2 0x00_8000 ~ 0x00_BFFF
- * | | |BWP3 0x00_C000 ~ 0x00_FFFF
- * | | |BWP4 0x01_0000 ~ 0x01_3FFF
- * | | |BWP5 0x01_4000 ~ 0x01_7FFF
- * | | |BWP6 0x01_8000 ~ 0x01_BFFF
- * | | |BWP7 0x01_C000 ~ 0x01_FFFF
- * | | |BWP8 0x02_0000 ~ 0x02_3FFF
- * | | |BWP9 0x02_4000 ~ 0x02_7FFF
- * | | |BWP10 0x02_8000 ~ 0x02_BFFF
- * | | |BWP11 0x02_C000 ~ 0x02_FFFF
- * | | |BWP12 0x03_0000 ~ 0x03_3FFF
- * | | |BWP13 0x03_4000 ~ 0x03_7FFF
- * | | |BWP14 0x03_8000 ~ 0x03_BFFF
- * | | |BWP15 0x03_C000 ~ 0x03_FFFF
- * | | |BWP16 0x04_0000 ~ 0x04_3FFF
- * | | |BWP17 0x04_4000 ~ 0x04_7FFF
- * | | |BWP18 0x04_8000 ~ 0x04_BFFF
- * | | |BWP19 0x04_C000 ~ 0x04_FFFF
- * | | |BWP20 0x05_0000 ~ 0x05_3FFF
- * | | |BWP21 0x05_4000 ~ 0x05_7FFF
- * | | |BWP22 0x05_8000 ~ 0x05_BFFF
- * | | |BWP23 0x05_C000 ~ 0x05_FFFF
- * | | |BWP24 0x06_0000 ~ 0x06_3FFF
- * | | |BWP25 0x06_4000 ~ 0x06_7FFF
- * | | |BWP26 0x06_8000 ~ 0x06_BFFF
- * | | |BWP27 0x06_C000 ~ 0x06_FFFF
- * | | |BWP28 0x07_0000 ~ 0x07_3FFF
- * | | |BWP29 0x07_4000 ~ 0x07_7FFF
- * | | |BWP30 0x07_8000 ~ 0x07_BFFF
- * | | |BWP31 0x07_C000 ~ 0x07_FFFF
- * | | |This register is loaded from Config2 when chip is power on.
- * | | |It is read only, except the correct Super Key is matched.
- * | | |This register is also a protected bit which means programming this bit needs to write "59h", "16h", "88h" to address GCR_BA+0x100 to disable register protection.
- * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
- */
- __IO uint32_t FBWP;
- uint32_t RESERVE1[14];
-
- /**
- * MPDAT0
- * ===================================================================================================
- * Offset: 0x80 ISP Data 0 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ISPDAT0 |ISP Data 0
- * | | |This register is the first 32-bit data for 32b/64b/multi-word program,
- * | | |and it is also the mirror of FMC_ISPDAT register, both registers keep the same data.
- */
- __IO uint32_t MPDAT0;
-
- /**
- * MPDAT1
- * ===================================================================================================
- * Offset: 0x84 ISP Data 1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ISPDAT1 |ISP Data 1
- * | | |This register is the second 32-bit data for 32b/64b/multi-word program.
- */
- __IO uint32_t MPDAT1;
-
- /**
- * MPDAT2
- * ===================================================================================================
- * Offset: 0x88 ISP Data 2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ISPDAT2 |ISP Data 2
- * | | |This register is the third 32-bit data for 32b/64b/multi-word program.
- */
- __IO uint32_t MPDAT2;
-
- /**
- * MPDAT3
- * ===================================================================================================
- * Offset: 0x8C ISP Data 1 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ISPDAT3 |ISP Data 3
- * | | |This register is the fourth 32-bit data for 32b/64b/multi-word program.
- */
- __IO uint32_t MPDAT3;
-
- uint32_t RESERVE2[12];
-
- /**
- * MPSTS
- * ===================================================================================================
- * Offset: 0xC0 ISP Multi-Word Program Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |MPBUSY |ISP Multi-Word Program Busy Flag (Read Only)
- * | | |0 = ISP Multi-Word Program operation is aborted or finished.
- * | | |1 = ISP Multi-Word Program operation is progressed.
- * |[2] |ISPFF |ISP Fail Flag (Read Only)
- * | | |This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
- * |[4] |D0 |ISP DATA 0 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0
- * | | |when the FMC_MPDAT0 is programmed to flash complete.
- * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT0 register has been written, and not programmed to flash yet.
- * |[5] |D1 |ISP DATA 1 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0
- * | | |when the FMC_MPDAT1 is programmed to flash complete.
- * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT1 register has been written, and not programmed to flash yet.
- * |[6] |D2 |ISP DATA 2 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0
- * | | |when the FMC_MPDAT2 is programmed to flash complete.
- * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT2 register has been written, and not programmed to flash yet.
- * |[7] |D3 |ISP DATA 3 Flag (Read Only)
- * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0
- * | | |when the FMC_MPDAT3 is programmed to flash complete.
- * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
- * | | |1 = FMC_MPDAT3 register has been written, and not programmed to flash yet.
- */
- __IO uint32_t MPSTS;
-
- /**
- * MPADDR
- * ===================================================================================================
- * Offset: 0xC4 ISP Multi-Word Program Address Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |MPADDR |ISP Multi-Word Program Address Status
- * | | |MPADDR is the address of ISP Multi-Word Program operation when
- * | | |MPBUSY flag is 1. MPADDR will keep the final address when
- * | | |Multi-Word Program is aborted or finished.
- */
- __IO uint32_t MPADDR;
-
-} FMC_T;
-
-
-/**
- @addtogroup FMC_CONST FMC Bit Field Definition
- Constant Definitions for FMC Controller
-@{ */
-
-#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC ISPCTL: ISPEN Position */
-#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC ISPCTL: ISPEN Mask */
-
-#define FMC_ISPCTL_BS_Pos (1) /*!< FMC ISPCTL: BS Position */
-#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC ISPCTL: BS Mask */
-
-#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC ISPCTL: APUEN Position */
-#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC ISPCTL: APUEN Mask */
-
-#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC ISPCTL: CFGUEN Position */
-#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC ISPCTL: CFGUEN Mask */
-
-#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC ISPCTL: LDUEN Position */
-#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC ISPCTL: LDUEN Mask */
-
-#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC ISPCTL: ISPFF Position */
-#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC ISPCTL: ISPFF Mask */
-
-#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC ISPADDR: ISPADDR Position */
-#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC ISPADDR: ISPADDR Mask */
-
-#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC ISPDAT: ISPDAT Position */
-#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC ISPDAT: ISPDAT Mask */
-
-#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC ISPCMD: CMD Position */
-#define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos) /*!< FMC ISPCMD: CMD Mask */
-
-#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC ISPTRG: ISPGO Position */
-#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC ISPTRG: ISPGO Mask */
-
-#define FMC_DFBA_DFBA_Pos (0) /*!< FMC DFBA: DFBA Position */
-#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC DFBA: DFBA Mask */
-
-#define FMC_FTCTL_FOM_Pos (4) /*!< FMC FTCTL: FOM Position */
-#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC FTCTL: FOM Mask */
-
-#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC ISPSTS: ISPBUSY Position */
-#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC ISPSTS: ISPBUSY Mask */
-
-#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC ISPSTS: CBS Position */
-#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC ISPSTS: CBS Mask */
-
-#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC ISPSTS: ISPFF Position */
-#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC ISPSTS: ISPFF Mask */
-
-#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC ISPSTS: VECMAP Position */
-#define FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC ISPSTS: VECMAP Mask */
-
-#define FMC_ISPSTS_CFGCRCF_Pos (26) /*!< FMC ISPSTS: CFGCRCF Position */
-#define FMC_ISPSTS_CFGCRCF_Msk (0x1ul << FMC_ISPSTS_CFGCRCF_Pos) /*!< FMC ISPSTS: CFGCRCF Mask */
-
-#define FMC_FBWP_BWP_Pos (0) /*!< FMC FBWP: BWP Position */
-#define FMC_FBWP_BWP_Msk (0xfffffffful << FMC_FBWP_BWP_Pos) /*!< FMC FBWP: BWP Mask */
-
-#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC MPDAT0: ISPDAT0 Position */
-#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC MPDAT0: ISPDAT0 Mask */
-
-#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC MPDAT1: ISPDAT1 Position */
-#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC MPDAT1: ISPDAT1 Mask */
-
-#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC MPDAT2: ISPDAT2 Position */
-#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC MPDAT2: ISPDAT2 Mask */
-
-#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC MPDAT3: ISPDAT3 Position */
-#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC MPDAT3: ISPDAT3 Mask */
-
-#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC MPSTS: WMPBUSY Position */
-#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC MPSTS: MPBUSY Mask */
-
-#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC MPSTS: ISPFF Position */
-#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC MPSTS: ISPFF Mask */
-
-#define FMC_MPSTS_D0_Pos (4) /*!< FMC MPSTS: D0 Position */
-#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC MPSTS: D0 Mask */
-
-#define FMC_MPSTS_D1_Pos (5) /*!< FMC MPSTS: D1 Position */
-#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC MPSTS: D1 Mask */
-
-#define FMC_MPSTS_D2_Pos (6) /*!< FMC MPSTS: D2 Position */
-#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC MPSTS: D2 Mask */
-
-#define FMC_MPSTS_D3_Pos (7) /*!< FMC MPSTS: D3 Position */
-#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC MPSTS: D3 Mask */
-
-#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC MPADDR: MPADDR Position */
-#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC MPADDR: MPADDR Mask */
-
-/**@}*/ /* FMC_CONST */
-/**@}*/ /* end of FMC register group */
-
-
-/*---------------------- General Purpose Input/Output Controller -------------------------*/
-/**
- @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
- Memory Mapped Structure for GPIO Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * Px_MODE
- * ===================================================================================================
- * Offset: 0x00 Px I/O Mode Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |MODE0 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[2:3] |MODE1 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[4:5] |MODE2 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[6:7] |MODE3 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[8:9] |MODE4 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[10:11] |MODE5 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[12:13] |MODE6 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[14:15] |MODE7 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[16:17] |MODE8 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[18:19] |MODE9 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[20:21] |MODE10 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[22:23] |MODE11 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[24:25] |MODE12 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[26:27] |MODE13 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[28:29] |MODE14 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- * |[30:31] |MODE15 |Port N Bit M I/O Mode Control
- * | | |Determine the I/O mode of port n bit m.
- * | | |00 = INPUT only mode.
- * | | |01 = OUTPUT mode.
- * | | |10 = Open-drain mode.
- * | | |11 = Quasi-bidirectional mode.
- * | | |Reset value:
- * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
- * | | |0x0000_00000 when ( cfg_io =1'b1).
- */
- __IO uint32_t MODE;
-
- /**
- * Px_DINOFF
- * ===================================================================================================
- * Offset: 0x04 Px Digital Input Path Disable Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16] |DINOFF0 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[17] |DINOFF1 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[18] |DINOFF2 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[19] |DINOFF3 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[20] |DINOFF4 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[21] |DINOFF5 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[22] |DINOFF6 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[23] |DINOFF7 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[24] |DINOFF8 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[25] |DINOFF9 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[26] |DINOFF10 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[27] |DINOFF11 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[28] |DINOFF12 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[29] |DINOFF13 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[30] |DINOFF14 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- * |[31] |DINOFF15 |Port N Bit M Off Digital Input Path
- * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
- * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
- * | | |0 = Digital input path Enabled.
- * | | |1 = Digital input path Disabled (Digital input is tied to low).
- */
- __IO uint32_t DINOFF;
-
- /**
- * Px_DOUT
- * ===================================================================================================
- * Offset: 0x08 Px Data Output Value
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DOUT0 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[1] |DOUT1 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[2] |DOUT2 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[3] |DOUT3 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[4] |DOUT4 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[5] |DOUT5 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[6] |DOUT6 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[7] |DOUT7 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[8] |DOUT8 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[9] |DOUT9 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[10] |DOUT10 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[11] |DOUT11 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[12] |DOUT12 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[13] |DOUT13 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[14] |DOUT14 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- * |[15] |DOUT15 |Port N Bit M Output
- * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
- * | | |0 = Drive port n bit m high low.
- * | | |1 = Drive port n bit m high level.
- */
- __IO uint32_t DOUT;
-
- /**
- * Px_DATMSK
- * ===================================================================================================
- * Offset: 0x0C Px Data Output Write Mask
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DATMSK0 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[1] |DATMSK1 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[2] |DATMSK2 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[3] |DATMSK3 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[4] |DATMSK4 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[5] |DATMSK5 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[6] |DATMSK6 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[7] |DATMSK7 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[8] |DATMSK8 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[9] |DATMSK9 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[10] |DATMSK10 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[11] |DATMSK11 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[12] |DATMSK12 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[13] |DATMSK13 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[14] |DATMSK14 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- * |[15] |DATMSK15 |Port N Bit M Data Output Write Mask
- * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
- * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
- * | | |The write to port pin latch is masked.
- * | | |0 = Px_DOUT[m] bit writing is valid.
- * | | |1 = Px_DOUT[m] bit writing is ignored.
- */
- __IO uint32_t DATMSK;
-
- /**
- * Px_PIN
- * ===================================================================================================
- * Offset: 0x10 Px Pin Value
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PIN0 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[1] |PIN1 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[2] |PIN2 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[3] |PIN3 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[4] |PIN4 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[5] |PIN5 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[6] |PIN6 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[7] |PIN7 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[8] |PIN8 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[9] |PIN9 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[10] |PIN10 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[11] |PIN11 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[12] |PIN12 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[13] |PIN13 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[14] |PIN14 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- * |[15] |PIN15 |Port N Bit M Pin Value
- * | | |Each bit of the register reflects the actual status of the respective port pin.
- * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
- */
- __I uint32_t PIN;
-
- /**
- * Px_DBEN
- * ===================================================================================================
- * Offset: 0x14 Px De-Bounce Enable Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DBEN0 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[1] |DBEN1 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[2] |DBEN2 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[3] |DBEN3 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[4] |DBEN4 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[5] |DBEN5 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[6] |DBEN6 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[7] |DBEN7 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[8] |DBEN8 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[9] |DBEN9 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[10] |DBEN10 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[11] |DBEN11 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[12] |DBEN12 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[13] |DBEN13 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[14] |DBEN14 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- * |[15] |DBEN15 |Port N Bit M Input De-Bounce Enable
- * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
- * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
- * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
- * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
- * | | |0 = Port n bit m input de-bounce Disabled.
- * | | |1 = Port n bit m input de-bounce Enabled.
- */
- __IO uint32_t DBEN;
-
- /**
- * Px_INTTYPE
- * ===================================================================================================
- * Offset: 0x18 Px Interrupt Trigger Type Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TYPE0 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[1] |TYPE1 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[2] |TYPE2 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[3] |TYPE3 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[4] |TYPE4 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[5] |TYPE5 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[6] |TYPE6 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[7] |TYPE7 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[8] |TYPE8 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[9] |TYPE9 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[10] |TYPE10 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[11] |TYPE11 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[12] |TYPE12 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[13] |TYPE13 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[14] |TYPE14 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- * |[15] |TYPE15 |Port N Bit M Edge Or Level Triggered Interrupt Control
- * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
- * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
- * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
- * | | |clock and generates the interrupt.
- * | | |0 = Edge triggered interrupt.
- * | | |1 = Level triggered interrupt.
- * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
- * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
- * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
- * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
- */
- __IO uint32_t INTTYPE;
-
- /**
- * Px_INTEN
- * ===================================================================================================
- * Offset: 0x1C Px Interrupt Enable
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLIEN0 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[1] |FLIEN1 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[2] |FLIEN2 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[3] |FLIEN3 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[4] |FLIEN4 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[5] |FLIEN5 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[6] |FLIEN6 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[7] |FLIEN7 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[8] |FLIEN8 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[9] |FLIEN9 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[10] |FLIEN10 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[11] |FLIEN11 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[12] |FLIEN12 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[13] |FLIEN13 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[14] |FLIEN14 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[15] |FLIEN15 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
- * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
- * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
- * |[16] |RHIEN0 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[17] |RHIEN1 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[18] |RHIEN2 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[19] |RHIEN3 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[20] |RHIEN4 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[21] |RHIEN5 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[22] |RHIEN6 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[23] |RHIEN7 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[24] |RHIEN8 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[25] |RHIEN9 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[26] |RHIEN10 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[27] |RHIEN11 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[28] |RHIEN12 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[29] |RHIEN13 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[30] |RHIEN14 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- * |[31] |RHIEN15 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
- * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
- * | | |Setting this bit to 1 also enables the pin wake-up function.
- * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
- * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * Px_INTSRC
- * ===================================================================================================
- * Offset: 0x20 Px Interrupt Source Flag
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |INTSRC0 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[1] |INTSRC1 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[2] |INTSRC2 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[3] |INTSRC3 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[4] |INTSRC4 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[5] |INTSRC5 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[6] |INTSRC6 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[7] |INTSRC7 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[8] |INTSRC8 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[9] |INTSRC9 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[10] |INTSRC10 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[11] |INTSRC11 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[12] |INTSRC12 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[13] |INTSRC13 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[14] |INTSRC14 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- * |[15] |INTSRC15 |Port N Bit M Interrupt Trigger Source Indicator
- * | | |Read:
- * | | |0 = No interrupt at Port n.
- * | | |1 = Port n bit m generate an interrupt.
- * | | |Write:
- * | | |0= No effect.
- * | | |1= Clear the correspond pending interrupt.
- */
- __IO uint32_t INTSRC;
-
- /**
- * Px_SMTEN
- * ===================================================================================================
- * Offset: 0x24 Px Input Schmitt Trigger Enable
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SMTEN0 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[1] |SMTEN1 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[2] |SMTEN2 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[3] |SMTEN3 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[4] |SMTEN4 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[5] |SMTEN5 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[6] |SMTEN6 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[7] |SMTEN7 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[8] |SMTEN8 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[9] |SMTEN9 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[10] |SMTEN10 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[11] |SMTEN11 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[12] |SMTEN12 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[13] |SMTEN13 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[14] |SMTEN14 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- * |[15] |SMTEN15 |0 = P I/O input Schmitt Trigger function Disabled.
- * | | |1 = P I/O input Schmitt Trigger function Enabled.
- */
- __IO uint32_t SMTEN;
-
- /**
- * Px_SLEWCTL
- * ===================================================================================================
- * Offset: 0x28 Px High Slew Rate Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HSREN0 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[1] |HSREN1 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[2] |HSREN2 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[3] |HSREN3 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[4] |HSREN4 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[5] |HSREN5 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[6] |HSREN6 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[7] |HSREN7 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[8] |HSREN8 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[9] |HSREN9 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[10] |HSREN10 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[11] |HSREN11 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[12] |HSREN12 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[13] |HSREN13 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[14] |HSREN14 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- * |[15] |HSREN15 |0 = P I/O output with basic slew rate.
- * | | |1 = P I/O output with higher slew rate.
- */
- __IO uint32_t SLEWCTL;
-
-} GPIO_T;
-
-
-typedef struct {
-
- /**
- * GPIO_DBCTL
- * ===================================================================================================
- * Offset: 0x000 Interrupt De-bounce Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |DBCLKSEL |De-Bounce Sampling Cycle Selection
- * | | |0000 = Sample interrupt input once per 1 clocks.
- * | | |0001 = Sample interrupt input once per 2 clocks.
- * | | |0010 = Sample interrupt input once per 4 clocks.
- * | | |0011 = Sample interrupt input once per 8 clocks.
- * | | |0100 = Sample interrupt input once per 16 clocks.
- * | | |0101 = Sample interrupt input once per 32 clocks.
- * | | |0110 = Sample interrupt input once per 64 clocks.
- * | | |0111 = Sample interrupt input once per 128 clocks.
- * | | |1000 = Sample interrupt input once per 256 clocks.
- * | | |1001 = Sample interrupt input once per 2*256 clocks.
- * | | |1010 = Sample interrupt input once per 4*256 clocks.
- * | | |1011 = Sample interrupt input once per 8*256 clocks.
- * | | |1100 = Sample interrupt input once per 16*256 clocks.
- * | | |1101 = Sample interrupt input once per 32*256 clocks.
- * | | |1110 = Sample interrupt input once per 64*256 clocks.
- * | | |1111 = Sample interrupt input once per 128*256 clocks.
- * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
- * | | |0 = De-bounce counter clock source is the HCLK.
- * | | |1 = De-bounce counter clock source is the internal 10 kHz clock.
- * |[5] |ICLKON |Interrupt Clock On Mode
- * | | |Setting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.
- * | | |0 = Disable the clock if the all port interrupts are disabled.
- * | | |1 = Interrupt generated circuit clock always Enabled.
- */
- __IO uint32_t DBCTL;
-
-} GPIO_DB_T;
-
-/**
- @addtogroup GPIO_CONST GPIO Bit Field Definition
- Constant Definitions for GPIO Controller
-@{ */
-
-#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO MODE: MODE0 Position */
-#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO MODE: MODE0 Mask */
-
-#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO MODE: MODE1 Position */
-#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO MODE: MODE1 Mask */
-
-#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO MODE: MODE2 Position */
-#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO MODE: MODE2 Mask */
-
-#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO MODE: MODE3 Position */
-#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO MODE: MODE3 Mask */
-
-#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO MODE: MODE4 Position */
-#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO MODE: MODE4 Mask */
-
-#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO MODE: MODE5 Position */
-#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO MODE: MODE5 Mask */
-
-#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO MODE: MODE6 Position */
-#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO MODE: MODE6 Mask */
-
-#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO MODE: MODE7 Position */
-#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO MODE: MODE7 Mask */
-
-#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO MODE: MODE8 Position */
-#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO MODE: MODE8 Mask */
-
-#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO MODE: MODE9 Position */
-#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO MODE: MODE9 Mask */
-
-#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO MODE: MODE10 Position */
-#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO MODE: MODE10 Mask */
-
-#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO MODE: MODE11 Position */
-#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO MODE: MODE11 Mask */
-
-#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO MODE: MODE12 Position */
-#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO MODE: MODE12 Mask */
-
-#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO MODE: MODE13 Position */
-#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO MODE: MODE13 Mask */
-
-#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO MODE: MODE14 Position */
-#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO MODE: MODE14 Mask */
-
-#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO MODE: MODE15 Position */
-#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO MODE: MODE15 Mask */
-
-#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO DINOFF: DINOFF0 Position */
-#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO DINOFF: DINOFF0 Mask */
-
-#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO DINOFF: DINOFF1 Position */
-#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO DINOFF: DINOFF1 Mask */
-
-#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO DINOFF: DINOFF2 Position */
-#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO DINOFF: DINOFF2 Mask */
-
-#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO DINOFF: DINOFF3 Position */
-#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO DINOFF: DINOFF3 Mask */
-
-#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO DINOFF: DINOFF4 Position */
-#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO DINOFF: DINOFF4 Mask */
-
-#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO DINOFF: DINOFF5 Position */
-#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO DINOFF: DINOFF5 Mask */
-
-#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO DINOFF: DINOFF6 Position */
-#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO DINOFF: DINOFF6 Mask */
-
-#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO DINOFF: DINOFF7 Position */
-#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO DINOFF: DINOFF7 Mask */
-
-#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO DINOFF: DINOFF8 Position */
-#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO DINOFF: DINOFF8 Mask */
-
-#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO DINOFF: DINOFF9 Position */
-#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO DINOFF: DINOFF9 Mask */
-
-#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO DINOFF: DINOFF10 Position */
-#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO DINOFF: DINOFF10 Mask */
-
-#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO DINOFF: DINOFF11 Position */
-#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO DINOFF: DINOFF11 Mask */
-
-#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO DINOFF: DINOFF12 Position */
-#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO DINOFF: DINOFF12 Mask */
-
-#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO DINOFF: DINOFF13 Position */
-#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO DINOFF: DINOFF13 Mask */
-
-#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO DINOFF: DINOFF14 Position */
-#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO DINOFF: DINOFF14 Mask */
-
-#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO DINOFF: DINOFF15 Position */
-#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO DINOFF: DINOFF15 Mask */
-
-#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO DOUT: DOUT0 Position */
-#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO DOUT: DOUT0 Mask */
-
-#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO DOUT: DOUT1 Position */
-#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO DOUT: DOUT1 Mask */
-
-#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO DOUT: DOUT2 Position */
-#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO DOUT: DOUT2 Mask */
-
-#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO DOUT: DOUT3 Position */
-#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO DOUT: DOUT3 Mask */
-
-#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO DOUT: DOUT4 Position */
-#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO DOUT: DOUT4 Mask */
-
-#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO DOUT: DOUT5 Position */
-#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO DOUT: DOUT5 Mask */
-
-#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO DOUT: DOUT6 Position */
-#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO DOUT: DOUT6 Mask */
-
-#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO DOUT: DOUT7 Position */
-#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO DOUT: DOUT7 Mask */
-
-#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO DOUT: DOUT8 Position */
-#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO DOUT: DOUT8 Mask */
-
-#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO DOUT: DOUT9 Position */
-#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO DOUT: DOUT9 Mask */
-
-#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO DOUT: DOUT10 Position */
-#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO DOUT: DOUT10 Mask */
-
-#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO DOUT: DOUT11 Position */
-#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO DOUT: DOUT11 Mask */
-
-#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO DOUT: DOUT12 Position */
-#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO DOUT: DOUT12 Mask */
-
-#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO DOUT: DOUT13 Position */
-#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO DOUT: DOUT13 Mask */
-
-#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO DOUT: DOUT14 Position */
-#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO DOUT: DOUT14 Mask */
-
-#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO DOUT: DOUT15 Position */
-#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO DOUT: DOUT15 Mask */
-
-#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO DATMSK: DATMSK0 Position */
-#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO DATMSK: DATMSK0 Mask */
-
-#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO DATMSK: DATMSK1 Position */
-#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO DATMSK: DATMSK1 Mask */
-
-#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO DATMSK: DATMSK2 Position */
-#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO DATMSK: DATMSK2 Mask */
-
-#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO DATMSK: DATMSK3 Position */
-#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO DATMSK: DATMSK3 Mask */
-
-#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO DATMSK: DATMSK4 Position */
-#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO DATMSK: DATMSK4 Mask */
-
-#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO DATMSK: DATMSK5 Position */
-#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO DATMSK: DATMSK5 Mask */
-
-#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO DATMSK: DATMSK6 Position */
-#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO DATMSK: DATMSK6 Mask */
-
-#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO DATMSK: DATMSK7 Position */
-#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO DATMSK: DATMSK7 Mask */
-
-#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO DATMSK: DATMSK8 Position */
-#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO DATMSK: DATMSK8 Mask */
-
-#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO DATMSK: DATMSK9 Position */
-#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO DATMSK: DATMSK9 Mask */
-
-#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO DATMSK: DATMSK10 Position */
-#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO DATMSK: DATMSK10 Mask */
-
-#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO DATMSK: DATMSK11 Position */
-#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO DATMSK: DATMSK11 Mask */
-
-#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO DATMSK: DATMSK12 Position */
-#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO DATMSK: DATMSK12 Mask */
-
-#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO DATMSK: DATMSK13 Position */
-#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO DATMSK: DATMSK13 Mask */
-
-#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO DATMSK: DATMSK14 Position */
-#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO DATMSK: DATMSK14 Mask */
-
-#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO DATMSK: DATMSK15 Position */
-#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO DATMSK: DATMSK15 Mask */
-
-#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO PIN: PIN0 Position */
-#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO PIN: PIN0 Mask */
-
-#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO PIN: PIN1 Position */
-#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO PIN: PIN1 Mask */
-
-#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO PIN: PIN2 Position */
-#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO PIN: PIN2 Mask */
-
-#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO PIN: PIN3 Position */
-#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO PIN: PIN3 Mask */
-
-#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO PIN: PIN4 Position */
-#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO PIN: PIN4 Mask */
-
-#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO PIN: PIN5 Position */
-#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO PIN: PIN5 Mask */
-
-#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO PIN: PIN6 Position */
-#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO PIN: PIN6 Mask */
-
-#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO PIN: PIN7 Position */
-#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO PIN: PIN7 Mask */
-
-#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO PIN: PIN8 Position */
-#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO PIN: PIN8 Mask */
-
-#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO PIN: PIN9 Position */
-#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO PIN: PIN9 Mask */
-
-#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO PIN: PIN10 Position */
-#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO PIN: PIN10 Mask */
-
-#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO PIN: PIN11 Position */
-#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO PIN: PIN11 Mask */
-
-#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO PIN: PIN12 Position */
-#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO PIN: PIN12 Mask */
-
-#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO PIN: PIN13 Position */
-#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO PIN: PIN13 Mask */
-
-#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO PIN: PIN14 Position */
-#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO PIN: PIN14 Mask */
-
-#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO PIN: PIN15 Position */
-#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO PIN: PIN15 Mask */
-
-#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO DBEN: DBEN0 Position */
-#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO DBEN: DBEN0 Mask */
-
-#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO DBEN: DBEN1 Position */
-#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO DBEN: DBEN1 Mask */
-
-#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO DBEN: DBEN2 Position */
-#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO DBEN: DBEN2 Mask */
-
-#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO DBEN: DBEN3 Position */
-#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO DBEN: DBEN3 Mask */
-
-#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO DBEN: DBEN4 Position */
-#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO DBEN: DBEN4 Mask */
-
-#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO DBEN: DBEN5 Position */
-#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO DBEN: DBEN5 Mask */
-
-#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO DBEN: DBEN6 Position */
-#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO DBEN: DBEN6 Mask */
-
-#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO DBEN: DBEN7 Position */
-#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO DBEN: DBEN7 Mask */
-
-#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO DBEN: DBEN8 Position */
-#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO DBEN: DBEN8 Mask */
-
-#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO DBEN: DBEN9 Position */
-#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO DBEN: DBEN9 Mask */
-
-#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO DBEN: DBEN10 Position */
-#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO DBEN: DBEN10 Mask */
-
-#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO DBEN: DBEN11 Position */
-#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO DBEN: DBEN11 Mask */
-
-#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO DBEN: DBEN12 Position */
-#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO DBEN: DBEN12 Mask */
-
-#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO DBEN: DBEN13 Position */
-#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO DBEN: DBEN13 Mask */
-
-#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO DBEN: DBEN14 Position */
-#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO DBEN: DBEN14 Mask */
-
-#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO DBEN: DBEN15 Position */
-#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO DBEN: DBEN15 Mask */
-
-#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO INTTYPE: TYPE0 Position */
-#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO INTTYPE: TYPE0 Mask */
-
-#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO INTTYPE: TYPE1 Position */
-#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO INTTYPE: TYPE1 Mask */
-
-#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO INTTYPE: TYPE2 Position */
-#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO INTTYPE: TYPE2 Mask */
-
-#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO INTTYPE: TYPE3 Position */
-#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO INTTYPE: TYPE3 Mask */
-
-#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO INTTYPE: TYPE4 Position */
-#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO INTTYPE: TYPE4 Mask */
-
-#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO INTTYPE: TYPE5 Position */
-#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO INTTYPE: TYPE5 Mask */
-
-#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO INTTYPE: TYPE6 Position */
-#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO INTTYPE: TYPE6 Mask */
-
-#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO INTTYPE: TYPE7 Position */
-#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO INTTYPE: TYPE7 Mask */
-
-#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO INTTYPE: TYPE8 Position */
-#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO INTTYPE: TYPE8 Mask */
-
-#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO INTTYPE: TYPE9 Position */
-#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO INTTYPE: TYPE9 Mask */
-
-#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO INTTYPE: TYPE10 Position */
-#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO INTTYPE: TYPE10 Mask */
-
-#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO INTTYPE: TYPE11 Position */
-#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO INTTYPE: TYPE11 Mask */
-
-#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO INTTYPE: TYPE12 Position */
-#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO INTTYPE: TYPE12 Mask */
-
-#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO INTTYPE: TYPE13 Position */
-#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO INTTYPE: TYPE13 Mask */
-
-#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO INTTYPE: TYPE14 Position */
-#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO INTTYPE: TYPE14 Mask */
-
-#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO INTTYPE: TYPE15 Position */
-#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO INTTYPE: TYPE15 Mask */
-
-#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO INTEN: FLIEN0 Position */
-#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO INTEN: FLIEN0 Mask */
-
-#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO INTEN: FLIEN1 Position */
-#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO INTEN: FLIEN1 Mask */
-
-#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO INTEN: FLIEN2 Position */
-#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO INTEN: FLIEN2 Mask */
-
-#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO INTEN: FLIEN3 Position */
-#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO INTEN: FLIEN3 Mask */
-
-#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO INTEN: FLIEN4 Position */
-#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO INTEN: FLIEN4 Mask */
-
-#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO INTEN: FLIEN5 Position */
-#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO INTEN: FLIEN5 Mask */
-
-#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO INTEN: FLIEN6 Position */
-#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO INTEN: FLIEN6 Mask */
-
-#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO INTEN: FLIEN7 Position */
-#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO INTEN: FLIEN7 Mask */
-
-#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO INTEN: FLIEN8 Position */
-#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO INTEN: FLIEN8 Mask */
-
-#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO INTEN: FLIEN9 Position */
-#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO INTEN: FLIEN9 Mask */
-
-#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO INTEN: FLIEN10 Position */
-#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO INTEN: FLIEN10 Mask */
-
-#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO INTEN: FLIEN11 Position */
-#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO INTEN: FLIEN11 Mask */
-
-#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO INTEN: FLIEN12 Position */
-#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO INTEN: FLIEN12 Mask */
-
-#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO INTEN: FLIEN13 Position */
-#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO INTEN: FLIEN13 Mask */
-
-#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO INTEN: FLIEN14 Position */
-#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO INTEN: FLIEN14 Mask */
-
-#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO INTEN: FLIEN15 Position */
-#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO INTEN: FLIEN15 Mask */
-
-#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO INTEN: RHIEN0 Position */
-#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO INTEN: RHIEN0 Mask */
-
-#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO INTEN: RHIEN1 Position */
-#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO INTEN: RHIEN1 Mask */
-
-#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO INTEN: RHIEN2 Position */
-#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO INTEN: RHIEN2 Mask */
-
-#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO INTEN: RHIEN3 Position */
-#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO INTEN: RHIEN3 Mask */
-
-#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO INTEN: RHIEN4 Position */
-#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO INTEN: RHIEN4 Mask */
-
-#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO INTEN: RHIEN5 Position */
-#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO INTEN: RHIEN5 Mask */
-
-#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO INTEN: RHIEN6 Position */
-#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO INTEN: RHIEN6 Mask */
-
-#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO INTEN: RHIEN7 Position */
-#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO INTEN: RHIEN7 Mask */
-
-#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO INTEN: RHIEN8 Position */
-#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO INTEN: RHIEN8 Mask */
-
-#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO INTEN: RHIEN9 Position */
-#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO INTEN: RHIEN9 Mask */
-
-#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO INTEN: RHIEN10 Position */
-#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO INTEN: RHIEN10 Mask */
-
-#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO INTEN: RHIEN11 Position */
-#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO INTEN: RHIEN11 Mask */
-
-#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO INTEN: RHIEN12 Position */
-#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO INTEN: RHIEN12 Mask */
-
-#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO INTEN: RHIEN13 Position */
-#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO INTEN: RHIEN13 Mask */
-
-#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO INTEN: RHIEN14 Position */
-#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO INTEN: RHIEN14 Mask */
-
-#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO INTEN: RHIEN15 Position */
-#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO INTEN: RHIEN15 Mask */
-
-#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO INTSRC: INTSRC0 Position */
-#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO INTSRC: INTSRC0 Mask */
-
-#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO INTSRC: INTSRC1 Position */
-#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO INTSRC: INTSRC1 Mask */
-
-#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO INTSRC: INTSRC2 Position */
-#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO INTSRC: INTSRC2 Mask */
-
-#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO INTSRC: INTSRC3 Position */
-#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO INTSRC: INTSRC3 Mask */
-
-#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO INTSRC: INTSRC4 Position */
-#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO INTSRC: INTSRC4 Mask */
-
-#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO INTSRC: INTSRC5 Position */
-#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO INTSRC: INTSRC5 Mask */
-
-#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO INTSRC: INTSRC6 Position */
-#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO INTSRC: INTSRC6 Mask */
-
-#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO INTSRC: INTSRC7 Position */
-#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO INTSRC: INTSRC7 Mask */
-
-#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO INTSRC: INTSRC8 Position */
-#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO INTSRC: INTSRC8 Mask */
-
-#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO INTSRC: INTSRC9 Position */
-#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO INTSRC: INTSRC9 Mask */
-
-#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO INTSRC: INTSRC10 Position */
-#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO INTSRC: INTSRC10 Mask */
-
-#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO INTSRC: INTSRC11 Position */
-#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO INTSRC: INTSRC11 Mask */
-
-#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO INTSRC: INTSRC12 Position */
-#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO INTSRC: INTSRC12 Mask */
-
-#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO INTSRC: INTSRC13 Position */
-#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO INTSRC: INTSRC13 Mask */
-
-#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO INTSRC: INTSRC14 Position */
-#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO INTSRC: INTSRC14 Mask */
-
-#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO INTSRC: INTSRC15 Position */
-#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO INTSRC: INTSRC15 Mask */
-
-#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO SMTEN: SMTEN0 Position */
-#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO SMTEN: SMTEN0 Mask */
-
-#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO SMTEN: SMTEN1 Position */
-#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO SMTEN: SMTEN1 Mask */
-
-#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO SMTEN: SMTEN2 Position */
-#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO SMTEN: SMTEN2 Mask */
-
-#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO SMTEN: SMTEN3 Position */
-#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO SMTEN: SMTEN3 Mask */
-
-#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO SMTEN: SMTEN4 Position */
-#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO SMTEN: SMTEN4 Mask */
-
-#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO SMTEN: SMTEN5 Position */
-#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO SMTEN: SMTEN5 Mask */
-
-#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO SMTEN: SMTEN6 Position */
-#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO SMTEN: SMTEN6 Mask */
-
-#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO SMTEN: SMTEN7 Position */
-#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO SMTEN: SMTEN7 Mask */
-
-#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO SMTEN: SMTEN8 Position */
-#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO SMTEN: SMTEN8 Mask */
-
-#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO SMTEN: SMTEN9 Position */
-#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO SMTEN: SMTEN9 Mask */
-
-#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO SMTEN: SMTEN10 Position */
-#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO SMTEN: SMTEN10 Mask */
-
-#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO SMTEN: SMTEN11 Position */
-#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO SMTEN: SMTEN11 Mask */
-
-#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO SMTEN: SMTEN12 Position */
-#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO SMTEN: SMTEN12 Mask */
-
-#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO SMTEN: SMTEN13 Position */
-#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO SMTEN: SMTEN13 Mask */
-
-#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO SMTEN: SMTEN14 Position */
-#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO SMTEN: SMTEN14 Mask */
-
-#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO SMTEN: SMTEN15 Position */
-#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO SMTEN: SMTEN15 Mask */
-
-#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO SLEWCTL: HSREN0 Position */
-#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO SLEWCTL: HSREN0 Mask */
-
-#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO SLEWCTL: HSREN1 Position */
-#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO SLEWCTL: HSREN1 Mask */
-
-#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO SLEWCTL: HSREN2 Position */
-#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO SLEWCTL: HSREN2 Mask */
-
-#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO SLEWCTL: HSREN3 Position */
-#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO SLEWCTL: HSREN3 Mask */
-
-#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO SLEWCTL: HSREN4 Position */
-#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO SLEWCTL: HSREN4 Mask */
-
-#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO SLEWCTL: HSREN5 Position */
-#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO SLEWCTL: HSREN5 Mask */
-
-#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO SLEWCTL: HSREN6 Position */
-#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO SLEWCTL: HSREN6 Mask */
-
-#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO SLEWCTL: HSREN7 Position */
-#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO SLEWCTL: HSREN7 Mask */
-
-#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO SLEWCTL: HSREN8 Position */
-#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO SLEWCTL: HSREN8 Mask */
-
-#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO SLEWCTL: HSREN9 Position */
-#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO SLEWCTL: HSREN9 Mask */
-
-#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO SLEWCTL: HSREN10 Position */
-#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO SLEWCTL: HSREN10 Mask */
-
-#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO SLEWCTL: HSREN11 Position */
-#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO SLEWCTL: HSREN11 Mask */
-
-#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO SLEWCTL: HSREN12 Position */
-#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO SLEWCTL: HSREN12 Mask */
-
-#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO SLEWCTL: HSREN13 Position */
-#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO SLEWCTL: HSREN13 Mask */
-
-#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO SLEWCTL: HSREN14 Position */
-#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO SLEWCTL: HSREN14 Mask */
-
-#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO SLEWCTL: HSREN15 Position */
-#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO SLEWCTL: HSREN15 Mask */
-
-#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO DBCTL: DBCLKSEL Position */
-#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO DBCTL: DBCLKSEL Mask */
-
-#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO DBCTL: DBCLKSRC Position */
-#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO DBCTL: DBCLKSRC Mask */
-
-#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO DBCTL: ICLKON Position */
-#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO DBCTL: ICLKON Mask */
-
-/**@}*/ /* GPIO_CONST */
-/**@}*/ /* end of GPIO register group */
-
-
-/*---------------------- Inter-IC Bus Controller -------------------------*/
-/**
- @addtogroup I2C Inter-IC Bus Controller(I2C)
- Memory Mapped Structure for I2C Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 I2C Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2] |AA |Assert Acknowledge Control
- * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
- * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
- * |[3] |SI |I2C Interrupt Flag
- * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested.
- * | | |SI must be cleared by software.
- * | | |Clear SI by writing 1 to this bit.
- * |[4] |STO |I2C STOP Control
- * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically.
- * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode.
- * | | |This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
- * |[5] |STA |I2C START Control
- * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
- * |[6] |I2CEN |I2C Controller Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |Set to enable I2C serial function controller.
- * | | |When ENS1=1 the I2C serial function enables.
- * | | |The multi-function pin function of SDA and SCL must set to I2C function first.
- * |[7] |INTEN |I2C Interrupt Enable Control
- * | | |0 = I2C interrupt Disabled.
- * | | |1 = I2C interrupt Enabled.
- */
- __IO uint32_t CTL;
-
- /**
- * ADDR0
- * ===================================================================================================
- * Offset: 0x04 I2C Slave Address Register0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[1:7] |ADDR |I2C Address Bits
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- */
- __IO uint32_t ADDR0;
-
- /**
- * DAT
- * ===================================================================================================
- * Offset: 0x08 I2C Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DAT |I2C Data Bits
- * | | |Bit [7:0] is located with the 8-bit transferred data of I2C serial port.
- */
- __IO uint32_t DAT;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x0C I2C Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |STATUS |I2C Status Bits
- * | | |The status register of I2C:
- * | | |The three least significant bits are always 0.
- * | | |The five most significant bits contain the status code.
- * | | |Refer to section 6.15.5.4 for detail description.
- */
- __I uint32_t STATUS;
-
- /**
- * CLKDIV
- * ===================================================================================================
- * Offset: 0x10 I2C Clock Divided Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DIVIDER |I2C Clock Divided Bits
- * | | |The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4x (I2CLK+1)).
- * | | |Note: The minimum value of I2CLK is 4.
- */
- __IO uint32_t CLKDIV;
-
- /**
- * TOCTL
- * ===================================================================================================
- * Offset: 0x14 I2C Time-out Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TOIF |Time-Out Flag
- * | | |This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI (I2CON[7])) is set to 1.
- * | | |Note: Write 1 to clear this bit.
- * |[1] |TOCDIV4 |Time-Out Counter Input Clock Divided By 4
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |When Enabled, The time-out period is extend 4 times.
- * |[2] |TOCEN |Time-Out Counter Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |When Enabled, the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear.
- * | | |Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
- */
- __IO uint32_t TOCTL;
-
- /**
- * ADDR1
- * ===================================================================================================
- * Offset: 0x18 I2C Slave Address Register1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[1:7] |ADDR |I2C Address Bits
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- */
- __IO uint32_t ADDR1;
-
- /**
- * ADDR2
- * ===================================================================================================
- * Offset: 0x1C I2C Slave Address Register2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[1:7] |ADDR |I2C Address Bits
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- */
- __IO uint32_t ADDR2;
-
- /**
- * ADDR3
- * ===================================================================================================
- * Offset: 0x20 I2C Slave Address Register3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GC |General Call Function
- * | | |0 = General Call Function Disabled.
- * | | |1 = General Call Function Enabled.
- * |[1:7] |ADDR |I2C Address Bits
- * | | |The content of this register is irrelevant when I2C is in Master mode.
- * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
- * | | |The I2C hardware will react if either of the address is matched.
- */
- __IO uint32_t ADDR3;
-
- /**
- * ADDRMSK0
- * ===================================================================================================
- * Offset: 0x24 I2C Slave Address Mask Register0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:7] |ADDRMSK |I2C Address Mask Bits
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- */
- __IO uint32_t ADDRMSK0;
-
- /**
- * ADDRMSK1
- * ===================================================================================================
- * Offset: 0x28 I2C Slave Address Mask Register1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:7] |ADDRMSK |I2C Address Mask Bits
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- */
- __IO uint32_t ADDRMSK1;
-
- /**
- * ADDRMSK2
- * ===================================================================================================
- * Offset: 0x2C I2C Slave Address Mask Register2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:7] |ADDRMSK |I2C Address Mask Bits
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- */
- __IO uint32_t ADDRMSK2;
-
- /**
- * ADDRMSK3
- * ===================================================================================================
- * Offset: 0x30 I2C Slave Address Mask Register3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1:7] |ADDRMSK |I2C Address Mask Bits
- * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
- * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
- * | | |I2C bus controllers support multiple address recognition with four address mask register.
- * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
- * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
- */
- __IO uint32_t ADDRMSK3;
- uint32_t RESERVE0[2];
-
-
- /**
- * WKCTL
- * ===================================================================================================
- * Offset: 0x3C I2C Wake-up Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WKEN |I2C Wake-Up Enable Control
- * | | |0 = I2C wake-up function Disabled.
- * | | |1 = I2C wake-up function Enabled.
- */
- __IO uint32_t WKCTL;
-
- /**
- * WKSTS
- * ===================================================================================================
- * Offset: 0x40 I2C Wake-up Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WKIF |I2C Wake-Up Flag
- * | | |0 = No wake up occurred.
- * | | |1 = Wake up from Power-down mode.
- * | | |Note: Software can write 1 to clear this bit.
- */
- __IO uint32_t WKSTS;
-
-} I2C_T;
-
-/**
- @addtogroup I2C_CONST I2C Bit Field Definition
- Constant Definitions for I2C Controller
-@{ */
-
-#define I2C_CTL_AA_Pos (2) /*!< I2C CTL: AA Position */
-#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /*!< I2C CTL: AA Mask */
-
-#define I2C_CTL_SI_Pos (3) /*!< I2C CTL: SI Position */
-#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /*!< I2C CTL: SI Mask */
-
-#define I2C_CTL_STO_Pos (4) /*!< I2C CTL: STO Position */
-#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /*!< I2C CTL: STO Mask */
-
-#define I2C_CTL_STA_Pos (5) /*!< I2C CTL: STA Position */
-#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /*!< I2C CTL: STA Mask */
-
-#define I2C_CTL_I2CEN_Pos (6) /*!< I2C CTL: I2CEN Position */
-#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /*!< I2C CTL: I2CEN Mask */
-
-#define I2C_CTL_INTEN_Pos (7) /*!< I2C CTL: INTEN Position */
-#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /*!< I2C CTL: INTEN Mask */
-
-#define I2C_ADDR0_GC_Pos (0) /*!< I2C ADDR0: GC Position */
-#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C ADDR0: GC Mask */
-
-#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C ADDR0: ADDR Position */
-#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C ADDR0: ADDR Mask */
-
-#define I2C_DAT_DAT_Pos (0) /*!< I2C DAT: DAT Position */
-#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C DAT: DAT Mask */
-
-#define I2C_STATUS_STATUS_Pos (0) /*!< I2C STATUS: STATUS Position */
-#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C STATUS: STATUS Mask */
-
-#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C CLKDIV: DIVIDER Position */
-#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C CLKDIV: DIVIDER Mask */
-
-#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C TOCTL: TOIF Position */
-#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C TOCTL: TOIF Mask */
-
-#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C TOCTL: TOCDIV4 Position */
-#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C TOCTL: TOCDIV4 Mask */
-
-#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C TOCTL: TOCEN Position */
-#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C TOCTL: TOCEN Mask */
-
-#define I2C_ADDR1_GC_Pos (0) /*!< I2C ADDR1: GC Position */
-#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C ADDR1: GC Mask */
-
-#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C ADDR1: ADDR Position */
-#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C ADDR1: ADDR Mask */
-
-#define I2C_ADDR2_GC_Pos (0) /*!< I2C ADDR2: GC Position */
-#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C ADDR2: GC Mask */
-
-#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C ADDR2: ADDR Position */
-#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C ADDR2: ADDR Mask */
-
-#define I2C_ADDR3_GC_Pos (0) /*!< I2C ADDR3: GC Position */
-#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C ADDR3: GC Mask */
-
-#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C ADDR3: ADDR Position */
-#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C ADDR3: ADDR Mask */
-
-#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C ADDRMSK0: ADDRMSK Position */
-#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C ADDRMSK0: ADDRMSK Mask */
-
-#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C ADDRMSK1: ADDRMSK Position */
-#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C ADDRMSK1: ADDRMSK Mask */
-
-#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C ADDRMSK2: ADDRMSK Position */
-#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C ADDRMSK2: ADDRMSK Mask */
-
-#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C ADDRMSK3: ADDRMSK Position */
-#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C ADDRMSK3: ADDRMSK Mask */
-
-#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C WKCTL: WKEN Position */
-#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C WKCTL: WKEN Mask */
-
-#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C WKSTS: WKIF Position */
-#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C WKSTS: WKIF Mask */
-
-/**@}*/ /* I2C_CONST */
-/**@}*/ /* end of I2C register group */
-
-
-/*---------------------- I2S Interface Controller -------------------------*/
-/**
- @addtogroup I2S I2S Interface Controller(I2S)
- Memory Mapped Structure for I2S Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 I2S Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |I2SEN |I2S Controller Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |TXEN |Transmit Enable Control
- * | | |0 = Data transmission Disabled.
- * | | |1 = Data transmission Enabled.
- * |[2] |RXEN |Receive Enable Control
- * | | |0 = Data receiving Disabled.
- * | | |1 = Data receiving Enabled.
- * |[3] |MUTE |Transmit Mute Enable Control
- * | | |0 = Transmit data is shifted from buffer.
- * | | |1 = Transmit zero data.
- * |[4:5] |WDWIDTH |Word Width
- * | | |00 = data is 8-bit.
- * | | |01 = data is 16-bit.
- * | | |10 = data is 24-bit.
- * | | |11 = data is 32-bit.
- * |[6] |MONO |Monaural Data Control
- * | | |0 = Data is stereo format.
- * | | |1 = Data is monaural format.
- * | | |Note: when chip records data, only right channel data will be saved if monaural format is select.
- * |[7] |FORMAT |Data Format Selection
- * | | |If PCM=0,
- * | | |0 = I2S data format.
- * | | |1 = MSB justified data format.
- * | | |If PCM=1,
- * | | |0 = PCM mode A.
- * | | |1 = PCM mode B.
- * |[8] |SLAVE |Slave Mode Enable Control
- * | | |0 = Master mode.
- * | | |1 = Slave mode.
- * | | |Note: I2S can operate as master or slave.
- * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro(TM)
- * | | |NUC442/NUC472 series to Audio CODEC chip.
- * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
- * |[9:11] |TXTH |Transmit FIFO Threshold Level
- * | | |000 = 0 word data in transmit FIFO.
- * | | |001 = 1 word data in transmit FIFO.
- * | | |010 = 2 words data in transmit FIFO.
- * | | |011 = 3 words data in transmit FIFO.
- * | | |100 = 4 words data in transmit FIFO.
- * | | |101 = 5 words data in transmit FIFO.
- * | | |110 = 6 words data in transmit FIFO.
- * | | |111 = 7 words data in transmit FIFO.
- * | | |Note: If remain data word(s) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.
- * |[12:14] |RXTH |Receive FIFO Threshold Level
- * | | |000 = 1 word data in receive FIFO.
- * | | |001 = 2 word data in receive FIFO.
- * | | |010 = 3 word data in receive FIFO.
- * | | |011 = 4 word data in receive FIFO.
- * | | |100 = 5 word data in receive FIFO.
- * | | |101 = 6 word data in receive FIFO.
- * | | |110 = 7 word data in receive FIFO.
- * | | |111 = 8 word data in receive FIFO.
- * | | |Note: When received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.
- * |[15] |MCLKEN |Master Clock Enable Control
- * | | |0 = Master clock Disabled.
- * | | |1 = Master clock Enabled.
- * | | |Note: If the external crystal clock in NuMicro(TM) NUC442/NUC472 series is frequency 2*N*256fs, software can program MCLK_DIV(I2S_CLK[5:0]) to get 256fs clock to audio codec chip.
- * |[16] |RZCEN |Right Channel Zero-Cross Detection Enable Control
- * | | |0 = Right channel zero-cross detect Disabled.
- * | | |1 = Right channel zero-cross detect Enabled.
- * | | |Note1: If this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCF(I2S_STATUS[22]) flag is set to 1.
- * | | |Note2: If RZCF Flag is set to 1, the right channel will be mute.
- * |[17] |LZCEN |Left Channel Zero-Cross Detect Enable Control
- * | | |0 = Left channel zero-cross detect Disabled.
- * | | |1 = Left channel zero-cross detect Enabled.
- * | | |Note1: If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF(I2S_STATUS[23]) flag is set to 1.
- * | | |Note2: If LZCF Flag is set to 1, the left channel will be mute.
- * |[18] |TXCLR |Clear Transmit FIFO
- * | | |0 = No Effect.
- * | | |1 = Clear TX FIFO.
- * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT(I2S_STATUS[31:28]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
- * | | |Note2: This bit is clear by hardware automatically, read it return zero.
- * |[19] |RXCLR |Clear Receive FIFO
- * | | |0 = No Effect.
- * | | |1 = Clear RX FIFO.
- * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty.
- * | | |Note2: This bit is cleared by hardware automatically, read it return zero.
- * |[20] |TXPDMAEN |Transmit DMA Enable Control
- * | | |0 = TX DMA Disabled.
- * | | |1 = TX DMA Enabled.
- * | | |Note: When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
- * |[21] |RXPDMAEN |Receive DMA Enable Control
- * | | |0 = RX DMA Disabled.
- * | | |1 = RX DMA Enabled.
- * | | |Note: When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
- * |[23] |RXLCH |Receive Left Channel Enable Control
- * | | |0 = Receives right channel data when monaural format is selected.
- * | | |1 = Receives left channel data when monaural format is selected.
- * | | |Note: When monaural format is selected (MONO = 1), I2S will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
- * |[24] |PCMEN |PCM Interface Enable Control
- * | | |0 = I2S Interface.
- * | | |1 = PCM Interface.
- */
- __IO uint32_t CTL;
-
- /**
- * CLKDIV
- * ===================================================================================================
- * Offset: 0x04 I2S Clock Divider Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |MCLKDIV |Master Clock Divider
- * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip.
- * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
- * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
- * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
- * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
- * | | |Note: F_MCLK is the frequency of MCLK, and F_i2SCLK is the frequency of the I2S_CLK
- * |[8:16] |BCLKDIV |Bit Clock Divider
- * | | |If I2S operates in Master mode, bit clock is provided by the NuMicro(TM) NUC442/NUC472 series.
- * | | |Software can program these bits to generate sampling rate clock frequency.
- * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
- * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
- */
- __IO uint32_t CLKDIV;
-
- /**
- * IEN
- * ===================================================================================================
- * Offset: 0x08 I2S Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXUDIEN |Receive FIFO Underflow Interrupt E Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: If software reads receive FIFO when it is empty then RXUDIF(I2S_STATUS[8]) flag is set to 1.
- * |[1] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIEN(I2S_STATUS[9]) flag is set to 1
- * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHF bit is set to 1.
- * | | |If RXTHIEN bit is enabled, interrupt occur.
- * |[8] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIEN(I2S_STATUS[16]) flag is set to 1.
- * |[9] |TXOVIEN |Transmit FIFO Overflow Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIEN(I2S_STATUS[17]) flag is set to 1
- * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH(I2S_CTL[11:9]).
- * |[11] |RZCIEN |Right Channel Zero-Cross Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Interrupt occurs if this bit is set to 1 and right channel zero-cross
- * |[12] |LZCIEN |Left Channel Zero-Cross Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Interrupt occurs if this bit is set to 1 and left channel zero-cross
- */
- __IO uint32_t IEN;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x0C I2S Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |I2SIF |I2S Interrupt Flag (Read Only)
- * | | |0 = No I2S interrupt.
- * | | |1 = I2S interrupt.
- * | | |Note: It is wire-OR of TXIF and RXIF bits.
- * |[1] |RXIF |I2S Receive Interrupt (Read Only)
- * | | |0 = No receive interrupt.
- * | | |1 = Receive interrupt.
- * |[2] |TXIF |I2S Transmit Interrupt (Read Only)
- * | | |0 = No transmit interrupt.
- * | | |1 = Transmit interrupt.
- * |[3] |RIGHT |Right Channel (Read Only)
- * | | |0 = Left channel.
- * | | |1 = Right channel.
- * | | |Note: This bit indicate current transmit data is belong to right channel
- * |[8] |RXUDIF |Receive FIFO Underflow Flag
- * | | |0 = No underflow occur.
- * | | |1 = Underflow occur.
- * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again.
- * | | |This bit will be set to 1, and it indicates underflow situation occurs.
- * | | |Note2: Write 1 to clear this bit to zero
- * |[9] |RXOVIF |Receive FIFO Overflow Flag
- * | | |0 = No overflow occur.
- * | | |1 = Overflow occur.
- * | | |Note1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
- * | | |Note2: Write 1 to clear this bit to 0.
- * |[10] |RXTHIF |Receive FIFO Threshold Flag (Read Only)
- * | | |0 = Data word(s) in FIFO is lower than threshold level.
- * | | |1 = Data word(s) in FIFO is equal or higher than threshold level.
- * | | |Note: When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH(I2S_CTL[14:12]) the RXTHIF bit becomes to 1.
- * | | |It keeps at 1 till RXCNT less than RXTH after software read RXFIFO register.
- * |[11] |RXFULL |Receive FIFO Full (Read Only)
- * | | |0 = Not full.
- * | | |1 = Full.
- * | | |Note: This bit reflects data words number in receive FIFO is 8.
- * |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
- * | | |0 = Not empty.
- * | | |1 = Empty.
- * | | |Note: This bit reflects data words number in receive FIFO is zero
- * |[16] |TXUDIF |Transmit FIFO Underflow Flag
- * | | |0 = No underflow.
- * | | |1 = Underflow.
- * | | |Note1: When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.
- * | | |Note2: Write 1 to clear this bit to 0.
- * |[17] |TXOVIF |Transmit FIFO Overflow Flag
- * | | |0 = No overflow.
- * | | |1 = Overflow.
- * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1
- * | | |Note2: Write 1 to clear this bit to 0.
- * |[18] |TXTHIF |Transmit FIFO Threshold Flag (Read Only)
- * | | |0 = Data word(s) in FIFO is higher than threshold level.
- * | | |1 = Data word(s) in FIFO is equal or lower than threshold level.
- * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH(I2S_CTL[11:9]) the TXTHIF bit becomes to 1.
- * | | |It keeps at 1 till TXCNT is higher than TXTH after software write TXFIFO register.
- * |[19] |TXFULL |Transmit FIFO Full (Read Only)
- * | | |This bit reflect data word number in transmit FIFO is 8
- * | | |0 = Not full.
- * | | |1 = Full.
- * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
- * | | |This bit reflect data word number in transmit FIFO is zero
- * | | |0 = Not empty.
- * | | |1 = Empty.
- * |[21] |TXBUSY |Transmit Busy (Read Only)
- * | | |0 = Transmit shift buffer is empty.
- * | | |1 = Transmit shift buffer is busy.
- * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out.
- * | | |And set to 1 when 1st data is load to shift buffer.
- * |[22] |RZCIF |Right Channel Zero-Cross Flag
- * | | |It indicates right channel next sample data sign bit is changed or all data bits are zero.
- * | | |0 = No zero-cross.
- * | | |1 = Right channel zero-cross is detected.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[23] |LZCIF |Left Channel Zero-Cross Flag
- * | | |It indicates left channel next sample data sign bit is changed or all data bits are zero.
- * | | |0 = No zero-cross.
- * | | |1 = Left channel zero-cross is detected.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[24:27] |RXCNT |Receive FIFO Level (Read Only)
- * | | |These bits indicate word number in receive FIFO
- * | | |0000 = No data.
- * | | |0001 = 1 word in receive FIFO.
- * | | |....
- * | | |1000 = 8 words in receive FIFO.
- * |[28:31] |TXCNT |Transmit FIFO Level (Read Only)
- * | | |These bits indicate word number in transmit FIFO
- * | | |0000 = No data.
- * | | |0001 = 1 word in transmit FIFO.
- * | | |....
- * | | |1000 = 8 words in transmit FIFO.
- */
- __I uint32_t STATUS;
-
- /**
- * TX
- * ===================================================================================================
- * Offset: 0x10 I2S Transmit FIFO Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |TX |Transmit FIFO Bits
- * | | |I2S contains 8 words (8x32 bit) data buffer for data transmit.
- * | | |Write data to this register to prepare data for transmit.
- * | | |The remaining word number is indicated by TXCNT(I2S_STATUS[31:28]).
- */
- __O uint32_t TX;
-
- /**
- * RX
- * ===================================================================================================
- * Offset: 0x14 I2S Receive FIFO Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |RX |Receive FIFO Bits
- * | | |I2S contains 8 words (8x32 bit) data buffer for data receive.
- * | | |Read this register to get data in FIFO.
- * | | |The remaining data word number is indicated by RXCNT(I2S_STATUS[27:24]).
- */
- __I uint32_t RX;
-
-} I2S_T;
-
-/**
- @addtogroup I2S_CONST I2S Bit Field Definition
- Constant Definitions for I2S Controller
-@{ */
-
-#define I2S_CTL_I2SEN_Pos (0) /*!< I2S CTL: I2SEN Position */
-#define I2S_CTL_I2SEN_Msk (0x1ul << I2S_CTL_I2SEN_Pos) /*!< I2S CTL: I2SEN Mask */
-
-#define I2S_CTL_TXEN_Pos (1) /*!< I2S CTL: TXEN Position */
-#define I2S_CTL_TXEN_Msk (0x1ul << I2S_CTL_TXEN_Pos) /*!< I2S CTL: TXEN Mask */
-
-#define I2S_CTL_RXEN_Pos (2) /*!< I2S CTL: RXEN Position */
-#define I2S_CTL_RXEN_Msk (0x1ul << I2S_CTL_RXEN_Pos) /*!< I2S CTL: RXEN Mask */
-
-#define I2S_CTL_MUTE_Pos (3) /*!< I2S CTL: MUTE Position */
-#define I2S_CTL_MUTE_Msk (0x1ul << I2S_CTL_MUTE_Pos) /*!< I2S CTL: MUTE Mask */
-
-#define I2S_CTL_WDWIDTH_Pos (4) /*!< I2S CTL: WDWIDTH Position */
-#define I2S_CTL_WDWIDTH_Msk (0x3ul << I2S_CTL_WDWIDTH_Pos) /*!< I2S CTL: WDWIDTH Mask */
-
-#define I2S_CTL_MONO_Pos (6) /*!< I2S CTL: MONO Position */
-#define I2S_CTL_MONO_Msk (0x1ul << I2S_CTL_MONO_Pos) /*!< I2S CTL: MONO Mask */
-
-#define I2S_CTL_FORMAT_Pos (7) /*!< I2S CTL: FORMAT Position */
-#define I2S_CTL_FORMAT_Msk (0x1ul << I2S_CTL_FORMAT_Pos) /*!< I2S CTL: FORMAT Mask */
-
-#define I2S_CTL_SLAVE_Pos (8) /*!< I2S CTL: SLAVE Position */
-#define I2S_CTL_SLAVE_Msk (0x1ul << I2S_CTL_SLAVE_Pos) /*!< I2S CTL: SLAVE Mask */
-
-#define I2S_CTL_TXTH_Pos (9) /*!< I2S CTL: TXTH Position */
-#define I2S_CTL_TXTH_Msk (0x7ul << I2S_CTL_TXTH_Pos) /*!< I2S CTL: TXTH Mask */
-
-#define I2S_CTL_RXTH_Pos (12) /*!< I2S CTL: RXTH Position */
-#define I2S_CTL_RXTH_Msk (0x7ul << I2S_CTL_RXTH_Pos) /*!< I2S CTL: RXTH Mask */
-
-#define I2S_CTL_MCLKEN_Pos (15) /*!< I2S CTL: MCLKEN Position */
-#define I2S_CTL_MCLKEN_Msk (0x1ul << I2S_CTL_MCLKEN_Pos) /*!< I2S CTL: MCLKEN Mask */
-
-#define I2S_CTL_RZCEN_Pos (16) /*!< I2S CTL: RZCEN Position */
-#define I2S_CTL_RZCEN_Msk (0x1ul << I2S_CTL_RZCEN_Pos) /*!< I2S CTL: RZCEN Mask */
-
-#define I2S_CTL_LZCEN_Pos (17) /*!< I2S CTL: LZCEN Position */
-#define I2S_CTL_LZCEN_Msk (0x1ul << I2S_CTL_LZCEN_Pos) /*!< I2S CTL: LZCEN Mask */
-
-#define I2S_CTL_TXCLR_Pos (18) /*!< I2S CTL: TXCLR Position */
-#define I2S_CTL_TXCLR_Msk (0x1ul << I2S_CTL_TXCLR_Pos) /*!< I2S CTL: TXCLR Mask */
-
-#define I2S_CTL_RXCLR_Pos (19) /*!< I2S CTL: RXCLR Position */
-#define I2S_CTL_RXCLR_Msk (0x1ul << I2S_CTL_RXCLR_Pos) /*!< I2S CTL: RXCLR Mask */
-
-#define I2S_CTL_TXPDMAEN_Pos (20) /*!< I2S CTL: TXPDMAEN Position */
-#define I2S_CTL_TXPDMAEN_Msk (0x1ul << I2S_CTL_TXPDMAEN_Pos) /*!< I2S CTL: TXPDMAEN Mask */
-
-#define I2S_CTL_RXPDMAEN_Pos (21) /*!< I2S CTL: RXPDMAEN Position */
-#define I2S_CTL_RXPDMAEN_Msk (0x1ul << I2S_CTL_RXPDMAEN_Pos) /*!< I2S CTL: RXPDMAEN Mask */
-
-#define I2S_CTL_RXLCH_Pos (23) /*!< I2S CTL: RXLCH Position */
-#define I2S_CTL_RXLCH_Msk (0x1ul << I2S_CTL_RXLCH_Pos) /*!< I2S CTL: RXLCH Mask */
-
-#define I2S_CTL_PCMEN_Pos (24) /*!< I2S CTL: PCMEN Position */
-#define I2S_CTL_PCMEN_Msk (0x1ul << I2S_CTL_PCMEN_Pos) /*!< I2S CTL: PCMEN Mask */
-
-#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S CLKDIV: MCLKDIV Position */
-#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S CLKDIV: MCLKDIV Mask */
-
-#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S CLKDIV: BCLKDIV Position */
-#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S CLKDIV: BCLKDIV Mask */
-
-#define I2S_IEN_RXUDIEN_Pos (0) /*!< I2S IEN: RXUDIEN Position */
-#define I2S_IEN_RXUDIEN_Msk (0x1ul << I2S_IEN_RXUDIEN_Pos) /*!< I2S IEN: RXUDIEN Mask */
-
-#define I2S_IEN_RXOVIEN_Pos (1) /*!< I2S IEN: RXOVIEN Position */
-#define I2S_IEN_RXOVIEN_Msk (0x1ul << I2S_IEN_RXOVIEN_Pos) /*!< I2S IEN: RXOVIEN Mask */
-
-#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S IEN: RXTHIEN Position */
-#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S IEN: RXTHIEN Mask */
-
-#define I2S_IEN_TXUDIEN_Pos (8) /*!< I2S IEN: TXUDIEN Position */
-#define I2S_IEN_TXUDIEN_Msk (0x1ul << I2S_IEN_TXUDIEN_Pos) /*!< I2S IEN: TXUDIEN Mask */
-
-#define I2S_IEN_TXOVIEN_Pos (9) /*!< I2S IEN: TXOVIEN Position */
-#define I2S_IEN_TXOVIEN_Msk (0x1ul << I2S_IEN_TXOVIEN_Pos) /*!< I2S IEN: TXOVIEN Mask */
-
-#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S IEN: TXTHIEN Position */
-#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S IEN: TXTHIEN Mask */
-
-#define I2S_IEN_RZCIEN_Pos (11) /*!< I2S IEN: RZCIEN Position */
-#define I2S_IEN_RZCIEN_Msk (0x1ul << I2S_IEN_RZCIEN_Pos) /*!< I2S IEN: RZCIEN Mask */
-
-#define I2S_IEN_LZCIEN_Pos (12) /*!< I2S IEN: LZCIEN Position */
-#define I2S_IEN_LZCIEN_Msk (0x1ul << I2S_IEN_LZCIEN_Pos) /*!< I2S IEN: LZCIEN Mask */
-
-#define I2S_STATUS_I2SIF_Pos (0) /*!< I2S STATUS: I2SIF Position */
-#define I2S_STATUS_I2SIF_Msk (0x1ul << I2S_STATUS_I2SIF_Pos) /*!< I2S STATUS: I2SIF Mask */
-
-#define I2S_STATUS_RXIF_Pos (1) /*!< I2S STATUS: RXIF Position */
-#define I2S_STATUS_RXIF_Msk (0x1ul << I2S_STATUS_RXIF_Pos) /*!< I2S STATUS: RXIF Mask */
-
-#define I2S_STATUS_TXIF_Pos (2) /*!< I2S STATUS: TXIF Position */
-#define I2S_STATUS_TXIF_Msk (0x1ul << I2S_STATUS_TXIF_Pos) /*!< I2S STATUS: TXIF Mask */
-
-#define I2S_STATUS_RIGHT_Pos (3) /*!< I2S STATUS: RIGHT Position */
-#define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) /*!< I2S STATUS: RIGHT Mask */
-
-#define I2S_STATUS_RXUDIF_Pos (8) /*!< I2S STATUS: RXUDIF Position */
-#define I2S_STATUS_RXUDIF_Msk (0x1ul << I2S_STATUS_RXUDIF_Pos) /*!< I2S STATUS: RXUDIF Mask */
-
-#define I2S_STATUS_RXOVIF_Pos (9) /*!< I2S STATUS: RXOVIF Position */
-#define I2S_STATUS_RXOVIF_Msk (0x1ul << I2S_STATUS_RXOVIF_Pos) /*!< I2S STATUS: RXOVIF Mask */
-
-#define I2S_STATUS_RXTHIF_Pos (10) /*!< I2S STATUS: RXTHIF Position */
-#define I2S_STATUS_RXTHIF_Msk (0x1ul << I2S_STATUS_RXTHIF_Pos) /*!< I2S STATUS: RXTHIF Mask */
-
-#define I2S_STATUS_RXFULL_Pos (11) /*!< I2S STATUS: RXFULL Position */
-#define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) /*!< I2S STATUS: RXFULL Mask */
-
-#define I2S_STATUS_RXEMPTY_Pos (12) /*!< I2S STATUS: RXEMPTY Position */
-#define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) /*!< I2S STATUS: RXEMPTY Mask */
-
-#define I2S_STATUS_TXUDIF_Pos (16) /*!< I2S STATUS: TXUDIF Position */
-#define I2S_STATUS_TXUDIF_Msk (0x1ul << I2S_STATUS_TXUDIF_Pos) /*!< I2S STATUS: TXUDIF Mask */
-
-#define I2S_STATUS_TXOVIF_Pos (17) /*!< I2S STATUS: TXOVIF Position */
-#define I2S_STATUS_TXOVIF_Msk (0x1ul << I2S_STATUS_TXOVIF_Pos) /*!< I2S STATUS: TXOVIF Mask */
-
-#define I2S_STATUS_TXTHIF_Pos (18) /*!< I2S STATUS: TXTHIF Position */
-#define I2S_STATUS_TXTHIF_Msk (0x1ul << I2S_STATUS_TXTHIF_Pos) /*!< I2S STATUS: TXTHIF Mask */
-
-#define I2S_STATUS_TXFULL_Pos (19) /*!< I2S STATUS: TXFULL Position */
-#define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) /*!< I2S STATUS: TXFULL Mask */
-
-#define I2S_STATUS_TXEMPTY_Pos (20) /*!< I2S STATUS: TXEMPTY Position */
-#define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) /*!< I2S STATUS: TXEMPTY Mask */
-
-#define I2S_STATUS_TXBUSY_Pos (21) /*!< I2S STATUS: TXBUSY Position */
-#define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) /*!< I2S STATUS: TXBUSY Mask */
-
-#define I2S_STATUS_RZCIF_Pos (22) /*!< I2S STATUS: RZCIF Position */
-#define I2S_STATUS_RZCIF_Msk (0x1ul << I2S_STATUS_RZCIF_Pos) /*!< I2S STATUS: RZCIF Mask */
-
-#define I2S_STATUS_LZCIF_Pos (23) /*!< I2S STATUS: LZCIF Position */
-#define I2S_STATUS_LZCIF_Msk (0x1ul << I2S_STATUS_LZCIF_Pos) /*!< I2S STATUS: LZCIF Mask */
-
-#define I2S_STATUS_RXCNT_Pos (24) /*!< I2S STATUS: RXCNT Position */
-#define I2S_STATUS_RXCNT_Msk (0xful << I2S_STATUS_RXCNT_Pos) /*!< I2S STATUS: RXCNT Mask */
-
-#define I2S_STATUS_TXCNT_Pos (28) /*!< I2S STATUS: TXCNT Position */
-#define I2S_STATUS_TXCNT_Msk (0xful << I2S_STATUS_TXCNT_Pos) /*!< I2S STATUS: TXCNT Mask */
-
-#define I2S_TX_TX_Pos (0) /*!< I2S TX: TX Position */
-#define I2S_TX_TX_Msk (0xfffffffful << I2S_TX_TX_Pos) /*!< I2S TX: TX Mask */
-
-#define I2S_RX_RX_Pos (0) /*!< I2S RX: RX Position */
-#define I2S_RX_RX_Msk (0xfffffffful << I2S_RX_RX_Pos) /*!< I2S RX: RX Mask */
-
-/**@}*/ /* I2S_CONST */
-/**@}*/ /* end of I2S register group */
-
-
-/*---------------------- OP Amplifier -------------------------*/
-/**
- @addtogroup OPA OP Amplifier(OPA)
- Memory Mapped Structure for OPA Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 OP Amplifier Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OPEN0 |OP Amplifier 0 Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |Note: OP Amplifier 0 output needs wait stable 20us[MS1] after OPEN0 is first set.
- * | | |[MS1]alpha test
- * |[1] |OPEN1 |OP Amplifier 1 Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |Note: OP Amplifier 1 output needs wait stable 20us[MS1] after OPEN1 is first set.
- * | | |[MS1]alpha test
- * |[4] |OPSMTEN0 |OP Amplifier 0 Schmitt Trigger Non-Inverting Buffer Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |OPSMTEN1 |OP Amplifier 1 Schmitt Trigger Non-Inverting Buffer Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[8] |OPAIE0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Control
- * | | |0 = OP Amplifier 0 digital output interrupt function Disabled.
- * | | |1 = OP Amplifier 0 digital output interrupt function Enabled.
- * | | |The OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE0 is set to 1, a comparator interrupt request is generated.
- * |[9] |OPAIE1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Control
- * | | |0 = OP Amplifier 1 digital output interrupt function Disabled.
- * | | |1 = OP Amplifier 1 digital output interrupt function Enabled.
- * | | |OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE1 is set to 1, a comparator interrupt request is generated.
- */
- __IO uint32_t CTL;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x04 OP Amplifier Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OPDO0 |OP Amplifier 0 Digital Output
- * | | |Synchronized to the APB clock to allow reading by software.
- * | | |Cleared when the Schmitt trigger buffer is disabled (OPSMTEN0 = 0).
- * |[1] |OPDO1 |OP Amplifier 1 Digital Output
- * | | |Synchronized to the APB clock to allow reading by software.
- * | | |Cleared when the Schmitt trigger buffer is disabled (OPSMTEN1 = 0).
- * |[4] |OPDF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
- * | | |OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state.
- * | | |This bit is cleared by writing 1 to it.
- * |[5] |OPDF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag
- * | | |OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state.
- * | | |This bit is cleared by writing 1 to it.
- */
- __IO uint32_t STATUS;
-
-} OPA_T;
-
-/**
- @addtogroup OPA_CONST OPA Bit Field Definition
- Constant Definitions for OPA Controller
-@{ */
-
-#define OPA_CTL_OPEN0_Pos (0) /*!< OPA CTL: OPEN0 Position */
-#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA CTL: OPEN0 Mask */
-
-#define OPA_CTL_OPEN1_Pos (1) /*!< OPA CTL: OPEN1 Position */
-#define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA CTL: OPEN1 Mask */
-
-#define OPA_CTL_OPSMTEN0_Pos (4) /*!< OPA CTL: OPSMTEN0 Position */
-#define OPA_CTL_OPSMTEN0_Msk (0x1ul << OPA_CTL_OPSMTEN0_Pos) /*!< OPA CTL: OPSMTEN0 Mask */
-
-#define OPA_CTL_OPSMTEN1_Pos (5) /*!< OPA CTL: OPSMTEN1 Position */
-#define OPA_CTL_OPSMTEN1_Msk (0x1ul << OPA_CTL_OPSMTEN1_Pos) /*!< OPA CTL: OPSMTEN1 Mask */
-
-#define OPA_CTL_OPAIE0_Pos (8) /*!< OPA CTL: OPAIE0 Position */
-#define OPA_CTL_OPAIE0_Msk (0x1ul << OPA_CTL_OPAIE0_Pos) /*!< OPA CTL: OPAIE0 Mask */
-
-#define OPA_CTL_OPAIE1_Pos (9) /*!< OPA CTL: OPAIE1 Position */
-#define OPA_CTL_OPAIE1_Msk (0x1ul << OPA_CTL_OPAIE1_Pos) /*!< OPA CTL: OPAIE1 Mask */
-
-#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA STATUS: OPDO0 Position */
-#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA STATUS: OPDO0 Mask */
-
-#define OPA_STATUS_OPDO1_Pos (1) /*!< OPA STATUS: OPDO1 Position */
-#define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA STATUS: OPDO1 Mask */
-
-#define OPA_STATUS_OPDF0_Pos (4) /*!< OPA STATUS: OPDF0 Position */
-#define OPA_STATUS_OPDF0_Msk (0x1ul << OPA_STATUS_OPDF0_Pos) /*!< OPA STATUS: OPDF0 Mask */
-
-#define OPA_STATUS_OPDF1_Pos (5) /*!< OPA STATUS: OPDF1 Position */
-#define OPA_STATUS_OPDF1_Msk (0x1ul << OPA_STATUS_OPDF1_Pos) /*!< OPA STATUS: OPDF1 Mask */
-
-/**@}*/ /* OPA_CONST */
-/**@}*/ /* end of OPA register group */
-
-
-/*---------------------- USB On-The-Go Controller -------------------------*/
-/**
- @addtogroup OTG USB On-The-Go Controller(OTG)
- Memory Mapped Structure for OTG Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 OTG Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |VBUSDROP |Drop The VUSB Bus
- * | | |If user application running on this OTG A-device wants to conserve power consumption, set this bit to high When set this bit to TRUE, BUSREQ shall be cleared as well.
- * | | |0 = Did Not drop the VBUS and keep going on USB data transfers.
- * | | |1 = Drop the VBUS to conserve power consumption.
- * |[1] |BUSREQ |OTG A-Device Bus Request
- * | | |If user application of an OTG A-device wants to do data transfers via USB bus, set this bit to high Otherwise if user application won't use the bus any more, set this bit to low.
- * | | |This bit will be automatically cleared if VBUSDROP bit is set to TRUE.
- * |[2] |HNPREQEN |OTG B-Device HNP Enable/Request
- * | | |Set this bit to TRUE after the OTG A-device successfully sends a SetFeature(b_hnp_enable) command to the OTG B-device This bit will be cleared automatically when a bus reset or SESS_VLD goes from TRUE to FALSE.
- * |[4] |OTGEN |OTG Function Enable Control
- * | | |If USB is configured as OTG device, this bit must set high.
- * | | |0= OTG function Disabled.
- * | | |1 = OTG function Enabled.
- * |[7] |PDEVCKON |Force OTG PHY Output Clock To USB Device
- * | | |If software configures OTG controller as OTG device and OTG device as A-device, OTG controller will output OTG PHY clock (30 MHz) to USB device only when OTG device as A-peripheral.
- * | | |If software needs to configure USB device before role change (from A-Host to A-Peripheral), software can set this bit high to output OTG PHY clock to USB device.
- * | | |0= USB device clock is available only when OTG device as a peripheral.
- * | | |1 = Force output OTG PHY clock to USB device.
- * |[8] |WKEN |OTG Wake-Up Enable Control
- * | | |0= OTG ID pin status change wake-up Disabled.
- * | | |1 = OTG ID pin status change wake-up Enabled.
- */
- __IO uint32_t CTL;
-
- /**
- * PHYCTL
- * ===================================================================================================
- * Offset: 0x04 OTG PHY Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SWPDEN |Software Control Pull-Down On Data Lines Enable Control
- * | | |0 = Pull-down resistors on data lines is controlled by OTG control logic.
- * | | |1 = Pull-down resistors on data lines is controlled by software.
- * | | |Note: Software must set this bit high before controlling DPPDEN and DMPDEN.
- * |[1] |DPPDEN |D+ Pull-Down Enable Control Set SWPDEN to TRUE before using this function
- * | | |0 = 15 kOhm resistor pull-down on D+ pin Disabled.
- * | | |1 = 15 kOhm resistor pull-down on D+ pin Enabled.
- * |[2] |DMPDEN |D- Pull-Down Enable Control Set SWPDEN to TRUE before using this function
- * | | |0 = 15 kOhm resistor pull-down on D- pin Disabled.
- * | | |1 = 15 kOhm resistor pull-down on D- pin Enabled.
- * |[5] |VBSTSPOL |Off-Chip USB VBUS Power Status Polarity
- * | | |The polarity of off-chip USB VBUS LDO valid depends on the selected component.
- * | | |This bit provides the inversed option of off-chip USB VBUS LDO valid.
- * | | |0 = The polarity of off-chip USB VBUS LDO valid not inversed.
- * | | |1 = The polarity of off-chip USB VBUS LDO valid inversed.
- * |[6] |VBENPOL |Off-Chip USB VBUS Power Enable Polarity
- * | | |The OTG controller will enable off-chip USB VBUS LDO to provide VBUS power when need.
- * | | |The polarity of enabling off-chip BSU VBUS LDO (high active or low active) depends on the selected component.
- * | | |This bit provides the inverse option of off-chip USB VBUS LDO enable.
- * | | |0 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller not inversed.
- * | | |1 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller inversed.
- * |[7] |IDDETEN |ID Detection Enable
- * | | |0 = Sampling on ID pin Enabled.
- * | | |1 = Sampling on ID pin Disabled.
- * |[8] |PHYCLK |PHY Input Clock Selection
- * | | |0 = PHY input clock is12 MHz.
- * | | |1 = PHY input clock is 24 MHz.
- * |[9] |OTGPHYEN |OTG PHY Enable Control When Device Configured As OTG-Device
- * | | |When device is configured as OTG-device, hardware will not enable OTG PHY automatically.
- * | | |Software can set OTG_EN to enable OTG PHY.
- * | | |0 = OTG PHY Disabled.
- * | | |1 = OTG PHY Enabled.
- */
- __IO uint32_t PHYCTL;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x08 OTG Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ROLECHGIEN|Role(Host Or Peripheral) Changed Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[1] |VBEIEN |VBUS Error Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
- * |[2] |SRPFIEN |SRP Fail Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[3] |HNPFIEN |HNP Fail Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[4] |GOIDLEIEN |OTG Device Goes IDLE State Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * | | |Note: Going to idle state means going to a_idle or b_idle state.
- * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
- * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Control
- * | | |0 = This device as a peripheral interrupt Disabled.
- * | | |1 = This device as a peripheral interrupt Enabled.
- * |[7] |HOSTIEN |Act As Host Interrupt Enable Control
- * | | |0= This device as a host interrupt Disabled.
- * | | |1 = This device as a host interrupt Enabled.
- * |[8] |BVLDCHGIEN|B-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Control
- * | | |0 =Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[9] |AVLDCHGIEN|A-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[10] |VBCHGIEN |VBVALID Status Changed Interrupt Enable
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Control 0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Control
- * | | |0 = Interrupt Disabled.
- * | | |1 = Interrupt Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x0C OTG Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
- * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host
- * | | |Note: Write 1 to clear this flag.
- * |[1] |VBEIF |VBUS Error Interrupt Status
- * | | |This flag will be set in one of two conditions
- * | | |l One case is that voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A device starting to drive.
- * | | |l The other case is that the supplied VBUS drops below a minimum valid threshold due to the overcurrent condition.
- * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
- * |[2] |SRPFIF |SRP Fail Interrupt Status
- * | | |After initiating SRP, an OTG B-device will wait at least TB_SRP_FAIL min, defined in OTG specification, for the OTG A-device respond This flag is set when the OTG B-device didn't get the response from the remote A-device to turn VBUS on and generate a bus reset.
- * | | |Note: Write 1 to clear this flag.
- * |[3] |HNPFIF |HNP Fail Interrupt Status
- * | | |When A-device has granted B-device to be host and USB bus in SE0 state, this bit will be set in specified interval (b_ase0_brst_tmr, defined in OTG spec.
- * | | |specification), A-device does not signal connect signal.
- * | | |Note: Write 1 to clear this flag.
- * |[4] |GOIDLEIF |OTG Device Goes IDLE Interrupt Status
- * | | |Flag is set if the OTG device transfers from non-idle state to idle state.
- * | | |The OTG device will be neither a host nor a peripheral.
- * | | |0 = OTG device does not go back to idle state(a_idle or b_idle).
- * | | |1 = OTG device go back to idle state(a_idle or b_idle).
- * | | |Note: Write 1 to clear this flag.
- * |[5] |IDCHGIF |ID State Change Interrupt Status
- * | | |0 = IDSTS not toggled.
- * | | |1 = IDSTS from high to low or from low to high.
- * | | |Note1: OTG_CTL[BUSREQ] will be cleared when IDDIG is high.
- * | | |Note2: Write 1 to clear this flag.
- * |[6] |PDEVIF |Act As Peripheral Interrupt Status
- * | | |0= This device does not act as a peripheral.
- * | | |1 = This device acts as a peripheral.
- * | | |Note: Write 1 to clear this flag.
- * |[7] |HOSTIF |Act As Host Interrupt Status
- * | | |0= This device does not act as a host.
- * | | |1 = This device acts as a host.
- * | | |Note: Write 1 to clear this flag.
- * |[8] |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
- * | | |0 = BVLD not toggled.
- * | | |1 = BVLD from high to low or low to high.
- * | | |Note: Write 1 to clear this status.
- * |[9] |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
- * | | |0 = AVLD not toggled.
- * | | |1 = AVLD from high to low or low to high.
- * | | |Note: Write 1 to clear this flag.
- * |[10] |VBCHGIF |VBVALID State Change Interrupt Status
- * | | |0 = VBUS_VLD not toggled.
- * | | |1 = VBUSVLD from high to low or from low to high.
- * | | |Note: Write 1 to clear this flag.
- * |[11] |SECHGIF |SESSEND State Change Interrupt Status
- * | | |0 = Session end not toggled.
- * | | |1 = SESSEND from high to low or from low to high.
- * | | |Note: Write 1 to clear this flag.
- * |[13] |SRPDETIF |SRP Detected Interrupt Status
- * | | |0 = SRP not detected.
- * | | |1 = SRP detected.
- * | | |Note: Write 1 to clear this status.
- */
- __IO uint32_t INTSTS;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x10 Functional Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OVERCUR |Over current Condition
- * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A device starting to drive
- * | | |0 = OTG A-device drives VBUS successfully.
- * | | |1 = Over current condition occurred.
- * |[1] |IDSTS |ID Pin State Of Mini-B/Micro-Plug
- * | | |0 = Mini-A/Micro-A plug is attached.
- * | | |1 = Mini-B/Micro-B plug is attached.
- * |[2] |SESSEND |Session End Status
- * | | |0 = VBUS > 0.8V.
- * | | |1 = VBUS < 0.2V.
- * |[3] |BVLID |B-Device Session Valid Status
- * | | |0 = VBUS < 0.8V.
- * | | |1 = VBUS > 4V.
- * |[4] |AVLD |A-Device Session Valid Status
- * | | |0 = VBUS < 0.8V.
- * | | |1 = VBUS > 2V.
- * |[5] |VBUSVLD |VBUS Valid Status
- * | | |0 = VBUS < 4.4V.
- * | | |1 = VBUS > 4.75V.
- */
- __I uint32_t STATUS;
-
-} OTG_T;
-
-/**
- @addtogroup OTG_CONST OTG Bit Field Definition
- Constant Definitions for OTG Controller
-@{ */
-
-#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG CTL: VBUSDROP Position */
-#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG CTL: VBUSDROP Mask */
-
-#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG CTL: BUSREQ Position */
-#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG CTL: BUSREQ Mask */
-
-#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG CTL: HNPREQEN Position */
-#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG CTL: HNPREQEN Mask */
-
-#define OTG_CTL_OTGEN_Pos (4) /*!< OTG CTL: OTGEN Position */
-#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG CTL: OTGEN Mask */
-
-#define OTG_CTL_PDEVCKON_Pos (7) /*!< OTG CTL: PDEVCKON Position */
-#define OTG_CTL_PDEVCKON_Msk (0x1ul << OTG_CTL_PDEVCKON_Pos) /*!< OTG CTL: PDEVCKON Mask */
-
-#define OTG_CTL_WKEN_Pos (8) /*!< OTG CTL: WKEN Position */
-#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG CTL: WKEN Mask */
-
-#define OTG_PHYCTL_SWPDEN_Pos (0) /*!< OTG PHYCTL: SWPDEN Position */
-#define OTG_PHYCTL_SWPDEN_Msk (0x1ul << OTG_PHYCTL_SWPDEN_Pos) /*!< OTG PHYCTL: SWPDEN Mask */
-
-#define OTG_PHYCTL_DPPDEN_Pos (1) /*!< OTG PHYCTL: DPPDEN Position */
-#define OTG_PHYCTL_DPPDEN_Msk (0x1ul << OTG_PHYCTL_DPPDEN_Pos) /*!< OTG PHYCTL: DPPDEN Mask */
-
-#define OTG_PHYCTL_DMPDEN_Pos (2) /*!< OTG PHYCTL: DMPDEN Position */
-#define OTG_PHYCTL_DMPDEN_Msk (0x1ul << OTG_PHYCTL_DMPDEN_Pos) /*!< OTG PHYCTL: DMPDEN Mask */
-
-#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG PHYCTL: VBSTSPOL Position */
-#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG PHYCTL: VBSTSPOL Mask */
-
-#define OTG_PHYCTL_VBENPOL_Pos (6) /*!< OTG PHYCTL: VBUSPOL Position */
-#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG PHYCTL: VBUSPOL Mask */
-
-#define OTG_PHYCTL_IDDETEN_Pos (7) /*!< OTG PHYCTL: IDDETEN Position */
-#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG PHYCTL: IDDETEN Mask */
-
-#define OTG_PHYCTL_PHYCLK_Pos (8) /*!< OTG PHYCTL: PHYCLK Position */
-#define OTG_PHYCTL_PHYCLK_Msk (0x1ul << OTG_PHYCTL_PHYCLK_Pos) /*!< OTG PHYCTL: PHYCLK Mask */
-
-#define OTG_PHYCTL_OTGPHYEN_Pos (9) /*!< OTG PHYCTL: OTGPHYEN Position */
-#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG PHYCTL: OTGPHYEN Mask */
-
-#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG INTEN: ROLECHGIEN Position */
-#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG INTEN: ROLECHGIEN Mask */
-
-#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG INTEN: VBEIEN Position */
-#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG INTEN: VBEIEN Mask */
-
-#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG INTEN: SRPFIEN Position */
-#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG INTEN: SRPFIEN Mask */
-
-#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG INTEN: HNPFIEN Position */
-#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG INTEN: HNPFIEN Mask */
-
-#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG INTEN: GOIDLEIEN Position */
-#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG INTEN: GOIDLEIEN Mask */
-
-#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG INTEN: IDCHGIEN Position */
-#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG INTEN: IDCHGIEN Mask */
-
-#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG INTEN: PDEVIEN Position */
-#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG INTEN: PDEVIEN Mask */
-
-#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG INTEN: HOSTIEN Position */
-#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG INTEN: HOSTIEN Mask */
-
-#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG INTEN: BVLDCHGIEN Position */
-#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG INTEN: BVLDCHGIEN Mask */
-
-#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG INTEN: AVLDCHGIEN Position */
-#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG INTEN: AVLDCHGIEN Mask */
-
-#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG INTEN: VBCHGIEN Position */
-#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG INTEN: VBCHGIEN Mask */
-
-#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG INTEN: SECHGIEN Position */
-#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG INTEN: SECHGIEN Mask */
-
-#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG INTEN: SRPDETIEN Position */
-#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG INTEN: SRPDETIEN Mask */
-
-#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG INTSTS: ROLECHGIF Position */
-#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG INTSTS: ROLECHGIF Mask */
-
-#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG INTSTS: VBEIF Position */
-#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG INTSTS: VBEIF Mask */
-
-#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG INTSTS: SRPFIF Position */
-#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG INTSTS: SRPFIF Mask */
-
-#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG INTSTS: HNPFIF Position */
-#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG INTSTS: HNPFIF Mask */
-
-#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG INTSTS: GOIDLEIF Position */
-#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG INTSTS: GOIDLEIF Mask */
-
-#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG INTSTS: IDCHGIF Position */
-#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG INTSTS: IDCHGIF Mask */
-
-#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG INTSTS: PDEVIF Position */
-#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG INTSTS: PDEVIF Mask */
-
-#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG INTSTS: HOSTIF Position */
-#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG INTSTS: HOSTIF Mask */
-
-#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG INTSTS: BVLDCHGIF Position */
-#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG INTSTS: BVLDCHGIF Mask */
-
-#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG INTSTS: AVLDCHGIF Position */
-#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG INTSTS: AVLDCHGIF Mask */
-
-#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG INTSTS: VBCHGIF Position */
-#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG INTSTS: VBCHGIF Mask */
-
-#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG INTSTS: SECHGIF Position */
-#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG INTSTS: SECHGIF Mask */
-
-#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG INTSTS: SRPDETIF Position */
-#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG INTSTS: SRPDETIF Mask */
-
-#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG STATUS: OVERCUR Position */
-#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG STATUS: OVERCUR Mask */
-
-#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG STATUS: IDSTS Position */
-#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG STATUS: IDSTS Mask */
-
-#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG STATUS: SESSEND Position */
-#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG STATUS: SESSEND Mask */
-
-#define OTG_STATUS_BVLD_Pos (3) /*!< OTG STATUS: BVLD Position */
-#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG STATUS: BVLD Mask */
-
-#define OTG_STATUS_AVLD_Pos (4) /*!< OTG STATUS: AVLD Position */
-#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG STATUS: AVLD Mask */
-
-#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG STATUS: VBUSVLD Position */
-#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG STATUS: VBUSVLD Mask */
-
-/**@}*/ /* OTG_CONST */
-/**@}*/ /* end of OTG register group */
-
-
-/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
-/**
- @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
- Memory Mapped Structure for PDMA Controller
-@{ */
-
-typedef struct {
-
- /**
- * DSCTx_CTL
- * ===================================================================================================
- * Offset: 0x00 Descriptor Table Control Register of PDMA Channel x
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |OPMODE |PDMA Operation Mode Selection
- * | | |00 = Stop Mode.
- * | | |Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to stop mode automatically.
- * | | |01 = Basic Mode.
- * | | |The descriptor table only has one task.
- * | | |When this task is finished, the PDMA_INTSTS[x] will be asserted.
- * | | |10 = Scatter-Gather Mode.
- * | | |When operating in this mode, user must give the next descriptor table address in EMBTA_NTAAR register; PDMA will ignore this task, and then load the next task to execute.
- * | | |Note: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete.
- * |[2] |TXTYPE |Request Type
- * | | |0 = Burst request type.
- * | | |1 = Single request type.
- * |[4:6] |BURSIZE |Burst Size
- * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
- * | | |But if in Single Request Type, this field is not useful and only 1 transfer item been transmitted for each transfer.
- * | | |000 = 128 transfers.
- * | | |001 = 64 transfers.
- * | | |010 = 32 transfers.
- * | | |011 = 16 transfers.
- * | | |100 = 8 transfers.
- * | | |101 = 4 transfers.
- * | | |110 = 2 transfers.
- * | | |111 = 1 transfers.
- * |[7] |TBINTDIS |Table Interrupt Disable Control
- * | | |This field can be used to decide whether to enable table interrupt or not.
- * | | |When with transfer done flag, this bit is only used for scatter-gather mode.
- * | | |If the TBINTDIS bit is enabled when PDMA finishes this task, there will no any interrupt generated.
- * | | |However, with the table empty flag, this bit is also useful.
- * | | |If it is set to '1', the TEMPTYF will not be set when this situation has happened.
- * | | |0 = Table interrupt Enabled.
- * | | |1 = Table interrupt Disabled.
- * |[8:9] |SAINC |Source Address Increment
- * | | |This field is used to set the source address increment size
- * | | |11 = No Increment (Fixed Address.).
- * | | |Other = Increment and size is depended on TXWIDTH selection.
- * |[10:11] |DAINC |Destination Address Increment
- * | | |This field is used to set the destination address increment size
- * | | |11 = No Increment (Fixed Address.).
- * | | |Other = Increment and size is depended on TXWIDTH selection.
- * |[12:13] |TXWIDTH |Transfer Width Selection
- * | | |This field is used for transfer width.
- * | | |00 = 8 bits for every transfer item.
- * | | |01 = 16 bits for every transfer item.
- * | | |10 = 32 bits for every transfer item.
- * | | |11 = Reserved.
- * | | |Note: The PDMA transfer source address (EMBTA_ENDSAR) and PDMA transfer destination address (EMBTA_ENDDAR) should be alignment under the TXWIDTH selection
- * |[16:29] |TXCNT |Transfer Count
- * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
- * | | |Note: When PDMA finish each transfer item, this field will be decrease imminently
- */
- __IO uint32_t CTL;
-
- /**
- * DSCTx_ENDSA
- * ===================================================================================================
- * Offset: 0x04 End Source Address Register of PDMA Channel x
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ENDSA |PDMA Transfer Ending Source Address Bits
- * | | |This field indicates a 32-bit ending source address of PDMA.
- * | | |Note: If the source start address is 0x2000_0000, the transfer count is 0x100 and the source address increment is word, this field must be filled 0x2000_0400.
- * | | |The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)".
- */
- __IO uint32_t ENDSA;
-
- /**
- * DSCTx_ENDDA
- * ===================================================================================================
- * Offset: 0x08 End Destination Address Register of PDMA Channel x
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ENDDA |PDMA Transfer Ending Destination Address Bits
- * | | |This field indicates a 32-bit ending destination address of PDMA.
- * | | |Note: If the destination start address is 0x2000_0000, the transfer count is 0x100 and the destination address increment is word, this field must be filled 0x2000_0400.
- * | | |The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)".
- */
- __IO uint32_t ENDDA;
-
- /**
- * DSCTx_NEXT
- * ===================================================================================================
- * Offset: 0x0C Scatter-Gather Descriptor Table Offset Address of PDMA Channel x
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2:15] |NEXT |PDMA Next Description Table Offset Address Bits
- * | | |This field indicates the offset of next descriptor table address in system memory.
- * | | |Note1: The next descriptor table address must be word boundary.
- * | | |Note2: The system memory based address is 0x2000_0000 (PDMA_ETADDR), if the next descriptor table is 0x2000_0100, that this field must fill 0x0100.
- * | | |Note3: Before filled transfer task in the description table, user must check if the descriptor table is complete.
- */
- __IO uint32_t NEXT;
-
-} DSCT_T;
-
-typedef struct {
- DSCT_T DSCT[16];
- uint32_t RESERVE0[192];
-
- /**
- * CHCTL
- * ===================================================================================================
- * Offset: 0x400 PDMA Channel Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CHEN |PDMA Channel Enable Control Bit[X]
- * | | |Set this bit to 1 to enable PDMA[x] operation.
- * | | |0 = PDMA channel [x] Disabled.
- * | | |1 = PDMA channel [x] Enabled.
- * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
- * | | |Note2: Software reset (writing 0xFFFF_FFF to PDMA_STOP register) will clear this bit.
- * | | |Note3: If each channel is not set as enabled, each channel cannot be active.
- */
- __IO uint32_t CHCTL;
-
- /**
- * STOP
- * ===================================================================================================
- * Offset: 0x404 PDMA Stop Transfer Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |STOP |PDMA Stop Transfer Bit [X]
- * | | |User can stop the PDMA transfer by software reset (writing all '1' to PDMA_STOP register) or by PDMA_STOP register.
- * | | |The difference between software reset and PDMA_STOP register is when software set software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit and request active flag will be cleared to '0'.
- * | | |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit and request active flag.
- * | | |Software can poll channel enable bit to know if the on-going transfer is finished.
- * | | |0 = No effect.
- * | | |1 = Stop PDMA transfer[x].
- * | | |Note1: This field is Write-Only
- * | | |Note2: Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the embedded table will not be reset).
- */
- __O uint32_t STOP;
-
- /**
- * SWREQ
- * ===================================================================================================
- * Offset: 0x408 PDMA Software Request Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SWREQ |PDMA Software Request Bit [X]
- * | | |Set this bit to 1 to generate a software request to PDMA [x].
- * | | |0 = No effect.
- * | | |1 = Generate a software request.
- * | | |Note1: This field is Write-Only.
- * | | |Software can indicate which channel is on active by reading PDMA_TRGSTS register.
- * | | |Active flag may be triggered by software request or peripheral request.
- * | | |Note2: If user does not enable each PDMA channel, the software request will be ignored.
- */
- __O uint32_t SWREQ;
-
- /**
- * TRGSTS
- * ===================================================================================================
- * Offset: 0x40C PDMA Request Active Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |REQSTS |PDMA Request Active Flag [X]
- * | | |This flag indicates whether channel[x] have a request or not.
- * | | |0 = Have no requests.
- * | | |1 = Have a request.
- * | | |Note1: The request may come from software request (SWREQ) or peripheral request.
- * | | |Note2: When PDMA finishes channel transfer, this bit will be cleared automatically
- * | | |Note3: Software reset (setting PDMA_STOP to 0xFFFF_FFFF) will clear this bit.
- */
- __I uint32_t TRGSTS;
-
- /**
- * PRISET
- * ===================================================================================================
- * Offset: 0x410 PDMA Fixed Priority Setting Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FPRISET |PDMA Fixed Priority Setting Bit[X]
- * | | |Set this bit to 1 to enable fix priority level.
- * | | |0 = No effect.
- * | | |1 = Set PDMA channel [x] be fixed priority channel.
- * | | |The PDMA channel priority is shown in the following table.
- */
- __IO uint32_t PRISET;
-
- /**
- * PRICLR
- * ===================================================================================================
- * Offset: 0x414 PDMA Fixed Priority Clear Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FPRICLR |PDMA Fix Priority Clear Bit [X]
- * | | |Set this bit to 1 to clear fixed priority level.
- * | | |0 = No effect.
- * | | |1 = Set PDMA channel [x] to be round-robin priority channel.
- * | | |Note: This field is Write-Only, and software can indicate the channel priority by reading PDMA_FPIOSEL register.
- */
- __O uint32_t PRICLR;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x418 PDMA Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |INTEN |PDMA Interrupt Enable Control Register [X]
- * | | |This field is used for enabling PDMA channel[x] interrupt.
- * | | |0 = PDMA channel [x] interrupt Disabled.
- * | | |1 = PDMA channel [x] interrupt Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x41C PDMA Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Status Flag
- * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_TABORTF register to find which channel has target abort error.
- * | | |0 = No bus ERROR response received.
- * | | |1 = Bus ERROR response received.
- * | | |Note: This field is read only.
- * |[1] |TDIF |Transfer Done Interrupt Status Flag
- * | | |This bit indicates that PDMA has finished transmission; Software can read PDMA_TDSTS register to indicate which channel finished transfer.
- * | | |0 = Not finished yet.
- * | | |1 = PDMA channel has finished transmission.
- * | | |Note: This field is Read only.
- * |[2] |TEIF |Table Empty Interrupt Status Flag
- * | | |This bit indicates that PDMA has finished each table transmission and the operation is Stop mode.
- * | | |Software can read TEIF register to indicate which channel finished transfer.
- * | | |0 = Not finished yet.
- * | | |1 = PDMA channel has finished and the operation is Stop mode.
- * | | |Note: This field is Read only.
- * |[8:23] |REQTOFX |Time-Out Status Flag For Each Channel
- * | | |This flag indicates that PDMA has waited peripheral request for a period defined by TIMECNTX
- * | | |0 = No time-out flag.
- * | | |1 = Time-out flag.
- * | | |Note: This field is Read only, but software can write 1 to clear it.
- */
- __IO uint32_t INTSTS;
-
- /**
- * ABTSTS
- * ===================================================================================================
- * Offset: 0x420 PDMA Read/Write Target Abort Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |ABTIF |PDMA Read/Write Target Abort Interrupt Status Flag
- * | | |This bit indicates which PDMA has target abort error
- * | | |0 = No bus ERROR response received.
- * | | |1 = Bus ERROR response received.
- * | | |Note: This field is read only, but software can write 1 to clear it.
- */
- __IO uint32_t ABTSTS;
-
- /**
- * TDSTS
- * ===================================================================================================
- * Offset: 0x424 PDMA Transfer Done Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TDIF |Transfer Done Flag [X]
- * | | |This bit indicates which PDMA channel has finished transmission.
- * | | |0 = Not finished yet.
- * | | |1 = PDMA channel has finished transmission.
- * | | |Note: This field is read only, but software can write 1 to clear.
- */
- __IO uint32_t TDSTS;
-
- /**
- * SCATSTS
- * ===================================================================================================
- * Offset: 0x428 PDMA Scatter-Gather Transfer Done Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TEMPTYF |Table Empty Flag Bit [X]
- * | | |This bit indicates which PDMA channel table has finished transmission and the operation mode is Stop mode
- * | | |0 = Not finished or not in Stop mode.
- * | | |1 = PDMA channel has finished transmission and the operation is Stop mode.
- * | | |Note: This field is read only, but software can write 1 to clear.
- */
- __IO uint32_t SCATSTS;
-
- /**
- * TACTSTS
- * ===================================================================================================
- * Offset: 0x42C PDMA Transfer on Active Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TXACTF |Transfer On Active Flag Bit [X]
- * | | |This bit indicates which PDMA channel is on active.
- * | | |0 = PDMA channel is not finished.
- * | | |1 = PDMA channel is on active.
- */
- __I uint32_t TACTSTS;
- uint32_t RESERVE1[3];
-
-
- /**
- * SCATBA
- * ===================================================================================================
- * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[16:31] |SCATBA |PDMA Scatter-Gather Descriptor Table Base Address Bits
- * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
- * | | |The next link address equation is.
- * | | |Next Link Address = { SCATBA[15:0], EMBTA_NTAAR[15:2], 2'b00}.
- * | | |Note: Only useful in Scatter-Gather mode.
- */
- __IO uint32_t SCATBA;
-
- /**
- * TOC0_1
- * ===================================================================================================
- * Offset: 0x440 PDMA Time-out Period Counter Ch1 and Ch0 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC0 |Time-Out Period Counter For Channel 0
- * | | |This controls the period of time-out function for channel 0.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC1 |Time-Out Period Counter For Channel 1
- * | | |This controls the period of time-out function for channel 1.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC0_1;
-
- /**
- * TOC2_3
- * ===================================================================================================
- * Offset: 0x444 PDMA Time-out Period Counter Ch3 and Ch2 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC2 |Time-Out Period Counter For Channel 2
- * | | |This controls the period of time-out function for channel 2.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC3 |Time-Out Period Counter For Channel 3
- * | | |This controls the period of time-out function for channel 3.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC2_3;
-
- /**
- * TOC4_5
- * ===================================================================================================
- * Offset: 0x448 PDMA Time-out Period Counter Ch5 and Ch4 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC4 |Time-Out Period Counter For Channel 4
- * | | |This controls the period of time-out function for channel 4.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC5 |Time-Out Period Counter For Channel 5
- * | | |This controls the period of time-out function for channel 5.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC4_5;
-
- /**
- * TOC6_7
- * ===================================================================================================
- * Offset: 0x44C PDMA Time-out Period Counter Ch7 and Ch6 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC6 |Time-Out Period Counter For Channel 6
- * | | |This controls the period of time-out function for channel 6.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC7 |Time-Out Period Counter For Channel 7
- * | | |This controls the period of time-out function for channel 7.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC6_7;
-
- /**
- * TOC8_9
- * ===================================================================================================
- * Offset: 0x450 PDMA Time-out Period Counter Ch9 and Ch8 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC8 |Time-Out Period Counter For Channel 8
- * | | |This controls the period of time-out function for channel 8.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC9 |Time-Out Period Counter For Channel 9
- * | | |This controls the period of time-out function for channel 9.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC8_9;
-
- /**
- * TOC10_11
- * ===================================================================================================
- * Offset: 0x454 PDMA Time-out Period Counter Ch11 and Ch10 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC10 |Time-Out Period Counter For Channel 10
- * | | |This controls the period of time-out function for channel 10.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC11 |Time-Out Period Counter For Channel 11
- * | | |This controls the period of time-out function for channel 11.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC10_11;
-
- /**
- * TOC12_13
- * ===================================================================================================
- * Offset: 0x458 PDMA Time-out Period Counter Ch13 and Ch12 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC12 |Time-Out Period Counter For Channel 12
- * | | |This controls the period of time-out function for channel 12.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC13 |Time-Out Period Counter For Channel 13
- * | | |This controls the period of time-out function for channel 13.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC12_13;
-
- /**
- * TOC14_15
- * ===================================================================================================
- * Offset: 0x45C PDMA Time-out Period Counter Ch15 and Ch14 Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |TOC14 |Time-Out Period Counter For Channel 14
- * | | |This control the period of time-out function for channel 14.
- * | | |The calculation unit is based on 10 kHz clock.
- * |[16:31] |TOC15 |Time-Out Period Counter For Channel 15
- * | | |This control the period of time-out function for channel 15.
- * | | |The calculation unit is based on 10 kHz clock.
- */
- __IO uint32_t TOC14_15;
- uint32_t RESERVE2[8];
-
-
- /**
- * REQSEL0_3
- * ===================================================================================================
- * Offset: 0x480 PDMA Source Module Select Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:4] |REQSRC0 |Channel 0 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 0.
- * | | |Software can configure the peripheral by setting REQSRC0.
- * | | |00000 = Connect to SPI0_TX.
- * | | |00001 = Connect to SPI1_TX.
- * | | |00010 = Connect to SPI2_TX.
- * | | |00011 = Connect to SPI3_TX.
- * | | |00100 = Connect to UART0_TX.
- * | | |00101 = Connect to UART1_TX.
- * | | |00110 = Connect to UART2_TX.
- * | | |00111 = Connect to UART3_TX.
- * | | |01000 = Connect to UART4_TX.
- * | | |01001 = Connect to UART5_TX.
- * | | |01010 = Reserved.
- * | | |01011 = Connect to I2S_TX.
- * | | |01100 = Connect to I2S1_TX.
- * | | |01101 = Connect to SPI0_RX.
- * | | |01110 = Connect to SPI1_RX.
- * | | |01111 = Connect to SPI2_RX.
- * | | |10000 = Connect to SPI3_RX.
- * | | |10001 = Connect to UART0_RX.
- * | | |10010 = Connect to UART1_RX.
- * | | |10011 = Connect to UART2_RX.
- * | | |10100 = Connect to UART3_RX.
- * | | |10101 = Connect to UART4_RX.
- * | | |10110 = Connect to UART5_RX.
- * | | |10111 = Reserved.
- * | | |11000 = Connect to ADC.
- * | | |11001 = Connect to I2S_RX.
- * | | |11010 = Connect to I2S1_RX.
- * | | |Other = Reserved.
- * |[8:12] |REQSRC1 |Channel 1 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 1.
- * | | |Software can configure the peripheral setting by REQSRC1.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[16:20] |REQSRC2 |Channel 2 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 2.
- * | | |Software can configure the peripheral setting by REQSRC2.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[24:28] |REQSRC3 |Channel 3 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 3.
- * | | |Software can configure the peripheral setting by REQSRC3.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- */
- __IO uint32_t REQSEL0_3;
-
- /**
- * REQSEL4_7
- * ===================================================================================================
- * Offset: 0x484 PDMA Source Module Select Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:4] |REQSRC4 |Channel 0 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 4.
- * | | |Software can configure the peripheral setting by REQSRC4.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[8:12] |REQSRC5 |Channel 1 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 5.
- * | | |Software can configure the peripheral setting by REQSRC5.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[16:20] |REQSRC6 |Channel 6 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 6.
- * | | |Software can configure the peripheral setting by REQSRC6.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[24:28] |REQSRC7 |Channel 7 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 7.
- * | | |Software can configure the peripheral setting by REQSRC7.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- */
- __IO uint32_t REQSEL4_7;
-
- /**
- * REQSEL8_11
- * ===================================================================================================
- * Offset: 0x488 PDMA Source Module Select Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:4] |REQSRC8 |Channel 8 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 8.
- * | | |Software can configure the peripheral setting by REQSRC8.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[8:12] |REQSRC9 |Channel 9 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 9.
- * | | |Software can configure the peripheral setting by REQSRC9.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[16:20] |REQSRC10 |Channel 10 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 10.
- * | | |Software can configure the peripheral setting by REQSRC10.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[24:28] |REQSRC11 |Channel 11 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 11.
- * | | |Software can configure the peripheral setting by REQSRC11.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- */
- __IO uint32_t REQSEL8_11;
-
- /**
- * REQSEL12_15
- * ===================================================================================================
- * Offset: 0x48C PDMA Source Module Select Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:4] |REQSRC12 |Channel 12 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 12.
- * | | |Software can configure the peripheral setting by REQSRC12.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[8:12] |REQSRC13 |Channel 13 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 13.
- * | | |Software can configure the peripheral setting by REQSRC13.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[16:20] |REQSRC14 |Channel 14 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 14.
- * | | |Software can configure the peripheral setting by REQSRC14.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- * |[24:28] |REQSRC15 |Channel 15 Selection
- * | | |This filed defines which peripheral is connected to PDMA channel 15.
- * | | |Software can configure the peripheral setting by REQSRC15.
- * | | |The channel configuration is the same as REQSRC0 field.
- * | | |Please refer to the explanation of REQSRC0.
- */
- __IO uint32_t REQSEL12_15;
-
-} PDMA_T;
-
-/**
- @addtogroup PDMA_CONST PDMA Bit Field Definition
- Constant Definitions for PDMA Controller
-@{ */
-
-#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA DSCT_CTL: OPMODE Position */
-#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA DSCT_CTL: OPMODE Mask */
-
-#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA DSCT_CTL: TXTYPE Position */
-#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA DSCT_CTL: TXTYPE Mask */
-
-#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA DSCT_CTL: BURSIZE Position */
-#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA DSCT_CTL: BURSIZE Mask */
-
-#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA DSCT_CTL: TBINTDIS Position */
-#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA DSCT_CTL: TBINTDIS Mask */
-
-#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA DSCT_CTL: SAINC Position */
-#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA DSCT_CTL: SAINC Mask */
-
-#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA DSCT_CTL: DAINC Position */
-#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA DSCT_CTL: DAINC Mask */
-
-#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA DSCT_CTL: TXWIDTH Position */
-#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA DSCT_CTL: TXWIDTH Mask */
-
-#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA DSCT_CTL: TXCNT Position */
-#define PDMA_DSCT_CTL_TXCNT_Msk (0x3ffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA DSCT_CTL: TXCNT Mask */
-
-#define PDMA_DSCT_ENDSA_ENDSA_Pos (0) /*!< PDMA DSCT_ENDSA: ENDSA Position */
-#define PDMA_DSCT_ENDSA_ENDSA_Msk (0xfffffffful << PDMA_DSCT_ENDSA_ENDSA_Pos) /*!< PDMA DSCT_ENDSA: ENDSA Mask */
-
-#define PDMA_DSCT_ENDDA_ENDDA_Pos (0) /*!< PDMA DSCT_ENDDA: ENDDA Position */
-#define PDMA_DSCT_ENDDA_ENDDA_Msk (0xfffffffful << PDMA_DSCT_ENDDA_ENDDA_Pos) /*!< PDMA DSCT_ENDDA: ENDDA Mask */
-
-#define PDMA_DSCT_NEXT_NEXT_Pos (2) /*!< PDMA DSCT_NEXT: NEXT Position */
-#define PDMA_DSCT_NEXT_NEXT_Msk (0x3ffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA DSCT_NEXT: NEXT Mask */
-
-#define PDMA_CHCTL_CHEN_Pos (0) /*!< PDMA CHCTL: CHEN Position */
-#define PDMA_CHCTL_CHEN_Msk (0xfffful << PDMA_CHCTL_CHEN_Pos) /*!< PDMA CHCTL: CHEN Mask */
-
-#define PDMA_STOP_STOP_Pos (0) /*!< PDMA STOP: STOP Position */
-#define PDMA_STOP_STOP_Msk (0xfffful << PDMA_STOP_STOP_Pos) /*!< PDMA STOP: STOP Mask */
-
-#define PDMA_SWREQ_SWREQ_Pos (0) /*!< PDMA SWREQ: SWREQ Position */
-#define PDMA_SWREQ_SWREQ_Msk (0xffful << PDMA_SWREQ_SWREQ_Pos) /*!< PDMA SWREQ: SWREQ Mask */
-
-#define PDMA_TRGSTS_REQSTS_Pos (0) /*!< PDMA TRGSTS: REQSTS Position */
-#define PDMA_TRGSTS_REQSTS_Msk (0xfffful << PDMA_TRGSTS_REQSTS_Pos) /*!< PDMA TRGSTS: REQSTS Mask */
-
-#define PDMA_PRISET_FPRISET_Pos (0) /*!< PDMA PRISET: FPRISET Position */
-#define PDMA_PRISET_FPRISET_Msk (0xfffful << PDMA_PRISET_FPRISET_Pos) /*!< PDMA PRISET: FPRISET Mask */
-
-#define PDMA_PRICLR_FPRICLR_Pos (0) /*!< PDMA PRICLR: FPRICLR Position */
-#define PDMA_PRICLR_FPRICLR_Msk (0xfffful << PDMA_PRICLR_FPRICLR_Pos) /*!< PDMA PRICLR: FPRICLR Mask */
-
-#define PDMA_INTEN_INTEN_Pos (0) /*!< PDMA INTEN: INTEN Position */
-#define PDMA_INTEN_INTEN_Msk (0xfffful << PDMA_INTEN_INTEN_Pos) /*!< PDMA INTEN: INTEN Mask */
-
-#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA INTSTS: ABTIF Position */
-#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA INTSTS: ABTIF Mask */
-
-#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA INTSTS: TDIF Position */
-#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA INTSTS: TDIF Mask */
-
-#define PDMA_INTSTS_TEIF_Pos (2) /*!< PDMA INTSTS: TEIF Position */
-#define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /*!< PDMA INTSTS: TEIF Mask */
-
-#define PDMA_INTSTS_REQTOFX_Pos (8) /*!< PDMA INTSTS: REQTOFX Position */
-#define PDMA_INTSTS_REQTOFX_Msk (0xfffful << PDMA_INTSTS_REQTOFX_Pos) /*!< PDMA INTSTS: REQTOFX Mask */
-
-#define PDMA_ABTSTS_ABTIF_Pos (0) /*!< PDMA ABTSTS: ABTIF Position */
-#define PDMA_ABTSTS_ABTIF_Msk (0xfffful << PDMA_ABTSTS_ABTIF_Pos) /*!< PDMA ABTSTS: ABTIF Mask */
-
-#define PDMA_TDSTS_TDIF_Pos (0) /*!< PDMA TDSTS: TDIF Position */
-#define PDMA_TDSTS_TDIF_Msk (0xfffful << PDMA_TDSTS_TDIF_Pos) /*!< PDMA TDSTS: TDIF Mask */
-
-#define PDMA_SCATSTS_TEMPTYF_Pos (0) /*!< PDMA SCATSTS: TEMPTYF Position */
-#define PDMA_SCATSTS_TEMPTYF_Msk (0xfffful << PDMA_SCATSTS_TEMPTYF_Pos) /*!< PDMA SCATSTS: TEMPTYF Mask */
-
-#define PDMA_TACTSTS_TXACTF_Pos (0) /*!< PDMA TACTSTS: TXACTF Position */
-#define PDMA_TACTSTS_TXACTF_Msk (0xfffful << PDMA_TACTSTS_TXACTF_Pos) /*!< PDMA TACTSTS: TXACTF Mask */
-
-#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA SCATBA: SCATBA Position */
-#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA SCATBA: SCATBA Mask */
-
-#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA TOC0_1: TOC0 Position */
-#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA TOC0_1: TOC0 Mask */
-
-#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA TOC0_1: TOC1 Position */
-#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA TOC0_1: TOC1 Mask */
-
-#define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA TOC2_3: TOC2 Position */
-#define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA TOC2_3: TOC2 Mask */
-
-#define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA TOC2_3: TOC3 Position */
-#define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA TOC2_3: TOC3 Mask */
-
-#define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA TOC4_5: TOC4 Position */
-#define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA TOC4_5: TOC4 Mask */
-
-#define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA TOC4_5: TOC5 Position */
-#define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA TOC4_5: TOC5 Mask */
-
-#define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA TOC6_7: TOC6 Position */
-#define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA TOC6_7: TOC6 Mask */
-
-#define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA TOC6_7: TOC7 Position */
-#define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA TOC6_7: TOC7 Mask */
-
-#define PDMA_TOC8_9_TOC8_Pos (0) /*!< PDMA TOC8_9: TOC8 Position */
-#define PDMA_TOC8_9_TOC8_Msk (0xfffful << PDMA_TOC8_9_TOC8_Pos) /*!< PDMA TOC8_9: TOC8 Mask */
-
-#define PDMA_TOC8_9_TOC9_Pos (16) /*!< PDMA TOC8_9: TOC9 Position */
-#define PDMA_TOC8_9_TOC9_Msk (0xfffful << PDMA_TOC8_9_TOC9_Pos) /*!< PDMA TOC8_9: TOC9 Mask */
-
-#define PDMA_TOC10_11_TOC10_Pos (0) /*!< PDMA TOC10_11: TOC10 Position */
-#define PDMA_TOC10_11_TOC10_Msk (0xfffful << PDMA_TOC10_11_TOC10_Pos) /*!< PDMA TOC10_11: TOC10 Mask */
-
-#define PDMA_TOC10_11_TOC11_Pos (16) /*!< PDMA TOC10_11: TOC11 Position */
-#define PDMA_TOC10_11_TOC11_Msk (0xfffful << PDMA_TOC10_11_TOC11_Pos) /*!< PDMA TOC10_11: TOC11 Mask */
-
-#define PDMA_TOC12_13_TOC12_Pos (0) /*!< PDMA TOC12_13: TOC12 Position */
-#define PDMA_TOC12_13_TOC12_Msk (0xfffful << PDMA_TOC12_13_TOC12_Pos) /*!< PDMA TOC12_13: TOC12 Mask */
-
-#define PDMA_TOC12_13_TOC13_Pos (16) /*!< PDMA TOC12_13: TOC13 Position */
-#define PDMA_TOC12_13_TOC13_Msk (0xfffful << PDMA_TOC12_13_TOC13_Pos) /*!< PDMA TOC12_13: TOC13 Mask */
-
-#define PDMA_TOC14_15_TOC14_Pos (0) /*!< PDMA TOC14_15: TOC14 Position */
-#define PDMA_TOC14_15_TOC14_Msk (0xfffful << PDMA_TOC14_15_TOC14_Pos) /*!< PDMA TOC14_15: TOC14 Mask */
-
-#define PDMA_TOC14_15_TOC15_Pos (16) /*!< PDMA TOC14_15: TOC15 Position */
-#define PDMA_TOC14_15_TOC15_Msk (0xfffful << PDMA_TOC14_15_TOC15_Pos) /*!< PDMA TOC14_15: TOC15 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA REQSEL0_3: REQSRC0 Position */
-#define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA REQSEL0_3: REQSRC0 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA REQSEL0_3: REQSRC1 Position */
-#define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA REQSEL0_3: REQSRC1 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA REQSEL0_3: REQSRC2 Position */
-#define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA REQSEL0_3: REQSRC2 Mask */
-
-#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA REQSEL0_3: REQSRC3 Position */
-#define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA REQSEL0_3: REQSRC3 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA REQSEL4_7: REQSRC4 Position */
-#define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA REQSEL4_7: REQSRC4 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA REQSEL4_7: REQSRC5 Position */
-#define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA REQSEL4_7: REQSRC5 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA REQSEL4_7: REQSRC6 Position */
-#define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA REQSEL4_7: REQSRC6 Mask */
-
-#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA REQSEL4_7: REQSRC7 Position */
-#define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA REQSEL4_7: REQSRC7 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA REQSEL8_11: REQSRC8 Position */
-#define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA REQSEL8_11: REQSRC8 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA REQSEL8_11: REQSRC9 Position */
-#define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA REQSEL8_11: REQSRC9 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA REQSEL8_11: REQSRC10 Position */
-#define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA REQSEL8_11: REQSRC10 Mask */
-
-#define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA REQSEL8_11: REQSRC11 Position */
-#define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA REQSEL8_11: REQSRC11 Mask */
-
-#define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA REQSEL12_15: REQSRC12 Position */
-#define PDMA_REQSEL12_15_REQSRC12_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA REQSEL12_15: REQSRC12 Mask */
-
-#define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA REQSEL12_15: REQSRC13 Position */
-#define PDMA_REQSEL12_15_REQSRC13_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA REQSEL12_15: REQSRC13 Mask */
-
-#define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA REQSEL12_15: REQSRC14 Position */
-#define PDMA_REQSEL12_15_REQSRC14_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA REQSEL12_15: REQSRC14 Mask */
-
-#define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA REQSEL12_15: REQSRC15 Position */
-#define PDMA_REQSEL12_15_REQSRC15_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA REQSEL12_15: REQSRC15 Mask */
-
-/**@}*/ /* PDMA_CONST */
-/**@}*/ /* end of PDMA register group */
-
-
-/*---------------------- PS/2 Device Controller -------------------------*/
-/**
- @addtogroup PS2 PS/2 Device Controller(PS2)
- Memory Mapped Structure for PS2 Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 PS/2 Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PS2EN |PS/2 Device Enable Control
- * | | |Enable PS/2 device controller.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[1] |TXIEN |Transmit Interrupt Enable Control
- * | | |0 = Data transmit complete interrupt Disabled.
- * | | |1 = Data transmit complete interrupt Enabled.
- * |[2] |RXIEN |Receive Interrupt Enable Control
- * | | |0 = Data receive complete interrupt Disabled.
- * | | |1 = Data receive complete interrupt Enabled.
- * |[3:6] |TXFDEPTH |Transmit Data FIFO Depth
- * | | |There is 16-byte buffer for data transmit.
- * | | |Software can define the FIFO depth from 1 to 16 bytes depending on the application.
- * | | |0 = 1 byte.
- * | | |1 = 2 bytes.
- * | | |...
- * | | |14 = 15 bytes.
- * | | |15 = 16 bytes.
- * |[7] |ACK |Acknowledge Enable Control
- * | | |0 = Always sends acknowledge to host at 12th clock for host to device communication.
- * | | |1 = If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock.
- * |[8] |CLRFIFO |Clear TX FIFO
- * | | |Write 1 to this bit to terminate device to host transmission.
- * | | |The TXEMPTY(PS2_STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2_STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not.
- * | | |The buffer content is not been cleared.
- * | | |0 = Not active.
- * | | |1 = Clear FIFO.
- * |[9] |OVERRIDE |Software Override PS/2 CLK/DATA Pin State
- * | | |0 = CLKSTAT and DATSTAT pins are controlled by internal state machine.
- * | | |1 = CLKSTAT and DATSTAT pins are controlled by software.
- * |[10] |FPS2CLK |Force CLKSTAT Line
- * | | |It forces CLKSTAT line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.
- * | | |0 = Force CLKSTAT line low.
- * | | |1 = Force CLKSTAT line high.
- * |[11] |FPS2DAT |Force DATSTAT Line
- * | | |It forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high.
- * | | |0 = Force DATSTAT low.
- * | | |1 = Force DATSTAT high.
- */
- __IO uint32_t CTL;
-
- /**
- * TXDAT0
- * ===================================================================================================
- * Offset: 0x04 PS/2 Transmit DATA Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DAT |Transmit Data
- * | | |Write data to this register starts device to host communication if bus is in IDLE state.
- * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
- */
- __IO uint32_t TXDAT0;
-
- /**
- * TXDAT1
- * ===================================================================================================
- * Offset: 0x08 PS/2 Transmit DATA Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DAT |Transmit Data
- * | | |Write data to this register starts device to host communication if bus is in IDLE state.
- * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
- */
- __IO uint32_t TXDAT1;
-
- /**
- * TXDAT2
- * ===================================================================================================
- * Offset: 0x0C PS/2 Transmit DATA Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DAT |Transmit Data
- * | | |Write data to this register starts device to host communication if bus is in IDLE state.
- * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
- */
- __IO uint32_t TXDAT2;
-
- /**
- * TXDAT3
- * ===================================================================================================
- * Offset: 0x10 PS/2 Transmit DATA Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DAT |Transmit Data
- * | | |Write data to this register starts device to host communication if bus is in IDLE state.
- * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
- */
- __IO uint32_t TXDAT3;
-
- /**
- * RXDAT
- * ===================================================================================================
- * Offset: 0x14 PS/2 Receive DATA Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DAT |Received Data
- * | | |For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2_RXDAT register.
- * | | |CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOV(PS2_STATUS[6]) bit will be set to 1.
- */
- __I uint32_t RXDAT;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x18 PS/2 Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CLKSTAT |CLK Pin State
- * | | |This bit reflects the status of the CLKSTAT line after synchronizing.
- * |[1] |DATSTAT |DATA Pin State
- * | | |This bit reflects the status of the DATSTAT line after synchronizing and sampling.
- * |[2] |FRAMEERR |Frame Error
- * | | |For host to device communication, if STOP bit (logic 1) is not received it is a frame error.
- * | | |If frame error occurs, DATA line may keep at low state after 12th clock.
- * | | |At this moment, software overrides CLKSTAT to send clock till DATSTAT release to high state.
- * | | |After that, device sends a "Resend" command to host.
- * | | |0 = No frame error.
- * | | |1 = Frame error occurred .
- * | | |Note: Write 1 to clear this bit.
- * |[3] |RXPARITY |Received Parity
- * | | |This bit reflects the parity bit for the last received data byte (odd parity).
- * | | |Note: This bit is read only.
- * |[4] |RXBUSY |Receive Busy
- * | | |This bit indicates that the PS/2 device is currently receiving data.
- * | | |0 = Idle.
- * | | |1 = Currently receiving data.
- * | | |Note: This bit is read only.
- * |[5] |TXBUSY |Transmit Busy
- * | | |This bit indicates that the PS/2 device is currently sending data.
- * | | |0 = Idle.
- * | | |1 = Currently sending data.
- * | | |Note: This bit is read only.
- * |[6] |RXOV |RX Buffer Overwrite
- * | | |0 = No overwrite.
- * | | |1 = Data in PS2_RXDAT register is overwritten by new received data.
- * | | |Note: Write 1 to clear this bit.
- * |[7] |TXEMPTY |TX FIFO Empty
- * | | |When software writes any data to PS2_TXDAT0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled.
- * | | |When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.
- * | | |0 = There is data to be transmitted.
- * | | |1 = FIFO is empty.
- * | | |Note: This bit is read only.
- * |[8:11] |BYTEIDX |Byte Index
- * | | |It indicates which data byte in transmit data shift register.
- * | | |When all data in FIFO is transmitted and it will be cleared to 0.
- * | | |Note: This bit is read only.
- * | | |BYTEIDX DATA Transmit
- * | | |0000 TXDATA0[7:0]
- * | | |0001 TXDATA0[15:8]
- * | | |0010 TXDATA0[23:16]
- * | | |0011 TXDATA0[31:24]
- * | | |0100 TXDATA1[7:0]
- * | | |0101 TXDATA1[15:8]
- * | | |0110 TXDATA1[23:16]
- * | | |0111 TXDATA1[31:24]
- * | | |1000 TXDATA2[7:0]
- * | | |1001 TXDATA2[15:8]
- * | | |1010 TXDATA2[23:16]
- * | | |1011 TXDATA2[31:24]
- * | | |1100 TXDATA3[7:0]
- * | | |1101 TXDATA3[15:8]
- * | | |1110 TXDATA3[23:16]
- * | | |1111 TXDATA3[31:24]
- */
- __IO uint32_t STATUS;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x1C PS/2 Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXIF |Receive Interrupt
- * | | |This bit is set to 1 when acknowledge bit is sent for Host to device communication.
- * | | |Interrupt occurs if RXIEN(PS2_CTL[2]) bit is set to 1.
- * | | |0 = No interrupt.
- * | | |1 = Receive interrupt occurred.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[1] |TXIF |Transmit Interrupt
- * | | |This bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXIEN(PS2_CTL[1]) bit is set
- * | | |to 1.
- * | | |0 = No interrupt.
- * | | |1 = Transmit interrupt occurred.
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t INTSTS;
-
-} PS2_T;
-
-/**
- @addtogroup PS2_CONST PS2 Bit Field Definition
- Constant Definitions for PS2 Controller
-@{ */
-
-#define PS2_CTL_PS2EN_Pos (0) /*!< PS2 CTL: PS2EN Position */
-#define PS2_CTL_PS2EN_Msk (0x1ul << PS2_CTL_PS2EN_Pos) /*!< PS2 CTL: PS2EN Mask */
-
-#define PS2_CTL_TXIEN_Pos (1) /*!< PS2 CTL: TXIEN Position */
-#define PS2_CTL_TXIEN_Msk (0x1ul << PS2_CTL_TXIEN_Pos) /*!< PS2 CTL: TXIEN Mask */
-
-#define PS2_CTL_RXIEN_Pos (2) /*!< PS2 CTL: RXIEN Position */
-#define PS2_CTL_RXIEN_Msk (0x1ul << PS2_CTL_RXIEN_Pos) /*!< PS2 CTL: RXIEN Mask */
-
-#define PS2_CTL_TXFDEPTH_Pos (3) /*!< PS2 CTL: TXFDEPTH Position */
-#define PS2_CTL_TXFDEPTH_Msk (0xful << PS2_CTL_TXFDEPTH_Pos) /*!< PS2 CTL: TXFDEPTH Mask */
-
-#define PS2_CTL_ACK_Pos (7) /*!< PS2 CTL: ACK Position */
-#define PS2_CTL_ACK_Msk (0x1ul << PS2_CTL_ACK_Pos) /*!< PS2 CTL: ACK Mask */
-
-#define PS2_CTL_CLRFIFO_Pos (8) /*!< PS2 CTL: CLRFIFO Position */
-#define PS2_CTL_CLRFIFO_Msk (0x1ul << PS2_CTL_CLRFIFO_Pos) /*!< PS2 CTL: CLRFIFO Mask */
-
-#define PS2_CTL_OVERRIDE_Pos (9) /*!< PS2 CTL: OVERRIDE Position */
-#define PS2_CTL_OVERRIDE_Msk (0x1ul << PS2_CTL_OVERRIDE_Pos) /*!< PS2 CTL: OVERRIDE Mask */
-
-#define PS2_CTL_FPS2CLK_Pos (10) /*!< PS2 CTL: FPS2CLK Position */
-#define PS2_CTL_FPS2CLK_Msk (0x1ul << PS2_CTL_FPS2CLK_Pos) /*!< PS2 CTL: FPS2CLK Mask */
-
-#define PS2_CTL_FPS2DAT_Pos (11) /*!< PS2 CTL: FPS2DAT Position */
-#define PS2_CTL_FPS2DAT_Msk (0x1ul << PS2_CTL_FPS2DAT_Pos) /*!< PS2 CTL: FPS2DAT Mask */
-
-#define PS2_TXDAT0_DAT_Pos (0) /*!< PS2 TXDAT0: DAT Position */
-#define PS2_TXDAT0_DAT_Msk (0xfffffffful << PS2_TXDAT0_DAT_Pos) /*!< PS2 TXDAT0: DAT Mask */
-
-#define PS2_TXDAT1_DAT_Pos (0) /*!< PS2 TXDAT1: DAT Position */
-#define PS2_TXDAT1_DAT_Msk (0xfffffffful << PS2_TXDAT1_DAT_Pos) /*!< PS2 TXDAT1: DAT Mask */
-
-#define PS2_TXDAT2_DAT_Pos (0) /*!< PS2 TXDAT2: DAT Position */
-#define PS2_TXDAT2_DAT_Msk (0xfffffffful << PS2_TXDAT2_DAT_Pos) /*!< PS2 TXDAT2: DAT Mask */
-
-#define PS2_TXDAT3_DAT_Pos (0) /*!< PS2 TXDAT3: DAT Position */
-#define PS2_TXDAT3_DAT_Msk (0xfffffffful << PS2_TXDAT3_DAT_Pos) /*!< PS2 TXDAT3: DAT Mask */
-
-#define PS2_RXDAT_DAT_Pos (0) /*!< PS2 RXDAT: DAT Position */
-#define PS2_RXDAT_DAT_Msk (0xfful << PS2_RXDAT_DAT_Pos) /*!< PS2 RXDAT: DAT Mask */
-
-#define PS2_STATUS_CLKSTAT_Pos (0) /*!< PS2 STATUS: CLKSTAT Position */
-#define PS2_STATUS_CLKSTAT_Msk (0x1ul << PS2_STATUS_CLKSTAT_Pos) /*!< PS2 STATUS: CLKSTAT Mask */
-
-#define PS2_STATUS_DATSTAT_Pos (1) /*!< PS2 STATUS: DATSTAT Position */
-#define PS2_STATUS_DATSTAT_Msk (0x1ul << PS2_STATUS_DATSTAT_Pos) /*!< PS2 STATUS: DATSTAT Mask */
-
-#define PS2_STATUS_FRAMEERR_Pos (2) /*!< PS2 STATUS: FRAMEERR Position */
-#define PS2_STATUS_FRAMEERR_Msk (0x1ul << PS2_STATUS_FRAMEERR_Pos) /*!< PS2 STATUS: FRAMEERR Mask */
-
-#define PS2_STATUS_RXPARITY_Pos (3) /*!< PS2 STATUS: RXPARITY Position */
-#define PS2_STATUS_RXPARITY_Msk (0x1ul << PS2_STATUS_RXPARITY_Pos) /*!< PS2 STATUS: RXPARITY Mask */
-
-#define PS2_STATUS_RXBUSY_Pos (4) /*!< PS2 STATUS: RXBUSY Position */
-#define PS2_STATUS_RXBUSY_Msk (0x1ul << PS2_STATUS_RXBUSY_Pos) /*!< PS2 STATUS: RXBUSY Mask */
-
-#define PS2_STATUS_TXBUSY_Pos (5) /*!< PS2 STATUS: TXBUSY Position */
-#define PS2_STATUS_TXBUSY_Msk (0x1ul << PS2_STATUS_TXBUSY_Pos) /*!< PS2 STATUS: TXBUSY Mask */
-
-#define PS2_STATUS_RXOV_Pos (6) /*!< PS2 STATUS: RXOV Position */
-#define PS2_STATUS_RXOV_Msk (0x1ul << PS2_STATUS_RXOV_Pos) /*!< PS2 STATUS: RXOV Mask */
-
-#define PS2_STATUS_TXEMPTY_Pos (7) /*!< PS2 STATUS: TXEMPTY Position */
-#define PS2_STATUS_TXEMPTY_Msk (0x1ul << PS2_STATUS_TXEMPTY_Pos) /*!< PS2 STATUS: TXEMPTY Mask */
-
-#define PS2_STATUS_BYTEIDX_Pos (8) /*!< PS2 STATUS: BYTEIDX Position */
-#define PS2_STATUS_BYTEIDX_Msk (0xful << PS2_STATUS_BYTEIDX_Pos) /*!< PS2 STATUS: BYTEIDX Mask */
-
-#define PS2_INTSTS_RXIF_Pos (0) /*!< PS2 INTSTS: RXIF Position */
-#define PS2_INTSTS_RXIF_Msk (0x1ul << PS2_INTSTS_RXIF_Pos) /*!< PS2 INTSTS: RXIF Mask */
-
-#define PS2_INTSTS_TXIF_Pos (1) /*!< PS2 INTSTS: TXIF Position */
-#define PS2_INTSTS_TXIF_Msk (0x1ul << PS2_INTSTS_TXIF_Pos) /*!< PS2 INTSTS: TXIF Mask */
-
-/**@}*/ /* PS2_CONST */
-/**@}*/ /* end of PS2 register group */
-
-
-/*---------------------- Pulse Width Modulation Controller -------------------------*/
-/**
- @addtogroup PWM Pulse Width Modulation Controller(PWM)
- Memory Mapped Structure for PWM Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CLKPSC
- * ===================================================================================================
- * Offset: 0x00 PWM Clock Prescale Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |CLKPSC01 |PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1
- * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
- * | | |Each PWM pair share one PWM counter base-clock prescaler.
- * | | |The base-clock of PWM counter is divided by (CLKPSC01 + 1).
- * | | |If the value of CLKPSC01 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
- * |[8:15] |CLKPSC23 |PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3
- * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
- * | | |Each PWM pair share one PWM counter base-clock prescaler.
- * | | |The base-clock of PWM counter is divided by (CLKPSC23 + 1).
- * | | |If the value of CLKPSC23 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
- * |[16:23] |CLKPSC45 |PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5
- * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
- * | | |Each PWM pair share one PWM counter base-clock prescaler.
- * | | |The base-clock of PWM counter is divided by (CLKPSC45 + 1).
- * | | |If the value of CLKPSC45 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
- */
- __IO uint32_t CLKPSC;
-
- /**
- * CLKDIV
- * ===================================================================================================
- * Offset: 0x04 PWM Clock Divide Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |CLKDIV0 |PWM Counter Base-Clock Divide For PWMx_CH0
- * | | |(Table is the same as CLKDIV5)
- * |[4:6] |CLKDIV1 |PWM Counter Base-Clock Divide For PWMx_CH1
- * | | |(Table is the same as CLKDIV5)
- * |[8:10] |CLKDIV2 |PWM Counter Base-Clock Divide For PWMx_CH2
- * | | |(Table is the same as CLKDIV5)
- * |[12:14] |CLKDIV3 |PWM Counter Base-Clock Divide For PWMx_CH3
- * | | |(Table is the same as CLKDIV5)
- * |[16:18] |CLKDIV4 |PWM Counter Base-Clock Divide For PWMx_CH4
- * | | |(Table is the same as CLKDIV5)
- * |[20:22] |CLKDIV5 |PWM Counter Base-Clock Divide For PWMx_CH5
- * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
- * | | |Each PWM counter has independent clock divider control register and the divided value is listed in the table below:.
- * | | |000 = 2.
- * | | |001 = 4.
- * | | |010 = 8.
- * | | |011 = 16.
- * | | |100 = 1.
- */
- __IO uint32_t CLKDIV;
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x08 PWM Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |CMPINV |PWM Comparator Output Inverter Enable Control
- * | | |When CMPINV is set to high, the PWM comparator output signals will be inversed,
- * | | |0 = Comparator output inverter Disabled.
- * | | |1 = Comparator output inverter Enabled.
- * | | |Note: Each bit control corresponding PWM channel
- * |[6] |OUTMODE |PWM Output Mode
- * | | |The register controls the output mode of PWM
- * | | |0 = PWM output at independent mode.
- * | | |1 = PWM output at complementary mode.
- * |[7] |GROUPEN |Group Mode Enable Control
- * | | |0 = The signals timing of each PWM channel are independent.
- * | | |1 = Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1.
- * |[8:13] |PINV |PWM Output Polar Inverse Enable Control
- * | | |The register controls polarity state of PWM output
- * | | |0 = PWM output polar inverse Disabled.
- * | | |1 = PWM output polar inverse Enabled.
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[15] |SYNCEN |Synchronous Mode Enable Control
- * | | |0 = The signals timing of each PWM channel are independent.
- * | | |1 = Unify the signals timing of PWM0 and PWM1 in the same phase which is controlled by PWM0 and so as another two PWM pair.
- * | | |Note: If Group and Synchronous mode are enabled simultaneously, the Synchronous mode will be inactive.
- * |[16:21] |CNTMODE |PWM Counter Operation Mode
- * | | |0 = PWM counter working as One-shot mode.
- * | | |1 = PWM counter working as Auto-reload mode.
- * | | |Note: Each bit control corresponding PWM channel
- * | | |Note: If there is a transition at this bit, it will cause PWM_PERIODn and PWM_CMPDATn be cleared.
- * |[24:29] |CNTTYPE |PWM Counter Operation Aligned Type
- * | | |0 = PWM counter operating as Edge-aligned type.
- * | | |1 = PWM counter operating as Center-aligned type.
- * | | |Note: Each bit control corresponding PWM channel
- * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Control (Write Protect)
- * | | |0 = ICE debug mode acknowledgement effects PWM output.
- * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
- * | | |1 = ICE debug mode acknowledgement disabled.
- * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not.
- */
- __IO uint32_t CTL;
-
- /**
- * CNTEN
- * ===================================================================================================
- * Offset: 0x0C PWM Counter Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |CNTEN |PWM Counter Enable Control
- * | | |0 = PWM Counter Stop Running.
- * | | |1 = PWM Counter Start Running.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t CNTEN;
-
- /**
- * PERIOD
- * ===================================================================================================
- * Offset: 0x10 ~ 0x24 PWM Counter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |PERIOD |PWM Period Register
- * | | |PERIOD determines the PWM period.
- * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(PERIOD+1)]; where xy, could be 01, 23 or 45, depends on selected PWM channel.
- * | | |For Edge-aligned mode:
- * | | |l Duty ratio = (CMP+1)/(PERIOD+1).
- * | | |l CMP >= PERIOD: PWM output is always high.
- * | | |l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
- * | | |l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
- * | | |For Center-aligned mode:
- * | | |l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)].
- * | | |l CMP > PERIOD: PWM output is always high.
- * | | |l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit.
- * | | |l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit.
- * | | |(Unit = one PWM clock cycle).
- * | | |Note1: Any write to PERIOD will take effect in next PWM cycle.
- * | | |Note2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE.
- * | | |If PERIOD equal to 0xFFFF, the PWM will work unpredictable.
- * | | |Note3: When PERIOD value is set to 0, PWM output is always high.
- */
- __IO uint32_t PERIOD[6];
-
- /**
- * CMPDAT
- * ===================================================================================================
- * Offset: 0x28 ~0x3C PWM Comparator Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CMP |PWM Duty Register
- * | | |CMP determines the PWM duty.
- * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(PERIOD+1)]; where xy, could be 01, 23 or, 45, depends on selected PWM channel.
- * | | |For Edge-aligned mode:
- * | | |l Duty ratio = (CMP+1)/(PERIOD+1).
- * | | |l CMP >= PERIOD: PWM output is always high.
- * | | |l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
- * | | |l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
- * | | |For Center-aligned mode:
- * | | |l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)].
- * | | |l CMP > PERIOD: PWM output is always high.
- * | | |l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit.
- * | | |l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit.
- * | | |(Unit = one PWM clock cycle).
- * | | |Note: Any write to CMP will take effect in next PWM cycle.
- */
- __IO uint32_t CMPDAT[6];
-
- /**
- * CNT
- * ===================================================================================================
- * Offset: 0x40 ~ 0x54 PWM Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |CNT |PWM Data Register
- * | | |User can monitor CNT to know the current value in 16-bit down counter.
- * | | |Note: It is recommended that read this register when PWM engine clock is source from system clock, otherwise a transition value of PWM counter may be read.
- */
- __I uint32_t CNT[6];
-
- /**
- * MSKEN
- * ===================================================================================================
- * Offset: 0x58 PWM Mask Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |MSKEN |PWM Mask Enable Control
- * | | |The PWM output signal will be masked when this bit is enabled.
- * | | |The corresponding PWMn channel will be output with MSKDAT data.
- * | | |0 = PWM output signal is non-masked.
- * | | |1 = PWM output signal is masked and output with MSKDAT data.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t MSKEN;
-
- /**
- * MSK
- * ===================================================================================================
- * Offset: 0x5C PWM Mask Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |MSKDAT |PWM Mask Data Bit:
- * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
- * | | |0 = Output logic low to PWMn.
- * | | |1 = Output logic high to PWMn.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t MSK;
-
- /**
- * DTCTL
- * ===================================================================================================
- * Offset: 0x60 PWM Dead-zone Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DTCNT01 |Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1
- * | | |These 8-bit determine the Dead-zone length.
- * | | |The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
- * |[8:15] |DTCNT23 |Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3
- * | | |These 8-bit determine the Dead-zone length.
- * | | |The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
- * |[16:23] |DTCNT45 |Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5
- * | | |These 8-bit determine the Dead-zone length.
- * | | |The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
- * |[24:25] |DTDIV |Dead-Zone Generator Divider
- * | | |00 = Dead-zone clock equal to PWM base clock divide 1.
- * | | |01 = Dead-zone clock equal to PWM base clock divide 2.
- * | | |10 = Dead-zone clock equal to PWM base clock divide 4.
- * | | |11 = Dead-zone clock equal to PWM base clock divide 8.
- * |[28] |DTEN01 |Dead-Zone Enable Control For PWM Pair Of Channel 0 And Channel 1
- * | | |Dead-zone insertion is only active when this pair of complementary PWM is enabled.
- * | | |If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-zone insertion Disabled.
- * | | |1 = Dead-zone insertion Enabled.
- * |[29] |DTEN23 |Dead-Zone Enable Control For PWM Pair Of Channel 2 And Channel 3
- * | | |Dead-zone insertion is only active when this pair of complementary PWM is enabled.
- * | | |If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-zone insertion Disabled.
- * | | |1 = Dead-zone insertion Enabled.
- * |[30] |DTEN45 |Dead-Zone Enable Control For PWM Pair Of Channel 4 And Channel 5
- * | | |Dead-zone insertion is only active when this pair of complementary PWM is enabled.
- * | | |If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
- * | | |0 = Dead-zone insertion Disabled.
- * | | |1 = Dead-zone insertion Enabled.
- */
- __IO uint32_t DTCTL;
-
- /**
- * TRGADCTL
- * ===================================================================================================
- * Offset: 0x64 PWM Trigger Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |PTRGEN |PWM Period Point Trigger Enable Control
- * | | |0 = PWM period point trigger ADC function Disabled.
- * | | |1 = PWM period point trigger ADC function Enabled.
- * | | |PWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1.
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[8:13] |CTRGEN |PWM Center Point Trigger Enable Control
- * | | |0 = PWM center point trigger ADC function Disabled.
- * | | |1 = PWM center point trigger ADC function Enabled.
- * | | |PWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1.
- * | | |Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
- * | | |Note2: Each bit controls the corresponding PWM channel.
- * |[16:21] |FTRGEN |PWM Falling Edge Point Trigger Enable Control
- * | | |0 = PWM falling edge point trigger ADC function Disabled.
- * | | |1 = PWM falling edge point trigger ADC function Enabled.
- * | | |PWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1.
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[24:29] |RTRGEN |PWM Rising Edge Point Trigger Enable Control
- * | | |0 = PWM rising edge point trigger ADC function Disabled.
- * | | |1 = PWM rising edge point trigger ADC function Enabled.
- * | | |PWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t TRGADCTL;
-
- /**
- * TRGADCSTS
- * ===================================================================================================
- * Offset: 0x68 PWM Trigger ADC Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |PTRGF |PWM Period Point Trigger Flag
- * | | |This bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1.
- * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
- * | | |Note1: Write 1 to clear this bit.
- * | | |Note2: Each bit controls the corresponding PWM channel.
- * |[8:13] |CTRGF |PWM Center Point Trigger Flag
- * | | |This bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1.
- * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
- * | | |Note1: Write 1 to clear this bit.
- * | | |Note2: Each bit controls the corresponding PWM channel.
- * |[16:21] |FTRGF |PWM Falling Edge Point Trigger Indicator
- * | | |This bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1.
- * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
- * | | |Note1: Write 1 to clear this bit.
- * | | |Note2: Each bit controls the corresponding PWM channel.
- * |[24:29] |RTRGF |PWM Rising Edge Point Trigger Indicator
- * | | |This bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1.
- * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
- * | | |Note1: Write 1 to clear this bit.
- * | | |Note2: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t TRGADCSTS;
-
- /**
- * BRKCTL
- * ===================================================================================================
- * Offset: 0x6C PWM Brake Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BRKP0EN |Brake0 Function Enable Control
- * | | |0 = Brake0 detect function Disabled.
- * | | |1 = Brake0 detect function Enabled.
- * |[1] |BRK0NFDIS |PWM Brake 0 Noise Filter Disable Control
- * | | |0 = Noise filter of PWM Brake 0 Enabled.
- * | | |1 = Noise filter of PWM Brake 0 Disabled.
- * |[2] |BRK0INV |Inverse BKP0 State
- * | | |0 = The state of pin BKPx0 is passed to the negative edge detector.
- * | | |1 = The inversed state of pin BKPx0 is passed to the negative edge detector.
- * |[6:7] |BRK0NFSEL |Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection
- * | | |00 = Filter clock = HCLK.
- * | | |01 = Filter clock = HCLK/2.
- * | | |10 = Filter clock = HCLK/4.
- * | | |11 = Filter clock = HCLK/16.
- * |[8] |BRKP1EN |Brake1 Function Enable Control
- * | | |0 = Brake1 function Disabled.
- * | | |1 = Brake1 function Enabled.
- * |[9] |BRK1NFDIS |PWM Brake 1 Noise Filter Disable Control
- * | | |0 = Noise filter of PWM Brake 1 Enabled.
- * | | |1 = Noise filter of PWM Brake 1 Disabled.
- * |[10] |BRK1INV |Inverse BKP1 State
- * | | |0 = The state of pin BKPx1 is passed to the negative edge detector.
- * | | |1 = The inversed state of pin BKPx1 is passed to the negative edge detector.
- * |[12:13] |BK1SEL |Brake Function 1 Source Selection
- * | | |00 = From external pin BKP1.
- * | | |01 = From analog comparator 0 output (CPO0).
- * | | |10 = From analog comparator 1 output (CPO1).
- * | | |11 = Reserved.
- * |[14:15] |BRK1NFSEL |Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection
- * | | |00 = Filter clock = HCLK.
- * | | |01 = Filter clock = HCLK/2.
- * | | |10 = Filter clock = HCLK/4.
- * | | |11 = Filter clock = HCLK/16.
- * |[16] |CPO0BKEN |CPO0 Digital Output As Brake0 Source Enable Control
- * | | |0 = CPO0 as one brake source in Brake 0 Disabled.
- * | | |1 = CPO0 as one brake source in Brake 0 Enabled.
- * |[17] |CPO1BKEN |CPO1 Digital Output As Brake 0 Source Enable Control
- * | | |0 = CPO1 as one brake source in Brake 0 Disabled.
- * | | |1 = CPO1 as one brake source in Brake 0 Enabled.
- * |[18] |CPO2BKEN |CPO2 Digital Output As Brake 0 Source Enable Control
- * | | |0 = CPO2 as one brake source in Brake 0 Disabled.
- * | | |1 = CPO2 as one brake source in Brake 0 Enabled.
- * |[19] |LVDBKEN |Low-Level Detection Trigger PWM Brake Function 1 Enable Control
- * | | |0 = Brake Function 1 triggered by Low-level detection Disabled.
- * | | |1 = Brake Function 1 triggered by Low-level detection Enabled.
- * |[24:29] |BKOD |PWM Brake Output Data Register
- * | | |0 = PWM output low when fault brake conditions asserted.
- * | | |1 = PWM output high when fault brake conditions asserted.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t BRKCTL;
-
- /**
- * INTCTL
- * ===================================================================================================
- * Offset: 0x70 PWM Interrupt Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |PINTTYPE |PWM Period Interrupt Type Selection
- * | | |0 = PIF[n] will be set if PWM counter underflow.
- * | | |1 = PIF[n] will be set if PWM counter matches PWM_PERIODn register.
- * | | |Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
- * | | |Note2: Each bit controls the corresponding PWM channel.
- * |[8:13] |DINTTYPE |PWM Duty Interrupt Type Selection
- * | | |0 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting.
- * | | |1 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during up counting.
- * | | |Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
- * | | |Note2: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t INTCTL;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x74 PWM Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |PIEN |PWM Period Interrupt Enable Control
- * | | |0 = Period interrupt Disabled.
- * | | |1 = Period interrupt Enabled.
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[6] |BRKIEN |Brake0 And Brak1 Interrupt Enable Control
- * | | |0 = Disabling flags BFK0 and BFK1 to trigger PWM interrupt.
- * | | |1 = Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt.
- * |[8:13] |DIEN |PWM Duty Interrupt Enable Control
- * | | |0 = Duty interrupt Disabled.
- * | | |1 = Duty interrupt Enabled.
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[16:21] |RLIEN |Rising Latch Interrupt Enable Control
- * | | |0 = Rising latch interrupt Disabled.
- * | | |1 = Rising latch interrupt Enabled.
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[24:29] |FLIEN |Falling Latch Interrupt Enable Control
- * | | |0 = Falling latch interrupt Disabled.
- * | | |1 = Falling latch interrupt Enabled.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x78 PWM Interrupt Flag Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |PIF |PWM Period Interrupt Flag
- * | | |This bit is set by hardware when PWM counter reaches the requirement condition of interrupt (depending on PINTTYPE (PWM_INTCTL[n]) ).
- * | | |Software can write 1 to clear this bit to 0.
- * |[6] |BRKIF0 |PWM Brake0 Flag
- * | | |0 = PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one.
- * | | |1 = When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[7] |BRKIF1 |PWM Brake1 Flag
- * | | |0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one.
- * | | |1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[8:13] |DIF |PWM Duty Interrupt Flag
- * | | |Flag is set by hardware when channel 0 PWM counter down count and reaches CMP0.
- * | | |Software can clear this bit by writing 1 to it.
- * | | |Note: If CMP is equal to PERIOD, this flag is not working in edge-aligned type selection.
- * |[14] |BRKLK0 |PWM Brake0 Locked
- * | | |0 = Brake 0 state is released.
- * | | |1 = When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[16:21] |CRLIF |Capture Rising Latch Interrupt Flag
- * | | |0 = No capture rising latch condition happened.
- * | | |1 = Capture rising latch condition happened, this flag will be set to high.
- * | | |Note: This bit must be cleared by writing 1 to it.
- * |[22] |BRKSTS0 |Brake 0 Status (Read Only)
- * | | |0 = PWM had been out of Brake 0 state.
- * | | |1 = PWM is in Brake 0 state.
- * |[23] |BRKSTS1 |Brake 1 Status (Read Only)
- * | | |0 = PWM had been out of Brake 1 state.
- * | | |1 = PWM is in Brake 1 state.
- * |[24:29] |CFLIF |Capture Falling Latch Interrupt Flag
- * | | |0 = No capture falling latch condition happened.
- * | | |1 = Capture falling latch condition happened, this flag will be set to high.
- * | | |Note: This bit must be cleared by writing 1 to it.
- */
- __IO uint32_t INTSTS;
-
- /**
- * POEN
- * ===================================================================================================
- * Offset: 0x7C PWM Output Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |POEN |PWM Pin Output Enable Control
- * | | |0 = PWM pin at tri-state.
- * | | |1 = PWM pin in output mode.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t POEN;
-
- /**
- * CAPCTL
- * ===================================================================================================
- * Offset: 0x80 PWM Capture Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |CAPEN |Capture Function Enable Control
- * | | |0 = Capture function Disabled. RCAPDAT and FCAPDAT will not be updated.
- * | | |1 = Capture function Enabled.
- * | | |Capture latched the PWM counter value and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[8:13] |CAPINV |Capture Inverter Enable Control
- * | | |0 = Capture source inverter Disabled.
- * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO
- * | | |Note: Each bit controls the corresponding PWM channel.
- * |[16:21] |RCRLDEN |Rising Latch Reload Enable Control
- * | | |0 = Rising latch reload counter Enabled.
- * | | |1 = Rising latch reload counter Enabled.
- * |[24:29] |FCRLDEN |Falling Latch Reload Enable Control
- * | | |0 = Falling latch reload counter Disabled.
- * | | |1 = Falling latch
- * | | |reload counter Enabled.
- */
- __IO uint32_t CAPCTL;
-
- /**
- * CAPINEN
- * ===================================================================================================
- * Offset: 0x84 PWM Capture Input Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |CAPINEN |Capture Input Enable Control
- * | | |0 = PWM Channel capture input path Disabled.
- * | | |The input of PWM channel capture function is always regarded as 0.
- * | | |1 = PWM Channel capture input path Enabled.
- * | | |The input of PWM channel capture function comes from correlative multifunction pin.
- * | | |Note: Each bit controls the corresponding PWM channel.
- */
- __IO uint32_t CAPINEN;
-
- /**
- * CAPSTS
- * ===================================================================================================
- * Offset: 0x88 PWM Capture Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |CRIFOV |Rising Latch Interrupt Flag Overrun Status
- * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1
- * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
- * |[8:13] |FLIFOV |Falling Latch Interrupt Flag Overrun Status
- * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1
- * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
- */
- __I uint32_t CAPSTS;
- uint32_t RESERVE0[1];
-
-
- /**
- * RCAPDAT0
- * ===================================================================================================
- * Offset: 0x90 PWM Capture Rising Latch Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RCAPDAT |Capture Rising Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
- */
- __I uint32_t RCAPDAT0;
-
- /**
- * FCAPDAT0
- * ===================================================================================================
- * Offset: 0x94 PWM Capture Falling Latch Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FCAPDAT |Capture Falling Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
- */
- __I uint32_t FCAPDAT0;
-
- /**
- * RCAPDAT1
- * ===================================================================================================
- * Offset: 0x98 PWM Capture Rising Latch Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RCAPDAT |Capture Rising Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
- */
- __I uint32_t RCAPDAT1;
-
- /**
- * FCAPDAT1
- * ===================================================================================================
- * Offset: 0x9C PWM Capture Falling Latch Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FCAPDAT |Capture Falling Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
- */
- __I uint32_t FCAPDAT1;
-
- /**
- * RCAPDAT2
- * ===================================================================================================
- * Offset: 0xA0 PWM Capture Rising Latch Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RCAPDAT |Capture Rising Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
- */
- __I uint32_t RCAPDAT2;
-
- /**
- * FCAPDAT2
- * ===================================================================================================
- * Offset: 0xA4 PWM Capture Falling Latch Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FCAPDAT |Capture Falling Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
- */
- __I uint32_t FCAPDAT2;
-
- /**
- * RCAPDAT3
- * ===================================================================================================
- * Offset: 0xA8 PWM Capture Rising Latch Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RCAPDAT |Capture Rising Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
- */
- __I uint32_t RCAPDAT3;
-
- /**
- * FCAPDAT3
- * ===================================================================================================
- * Offset: 0xAC PWM Capture Falling Latch Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FCAPDAT |Capture Falling Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
- */
- __I uint32_t FCAPDAT3;
-
- /**
- * RCAPDAT4
- * ===================================================================================================
- * Offset: 0xB0 PWM Capture Rising Latch Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RCAPDAT |Capture Rising Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
- */
- __I uint32_t RCAPDAT4;
-
- /**
- * FCAPDAT4
- * ===================================================================================================
- * Offset: 0xB4 PWM Capture Falling Latch Register 4
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FCAPDAT |Capture Falling Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
- */
- __I uint32_t FCAPDAT4;
-
- /**
- * RCAPDAT5
- * ===================================================================================================
- * Offset: 0xB8 PWM Capture Rising Latch Register 5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RCAPDAT |Capture Rising Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
- */
- __I uint32_t RCAPDAT5;
-
- /**
- * FCAPDAT5
- * ===================================================================================================
- * Offset: 0xBC PWM Capture Falling Latch Register 5
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FCAPDAT |Capture Falling Latch Register
- * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
- */
- __I uint32_t FCAPDAT5;
- uint32_t RESERVE1[8];
-
-
- /**
- * SBS0
- * ===================================================================================================
- * Offset: 0xE0 PWM0 Synchronous Busy Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SYNCBUSY |PWM Synchronous Busy
- * | | |When software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (CONR[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
- * | | |Software needs to check this busy status before writes PWM_PERIOD0/PWM_CMPDAT0/ PWM_CLKPSC or switch PWM0 counter operation mode to make sure previous setting has been update completely.
- * | | |This bit will be set when software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 operation mode CNTMOD (CONR[16]) and will be cleared by hardware automatically when PWM update these value completely.
- */
- __I uint32_t SBS[6];
-
-} PWM_T;
-
-/**
- @addtogroup PWM_CONST PWM Bit Field Definition
- Constant Definitions for PWM Controller
-@{ */
-
-#define PWM_CLKPSC_CLKPSC01_Pos (0) /*!< PWM CLKPSC: CLKPSC01 Position */
-#define PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos) /*!< PWM CLKPSC: CLKPSC01 Mask */
-
-#define PWM_CLKPSC_CLKPSC23_Pos (8) /*!< PWM CLKPSC: CLKPSC23 Position */
-#define PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos) /*!< PWM CLKPSC: CLKPSC23 Mask */
-
-#define PWM_CLKPSC_CLKPSC45_Pos (16) /*!< PWM CLKPSC: CLKPSC45 Position */
-#define PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos) /*!< PWM CLKPSC: CLKPSC45 Mask */
-
-#define PWM_CLKDIV_CLKDIV0_Pos (0) /*!< PWM CLKDIV: CLKDIV0 Position */
-#define PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos) /*!< PWM CLKDIV: CLKDIV0 Mask */
-
-#define PWM_CLKDIV_CLKDIV1_Pos (4) /*!< PWM CLKDIV: CLKDIV1 Position */
-#define PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos) /*!< PWM CLKDIV: CLKDIV1 Mask */
-
-#define PWM_CLKDIV_CLKDIV2_Pos (8) /*!< PWM CLKDIV: CLKDIV2 Position */
-#define PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos) /*!< PWM CLKDIV: CLKDIV2 Mask */
-
-#define PWM_CLKDIV_CLKDIV3_Pos (12) /*!< PWM CLKDIV: CLKDIV3 Position */
-#define PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos) /*!< PWM CLKDIV: CLKDIV3 Mask */
-
-#define PWM_CLKDIV_CLKDIV4_Pos (16) /*!< PWM CLKDIV: CLKDIV4 Position */
-#define PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos) /*!< PWM CLKDIV: CLKDIV4 Mask */
-
-#define PWM_CLKDIV_CLKDIV5_Pos (20) /*!< PWM CLKDIV: CLKDIV5 Position */
-#define PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos) /*!< PWM CLKDIV: CLKDIV5 Mask */
-
-#define PWM_CTL_CMPINV_Pos (0) /*!< PWM CTL: CMPINV Position */
-#define PWM_CTL_CMPINV_Msk (0x3ful << PWM_CTL_CMPINV_Pos) /*!< PWM CTL: CMPINV Mask */
-
-#define PWM_CTL_OUTMODE_Pos (6) /*!< PWM CTL: OUTMODE Position */
-#define PWM_CTL_OUTMODE_Msk (0x1ul << PWM_CTL_OUTMODE_Pos) /*!< PWM CTL: OUTMODE Mask */
-
-#define PWM_CTL_GROUPEN_Pos (7) /*!< PWM CTL: GROUPEN Position */
-#define PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos) /*!< PWM CTL: GROUPEN Mask */
-
-#define PWM_CTL_PINV_Pos (8) /*!< PWM CTL: PINV Position */
-#define PWM_CTL_PINV_Msk (0x3ful << PWM_CTL_PINV_Pos) /*!< PWM CTL: PINV Mask */
-
-#define PWM_CTL_SYNCEN_Pos (15) /*!< PWM CTL: SYNCEN Position */
-#define PWM_CTL_SYNCEN_Msk (0x1ul << PWM_CTL_SYNCEN_Pos) /*!< PWM CTL: SYNCEN Mask */
-
-#define PWM_CTL_CNTMODE_Pos (16) /*!< PWM CTL: CNTMODE Position */
-#define PWM_CTL_CNTMODE_Msk (0x3ful << PWM_CTL_CNTMODE_Pos) /*!< PWM CTL: CNTMODE Mask */
-
-#define PWM_CTL_CNTTYPE_Pos (24) /*!< PWM CTL: CNTTYPE Position */
-#define PWM_CTL_CNTTYPE_Msk (0x3ful << PWM_CTL_CNTTYPE_Pos) /*!< PWM CTL: CNTTYPE Mask */
-
-#define PWM_CTL_DBGTRIOFF_Pos (31) /*!< PWM CTL: DBGTRIOFF Position */
-#define PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos) /*!< PWM CTL: DBGTRIOFF Mask */
-
-#define PWM_CNTEN_CNTEN_Pos (0) /*!< PWM CNTEN: CNTEN Position */
-#define PWM_CNTEN_CNTEN_Msk (0x3ful << PWM_CNTEN_CNTEN_Pos) /*!< PWM CNTEN: CNTEN Mask */
-
-#define PWM_PERIOD0_PERIOD_Pos (0) /*!< PWM PERIOD0: PERIOD Position */
-#define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) /*!< PWM PERIOD0: PERIOD Mask */
-
-#define PWM_PERIOD1_PERIOD_Pos (0) /*!< PWM PERIOD1: PERIOD Position */
-#define PWM_PERIOD1_PERIOD_Msk (0xfffful << PWM_PERIOD1_PERIOD_Pos) /*!< PWM PERIOD1: PERIOD Mask */
-
-#define PWM_PERIOD2_PERIOD_Pos (0) /*!< PWM PERIOD2: PERIOD Position */
-#define PWM_PERIOD2_PERIOD_Msk (0xfffful << PWM_PERIOD2_PERIOD_Pos) /*!< PWM PERIOD2: PERIOD Mask */
-
-#define PWM_PERIOD3_PERIOD_Pos (0) /*!< PWM PERIOD3: PERIOD Position */
-#define PWM_PERIOD3_PERIOD_Msk (0xfffful << PWM_PERIOD3_PERIOD_Pos) /*!< PWM PERIOD3: PERIOD Mask */
-
-#define PWM_PERIOD4_PERIOD_Pos (0) /*!< PWM PERIOD4: PERIOD Position */
-#define PWM_PERIOD4_PERIOD_Msk (0xfffful << PWM_PERIOD4_PERIOD_Pos) /*!< PWM PERIOD4: PERIOD Mask */
-
-#define PWM_PERIOD5_PERIOD_Pos (0) /*!< PWM PERIOD5: PERIOD Position */
-#define PWM_PERIOD5_PERIOD_Msk (0xfffful << PWM_PERIOD5_PERIOD_Pos) /*!< PWM PERIOD5: PERIOD Mask */
-
-#define PWM_CMPDAT0_CMP_Pos (0) /*!< PWM CMPDAT0: CMP Position */
-#define PWM_CMPDAT0_CMP_Msk (0xfffful << PWM_CMPDAT0_CMP_Pos) /*!< PWM CMPDAT0: CMP Mask */
-
-#define PWM_CMPDAT1_CMP_Pos (0) /*!< PWM CMPDAT1: CMP Position */
-#define PWM_CMPDAT1_CMP_Msk (0xfffful << PWM_CMPDAT1_CMP_Pos) /*!< PWM CMPDAT1: CMP Mask */
-
-#define PWM_CMPDAT2_CMP_Pos (0) /*!< PWM CMPDAT2: CMP Position */
-#define PWM_CMPDAT2_CMP_Msk (0xfffful << PWM_CMPDAT2_CMP_Pos) /*!< PWM CMPDAT2: CMP Mask */
-
-#define PWM_CMPDAT3_CMP_Pos (0) /*!< PWM CMPDAT3: CMP Position */
-#define PWM_CMPDAT3_CMP_Msk (0xfffful << PWM_CMPDAT3_CMP_Pos) /*!< PWM CMPDAT3: CMP Mask */
-
-#define PWM_CMPDAT4_CMP_Pos (0) /*!< PWM CMPDAT4: CMP Position */
-#define PWM_CMPDAT4_CMP_Msk (0xfffful << PWM_CMPDAT4_CMP_Pos) /*!< PWM CMPDAT4: CMP Mask */
-
-#define PWM_CMPDAT5_CMP_Pos (0) /*!< PWM CMPDAT5: CMP Position */
-#define PWM_CMPDAT5_CMP_Msk (0xfffful << PWM_CMPDAT5_CMP_Pos) /*!< PWM CMPDAT5: CMP Mask */
-
-#define PWM_CNT0_CNT_Pos (0) /*!< PWM CNT0: CNT Position */
-#define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos) /*!< PWM CNT0: CNT Mask */
-
-#define PWM_CNT1_CNT_Pos (0) /*!< PWM CNT1: CNT Position */
-#define PWM_CNT1_CNT_Msk (0xfffful << PWM_CNT1_CNT_Pos) /*!< PWM CNT1: CNT Mask */
-
-#define PWM_CNT2_CNT_Pos (0) /*!< PWM CNT2: CNT Position */
-#define PWM_CNT2_CNT_Msk (0xfffful << PWM_CNT2_CNT_Pos) /*!< PWM CNT2: CNT Mask */
-
-#define PWM_CNT3_CNT_Pos (0) /*!< PWM CNT3: CNT Position */
-#define PWM_CNT3_CNT_Msk (0xfffful << PWM_CNT3_CNT_Pos) /*!< PWM CNT3: CNT Mask */
-
-#define PWM_CNT4_CNT_Pos (0) /*!< PWM CNT4: CNT Position */
-#define PWM_CNT4_CNT_Msk (0xfffful << PWM_CNT4_CNT_Pos) /*!< PWM CNT4: CNT Mask */
-
-#define PWM_CNT5_CNT_Pos (0) /*!< PWM CNT5: CNT Position */
-#define PWM_CNT5_CNT_Msk (0xfffful << PWM_CNT5_CNT_Pos) /*!< PWM CNT5: CNT Mask */
-
-#define PWM_MSKEN_MSKEN_Pos (0) /*!< PWM MSKEN: MSKEN Position */
-#define PWM_MSKEN_MSKEN_Msk (0x3ful << PWM_MSKEN_MSKEN_Pos) /*!< PWM MSKEN: MSKEN Mask */
-
-#define PWM_MSK_MSKDAT_Pos (0) /*!< PWM MSK: MSKDAT Position */
-#define PWM_MSK_MSKDAT_Msk (0x3ful << PWM_MSK_MSKDAT_Pos) /*!< PWM MSK: MSKDAT Mask */
-
-#define PWM_DTCTL_DTCNT01_Pos (0) /*!< PWM DTCTL: DTCNT01 Position */
-#define PWM_DTCTL_DTCNT01_Msk (0xfful << PWM_DTCTL_DTCNT01_Pos) /*!< PWM DTCTL: DTCNT01 Mask */
-
-#define PWM_DTCTL_DTCNT23_Pos (8) /*!< PWM DTCTL: DTCNT23 Position */
-#define PWM_DTCTL_DTCNT23_Msk (0xfful << PWM_DTCTL_DTCNT23_Pos) /*!< PWM DTCTL: DTCNT23 Mask */
-
-#define PWM_DTCTL_DTCNT45_Pos (16) /*!< PWM DTCTL: DTCNT45 Position */
-#define PWM_DTCTL_DTCNT45_Msk (0xfful << PWM_DTCTL_DTCNT45_Pos) /*!< PWM DTCTL: DTCNT45 Mask */
-
-#define PWM_DTCTL_DTDIV_Pos (24) /*!< PWM DTCTL: DTDIV Position */
-#define PWM_DTCTL_DTDIV_Msk (0x3ul << PWM_DTCTL_DTDIV_Pos) /*!< PWM DTCTL: DTDIV Mask */
-
-#define PWM_DTCTL_DTEN01_Pos (28) /*!< PWM DTCTL: DTEN01 Position */
-#define PWM_DTCTL_DTEN01_Msk (0x1ul << PWM_DTCTL_DTEN01_Pos) /*!< PWM DTCTL: DTEN01 Mask */
-
-#define PWM_DTCTL_DTEN23_Pos (29) /*!< PWM DTCTL: DTEN23 Position */
-#define PWM_DTCTL_DTEN23_Msk (0x1ul << PWM_DTCTL_DTEN23_Pos) /*!< PWM DTCTL: DTEN23 Mask */
-
-#define PWM_DTCTL_DTEN45_Pos (30) /*!< PWM DTCTL: DTEN45 Position */
-#define PWM_DTCTL_DTEN45_Msk (0x1ul << PWM_DTCTL_DTEN45_Pos) /*!< PWM DTCTL: DTEN45 Mask */
-
-#define PWM_TRGADCTL_PTRGEN_Pos (0) /*!< PWM TRGADCTL: PTRGEN Position */
-#define PWM_TRGADCTL_PTRGEN_Msk (0x3ful << PWM_TRGADCTL_PTRGEN_Pos) /*!< PWM TRGADCTL: PTRGEN Mask */
-
-#define PWM_TRGADCTL_CTRGEN_Pos (8) /*!< PWM TRGADCTL: CTRGEN Position */
-#define PWM_TRGADCTL_CTRGEN_Msk (0x3ful << PWM_TRGADCTL_CTRGEN_Pos) /*!< PWM TRGADCTL: CTRGEN Mask */
-
-#define PWM_TRGADCTL_FTRGEN_Pos (16) /*!< PWM TRGADCTL: FTRGEN Position */
-#define PWM_TRGADCTL_FTRGEN_Msk (0x3ful << PWM_TRGADCTL_FTRGEN_Pos) /*!< PWM TRGADCTL: FTRGEN Mask */
-
-#define PWM_TRGADCTL_RTRGEN_Pos (24) /*!< PWM TRGADCTL: RTRGEN Position */
-#define PWM_TRGADCTL_RTRGEN_Msk (0x3ful << PWM_TRGADCTL_RTRGEN_Pos) /*!< PWM TRGADCTL: RTRGEN Mask */
-
-#define PWM_TRGADCSTS_PTRGF_Pos (0) /*!< PWM TRGADCSTS: PTRGF Position */
-#define PWM_TRGADCSTS_PTRGF_Msk (0x3ful << PWM_TRGADCSTS_PTRGF_Pos) /*!< PWM TRGADCSTS: PTRGF Mask */
-
-#define PWM_TRGADCSTS_CTRGF_Pos (8) /*!< PWM TRGADCSTS: CTRGF Position */
-#define PWM_TRGADCSTS_CTRGF_Msk (0x3ful << PWM_TRGADCSTS_CTRGF_Pos) /*!< PWM TRGADCSTS: CTRGF Mask */
-
-#define PWM_TRGADCSTS_FTRGF_Pos (16) /*!< PWM TRGADCSTS: FTRGF Position */
-#define PWM_TRGADCSTS_FTRGF_Msk (0x3ful << PWM_TRGADCSTS_FTRGF_Pos) /*!< PWM TRGADCSTS: FTRGF Mask */
-
-#define PWM_TRGADCSTS_RTRGF_Pos (24) /*!< PWM TRGADCSTS: RTRGF Position */
-#define PWM_TRGADCSTS_RTRGF_Msk (0x3ful << PWM_TRGADCSTS_RTRGF_Pos) /*!< PWM TRGADCSTS: RTRGF Mask */
-
-#define PWM_BRKCTL_BRK0EN_Pos (0) /*!< PWM BRKCTL: BRK0EN Position */
-#define PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos) /*!< PWM BRKCTL: BRK0EN Mask */
-
-#define PWM_BRKCTL_BRK0NFDIS_Pos (1) /*!< PWM BRKCTL: BRK0NFDIS Position */
-#define PWM_BRKCTL_BRK0NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK0NFDIS_Pos) /*!< PWM BRKCTL: BRK0NFDIS Mask */
-
-#define PWM_BRKCTL_BRK0INV_Pos (2) /*!< PWM BRKCTL: BRK0INV Position */
-#define PWM_BRKCTL_BRK0INV_Msk (0x1ul << PWM_BRKCTL_BRK0INV_Pos) /*!< PWM BRKCTL: BRK0INV Mask */
-
-#define PWM_BRKCTL_BRK0NFSEL_Pos (6) /*!< PWM BRKCTL: BRK0NFSEL Position */
-#define PWM_BRKCTL_BRK0NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK0NFSEL_Pos) /*!< PWM BRKCTL: BRK0NFSEL Mask */
-
-#define PWM_BRKCTL_BRK1EN_Pos (8) /*!< PWM BRKCTL: BRK1EN Position */
-#define PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos) /*!< PWM BRKCTL: BRK1EN Mask */
-
-#define PWM_BRKCTL_BRK1NFDIS_Pos (9) /*!< PWM BRKCTL: BRK1NFDIS Position */
-#define PWM_BRKCTL_BRK1NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK1NFDIS_Pos) /*!< PWM BRKCTL: BRK1NFDIS Mask */
-
-#define PWM_BRKCTL_BRK1INV_Pos (10) /*!< PWM BRKCTL: BRK1INV Position */
-#define PWM_BRKCTL_BRK1INV_Msk (0x1ul << PWM_BRKCTL_BRK1INV_Pos) /*!< PWM BRKCTL: BRK1INV Mask */
-
-#define PWM_BRKCTL_BK1SEL_Pos (12) /*!< PWM BRKCTL: BK1SEL Position */
-#define PWM_BRKCTL_BK1SEL_Msk (0x3ul << PWM_BRKCTL_BK1SEL_Pos) /*!< PWM BRKCTL: BK1SEL Mask */
-
-#define PWM_BRKCTL_BRK1NFSEL_Pos (14) /*!< PWM BRKCTL: BRK1NFSEL Position */
-#define PWM_BRKCTL_BRK1NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK1NFSEL_Pos) /*!< PWM BRKCTL: BRK1NFSEL Mask */
-
-#define PWM_BRKCTL_CPO0BKEN_Pos (16) /*!< PWM BRKCTL: CPO0BKEN Position */
-#define PWM_BRKCTL_CPO0BKEN_Msk (0x1ul << PWM_BRKCTL_CPO0BKEN_Pos) /*!< PWM BRKCTL: CPO0BKEN Mask */
-
-#define PWM_BRKCTL_CPO1BKEN_Pos (17) /*!< PWM BRKCTL: CPO1BKEN Position */
-#define PWM_BRKCTL_CPO1BKEN_Msk (0x1ul << PWM_BRKCTL_CPO1BKEN_Pos) /*!< PWM BRKCTL: CPO1BKEN Mask */
-
-#define PWM_BRKCTL_CPO2BKEN_Pos (18) /*!< PWM BRKCTL: CPO2BKEN Position */
-#define PWM_BRKCTL_CPO2BKEN_Msk (0x1ul << PWM_BRKCTL_CPO2BKEN_Pos) /*!< PWM BRKCTL: CPO2BKEN Mask */
-
-#define PWM_BRKCTL_LVDBKEN_Pos (19) /*!< PWM BRKCTL: LVDBKEN Position */
-#define PWM_BRKCTL_LVDBKEN_Msk (0x1ul << PWM_BRKCTL_LVDBKEN_Pos) /*!< PWM BRKCTL: LVDBKEN Mask */
-
-#define PWM_BRKCTL_BKOD_Pos (24) /*!< PWM BRKCTL: BKOD Position */
-#define PWM_BRKCTL_BKOD_Msk (0x3ful << PWM_BRKCTL_BKOD_Pos) /*!< PWM BRKCTL: BKOD Mask */
-
-#define PWM_INTCTL_PINTTYPE_Pos (0) /*!< PWM INTCTL: PINTTYPE Position */
-#define PWM_INTCTL_PINTTYPE_Msk (0x3ful << PWM_INTCTL_PINTTYPE_Pos) /*!< PWM INTCTL: PINTTYPE Mask */
-
-#define PWM_INTCTL_DINTTYPE_Pos (8) /*!< PWM INTCTL: DINTTYPE Position */
-#define PWM_INTCTL_DINTTYPE_Msk (0x3ful << PWM_INTCTL_DINTTYPE_Pos) /*!< PWM INTCTL: DINTTYPE Mask */
-
-#define PWM_INTEN_PIEN_Pos (0) /*!< PWM INTEN: PIEN Position */
-#define PWM_INTEN_PIEN_Msk (0x3ful << PWM_INTEN_PIEN_Pos) /*!< PWM INTEN: PIEN Mask */
-
-#define PWM_INTEN_BRKIEN_Pos (6) /*!< PWM INTEN: BRKIEN Position */
-#define PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos) /*!< PWM INTEN: BRKIEN Mask */
-
-#define PWM_INTEN_DIEN_Pos (8) /*!< PWM INTEN: DIEN Position */
-#define PWM_INTEN_DIEN_Msk (0x3ful << PWM_INTEN_DIEN_Pos) /*!< PWM INTEN: DIEN Mask */
-
-#define PWM_INTEN_RLIEN_Pos (16) /*!< PWM INTEN: RLIEN Position */
-#define PWM_INTEN_RLIEN_Msk (0x3ful << PWM_INTEN_RLIEN_Pos) /*!< PWM INTEN: RLIEN Mask */
-
-#define PWM_INTEN_FLIEN_Pos (24) /*!< PWM INTEN: FLIEN Position */
-#define PWM_INTEN_FLIEN_Msk (0x3ful << PWM_INTEN_FLIEN_Pos) /*!< PWM INTEN: FLIEN Mask */
-
-#define PWM_INTSTS_PIF_Pos (0) /*!< PWM INTSTS: PIF Position */
-#define PWM_INTSTS_PIF_Msk (0x3ful << PWM_INTSTS_PIF_Pos) /*!< PWM INTSTS: PIF Mask */
-
-#define PWM_INTSTS_BRKIF0_Pos (6) /*!< PWM INTSTS: BRKIF0 Position */
-#define PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos) /*!< PWM INTSTS: BRKIF0 Mask */
-
-#define PWM_INTSTS_BRKIF1_Pos (7) /*!< PWM INTSTS: BRKIF1 Position */
-#define PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos) /*!< PWM INTSTS: BRKIF1 Mask */
-
-#define PWM_INTSTS_DIF_Pos (8) /*!< PWM INTSTS: DIF Position */
-#define PWM_INTSTS_DIF_Msk (0x3ful << PWM_INTSTS_DIF_Pos) /*!< PWM INTSTS: DIF Mask */
-
-#define PWM_INTSTS_BRKLK0_Pos (14) /*!< PWM INTSTS: BRKLK0 Position */
-#define PWM_INTSTS_BRKLK0_Msk (0x1ul << PWM_INTSTS_BRKLK0_Pos) /*!< PWM INTSTS: BRKLK0 Mask */
-
-#define PWM_INTSTS_CRLIF_Pos (16) /*!< PWM INTSTS: CRLIF Position */
-#define PWM_INTSTS_CRLIF_Msk (0x3ful << PWM_INTSTS_CRLIF_Pos) /*!< PWM INTSTS: CRLIF Mask */
-
-#define PWM_INTSTS_BRKSTS0_Pos (22) /*!< PWM INTSTS: BRKSTS0 Position */
-#define PWM_INTSTS_BRKSTS0_Msk (0x1ul << PWM_INTSTS_BRKSTS0_Pos) /*!< PWM INTSTS: BRKSTS0 Mask */
-
-#define PWM_INTSTS_BRKSTS1_Pos (23) /*!< PWM INTSTS: BRKSTS1 Position */
-#define PWM_INTSTS_BRKSTS1_Msk (0x1ul << PWM_INTSTS_BRKSTS1_Pos) /*!< PWM INTSTS: BRKSTS1 Mask */
-
-#define PWM_INTSTS_CFLIF_Pos (24) /*!< PWM INTSTS: CFLIF Position */
-#define PWM_INTSTS_CFLIF_Msk (0x3ful << PWM_INTSTS_CFLIF_Pos) /*!< PWM INTSTS: CFLIF Mask */
-
-#define PWM_POEN_POEN_Pos (0) /*!< PWM POEN: POEN Position */
-#define PWM_POEN_POEN_Msk (0x3ful << PWM_POEN_POEN_Pos) /*!< PWM POEN: POEN Mask */
-
-#define PWM_CAPCTL_CAPEN_Pos (0) /*!< PWM CAPCTL: CAPEN Position */
-#define PWM_CAPCTL_CAPEN_Msk (0x3ful << PWM_CAPCTL_CAPEN_Pos) /*!< PWM CAPCTL: CAPEN Mask */
-
-#define PWM_CAPCTL_CAPINV_Pos (8) /*!< PWM CAPCTL: CAPINV Position */
-#define PWM_CAPCTL_CAPINV_Msk (0x3ful << PWM_CAPCTL_CAPINV_Pos) /*!< PWM CAPCTL: CAPINV Mask */
-
-#define PWM_CAPCTL_RCRLDEN_Pos (16) /*!< PWM CAPCTL: RCRLDEN Position */
-#define PWM_CAPCTL_RCRLDEN_Msk (0x3ful << PWM_CAPCTL_RCRLDEN_Pos) /*!< PWM CAPCTL: RCRLDEN Mask */
-
-#define PWM_CAPCTL_FCRLDEN_Pos (24) /*!< PWM CAPCTL: FCRLDEN Position */
-#define PWM_CAPCTL_FCRLDEN_Msk (0x3ful << PWM_CAPCTL_FCRLDEN_Pos) /*!< PWM CAPCTL: FCRLDEN Mask */
-
-#define PWM_CAPINEN_CAPINEN_Pos (0) /*!< PWM CAPINEN: CAPINEN Position */
-#define PWM_CAPINEN_CAPINEN_Msk (0x3ful << PWM_CAPINEN_CAPINEN_Pos) /*!< PWM CAPINEN: CAPINEN Mask */
-
-#define PWM_CAPSTS_CRIFOV_Pos (0) /*!< PWM CAPSTS: CRIFOV Position */
-#define PWM_CAPSTS_CRIFOV_Msk (0x3ful << PWM_CAPSTS_CRIFOV_Pos) /*!< PWM CAPSTS: CRIFOV Mask */
-
-#define PWM_CAPSTS_FLIFOV_Pos (8) /*!< PWM CAPSTS: FLIFOV Position */
-#define PWM_CAPSTS_FLIFOV_Msk (0x3ful << PWM_CAPSTS_FLIFOV_Pos) /*!< PWM CAPSTS: FLIFOV Mask */
-
-#define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM RCAPDAT0: RCAPDAT Position */
-#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM RCAPDAT0: RCAPDAT Mask */
-
-#define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM FCAPDAT0: FCAPDAT Position */
-#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM FCAPDAT0: FCAPDAT Mask */
-
-#define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM RCAPDAT1: RCAPDAT Position */
-#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM RCAPDAT1: RCAPDAT Mask */
-
-#define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM FCAPDAT1: FCAPDAT Position */
-#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM FCAPDAT1: FCAPDAT Mask */
-
-#define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM RCAPDAT2: RCAPDAT Position */
-#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM RCAPDAT2: RCAPDAT Mask */
-
-#define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM FCAPDAT2: FCAPDAT Position */
-#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM FCAPDAT2: FCAPDAT Mask */
-
-#define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM RCAPDAT3: RCAPDAT Position */
-#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM RCAPDAT3: RCAPDAT Mask */
-
-#define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM FCAPDAT3: FCAPDAT Position */
-#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM FCAPDAT3: FCAPDAT Mask */
-
-#define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM RCAPDAT4: RCAPDAT Position */
-#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM RCAPDAT4: RCAPDAT Mask */
-
-#define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM FCAPDAT4: FCAPDAT Position */
-#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM FCAPDAT4: FCAPDAT Mask */
-
-#define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM RCAPDAT5: RCAPDAT Position */
-#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM RCAPDAT5: RCAPDAT Mask */
-
-#define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM FCAPDAT5: FCAPDAT Position */
-#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM FCAPDAT5: FCAPDAT Mask */
-
-#define PWM_SBS0_SYNCBUSY_Pos (0) /*!< PWM SBS0: SYNCBUSY Position */
-#define PWM_SBS0_SYNCBUSY_Msk (0x1ul << PWM_SBS0_SYNCBUSY_Pos) /*!< PWM SBS0: SYNCBUSY Mask */
-
-#define PWM_SBS1_SYNCBUSY_Pos (0) /*!< PWM SBS1: SYNCBUSY Position */
-#define PWM_SBS1_SYNCBUSY_Msk (0x1ul << PWM_SBS1_SYNCBUSY_Pos) /*!< PWM SBS1: SYNCBUSY Mask */
-
-#define PWM_SBS2_SYNCBUSY_Pos (0) /*!< PWM SBS2: SYNCBUSY Position */
-#define PWM_SBS2_SYNCBUSY_Msk (0x1ul << PWM_SBS2_SYNCBUSY_Pos) /*!< PWM SBS2: SYNCBUSY Mask */
-
-#define PWM_SBS3_SYNCBUSY_Pos (0) /*!< PWM SBS3: SYNCBUSY Position */
-#define PWM_SBS3_SYNCBUSY_Msk (0x1ul << PWM_SBS3_SYNCBUSY_Pos) /*!< PWM SBS3: SYNCBUSY Mask */
-
-#define PWM_SBS4_SYNCBUSY_Pos (0) /*!< PWM SBS4: SYNCBUSY Position */
-#define PWM_SBS4_SYNCBUSY_Msk (0x1ul << PWM_SBS4_SYNCBUSY_Pos) /*!< PWM SBS4: SYNCBUSY Mask */
-
-#define PWM_SBS5_SYNCBUSY_Pos (0) /*!< PWM SBS5: SYNCBUSY Position */
-#define PWM_SBS5_SYNCBUSY_Msk (0x1ul << PWM_SBS5_SYNCBUSY_Pos) /*!< PWM SBS5: SYNCBUSY Mask */
-
-/**@}*/ /* PWM_CONST */
-/**@}*/ /* end of PWM register group */
-
-
-/*---------------------- Quadrature Encoder Interface -------------------------*/
-/**
- @addtogroup QEI Quadrature Encoder Interface(QEI)
- Memory Mapped Structure for QEI Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CNT
- * ===================================================================================================
- * Offset: 0x00 QEI Pulse Counter
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |VAL |Quadrature Encoder Pulse Counter
- * | | |A 32-bit up/down counter.
- * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[27]) is one or decreased by one if the bit DIRF is zero.
- * | | |This register performs an integrator which count value is proportional to the encoder position.
- * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:.
- * | | |1. Software written if QEIEN (QEI_CTR[29]) = 0.
- * | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
- * | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTR[27])=1.
- */
- __IO uint32_t CNT;
-
- /**
- * CNTHOLD
- * ===================================================================================================
- * Offset: 0x04 QEI Pulse Counter Hold Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |VAL |Quadrature Encoder Pulse Counter Hold Register
- * | | |When bit HOLDCNT (QEIx_CTR[24]) goes from low to high, the QEI_CNT value is copied into QEI_CNTHOLD register.
- */
- __IO uint32_t CNTHOLD;
-
- /**
- * CNTLATCH
- * ===================================================================================================
- * Offset: 0x08 QEI Pulse Counter Index Latch Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |VAL |Quadrature Encoder Pulse Counter Index Latch
- * | | |When the IDXF (QEI_STATUS[18]) bit is set, the QEI_CNT value is copied into QEI_CNTLATCH register.
- */
- __IO uint32_t CNTLATCH;
-
- /**
- * CNTCMP
- * ===================================================================================================
- * Offset: 0x0C QEI Pulse Counter Compare Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |VAL |Quadrature Encoder Pulse Counter Compare
- * | | |if the QEI controller is in the compare-counting mode CMPENN (QEI_CTR[28]) =1, when the value of QEI_CNT matches the value of VAL the bit CMPF will be set.
- * | | |This register is software writable.
- */
- __IO uint32_t CNTCMP;
- uint32_t RESERVE0[1];
-
-
- /**
- * MAXCNT
- * ===================================================================================================
- * Offset: 0x14 QEI Pre-set Maximum Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |VAL |Quadrature Encoder Preset Maximum Count
- * | | |This register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode
- */
- __IO uint32_t CNTMAX;
-
- /**
- * CTR
- * ===================================================================================================
- * Offset: 0x18 QEI Controller Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |NFCLKSEL |Noise Filter Clock Pre-Divide Selection
- * | | |To determine the sampling frequency of the Noise Filter clock .
- * | | |00 = QEI_CLK.
- * | | |01 = QEI_CLK/2.
- * | | |10 = QEI_CLK/4.
- * | | |11 = QEI_CLK/16.
- * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Control
- * | | |0 = The noise filter of QEI controller Enabled.
- * | | |1 = The noise filter of QEI controller Disabled.
- * |[4] |CHAEN |QEA Input To QEI Controller Enable Control
- * | | |0 = QEA input to QEI Controller Disabled.
- * | | |1 = QEA input to QEI Controller Enabled.
- * |[5] |CHBEN |QEB Input To QEI Controller Enable Control
- * | | |0 = QEB input to QEI Controller Disabled.
- * | | |1 = QEB input to QEI Controller Enabled.
- * |[6] |IDXEN |IDX Input To QEI Controller Enable Control
- * | | |0 = IDX input to QEI Controller Disabled.
- * | | |1 = IDX input to QEI Controller Enabled.
- * |[8:9] |MODE |QEI Counting Mode Selection
- * | | |There are four quadrature encoder pulse counter operation modes.
- * | | |00 = X4 Free-counting Mode.
- * | | |01 = X2 Free-counting Mode.
- * | | |10 = X4 Compare-counting Mode.
- * | | |11 = X2 Compare-counting Mode.
- * |[12] |CHAINV |Inverse QEA Input Polarity
- * | | |0 = Not inverse QEA input polarity.
- * | | |1 = QEA input polarity is inversed to QEI controller.
- * |[13] |CHBINV |Inverse QEB Input Polarity
- * | | |0 = Not inverse QEB input polarity.
- * | | |1 = QEB input polarity is inversed to QEI controller.
- * |[14] |IDXINV |Inverse IDX Input Polarity
- * | | |0 = Not inverse IDX input polarity.
- * | | |1 = IDX input polarity is inversed to QEI controller.
- * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Control
- * | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
- * | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
- * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Control
- * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
- * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
- * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Control
- * | | |0 = CMPF can trigger QEI controller interrupt Disabled.
- * | | |1 = CMPF can trigger QEI controller interrupt Enabled.
- * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Control
- * | | |0 = The IDXF can trigger QEI interrupt Disabled.
- * | | |1 = The IDXF can trigger QEI interrupt Enabled.
- * |[20] |HOLDTMR0 |Hold QEI_CNT By Timer 0
- * | | |0 = TIF (TISR0[0]) has no effect on HOLDCNT.
- * | | |1 = A rising edge of bit TIF (TISR0[0]) in timer 0 sets HOLDCNT to 1.
- * |[21] |HOLDTMR1 |Hold QEI_CNT By Timer 1
- * | | |0 = TIF (TISR1[0]) has no effect on HOLDCNT.
- * | | |1 = A rising edge of bit TIF (TISR1[0]) in timer 1 sets HOLDCNT to 1.
- * |[22] |HOLDTMR2 |Hold QEI_CNT By Timer 2
- * | | |0 = TIF (TISR2[0]) has no effect on HOLDCNT.
- * | | |1 = A rising edge of bit TIF (TISR2[0]) in timer 2 sets HOLDCNT to 1.
- * |[23] |HOLDTMR3 |Hold QEI_CNT By Timer 3
- * | | |0 = TIF (TISR3[0]) has no effect on HOLDCNT.
- * | | |1 = A rising edge of bit TIF (TISR3[0]) in timer 3 sets HOLDCNT to 1.
- * |[24] |HOLDCNT |Hold QEI_CNT Control
- * | | |When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHOLD.
- * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TISTRx[0]).
- * | | |0 = No operation.
- * | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
- * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
- * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Control
- * | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
- * | | |0 = The index signal latch QEI counter function Disabled.
- * | | |1 = The index signal latch QEI counter function Enabled.
- * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Control
- * | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with QEI_MAXCNT content if the counter is in down-counting type (DIRF = 0).
- * | | |0 = Reload function Disabled.
- * | | |1 = QEI_CNT re-initialized by Index signal Enabled.
- * |[28] |CMPENN |The Compare Function Enable Control
- * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set.
- * | | |0 = Compare function Disabled.
- * | | |1 = Compare function Enabled.
- * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Control
- * | | |0 = QEI controller function Disabled.
- * | | |1 = QEI controller function Enabled.
- */
- __IO uint32_t CTR;
- uint32_t RESERVE1[4];
-
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x2C QEI Controller Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |IDXF |IDX Detected Flag
- * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
- * | | |0 = No rising edge detected on signal CHX.
- * | | |1 = A rising edge occurs on signal CHX.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[1] |CMPF |Compare-Match Flag
- * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.
- * | | |0 = QEI counter does not match with QEI_CNTCMP value.
- * | | |1 = QEI counter counts to the same as QEI_CNTCMP value.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[2] |OVUNF |QEI Counter Overflow Or Underflow Flag
- * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode.
- * | | |Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT.
- * | | |0 = No overflow or underflow occurs in QEI counter.
- * | | |1 = QEI counter occurs counting overflow or underflow.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[3] |DIRCHGF |Direction Change Flag
- * | | |Flag is set by hardware while QEI counter counting direction is changed.
- * | | |Software can clear this bit by writing 1 to it.
- * | | |0 = No change in QEI counter counting direction.
- * | | |1 = QEI counter counting direction is changed.
- * | | |Note: This bit is only cleared by writing 1 to it.
- * |[8] |DIRF |QEI Counter Counting Direction Indication
- * | | |0 = QEI Counter is in down-counting.
- * | | |1 = QEI Counter is in up-counting.
- * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
- */
- __IO uint32_t STATUS;
-
-} QEI_T;
-
-/**
- @addtogroup QEI_CONST QEI Bit Field Definition
- Constant Definitions for QEI Controller
-@{ */
-
-#define QEI_CNT_VAL_Pos (0) /*!< QEI CNT: VAL Position */
-#define QEI_CNT_VAL_Msk (0xfffffffful << QEI_CNT_VAL_Pos) /*!< QEI CNT: VAL Mask */
-
-#define QEI_CNTHOLD_VAL_Pos (0) /*!< QEI CNTHOLD: VAL Position */
-#define QEI_CNTHOLD_VAL_Msk (0xfffffffful << QEI_CNTHOLD_VAL_Pos) /*!< QEI CNTHOLD: VAL Mask */
-
-#define QEI_CNTLATCH_VAL_Pos (0) /*!< QEI CNTLATCH: VAL Position */
-#define QEI_CNTLATCH_VAL_Msk (0xfffffffful << QEI_CNTLATCH_VAL_Pos) /*!< QEI CNTLATCH: VAL Mask */
-
-#define QEI_CNTCMP_VAL_Pos (0) /*!< QEI CNTCMP: VAL Position */
-#define QEI_CNTCMP_VAL_Msk (0xfffffffful << QEI_CNTCMP_VAL_Pos) /*!< QEI CNTCMP: VAL Mask */
-
-#define QEI_CNTMAX_VAL_Pos (0) /*!< QEI CNTMAX: VAL Position */
-#define QEI_CNTMAX_VAL_Msk (0xfffffffful << QEI_CNTMAX_VAL_Pos) /*!< QEI CNTMAX: VAL Mask */
-
-#define QEI_CTR_NFCLKSEL_Pos (0) /*!< QEI CTR: NFCLKSEL Position */
-#define QEI_CTR_NFCLKSEL_Msk (0x3ul << QEI_CTR_NFCLKSEL_Pos) /*!< QEI CTR: NFCLKSEL Mask */
-
-#define QEI_CTR_NFDIS_Pos (3) /*!< QEI CTR: NFDIS Position */
-#define QEI_CTR_NFDIS_Msk (0x1ul << QEI_CTR_NFDIS_Pos) /*!< QEI CTR: NFDIS Mask */
-
-#define QEI_CTR_CHAEN_Pos (4) /*!< QEI CTR: CHAEN Position */
-#define QEI_CTR_CHAEN_Msk (0x1ul << QEI_CTR_CHAEN_Pos) /*!< QEI CTR: CHAEN Mask */
-
-#define QEI_CTR_CHBEN_Pos (5) /*!< QEI CTR: CHBEN Position */
-#define QEI_CTR_CHBEN_Msk (0x1ul << QEI_CTR_CHBEN_Pos) /*!< QEI CTR: CHBEN Mask */
-
-#define QEI_CTR_IDXEN_Pos (6) /*!< QEI CTR: IDXEN Position */
-#define QEI_CTR_IDXEN_Msk (0x1ul << QEI_CTR_IDXEN_Pos) /*!< QEI CTR: IDXEN Mask */
-
-#define QEI_CTR_MODE_Pos (8) /*!< QEI CTR: MODE Position */
-#define QEI_CTR_MODE_Msk (0x3ul << QEI_CTR_MODE_Pos) /*!< QEI CTR: MODE Mask */
-
-#define QEI_CTR_CHAINV_Pos (12) /*!< QEI CTR: CHAINV Position */
-#define QEI_CTR_CHAINV_Msk (0x1ul << QEI_CTR_CHAINV_Pos) /*!< QEI CTR: CHAINV Mask */
-
-#define QEI_CTR_CHBINV_Pos (13) /*!< QEI CTR: CHBINV Position */
-#define QEI_CTR_CHBINV_Msk (0x1ul << QEI_CTR_CHBINV_Pos) /*!< QEI CTR: CHBINV Mask */
-
-#define QEI_CTR_IDXINV_Pos (14) /*!< QEI CTR: IDXINV Position */
-#define QEI_CTR_IDXINV_Msk (0x1ul << QEI_CTR_IDXINV_Pos) /*!< QEI CTR: IDXINV Mask */
-
-#define QEI_CTR_OVUNIEN_Pos (16) /*!< QEI CTR: OVUNIEN Position */
-#define QEI_CTR_OVUNIEN_Msk (0x1ul << QEI_CTR_OVUNIEN_Pos) /*!< QEI CTR: OVUNIEN Mask */
-
-#define QEI_CTR_DIRIEN_Pos (17) /*!< QEI CTR: DIRIEN Position */
-#define QEI_CTR_DIRIEN_Msk (0x1ul << QEI_CTR_DIRIEN_Pos) /*!< QEI CTR: DIRIEN Mask */
-
-#define QEI_CTR_CMPIEN_Pos (18) /*!< QEI CTR: CMPIEN Position */
-#define QEI_CTR_CMPIEN_Msk (0x1ul << QEI_CTR_CMPIEN_Pos) /*!< QEI CTR: CMPIEN Mask */
-
-#define QEI_CTR_IDXIEN_Pos (19) /*!< QEI CTR: IDXIEN Position */
-#define QEI_CTR_IDXIEN_Msk (0x1ul << QEI_CTR_IDXIEN_Pos) /*!< QEI CTR: IDXIEN Mask */
-
-#define QEI_CTR_HOLDTMR0_Pos (20) /*!< QEI CTR: HOLDTMR0 Position */
-#define QEI_CTR_HOLDTMR0_Msk (0x1ul << QEI_CTR_HOLDTMR0_Pos) /*!< QEI CTR: HOLDTMR0 Mask */
-
-#define QEI_CTR_HOLDTMR1_Pos (21) /*!< QEI CTR: HOLDTMR1 Position */
-#define QEI_CTR_HOLDTMR1_Msk (0x1ul << QEI_CTR_HOLDTMR1_Pos) /*!< QEI CTR: HOLDTMR1 Mask */
-
-#define QEI_CTR_HOLDTMR2_Pos (22) /*!< QEI CTR: HOLDTMR2 Position */
-#define QEI_CTR_HOLDTMR2_Msk (0x1ul << QEI_CTR_HOLDTMR2_Pos) /*!< QEI CTR: HOLDTMR2 Mask */
-
-#define QEI_CTR_HOLDTMR3_Pos (23) /*!< QEI CTR: HOLDTMR3 Position */
-#define QEI_CTR_HOLDTMR3_Msk (0x1ul << QEI_CTR_HOLDTMR3_Pos) /*!< QEI CTR: HOLDTMR3 Mask */
-
-#define QEI_CTR_HOLDCNT_Pos (24) /*!< QEI CTR: HOLDCNT Position */
-#define QEI_CTR_HOLDCNT_Msk (0x1ul << QEI_CTR_HOLDCNT_Pos) /*!< QEI CTR: HOLDCNT Mask */
-
-#define QEI_CTR_IDXLATEN_Pos (25) /*!< QEI CTR: IDXLATEN Position */
-#define QEI_CTR_IDXLATEN_Msk (0x1ul << QEI_CTR_IDXLATEN_Pos) /*!< QEI CTR: IDXLATEN Mask */
-
-#define QEI_CTR_IDXRLDEN_Pos (27) /*!< QEI CTR: IDXRLDEN Position */
-#define QEI_CTR_IDXRLDEN_Msk (0x1ul << QEI_CTR_IDXRLDEN_Pos) /*!< QEI CTR: IDXRLDEN Mask */
-
-#define QEI_CTR_CMPENN_Pos (28) /*!< QEI CTR: CMPENN Position */
-#define QEI_CTR_CMPENN_Msk (0x1ul << QEI_CTR_CMPENN_Pos) /*!< QEI CTR: CMPENN Mask */
-
-#define QEI_CTR_QEIEN_Pos (29) /*!< QEI CTR: QEIEN Position */
-#define QEI_CTR_QEIEN_Msk (0x1ul << QEI_CTR_QEIEN_Pos) /*!< QEI CTR: QEIEN Mask */
-
-#define QEI_STATUS_IDXF_Pos (0) /*!< QEI STATUS: IDXF Position */
-#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI STATUS: IDXF Mask */
-
-#define QEI_STATUS_CMPF_Pos (1) /*!< QEI STATUS: CMPF Position */
-#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI STATUS: CMPF Mask */
-
-#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI STATUS: OVUNF Position */
-#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI STATUS: OVUNF Mask */
-
-#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI STATUS: DIRCHGF Position */
-#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI STATUS: DIRCHGF Mask */
-
-#define QEI_STATUS_DIRF_Pos (8) /*!< QEI STATUS: DIRF Position */
-#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI STATUS: DIRF Mask */
-
-/**@}*/ /* QEI_CONST */
-/**@}*/ /* end of QEI register group */
-
-
-/*---------------------- Real Time Clock Controller -------------------------*/
-/**
- @addtogroup RTC Real Time Clock Controller(RTC)
- Memory Mapped Structure for RTC Controller
-@{ */
-
-typedef struct {
-
- /**
- * INIT
- * ===================================================================================================
- * Offset: 0x00 RTC Initiation Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |INIT_Active|RTC Active Status (Read Only)
- * | | |0 = RTC is at reset state.
- * | | |1 = RTC is at normal active state.
- * |[1:31] |INIT |RTC Initiation
- * | | |When RTC block is powered on, RTC is at reset state.
- * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
- * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
- * | | |The INIT is a write-only field and read value will be always "0".
- */
- __IO uint32_t INIT;
-
- /**
- * RWEN
- * ===================================================================================================
- * Offset: 0x04 RTC Access Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |RWEN |RTC Register Access Enable Password (Write Only)
- * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
- * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
- * | | |0 = RTC register read/write Disabled.
- * | | |1 = RTC register read/write Enabled.
- * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
- */
- __O uint32_t RWEN;
-
- /**
- * FREQADJ
- * ===================================================================================================
- * Offset: 0x08 RTC Frequency Compensation Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |FRACTION |Fraction Part
- * | | |Formula = (fraction part of detected value) x 60.
- * | | |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
- * |[8:11] |INTEGER |Integer Part
- */
- __IO uint32_t FREQADJ;
-
- /**
- * TIME
- * ===================================================================================================
- * Offset: 0x0C Time Loading Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |SEC |1-Sec Time Digit (0~9)
- * |[4:6] |TENSEC |10-Sec Time Digit (0~5)
- * |[8:11] |MIN |1-Min Time Digit (0~9)
- * |[12:14] |TENMIN |10-Min Time Digit (0~5)
- * |[16:19] |HR |1-Hour Time Digit (0~9)
- * |[20:21] |TENHR |10-Hour Time Digit (0~2)
- */
- __IO uint32_t TIME;
-
- /**
- * CAL
- * ===================================================================================================
- * Offset: 0x10 Calendar Loading Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |DAY |1-Day Calendar Digit (0~9)
- * |[4:5] |TENDAY |10-Day Calendar Digit (0~3)
- * |[8:11] |MON |1-Month Calendar Digit (0~9)
- * |[12] |TENMON |10-Month Calendar Digit (0~1)
- * |[16:19] |YEAR |1-Year Calendar Digit (0~9)
- * |[20:23] |TENYEAR |10-Year Calendar Digit (0~9)
- */
- __IO uint32_t CAL;
-
- /**
- * CLKFMT
- * ===================================================================================================
- * Offset: 0x14 Time Scale Selection Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |24HEN |24-Hour / 12-Hour Time Scale Selection
- * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
- * | | |0 = 12-hour time scale with AM and PM indication selected.
- * | | |1 = 24-hour time scale selected.
- */
- __IO uint32_t CLKFMT;
-
- /**
- * WEEKDAY
- * ===================================================================================================
- * Offset: 0x18 Day of the Week Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |WEEKDAY |Day Of The Week Bits
- * | | |000 = Sunday.
- * | | |001 = Monday.
- * | | |010 = Tuesday.
- * | | |011 = Wednesday.
- * | | |100 = Thursday.
- * | | |101 = Friday.
- * | | |110 = Saturday.
- * | | |111 = Reserved
- */
- __IO uint32_t WEEKDAY;
-
- /**
- * TALM
- * ===================================================================================================
- * Offset: 0x1C Time Alarm Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
- * |[4:6] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
- * |[8:11] |MIN |1-Min Time Digit of Alarm Setting (0~9)
- * |[12:14] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
- * |[16:19] |HR |1-Hour Time Digit of Alarm Setting (0~9)
- * |[20:21] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
- */
- __IO uint32_t TALM;
-
- /**
- * CALM
- * ===================================================================================================
- * Offset: 0x20 Calendar Alarm Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
- * |[4:5] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
- * |[8:11] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
- * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
- * |[16:19] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
- * |[20:23] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
- */
- __IO uint32_t CALM;
-
- /**
- * LEAPYEAR
- * ===================================================================================================
- * Offset: 0x24 Leap Year Indication Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |LEAPYEAR |Leap Year Indicator (Read Only)
- * | | |0 = This year is not a leap year.
- * | | |1 = This year is leap year.
- */
- __I uint32_t LEAPYEAR;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x28 RTC Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ALMIEN |Alarm Interrupt Enable Control
- * | | |0 = RTC Alarm Interrupt Disabled.
- * | | |1 = RTC Alarm Interrupt Enabled.
- * |[1] |TICKIEN |Time Tick Interrupt Enable Control
- * | | |0 = RTC Time Tick Interrupt Disabled.
- * | | |1 = RTC Time Tick Interrupt Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x2C RTC Interrupt Indicator Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ALMIF |RTC Alarm Interrupt Flag
- * | | |When RTC real time counters RTC_TIME and RTC_CAL reach the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled (ALMIEN (RTC_INTEN(0)) is set to 1.
- * | | |Chip will also be waken up if RTC Alarm Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
- * | | |Note: This bit can be cleared by writing 1 to it.
- * |[1] |TICKIF |RTC Time Tick Interrupt Flag
- * | | |When RTC Time Tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled (TICKIEN (RTC_INTEN[1])) is set to 1.
- * | | |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
- * | | |Note: This bit can be cleared by writing 1 to it.
- */
- __IO uint32_t INTSTS;
-
- /**
- * TICK
- * ===================================================================================================
- * Offset: 0x30 RTC Time Tick Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |TICKSEL |Time Tick Bits
- * | | |The RTC time tick period for Periodic Time Tick Interrupt request.
- * | | |000 = Time tick is 1 second.
- * | | |001 = Time tick is 1/2 second.
- * | | |010 = Time tick is 1/4 second.
- * | | |011 = Time tick is 1/8 second.
- * | | |100 = Time tick is 1/16 second.
- * | | |101 = Time tick is 1/32 second.
- * | | |110 = Time tick is 1/64 second.
- * | | |111 = Time tick is 1/128 second.
- * | | |Note: These bits can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
- */
- __IO uint32_t TICK;
- uint32_t RESERVE0[2];
-
-
- /**
- * SPRCTL
- * ===================================================================================================
- * Offset: 0x3C RTC Spare Functional Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[2] |SPRRWEN |SPR Register Enable Control
- * | | |This bit controls the spare register to be enabled or not.
- * | | |0 = Spare register Disabled and RTC_SPR0 ~ RTC_SPR23 cannot be accessed.
- * | | |1 = Spare register Enabled and RTC_SPR0 ~ RTC_SPR23 can be accessed.
- * |[7] |SPRRWRDY |SPR Register Ready
- * | | |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are ready to be accessed.
- * | | |After CPU writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23, polling this bit to check if these registers are updated done is necessary.
- * | | |This bit is read only and any write to it won't take any effect.
- * | | |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 updating is in progress.
- * | | |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are updated done and ready to be accessed.
- */
- __IO uint32_t SPRCTL;
-
- /**
- * SPRx
- * ===================================================================================================
- * Offset: 0x40 RTC Spare Register 0 ~ 23
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SPARE |SPARE Bits
- * | | |This field is used to store back-up information defined by software.
- * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
- * | | |Before storing back-up information in to SPARE register, software should write 0xA965 to RTC_RWEN to make sure register read/write enabled.
- */
- __IO uint32_t SPR[24];
- uint32_t RESERVE1[28];
-
-
- /**
- * TAMPCTL
- * ===================================================================================================
- * Offset: 0x110 Tamper Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TIEN |Tamper Interrupt Enable Control
- * | | |0 = Tamper interrupt Disabled.
- * | | |1 = Tamper interrupt Enabled.
- * |[1] |DESTROYEN |Destroy Spare Register Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[2] |TAMPEN0 |Tamper0 Detect Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[3] |TAMPEN1 |Tamper1 Detect Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[4] |TAMPDBEN0 |Tamper0 De-Bounce Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[5] |TAMPDBEN1 |Tamper1 De-Bounce Enable Control
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[6] |TAMPLV0 |Tamper0 Level
- * | | |0 = Low.
- * | | |1 = High.
- * |[7] |TAMPLV1 |Tamper1 Level
- * | | |0 = Low.
- * | | |1 = High.
- */
- __IO uint32_t TAMPCTL;
-
- /**
- * TAMPSTS
- * ===================================================================================================
- * Offset: 0x114 Tamper Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TAMPSTS0 |Tamper0 Sense Flag
- * | | |0 = No invasion.
- * | | |1 = Tamper0 detect invasion.
- * | | |Note: Write 1 to clear it
- * |[1] |TAMPSTS1 |Tamper1 Sense Flag
- * | | |0 = No invasion.
- * | | |1 = Tamper1 detect invasion.
- * | | |Note: Write 1 to clear it
- */
- __IO uint32_t TAMPSTS;
- uint32_t RESERVE2[3];
-
-
- /**
- * TAMP0PCTL
- * ===================================================================================================
- * Offset: 0x124 TAMPER0 Pin I/O Mode Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OUTLV |Output Level
- * | | |0 = Low.
- * | | |1 = High.
- * |[1] |OUTEN |Output Enable Control
- * | | |0 = Output Enabled.
- * | | |1 = Output Disabled.
- * |[2] |TRIEN |Tri-State
- * | | |0 = Tri-state Disabled.
- * | | |1 = Tri-state Enabled.
- * |[3] |TYPE |Type
- * | | |0 = Input Schmitt Trigger function Disabled.
- * | | |1 = Input Schmitt Trigger function Enabled.
- * |[4] |DINOFF |Off Digital
- * | | |0 = Off digital Disabled.
- * | | |1 = Off digital Enabled.
- */
- __IO uint32_t TAMP0PCTL;
-
- /**
- * TAMP1PCTL
- * ===================================================================================================
- * Offset: 0x128 TAMPER1 Pin I/O Mode Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OUTLV |Output Level
- * | | |0 = Low.
- * | | |1 = High.
- * |[1] |OUTEN |Output Enable Control
- * | | |0 = Output Enabled.
- * | | |1 = Output Disabled.
- * |[2] |TRIEN |Tri-State
- * | | |0 = Tri-state Disabled.
- * | | |1 = Tri-state Enabled.
- * |[3] |TYPE |Type
- * | | |0 = Input Schmitt Trigger function Disabled.
- * | | |1 = Input Schmitt Trigger function Enabled.
- * |[4] |DINOFF |Off Digital
- * | | |0 = Off digital Disabled.
- * | | |1 = Off digital Enabled.
- */
- __IO uint32_t TAMP1PCTL;
-
- /**
- * LXTIPCTL
- * ===================================================================================================
- * Offset: 0x12C 32K Input Pin I/O Mode Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OUTLV |Output Level
- * | | |0 = Low.
- * | | |1 = High.
- * |[1] |OUTEN |Output Enable Control
- * | | |0 = Output Enabled.
- * | | |1 = Output Disabled.
- * |[2] |TRIEN |Tri-State
- * | | |0 = Tri-state Disabled.
- * | | |1 = Tri-state Enabled.
- * |[3] |TYPE |Type
- * | | |0 = Input Schmitt Trigger function Disabled.
- * | | |1 = Input Schmitt Trigger function Enabled.
- * |[4] |DINOFF |Off Digital
- * | | |0 = Off digital Disabled.
- * | | |1 = Off digital Enabled.
- */
- __IO uint32_t LXTIPCTL;
-
- /**
- * LXTOPCTL
- * ===================================================================================================
- * Offset: 0x130 32K Output Pin I/O Mode Control
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |OUTLV |Output Level
- * | | |0 = Low.
- * | | |1 = High.
- * |[1] |OUTEN |Output Enable Control
- * | | |0 = Output Enabled.
- * | | |1 = Output Disabled.
- * |[2] |TRIEN |Tri-State
- * | | |0 = Tri-state Disabled.
- * | | |1 = Tri-state Enabled.
- * |[3] |TYPE |Type
- * | | |0 = Input Schmitt Trigger function Disabled.
- * | | |1 = Input Schmitt Trigger function Enabled.
- * |[4] |DINOFF |Off Digital
- * | | |0 = Off digital Disabled.
- * | | |1 = Off digital Enabled.
- */
- __IO uint32_t LXTOPCTL;
- uint32_t RESERVE3[3];
-
-
- /**
- * TAMSK
- * ===================================================================================================
- * Offset: 0x140 Time Alarm MASK Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
- * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
- * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
- * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
- * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
- * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
- */
- __IO uint32_t TAMSK;
-
- /**
- * CAMSK
- * ===================================================================================================
- * Offset: 0x144 Calendar Alarm MASK Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
- * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
- * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
- * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
- * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
- * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
- */
- __IO uint32_t CAMSK;
-
-} RTC_T;
-
-/**
- @addtogroup RTC_CONST RTC Bit Field Definition
- Constant Definitions for RTC Controller
-@{ */
-
-#define RTC_INIT_INIT_Active_Pos (0) /*!< RTC INIT: INIT_Active Position */
-#define RTC_INIT_INIT_Active_Msk (0x1ul << RTC_INIT_INIT_Active_Pos) /*!< RTC INIT: INIT_Active Mask */
-
-#define RTC_INIT_INIT_Pos (1) /*!< RTC INIT: INIT Position */
-#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC INIT: INIT Mask */
-
-#define RTC_RWEN_RWEN_Pos (0) /*!< RTC RWEN: RWEN Position */
-#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC RWEN: RWEN Mask */
-
-#define RTC_RWEN_RWENF_Pos (16) /*!< RTC RWEN: RWENF Position */
-#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC RWEN: RWENF Mask */
-
-#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC FREQADJ: FRACTION Position */
-#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC FREQADJ: FRACTION Mask */
-
-#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC FREQADJ: INTEGER Position */
-#define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC FREQADJ: INTEGER Mask */
-
-#define RTC_TIME_SEC_Pos (0) /*!< RTC TIME: SEC Position */
-#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC TIME: SEC Mask */
-
-#define RTC_TIME_TENSEC_Pos (4) /*!< RTC TIME: TENSEC Position */
-#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC TIME: TENSEC Mask */
-
-#define RTC_TIME_MIN_Pos (8) /*!< RTC TIME: MIN Position */
-#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC TIME: MIN Mask */
-
-#define RTC_TIME_TENMIN_Pos (12) /*!< RTC TIME: TENMIN Position */
-#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC TIME: TENMIN Mask */
-
-#define RTC_TIME_HR_Pos (16) /*!< RTC TIME: HR Position */
-#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC TIME: HR Mask */
-
-#define RTC_TIME_TENHR_Pos (20) /*!< RTC TIME: TENHR Position */
-#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC TIME: TENHR Mask */
-
-#define RTC_CAL_DAY_Pos (0) /*!< RTC CAL: DAY Position */
-#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC CAL: DAY Mask */
-
-#define RTC_CAL_TENDAY_Pos (4) /*!< RTC CAL: TENDAY Position */
-#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC CAL: TENDAY Mask */
-
-#define RTC_CAL_MON_Pos (8) /*!< RTC CAL: MON Position */
-#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC CAL: MON Mask */
-
-#define RTC_CAL_TENMON_Pos (12) /*!< RTC CAL: TENMON Position */
-#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC CAL: TENMON Mask */
-
-#define RTC_CAL_YEAR_Pos (16) /*!< RTC CAL: YEAR Position */
-#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC CAL: YEAR Mask */
-
-#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC CAL: TENYEAR Position */
-#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC CAL: TENYEAR Mask */
-
-#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC CLKFMT: 24HEN Position */
-#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC CLKFMT: 24HEN Mask */
-
-#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC WEEKDAY: WEEKDAY Position */
-#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC WEEKDAY: WEEKDAY Mask */
-
-#define RTC_TALM_SEC_Pos (0) /*!< RTC TALM: SEC Position */
-#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC TALM: SEC Mask */
-
-#define RTC_TALM_TENSEC_Pos (4) /*!< RTC TALM: TENSEC Position */
-#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC TALM: TENSEC Mask */
-
-#define RTC_TALM_MIN_Pos (8) /*!< RTC TALM: MIN Position */
-#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC TALM: MIN Mask */
-
-#define RTC_TALM_TENMIN_Pos (12) /*!< RTC TALM: TENMIN Position */
-#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC TALM: TENMIN Mask */
-
-#define RTC_TALM_HR_Pos (16) /*!< RTC TALM: HR Position */
-#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC TALM: HR Mask */
-
-#define RTC_TALM_TENHR_Pos (20) /*!< RTC TALM: TENHR Position */
-#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC TALM: TENHR Mask */
-
-#define RTC_CALM_DAY_Pos (0) /*!< RTC CALM: DAY Position */
-#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC CALM: DAY Mask */
-
-#define RTC_CALM_TENDAY_Pos (4) /*!< RTC CALM: TENDAY Position */
-#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC CALM: TENDAY Mask */
-
-#define RTC_CALM_MON_Pos (8) /*!< RTC CALM: MON Position */
-#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC CALM: MON Mask */
-
-#define RTC_CALM_TENMON_Pos (12) /*!< RTC CALM: TENMON Position */
-#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC CALM: TENMON Mask */
-
-#define RTC_CALM_YEAR_Pos (16) /*!< RTC CALM: YEAR Position */
-#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC CALM: YEAR Mask */
-
-#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC CALM: TENYEAR Position */
-#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC CALM: TENYEAR Mask */
-
-#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC LEAPYEAR: LEAPYEAR Position */
-#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC LEAPYEAR: LEAPYEAR Mask */
-
-#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC INTEN: ALMIEN Position */
-#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC INTEN: ALMIEN Mask */
-
-#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC INTEN: TICKIEN Position */
-#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC INTEN: TICKIEN Mask */
-
-#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC INTSTS: ALMIF Position */
-#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC INTSTS: ALMIF Mask */
-
-#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC INTSTS: TICKIF Position */
-#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC INTSTS: TICKIF Mask */
-
-#define RTC_TICK_TICKSEL_Pos (0) /*!< RTC TICK: TICKSEL Position */
-#define RTC_TICK_TICKSEL_Msk (0x7ul << RTC_TICK_TICKSEL_Pos) /*!< RTC TICK: TICKSEL Mask */
-
-#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC SPRCTL: SPRRWEN Position */
-#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC SPRCTL: SPRRWEN Mask */
-
-#define RTC_SPRCTL_SPRRWRDY_Pos (7) /*!< RTC SPRCTL: SPRRWRDY Position */
-#define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /*!< RTC SPRCTL: SPRRWRDY Mask */
-
-#define RTC_TAMPCTL_TIEN_Pos (0) /*!< RTC TAMPCTL: TIEN Position */
-#define RTC_TAMPCTL_TIEN_Msk (0x1ul << RTC_TAMPCTL_TIEN_Pos) /*!< RTC TAMPCTL: TIEN Mask */
-
-#define RTC_TAMPCTL_DESTROYEN_Pos (1) /*!< RTC TAMPCTL: DESTROYEN Position */
-#define RTC_TAMPCTL_DESTROYEN_Msk (0x1ul << RTC_TAMPCTL_DESTROYEN_Pos) /*!< RTC TAMPCTL: DESTROYEN Mask */
-
-#define RTC_TAMPCTL_TAMPEN0_Pos (2) /*!< RTC TAMPCTL: TAMPEN0 Position */
-#define RTC_TAMPCTL_TAMPEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPEN0_Pos) /*!< RTC TAMPCTL: TAMPEN0 Mask */
-
-#define RTC_TAMPCTL_TAMPEN1_Pos (3) /*!< RTC TAMPCTL: TAMPEN1 Position */
-#define RTC_TAMPCTL_TAMPEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPEN1_Pos) /*!< RTC TAMPCTL: TAMPEN1 Mask */
-
-#define RTC_TAMPCTL_TAMPDBEN0_Pos (4) /*!< RTC TAMPCTL: TAMPDBEN0 Position */
-#define RTC_TAMPCTL_TAMPDBEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN0_Pos) /*!< RTC TAMPCTL: TAMPDBEN0 Mask */
-
-#define RTC_TAMPCTL_TAMPDBEN1_Pos (5) /*!< RTC TAMPCTL: TAMPDBEN1 Position */
-#define RTC_TAMPCTL_TAMPDBEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN1_Pos) /*!< RTC TAMPCTL: TAMPDBEN1 Mask */
-
-#define RTC_TAMPCTL_TAMPLV0_Pos (6) /*!< RTC TAMPCTL: TAMPLV0 Position */
-#define RTC_TAMPCTL_TAMPLV0_Msk (0x1ul << RTC_TAMPCTL_TAMPLV0_Pos) /*!< RTC TAMPCTL: TAMPLV0 Mask */
-
-#define RTC_TAMPCTL_TAMPLV1_Pos (7) /*!< RTC TAMPCTL: TAMPLV1 Position */
-#define RTC_TAMPCTL_TAMPLV1_Msk (0x1ul << RTC_TAMPCTL_TAMPLV1_Pos) /*!< RTC TAMPCTL: TAMPLV1 Mask */
-
-#define RTC_TAMPSTS_TAMPSTS0_Pos (0) /*!< RTC TAMPSTS: TAMPSTS0 Position */
-#define RTC_TAMPSTS_TAMPSTS0_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS0_Pos) /*!< RTC TAMPSTS: TAMPSTS0 Mask */
-
-#define RTC_TAMPSTS_TAMPSTS1_Pos (1) /*!< RTC TAMPSTS: TAMPSTS1 Position */
-#define RTC_TAMPSTS_TAMPSTS1_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS1_Pos) /*!< RTC TAMPSTS: TAMPSTS1 Mask */
-
-#define RTC_TAMP0PCTL_OUTLV_Pos (0) /*!< RTC TAMP0PCTL: OUTLV Position */
-#define RTC_TAMP0PCTL_OUTLV_Msk (0x1ul << RTC_TAMP0PCTL_OUTLV_Pos) /*!< RTC TAMP0PCTL: OUTLV Mask */
-
-#define RTC_TAMP0PCTL_OUTEN_Pos (1) /*!< RTC TAMP0PCTL: OUTEN Position */
-#define RTC_TAMP0PCTL_OUTEN_Msk (0x1ul << RTC_TAMP0PCTL_OUTEN_Pos) /*!< RTC TAMP0PCTL: OUTEN Mask */
-
-#define RTC_TAMP0PCTL_TRIEN_Pos (2) /*!< RTC TAMP0PCTL: TRIEN Position */
-#define RTC_TAMP0PCTL_TRIEN_Msk (0x1ul << RTC_TAMP0PCTL_TRIEN_Pos) /*!< RTC TAMP0PCTL: TRIEN Mask */
-
-#define RTC_TAMP0PCTL_TYPE_Pos (3) /*!< RTC TAMP0PCTL: TYPE Position */
-#define RTC_TAMP0PCTL_TYPE_Msk (0x1ul << RTC_TAMP0PCTL_TYPE_Pos) /*!< RTC TAMP0PCTL: TYPE Mask */
-
-#define RTC_TAMP0PCTL_DINOFF_Pos (4) /*!< RTC TAMP0PCTL: DINOFF Position */
-#define RTC_TAMP0PCTL_DINOFF_Msk (0x1ul << RTC_TAMP0PCTL_DINOFF_Pos) /*!< RTC TAMP0PCTL: DINOFF Mask */
-
-#define RTC_TAMP1PCTL_OUTLV_Pos (0) /*!< RTC TAMP1PCTL: OUTLV Position */
-#define RTC_TAMP1PCTL_OUTLV_Msk (0x1ul << RTC_TAMP1PCTL_OUTLV_Pos) /*!< RTC TAMP1PCTL: OUTLV Mask */
-
-#define RTC_TAMP1PCTL_OUTEN_Pos (1) /*!< RTC TAMP1PCTL: OUTEN Position */
-#define RTC_TAMP1PCTL_OUTEN_Msk (0x1ul << RTC_TAMP1PCTL_OUTEN_Pos) /*!< RTC TAMP1PCTL: OUTEN Mask */
-
-#define RTC_TAMP1PCTL_TRIEN_Pos (2) /*!< RTC TAMP1PCTL: TRIEN Position */
-#define RTC_TAMP1PCTL_TRIEN_Msk (0x1ul << RTC_TAMP1PCTL_TRIEN_Pos) /*!< RTC TAMP1PCTL: TRIEN Mask */
-
-#define RTC_TAMP1PCTL_TYPE_Pos (3) /*!< RTC TAMP1PCTL: TYPE Position */
-#define RTC_TAMP1PCTL_TYPE_Msk (0x1ul << RTC_TAMP1PCTL_TYPE_Pos) /*!< RTC TAMP1PCTL: TYPE Mask */
-
-#define RTC_TAMP1PCTL_DINOFF_Pos (4) /*!< RTC TAMP1PCTL: DINOFF Position */
-#define RTC_TAMP1PCTL_DINOFF_Msk (0x1ul << RTC_TAMP1PCTL_DINOFF_Pos) /*!< RTC TAMP1PCTL: DINOFF Mask */
-
-#define RTC_LXTIPCTL_OUTLV_Pos (0) /*!< RTC LXTIPCTL: OUTLV Position */
-#define RTC_LXTIPCTL_OUTLV_Msk (0x1ul << RTC_LXTIPCTL_OUTLV_Pos) /*!< RTC LXTIPCTL: OUTLV Mask */
-
-#define RTC_LXTIPCTL_OUTEN_Pos (1) /*!< RTC LXTIPCTL: OUTEN Position */
-#define RTC_LXTIPCTL_OUTEN_Msk (0x1ul << RTC_LXTIPCTL_OUTEN_Pos) /*!< RTC LXTIPCTL: OUTEN Mask */
-
-#define RTC_LXTIPCTL_TRIEN_Pos (2) /*!< RTC LXTIPCTL: TRIEN Position */
-#define RTC_LXTIPCTL_TRIEN_Msk (0x1ul << RTC_LXTIPCTL_TRIEN_Pos) /*!< RTC LXTIPCTL: TRIEN Mask */
-
-#define RTC_LXTIPCTL_TYPE_Pos (3) /*!< RTC LXTIPCTL: TYPE Position */
-#define RTC_LXTIPCTL_TYPE_Msk (0x1ul << RTC_LXTIPCTL_TYPE_Pos) /*!< RTC LXTIPCTL: TYPE Mask */
-
-#define RTC_LXTIPCTL_DINOFF_Pos (4) /*!< RTC LXTIPCTL: DINOFF Position */
-#define RTC_LXTIPCTL_DINOFF_Msk (0x1ul << RTC_LXTIPCTL_DINOFF_Pos) /*!< RTC LXTIPCTL: DINOFF Mask */
-
-#define RTC_LXTOPCTL_OUTLV_Pos (0) /*!< RTC LXTOPCTL: OUTLV Position */
-#define RTC_LXTOPCTL_OUTLV_Msk (0x1ul << RTC_LXTOPCTL_OUTLV_Pos) /*!< RTC LXTOPCTL: OUTLV Mask */
-
-#define RTC_LXTOPCTL_OUTEN_Pos (1) /*!< RTC LXTOPCTL: OUTEN Position */
-#define RTC_LXTOPCTL_OUTEN_Msk (0x1ul << RTC_LXTOPCTL_OUTEN_Pos) /*!< RTC LXTOPCTL: OUTEN Mask */
-
-#define RTC_LXTOPCTL_TRIEN_Pos (2) /*!< RTC LXTOPCTL: TRIEN Position */
-#define RTC_LXTOPCTL_TRIEN_Msk (0x1ul << RTC_LXTOPCTL_TRIEN_Pos) /*!< RTC LXTOPCTL: TRIEN Mask */
-
-#define RTC_LXTOPCTL_TYPE_Pos (3) /*!< RTC LXTOPCTL: TYPE Position */
-#define RTC_LXTOPCTL_TYPE_Msk (0x1ul << RTC_LXTOPCTL_TYPE_Pos) /*!< RTC LXTOPCTL: TYPE Mask */
-
-#define RTC_LXTOPCTL_DINOFF_Pos (4) /*!< RTC LXTOPCTL: DINOFF Position */
-#define RTC_LXTOPCTL_DINOFF_Msk (0x1ul << RTC_LXTOPCTL_DINOFF_Pos) /*!< RTC LXTOPCTL: DINOFF Mask */
-
-#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC TAMSK: MSEC Position */
-#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC TAMSK: MSEC Mask */
-
-#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC TAMSK: MTENSEC Position */
-#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC TAMSK: MTENSEC Mask */
-
-#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC TAMSK: MMIN Position */
-#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC TAMSK: MMIN Mask */
-
-#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC TAMSK: MTENMIN Position */
-#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC TAMSK: MTENMIN Mask */
-
-#define RTC_TAMSK_MHR_Pos (4) /*!< RTC TAMSK: MHR Position */
-#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC TAMSK: MHR Mask */
-
-#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC TAMSK: MTENHR Position */
-#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC TAMSK: MTENHR Mask */
-
-#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC CAMSK: MDAY Position */
-#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC CAMSK: MDAY Mask */
-
-#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC CAMSK: MTENDAY Position */
-#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC CAMSK: MTENDAY Mask */
-
-#define RTC_CAMSK_MMON_Pos (2) /*!< RTC CAMSK: MMON Position */
-#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC CAMSK: MMON Mask */
-
-#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC CAMSK: MTENMON Position */
-#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC CAMSK: MTENMON Mask */
-
-#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC CAMSK: MYEAR Position */
-#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC CAMSK: MYEAR Mask */
-
-#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC CAMSK: MTENYEAR Position */
-#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC CAMSK: MTENYEAR Mask */
-
-/**@}*/ /* RTC_CONST */
-/**@}*/ /* end of RTC register group */
-
-
-/*---------------------- Smart Card Host Interface Controller -------------------------*/
-/**
- @addtogroup SC Smart Card Host Interface Controller(SC)
- Memory Mapped Structure for SC Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * DAT
- * ===================================================================================================
- * Offset: 0x00 SC Receive and Transmit Buffer Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DAT |Receiving/ Transmit Buffer
- * | | |Write Operation:
- * | | |By writing data to DAT, the SC will send out an 8-bit data.
- * | | |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
- * | | |Read Operation:
- * | | |By reading DAT, the SC will return an 8-bit received data.
- */
- __IO uint32_t DAT;
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x04 SC Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SCEN |SC Engine Enable Control
- * | | |Set this bit to 1 to enable SC operation.
- * | | |If this bit is cleared, SC will force all transition to IDLE state.
- * |[1] |RXOFF |RX Transition Disable Control
- * | | |0 = The receiver Enabled.
- * | | |1 = The receiver Disabled.
- * | | |Note: If AUTOCEN is enabled, this fields must be ignored.
- * |[2] |TXOFF |TX Transition Disable Control
- * | | |0 = The transceiver Enabled.
- * | | |1 = The transceiver Disabled.
- * |[3] |AUTOCEN |Auto Convention Enable Control
- * | | |0 = Auto-convention Disabled.
- * | | |1 = Auto-convention Enabled.
- * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
- * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 3B or 3F.
- * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
- * | | |If the first data is not 3B or 3F, hardware will generate an interrupt INT_ACON_ERR (if ACON_ERR IE (SC_INTEN[10]) = 1 to CPU.
- * |[4:5] |CONSEL |Convention Selection
- * | | |00 = Direct convention.
- * | | |01 = Reserved.
- * | | |10 = Reserved.
- * | | |11 = Inverse convention.
- * | | |Note: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
- * |[6:7] |RXTRGLV |Rx Buffer Trigger Level
- * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).
- * | | |00 = INTR_RDA Trigger Level with 01 Bytes.
- * | | |01 = INTR_RDA Trigger Level with 02 Bytes.
- * | | |10 = INTR_RDA Trigger Level with 03 Bytees.
- * | | |11 = Reserved.
- * |[8:12] |BGT |Block Guard Time (BGT)
- * | | |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
- * | | |This field indicates the counter for the bit length of block guard time.
- * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
- * | | |In RX mode, software can enable SC_ALTCTL [RXBGTEN] to detect the first coming character timing.
- * | | |If the incoming data timing less than BGT, an interrupt will be generated.
- * | | |Note: The real block guard time is BGT + 1.
- * |[13:14] |TMRSEL |Timer Selection
- * | | |00 = All internal timer function Disabled.
- * | | |01 = Internal 24 bit timer Enabled.
- * | | |Software can configure it by setting SC_TMRCTL0 [23:0].
- * | | |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
- * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled.
- * | | |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
- * | | |SC_TMRCTL2 will be ignored in this mode.
- * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled.
- * | | |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
- * |[15] |NSB |Stop Bit Length
- * | | |This field indicates the length of stop bit.
- * | | |0 = The stop bit length is 2 ETU.
- * | | |1= The stop bit length is 1 ETU.
- * | | |Note: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
- * |[16:18] |RXRTY |RX Error Retry Count Number
- * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
- * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
- * | | |Note2: This field cannot be changed when RXRTYEN enabled.
- * | | |The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
- * |[19] |RXRTYEN |RX Error Retry Enable Control
- * | | |This bit enables receiver retry function when parity error has occurred.
- * | | |1 = RX error retry function Enabled.
- * | | |0 = RX error retry function Disabled.
- * | | |Note: Software must fill in the RXRTY value before enabling this bit.
- * |[20:22] |TXRTY |TX Error Retry Count Number
- * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
- * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
- * | | |Note2: This field cannot be changed when TXRTYEN enabled.
- * | | |The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
- * |[23] |TXRTYEN |TX Error Retry Enable Control
- * | | |This bit enables transmitter retry function when parity error has occurred.
- * | | |0 = TX error retry function Disabled.
- * | | |1 = TX error retry function Enabled.
- * |[24:25] |CDDBSEL |Card Detect De-Bounce Selection
- * | | |This field indicates the card detect de-bounce selection.
- * | | |00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks.
- * | | |01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks.
- * | | |10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks.
- * | | |11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks.
- * |[26] |CDLV |Card Detect Level
- * | | |0 = When hardware detects the card detect pin from high to low, it indicates a card is detected.
- * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
- * | | |Note: Software must select card detect level before Smart Card engine enabled.
- * |[30] |SYNC |SYNC Flag Indicator
- * | | |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
- * | | |0 = synchronizing is completion, user can write new data to SC_PINCTL register.
- * | | |1 = Last value is synchronizing.
- * | | |Note: This bit is read only.
- */
- __IO uint32_t CTL;
-
- /**
- * ALTCTL
- * ===================================================================================================
- * Offset: 0x08 SC Alternate Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TXRST |TX Software Reset
- * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the TX internal state machine and pointers.
- * | | |Note: This bit will be auto cleared after reset is complete.
- * |[1] |RXRST |Rx Software Reset
- * | | |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the Rx internal state machine and pointers.
- * | | |Note: This bit will be auto cleared after reset is complete.
- * |[2] |DACTEN |Deactivation Sequence Generator Enable Control
- * | | |This bit enables SC controller to initiate the card by deactivation sequence
- * | | |0 = No effect.
- * | | |1 = Deactivation sequence generator Enabled.
- * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
- * | | |Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
- * | | |So don't fill this bit, TXRST, and RXRST at the same time.
- * | | |Note3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
- * |[3] |ACTEN |Activation Sequence Generator Enable Control
- * | | |This bit enables SC controller to initiate the card by activation sequence
- * | | |0 = No effect.
- * | | |1 = Activation sequence generator Enabled.
- * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
- * | | |Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
- * | | |Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Control
- * | | |This bit enables SC controller to initiate the card by warm reset sequence
- * | | |0 = No effect.
- * | | |1 = Warm reset sequence generator Enabled.
- * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
- * | | |Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
- * | | |Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[5] |CNTEN0 |Internal Timer0 Start Enable Control
- * | | |This bit enables Timer 0 to start counting.
- * | | |Software can fill 0 to stop it and set 1 to reload and count.
- * | | |0 = Stops counting.
- * | | |1 = Start counting.
- * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
- * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
- * | | |Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
- * | | |So don't fill this bit, TXRST and RXRST at the same time.
- * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[6] |CNTEN1 |Internal Timer1 Start Enable Control
- * | | |This bit enables Timer 1 to start counting.
- * | | |Software can fill 0 to stop it and set 1 to reload and count.
- * | | |0 = Stops counting.
- * | | |1 = Start counting.
- * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
- * | | |Don't filled CNTEN1 when SC_CTL([TMRSEL] = 00 or SC_CTL[TMRSEL] = 01.
- * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
- * | | |Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
- * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[7] |CNTEN2 |Internal Timer2 Start Enable Control
- * | | |This bit enables Timer 2 to start counting.
- * | | |Software can fill 0 to stop it and set 1 to reload and count.
- * | | |0 = Stops counting.
- * | | |1 = Start counting.
- * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
- * | | |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
- * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
- * | | |Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
- * | | |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
- * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
- * |[8:9] |INITSEL |Initial Timing Selection
- * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
- * | | |Unit: SC clock
- * | | |Activation: refer to SC Activation Sequence in Figure 5.19-4.
- * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 5.19-5
- * | | |Deactivation: refer to Deactivation Sequence in Figure 5.19-6
- * |[11] |ADACEN |Auto Deactivation When Card Removal
- * | | |0 = Auto deactivation Disabled when hardware detected the card removal.
- * | | |1 = Auto deactivation Enabled when hardware detected the card removal.
- * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set).
- * | | |If this process completes, hardware will generate an interrupt INT_INIT to CPU.
- * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Control
- * | | |0 = Receiver block guard time function Disabled.
- * | | |1 = Receiver block guard time function Enabled.
- * |[13] |ACTSTS0 |Internal Timer0 Active State (Read Only)
- * | | |This bit indicates the timer counter status of timer0.
- * | | |0 = Timer0 is not active.
- * | | |1 = Timer0 is active.
- * |[14] |ACTSTS1 |Internal Timer1 Active State (Read Only)
- * | | |This bit indicates the timer counter status of timer1.
- * | | |0 = Timer1 is not active.
- * | | |1 = Timer1 is active.
- * |[15] |ACTSTS2 |Internal Timer2 Active State (Read Only)
- * | | |This bit indicates the timer counter status of timer2.
- * | | |0 = Timer2 is not active.
- * | | |1 = Timer2 is active.
- */
- __IO uint32_t ALTCTL;
-
- /**
- * EGT
- * ===================================================================================================
- * Offset: 0x0C SC Extend Guard Time Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EGT |Extended Guard Time
- * | | |This field indicates the extended guard timer value.
- * | | |Note: The counter is ETU base and the real extended guard time is EGT.
- */
- __IO uint32_t EGT;
-
- /**
- * RXTOUT
- * ===================================================================================================
- * Offset: 0x10 SC Receive Buffer Time-out Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:8] |RFTM |SC Receiver Buffer Time-Out (ETU Base)
- * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
- * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
- * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
- * | | |Note2: Fill all 0 to this field indicates to disable this function.
- */
- __IO uint32_t RXTOUT;
-
- /**
- * ETUCTL
- * ===================================================================================================
- * Offset: 0x14 SC ETU Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |ETURDIV |ETU Rate Divider
- * | | |The field indicates the clock rate divider.
- * | | |The real ETU is ETURDIV + 1.
- * | | |Note: Software can configure this field, but this field must be greater than 0x004.
- * |[15] |CMPEN |Compensation Mode Enable Control
- * | | |This bit enables clock compensation function.
- * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
- * | | |0 = Compensation function Disabled.
- * | | |1 = Compensation function Enabled.
- */
- __IO uint32_t ETUCTL;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x18 SC Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Control
- * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
- * | | |0 = Receive data reach trigger level interrupt Disabled.
- * | | |1 = Receive data reach trigger level interrupt Enabled.
- * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Control
- * | | |This field is used for transmit buffer empty interrupt enable.
- * | | |0 = Transmit buffer empty interrupt Disabled.
- * | | |1 = Transmit buffer empty interrupt Enabled.
- * |[2] |TERRIEN |Transfer Error Interrupt Enable Control
- * | | |This field is used for transfer error interrupt enable.
- * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].
- * | | |0 = Transfer error interrupt Disabled.
- * | | |1 = Transfer error interrupt Enabled.
- * |[3] |TMR0IEN |Timer0 Interrupt Enable Control
- * | | |This field is used to enable TMR0 interrupt enable.
- * | | |0 = Timer0 interrupt Disabled.
- * | | |1 = Timer0 interrupt Enabled.
- * |[4] |TMR1IEN |Timer1 Interrupt Enable Control
- * | | |This field is used to enable the TMR1 interrupt.
- * | | |0 = Timer1 interrupt Disabled.
- * | | |1 = Timer1 interrupt Enabled.
- * |[5] |TMR2IEN |Timer2 Interrupt Enable Control
- * | | |This field is used for TMR2 interrupt enable.
- * | | |0 = Timer2 interrupt Disabled.
- * | | |1 = Timer2 interrupt Enabled.
- * |[6] |BGTIEN |Block Guard Time Interrupt Enable Control
- * | | |This field is used for block guard time interrupt enable.
- * | | |0 = Block guard time Disabled.
- * | | |1 = Block guard time Enabled.
- * |[7] |CDIEN |Card Detect Interrupt Enable Control
- * | | |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
- * | | |0 = Card detect interrupt Disabled.
- * | | |1 = Card detect interrupt Enabled.
- * |[8] |INITIEN |Initial End Interrupt Enable Control
- * | | |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation (DACTEN SC_ALTCTL[2] = 1) and warm reset (SC_ALTCTL [WARSTEN]) sequence interrupt enable.
- * | | |0 = Initial end interrupt Disabled.
- * | | |1 = Initial end interrupt Enabled.
- * |[9] |RXTOIF |Receiver Buffer Time-Out Interrupt Enable Control
- * | | |This field is used for receiver buffer time-out interrupt enable.
- * | | |0 = Receiver buffer time-out interrupt Disabled.
- * | | |1 = Receiver buffer time-out interrupt Enabled.
- * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Control
- * | | |This field is used for auto-convention error interrupt enable.
- * | | |0 = Auto-convention error interrupt Disabled.
- * | | |1 = Auto-convention error interrupt Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x1C SC Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
- * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
- * | | |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
- * | | |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
- * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
- * | | |This field is used for transmit buffer empty interrupt status flag.
- * | | |Note: This field is the status flag of transmit buffer empty state.
- * | | |If software wants to clear this bit, software must write data to SC_DAT bufferand then this bit will be cleared automatically.
- * |[2] |TERRIF |Transfer Error Interrupt Status Flag (Read Only)
- * | | |This field is used for transfer error interrupt status flag.
- * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
- * | | |Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]).
- * | | |So, if software wants to clear this bit, software must write 1 to each field.
- * |[3] |TMR0IF |Timer0 Interrupt Status Flag (Read Only)
- * | | |This field is used for TMR0 interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[4] |TMR1IF |Timer1 Interrupt Status Flag (Read Only)
- * | | |This field is used for TMR1 interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[5] |TMR2IF |Timer2 Interrupt Status Flag (Read Only)
- * | | |This field is used for TMR2 interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[6] |BGTIF |Block Guard Time Interrupt Status Flag (Read Only)
- * | | |This field is used for block guard time interrupt status flag.
- * | | |Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
- * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it.
- * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
- * | | |This field is used for card detect interrupt status flag.
- * | | |The card detect status is CINSERT (SC_STATUS[12])] and CREMOVE(SC_STATUS[11]).
- * | | |Note: This field is the status flag of CINSERT SC_STATUS[12]) SC_PINCTL[CINSERT] or CREMOVE(SC_STATUS[11])].
- * | | |So if software wants to clear this bit, software must write 1 to this field.
- * |[8] |INITIF |Initial End Interrupt Status Flag (Read Only)
- * | | |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[9] |RBTOIF |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
- * | | |This field is used for receiver buffer time-out interrupt status flag.
- * | | |Note: This field is the status flag of receiver buffer time-out state.
- * | | |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
- * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag (Read Only)
- * | | |This field indicates auto convention sequence error.
- * | | |If the received TS at ATR state is neither 3B nor 3F, this bit will be set.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- */
- __IO uint32_t INTSTS;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x20 SC Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXOV |RX Overflow Error Status Flag (Read Only)
- * | | |This bit is set when RX buffer overflow.
- * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[1] |RXEMPTY |Receiver Buffer Empty Status Flag(Read Only)
- * | | |This bit indicates RX buffer empty or not.
- * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
- * | | |It will be cleared when SC receives any new data.
- * |[2] |RXFULL |Receiver Buffer Full Status Flag (Read Only)
- * | | |This bit indicates RX buffer full or not.
- * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
- * |[4] |PEF |Receiver Parity Error Status Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid
- * | | |"parity bit".
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
- * |[5] |FEF |Receiver Frame Error Status Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
- * |[6] |BEF |Receiver Break Error Status Flag (Read Only)
- * | | |This bit is set to a logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
- * | | |.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
- * |[8] |TXOV |TX Overflow Error Interrupt Status Flag (Read Only)
- * | | |If TX buffer is full, an additional write to SC_DAT will cause this bit be set to "1" by hardware.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
- * | | |This bit indicates TX buffer empty or not.
- * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
- * | | |It will be cleared when writing data into SC_DAT (TX buffer not empty).
- * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
- * | | |This bit indicates TX buffer full or not.
- * | | |This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
- * |[11] |CREMOVE |Card Detect Removal Status Of SC_CD Pin (Read Only)
- * | | |This bit is set whenever card has been removal.
- * | | |0 = No effect.
- * | | |1 = Card removed.
- * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
- * | | |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
- * |[12] |CINSERT |Card Detect Insert Status Of SC_CD Pin (Read Only)
- * | | |This bit is set whenever card has been inserted.
- * | | |0 = No effect.1 = Card insert.
- * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
- * | | |Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
- * |[13] |CDPINSTS |Card Detect Status Of SC_CD Pin Status (Read Only)
- * | | |This bit is the pin status flag of SC_CD
- * | | |0 = The SC_CD pin state at low.
- * | | |1 = The SC_CD pin state at high.
- * |[16:17] |RXPOINT |Receiver Buffer Pointer Status Flag (Read Only)
- * | | |This field indicates the RX buffer pointer status flag.
- * | | |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
- * | | |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
- * |[21] |RXRERR |Receiver Retry Error (Read Only)
- * | | |This bit is set by hardware when RX has any error and retries transfer.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
- * | | |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
- * |[22] |RXOVERR |Receiver Over Retry Error (Read Only)
- * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
- * |[23] |RXACT |Receiver In Active Status Flag (Read Only)
- * | | |This bit is set by hardware when RX transfer is in active.
- * | | |This bit is cleared automatically when RX transfer is finished.
- * |[24:25] |TXPOINT |Transmit Buffer Pointer Status Flag (Read Only)
- * | | |This field indicates the TX buffer pointer status flag.
- * | | |When CPU writes data into SC_DAT, TXPOINT increases one.
- * | | |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
- * |[29] |TXRERR |Transmitter Retry Error (Read Only)
- * | | |This bit is set by hardware when transmitter re-transmits.
- * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
- * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
- * |[30] |TXOVERR |Transmitter Over Retry Error (Read Only)
- * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
- * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
- * |[31] |TXACT |Transmit In Active Status Flag (Read Only)
- * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
- * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
- */
- __IO uint32_t STATUS;
-
- /**
- * PINCTL
- * ===================================================================================================
- * Offset: 0x24 SC Pin Control State Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PWREN |SC_PWREN Pin Signal
- * | | |Software can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.
- * | | |Write this field to drive SC_PWR pin
- * | | |Refer PWRINV description for programming SC_PWR pin voltage level.
- * | | |Read this field to get SC_PWR pin status.
- * | | |0 = SC_PWR pin status is low.
- * | | |1 = SC_PWR pin status is high.
- * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when operating in these modes.
- * |[1] |SCRST |SCRST Pin Signal
- * | | |This bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.
- * | | |Write this field to drive SCRST pin.
- * | | |0 = Drive SCRST pin to low.
- * | | |1 = Drive SCRST pin to high.
- * | | |Read this
- * | | |field to get SCRST pin status.
- * | | |0 = SCRST pin status is low.
- * | | |1 = SCRST pin status is high.
- * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when operating in these modes.
- * |[6] |CLKKEEP |SC Clock Enable Control
- * | | |0 = SC clock generation Disabled.
- * | | |1 = SC clock always keeps free running.
- * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when operating in these modes.
- * |[9] |SCDOOUT |SC Data Output Pin
- * | | |This bit is the pin status of SCDOOUT but user can drive SCDOOUT pin to high or low by setting this bit.
- * | | |0 = Drive SCDOOUT pin to low.
- * | | |1 = Drive SCDOOUT pin to high.
- * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |So don't fill this field when SC is in these modes.
- * |[11] |PWRINV |SC_POW Pin Inverse
- * | | |This bit is used for inverse the SC_POW pin.
- * | | |There are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]).
- * | | |PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.
- * | | |PWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.
- * | | |PWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.
- * | | |PWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.
- * | | |PWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.
- * | | |Note: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
- * |[16] |DATSTS |This bit is the pin status of SC_DAT
- * | | |0 = The SC_DAT pin is low.
- * | | |1 = The SC_DAT pin is high.
- * |[17] |PWRSTS |SC_PWR Pin Signal
- * | | |This bit is the pin status of SC_PWR
- * | | |0 = SC_PWR pin to low.
- * | | |1 = SC_PWR pin to high.
- * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |This bit is not allowed to program when SC is operated at these modes.
- * |[18] |RSTSTS |SC_RST Pin Signals
- * | | |This bit is the pin status of SC_RST
- * | | |0 = SC_RST pin is low.
- * | | |1 = SC_RST pin is high.
- * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
- * | | |This bit is not allowed to program when SC is operated at these modes.
- * |[30] |SYNC |SYNC Flag Indicator
- * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
- * | | |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
- * | | |1 = Last value is synchronizing.
- * | | |Note: This bit is read only.
- */
- __IO uint32_t PINCTL;
-
- /**
- * TMRCTL0
- * ===================================================================================================
- * Offset: 0x28 SC Internal Timer Control Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |CNT |Timer 0 Counter Value (ETU Base)
- * | | |This field indicates the internal timer operation values.
- * |[24:27] |OPMODE |Timer 0 Operation Mode Selection
- * | | |This field indicates the internal 24-bit timer operation selection.
- * | | |Refer to 6.25.4.4 for programming Timer0.
- */
- __IO uint32_t TMRCTL0;
-
- /**
- * TMRCTL1
- * ===================================================================================================
- * Offset: 0x2C SC Internal Timer Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |CNT |Timer 1 Counter Value (ETU Base)
- * | | |This field indicates the internal timer operation values.
- * |[24:27] |OPMODE |Timer 1 Operation Mode Selection
- * | | |This field indicates the internal 8-bit timer operation selection.
- * | | |Refer to 6.25.4.4 for programming Timer1.
- */
- __IO uint32_t TMRCTL1;
-
- /**
- * TMRCTL2
- * ===================================================================================================
- * Offset: 0x30 SC Internal Timer Control Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |CNT |Timer 2 Counter Value (ETU Base)
- * | | |This field indicates the internal timer operation values.
- * |[24:27] |OPMODE |Timer 2 Operation Mode Selection
- * | | |This field indicates the internal 8-bit timer operation selection
- * | | |Refer to 6.25.4.4 for programming Timer2
- */
- __IO uint32_t TMRCTL2;
-
- /**
- * UARTCTL
- * ===================================================================================================
- * Offset: 0x34 SC UART Mode Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |UARTEN |UART Mode Enable Control
- * | | |0 = Smart Card mode.
- * | | |1 = UART mode.
- * | | |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
- * | | |Note2: When operating in Smart Card mode, user must set SC_UARTCTL [7:0] = 00.
- * | | |Note3: When UART is enabled, hardware will generate a reset to resetFIFO and internal state machine.
- * |[4:5] |WLS |Data Length
- * | | |00 = Character Data Length is 8 bits.
- * | | |01 = Character Data Length is 7 bits.
- * | | |10 = Character Data length is 6 bits.
- * | | |11 = Character Data Length is 5 bits.
- * | | |Note: In smart card mode, this WLS must be '00'
- * |[6] |PBOFF |Parity Bit Disable Control
- * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
- * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
- * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
- * |[7] |OPE |Odd Parity Enable Control
- * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
- * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
- * | | |Note: This bit has effect only when PBOFF bit is '0'.
- */
- __IO uint32_t UARTCTL;
-
- /**
- * TMRDAT0
- * ===================================================================================================
- * Offset: 0x38 SC Timer 0 Current Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |CNT0 |Timer0 Current Counter Value (Read Only)
- * | | |This field indicates the current count values of timer0.
- */
- __I uint32_t TMRDAT0;
-
- /**
- * TMRDAT1_2
- * ===================================================================================================
- * Offset: 0x3C SC Timer 1 and 2 Current Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |CNT1 |Timer1 Current Counter Value (Read Only)
- * | | |This field indicates the current count values of timer1.
- * |[8:15] |CNT2 |Timer2 Current Counter Value (Read Only)
- * | | |This field indicates the current count values of timer2.
- */
- __I uint32_t TMRDAT1_2;
-
-} SC_T;
-
-/**
- @addtogroup SC_CONST SC Bit Field Definition
- Constant Definitions for SC Controller
-@{ */
-
-#define SC_DAT_DAT_Pos (0) /*!< SC DAT: DAT Position */
-#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC DAT: DAT Mask */
-
-#define SC_CTL_SCEN_Pos (0) /*!< SC CTL: SCEN Position */
-#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC CTL: SCEN Mask */
-
-#define SC_CTL_RXOFF_Pos (1) /*!< SC CTL: RXOFF Position */
-#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC CTL: RXOFF Mask */
-
-#define SC_CTL_TXOFF_Pos (2) /*!< SC CTL: TXOFF Position */
-#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC CTL: TXOFF Mask */
-
-#define SC_CTL_AUTOCEN_Pos (3) /*!< SC CTL: AUTOCEN Position */
-#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC CTL: AUTOCEN Mask */
-
-#define SC_CTL_CONSEL_Pos (4) /*!< SC CTL: CONSEL Position */
-#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC CTL: CONSEL Mask */
-
-#define SC_CTL_RXTRGLV_Pos (6) /*!< SC CTL: RXTRGLV Position */
-#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC CTL: RXTRGLV Mask */
-
-#define SC_CTL_BGT_Pos (8) /*!< SC CTL: BGT Position */
-#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC CTL: BGT Mask */
-
-#define SC_CTL_TMRSEL_Pos (13) /*!< SC CTL: TMRSEL Position */
-#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC CTL: TMRSEL Mask */
-
-#define SC_CTL_NSB_Pos (15) /*!< SC CTL: NSB Position */
-#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC CTL: NSB Mask */
-
-#define SC_CTL_RXRTY_Pos (16) /*!< SC CTL: RXRTY Position */
-#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC CTL: RXRTY Mask */
-
-#define SC_CTL_RXRTYEN_Pos (19) /*!< SC CTL: RXRTYEN Position */
-#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC CTL: RXRTYEN Mask */
-
-#define SC_CTL_TXRTY_Pos (20) /*!< SC CTL: TXRTY Position */
-#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC CTL: TXRTY Mask */
-
-#define SC_CTL_TXRTYEN_Pos (23) /*!< SC CTL: TXRTYEN Position */
-#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC CTL: TXRTYEN Mask */
-
-#define SC_CTL_CDDBSEL_Pos (24) /*!< SC CTL: CDDBSEL Position */
-#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC CTL: CDDBSEL Mask */
-
-#define SC_CTL_CDLV_Pos (26) /*!< SC CTL: CDLV Position */
-#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC CTL: CDLV Mask */
-
-#define SC_CTL_SYNC_Pos (30) /*!< SC CTL: SYNC Position */
-#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC CTL: SYNC Mask */
-
-#define SC_ALTCTL_TXRST_Pos (0) /*!< SC ALTCTL: TXRST Position */
-#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC ALTCTL: TXRST Mask */
-
-#define SC_ALTCTL_RXRST_Pos (1) /*!< SC ALTCTL: RXRST Position */
-#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC ALTCTL: RXRST Mask */
-
-#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC ALTCTL: DACTEN Position */
-#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC ALTCTL: DACTEN Mask */
-
-#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC ALTCTL: ACTEN Position */
-#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC ALTCTL: ACTEN Mask */
-
-#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC ALTCTL: WARSTEN Position */
-#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC ALTCTL: WARSTEN Mask */
-
-#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC ALTCTL: CNTEN0 Position */
-#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC ALTCTL: CNTEN0 Mask */
-
-#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC ALTCTL: CNTEN1 Position */
-#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC ALTCTL: CNTEN1 Mask */
-
-#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC ALTCTL: CNTEN2 Position */
-#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC ALTCTL: CNTEN2 Mask */
-
-#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC ALTCTL: INITSEL Position */
-#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC ALTCTL: INITSEL Mask */
-
-#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC ALTCTL: ADACEN Position */
-#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC ALTCTL: ADACEN Mask */
-
-#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC ALTCTL: RXBGTEN Position */
-#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC ALTCTL: RXBGTEN Mask */
-
-#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC ALTCTL: ACTSTS0 Position */
-#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC ALTCTL: ACTSTS0 Mask */
-
-#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC ALTCTL: ACTSTS1 Position */
-#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC ALTCTL: ACTSTS1 Mask */
-
-#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC ALTCTL: ACTSTS2 Position */
-#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC ALTCTL: ACTSTS2 Mask */
-
-#define SC_EGT_EGT_Pos (0) /*!< SC EGT: EGT Position */
-#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC EGT: EGT Mask */
-
-#define SC_RXTOUT_RFTM_Pos (0) /*!< SC RXTOUT: RFTM Position */
-#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC RXTOUT: RFTM Mask */
-
-#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC ETUCTL: ETURDIV Position */
-#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC ETUCTL: ETURDIV Mask */
-
-#define SC_ETUCTL_CMPEN_Pos (15) /*!< SC ETUCTL: CMPEN Position */
-#define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /*!< SC ETUCTL: CMPEN Mask */
-
-#define SC_INTEN_RDAIEN_Pos (0) /*!< SC INTEN: RDAIEN Position */
-#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC INTEN: RDAIEN Mask */
-
-#define SC_INTEN_TBEIEN_Pos (1) /*!< SC INTEN: TBEIEN Position */
-#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC INTEN: TBEIEN Mask */
-
-#define SC_INTEN_TERRIEN_Pos (2) /*!< SC INTEN: TERRIEN Position */
-#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC INTEN: TERRIEN Mask */
-
-#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC INTEN: TMR0IEN Position */
-#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC INTEN: TMR0IEN Mask */
-
-#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC INTEN: TMR1IEN Position */
-#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC INTEN: TMR1IEN Mask */
-
-#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC INTEN: TMR2IEN Position */
-#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC INTEN: TMR2IEN Mask */
-
-#define SC_INTEN_BGTIEN_Pos (6) /*!< SC INTEN: BGTIEN Position */
-#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC INTEN: BGTIEN Mask */
-
-#define SC_INTEN_CDIEN_Pos (7) /*!< SC INTEN: CDIEN Position */
-#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC INTEN: CDIEN Mask */
-
-#define SC_INTEN_INITIEN_Pos (8) /*!< SC INTEN: INITIEN Position */
-#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC INTEN: INITIEN Mask */
-
-#define SC_INTEN_RXTOIF_Pos (9) /*!< SC INTEN: RXTOIF Position */
-#define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /*!< SC INTEN: RXTOIF Mask */
-
-#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC INTEN: ACERRIEN Position */
-#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC INTEN: ACERRIEN Mask */
-
-#define SC_INTSTS_RDAIF_Pos (0) /*!< SC INTSTS: RDAIF Position */
-#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC INTSTS: RDAIF Mask */
-
-#define SC_INTSTS_TBEIF_Pos (1) /*!< SC INTSTS: TBEIF Position */
-#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC INTSTS: TBEIF Mask */
-
-#define SC_INTSTS_TERRIF_Pos (2) /*!< SC INTSTS: TERRIF Position */
-#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC INTSTS: TERRIF Mask */
-
-#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC INTSTS: TMR0IF Position */
-#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC INTSTS: TMR0IF Mask */
-
-#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC INTSTS: TMR1IF Position */
-#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC INTSTS: TMR1IF Mask */
-
-#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC INTSTS: TMR2IF Position */
-#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC INTSTS: TMR2IF Mask */
-
-#define SC_INTSTS_BGTIF_Pos (6) /*!< SC INTSTS: BGTIF Position */
-#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC INTSTS: BGTIF Mask */
-
-#define SC_INTSTS_CDIF_Pos (7) /*!< SC INTSTS: CDIF Position */
-#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC INTSTS: CDIF Mask */
-
-#define SC_INTSTS_INITIF_Pos (8) /*!< SC INTSTS: INITIF Position */
-#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC INTSTS: INITIF Mask */
-
-#define SC_INTSTS_RBTOIF_Pos (9) /*!< SC INTSTS: RBTOIF Position */
-#define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /*!< SC INTSTS: RBTOIF Mask */
-
-#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC INTSTS: ACERRIF Position */
-#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC INTSTS: ACERRIF Mask */
-
-#define SC_STATUS_RXOV_Pos (0) /*!< SC STATUS: RXOV Position */
-#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC STATUS: RXOV Mask */
-
-#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC STATUS: RXEMPTY Position */
-#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC STATUS: RXEMPTY Mask */
-
-#define SC_STATUS_RXFULL_Pos (2) /*!< SC STATUS: RXFULL Position */
-#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC STATUS: RXFULL Mask */
-
-#define SC_STATUS_PEF_Pos (4) /*!< SC STATUS: PEF Position */
-#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC STATUS: PEF Mask */
-
-#define SC_STATUS_FEF_Pos (5) /*!< SC STATUS: FEF Position */
-#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC STATUS: FEF Mask */
-
-#define SC_STATUS_BEF_Pos (6) /*!< SC STATUS: BEF Position */
-#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC STATUS: BEF Mask */
-
-#define SC_STATUS_TXOV_Pos (8) /*!< SC STATUS: TXOV Position */
-#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC STATUS: TXOV Mask */
-
-#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC STATUS: TXEMPTY Position */
-#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC STATUS: TXEMPTY Mask */
-
-#define SC_STATUS_TXFULL_Pos (10) /*!< SC STATUS: TXFULL Position */
-#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC STATUS: TXFULL Mask */
-
-#define SC_STATUS_CREMOVE_Pos (11) /*!< SC STATUS: CREMOVE Position */
-#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC STATUS: CREMOVE Mask */
-
-#define SC_STATUS_CINSERT_Pos (12) /*!< SC STATUS: CINSERT Position */
-#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC STATUS: CINSERT Mask */
-
-#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC STATUS: CDPINSTS Position */
-#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC STATUS: CDPINSTS Mask */
-
-#define SC_STATUS_RXPOINT_Pos (16) /*!< SC STATUS: RXPOINT Position */
-#define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /*!< SC STATUS: RXPOINT Mask */
-
-#define SC_STATUS_RXRERR_Pos (21) /*!< SC STATUS: RXRERR Position */
-#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC STATUS: RXRERR Mask */
-
-#define SC_STATUS_RXOVERR_Pos (22) /*!< SC STATUS: RXOVERR Position */
-#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC STATUS: RXOVERR Mask */
-
-#define SC_STATUS_RXACT_Pos (23) /*!< SC STATUS: RXACT Position */
-#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC STATUS: RXACT Mask */
-
-#define SC_STATUS_TXPOINT_Pos (24) /*!< SC STATUS: TXPOINT Position */
-#define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /*!< SC STATUS: TXPOINT Mask */
-
-#define SC_STATUS_TXRERR_Pos (29) /*!< SC STATUS: TXRERR Position */
-#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC STATUS: TXRERR Mask */
-
-#define SC_STATUS_TXOVERR_Pos (30) /*!< SC STATUS: TXOVERR Position */
-#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC STATUS: TXOVERR Mask */
-
-#define SC_STATUS_TXACT_Pos (31) /*!< SC STATUS: TXACT Position */
-#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC STATUS: TXACT Mask */
-
-#define SC_PINCTL_PWREN_Pos (0) /*!< SC PINCTL: PWREN Position */
-#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC PINCTL: PWREN Mask */
-
-#define SC_PINCTL_SCRST_Pos (1) /*!< SC PINCTL: SCRST Position */
-#define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /*!< SC PINCTL: SCRST Mask */
-
-#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC PINCTL: CLKKEEP Position */
-#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC PINCTL: CLKKEEP Mask */
-
-#define SC_PINCTL_SCDOUT_Pos (9) /*!< SC PINCTL: SCDOUT Position */
-#define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /*!< SC PINCTL: SCDOUT Mask */
-
-#define SC_PINCTL_PWRINV_Pos (11) /*!< SC PINCTL: PWRINV Position */
-#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC PINCTL: PWRINV Mask */
-
-#define SC_PINCTL_DATSTS_Pos (16) /*!< SC PINCTL: DATSTS Position */
-#define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /*!< SC PINCTL: DATSTS Mask */
-
-#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC PINCTL: PWRSTS Position */
-#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC PINCTL: PWRSTS Mask */
-
-#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC PINCTL: RSTSTS Position */
-#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC PINCTL: RSTSTS Mask */
-
-#define SC_PINCTL_SYNC_Pos (30) /*!< SC PINCTL: SYNC Position */
-#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC PINCTL: SYNC Mask */
-
-#define SC_TMRCTL0_CNT_Pos (0) /*!< SC TMRCTL0: CNT Position */
-#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC TMRCTL0: CNT Mask */
-
-#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC TMRCTL0: OPMODE Position */
-#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC TMRCTL0: OPMODE Mask */
-
-#define SC_TMRCTL1_CNT_Pos (0) /*!< SC TMRCTL1: CNT Position */
-#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC TMRCTL1: CNT Mask */
-
-#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC TMRCTL1: OPMODE Position */
-#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC TMRCTL1: OPMODE Mask */
-
-#define SC_TMRCTL2_CNT_Pos (0) /*!< SC TMRCTL2: CNT Position */
-#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC TMRCTL2: CNT Mask */
-
-#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC TMRCTL2: OPMODE Position */
-#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC TMRCTL2: OPMODE Mask */
-
-#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC UARTCTL: UARTEN Position */
-#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC UARTCTL: UARTEN Mask */
-
-#define SC_UARTCTL_WLS_Pos (4) /*!< SC UARTCTL: WLS Position */
-#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC UARTCTL: WLS Mask */
-
-#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC UARTCTL: PBOFF Position */
-#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC UARTCTL: PBOFF Mask */
-
-#define SC_UARTCTL_OPE_Pos (7) /*!< SC UARTCTL: OPE Position */
-#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC UARTCTL: OPE Mask */
-
-#define SC_TMRDAT0_TDR0_Pos (0) /*!< SC TMRDAT0: TDR0 Position */
-#define SC_TMRDAT0_TDR0_Msk (0xfffffful << SC_TMRDAT0_TDR0_Pos) /*!< SC TMRDAT0: TDR0 Mask */
-
-#define SC_TMRDAT1_2_TDR1_Pos (0) /*!< SC TMRDAT1_2: TDR1 Position */
-#define SC_TMRDAT1_2_TDR1_Msk (0xfful << SC_TMRDAT1_2_TDR1_Pos) /*!< SC TMRDAT1_2: TDR1 Mask */
-
-#define SC_TMRDAT1_2_TDR2_Pos (8) /*!< SC TMRDAT1_2: TDR2 Position */
-#define SC_TMRDAT1_2_TDR2_Msk (0xfful << SC_TMRDAT1_2_TDR2_Pos) /*!< SC TMRDAT1_2: TDR2 Mask */
-
-/**@}*/ /* SC_CONST */
-/**@}*/ /* end of SC register group */
-
-
-/*---------------------- SD Card Host Interface -------------------------*/
-/**
- @addtogroup SDH SD Card Host Interface(SDH)
- Memory Mapped Structure for SDH Controller
-@{ */
-
-typedef struct {
-
- /**
- * FBx
- * ===================================================================================================
- * Offset: 0x00 ~ 0x7C Shared Buffer (FIFO) 0 ~ 31
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |BUF |Shared Buffer
-
- */
- uint32_t FB[32];
- uint32_t RESERVE0[224];
-
-
- /**
- * DMACTL
- * ===================================================================================================
- * Offset: 0x400 DMA Control and Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DMAEN |DMA Engine Enable Control
- * | | |0 = DMA Disabled.
- * | | |1 = DMA Enabled.
- * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
- * | | |Note: If target abort is occurred, DMAEN will be cleared.
- * |[1] |DMARST |Software Engine Reset
- * | | |0 = No effect.
- * | | |1 = Reset internal state machine and pointers.
- * | | |The contents of control register will not be cleared.
- * | | |This bit will auto be cleared after few clock cycles.
- * | | |Note: The software reset DMA related registers.
- * |[3] |SGEN |Scatter-Gather Function Enable Control
- * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
- * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table.
- * | | |The format of these Pads' will be described later).
- * |[9] |DMABUSY |DMA Transfer Is In Progress
- * | | |This bit indicates if SD Host is granted and doing DMA transfer or not.
- * | | |0 = DMA transfer is not in progress.
- * | | |1 = DMA transfer is in progress.
- */
- __IO uint32_t DMACTL;
- uint32_t RESERVE1[1];
-
-
- /**
- * DMASA
- * ===================================================================================================
- * Offset: 0x408 DMA Transfer Starting Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ORDER |Determined To The PAD Table Fetching Is In Order Or Out Of Order
- * | | |0 = PAD table is fetched in order.
- * | | |1 = PAD table is fetched out of order.
- * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
- * |[1:31] |DMASA |DMA Transfer Starting Address
- * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
- * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
- */
- __IO uint32_t DMASA;
-
- /**
- * DMABCNT
- * ===================================================================================================
- * Offset: 0x40C DMA Transfer Byte Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:25] |BCNT |DMA Transfer Byte Count (Read Only)
- * | | |This field indicates the remained byte count of DMA transfer.
- * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.
- */
- __I uint32_t DMABCNT;
-
- /**
- * DMAINTEN
- * ===================================================================================================
- * Offset: 0x410 DMA Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Control
- * | | |0 = Target abort interrupt generation Disabled during DMA transfer.
- * | | |1 = Target abort interrupt generation Enabled during DMA transfer.
- * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Control
- * | | |0 = Interrupt generation Disabled when wrong EOT is encountered.
- * | | |1 = Interrupt generation Enabled when wrong EOT is encountered.
- */
- __IO uint32_t DMAINTEN;
-
- /**
- * DMAINTSTS
- * ===================================================================================================
- * Offset: 0x414 DMA Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag
- * | | |0 = No bus ERROR response received.
- * | | |1 = Bus ERROR response received.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag
- * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
- * | | |0 = No EOT encountered before DMA transfer finished.
- * | | |1 = EOT encountered before DMA transfer finished.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- */
- __IO uint32_t DMAINTSTS;
- uint32_t RESERVE2[250];
-
-
- /**
- * GCTL
- * ===================================================================================================
- * Offset: 0x800 Global Control and Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |GCTLRST |Software Engine Reset
- * | | |0 = No effect.
- * | | |1 = Reset SD host.
- * | | |The contents of control register will not be cleared.
- * | | |This bit will auto cleared after reset complete.
- * |[1] |SDEN |Secure Digital Functionality Enable Control
- * | | |0 = SD functionality disabled.
- * | | |1 = SD functionality enabled.
- */
- __IO uint32_t GCTL;
-
- /**
- * GINTEN
- * ===================================================================================================
- * Offset: 0x804 Global Interrupt Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Control
- * | | |0 = DMA READ/WRITE target abort interrupt generation disabled.
- * | | |1 = DMA READ/WRITE target abort interrupt generation enabled.
- */
- __IO uint32_t GINTEN;
-
- /**
- * GINTSTS
- * ===================================================================================================
- * Offset: 0x808 Global Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
- * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation.
- * | | |When Target Abort is occurred, please reset all engine.
- * | | |0 = No bus ERROR response received.
- * | | |1 = Bus ERROR response received.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- */
- __I uint32_t GINTSTS;
- uint32_t RESERVE3[5];
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x820 SD Control and Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |COEN |Command Output Enable Control
- * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
- * | | |1 = Enabled, SD host will output a command to SD card.
- * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
- * |[1] |RIEN |Response Input Enable Control
- * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
- * | | |1 = Enabled, SD host will wait to receive a response from SD card.
- * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
- * |[2] |DIEN |Data Input Enable Control
- * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
- * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
- * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
- * |[3] |DOEN |Data Output Enable Control
- * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
- * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
- * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
- * |[4] |R2EN |Response R2 Input Enable Control
- * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
- * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
- * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
- * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Control
- * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
- * | | |1 = Enabled, SD host will output 74 clock cycles to SD card.
- * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
- * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Control
- * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
- * | | |1 = Enabled, SD host will output 8 clock cycles.
- * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
- * |[7] |CLKKEEP0 |SD Clock Enable Control For Port 0
- * | | |0 = SD host decided when to output clock and when to disable clock output automatically.
- * | | |1 = SD clock always keeps free running.
- * |[8:13] |CMDCODE |SD Command Code
- * | | |This register contains the SD command code (0x00 - 0x3F).
- * |[14] |CTLRST |Software Engine Reset
- * | | |0 = No effect.
- * | | |1 = Reset the internal state machine and counters.
- * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared).
- * | | |This bit will be auto cleared after few clock cycles.
- * |[15] |DBW |SD Data Bus Width (For 1-Bit / 4-Bit Selection)
- * | | |0 = Data bus width is 1-bit.
- * | | |1 = Data bus width is 4-bit.
- * |[16:23] |BLKCNT |Block Counts To Be Transferred Or Received
- * | | |This field contains the block counts for data-in and data-out transfer.
- * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance.
- * | | |Don't fill 0x0 to this field.
- * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
- * |[24:27] |SDNWR |NWR Parameter For Block Write Operation
- * | | |This value indicates the NWR parameter for data block write operation in SD clock counts.
- * | | |The actual clock cycle will be SDNWR+1.
- * |[29:30] |SDPORT |SD Port Selection
- * | | |00 = Port 0 selected.
- * | | |01 = Port 1 selected.
- * | | |Other = Reserved.
- * |[31] |CLKKEEP1 |SD Clock Enable Control For Port 1
- * | | |0 = SD host decided when to output clock and when to disable clock output automatically.
- * | | |1 = SD clock always keeps free running.
- */
- __IO uint32_t CTL;
-
- /**
- * CMDARG
- * ===================================================================================================
- * Offset: 0x824 SD Command Argument Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |ARGUMENT |SD Command Argument
- * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card.
- * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
- */
- __IO uint32_t CMDARG;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x828 SD Interrupt Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Control
- * | | |0 = SD host will not generate interrupt when data-in (out) transfer done.
- * | | |1 = SD host will generate interrupt when data-in (out) transfer done.
- * |[1] |CRCIEN |CRC7, CRC16 And CRC Status Error Interrupt Enable Control
- * | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error.
- * | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error.
- * |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Control
- * | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed.
- * | | |0 = Disable.
- * | | |1 = Enabled.
- * |[9] |CDIEN1 |SD1 Card Detection Interrupt Enable Control
- * | | |Enable/Disable interrupts generation of SD controller when card 1 is inserted or removed.
- * | | |0 = Disable.
- * | | |1 = Enabled.
- * |[12] |RTOIEN |Response Time-Out Interrupt Enable Control
- * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out.
- * | | |Time-out value is specified at TOUT register.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[13] |DITOIEN |Data Input Time-Out Interrupt Enable Control
- * | | |Enable/Disable interrupts generation of SD controller when data input time-out.
- * | | |Time-out value is specified at TOUT register.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[14] |WKIEN |Wake-Up Signal Generating Enable Control
- * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * |[30] |CDSRC0 |SD0 Card Detect Source Selection
- * | | |0 = From SD0 card's DAT3 pin.
- * | | |Host need clock to got data on pin DAT3.
- * | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
- * | | |1 = From GPIO pin.
- * |[31] |CDSRC1 |SD1 Card Detect Source Selection
- * | | |0 = From SD1 card's DAT3 pin.
- * | | |Host need clock to got data on pin DAT3.
- * | | |Please make sure CLKKEEP1 (SDH_CTL[31]) is 1 in order to generate free running clock for DAT3 pin.
- * | | |1 = From GPIO pin.
- */
- __IO uint32_t INTEN;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x82C SD Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)
- * | | |This bit indicates that SD host has finished all data-in or data-out block transfer.
- * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
- * | | |0 = Not finished yet.
- * | | |1 = Done.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[1] |CRCIF |CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only)
- * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer.
- * | | |When CRC error is occurred, software should reset SD engine.
- * | | |Some response (ex.
- * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag.
- * | | |In this condition, software should ignore CRC error and clears this bit manually.
- * | | |0 = No CRC error is occurred.
- * | | |1 = CRC error is occurred.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[2] |CRC7 |CRC7 Check Status (Read Only)
- * | | |SD host will check CRC7 correctness during each response in.
- * | | |If that response does not contain CRC7 information (ex.
- * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
- * | | |0 = Fault.
- * | | |1 = OK.
- * |[3] |CRC16 |CRC16 Check Status Of Data-In Transfer (Read Only)
- * | | |SD host will check CRC16 correctness after data-in transfer.
- * | | |0 = Fault.
- * | | |1 = OK.
- * |[4:6] |CRCSTS |CRC Status Value Of Data-Out Transfer (Read Only)
- * | | |SD host will record CRC status of data-out transfer.
- * | | |Software could use this value to identify what type of error is during data-out transfer.
- * | | |010 = Positive CRC status.
- * | | |101 = Negative CRC status.
- * | | |111 = SD card programming error occurs.
- * |[7] |DAT0STS |DAT0 Pin Status Of Current Selected SD Port (Read Only)
- * | | |This bit is the DAT0 pin status of current selected SD port.
- * |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only)
- * | | |This bit indicates that SD card 0 is inserted or removed.
- * | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.
- * | | |0 = No card is inserted or removed.
- * | | |1 = There is a card inserted in or removed from SD0.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[9] |CDIF1 |SD1 Card Detection Interrupt Flag (Read Only)
- * | | |This bit indicates that SD card 1 is inserted or removed.
- * | | |Only when CDIEN1 (SDH_INTEN[9]) is set to 1, this bit is active.
- * | | |0 = No card is inserted or removed.
- * | | |1 = There is a card inserted in or removed from SD1.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[12] |RTOIF |Response Time-Out Interrupt Flag (Read Only)
- * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
- * | | |0 = Not time-out.
- * | | |1 = Response time-out.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[13] |DITOIF |Data Input Time-Out Interrupt Flag (Read Only)
- * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
- * | | |0 = Not time-out.
- * | | |1 = Data input time-out.
- * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
- * |[16] |CDSTS0 |Card Detect Status Of SD0 (Read Only)
- * | | |This bit indicates the card detect pin status of SD0, and is used for card detection.
- * | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.
- * | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
- * | | |0 = Card removed.
- * | | |1 = Card inserted.
- * | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
- * | | |0 = Card inserted.
- * | | |1 = Card removed.
- * |[17] |CDSTS1 |Card Detect Status Of SD1 (Read Only)
- * | | |This bit indicates the card detect pin status of SD1, and is used for card detection.
- * | | |When there is a card inserted in or removed from SD1, software should check this bit to confirm if there is really a card insertion or removal.
- * | | |If CDSRC1 (SDH_INTEN[31]) = 0, to select DAT3 for card detection:.
- * | | |0 = Card removed.
- * | | |1 = Card inserted.
- * | | |If CDSRC1 (SDH_INTEN[31]) = 1, to select GPIO for card detection:.
- * | | |0 = Card inserted.
- * | | |1 = Card removed.
- * |[18] |DAT1STS |DAT1 Pin Status Of SD Port (Read Only)
- * | | |This bit indicates the DAT1 pin status of SD port.
- */
- __IO uint32_t INTSTS;
-
- /**
- * RESP0
- * ===================================================================================================
- * Offset: 0x830 SD Receiving Response Token Register 0
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |RESPTK0 |SD Receiving Response Token 0
- * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set.
- * | | |This field contains response bit 47-16 of the response token.
- */
- __I uint32_t RESP0;
-
- /**
- * RESP1
- * ===================================================================================================
- * Offset: 0x834 SD Receiving Response Token Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |RESPTK1 |SD Receiving Response Token 1
- * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set.
- * | | |This register contains the bit 15-8 of the response token.
- */
- __I uint32_t RESP1;
-
- /**
- * BLEN
- * ===================================================================================================
- * Offset: 0x838 SD Block Length Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |BLKLEN |SD BLOCK LENGTH In Byte Unit
- * | | |An 11-bit value specifies the SD transfer byte count of a block.
- * | | |The actual byte count is equal to BLKLEN+1.
- * | | |Note: The default SD block length is 512 bytes
- */
- __IO uint32_t BLEN;
-
- /**
- * TOUT
- * ===================================================================================================
- * Offset: 0x83C SD Response/Data-in Time-out Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |TOUT |SD Response/Data-In Time-Out Value
- * | | |A 24-bit value specifies the time-out counts of response and data input.
- * | | |SD host controller will wait start bit of response or data-in until this value reached.
- * | | |The time period depends on SD engine clock frequency.
- * | | |Do not write a small number into this field, or you may never get response or data due to time-out.
- * | | |Note: Filling 0x0 into this field will disable hardware time-out function.
- */
- __IO uint32_t TOUT;
-
-} SDH_T;
-
-/**
- @addtogroup SDH_CONST SDH Bit Field Definition
- Constant Definitions for SDH Controller
-@{ */
-
-#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH DMACTL: DMAEN Position */
-#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH DMACTL: DMAEN Mask */
-
-#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH DMACTL: DMARST Position */
-#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH DMACTL: DMARST Mask */
-
-#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH DMACTL: SGEN Position */
-#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH DMACTL: SGEN Mask */
-
-#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH DMACTL: DMABUSY Position */
-#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH DMACTL: DMABUSY Mask */
-
-#define SDH_DMASA_ORDER_Pos (0) /*!< SDH DMASA: ORDER Position */
-#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH DMASA: ORDER Mask */
-
-#define SDH_DMASA_DMASA_Pos (1) /*!< SDH DMASA: DMASA Position */
-#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH DMASA: DMASA Mask */
-
-#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH DMABCNT: BCNT Position */
-#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH DMABCNT: BCNT Mask */
-
-#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH DMAINTEN: ABORTIEN Position */
-#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH DMAINTEN: ABORTIEN Mask */
-
-#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH DMAINTEN: WEOTIEN Position */
-#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH DMAINTEN: WEOTIEN Mask */
-
-#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH DMAINTSTS: ABORTIF Position */
-#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH DMAINTSTS: ABORTIF Mask */
-
-#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH DMAINTSTS: WEOTIF Position */
-#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH DMAINTSTS: WEOTIF Mask */
-
-#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH GCTL: GCTLRST Position */
-#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH GCTL: GCTLRST Mask */
-
-#define SDH_GCTL_SDEN_Pos (1) /*!< SDH GCTL: SDEN Position */
-#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH GCTL: SDEN Mask */
-
-#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH GINTEN: DTAIEN Position */
-#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH GINTEN: DTAIEN Mask */
-
-#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH GINTSTS: DTAIF Position */
-#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH GINTSTS: DTAIF Mask */
-
-#define SDH_CTL_COEN_Pos (0) /*!< SDH CTL: COEN Position */
-#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH CTL: COEN Mask */
-
-#define SDH_CTL_RIEN_Pos (1) /*!< SDH CTL: RIEN Position */
-#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH CTL: RIEN Mask */
-
-#define SDH_CTL_DIEN_Pos (2) /*!< SDH CTL: DIEN Position */
-#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH CTL: DIEN Mask */
-
-#define SDH_CTL_DOEN_Pos (3) /*!< SDH CTL: DOEN Position */
-#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH CTL: DOEN Mask */
-
-#define SDH_CTL_R2EN_Pos (4) /*!< SDH CTL: R2EN Position */
-#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH CTL: R2EN Mask */
-
-#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH CTL: CLK74OEN Position */
-#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH CTL: CLK74OEN Mask */
-
-#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH CTL: CLK8OEN Position */
-#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH CTL: CLK8OEN Mask */
-
-#define SDH_CTL_CLKKEEP0_Pos (7) /*!< SDH CTL: CLKKEEP0 Position */
-#define SDH_CTL_CLKKEEP0_Msk (0x1ul << SDH_CTL_CLKKEEP0_Pos) /*!< SDH CTL: CLKKEEP0 Mask */
-
-#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH CTL: CMDCODE Position */
-#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH CTL: CMDCODE Mask */
-
-#define SDH_CTL_CTLRST_Pos (14) /*!< SDH CTL: CTLRST Position */
-#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH CTL: CTLRST Mask */
-
-#define SDH_CTL_DBW_Pos (15) /*!< SDH CTL: DBW Position */
-#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH CTL: DBW Mask */
-
-#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH CTL: BLKCNT Position */
-#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH CTL: BLKCNT Mask */
-
-#define SDH_CTL_SDNWR_Pos (24) /*!< SDH CTL: SDNWR Position */
-#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH CTL: SDNWR Mask */
-
-#define SDH_CTL_SDPORT_Pos (29) /*!< SDH CTL: SDPORT Position */
-#define SDH_CTL_SDPORT_Msk (0x3ul << SDH_CTL_SDPORT_Pos) /*!< SDH CTL: SDPORT Mask */
-
-#define SDH_CTL_CLKKEEP1_Pos (31) /*!< SDH CTL: CLKKEEP1 Position */
-#define SDH_CTL_CLKKEEP1_Msk (0x1ul << SDH_CTL_CLKKEEP1_Pos) /*!< SDH CTL: CLKKEEP1 Mask */
-
-#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH CMDARG: ARGUMENT Position */
-#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH CMDARG: ARGUMENT Mask */
-
-#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH INTEN: BLKDIEN Position */
-#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH INTEN: BLKDIEN Mask */
-
-#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH INTEN: CRCIEN Position */
-#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH INTEN: CRCIEN Mask */
-
-#define SDH_INTEN_CDIEN0_Pos (8) /*!< SDH INTEN: CDIEN0 Position */
-#define SDH_INTEN_CDIEN0_Msk (0x1ul << SDH_INTEN_CDIEN0_Pos) /*!< SDH INTEN: CDIEN0 Mask */
-
-#define SDH_INTEN_CDIEN1_Pos (9) /*!< SDH INTEN: CDIEN1 Position */
-#define SDH_INTEN_CDIEN1_Msk (0x1ul << SDH_INTEN_CDIEN1_Pos) /*!< SDH INTEN: CDIEN1 Mask */
-
-#define SDH_INTEN_SDHOST0IEN_Pos (10) /*!< SDH INTSTS: SDHOST0IEN Position */
-#define SDH_INTEN_SDHOST0IEN_Msk (0x1ul << SDH_INTEN_SDHOST0IEN_Pos) /*!< SDH INTSTS: SDHOST0IEN Mask */
-
-#define SDH_INTEN_SDHOST1IEN_Pos (11) /*!< SDH INTSTS: SDHOST1IEN Position */
-#define SDH_INTEN_SDHOST1IEN_Msk (0x1ul << SDH_INTEN_SDHOST1IEN_Pos) /*!< SDH INTSTS: SDHOST1IEN Mask */
-
-#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH INTEN: RTOIEN Position */
-#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH INTEN: RTOIEN Mask */
-
-#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH INTEN: DITOIEN Position */
-#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH INTEN: DITOIEN Mask */
-
-#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH INTEN: WKIEN Position */
-#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH INTEN: WKIEN Mask */
-
-#define SDH_INTEN_CDSRC0_Pos (30) /*!< SDH INTEN: CDSRC0 Position */
-#define SDH_INTEN_CDSRC0_Msk (0x1ul << SDH_INTEN_CDSRC0_Pos) /*!< SDH INTEN: CDSRC0 Mask */
-
-#define SDH_INTEN_CDSRC1_Pos (31) /*!< SDH INTEN: CDSRC1 Position */
-#define SDH_INTEN_CDSRC1_Msk (0x1ul << SDH_INTEN_CDSRC1_Pos) /*!< SDH INTEN: CDSRC1 Mask */
-
-#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH INTSTS: BLKDIF Position */
-#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH INTSTS: BLKDIF Mask */
-
-#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH INTSTS: CRCIF Position */
-#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH INTSTS: CRCIF Mask */
-
-#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH INTSTS: CRC7 Position */
-#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH INTSTS: CRC7 Mask */
-
-#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH INTSTS: CRC16 Position */
-#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH INTSTS: CRC16 Mask */
-
-#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH INTSTS: CRCSTS Position */
-#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH INTSTS: CRCSTS Mask */
-
-#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH INTSTS: DAT0STS Position */
-#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH INTSTS: DAT0STS Mask */
-
-#define SDH_INTSTS_CDIF0_Pos (8) /*!< SDH INTSTS: CDIF0 Position */
-#define SDH_INTSTS_CDIF0_Msk (0x1ul << SDH_INTSTS_CDIF0_Pos) /*!< SDH INTSTS: CDIF0 Mask */
-
-#define SDH_INTSTS_CDIF1_Pos (9) /*!< SDH INTSTS: CDIF1 Position */
-#define SDH_INTSTS_CDIF1_Msk (0x1ul << SDH_INTSTS_CDIF1_Pos) /*!< SDH INTSTS: CDIF1 Mask */
-
-#define SDH_INTSTS_SDHOST0IF_Pos (10) /*!< SDH INTSTS: SDHOST0IF Position */
-#define SDH_INTSTS_SDHOST0IF_Msk (0x1ul << SDH_INTSTS_SDHOST0IF_Pos) /*!< SDH INTSTS: SDHOST0IF Mask */
-
-#define SDH_INTSTS_SDHOST1IF_Pos (11) /*!< SDH INTSTS: SDHOST1IF Position */
-#define SDH_INTSTS_SDHOST1IF_Msk (0x1ul << SDH_INTSTS_SDHOST1IF_Pos) /*!< SDH INTSTS: SDHOST1IF Mask */
-
-#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH INTSTS: RTOIF Position */
-#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH INTSTS: RTOIF Mask */
-
-#define SDH_INTSTS_DINTOIF_Pos (13) /*!< SDH INTSTS: DINTOIF Position */
-#define SDH_INTSTS_DINTOIF_Msk (0x1ul << SDH_INTSTS_DINTOIF_Pos) /*!< SDH INTSTS: DINTOIF Mask */
-
-#define SDH_INTSTS_CDSTS0_Pos (16) /*!< SDH INTSTS: CDSTS0 Position */
-#define SDH_INTSTS_CDSTS0_Msk (0x1ul << SDH_INTSTS_CDSTS0_Pos) /*!< SDH INTSTS: CDSTS0 Mask */
-
-#define SDH_INTSTS_CDSTS1_Pos (17) /*!< SDH INTSTS: CDSTS1 Position */
-#define SDH_INTSTS_CDSTS1_Msk (0x1ul << SDH_INTSTS_CDSTS1_Pos) /*!< SDH INTSTS: CDSTS1 Mask */
-
-#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH INTSTS: DAT1STS Position */
-#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH INTSTS: DAT1STS Mask */
-
-#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH RESP0: RESPTK0 Position */
-#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH RESP0: RESPTK0 Mask */
-
-#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH RESP1: RESPTK1 Position */
-#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH RESP1: RESPTK1 Mask */
-
-#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH BLEN: BLKLEN Position */
-#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH BLEN: BLKLEN Mask */
-
-#define SDH_TOUT_TOUT_Pos (0) /*!< SDH TOUT: TOUT Position */
-#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH TOUT: TOUT Mask */
-
-/**@}*/ /* SDH_CONST */
-/**@}*/ /* end of SDH register group */
-
-
-/*---------------------- Serial Peripheral Interface Controller -------------------------*/
-/**
- @addtogroup SPI Serial Peripheral Interface Controller(SPI)
- Memory Mapped Structure for SPI Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 SPI Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SPIEN |SPI Transfer Control Enable Control
- * | | |0 = Transfer control Disabled.
- * | | |1 = Transfer control Enabled.
- * | | |Note1: In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
- * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
- * | | |Note2: All configurations should be set before writing 1 to this SPIEN bit.
- * | | |(eg: TXNEG, RXNEG, DWIDTH, LSB, CLKPOL, and so on).
- * |[1] |RXNEG |Receive On Negative Edge
- * | | |0 = Received data input signal is latched on the rising edge of SPICLK.
- * | | |1 = Received data input signal is latched on the falling edge of SPICLK.
- * |[2] |TXNEG |Transmit On Negative Edge
- * | | |0 = Transmitted data output signal is changed on the rising edge of SPICLK.
- * | | |1 = Transmitted data output signal is changed on the falling edge of SPICLK.
- * |[3] |CLKPOL |Clock Polarity
- * | | |0 = SPICLK is idle low.
- * | | |1 = SPICLK is idle high.
- * |[4:7] |SUSPITV |Suspend Interval (Master Only)
- * | | |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
- * | | |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
- * | | |......
- * | | |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
- * | | |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
- * | | |Note: The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
- * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
- * | | |The default value is 0x3.
- * | | |The period of the suspend interval is obtained according to the following equation.
- * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
- * |[8:12] |DWIDTH |Data Transmit Bit Width
- * | | |This field specifies how many bits can be transmitted / received in one transaction.
- * | | |The minimum bit length is 8 bits and can up to 32 bits.
- * | | |DWIDTH = 0x08 ... 8 bits.
- * | | |DWIDTH = 0x09 ... 9 bits.
- * | | |......
- * | | |DWIDTH = 0x1F ... 31 bits.
- * | | |DWIDTH = 0x00 ... 32 bits.
- * |[13] |LSB |Send LSB First
- * | | |0 = MSB first.
- * | | |1 = LSB first.
- * | | |Note1: The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
- * | | |Note2: The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
- * |[16] |TWOBIT |2-Bit Mode Enable Control
- * | | |0 = 2-bit mode Disabled.
- * | | |1 = 2-bit mode Enabled.
- * | | |Note: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
- * | | |serial transmitted bit data is from the second FIFO buffer data.
- * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
- * |[17] |UNITIEN |Unit Transfer Interrupt Enable Control
- * | | |0 = SPI unit transfer interrupt Disabled.
- * | | |1 = SPI unit transfer interrupt Enabled.
- * |[18] |SLAVE |Slave Mode Enable Control
- * | | |0 = Master mode.
- * | | |1 = Slave mode.
- * |[19] |REORDER |Byte Reorder Function Enable Control
- * | | |0 = Byte reorder function Disabled.
- * | | |1 = Byte reorder function Enabled.
- * | | |Note1: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
- * | | |Note2: The byte reorder function is not supported when the Quad or Dual I/O mode is enabled.
- * | | |Note3: A byte suspend interval will be inserted among each byte.
- * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
- * |[20] |QDIODIR |Quad Or Dual I/O Mode Direction Control
- * | | |0 = Quad or Dual Input mode.
- * | | |1 = Quad or Dual Output mode.
- * |[21] |DUALIOEN |Dual I/O Mode Enable Control
- * | | |0 = Dual I/O mode Disabled.
- * | | |1 = Dual I/O mode Enabled.
- * |[22] |QUADIOEN |Quad I/O Mode Enable Control
- * | | |0 = Quad I/O mode Disabled.
- * | | |1 = Quad I/O mode Enabled.
- */
- __IO uint32_t CTL;
-
- /**
- * CLKDIV
- * ===================================================================================================
- * Offset: 0x04 SPI Clock Divider Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DIVIDER |Clock Divider Register
- * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
- * | | |The frequency is obtained according to the following equation.
- * | | |Note1: is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
- * | | |Note2: is the peripheral clock which is used to drive the SPI logic unit.
- */
- __IO uint32_t CLKDIV;
-
- /**
- * SSCTL
- * ===================================================================================================
- * Offset: 0x08 SPI Slave Select Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |SS |Slave Select Control (Master Only)
- * | | |If AUTOSS bit is cleared to 0,
- * | | |0 = Set the SPI_SS line to inactive state.
- * | | |1 = Set the proper SPI_SS line to active state.
- * | | |If AUTOSS bit is set to 1,
- * | | |0 = Keep the SPI_SS line at inactive state.
- * | | |1 = Select the SPI_SS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time.
- * | | |The active state of SPI_SS is specified in SSACTPOL bit.
- * | | |Note: SPI_SS0 is defined as the slave select input in Slave mode.
- * |[2] |SSACTPOL |Slave Select Active Level
- * | | |0 = The slave select signal SPI_SS0/1 is active on low-level.
- * | | |1 = The slave select signal SPI_SS0/1 is active on high-level.
- * | | |Note: This bit defines the active status of slave select signal (SPI_SS0/1).
- * |[3] |AUTOSS |Automatic Slave Select Function Enable Control (Master Only)
- * | | |0 = Automatic slave select function Disabled.
- * | | |1 = Automatic slave select function Enabled.
- * | | |Note1: If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSCTL[1:0].
- * | | |Note2: If this bit is set, SPI_SS0/1 signals will be generated automatically.
- * | | |It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
- * |[4] |SLV3WIRE |Slave 3-Wire Mode Enable Control
- * | | |0 = 4-wire bi-direction interface.
- * | | |1 = 3-wire bi-direction interface.
- * | | |Note: This is used to ignore the slave select signal in Slave mode.
- * | | |The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.
- * |[5] |SLVTOIEN |Slave Mode Time-Out Interrupt Enable Control
- * | | |0 = Slave mode time-out interrupt Disabled.
- * | | |1 = Slave mode time-out interrupt Enabled.
- * |[6] |SLVTORST |Slave Mode Time-Out FIFO Clear
- * | | |0 = Time out FIFO clear Disabled.
- * | | |1 = Time out FIFO clear Enabled.
- * | | |Note: Both the FIFO clear function, TX_CLK and RXRST, active automatically when there is slave mode time-out event.
- * |[8] |SLVBEIEN |Slave Mode Error 0 Interrupt Enable Control
- * | | |0 = Slave mode error 0 interrupt Disabled.
- * | | |1 = Slave mode error 0 interrupt Enabled.
- * |[9] |SLVURIEN |Slave Mode Error 1 Interrupt Enable Control
- * | | |0 = Slave mode error 1 interrupt Disabled.
- * | | |1 = Slave mode error 1 interrupt Enabled.
- * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Control
- * | | |0 = Slave select active interrupt Disabled.
- * | | |1 = Slave select active interrupt Enabled.
- * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Control
- * | | |0 = Slave select inactive interrupt Disabled.
- * | | |1 = Slave select inactive interrupt Enabled.
- * |[16:31] |SLVTOCNT |Slave Mode Time-Out Period
- * | | |0 = Slave time out function disabled.
- * | | |Others = Slave time out period.
- * | | |Note: In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
- * | | |The clock source of the time-out counter is Slave peripheral clock.
- * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
- */
- __IO uint32_t SSCTL;
-
- /**
- * PDMACTL
- * ===================================================================================================
- * Offset: 0x0C SPI PDMA Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TXPDMAEN |Transmit DMA Enable Control
- * | | |0 = Transmit PDMA Disabled.
- * | | |1 = Transmit PDMA Enabled.
- * | | |Note: Setting this bit to 1 will start the transmit PDMA process.
- * | | |SPI controller will issue request to PDMA controller automatically.
- * | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
- * |[1] |RXPDMAEN |Receive PDMA Enable Control
- * | | |0 = Receive PDMA Disabled.
- * | | |1 = Receive PDMA Enabled.
- * | | |Note: Setting this bit to 1 will start the receive PDMA process.
- * | | |The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty.
- * | | |This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.
- * |[2] |PDMARST |PDMA Reset
- * | | |0 = No effect.
- * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically.
- */
- __IO uint32_t PDMACTL;
-
- /**
- * FIFOCTL
- * ===================================================================================================
- * Offset: 0x10 SPI FIFO Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXRST |Clear Receive FIFO Buffer
- * | | |0 = No effect.
- * | | |1 = Clear receive FIFO buffer.
- * | | |Note1: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled.
- * | | |Note2: The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
- * | | |This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1.
- * |[1] |TXRST |Clear Transmit FIFO Buffer
- * | | |0 = No effect.
- * | | |1 = Clear transmit FIFO buffer.
- * | | |Note1: If there is slave receive time-out event, the TXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled.
- * | | |Note2: The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
- * | | |This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1.
- * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Control
- * | | |0 = RX FIFO threshold interrupt Disabled.
- * | | |1 = RX FIFO threshold interrupt Enabled.
- * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Control
- * | | |0 = TX FIFO threshold interrupt Disabled.
- * | | |1 = TX FIFO threshold interrupt Enabled.
- * |[4] |RXTOIEN |Slave Receive Time-Out Interrupt Enable Control (Slave Only)
- * | | |0 = Receive time-out interrupt Disabled.
- * | | |1 = Receive time-out interrupt Enabled.
- * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Control
- * | | |0 = Receive FIFO overrun interrupt Disabled.
- * | | |1 = Receive FIFO overrun interrupt Enabled.
- * |[6] |TXUFPOL |Transmit Under-Run Data Out (Slave Only)
- * | | |0 = The SPI data bus is keep low if there is transmit under-run event.
- * | | |1 = The SPI data bus is keep high if there is transmit under-run event.
- * | | |Note1: The under run event is activated after the bus clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the peripheral clock) data out will be the last transaction data.
- * | | |Note2: If the frequency of system clock approach to peripheral clock, they may need 3-bit time to report the transmit under-run event.
- * |[7] |TXUFIEN |Transmit Under Run Interrupt Enable Control (Slave Only)
- * | | |0 = Transmit FIFO under-run interrupt Disabled.
- * | | |1 = Transmit FIFO under-run interrupt Enabled.
- * |[24:26] |RXTH |Receive FIFO Threshold
- * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
- * |[28:30] |TXTH |Transmit FIFO Threshold
- * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
- */
- __IO uint32_t FIFOCTL;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x14 SPI Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUSY |Busy Status (Read Only)
- * | | |0 = SPI controller is in Idle state.
- * | | |1 = SPI controller is in busy state.
- * | | |The following listing are the bus busy conditions:
- * | | |*. SPIEN = 1 and the TXEMPTY = 0.
- * | | |*. For SPI Master, the TXEMPTY = 1 but the current transaction is not finished yet.
- * | | |*. For SPI Slave receive mode, the SPIEN = 1 and there is serial clock input into the SPI core logic when slave select is active.
- * | | |*. For SPI Slave transmit mode, the SPIEN = 1 and the transmit buffer is not empty in SPI core logic even if the slave select is inactive.
- * |[1] |UNITIF |Unit Transfer Interrupt Status
- * | | |0 = No transaction has been finished since this bit was cleared to 0.
- * | | |1 = SPI controller has finished one unit transfer.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[2] |SSACTIF |Slave Select Active Interrupt Status
- * | | |0 = Slave select active interrupt is clear or not occur.
- * | | |1 = Slave select active interrupt event occurred.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[3] |SSINAIF |Slave Select Inactive Interrupt Status
- * | | |0 = Slave select inactive interrupt is clear or not occur.
- * | | |1 = Slave select inactive interrupt event occurred.
- * | | |Note: This bit will be cleared by writing 1 to it.
- * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
- * | | |0 = Indicates the slave select line bus status is 0.
- * | | |1 = Indicates the slave select line bus status is 1.
- * | | |Note: If SSACTPOL, SPI_SSCTL[2], is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
- * |[5] |SLVTOIF |Slave Time-Out Interrupt Status
- * | | |0 = Slave time-out is not active.
- * | | |1 = Slave time-out is active.
- * | | |Note1: If the DWIDTH is set 16, one transaction is equal 16 bits bus clock period.
- * | | |This bit will be cleared by writing 1 to it.
- * | | |Note2: When the Slave Select is active and the value of SLVTOCNT is not 0 and the busclock input, the slave time-out counter in SPI controller logic will be start.
- * | | |When the value of time-out counter greater or equal than the value of SLVTOCNT, SPI_SSCTL[31:16], during before one transaction done, the slave time-out interrupt event will active.
- * |[6] |SLVBEIF |Slave Mode Error 0 Interrupt Status
- * | | |0 = No Slave mode error 0 event.
- * | | |1 = Slave mode error 0 occurs.
- * | | |Note1: If the slave select active but there is no any bus clock input, the SLVER0_INTSTS also active when the slave select goes to inactive state.
- * | | |This bit will be cleared by writing 1 to it.
- * | | |Note2: In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.
- * |[7] |SLVURIF |Slave Mode Error 1 Interrupt Status
- * | | |0 = No Slave mode error 1 event.
- * | | |1 = Slave mode error 1 occurs.
- * | | |Note: In Slave mode, transmit under-run occurs when the slave select line goes to inactive state.
- * | | |This bit will be cleared by writing 1 to it.
- * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
- * | | |0 = Receive FIFO buffer is not empty.
- * | | |1 = Receive FIFO buffer is empty.
- * |[9] |RXFULL |Receive FIFO Buffer Empty Indicator (Read Only)
- * | | |0 = Receive FIFO buffer is not empty.
- * | | |1 = Receive FIFO buffer is empty.
- * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Status (Read Only)
- * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
- * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
- * | | |Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt request.
- * |[11] |RXOVIF |Receive FIFO Overrun Status
- * | | |0 = No FIFO over-run event.
- * | | |1 = FIFO over-run event occurred.
- * | | |Note: When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
- * | | |This bit will be cleared by writing 1 to it.
- * |[12] |RXTOIF |Receive Time-Out Interrupt Status
- * | | |0 = No receive FIFO time-out event.
- * | | |1 = FIFO time-out event occurred.
- * | | |Note: Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
- * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
- * | | |This bit will be cleared by writing 1 to it.
- * |[15] |SPIENSTS |SPI Enable Bit Status (Read Only)
- * | | |0 = Indicates the transmit control bit is disabled.
- * | | |1 = Indicates the transfer control bit is active.
- * | | |Note: The clock source of SPI controller logic is peripheral clock, it is asynchronous with the system clock.
- * | | |In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user.
- * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
- * | | |0 = Transmit FIFO buffer is not empty.
- * | | |1 = Transmit FIFO buffer is empty.
- * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
- * | | |0 = Transmit FIFO buffer is not full.
- * | | |1 = Transmit FIFO buffer is full.
- * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Status (Read Only)
- * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
- * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
- * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
- * |[19] |TXUFIF |Transmit FIFO Under-Run Interrupt Status
- * | | |0 =No under-run interrupt event.
- * | | |1 = Under-run interrupt occurred.
- * | | |Note: When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input , the output data depends on the setting of SLVUDFPOL and this bit will be set to 1 and this bit will be cleared by writing 1 to it.
- * |[23] |TXRXRST |FIFO CLR Status (Read Only)
- * | | |0 = Done the FIFO buffer clear function of TXRST or RXRST.
- * | | |1 = Doing the FIFO buffer clear function of TXRST or RXRST.
- * | | |Note: Both the TXRST, RXRST, need 3 system clock + 3 peripheral clock , the status of this bit support the user to monitor the clear function is doing or done.
- * |[24:27] |RXCNT |Receive FIFO Data Count (Read Only)
- * | | |This bit field indicates the valid data count of receive FIFO buffer.
- * |[28:31] |TXCNT |Transmit FIFO Data Count (Read Only)
- * | | |This bit field indicates the valid data count of transmit FIFO buffer.
- */
- __IO uint32_t STATUS;
- uint32_t RESERVE0[2];
-
-
- /**
- * TX
- * ===================================================================================================
- * Offset: 0x20 SPI Data Transmit Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |TX |Data Transmit Bits
- * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer.
- * | | |The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.
- * | | |In Master mode, the serial data in SPI bus output need 5 module clock cycle when the data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer.
- * | | |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
- * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
- */
- __O uint32_t TX;
- uint32_t RESERVE1[3];
-
-
- /**
- * RX
- * ===================================================================================================
- * Offset: 0x30 SPI Data Receive Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |RX |Data Receive Bits
- * | | |There is 8-level FIFO buffer in this controller.
- * | | |The data receive register holds the earliest datum received from SPI data input pin.
- * | | |If the RXEMPTY bit, SPI_STATUS[8], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register.
- * | | |This is a read only register.
- */
- __I uint32_t RX;
-
-} SPI_T;
-
-/**
- @addtogroup SPI_CONST SPI Bit Field Definition
- Constant Definitions for SPI Controller
-@{ */
-
-#define SPI_CTL_SPIEN_Pos (0) /*!< SPI CTL: SPIEN Position */
-#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI CTL: SPIEN Mask */
-
-#define SPI_CTL_RXNEG_Pos (1) /*!< SPI CTL: RXNEG Position */
-#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI CTL: RXNEG Mask */
-
-#define SPI_CTL_TXNEG_Pos (2) /*!< SPI CTL: TXNEG Position */
-#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI CTL: TXNEG Mask */
-
-#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI CTL: CLKPOL Position */
-#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI CTL: CLKPOL Mask */
-
-#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI CTL: SUSPITV Position */
-#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI CTL: SUSPITV Mask */
-
-#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI CTL: DWIDTH Position */
-#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI CTL: DWIDTH Mask */
-
-#define SPI_CTL_LSB_Pos (13) /*!< SPI CTL: LSB Position */
-#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI CTL: LSB Mask */
-
-#define SPI_CTL_TWOBIT_Pos (16) /*!< SPI CTL: TWOBIT Position */
-#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI CTL: TWOBIT Mask */
-
-#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI CTL: UNITIEN Position */
-#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI CTL: UNITIEN Mask */
-
-#define SPI_CTL_SLAVE_Pos (18) /*!< SPI CTL: SLAVE Position */
-#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI CTL: SLAVE Mask */
-
-#define SPI_CTL_REORDER_Pos (19) /*!< SPI CTL: REORDER Position */
-#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI CTL: REORDER Mask */
-
-#define SPI_CTL_QDIODIR_Pos (20) /*!< SPI CTL: QDIODIR Position */
-#define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /*!< SPI CTL: QDIODIR Mask */
-
-#define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI CTL: DUALIOEN Position */
-#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI CTL: DUALIOEN Mask */
-
-#define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI CTL: QUADIOEN Position */
-#define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI CTL: QUADIOEN Mask */
-
-#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI CLKDIV: DIVIDER Position */
-#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI CLKDIV: DIVIDER Mask */
-
-#define SPI_SSCTL_SS_Pos (0) /*!< SPI SSCTL: SS Position */
-#define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos) /*!< SPI SSCTL: SS Mask */
-
-#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI SSCTL: SSACTPOL Position */
-#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI SSCTL: SSACTPOL Mask */
-
-#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI SSCTL: AUTOSS Position */
-#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI SSCTL: AUTOSS Mask */
-
-#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI SSCTL: SLV3WIRE Position */
-#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI SSCTL: SLV3WIRE Mask */
-
-#define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI SSCTL: SLVTOIEN Position */
-#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI SSCTL: SLVTOIEN Mask */
-
-#define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI SSCTL: SLVTORST Position */
-#define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI SSCTL: SLVTORST Mask */
-
-#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI SSCTL: SLVBEIEN Position */
-#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI SSCTL: SLVBEIEN Mask */
-
-#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI SSCTL: SLVURIEN Position */
-#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI SSCTL: SLVURIEN Mask */
-
-#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI SSCTL: SSACTIEN Position */
-#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI SSCTL: SSACTIEN Mask */
-
-#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI SSCTL: SSINAIEN Position */
-#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI SSCTL: SSINAIEN Mask */
-
-#define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI SSCTL: SLVTOCNT Position */
-#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI SSCTL: SLVTOCNT Mask */
-
-#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI PDMACTL: TXPDMAEN Position */
-#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI PDMACTL: TXPDMAEN Mask */
-
-#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI PDMACTL: RXPDMAEN Position */
-#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI PDMACTL: RXPDMAEN Mask */
-
-#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI PDMACTL: PDMARST Position */
-#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI PDMACTL: PDMARST Mask */
-
-#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI FIFOCTL: RXRST Position */
-#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI FIFOCTL: RXRST Mask */
-
-#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI FIFOCTL: TXRST Position */
-#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI FIFOCTL: TXRST Mask */
-
-#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI FIFOCTL: RXTHIEN Position */
-#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI FIFOCTL: RXTHIEN Mask */
-
-#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI FIFOCTL: TXTHIEN Position */
-#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI FIFOCTL: TXTHIEN Mask */
-
-#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI FIFOCTL: RXTOIEN Position */
-#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI FIFOCTL: RXTOIEN Mask */
-
-#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI FIFOCTL: RXOVIEN Position */
-#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI FIFOCTL: RXOVIEN Mask */
-
-#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI FIFOCTL: TXUFPOL Position */
-#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI FIFOCTL: TXUFPOL Mask */
-
-#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI FIFOCTL: TXUFIEN Position */
-#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI FIFOCTL: TXUFIEN Mask */
-
-#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI FIFOCTL: RXTH Position */
-#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI FIFOCTL: RXTH Mask */
-
-#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI FIFOCTL: TXTH Position */
-#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI FIFOCTL: TXTH Mask */
-
-#define SPI_STATUS_BUSY_Pos (0) /*!< SPI STATUS: BUSY Position */
-#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI STATUS: BUSY Mask */
-
-#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI STATUS: UNITIF Position */
-#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI STATUS: UNITIF Mask */
-
-#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI STATUS: SSACTIF Position */
-#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI STATUS: SSACTIF Mask */
-
-#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI STATUS: SSINAIF Position */
-#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI STATUS: SSINAIF Mask */
-
-#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI STATUS: SSLINE Position */
-#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI STATUS: SSLINE Mask */
-
-#define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI STATUS: SLVTOIF Position */
-#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI STATUS: SLVTOIF Mask */
-
-#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI STATUS: SLVBEIF Position */
-#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI STATUS: SLVBEIF Mask */
-
-#define SPI_STATUS_SLVUDRIF_Pos (7) /*!< SPI STATUS: SLVUDRIF Position */
-#define SPI_STATUS_SLVUDRIF_Msk (0x1ul << SPI_STATUS_SLVUDRIF_Pos) /*!< SPI STATUS: SLVUDRIF Mask */
-
-#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI STATUS: RXEMPTY Position */
-#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI STATUS: RXEMPTY Mask */
-
-#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI STATUS: RXFULL Position */
-#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI STATUS: RXFULL Mask */
-
-#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI STATUS: RXTHIF Position */
-#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI STATUS: RXTHIF Mask */
-
-#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI STATUS: RXOVIF Position */
-#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI STATUS: RXOVIF Mask */
-
-#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI STATUS: RXTOIF Position */
-#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI STATUS: RXTOIF Mask */
-
-#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI STATUS: SPIENSTS Position */
-#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI STATUS: SPIENSTS Mask */
-
-#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI STATUS: TXEMPTY Position */
-#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI STATUS: TXEMPTY Mask */
-
-#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI STATUS: TXFULL Position */
-#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI STATUS: TXFULL Mask */
-
-#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI STATUS: TXTHIF Position */
-#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI STATUS: TXTHIF Mask */
-
-#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI STATUS: TXUFIF Position */
-#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI STATUS: TXUFIF Mask */
-
-#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI STATUS: TXRXRST Position */
-#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI STATUS: TXRXRST Mask */
-
-#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI STATUS: RXCNT Position */
-#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI STATUS: RXCNT Mask */
-
-#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI STATUS: TXCNT Position */
-#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI STATUS: TXCNT Mask */
-
-#define SPI_TX_TX_Pos (0) /*!< SPI TX: TX Position */
-#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI TX: TX Mask */
-
-#define SPI_RX_RX_Pos (0) /*!< SPI RX: RX Position */
-#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI RX: RX Mask */
-
-/**@}*/ /* SPI_CONST */
-/**@}*/ /* end of SPI register group */
-
-
-/*---------------------- System Manger Controller -------------------------*/
-/**
- @addtogroup SYS System Manger Controller(SYS)
- Memory Mapped Structure for SYS Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * PDID
- * ===================================================================================================
- * Offset: 0x00 Part Device Identification Number Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |SYS_PDID |Part Device Identification Number
- * | | |This register reflects device part number code.
- * | | |S/W can read this register to identify which device is used.
- */
- __I uint32_t PDID;
-
- /**
- * RSTSTS
- * ===================================================================================================
- * Offset: 0x04 System Reset Source Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PORF |The PORF Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Controller Or Bit CHIPRST (SYS_IPRST0[0]) To Indicate The Previous Reset Source
- * | | |0 = No reset from POR or CHIPRST.
- * | | |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[1] |PINRF |The PINRF Flag Is Set By The "Reset Signal" From The /RESET Pin To Indicate The Previous Reset Source
- * | | |0 = No reset from /RESET pin.
- * | | |1 = The Pin /RESET had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[2] |WDTRF |The WDTRF Flag Is Set By The "Reset Signal" From The Watchdog Timer To Indicate The Previous Reset Source
- * | | |0 = No reset from watchdog timer.
- * | | |1 = The watchdog timer had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |LVRF |The LVRF Flag Is Set By The "Reset Signal" From The Low-Voltage-Reset Controller To Indicate The Previous Reset Source
- * | | |0 = No reset from LVR.
- * | | |1 = The LVR controller had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |BODRF |The BODRF Flag Is Set By The "Reset Signal" From The Brown-Out-Detector To Indicate The Previous Reset Source
- * | | |0 = No reset from BOD.
- * | | |1 = The BOD had issued the reset signal to reset the system.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |SYSRF |The SYSRF Flag Is Set By The "Reset Signal" From The Cortex(TM)-M4 Core To Indicate The Previous Reset Source
- * | | |0 = No reset from Cortex(TM)-M4.
- * | | |1 = The Cortex(TM)-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex(TM)-M4 core.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |CPURF |The CPURF Flag Is Set By Hardware If Software Writes CPURST (SYS_IPRST0[1]) 1 To Reset Cortex(TM)-M4 Core And Flash Memory Controller (FMC)
- * | | |0 = No reset from CPU.
- * | | |1 = The Cortex(TM)-M4 Core and FMC are reset by software setting CPURST to 1.
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t RSTSTS;
-
- /**
- * IPRST0
- * ===================================================================================================
- * Offset: 0x08 Peripheral Controller Reset Control Register 1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CHIPRST |Chip One-Shot Reset (Write Protect)
- * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
- * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
- * | | |This bit is a write protected bit, which means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = Chip normal operation.
- * | | |1 = Chip one shot reset.
- * |[1] |CPURST |Processor Core One-Shot Reset (Write Protect)
- * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = Processor core normal operation.
- * | | |1 = Processor core one-shot reset.
- * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the PDMA.
- * | | |User needs to set this bit to 0 to release from reset state.
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = PDMA controller normal operation.
- * | | |1 = PDMA controller reset.
- * |[3] |EBIRST |EBI Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the EBI.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = EBI controller normal operation.
- * | | |1 = EBI controller reset.
- * |[4] |USBHRST |UHC Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the HSB HOST controller.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = UHC controller normal operation.
- * | | |1 = UHC controller reset.
- * |[5] |SDHRST |EMAC Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = EMAC controller normal operation.
- * | | |1 = EMAC controller reset.
- * |[6] |SDHOST_RST|SD HOST Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the SD HOST controller.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = SD HOST controller normal operation.
- * | | |1 = SD HOST controller reset.
- * |[7] |CRCRST |CRC Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the CRC controller.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Reference the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = CRC controller normal operation.
- * | | |1 = CRC controller reset.
- * |[8] |CAPRST |Image Capture Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the CAP controller.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Reference the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = CAP controller normal operation.
- * | | |1 = CAP controller reset.
- * |[12] |CRPT_RST |CRYPTO Controller Reset (Write Protect)
- * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller.
- * | | |User needs to set this bit to 0 to release from the reset state.
- * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * | | |0 = CRYPTO controller normal operation.
- * | | |1 = CRYPTO controller reset.
- */
- __IO uint32_t IPRST0;
-
- /**
- * IPRST1
- * ===================================================================================================
- * Offset: 0x0C Peripheral Controller Reset Control Register 2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |GPIORST |GPIO Controller Reset
- * | | |0 = GPIO controller normal operation.
- * | | |1 = GPIO controller reset.
- * |[2] |TMR0RST |Timer0 Controller Reset
- * | | |0 = Timer0 controller normal operation.
- * | | |1 = Timer0 controller reset.
- * |[3] |TMR1RST |Timer1 Controller Reset
- * | | |0 = Timer1 controller normal operation.
- * | | |1 = Timer1 controller reset.
- * |[4] |TMR2RST |Timer2 Controller Reset
- * | | |0 = Timer2 controller normal operation.
- * | | |1 = Timer2 controller reset.
- * |[5] |TMR3RST |Timer3 Controller Reset
- * | | |0 = Timer3 controller normal operation.
- * | | |1 = Timer3 controller reset.
- * |[7] |ACMPRST |Analog Comparator Controller Reset
- * | | |0 = Analog Comparator controller normal operation.
- * | | |1 = Analog Comparator controller reset.
- * |[8] |I2C0RST |I2C0 Controller Reset
- * | | |0 = I2C0 controller normal operation.
- * | | |1 = I2C0 controller reset.
- * |[9] |I2C1RST |I2C1 Controller Reset
- * | | |0 = I2C1 controller normal operation.
- * | | |1 = I2C1 controller reset.
- * |[12] |SPI0RST |SPI0 Controller Reset
- * | | |0 = SPI0 controller normal operation.
- * | | |1 = SPI0 controller reset.
- * |[13] |SPI1RST |SPI1 Controller Reset
- * | | |0 = SPI1 controller normal operation.
- * | | |1 = SPI1 controller reset.
- * |[14] |SPI2RST |SPI2 Controller Reset
- * | | |0 = SPI2 controller normal operation.
- * | | |1 = SPI2 controller reset.
- * |[15] |SPI3RST |SPI3 Controller Reset
- * | | |0 = SPI3 controller normal operation.
- * | | |1 = SPI3 controller reset.
- * |[16] |UART0RST |UART0 Controller Reset
- * | | |0 = UART0 controller normal operation.
- * | | |1 = UART0 controller reset.
- * |[17] |UART1RST |UART1 Controller Reset
- * | | |0 = UART1 controller normal operation.
- * | | |1 = UART1 controller reset.
- * |[18] |UART2RST |UART2 Controller Reset
- * | | |0 = UART2 controller normal operation.
- * | | |1 = UART2 controller reset.
- * |[19] |UART3RST |UART3 Controller Reset
- * | | |0 = UART3 controller normal operation.
- * | | |1 = UART3 controller reset.
- * |[20] |UART4RST |UART4 Controller Reset
- * | | |0 = UART4 controller normal operation.
- * | | |1 = UART4 controller reset.
- * |[21] |UART5RST |UART2 Controller Reset
- * | | |0 = UART5 controller normal operation.
- * | | |1 = UART5 controller reset.
- * |[24] |CAN0RST |CAN0 Controller Reset
- * | | |0 = CAN0 controller normal operation.
- * | | |1 = CAN0 controller reset.
- * |[25] |CAN1RST |CAN1 Controller Reset
- * | | |0 = CAN1 controller normal operation.
- * | | |1 = CAN1 controller reset.
- * |[27] |USBDRST |USB Device Controller Reset
- * | | |0 = USB device controller normal operation.
- * | | |1 = USB device controller reset.
- * |[28] |ADCRST |ADC Controller Reset
- * | | |0 = ADC controller normal operation.
- * | | |1 = ADC controller reset.
- * |[29] |I2SRST |I2S Controller Reset
- * | | |0 = I2S controller normal operation.
- * | | |1 = I2S controller reset.
- * |[30] |I2S1RST |I2S1 Controller Reset
- * | | |0 = I2S1 controller normal operation.
- * | | |1 = I2S1 controller reset.
- * |[31] |PS2RST |PS/2 Controller Reset
- * | | |0 = PS/2 controller normal operation.
- * | | |1 = PS/2 controller reset.
- */
- __IO uint32_t IPRST1;
-
- /**
- * IPRST2
- * ===================================================================================================
- * Offset: 0x10 Peripheral Controller Reset Control Register 3
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SC0RST |SC0 Controller Reset
- * | | |0 = SC0 controller normal operation.
- * | | |1 = SC0 controller reset.
- * |[1] |SC1RST |SC1 Controller Reset
- * | | |0 = SC1 controller normal operation.
- * | | |1 = SC1 controller reset.
- * |[2] |SC2RST |SC2 Controller Reset
- * | | |0 = SC2 controller normal operation.
- * | | |1 = SC2 controller reset.
- * |[3] |SC3RST |SC3 Controller Reset
- * | | |0 = SC3 controller normal operation.
- * | | |1 = SC3 controller reset.
- * |[4] |SC4RST |SC4 Controller Reset
- * | | |0 = SC4 controller normal operation.
- * | | |1 = SC4 controller reset.
- * |[5] |SC5RST |SC5 Controller Reset
- * | | |0 = SC5 controller normal operation.
- * | | |1 = SC5 controller reset.
- * |[8] |I2C4RST |I2C4 Controller Reset
- * | | |0 = I2C4 controller normal operation.
- * | | |1 = I2C4 controller reset.
- * |[16] |PWM0RST |PWM0 Controller Reset
- * | | |0 = PWM0 controller normal operation.
- * | | |1 = PWM0 controller reset.
- * |[17] |PWM1RST |PWM1 Controller Reset
- * | | |0 = PWM1 controller normal operation.
- * | | |1 = PWM1 controller reset.
- * |[22] |QEI0RST |QEI0 Controller Reset
- * | | |0 = QEI0 controller normal operation.
- * | | |1 = QEI0 controller reset.
- * |[23] |QEI1RST |QEI1 Controller Reset
- * | | |0 = QEI1 controller normal operation.
- * | | |1 = QEI1 controller reset.
- */
- __IO uint32_t IPRST2;
- uint32_t RESERVE0[1];
-
-
- /**
- * BODCTL
- * ===================================================================================================
- * Offset: 0x18 Brown-out Detector Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BODEN |Brown-Out Detector Enable Control (Write Protect)
- * | | |The default value is set by flash controller user configuration register config0 bit[23]
- * | | |0 = Brown-out Detector function Disabled.
- * | | |1 = Brown-out Detector function Enabled.
- * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * |[1:2] |BODVL |Brown-Out Detector Threshold Voltage Selection (Write Protect)
- * | | |The default value is set by flash controller user configuration register config0 bit[22:21]
- * | | |Relationship between BODVL and Brown-out voltage listed below:
- * | | |00 = 2.2V.
- * | | |01 = 2.7V.
- * | | |10 = 3.8V.
- * | | |11 = 4.5V.
- * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * |[3] |BODRSTEN |Brown-Out Reset Enable Control (Write Protect)
- * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
- * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
- * | | |BOD interrupt will keep till to the BODEN set to 0.
- * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
- * | | |The default value is set by flash controller user configuration register config0 bit[20].
- * | | |0 = Brown-out "INTERRUPT" function Enabled.
- * | | |1 = Brown-out "RESET" function Enabled.
- * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * |[4] |BODINTF |Brown-Out Detector Interrupt Flag
- * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
- * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |BODLPM |Brown-Out Detector Low Power Mode (Write Protect)
- * | | |The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
- * | | |0 = BOD operate in normal mode (default).
- * | | |1 = BOD Low Power mode Enabled.
- * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- * |[6] |BODOUT |Brown-Out Detector Output Status
- * | | |0 = Brown-out Detector output status is 0.
- * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
- * | | |1 = Brown-out Detector output status is 1.
- * | | |It means the detected voltage is lower than BODVL setting.
- * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
- * |[7] |LVREN |Low Voltage Reset Enable Control (Write Protect)
- * | | |The LVR function reset the chip when the input power voltage is lower than LVR circuit setting.
- * | | |LVR function is enabled in default.
- * | | |0 = Low Voltage Reset function Disabled.
- * | | |1 = Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (default).
- * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- */
- __IO uint32_t BODCTL;
-
- /**
- * TEMPCTL
- * ===================================================================================================
- * Offset: 0x1C Temperature Sensor Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |VTEMPEN |Temperature Sensor Enable Control
- * | | |This bit is used to enable/disable temperature sensor function.
- * | | |0 = Temperature sensor function Disabled (default).
- * | | |1 = Temperature sensor function Enabled.
- * | | |After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
- * | | |Please refer to ADC function chapter for details.
- */
- __IO uint32_t TEMPCTL;
-
- /**
- * VCID
- * ===================================================================================================
- * Offset: 0x20 Hardware Version Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |VCID |Hardware Version Control (Ready Only)
- * | | |These registers repress hardware version.
- * | | |These bits are the read protected bits.
- * | | |It means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- */
- __I uint32_t VCID;
-
- /**
- * PORCTL
- * ===================================================================================================
- * Offset: 0x24 Power-On-Reset Controller Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |POROFF |Power-On-Reset Enable Control (Write Protect)
- * | | |When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
- * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
- * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
- * | | |/RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
- * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
- * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
- */
- __IO uint32_t PORCTL;
-
- /**
- * VREFCTL
- * ===================================================================================================
- * Offset: 0x28 ADC VREF Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:4] |VREFCTL |Vref control bits (Write Protect)
- * | | |00011=Vref is internal 2.65V
- * | | |00111=Vref is internal 2.048V
- * | | |01011=Vref is internal 3.072V
- * | | |01111=Vref is internal 4.096V
- * | | |10000=Vref is from AVDD
- * | | |Others=Reserved
- * |[8] |ADCMODESEL|ADC IP Selection (Write Protect)
- * | | |0 = ADC mode.
- * | | |1 = E ADC mode.
- * |[9] |PWMSYNCMODE|PWM SYNC MODE (Write Protect)
- * | | |0 = PWM SYNC MODE Disabled; PWM engine clock can different with HCLK.
- * | | |1 = PWM SYNC MODE Enabled; PWM engine clock is same as HCLK.
- */
- __IO uint32_t VREFCTL;
-
- /**
- * USBPHY
- * ===================================================================================================
- * Offset: 0x2C USB PHY Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |USBROLE |USB Role Configuration (Write Protect)
- * | | |USB role configuration can be from ROMMAP or software setting if software setting option, controlled by ROMMAP, is enabled.
- * | | |00 = Standard USB device.
- * | | |01 = Standard USB host.
- * | | |10 = ID dependent device.
- * | | |11 = On-The-Go device.
- * |[8] |LDO33EN |LDO33 Enable Control (Write Protect)
- * | | |0 = USB LDO33 Disabled.
- * | | |1 = USB LDO33 Enabled.
- */
- __IO uint32_t USBPHY;
-
- /**
- * GPA_MFPL
- * ===================================================================================================
- * Offset: 0x30 Port A Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PA0MFP |PA.0 Multi-function Pin Selection
- * |[4:7] |PA1MFP |PA.1 Multi-function Pin Selection
- * |[8:11] |PA2MFP |PA.2 Multi-function Pin Selection
- * |[12:15] |PA3MFP |PA.3 Multi-function Pin Selection
- * |[16:19] |PA4MFP |PA.4 Multi-function Pin Selection
- * |[20:23] |PA5MFP |PA.5 Multi-function Pin Selection
- * |[24:27] |PA6MFP |PA.6 Multi-function Pin Selection
- * |[28:31] |PA7MFP |PA.7 Multi-function Pin Selection
- */
- __IO uint32_t GPA_MFPL;
-
- /**
- * GPA_MFPH
- * ===================================================================================================
- * Offset: 0x34 Port A High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PA8MFP |PA.8 Multi-function Pin Selection
- * |[4:7] |PA9MFP |PA.9 Multi-function Pin Selection
- * |[8:11] |PA10MFP |PA.10 Multi-function Pin Selection
- * |[12:15] |PA11MFP |PA.11 Multi-function Pin Selection
- * |[16:19] |PA12MFP |PA.12 Multi-function Pin Selection
- * |[20:23] |PA13MFP |PA.13 Multi-function Pin Selection
- * |[24:27] |PA14MFP |PA.14 Multi-function Pin Selection
- * |[28:31] |PA15MFP |PA.15 Multi-function Pin Selection
- */
- __IO uint32_t GPA_MFPH;
-
- /**
- * GPB_MFPL
- * ===================================================================================================
- * Offset: 0x38 Port B Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PB0MFP |PB.0 Multi-function Pin Selection
- * |[4:7] |PB1MFP |PB.1 Multi-function Pin Selection
- * |[8:11] |PB2MFP |PB.2 Multi-function Pin Selection
- * |[12:15] |PB3MFP |PB.3 Multi-function Pin Selection
- * |[16:19] |PB4MFP |PB.4 Multi-function Pin Selection
- * |[20:23] |PB5MFP |PB.5 Multi-function Pin Selection
- * |[24:27] |PB6MFP |PB.6 Multi-function Pin Selection
- * |[28:31] |PB7MFP |PB.7 Multi-function Pin Selection
- */
- __IO uint32_t GPB_MFPL;
-
- /**
- * GPB_MFPH
- * ===================================================================================================
- * Offset: 0x3C Port B High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PB8MFP |PB.8 Multi-function Pin Selection
- * |[4:7] |PB9MFP |PB.9 Multi-function Pin Selection
- * |[8:11] |PB10MFP |PB.10 Multi-function Pin Selection
- * |[12:15] |PB11MFP |PB.11 Multi-function Pin Selection
- * |[16:19] |PB12MFP |PB.12 Multi-function Pin Selection
- * |[20:23] |PB13MFP |PB.13 Multi-function Pin Selection
- * |[24:27] |PB14MFP |PB.14 Multi-function Pin Selection
- * |[28:31] |PB15MFP |PB.15 Multi-function Pin Selection
- */
- __IO uint32_t GPB_MFPH;
-
- /**
- * GPC_MFPL
- * ===================================================================================================
- * Offset: 0x40 Port C Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PC0MFP |PC.0 Multi-function Pin Selection
- * |[4:7] |PC1MFP |PC.1 Multi-function Pin Selection
- * |[8:11] |PC2MFP |PC.2 Multi-function Pin Selection
- * |[12:15] |PC3MFP |PC.3 Multi-function Pin Selection
- * |[16:19] |PC4MFP |PC.4 Multi-function Pin Selection
- * |[20:23] |PC5MFP |PC.5 Multi-function Pin Selection
- * |[24:27] |PC6MFP |PC.6 Multi-function Pin Selection
- * |[28:31] |PC7MFP |PC.7 Multi-function Pin Selection
- */
- __IO uint32_t GPC_MFPL;
-
- /**
- * GPC_MFPH
- * ===================================================================================================
- * Offset: 0x44 Port C High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PC8MFP |PC.8 Multi-function Pin Selection
- * |[4:7] |PC9MFP |PC.9 Multi-function Pin Selection
- * |[8:11] |PC10MFP |PC.10 Multi-function Pin Selection
- * |[12:15] |PC11MFP |PC.11 Multi-function Pin Selection
- * |[16:19] |PC12MFP |PC.12 Multi-function Pin Selection
- * |[20:23] |PC13MFP |PC.13 Multi-function Pin Selection
- * |[24:27] |PC14MFP |PC.14 Multi-function Pin Selection
- * |[28:31] |PC15MFP |PC.15 Multi-function Pin Selection
- */
- __IO uint32_t GPC_MFPH;
-
- /**
- * GPD_MFPL
- * ===================================================================================================
- * Offset: 0x48 Port D Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PD0MFP |PD.0 Multi-function Pin Selection
- * |[4:7] |PD1MFP |PD.1 Multi-function Pin Selection
- * |[8:11] |PD2MFP |PD.2 Multi-function Pin Selection
- * |[12:15] |PD3MFP |PD.3 Multi-function Pin Selection
- * |[16:19] |PD4MFP |PD.4 Multi-function Pin Selection
- * |[20:23] |PD5MFP |PD.5 Multi-function Pin Selection
- * |[24:27] |PD6MFP |PD.6 Multi-function Pin Selection
- * |[28:31] |PD7MFP |PD.7 Multi-function Pin Selection
- */
- __IO uint32_t GPD_MFPL;
-
- /**
- * GPD_MFPH
- * ===================================================================================================
- * Offset: 0x4C Port D High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PD8MFP |PD.8 Multi-function Pin Selection
- * |[4:7] |PD9MFP |PD.9 Multi-function Pin Selection
- * |[8:11] |PD10MFP |PD.10 Multi-function Pin Selection
- * |[12:15] |PD11MFP |PD.11 Multi-function Pin Selection
- * |[16:19] |PD12MFP |PD.12 Multi-function Pin Selection
- * |[20:23] |PD13MFP |PD.13 Multi-function Pin Selection
- * |[24:27] |PD14MFP |PD.14 Multi-function Pin Selection
- * |[28:31] |PD15MFP |PD.15 Multi-function Pin Selection
- */
- __IO uint32_t GPD_MFPH;
-
- /**
- * GPE_MFPL
- * ===================================================================================================
- * Offset: 0x50 Port E Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PE0MFP |PE.0 Multi-function Pin Selection
- * |[4:7] |PE1MFP |PE.1 Multi-function Pin Selection
- * |[8:11] |PE2MFP |PE.2 Multi-function Pin Selection
- * |[12:15] |PE3MFP |PE.3 Multi-function Pin Selection
- * |[16:19] |PE4MFP |PE.4 Multi-function Pin Selection
- * |[20:23] |PE5MFP |PE.5 Multi-function Pin Selection
- * |[24:27] |PE6MFP |PE.6 Multi-function Pin Selection
- * |[28:31] |PE7MFP |PE.7 Multi-function Pin Selection
- */
- __IO uint32_t GPE_MFPL;
-
- /**
- * GPE_MFPH
- * ===================================================================================================
- * Offset: 0x54 Port E High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PE8MFP |PE.8 Multi-function Pin Selection
- * |[4:7] |PE9MFP |PE.9 Multi-function Pin Selection
- * |[8:11] |PE10MFP |PE.10 Multi-function Pin Selection
- * |[12:15] |PE11MFP |PE.11 Multi-function Pin Selection
- * |[16:19] |PE12MFP |PE.12 Multi-function Pin Selection
- * |[20:23] |PE13MFP |PE.13 Multi-function Pin Selection
- * |[24:27] |PE14MFP |PE.14 Multi-function Pin Selection
- * |[28:31] |PE15MFP |PE.15 Multi-function Pin Selection
- */
- __IO uint32_t GPE_MFPH;
-
- /**
- * GPF_MFPL
- * ===================================================================================================
- * Offset: 0x58 Port F Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PF0MFP |PF.0 Multi-function Pin Selection
- * |[4:7] |PF1MFP |PF.1 Multi-function Pin Selection
- * |[8:11] |PF2MFP |PF.2 Multi-function Pin Selection
- * |[12:15] |PF3MFP |PF.3 Multi-function Pin Selection
- * |[16:19] |PF4MFP |PF.4 Multi-function Pin Selection
- * |[20:23] |PF5MFP |PF.5 Multi-function Pin Selection
- * |[24:27] |PF6MFP |PF.6 Multi-function Pin Selection
- * |[28:31] |PF7MFP |PF.7 Multi-function Pin Selection
- */
- __IO uint32_t GPF_MFPL;
-
- /**
- * GPF_MFPH
- * ===================================================================================================
- * Offset: 0x5C Port F High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PF8MFP |PF.8 Multi-function Pin Selection
- * |[4:7] |PF9MFP |PF.9 Multi-function Pin Selection
- * |[8:11] |PF10MFP |PF.10 Multi-function Pin Selection
- * |[12:15] |PF11MFP |PF.11 Multi-function Pin Selection
- * |[16:19] |PF12MFP |PF.12 Multi-function Pin Selection
- * |[20:23] |PF13MFP |PF.13 Multi-function Pin Selection
- * |[24:27] |PF14MFP |PF.14 Multi-function Pin Selection
- * |[28:31] |PF15MFP |PF.15 Multi-function Pin Selection
- */
- __IO uint32_t GPF_MFPH;
-
- /**
- * GPG_MFPL
- * ===================================================================================================
- * Offset: 0x60 Port G Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PG0MFP |PG.0 Multi-function Pin Selection
- * |[4:7] |PG1MFP |PG.1 Multi-function Pin Selection
- * |[8:11] |PG2MFP |PG.2 Multi-function Pin Selection
- * |[12:15] |PG3MFP |PG.3 Multi-function Pin Selection
- * |[16:19] |PG4MFP |PG.4 Multi-function Pin Selection
- * |[20:23] |PG5MFP |PG.5 Multi-function Pin Selection
- * |[24:27] |PG6MFP |PG.6 Multi-function Pin Selection
- * |[28:31] |PG7MFP |PG.7 Multi-function Pin Selection
- */
- __IO uint32_t GPG_MFPL;
-
- /**
- * GPG_MFPH
- * ===================================================================================================
- * Offset: 0x64 Port G High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PG8MFP |PG.8 Multi-function Pin Selection
- * |[4:7] |PG9MFP |PG.9 Multi-function Pin Selection
- * |[8:11] |PG10MFP |PG.10 Multi-function Pin Selection
- * |[12:15] |PG11MFP |PG.11 Multi-function Pin Selection
- * |[16:19] |PG12MFP |PG.12 Multi-function Pin Selection
- * |[20:23] |PG13MFP |PG.13 Multi-function Pin Selection
- * |[24:27] |PG14MFP |PG.14 Multi-function Pin Selection
- * |[28:31] |PG15MFP |PG.15 Multi-function Pin Selection
- */
- __IO uint32_t GPG_MFPH;
-
- /**
- * GPH_MFPL
- * ===================================================================================================
- * Offset: 0x68 Port H Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PH0MFP |PH.0 Multi-function Pin Selection
- * |[4:7] |PH1MFP |PH.1 Multi-function Pin Selection
- * |[8:11] |PH2MFP |PH.2 Multi-function Pin Selection
- * |[12:15] |PH3MFP |PH.3 Multi-function Pin Selection
- * |[16:19] |PH4MFP |PH.4 Multi-function Pin Selection
- * |[20:23] |PH5MFP |PH.5 Multi-function Pin Selection
- * |[24:27] |PH6MFP |PH.6 Multi-function Pin Selection
- * |[28:31] |PH7MFP |PH.7 Multi-function Pin Selection
- */
- __IO uint32_t GPH_MFPL;
-
- /**
- * GPH_MFPH
- * ===================================================================================================
- * Offset: 0x6C Port H High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PH8MFP |PH.8 Multi-function Pin Selection
- * |[4:7] |PH9MFP |PH.9 Multi-function Pin Selection
- * |[8:11] |PH10MFP |PH.10 Multi-function Pin Selection
- * |[12:15] |PH11MFP |PH.11 Multi-function Pin Selection
- * |[16:19] |PH12MFP |PH.12 Multi-function Pin Selection
- * |[20:23] |PH13MFP |PH.13 Multi-function Pin Selection
- * |[24:27] |PH14MFP |PH.14 Multi-function Pin Selection
- * |[28:31] |PH15MFP |PH.15 Multi-function Pin Selection
- */
- __IO uint32_t GPH_MFPH;
-
- /**
- * GPI_MFPL
- * ===================================================================================================
- * Offset: 0x70 Port I Low Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PI0MFP |PI.0 Multi-function Pin Selection
- * |[4:7] |PI1MFP |PI.1 Multi-function Pin Selection
- * |[8:11] |PI2MFP |PI.2 Multi-function Pin Selection
- * |[12:15] |PI3MFP |PI.3 Multi-function Pin Selection
- * |[16:19] |PI4MFP |PI.4 Multi-function Pin Selection
- * |[20:23] |PI5MFP |PI.5 Multi-function Pin Selection
- * |[24:27] |PI6MFP |PI.6 Multi-function Pin Selection
- * |[28:31] |PI7MFP |PI.7 Multi-function Pin Selection
- */
- __IO uint32_t GPI_MFPL;
-
- /**
- * GPI_MFPH
- * ===================================================================================================
- * Offset: 0x74 Port I High Byte Multi-function Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |PI8MFP |PI.8 Multi-function Pin Selection
- * |[4:7] |PI9MFP |PI.9 Multi-function Pin Selection
- * |[8:11] |PI10MFP |PI.10 Multi-function Pin Selection
- * |[12:15] |PI11MFP |PI.11 Multi-function Pin Selection
- * |[16:19] |PI12MFP |PI.12 Multi-function Pin Selection
- * |[20:23] |PI13MFP |PI.13 Multi-function Pin Selection
- * |[24:27] |PI14MFP |PI.14 Multi-function Pin Selection
- * |[28:31] |PI15MFP |PI.15 Multi-function Pin Selection
- */
- __IO uint32_t GPI_MFPH;
- uint32_t RESERVE1[18];
-
-
- /**
- * SRAM_INTCTL
- * ===================================================================================================
- * Offset: 0xC0 SRAM Failed Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PERRIEN |SRAM Parity Check Fail Interrupt Enable Control
- * | | |0 = SRAMF INT Disabled.
- * | | |1 = SRAMF INT Enabled when SRAM fail flag.
- */
- __IO uint32_t SRAM_INTCTL;
-
- /**
- * SRAM_STATUS
- * ===================================================================================================
- * Offset: 0xC4 SRAM Parity Check Error Flag
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |PERRIF0 |SRAM Parity Check Fail Flag
- * | | |0 = No first 1 SRAM fail.
- * | | |1 = First SRAM Fail.
- * |[1] |PERRIF1 |SRAM Parity Check Fail Flag
- * | | |0 = 2nd SRAM fail.
- * | | |1 = 2nd SRAM Fail.
- */
- __IO uint32_t SRAM_STATUS;
-
- /**
- * SRAM0_ERRADDR
- * ===================================================================================================
- * Offset: 0xC8 SRAM Parity Check Error First Address1
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |PERRADDR |First SRAM parity check fail address
- */
- __I uint32_t SRAM0_ERRADDR;
-
- /**
- * SRAM1_ERRADDR
- * ===================================================================================================
- * Offset: 0xCC SRAM Parity Check Error First Address2
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |PERRADDR |2nd
- * | | |SRAM parity check fail address
- */
- __I uint32_t SRAM1_ERRADDR;
- uint32_t RESERVE2[8];
-
-
- /**
- * IRCTCTL
- * ===================================================================================================
- * Offset: 0xF0 IRC Trim Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |FREQSEL |Trim Frequency Selection
- * | | |This field indicates the target frequency of HIRC auto trim.
- * | | |If no any target frequency is selected (FREQSEL is 00), the HIRC auto trim function is disabled.
- * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
- * | | |00 = Disable HIRC auto trim function.
- * | | |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
- * | | |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
- * | | |11 = Reserved.
- * |[4:5] |LOOPSEL |Trim Calculation Loop
- * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
- * | | |For example, if CALCLOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
- * | | |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
- * | | |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
- * | | |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
- * | | |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
- * |[6:7] |RETRYCNT |Trim Value Update Limitation Count
- * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
- * | | |Once the HIRC locked, the internal trim value update counter will be reset.
- * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
- * | | |00 = Trim retry count limitation is 64.
- * | | |01 = Trim retry count limitation is 128.
- * | | |10 = Trim retry count limitation is 256.
- * | | |11 = Trim retry count limitation is 512.
- * |[8] |CESTOPEN |Clock Error Stop Enable Control
- * | | |0 = The trim operation is keep going if clock is inaccuracy.
- * | | |1 = The trim operation is stopped if clock is inaccuracy.
- */
- __IO uint32_t IRCTCTL;
-
- /**
- * IRCTIEN
- * ===================================================================================================
- * Offset: 0xF4 IRC Trim Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |TFAILIEN |Trim Failure Interrupt Enable
- * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL.
- * | | |If this bit is high and TFAILIF is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
- * | | |0 = Disable TFAILIF status to trigger an interrupt to CPU.
- * | | |1 = Enable TFAILIF status to trigger an interrupt to CPU.
- * |[2] |CLKEIEN |Clock Error Interrupt Enable Control
- * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
- * | | |If this bit is set to1, and CLKERRIF is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
- * | | |0 = Disable CLKERRIF status to trigger an interrupt to CPU.
- * | | |1 = Enable CLKERRIF status to trigger an interrupt to CPU.
- */
- __IO uint32_t IRCTIEN;
-
- /**
- * IRCTISTS
- * ===================================================================================================
- * Offset: 0xF8 IRC Trim Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FREQLOCK |HIRC Frequency Lock Status
- * | | |This bit indicates the HIRC frequency is locked.
- * | | |This is a status bit and doesn't trigger any interrupt.
- * |[1] |TFAILIF |Trim Failure Interrupt Status
- * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked.
- * | | |Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically.
- * | | |If this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
- * | | |Write 1 to clear this to 0.
- * | | |0 = Trim value update limitation count does not reach.
- * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.
- * |[2] |CLKERRIF |Clock Error Interrupt Status
- * | | |When the frequency of external 32.768 kHz low-speed crystal or HIRC is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
- * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically if CESTOPEN is set to 1.
- * | | |If this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
- * | | |Write 1 to clear this to 0.
- * | | |0 = Clock frequency is accuracy.
- * | | |1 = Clock frequency is inaccuracy.
- */
- __IO uint32_t IRCTISTS;
- uint32_t RESERVE3[1];
-
-
- /**
- * REGLCTL
- * ===================================================================================================
- * Offset: 0x100 Register Write-Protection Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |REGLCTL |Register Write-Protection Disable Index (Read Only)
- * | | |0 = Write-protection Enabled for writing protected registers.
- * | | |Any write to the protected register is ignored.
- * | | |1 = Write-protection Disabled for writing protected registers.
- * | | |The Protected registers are:
- * | | |SYS_IPRST0: address 0x4000_0008
- * | | |SYS_BODCTL: address 0x4000_0018
- * | | |SYS_PORCTL: address 0x4000_0024
- * | | |PWRCON: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
- * | | |APBCLK bit[0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
- * | | |CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
- * | | |CLKSEL1 bit[1:0]: address 0x4000_0214 (for watchdog clock source select)
- * | | |NMI_SEL]: address 0x4000_0300 (for NMI source select)
- * | | |ISPCON: address 0x4000_5000 (Flash ISP Control register)
- * | | |ISPTRG: address 0x4000_5010 (ISP Trigger Control register)
- * | | |WTCR: address 0x4004_0000
- * | | |FATCON: address 0x4000_5018
- * | | |TAMPER: address 0x400E_1000
- * |[0:7] |SYS_REGLCTL|Register Write-Protection Code (Write Only)
- * | | |Some registers have write-protection function.
- * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
- * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
- */
- __IO uint32_t REGLCTL;
-
-} SYS_T;
-
-/**
- @addtogroup SYS_CONST SYS Bit Field Definition
- Constant Definitions for SYS Controller
-@{ */
-
-#define SYS_PDID_SYS_PDID_Pos (0) /*!< SYS PDID: SYS_PDID Position */
-#define SYS_PDID_SYS_PDID_Msk (0xfffffffful << SYS_PDID_SYS_PDID_Pos) /*!< SYS PDID: SYS_PDID Mask */
-
-#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS RSTSTS: PORF Position */
-#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS RSTSTS: PORF Mask */
-
-#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS RSTSTS: PINRF Position */
-#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS RSTSTS: PINRF Mask */
-
-#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS RSTSTS: WDTRF Position */
-#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS RSTSTS: WDTRF Mask */
-
-#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS RSTSTS: LVRF Position */
-#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS RSTSTS: LVRF Mask */
-
-#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS RSTSTS: BODRF Position */
-#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS RSTSTS: BODRF Mask */
-
-#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS RSTSTS: SYSRF Position */
-#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS RSTSTS: SYSRF Mask */
-
-#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS RSTSTS: CPURF Position */
-#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS RSTSTS: CPURF Mask */
-
-#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS IPRST0: CHIPRST Position */
-#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS IPRST0: CHIPRST Mask */
-
-#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS IPRST0: CPURST Position */
-#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS IPRST0: CPURST Mask */
-
-#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS IPRST0: PDMARST Position */
-#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS IPRST0: PDMARST Mask */
-
-#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS IPRST0: EBIRST Position */
-#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS IPRST0: EBIRST Mask */
-
-#define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS IPRST0: USBHRST Position */
-#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS IPRST0: USBHRST Mask */
-
-#define SYS_IPRST0_SDHRST_Pos (5) /*!< SYS IPRST0: SDHRST Position */
-#define SYS_IPRST0_SDHRST_Msk (0x1ul << SYS_IPRST0_SDHRST_Pos) /*!< SYS IPRST0: SDHRST Mask */
-
-#define SYS_IPRST0_SDHOST_RST_Pos (6) /*!< SYS IPRST0: SDHOST_RST Position */
-#define SYS_IPRST0_SDHOST_RST_Msk (0x1ul << SYS_IPRST0_SDHOST_RST_Pos) /*!< SYS IPRST0: SDHOST_RST Mask */
-
-#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS IPRST0: CRCRST Position */
-#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS IPRST0: CRCRST Mask */
-
-#define SYS_IPRST0_CAPRST_Pos (8) /*!< SYS IPRST0: CAPRST Position */
-#define SYS_IPRST0_CAPRST_Msk (0x1ul << SYS_IPRST0_CAPRST_Pos) /*!< SYS IPRST0: CAPRST Mask */
-
-#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS IPRST0: CRPTRST Position */
-#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS IPRST0: CRPTRST Mask */
-
-#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS IPRST1: GPIORST Position */
-#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS IPRST1: GPIORST Mask */
-
-#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS IPRST1: TMR0RST Position */
-#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS IPRST1: TMR0RST Mask */
-
-#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS IPRST1: TMR1RST Position */
-#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS IPRST1: TMR1RST Mask */
-
-#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS IPRST1: TMR2RST Position */
-#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS IPRST1: TMR2RST Mask */
-
-#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS IPRST1: TMR3RST Position */
-#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS IPRST1: TMR3RST Mask */
-
-#define SYS_IPRST1_ACMPRST_Pos (7) /*!< SYS IPRST1: ACMPRST Position */
-#define SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos) /*!< SYS IPRST1: ACMPRST Mask */
-
-#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS IPRST1: I2C0RST Position */
-#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS IPRST1: I2C0RST Mask */
-
-#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS IPRST1: I2C1RST Position */
-#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS IPRST1: I2C1RST Mask */
-
-#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS IPRST1: I2C2RST Position */
-#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS IPRST1: I2C2RST Mask */
-
-#define SYS_IPRST1_I2C3RST_Pos (11) /*!< SYS IPRST1: I2C3RST Position */
-#define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) /*!< SYS IPRST1: I2C3RST Mask */
-
-#define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS IPRST1: SPI0RST Position */
-#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS IPRST1: SPI0RST Mask */
-
-#define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS IPRST1: SPI1RST Position */
-#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS IPRST1: SPI1RST Mask */
-
-#define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS IPRST1: SPI2RST Position */
-#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS IPRST1: SPI2RST Mask */
-
-#define SYS_IPRST1_SPI3RST_Pos (15) /*!< SYS IPRST1: SPI3RST Position */
-#define SYS_IPRST1_SPI3RST_Msk (0x1ul << SYS_IPRST1_SPI3RST_Pos) /*!< SYS IPRST1: SPI3RST Mask */
-
-#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS IPRST1: UART0RST Position */
-#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS IPRST1: UART0RST Mask */
-
-#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS IPRST1: UART1RST Position */
-#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS IPRST1: UART1RST Mask */
-
-#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS IPRST1: UART2RST Position */
-#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS IPRST1: UART2RST Mask */
-
-#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS IPRST1: UART3RST Position */
-#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS IPRST1: UART3RST Mask */
-
-#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS IPRST1: UART4RST Position */
-#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS IPRST1: UART4RST Mask */
-
-#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS IPRST1: UART5RST Position */
-#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS IPRST1: UART5RST Mask */
-
-#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS IPRST1: CAN0RST Position */
-#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS IPRST1: CAN0RST Mask */
-
-#define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS IPRST1: CAN1RST Position */
-#define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS IPRST1: CAN1RST Mask */
-
-#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS IPRST1: USBDRST Position */
-#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS IPRST1: USBDRST Mask */
-
-#define SYS_IPRST1_ADCRST_Pos (28) /*!< SYS IPRST1: ADCRST Position */
-#define SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos) /*!< SYS IPRST1: ADCRST Mask */
-
-#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS IPRST1: I2SRST Position */
-#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS IPRST1: I2SRST Mask */
-
-#define SYS_IPRST1_I2S1RST_Pos (30) /*!< SYS IPRST1: I2S1RST Position */
-#define SYS_IPRST1_I2S1RST_Msk (0x1ul << SYS_IPRST1_I2S1RST_Pos) /*!< SYS IPRST1: I2S1RST Mask */
-
-#define SYS_IPRST1_PS2RST_Pos (31) /*!< SYS IPRST1: PS2RST Position */
-#define SYS_IPRST1_PS2RST_Msk (0x1ul << SYS_IPRST1_PS2RST_Pos) /*!< SYS IPRST1: PS2RST Mask */
-
-#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS IPRST2: SC0RST Position */
-#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS IPRST2: SC0RST Mask */
-
-#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS IPRST2: SC1RST Position */
-#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS IPRST2: SC1RST Mask */
-
-#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS IPRST2: SC2RST Position */
-#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS IPRST2: SC2RST Mask */
-
-#define SYS_IPRST2_SC3RST_Pos (3) /*!< SYS IPRST2: SC3RST Position */
-#define SYS_IPRST2_SC3RST_Msk (0x1ul << SYS_IPRST2_SC3RST_Pos) /*!< SYS IPRST2: SC3RST Mask */
-
-#define SYS_IPRST2_SC4RST_Pos (4) /*!< SYS IPRST2: SC4RST Position */
-#define SYS_IPRST2_SC4RST_Msk (0x1ul << SYS_IPRST2_SC4RST_Pos) /*!< SYS IPRST2: SC4RST Mask */
-
-#define SYS_IPRST2_SC5RST_Pos (5) /*!< SYS IPRST2: SC5RST Position */
-#define SYS_IPRST2_SC5RST_Msk (0x1ul << SYS_IPRST2_SC5RST_Pos) /*!< SYS IPRST2: SC5RST Mask */
-
-#define SYS_IPRST2_I2C4RST_Pos (8) /*!< SYS IPRST2: I2C4RST Position */
-#define SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos) /*!< SYS IPRST2: I2C4RST Mask */
-
-#define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS IPRST2: PWM0RST Position */
-#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS IPRST2: PWM0RST Mask */
-
-#define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS IPRST2: PWM1RST Position */
-#define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS IPRST2: PWM1RST Mask */
-
-#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS IPRST2: QEI0RST Position */
-#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS IPRST2: QEI0RST Mask */
-
-#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS IPRST2: QEI1RST Position */
-#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS IPRST2: QEI1RST Mask */
-
-#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS BODCTL: BODEN Position */
-#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS BODCTL: BODEN Mask */
-
-#define SYS_BODCTL_BODVL_Pos (1) /*!< SYS BODCTL: BODVL Position */
-#define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /*!< SYS BODCTL: BODVL Mask */
-
-#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS BODCTL: BODRSTEN Position */
-#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS BODCTL: BODRSTEN Mask */
-
-#define SYS_BODCTL_BODINTF_Pos (4) /*!< SYS BODCTL: BODINTF Position */
-#define SYS_BODCTL_BODINTF_Msk (0x1ul << SYS_BODCTL_BODINTF_Pos) /*!< SYS BODCTL: BODINTF Mask */
-
-#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS BODCTL: BODLPM Position */
-#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS BODCTL: BODLPM Mask */
-
-#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS BODCTL: BODOUT Position */
-#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS BODCTL: BODOUT Mask */
-
-#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS BODCTL: LVREN Position */
-#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS BODCTL: LVREN Mask */
-
-#define SYS_TEMPCTL_VTEMPEN_Pos (0) /*!< SYS TEMPCTL: VTEMPEN Position */
-#define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) /*!< SYS TEMPCTL: VTEMPEN Mask */
-
-#define SYS_VCID_VCID_Pos (0) /*!< SYS VCID: VCID Position */
-#define SYS_VCID_VCID_Msk (0xfffful << SYS_VCID_VCID_Pos) /*!< SYS VCID: VCID Mask */
-
-#define SYS_PORCTL_POROFF_Pos (0) /*!< SYS PORCTL: POROFF Position */
-#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS PORCTL: POROFF Mask */
-
-#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS VREFCTL: VREFCTL Position */
-#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS VREFCTL: VREFCTL Mask */
-
-#define SYS_VREFCTL_ADCMODESEL_Pos (8) /*!< SYS VREFCTL: ADCMODESEL Position */
-#define SYS_VREFCTL_ADCMODESEL_Msk (0x1ul << SYS_VREFCTL_ADCMODESEL_Pos) /*!< SYS VREFCTL: ADCMODESEL Mask */
-
-#define SYS_VREFCTL_PWMSYNCMODE_Pos (9) /*!< SYS VREFCTL: PWMSYNCMODE Position */
-#define SYS_VREFCTL_PWMSYNCMODE_Msk (0x1ul << SYS_VREFCTL_PWMSYNCMODE_Pos) /*!< SYS VREFCTL: PWMSYNCMODE Mask */
-
-#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS USBPHY: USBROLE Position */
-#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS USBPHY: USBROLE Mask */
-
-#define SYS_USBPHY_LDO33EN_Pos (8) /*!< SYS USBPHY: LDO33EN Position */
-#define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /*!< SYS USBPHY: LDO33EN Mask */
-
-#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS GPA_MFPL: PA0MFP Position */
-#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS GPA_MFPL: PA0MFP Mask */
-
-#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS GPA_MFPL: PA1MFP Position */
-#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS GPA_MFPL: PA1MFP Mask */
-
-#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS GPA_MFPL: PA2MFP Position */
-#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS GPA_MFPL: PA2MFP Mask */
-
-#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS GPA_MFPL: PA3MFP Position */
-#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS GPA_MFPL: PA3MFP Mask */
-
-#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS GPA_MFPL: PA4MFP Position */
-#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS GPA_MFPL: PA4MFP Mask */
-
-#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS GPA_MFPL: PA5MFP Position */
-#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS GPA_MFPL: PA5MFP Mask */
-
-#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS GPA_MFPL: PA6MFP Position */
-#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS GPA_MFPL: PA6MFP Mask */
-
-#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS GPA_MFPL: PA7MFP Position */
-#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS GPA_MFPL: PA7MFP Mask */
-
-#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS GPA_MFPH: PA8MFP Position */
-#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS GPA_MFPH: PA8MFP Mask */
-
-#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS GPA_MFPH: PA9MFP Position */
-#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS GPA_MFPH: PA9MFP Mask */
-
-#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS GPA_MFPH: PA10MFP Position */
-#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS GPA_MFPH: PA10MFP Mask */
-
-#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS GPA_MFPH: PA11MFP Position */
-#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS GPA_MFPH: PA11MFP Mask */
-
-#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS GPA_MFPH: PA12MFP Position */
-#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS GPA_MFPH: PA12MFP Mask */
-
-#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS GPA_MFPH: PA13MFP Position */
-#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS GPA_MFPH: PA13MFP Mask */
-
-#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS GPA_MFPH: PA14MFP Position */
-#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS GPA_MFPH: PA14MFP Mask */
-
-#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS GPA_MFPH: PA15MFP Position */
-#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS GPA_MFPH: PA15MFP Mask */
-
-#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS GPB_MFPL: PB0MFP Position */
-#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS GPB_MFPL: PB0MFP Mask */
-
-#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS GPB_MFPL: PB1MFP Position */
-#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS GPB_MFPL: PB1MFP Mask */
-
-#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS GPB_MFPL: PB2MFP Position */
-#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS GPB_MFPL: PB2MFP Mask */
-
-#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS GPB_MFPL: PB3MFP Position */
-#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS GPB_MFPL: PB3MFP Mask */
-
-#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS GPB_MFPL: PB4MFP Position */
-#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS GPB_MFPL: PB4MFP Mask */
-
-#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS GPB_MFPL: PB5MFP Position */
-#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS GPB_MFPL: PB5MFP Mask */
-
-#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS GPB_MFPL: PB6MFP Position */
-#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS GPB_MFPL: PB6MFP Mask */
-
-#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS GPB_MFPL: PB7MFP Position */
-#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS GPB_MFPL: PB7MFP Mask */
-
-#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS GPB_MFPH: PB8MFP Position */
-#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS GPB_MFPH: PB8MFP Mask */
-
-#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS GPB_MFPH: PB9MFP Position */
-#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS GPB_MFPH: PB9MFP Mask */
-
-#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS GPB_MFPH: PB10MFP Position */
-#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS GPB_MFPH: PB10MFP Mask */
-
-#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS GPB_MFPH: PB11MFP Position */
-#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS GPB_MFPH: PB11MFP Mask */
-
-#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS GPB_MFPH: PB12MFP Position */
-#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS GPB_MFPH: PB12MFP Mask */
-
-#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS GPB_MFPH: PB13MFP Position */
-#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS GPB_MFPH: PB13MFP Mask */
-
-#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS GPB_MFPH: PB14MFP Position */
-#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS GPB_MFPH: PB14MFP Mask */
-
-#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS GPB_MFPH: PB15MFP Position */
-#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS GPB_MFPH: PB15MFP Mask */
-
-#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS GPC_MFPL: PC0MFP Position */
-#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS GPC_MFPL: PC0MFP Mask */
-
-#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS GPC_MFPL: PC1MFP Position */
-#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS GPC_MFPL: PC1MFP Mask */
-
-#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS GPC_MFPL: PC2MFP Position */
-#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS GPC_MFPL: PC2MFP Mask */
-
-#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS GPC_MFPL: PC3MFP Position */
-#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS GPC_MFPL: PC3MFP Mask */
-
-#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS GPC_MFPL: PC4MFP Position */
-#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS GPC_MFPL: PC4MFP Mask */
-
-#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS GPC_MFPL: PC5MFP Position */
-#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS GPC_MFPL: PC5MFP Mask */
-
-#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS GPC_MFPL: PC6MFP Position */
-#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS GPC_MFPL: PC6MFP Mask */
-
-#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS GPC_MFPL: PC7MFP Position */
-#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS GPC_MFPL: PC7MFP Mask */
-
-#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS GPC_MFPH: PC8MFP Position */
-#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS GPC_MFPH: PC8MFP Mask */
-
-#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS GPC_MFPH: PC9MFP Position */
-#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS GPC_MFPH: PC9MFP Mask */
-
-#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS GPC_MFPH: PC10MFP Position */
-#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS GPC_MFPH: PC10MFP Mask */
-
-#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS GPC_MFPH: PC11MFP Position */
-#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS GPC_MFPH: PC11MFP Mask */
-
-#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS GPC_MFPH: PC12MFP Position */
-#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS GPC_MFPH: PC12MFP Mask */
-
-#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS GPC_MFPH: PC13MFP Position */
-#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS GPC_MFPH: PC13MFP Mask */
-
-#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS GPC_MFPH: PC14MFP Position */
-#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS GPC_MFPH: PC14MFP Mask */
-
-#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS GPC_MFPH: PC15MFP Position */
-#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS GPC_MFPH: PC15MFP Mask */
-
-#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS GPD_MFPL: PD0MFP Position */
-#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS GPD_MFPL: PD0MFP Mask */
-
-#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS GPD_MFPL: PD1MFP Position */
-#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS GPD_MFPL: PD1MFP Mask */
-
-#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS GPD_MFPL: PD2MFP Position */
-#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS GPD_MFPL: PD2MFP Mask */
-
-#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS GPD_MFPL: PD3MFP Position */
-#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS GPD_MFPL: PD3MFP Mask */
-
-#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS GPD_MFPL: PD4MFP Position */
-#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS GPD_MFPL: PD4MFP Mask */
-
-#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS GPD_MFPL: PD5MFP Position */
-#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS GPD_MFPL: PD5MFP Mask */
-
-#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS GPD_MFPL: PD6MFP Position */
-#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS GPD_MFPL: PD6MFP Mask */
-
-#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS GPD_MFPL: PD7MFP Position */
-#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS GPD_MFPL: PD7MFP Mask */
-
-#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS GPD_MFPH: PD8MFP Position */
-#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS GPD_MFPH: PD8MFP Mask */
-
-#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS GPD_MFPH: PD9MFP Position */
-#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS GPD_MFPH: PD9MFP Mask */
-
-#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS GPD_MFPH: PD10MFP Position */
-#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS GPD_MFPH: PD10MFP Mask */
-
-#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS GPD_MFPH: PD11MFP Position */
-#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS GPD_MFPH: PD11MFP Mask */
-
-#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS GPD_MFPH: PD12MFP Position */
-#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS GPD_MFPH: PD12MFP Mask */
-
-#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS GPD_MFPH: PD13MFP Position */
-#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS GPD_MFPH: PD13MFP Mask */
-
-#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS GPD_MFPH: PD14MFP Position */
-#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS GPD_MFPH: PD14MFP Mask */
-
-#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS GPD_MFPH: PD15MFP Position */
-#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS GPD_MFPH: PD15MFP Mask */
-
-#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS GPE_MFPL: PE0MFP Position */
-#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS GPE_MFPL: PE0MFP Mask */
-
-#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS GPE_MFPL: PE1MFP Position */
-#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS GPE_MFPL: PE1MFP Mask */
-
-#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS GPE_MFPL: PE2MFP Position */
-#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS GPE_MFPL: PE2MFP Mask */
-
-#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS GPE_MFPL: PE3MFP Position */
-#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS GPE_MFPL: PE3MFP Mask */
-
-#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS GPE_MFPL: PE4MFP Position */
-#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS GPE_MFPL: PE4MFP Mask */
-
-#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS GPE_MFPL: PE5MFP Position */
-#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS GPE_MFPL: PE5MFP Mask */
-
-#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS GPE_MFPL: PE6MFP Position */
-#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS GPE_MFPL: PE6MFP Mask */
-
-#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS GPE_MFPL: PE7MFP Position */
-#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS GPE_MFPL: PE7MFP Mask */
-
-#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS GPE_MFPH: PE8MFP Position */
-#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS GPE_MFPH: PE8MFP Mask */
-
-#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS GPE_MFPH: PE9MFP Position */
-#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS GPE_MFPH: PE9MFP Mask */
-
-#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS GPE_MFPH: PE10MFP Position */
-#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS GPE_MFPH: PE10MFP Mask */
-
-#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS GPE_MFPH: PE11MFP Position */
-#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS GPE_MFPH: PE11MFP Mask */
-
-#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS GPE_MFPH: PE12MFP Position */
-#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS GPE_MFPH: PE12MFP Mask */
-
-#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS GPE_MFPH: PE13MFP Position */
-#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS GPE_MFPH: PE13MFP Mask */
-
-#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS GPE_MFPH: PE14MFP Position */
-#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS GPE_MFPH: PE14MFP Mask */
-
-#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS GPE_MFPH: PE15MFP Position */
-#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS GPE_MFPH: PE15MFP Mask */
-
-#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS GPF_MFPL: PF0MFP Position */
-#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS GPF_MFPL: PF0MFP Mask */
-
-#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS GPF_MFPL: PF1MFP Position */
-#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS GPF_MFPL: PF1MFP Mask */
-
-#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS GPF_MFPL: PF2MFP Position */
-#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS GPF_MFPL: PF2MFP Mask */
-
-#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS GPF_MFPL: PF3MFP Position */
-#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS GPF_MFPL: PF3MFP Mask */
-
-#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS GPF_MFPL: PF4MFP Position */
-#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS GPF_MFPL: PF4MFP Mask */
-
-#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS GPF_MFPL: PF5MFP Position */
-#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS GPF_MFPL: PF5MFP Mask */
-
-#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS GPF_MFPL: PF6MFP Position */
-#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS GPF_MFPL: PF6MFP Mask */
-
-#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS GPF_MFPL: PF7MFP Position */
-#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS GPF_MFPL: PF7MFP Mask */
-
-#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS GPF_MFPH: PF8MFP Position */
-#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS GPF_MFPH: PF8MFP Mask */
-
-#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS GPF_MFPH: PF9MFP Position */
-#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS GPF_MFPH: PF9MFP Mask */
-
-#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS GPF_MFPH: PF10MFP Position */
-#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS GPF_MFPH: PF10MFP Mask */
-
-#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS GPF_MFPH: PF11MFP Position */
-#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS GPF_MFPH: PF11MFP Mask */
-
-#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS GPF_MFPH: PF12MFP Position */
-#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS GPF_MFPH: PF12MFP Mask */
-
-#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS GPF_MFPH: PF13MFP Position */
-#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS GPF_MFPH: PF13MFP Mask */
-
-#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS GPF_MFPH: PF14MFP Position */
-#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS GPF_MFPH: PF14MFP Mask */
-
-#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS GPF_MFPH: PF15MFP Position */
-#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS GPF_MFPH: PF15MFP Mask */
-
-#define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS GPG_MFPL: PG0MFP Position */
-#define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS GPG_MFPL: PG0MFP Mask */
-
-#define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS GPG_MFPL: PG1MFP Position */
-#define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS GPG_MFPL: PG1MFP Mask */
-
-#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS GPG_MFPL: PG2MFP Position */
-#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS GPG_MFPL: PG2MFP Mask */
-
-#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS GPG_MFPL: PG3MFP Position */
-#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS GPG_MFPL: PG3MFP Mask */
-
-#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS GPG_MFPL: PG4MFP Position */
-#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS GPG_MFPL: PG4MFP Mask */
-
-#define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS GPG_MFPL: PG5MFP Position */
-#define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS GPG_MFPL: PG5MFP Mask */
-
-#define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS GPG_MFPL: PG6MFP Position */
-#define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS GPG_MFPL: PG6MFP Mask */
-
-#define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS GPG_MFPL: PG7MFP Position */
-#define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS GPG_MFPL: PG7MFP Mask */
-
-#define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS GPG_MFPH: PG8MFP Position */
-#define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS GPG_MFPH: PG8MFP Mask */
-
-#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS GPG_MFPH: PG9MFP Position */
-#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS GPG_MFPH: PG9MFP Mask */
-
-#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS GPG_MFPH: PG10MFP Position */
-#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS GPG_MFPH: PG10MFP Mask */
-
-#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS GPG_MFPH: PG11MFP Position */
-#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS GPG_MFPH: PG11MFP Mask */
-
-#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS GPG_MFPH: PG12MFP Position */
-#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS GPG_MFPH: PG12MFP Mask */
-
-#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS GPG_MFPH: PG13MFP Position */
-#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS GPG_MFPH: PG13MFP Mask */
-
-#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS GPG_MFPH: PG14MFP Position */
-#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS GPG_MFPH: PG14MFP Mask */
-
-#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS GPG_MFPH: PG15MFP Position */
-#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS GPG_MFPH: PG15MFP Mask */
-
-#define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS GPH_MFPL: PH0MFP Position */
-#define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS GPH_MFPL: PH0MFP Mask */
-
-#define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS GPH_MFPL: PH1MFP Position */
-#define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS GPH_MFPL: PH1MFP Mask */
-
-#define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS GPH_MFPL: PH2MFP Position */
-#define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS GPH_MFPL: PH2MFP Mask */
-
-#define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS GPH_MFPL: PH3MFP Position */
-#define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS GPH_MFPL: PH3MFP Mask */
-
-#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS GPH_MFPL: PH4MFP Position */
-#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS GPH_MFPL: PH4MFP Mask */
-
-#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS GPH_MFPL: PH5MFP Position */
-#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS GPH_MFPL: PH5MFP Mask */
-
-#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS GPH_MFPL: PH6MFP Position */
-#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS GPH_MFPL: PH6MFP Mask */
-
-#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS GPH_MFPL: PH7MFP Position */
-#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS GPH_MFPL: PH7MFP Mask */
-
-#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS GPH_MFPH: PH8MFP Position */
-#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS GPH_MFPH: PH8MFP Mask */
-
-#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS GPH_MFPH: PH9MFP Position */
-#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS GPH_MFPH: PH9MFP Mask */
-
-#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS GPH_MFPH: PH10MFP Position */
-#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS GPH_MFPH: PH10MFP Mask */
-
-#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS GPH_MFPH: PH11MFP Position */
-#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS GPH_MFPH: PH11MFP Mask */
-
-#define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS GPH_MFPH: PH12MFP Position */
-#define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS GPH_MFPH: PH12MFP Mask */
-
-#define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS GPH_MFPH: PH13MFP Position */
-#define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS GPH_MFPH: PH13MFP Mask */
-
-#define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS GPH_MFPH: PH14MFP Position */
-#define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS GPH_MFPH: PH14MFP Mask */
-
-#define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS GPH_MFPH: PH15MFP Position */
-#define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS GPH_MFPH: PH15MFP Mask */
-
-#define SYS_GPI_MFPL_PI0MFP_Pos (0) /*!< SYS GPI_MFPL: PI0MFP Position */
-#define SYS_GPI_MFPL_PI0MFP_Msk (0xful << SYS_GPI_MFPL_PI0MFP_Pos) /*!< SYS GPI_MFPL: PI0MFP Mask */
-
-#define SYS_GPI_MFPL_PI1MFP_Pos (4) /*!< SYS GPI_MFPL: PI1MFP Position */
-#define SYS_GPI_MFPL_PI1MFP_Msk (0xful << SYS_GPI_MFPL_PI1MFP_Pos) /*!< SYS GPI_MFPL: PI1MFP Mask */
-
-#define SYS_GPI_MFPL_PI2MFP_Pos (8) /*!< SYS GPI_MFPL: PI2MFP Position */
-#define SYS_GPI_MFPL_PI2MFP_Msk (0xful << SYS_GPI_MFPL_PI2MFP_Pos) /*!< SYS GPI_MFPL: PI2MFP Mask */
-
-#define SYS_GPI_MFPL_PI3MFP_Pos (12) /*!< SYS GPI_MFPL: PI3MFP Position */
-#define SYS_GPI_MFPL_PI3MFP_Msk (0xful << SYS_GPI_MFPL_PI3MFP_Pos) /*!< SYS GPI_MFPL: PI3MFP Mask */
-
-#define SYS_GPI_MFPL_PI4MFP_Pos (16) /*!< SYS GPI_MFPL: PI4MFP Position */
-#define SYS_GPI_MFPL_PI4MFP_Msk (0xful << SYS_GPI_MFPL_PI4MFP_Pos) /*!< SYS GPI_MFPL: PI4MFP Mask */
-
-#define SYS_GPI_MFPL_PI5MFP_Pos (20) /*!< SYS GPI_MFPL: PI5MFP Position */
-#define SYS_GPI_MFPL_PI5MFP_Msk (0xful << SYS_GPI_MFPL_PI5MFP_Pos) /*!< SYS GPI_MFPL: PI5MFP Mask */
-
-#define SYS_GPI_MFPL_PI6MFP_Pos (24) /*!< SYS GPI_MFPL: PI6MFP Position */
-#define SYS_GPI_MFPL_PI6MFP_Msk (0xful << SYS_GPI_MFPL_PI6MFP_Pos) /*!< SYS GPI_MFPL: PI6MFP Mask */
-
-#define SYS_GPI_MFPL_PI7MFP_Pos (28) /*!< SYS GPI_MFPL: PI7MFP Position */
-#define SYS_GPI_MFPL_PI7MFP_Msk (0xful << SYS_GPI_MFPL_PI7MFP_Pos) /*!< SYS GPI_MFPL: PI7MFP Mask */
-
-#define SYS_GPI_MFPH_PI8MFP_Pos (0) /*!< SYS GPI_MFPH: PI8MFP Position */
-#define SYS_GPI_MFPH_PI8MFP_Msk (0xful << SYS_GPI_MFPH_PI8MFP_Pos) /*!< SYS GPI_MFPH: PI8MFP Mask */
-
-#define SYS_GPI_MFPH_PI9MFP_Pos (4) /*!< SYS GPI_MFPH: PI9MFP Position */
-#define SYS_GPI_MFPH_PI9MFP_Msk (0xful << SYS_GPI_MFPH_PI9MFP_Pos) /*!< SYS GPI_MFPH: PI9MFP Mask */
-
-#define SYS_GPI_MFPH_PI10MFP_Pos (8) /*!< SYS GPI_MFPH: PI10MFP Position */
-#define SYS_GPI_MFPH_PI10MFP_Msk (0xful << SYS_GPI_MFPH_PI10MFP_Pos) /*!< SYS GPI_MFPH: PI10MFP Mask */
-
-#define SYS_GPI_MFPH_PI11MFP_Pos (12) /*!< SYS GPI_MFPH: PI11MFP Position */
-#define SYS_GPI_MFPH_PI11MFP_Msk (0xful << SYS_GPI_MFPH_PI11MFP_Pos) /*!< SYS GPI_MFPH: PI11MFP Mask */
-
-#define SYS_GPI_MFPH_PI12MFP_Pos (16) /*!< SYS GPI_MFPH: PI12MFP Position */
-#define SYS_GPI_MFPH_PI12MFP_Msk (0xful << SYS_GPI_MFPH_PI12MFP_Pos) /*!< SYS GPI_MFPH: PI12MFP Mask */
-
-#define SYS_GPI_MFPH_PI13MFP_Pos (20) /*!< SYS GPI_MFPH: PI13MFP Position */
-#define SYS_GPI_MFPH_PI13MFP_Msk (0xful << SYS_GPI_MFPH_PI13MFP_Pos) /*!< SYS GPI_MFPH: PI13MFP Mask */
-
-#define SYS_GPI_MFPH_PI14MFP_Pos (24) /*!< SYS GPI_MFPH: PI14MFP Position */
-#define SYS_GPI_MFPH_PI14MFP_Msk (0xful << SYS_GPI_MFPH_PI14MFP_Pos) /*!< SYS GPI_MFPH: PI14MFP Mask */
-
-#define SYS_GPI_MFPH_PI15MFP_Pos (28) /*!< SYS GPI_MFPH: PI15MFP Position */
-#define SYS_GPI_MFPH_PI15MFP_Msk (0xful << SYS_GPI_MFPH_PI15MFP_Pos) /*!< SYS GPI_MFPH: PI15MFP Mask */
-
-#define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS SRAM_INTCTL: PERRIEN Position */
-#define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS SRAM_INTCTL: PERRIEN Mask */
-
-#define SYS_SRAM_STATUS_PERRIF0_Pos (0) /*!< SYS SRAM_STATUS: PERRIF0 Position */
-#define SYS_SRAM_STATUS_PERRIF0_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF0_Pos) /*!< SYS SRAM_STATUS: PERRIF0 Mask */
-
-#define SYS_SRAM_STATUS_PERRIF1_Pos (1) /*!< SYS SRAM_STATUS: PERRIF1 Position */
-#define SYS_SRAM_STATUS_PERRIF1_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF1_Pos) /*!< SYS SRAM_STATUS: PERRIF1 Mask */
-
-#define SYS_SRAM0_ERRADDR_PERRADDR_Pos (0) /*!< SYS SRAM0_ERRADDR: PERRADDR Position */
-#define SYS_SRAM0_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM0_ERRADDR_PERRADDR_Pos) /*!< SYS SRAM0_ERRADDR: PERRADDR Mask */
-
-#define SYS_SRAM1_ERRADDR_PERRADDR_Pos (0) /*!< SYS SRAM1_ERRADDR: PERRADDR Position */
-#define SYS_SRAM1_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM1_ERRADDR_PERRADDR_Pos) /*!< SYS SRAM1_ERRADDR: PERRADDR Mask */
-
-#define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS IRCTCTL: FREQSEL Position */
-#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS IRCTCTL: FREQSEL Mask */
-
-#define SYS_IRCTCTL_CALCLOOP_Pos (4) /*!< SYS IRCTCTL: CALCLOOP Position */
-#define SYS_IRCTCTL_CALCLOOP_Msk (0x3ul << SYS_IRCTCTL_CALCLOOP_Pos) /*!< SYS IRCTCTL: CALCLOOP Mask */
-
-#define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS IRCTCTL: RETRYCNT Position */
-#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS IRCTCTL: RETRYCNT Mask */
-
-#define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS IRCTCTL: CESTOPEN Position */
-#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS IRCTCTL: CESTOPEN Mask */
-
-#define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS IRCTIEN: TFAILIEN Position */
-#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS IRCTIEN: TFAILIEN Mask */
-
-#define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS IRCTIEN: CLKEIEN Position */
-#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS IRCTIEN: CLKEIEN Mask */
-
-#define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS IRCTISTS: FREQLOCK Position */
-#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS IRCTISTS: FREQLOCK Mask */
-
-#define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS IRCTISTS: TFAILIF Position */
-#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS IRCTISTS: TFAILIF Mask */
-
-#define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS IRCTISTS: CLKERRIF Position */
-#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS IRCTISTS: CLKERRIF Mask */
-
-#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS REGLCTL: REGLCTL Position */
-#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS REGLCTL: REGLCTL Mask */
-
-#define SYS_REGLCTL_SYS_REGLCTL_Pos (0) /*!< SYS REGLCTL: SYS_REGLCTL Position */
-#define SYS_REGLCTL_SYS_REGLCTL_Msk (0xfful << SYS_REGLCTL_SYS_REGLCTL_Pos) /*!< SYS REGLCTL: SYS_REGLCTL Mask */
-
-/**@}*/ /* SYS_CONST */
-/**@}*/ /* end of SYS register group */
-
-
-/*---------------------- Timer Controller -------------------------*/
-/**
- @addtogroup TIMER Timer Controller(TIMER)
- Memory Mapped Structure for TIMER Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 Timer Control and Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |PSC |PSC Counter
- * | | |Timer input clock source is divided by (PSC+1) before it is fed to the timer up counter.
- * | | |If this field is 0 (PSC = 0), then there is no scaling.
- * |[16] |CNTDATEN |Data Load Enable
- * | | |When this bit is set, timer counter value (TIMER_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.
- * | | |0 = Timer Data Register update Disabled.
- * | | |1 = Timer Data Register update Enabled while timer counter is active.
- * |[21] |TOGDIS1 |Toggle Output 1 Disable
- * | | |Setting this bit will disable the Toggle output pins group 1.
- * | | |0 = Toggle output pins group 1 Enabled.
- * | | |1 = Toggle output pins group 1 Disabled.
- * | | |Note: The group1 pins are PB4, PB1, PC6, and PC1.
- * |[22] |TOGDIS2 |Toggle Output 2 Disable
- * | | |Setting this bit will disable the Toggle output pins group 2.
- * | | |0 = Toggle output pins group 2 Enabled.
- * | | |1 = Toggle output pins group 2 Disabled.
- * | | |Note1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled, toggle output signal is generated only from TOUT1 pins.
- * | | |Note2: The group2 pins are PD1, PE8, PE1, and PD11.
- * |[23] |WKEN |Wake-Up Enable
- * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMER_INTSTS[0]) is 1 and INTEN (TIMERX_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
- * | | |0 = Wake-up trigger event Disabled if timer interrupt signal generated.
- * | | |1 = Wake-up trigger event Enabled if timer interrupt signal generated.
- * |[24] |EXTCNTEN |Counter Mode Enable Bit
- * | | |This bit is for external counting pin function enabled.
- * | | |When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
- * | | |0 = External counter mode Disabled.
- * | | |1 = External counter mode Enabled.
- * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
- * | | |This bit indicates the 24-bit up counter status.
- * | | |0 = 24-bit up counter is not active.
- * | | |1 = 24-bit up counter is active.
- * |[26] |RSTCNT |Timer Reset Bit
- * | | |Setting this bit will reset the 24-bit up counter value (TIMER_CNT) and also force CNTEN (TIMERX_CTL[30]) to 0 if ACTSTS (TIMERX_CTL[25]) is 1.
- * | | |0 = No effect.
- * | | |1 = Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit.
- * |[27:28] |OPMODE |Timer Operation Mode
- * | | |00 = The Timer controller is operated in One-shot mode.
- * | | |01 = The Timer controller is operated in Periodic mode.
- * | | |10 = The Timer controller is operated in Toggle-output mode.
- * | | |11 = The Timer controller is operated in Continuous Counting mode.
- * |[29] |INTEN |Interrupt Enable Bit
- * | | |0 = Timer Interrupt Disabled.
- * | | |1 = Timer Interrupt Enabled.
- * | | |If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
- * |[30] |CNTEN |Timer Enable
- * | | |0 = Stops/Suspends counting.
- * | | |1 = Starts counting.
- * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
- * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMERX_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMER_INTSTS[0]) is generated.
- * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable (Write Protect)
- * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
- * | | |TIMER counter will be held while CPU is held by ICE.
- * | | |1 = ICE debug mode acknowledgement Disabled.
- * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
- */
- __IO uint32_t CTL;
-
- /**
- * CMP
- * ===================================================================================================
- * Offset: 0x04 Timer Compare Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |CMPDAT |Timer Compared Value
- * | | |CMPDAT is a 24-bit compared value register.
- * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMER_INTSTS[0] timer interrupt flag) will set to 1.
- * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
- * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the timer will run into unknown state.
- * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field.
- * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field.
- */
- __IO uint32_t CMP;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x08 Timer Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |TIF |Timer Interrupt Flag
- * | | |This bit indicates the interrupt flag status of Timer while TIMER_CNT value reaches to CMPDAT value.
- * | | |0 = No effect.
- * | | |1 = TIMER_CNT value matches the CMPDAT value.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[1] |TWKF |Timer Wake-Up Flag
- * | | |This bit indicates the interrupt wake-up flag status of timer.
- * | | |0 = Timer does not cause CPU wake-up.
- * | | |1 = CPU wake-up from Idle or power-down mode if timer time-out interrupt signal generated.
- * | | |Note: This bit is cleared by writing 1 to it.
- */
- __IO uint32_t INTSTS;
-
- /**
- * CNT
- * ===================================================================================================
- * Offset: 0x0C Timer Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |TIMER_CNT |Timer Data Register
- * | | |1. EXTCNTEN (TIMERX_CTL[24] ) = 0 : TIMER_CNT is 24- bit counter value.
- * | | |User can read TIMER_CNT for getting current 24- bit counter value if TIMERX_CTL[24] is set to 0
- * | | |2. EXTCNTEN (TIMERX_CTL[24] ) = 1 : TIMER_CNT is 24- bit event counter value.
- * | | |User can read TIMER_CNT for getting current 24- bit event counter value if TIMERX_CTL[24] is 1
- */
- __I uint32_t CNT;
-
- /**
- * CAP
- * ===================================================================================================
- * Offset: 0x10 Timer Capture Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:23] |CAPDAT |Timer Capture Data Register
- * | | |When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, CAPIF (TIMER_EINTSTS[0]) will set to 1 and the current timer counter value (TIMER_CNT value) will be auto-loaded into this CAPDAT field.
- */
- __I uint32_t CAP;
-
- /**
- * EXTCTL
- * ===================================================================================================
- * Offset: 0x14 Timer External Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CNTPHASE |Timer External Count Phase
- * | | |This bit indicates the detection phase of external counting pin.
- * | | |0 = A falling edge of external counting pin will be counted.
- * | | |1 = A rising edge of external counting pin will be counted.
- * |[1:2] |CAPEDGE |Timer External Pin Edge Detect
- * | | |00 = A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected.
- * | | |01 = A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected.
- * | | |10 = Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected.
- * | | |11 = Reserved.
- * |[3] |CAPEN |Timer External Pin Enable
- * | | |This bit enables the CAPFUNCS (TIMER_EXTCTL[4]) function on the TMx_EXT pin.
- * | | |0 = CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored.
- * | | |1 = CAPFUNCS function of TMx_EXT (x= 0~3) pin is active.
- * |[4] |CAPFUNCS |Timer External Reset Counter / Capture Mode Select
- * | | |0 = Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
- * | | |(TIMER_CNT value) to timer capture value (TIMER_CAP value) if CAPIF (TIMER_EINTSTS[0]) is set to 1
- * | | |1 = Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
- * |[5] |CAPIEN |Timer External Interrupt Enable
- * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
- * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
- * | | |CAPIEN is used to enable timer external interrupt.
- * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF = 1.
- * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TEX pin will cause the CAPIF(TIMER_EINTSTS[0]) interrupt flag to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
- * |[6] |CAPDBEN |Timer External Capture Pin De-Bounce Enable
- * | | |0 = TMx_EXT (x= 0~3) pin de-bounce Disabled.
- * | | |1 = TMx_EXT (x= 0~3) pin de-bounce Enabled.
- * | | |If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
- * |[7] |ECNTDBEN |Timer Counter Pin De-Bounce Enable
- * | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
- * | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
- * | | |If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
- */
- __IO uint32_t EXTCTL;
-
- /**
- * EINTSTS
- * ===================================================================================================
- * Offset: 0x18 Timer External Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CAPIF |Timer External Interrupt Flag
- * | | |This bit indicates the timer external interrupt flag status.
- * | | |When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
- * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
- * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
- * | | |Note: This bit is cleared by writing 1 to it.
- */
- __IO uint32_t EINTSTS;
-
-} TIMER_T;
-
-/**
- @addtogroup TIMER_CONST TIMER Bit Field Definition
- Constant Definitions for TIMER Controller
-@{ */
-
-#define TIMER_CTL_PSC_Pos (0) /*!< TIMER CTL: PSC Position */
-#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER CTL: PSC Mask */
-
-#define TIMER_CTL_CNTDATEN_Pos (16) /*!< TIMER CTL: CNTDATEN Position */
-#define TIMER_CTL_CNTDATEN_Msk (0x1ul << TIMER_CTL_CNTDATEN_Pos) /*!< TIMER CTL: CNTDATEN Mask */
-
-#define TIMER_CTL_TOGDIS1_Pos (21) /*!< TIMER CTL: TOGDIS1 Position */
-#define TIMER_CTL_TOGDIS1_Msk (0x1ul << TIMER_CTL_TOGDIS1_Pos) /*!< TIMER CTL: TOGDIS1 Mask */
-
-#define TIMER_CTL_TOGDIS2_Pos (22) /*!< TIMER CTL: TOGDIS2 Position */
-#define TIMER_CTL_TOGDIS2_Msk (0x1ul << TIMER_CTL_TOGDIS2_Pos) /*!< TIMER CTL: TOGDIS2 Mask */
-
-#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER CTL: WKEN Position */
-#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER CTL: WKEN Mask */
-
-#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER CTL: EXTCNTEN Position */
-#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER CTL: EXTCNTEN Mask */
-
-#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER CTL: ACTSTS Position */
-#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER CTL: ACTSTS Mask */
-
-#define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER CTL: RSTCNT Position */
-#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER CTL: RSTCNT Mask */
-
-#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER CTL: OPMODE Position */
-#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER CTL: OPMODE Mask */
-
-#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER CTL: INTEN Position */
-#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER CTL: INTEN Mask */
-
-#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER CTL: CNTEN Position */
-#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER CTL: CNTEN Mask */
-
-#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER CTL: ICEDEBUG Position */
-#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER CTL: ICEDEBUG Mask */
-
-#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER CMP: CMPDAT Position */
-#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER CMP: CMPDAT Mask */
-
-#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER INTSTS: TIF Position */
-#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER INTSTS: TIF Mask */
-
-#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER INTSTS: TWKF Position */
-#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER INTSTS: TWKF Mask */
-
-#define TIMER_CNT_TIMER_CNT_Pos (0) /*!< TIMER CNT: TIMER_CNT Position */
-#define TIMER_CNT_TIMER_CNT_Msk (0xfffffful << TIMER_CNT_TIMER_CNT_Pos) /*!< TIMER CNT: TIMER_CNT Mask */
-
-#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER CAP: CAPDAT Position */
-#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER CAP: CAPDAT Mask */
-
-#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER EXTCTL: CNTPHASE Position */
-#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER EXTCTL: CNTPHASE Mask */
-
-#define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER EXTCTL: CAPEDGE Position */
-#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER EXTCTL: CAPEDGE Mask */
-
-#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER EXTCTL: CAPEN Position */
-#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER EXTCTL: CAPEN Mask */
-
-#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER EXTCTL: CAPFUNCS Position */
-#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER EXTCTL: CAPFUNCS Mask */
-
-#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER EXTCTL: CAPIEN Position */
-#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER EXTCTL: CAPIEN Mask */
-
-#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER EXTCTL: CAPDBEN Position */
-#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER EXTCTL: CAPDBEN Mask */
-
-#define TIMER_EXTCTL_ECNTDBEN_Pos (7) /*!< TIMER EXTCTL: ECNTDBEN Position */
-#define TIMER_EXTCTL_ECNTDBEN_Msk (0x1ul << TIMER_EXTCTL_ECNTDBEN_Pos) /*!< TIMER EXTCTL: ECNTDBEN Mask */
-
-#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER EINTSTS: CAPIF Position */
-#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER EINTSTS: CAPIF Mask */
-
-
-/**@}*/ /* TIMER_CONST */
-/**@}*/ /* end of TMR register group */
-
-
-/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
-/**
- @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
- Memory Mapped Structure for UART Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * DAT
- * ===================================================================================================
- * Offset: 0x00 UARTx Receive / Transmit Buffer Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DAT |Receiving/Transmit Buffer
- * | | |Write Operation:
- * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO. The
- * | | |UART Controller will send out the data stored in transmitter FIFO top location through the
- * | | |UART_TXD.
- * | | |Read Operation:
- * | | |By reading this register, the UART will return an 8-bit data received from receiving FIFO
- */
- __IO uint32_t DAT;
-
- /**
- * INTEN
- * ===================================================================================================
- * Offset: 0x04 UARTx Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIEN |Receive Data Available Interrupt Enable Control
- * | | |0 = INT_RDA Disabled.
- * | | |1 = INT_RDA Enabled.
- * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Control
- * | | |0 = INT_THRE Disabled.
- * | | |1 = INT_THRE Enabled.
- * |[2] |RLSIEN |Receive Line Status Interrupt Enable Control
- * | | |0 = INT_RLS Disabled.
- * | | |1 = INT_RLS Enabled.
- * |[3] |MODEMIEN |Modem Status Interrupt Enable Control
- * | | |0 = INT_MODEM Disabled.
- * | | |1 = INT_MODEM Enabled.
- * |[4] |RXTOIEN |RX Time-Out Interrupt Enable Control
- * | | |0 = NT_TOUT Disabled.
- * | | |1 = INT_TOUT Enabled.
- * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Control
- * | | |0 = INT_BUF_ERR Disabled.
- * | | |1 = INT_BUF_ERR Enabled.
- * |[6] |WKCTSIEN |UART Wake-Up Function Enable Control
- * | | |0 = UART wake-up function Disabled.
- * | | |1 = UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode.
- * |[8] |LINIEN |LIN RX Break Field Detected Interrupt Enable Control
- * | | |0 = Lin bus RX break filed interrupt Disabled.
- * | | |1 = Lin bus RX break filed interrupt Enabled.
- * | | |Note: This field is used for LIN function mode.
- * |[11] |TOCNTEN |Time-Out Counter Enable Control
- * | | |0 = Time-out counter Disabled.
- * | | |1 = Time-out counter Enabled.
- * |[12] |ATORTSEN |RTS Auto Flow Control Enable Control
- * | | |0 = RTS auto flow control Disabled.
- * | | |1 = RTS auto flow control Enabled.
- * | | |When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
- * |[13] |ATOCTSEN |CTS Auto Flow Control Enable Control
- * | | |0 = CTS auto flow control Disabled.
- * | | |1 = CTS auto flow control Enabled.
- * | | |When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
- * |[14] |TXPDMAEN |TX DMA Enable Control
- * | | |This bit can enable or disable TX DMA service.
- * | | |0 = TX DMA Disabled.
- * | | |1 = TX DMA Enabled.
- * |[15] |RXPDMAEN |RX DMA Enable Control
- * | | |This bit can enable or disable RX DMA service.
- * | | |0 = RX DMA Disabled.
- * | | |1 = RX DMA Enabled.
- */
- __IO uint32_t INTEN;
-
- /**
- * FIFO
- * ===================================================================================================
- * Offset: 0x08 UARTx FIFO Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |RXRST |RX Field Software Reset
- * | | |When RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the RX internal state machine and pointers.
- * | | |Note: This bit will be automatically cleared for at least 3 UART engine clock cycles.
- * |[2] |TXRST |TX Field Software Reset
- * | | |When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
- * | | |0 = No effect.
- * | | |1 = Reset the TX internal state machine and pointers.
- * | | |Note: This bit will auto clear needs at least 3 UART engine clock cycles.
- * |[4:7] |RFITL |RX FIFO Interrupt (INT_RDA) Trigger Level
- * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) is enabled, an interrupt will generated).
- * | | |0000 = 1 byte
- * | | |0001 = 4 bytes
- * | | |0010 = 8 bytes
- * | | |0011 = 14 bytes
- * | | |0100 = 30/14 bytes (High-speed/Normal Speed)
- * | | |0101 = 46/14 bytes (High-speed/Normal Speed)
- * | | |0110 = 62/14 bytes (High-speed/Normal Speed)
- * | | |others = 62/14 bytes (High-speed/Normal Speed)
- * |[8] |RXOFF |Receiver Disable
- * | | |The receiver is disabled or not.
- * | | |0 = Receiver Enabled.
- * | | |1 = Receiver Disabled.
- * | | |Note: This field is used for RS-485 Normal Multi-drop mode.
- * | | |It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
- * |[16:19] |RTSTRGLV |RTS Trigger Level For Auto-Flow Control Use
- * | | |0000 = 01 byte
- * | | |0001 = 04 bytes
- * | | |0010 = 08 bytes
- * | | |0011 = 14 bytes
- * | | |0100 = 30/14 bytes (High-speed/Normal Speed)
- * | | |0101 = 46/14 bytes (High-speed/Normal Speed)
- * | | |0110 = 62/14 bytes (High-speed/Normal Speed)
- * | | |others = 62/14 bytes (High-speed/Normal Speed)
- * | | |Note: This field is used for auto RTS flow control.
- */
- __IO uint32_t FIFO;
-
- /**
- * LINE
- * ===================================================================================================
- * Offset: 0x0C UARTx Line Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |WLS |Word Length Selection
- * | | |00 = 5-bit
- * | | |01 = 6-bit
- * | | |10 = 7-bit
- * | | |11 = 8-bit
- * |[2] |NSB |Number Of "STOP Bit"
- * | | |0= One " STOP bit" is generated in the transmitted data.
- * | | |1= One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected.
- * | | |Two "STOP bit" is generated when 6-, 7- and 8-bit word length is selected.
- * |[3] |PBE |Parity Bit Enable Control
- * | | |0 = No parity bit.
- * | | |1 = Parity bit is generated on each outgoing character and is checked on each incoming data.
- * |[4] |EPE |Even Parity Enable Control
- * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
- * | | |1 = Even number of logic 1's is transmitted and checked in each word.
- * | | |This bit is effective only when bit 3 (parity bit enable) is set.
- * |[5] |SPE |Stick Parity Enable Control
- * | | |0 = Stick parity Disabled.
- * | | |1 = If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0.
- * | | |If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1.
- * |[6] |BCB |Break Control
- * | | |When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
- * | | |This bit acts only on TX and has no effect on the transmitter logic.
- */
- __IO uint32_t LINE;
-
- /**
- * MODEM
- * ===================================================================================================
- * Offset: 0x10 UARTx Modem Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |RTS |RTS (Request-To-Send) Signal
- * | | |0 = Drive RTS pin to logic 1 (If the RTSACTLV
- * | | |set to low level triggered).
- * | | |1 = Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).
- * | | |0 = Drive RTS pin to logic 0 (If the RTSACTLV
- * | | |set to high level triggered).
- * | | |1 = Drive RTS pin to logic 1 (If the RTSACTLV set to high level triggered).
- * |[9] |RTSACTLV |RTS Trigger Level
- * | | |This bit can change the RTS trigger level.
- * | | |0= Low level triggered.
- * | | |1= High level triggered.
- * |[13] |RTSSTS |RTS Pin State (Read Only)
- * | | |This bit is the output pin status of RTS.
- */
- __IO uint32_t MODEM;
-
- /**
- * MODEMSTS
- * ===================================================================================================
- * Offset: 0x14 UARTx Modem Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CTSDETF |Detect CTS State Change Flag (Read Only)
- * | | |This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.
- * | | |Software can write 1 to clear this bit to 0
- * |[4] |CTSSTS |CTS Pin Status (Read Only)
- * | | |This bit is the pin status of CTS.
- * |[8] |CTSACTLV |CTS Trigger Level
- * | | |This bit can change the CTS trigger level.
- * | | |0= Low level triggered.
- * | | |1= High level triggered.
- */
- __IO uint32_t MODEMSTS;
-
- /**
- * FIFOSTS
- * ===================================================================================================
- * Offset: 0x18 UARTx FIFO Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RXOVIF |RX Overflow Error IF (Read Only)
- * | | |This bit is set when RX FIFO overflow.
- * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.
- * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
- * |[2] |SCERR |Smart Card Over Error Retry Flag
- * | | |It is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))
- * | | |0 = No any transmitter re-transmits over or receiver transfer error retry over.
- * | | |1 = one of the transmitter re-transmits over active or receiver transfer error retry over active.
- * | | |Note1: This field is used for SC function mode.
- * | | |Note2: This bit is read only, but it can be cleared by writing '1' to it.
- * |[3] |ADDRDETF |RS-485 Address Byte Detection Flag (Read Only)
- * | | |This bit is set to logic 1 and set RS-485_ADD_EN (UART_ALTCTL[15]) whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = '1') bit, and it is reset whenever the CPU writes 1 to this bit.
- * | | |Note1: This field is used for RS-485 function mode.
- * | | |Note2: This bit is read only, but it can be cleared by writing '1' to it.
- * |[4] |PEF |Parity Error Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.
- * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
- * |[5] |FEF |Framing Error Flag (Read Only)
- * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
- * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
- * |[6] |BIF |Break Interrupt Flag (Read Only)
- * | | |This bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
- * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
- * |[8:13] |RXPTR |RX FIFO Pointer (Read Only)
- * | | |This field indicates the RX FIFO Buffer Pointer.
- * | | |When UART receives one byte from external device, RXPTR increases one.
- * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
- * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
- * | | |This bit initiate RX FIFO empty or not.
- * | | |When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
- * | | |It will be cleared when UART receives any new data.
- * |[15] |RXFULL |Receiver FIFO Full (Read Only)
- * | | |This bit initiates RX FIFO full or not.
- * | | |This bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
- * |[16:21] |TXPTR |TX FIFO Pointer (Read Only)
- * | | |This field indicates the TX FIFO Buffer Pointer.
- * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.
- * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
- * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
- * | | |This bit indicates TX FIFO empty or not.
- * | | |When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
- * | | |It will be cleared when writing data into DAT (TX FIFO not empty).
- * |[23] |TX_FULL |Transmitter FIFO Full (Read Only)
- * | | |This bit indicates TX FIFO full or not.
- * | | |This bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
- * |[24] |TXOVIF |TX Overflow Error Interrupt Flag (Read Only)
- * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to
- * | | |logic 1.
- * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
- * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
- * | | |Bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
- * | | |Bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
- */
- __IO uint32_t FIFOSTS;
-
- /**
- * INTSTS
- * ===================================================================================================
- * Offset: 0x1C UARTx Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only)
- * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set.
- * | | |If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated.
- * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
- * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only)
- * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
- * | | |If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
- * | | |Note: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
- * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
- * | | |This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set).
- * | | |If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
- * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
- * | | |Note2: In SC function mode, this field includes error retry over flag .
- * | | |Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
- * |[3] |MODENIF |MODEM Interrupt Flag (Read Only)
- * | | |This bit is set when the CTS pin has state change (CTSDETF=1).
- * | | |If MODEMIEN bit (UART_INTEN[3]) is enabled, the Modem interrupt will be generated.
- * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
- * |[4] |RXTOIF |Time-Out Interrupt Flag (Read Only)
- * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
- * | | |If TIME_OUT_IEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated.
- * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
- * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
- * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set).
- * | | |When BERRIF is set, the transfer maybe is not correct.
- * | | |If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.
- * | | |Note: This bit is cleared when both TXOVIF and RXOVIF are cleared.
- * |[7] |LIN_IF |LIN Bus Flag (Read Only)
- * | | |This bit is set when LIN slave header detect (SLVHDETF=1), LIN break detect (BRKDETF=1), bit error detect (BITEF=1), LIN slave ID parity error (SLVIDPEF) or LIN slave header error detect (SLVHEF) If LIN_RX_BRK_ IEN bit (UART_INTEN[8]) is enabled the LIN interrupt will be generated.
- * | | |Note: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
- * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
- * | | |This bit is set if RDAIEN and RDAIF are both set to 1.
- * | | |0 = No RDA interrupt is generated.
- * | | |1 = RDA interrupt is generated.
- * |[9] |THREINT |Transmit Holding Register Empty Interrupt
- * | | |Indicator (Read Only)
- * | | |This bit is set if THREIEN and THREIF are both set to 1.
- * | | |0 = No THRE interrupt is generated.
- * | | |1 = THRE interrupt is generated.
- * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
- * | | |This bit is set if RLSIEN and RLSIF are both set to 1.
- * | | |0 = No RLS interrupt is generated.
- * | | |1 = RLS interrupt is generated.
- * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
- * | | |This bit is set if MODEMIEN and MODENIF are both set to 1.
- * | | |0 = No Modem interrupt is generated.
- * | | |1 = Modem interrupt is generated.
- * |[12] |RXTOINT |Time-Out Interrupt Indicator (Read Only)
- * | | |This bit is set if TOUT_IEN and RXTOIF are both set to 1.
- * | | |0 = No Tout interrupt is generated.
- * | | |1 = Tout interrupt is generated.
- * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
- * | | |This bit is set if BUFERRIEN and BERRIF are both set to 1.
- * | | |0 = No buffer error interrupt is generated.
- * | | |1 = The buffer error interrupt is generated.
- * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)
- * | | |This bit is set if LIN_IEN and LIN_RX_BREAK_IF are both set to 1.
- * | | |0 = No LIN RX Break interrupt is generated.
- * | | |1 = LIN RX Break interrupt is generated.
- * |[18] |HWRLSIF |In DMA Mode, Receive Line Status Flag (Read Only)
- * | | |This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set).
- * | | |If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
- * | | |Note1: In RS-485 function mode, this field includes receiver detect any address byte received address byte character (bit9 = '1') bit.
- * | | |Note2: In SC function mode, this field includes error retry over flag.
- * | | |Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
- * |[19] |HWMODIF |In DMA Mode, MODEM Interrupt Flag (Read Only)
- * | | |This bit is set when the CTS pin has state change (CTSDETF = 1).
- * | | |If MODEMIEN (UART_INTEN[3]) is enabled, the Modem interrupt will be generated.
- * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
- * |[20] |HWTOIF |In DMA Mode, Time-Out Interrupt Flag (Read Only)
- * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
- * | | |If TIME_OUT_IEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated.
- * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
- * |[21] |HWBUFEIF |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
- * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set).
- * | | |When BERRIF is set, the transfer maybe is not correct.
- * | | |If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
- * | | |Note: This bit is cleared when both TXOVIF and RXOVIF are cleared.
- * |[26] |HWRLSINT |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
- * | | |This bit is set if RLSIEN and HWRLSIF are both set to 1.
- * | | |0 = No RLS interrupt is generated in DMA mode.
- * | | |1 = RLS interrupt is generated in DMA mode.
- * |[27] |HWMODINT |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
- * | | |This bit is set if MODEMIEN and HWMODIF are both set to 1.
- * | | |0 = No Modem interrupt is generated in DMA mode.
- * | | |1 = Modem interrupt is generated in DMA mode.
- * |[28] |HWTOINT |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
- * | | |This bit is set if TOUT_IEN and HWTOIF are both set to 1.
- * | | |0 = No Tout interrupt is generated in DMA mode.
- * | | |1 = Tout interrupt is generated in DMA mode.
- * |[29] |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
- * | | |This bit is set if BUFERRIEN and HWBFERIF are both set to 1.
- * | | |0 = No buffer error interrupt is generated in DMA mode.
- * | | |1 = The buffer error interrupt is generated in DMA mode.
- */
- __IO uint32_t INTSTS;
-
- /**
- * TOUT
- * ===================================================================================================
- * Offset: 0x20 UARTx Time-out Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |TOIC |Time-Out Interrupt Comparator
- * | | |The time-out counter resets and starts counting (the counting clock = baud rate clock) whenever the RX FIFO receives a new data word.
- * | | |Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (INT_TOUT) is generated if RXTOIEN (UART_INTEN[4]).
- * | | |A new incoming data word or RX FIFO empty clears INT_TOUT.
- * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
- * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
- * |[8:15] |DLY |TX Delay Time Value
- * | | |This field is use to programming the transfer delay time between the last stop bit and next start bit.
- * | | |Note: The counter clock is baud rate clock
- */
- __IO uint32_t TOUT;
-
- /**
- * BAUD
- * ===================================================================================================
- * Offset: 0x24 UARTx Baud Rate Divisor Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |BRD |Baud Rate Divider
- * | | |The field indicated the baud rate divider
- * |[24:27] |EDIVM1 |Divider X
- * | | |The baud rate divider M = X+1.
- * |[28] |BAUDM0 |Divider X Equal To 1
- * | | |0 = Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8).
- * | | |1 = Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must >= 3).
- * | | |Refer to the table below for more information.
- * |[29] |BAUDM1 |Divider X Enable Control
- * | | |The BRD = Baud Rate Divider, and the baud rate equation is
- * | | |Baud Rate = Clock / [M * (BRD + 2)]; The default value of M is 16.
- * | | |0 = Divider X Disabled (the equation of M = 16).
- * | | |1 = Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8).
- * | | |Refer to the table below for more information.
- * | | |Note: In IrDA mode, this bit must disable.
- */
- __IO uint32_t BAUD;
-
- /**
- * IRDA
- * ===================================================================================================
- * Offset: 0x28 UARTx IrDA Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
- * | | |0 = IrDA receiver Enabled.
- * | | |1 = IrDA transmitter Enabled.
- * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
- * | | |0 = No inversion.
- * | | |1 = Inverse TX output signal.
- * |[6] |RXINV |IrDA Inverse Receive Input Signal
- * | | |0 = No inversion.
- * | | |1 = Inverse RX input signal.
- * |[7] |FIXPULSE |Pulse width of TX is fixed 1.6us.
- */
- __IO uint32_t IRDA;
-
- /**
- * ALTCTL
- * ===================================================================================================
- * Offset: 0x2C UARTx Alternate Control/Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |BKFL |LIN Break Field Length
- * | | |This field indicates a 4-bit LIN TX break field count.
- * | | |Note1: This break field length is BRKFL + 1.
- * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
- * |[6] |LINRXEN |LIN RX Enable Control
- * | | |0 = LIN RX mode Disabled.
- * | | |1 = LIN RX mode Enabled.
- * |[7] |LINTXEN |LIN TX Break Mode Enable Control
- * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field" depending on the setting HSEL register.
- * | | |0 = Send LIN TX header Disabled.
- * | | |1 = Send LIN TX header Enabled.
- * | | |Note: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
- * |[8] |RS485NMM |RS-485 Normal Multi-Drop Operation Mode (NMM)
- * | | |0 = RS-485 Normal Multi-drop Operation Mode (NMM) Disabled.
- * | | |1 = RS-485 Normal Multi-drop Operation Mode (NMM) Enabled.
- * | | |Note: It can't be active with RS-485_AAD operation mode.
- * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
- * | | |0 = RS-485 Auto Address Detection (AAD) Operation mode Disabled.
- * | | |1 = RS-485 Auto Address Detection (AAD) Operation mode Enabled.
- * | | |Note: It can't be active with RS-485_NMM operation mode.
- * |[10] |RS485AUD |RS-485 Auto Direction Mode (AUD)
- * | | |0 = RS-485 Auto Direction Operation (AUO) mode Disabled.
- * | | |1 = RS-485 Auto Direction Operation (AUO) mode Enabled.
- * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
- * |[15] |ADDRDEN |RS-485 Address Detection Enable Control
- * | | |This bit is use to enable RS-485 address detection mode.
- * | | |0 = address detection mode Disabled.
- * | | |1 = Address detection mode Enabled.
- * | | |Note: This field is used for RS-485 any operation mode.
- * |[24:31] |ADDRMV |Address Match Value
- * | | |This field contains the RS-485 address match values.
- * | | |Note: This field is used for RS-485 auto address detection mode.
- */
- __IO uint32_t ALTCTL;
-
- /**
- * FUNCSEL
- * ===================================================================================================
- * Offset: 0x30 UARTx Function Select Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |FUNCSEL |Function Select Enable Control
- * | | |000 = UART function.
- * | | |001 = LIN function Enabled.
- * | | |010 = IrDA function Enabled.
- * | | |011 = RS-485 function Enabled.
- * | | |100 = Smart-Card function Enabled.
- */
- __IO uint32_t FUNCSEL;
-
- /**
- * LINCTL
- * ===================================================================================================
- * Offset: 0x34 UARTx LIN Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SLVEN |LIN Slave Mode Enable Control
- * | | |0 = LIN slave mode Disabled.
- * | | |1 = LIN slave mode Enabled.
- * |[1] |SLVHDEN |LIN Slave Header Detection Enable Control
- * | | |0 = LIN slave header detection Disabled.
- * | | |1 = LIN slave header detection Enabled.
- * | | |Note1: This bit only valid in LIN slave mode (SLVEN = 1).
- * | | |Note2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
- * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Control
- * | | |0 = LIN automatic resynchronization Disabled.
- * | | |1 = LIN automatic resynchronization Enabled.
- * | | |Note1: This bit only valid in LIN slave mode (SLVEN = 1).
- * | | |Note2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).
- * | | |Note3: The control and interactions of this field are explained in 6.31.5.3.
- * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Control
- * | | |0 = UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time).
- * | | |1 = UART_BAUD is updated at the next received character.
- * | | |User must set the bit before checksum reception.
- * | | |Note1: This bit only valid in LIN slave mode (SLVEN = 1).
- * | | |Note2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).
- * | | |Note3: The control and interactions of this field are explained in 6.31.5.3.
- * |[4] |MUTE |LIN Mute Mode Enable Control
- * | | |0 = LIN mute mode. Disabled
- * | | |1 = LIN mute mode Enabled.
- * | | |Note: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.31.5.3.
- * |[8] |SENDH |LIN TX Send Header Enable Control
- * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field" depending on the setting HSEL register.
- * | | |0 = Send LIN TX header Disabled.
- * | | |1 = Send LIN TX header Enabled.
- * | | |Note: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
- * |[9] |IDPEN |LIN ID Parity Enable Control
- * | | |0 = LIN frame ID parity Disabled.
- * | | |1 = LIN frame ID parity Enabled.
- * | | |Note1: This bit can be used for LIN master to sending header field (SENDH = 1 and HSEL = 2'b10) or be used for enable LIN slave received frame ID parity checked.
- * | | |Note2: This bit is only used when operation header transmitter is in HSEL = 2'b10.
- * |[10] |BRKDETEN |LIN Break Detection Enable Control
- * | | |When detect great than 11/10 bits are detected as 0, and are followed by a delimiter character, the BRKDETF flag (UART_LINSTS[8]) at the end of break field.
- * | | |If the LINIEN bit (UART_INTEN[8]) = 1, an interrupt will be generated.
- * | | |0 = LIN break detection Disabled.
- * | | |1 = LIN break detection Enabled.
- * |[11] |RXOFF |If the receiver is be enabled (RXOFF = 0), all received byte data will be accepted and stored in the RX-FIFO, and if the receiver is disabled (RXOFF = 1), all received byte data will be ignore.
- * | | |0 = Bit error detection function Disabled.
- * | | |1 = Bit error detection Enabled.
- * | | |Note: This bit is only valid when operating in LIN function mode (UART_FUNCSEL = 2'b01).
- * |[12] |BITERREN |Bit Error Detect Enable Control
- * | | |0 = Bit error detection function Disabled.
- * | | |1 = Bit error detection Enabled.
- * | | |Note: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
- * |[16:19] |BRKFL |LIN Break Field Length
- * | | |This field indicates a 4-bit LIN TX break field count.
- * | | |Note1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).
- * | | |Note2: This break field length is BRKFL + 1.
- * | | |Note3: According to LIN spec, the reset value is 0XC (break field length = 13).
- * |[20:21] |BSL |LIN Break/Sync Delimiter Length
- * | | |00 = LIN break/sync delimiter length is 1 bit time.
- * | | |10 = The LIN break/sync delimiter length is 2 bit time.
- * | | |10 = The LIN break/sync delimiter length is 3 bit time.
- * | | |11 = The LIN break/sync delimiter length is 4 bit time.
- * | | |Note: This bit used for LIN master to send header field.
- * |[22:23] |HSEL |LIN Header Selection
- * | | |00 = LIN header includes "break field".
- * | | |01 = LIN header includes "break field" and "sync field".
- * | | |10 = LIN header includes "break field", "sync field" and "frame ID field".
- * | | |11 = LIN header includes "break field", "sync field" and "frame ID field", but this mode only supports Receiver mode, not support transmitter mode.
- * | | |This mode difference with mode "10"; in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set).
- * | | |Note: This bit is used to master mode for LIN to sending header field (SENDH = 1) or used to slave to indicates wake-up condition from mute mode (MUTE).
- * |[24:31] |PID |This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN]
- * | | |If the parity generated by hardware (IDPEN (UART_LINCTL[9]) = 1), user fill ID0~ID5, hardware will calculi P0 and P1, otherwise user must filled frame ID and parity in this field.
- * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)
- * | | |Note2: This field can be used for LIN Master mode or Slave mode.
- */
- __IO uint32_t LINCTL;
-
- /**
- * LINSTS
- * ===================================================================================================
- * Offset: 0x38 UARTx LIN Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SLVHDETF |LIN Slave Header Detection Flag (Read Only)
- * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
- * | | |0 = LIN header not detected.
- * | | |1 = LIN header detected (break + sync + frame ID).
- * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN slave header detection function (SLVHDEN (UART_LINCTL[1])) is enabled.
- * | | |Note3: When the ID parity check (IDPEN (UART_LINCTL[9]) = 1) is enabled, if hardware detect complete harder ("break + sync + frame ID"), the LINS_HEDT_F (UART_LINCTL[1]) will be set no matter the frame ID is corrected or not.
- * |[1] |SLVHEF |LIN Slave Header Error Flag (Read Only)
- * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
- * | | |The header include "break delimiter is too short", "frame error in sync field or Identifier field", "sync field data is not 0x55 without automatic resynchronization mode", "sync field deviation error with automatic resynchronization mode", "sync field measure time-out with automatic resynchronization mode" and "LIN header reception time-out".
- * | | |0 = LIN header error not detected.
- * | | |1 = LIN header error detected.
- * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN slave header detection function (SLVHDEN (UART_LINCTL[1])) is enabled.
- * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag (Read Only)
- * | | |This bit is set by hardware when receipted frame ID parity is not correct.
- * | | |0 = no active.
- * | | |1 = Receipted frame ID parity is not correct.
- * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN frame ID parity check function (IDPEN (UART_LINCTL[9])) is enabled.
- * |[3] |SLVSYNCF |LIN Slave Sync Field
- * | | |This bit indicates that the LIN sync field is being analyzed.
- * | | |When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.
- * | | |0 = The current character is not at LIN sync state.
- * | | |1 = The current character is at LIN sync state.
- * | | |Note1: This bit only valid in LIN Slave mode (SLVEN = 1).
- * | | |Note2: This bit is read only, but can be cleared by writing 1 to it.
- * | | |Note3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.31.5.3.
- * |[8] |BRKDETF |LIN Break Detection Flag (Read Only)
- * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it.
- * | | |0 = LIN break not detected.
- * | | |1 = LIN break detected.
- * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
- * |[9] |BITEF |Bit Error Detect Status Flag (Read Only)
- * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.
- * | | |When occur bit error, hardware will generate an interrupt to CPU (INT_LIN).
- * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
- * | | |Note2: This bit is only valid when enable bit error detection function (BRKL (UART_LINCTL[12]) == 1).
- */
- __IO uint32_t LINSTS;
-
- /**
- * LINDEBUG
- * ===================================================================================================
- * Offset: 0x3C UARTx LIN Debug Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DEVERRF |LIN Header Deviation Error (Read Only)
- * | | |This bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
- * |[1] |TOF |LIN Header Time-Out (Read Only)
- * | | |This bit indicates the header error cause by the LIN header reception time-out.
- * |[2] |FRAMEERRF |LIN Header Frame Error Flag (Read Only)
- * | | |This bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
- * |[3] |SYNCERRF |LIN Header Sync Data Error (Read Only)
- * | | |This bit indicates the header error cause by the LIN received sync data is not 0x55.
- */
- __IO uint32_t LINDEBUG;
-
-
-} UART_T;
-
-/**
- @addtogroup UART_CONST UART Bit Field Definition
- Constant Definitions for UART Controller
-@{ */
-
-#define UART_DAT_DAT_Pos (0) /*!< UART DAT: DAT Position */
-#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART DAT: DAT Mask */
-
-#define UART_INTEN_RDAIEN_Pos (0) /*!< UART INTEN: RDAIEN Position */
-#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART INTEN: RDAIEN Mask */
-
-#define UART_INTEN_THREIEN_Pos (1) /*!< UART INTEN: THREIEN Position */
-#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART INTEN: THREIEN Mask */
-
-#define UART_INTEN_RLSIEN_Pos (2) /*!< UART INTEN: RLSIEN Position */
-#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART INTEN: RLSIEN Mask */
-
-#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART INTEN: MODEMIEN Position */
-#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART INTEN: MODEMIEN Mask */
-
-#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART INTEN: RXTOIEN Position */
-#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART INTEN: RXTOIEN Mask */
-
-#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART INTEN: BUFERRIEN Position */
-#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART INTEN: BUFERRIEN Mask */
-
-#define UART_INTEN_WKCTSIEN_Pos (6) /*!< UART INTEN: WKCTSIEN Position */
-#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /*!< UART INTEN: WKCTSIEN Mask */
-
-#define UART_INTEN_LINIEN_Pos (8) /*!< UART INTEN: LINIEN Position */
-#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART INTEN: LINIEN Mask */
-
-#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART INTEN: TOCNTEN Position */
-#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART INTEN: TOCNTEN Mask */
-
-#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART INTEN: ATORTSEN Position */
-#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART INTEN: ATORTSEN Mask */
-
-#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART INTEN: ATOCTSEN Position */
-#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART INTEN: ATOCTSEN Mask */
-
-#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART INTEN: TXPDMAEN Position */
-#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART INTEN: TXPDMAEN Mask */
-
-#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART INTEN: RXPDMAEN Position */
-#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART INTEN: RXPDMAEN Mask */
-
-#define UART_FIFO_RXRST_Pos (1) /*!< UART FIFO: RXRST Position */
-#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART FIFO: RXRST Mask */
-
-#define UART_FIFO_TXRST_Pos (2) /*!< UART FIFO: TXRST Position */
-#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART FIFO: TXRST Mask */
-
-#define UART_FIFO_RFITL_Pos (4) /*!< UART FIFO: RFITL Position */
-#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART FIFO: RFITL Mask */
-
-#define UART_FIFO_RXOFF_Pos (8) /*!< UART FIFO: RXOFF Position */
-#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART FIFO: RXOFF Mask */
-
-#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART FIFO: RTSTRGLV Position */
-#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART FIFO: RTSTRGLV Mask */
-
-#define UART_LINE_WLS_Pos (0) /*!< UART LINE: WLS Position */
-#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART LINE: WLS Mask */
-
-#define UART_LINE_NSB_Pos (2) /*!< UART LINE: NSB Position */
-#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART LINE: NSB Mask */
-
-#define UART_LINE_PBE_Pos (3) /*!< UART LINE: PBE Position */
-#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART LINE: PBE Mask */
-
-#define UART_LINE_EPE_Pos (4) /*!< UART LINE: EPE Position */
-#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART LINE: EPE Mask */
-
-#define UART_LINE_SPE_Pos (5) /*!< UART LINE: SPE Position */
-#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART LINE: SPE Mask */
-
-#define UART_LINE_BCB_Pos (6) /*!< UART LINE: BCB Position */
-#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART LINE: BCB Mask */
-
-#define UART_MODEM_RTS_Pos (1) /*!< UART MODEM: RTS Position */
-#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART MODEM: RTS Mask */
-
-#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART MODEM: RTSACTLV Position */
-#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART MODEM: RTSACTLV Mask */
-
-#define UART_MODEM_RTSSTS_Pos (13) /*!< UART MODEM: RTSSTS Position */
-#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART MODEM: RTSSTS Mask */
-
-#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART MODEMSTS: CTSDETF Position */
-#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART MODEMSTS: CTSDETF Mask */
-
-#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART MODEMSTS: CTSSTS Position */
-#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART MODEMSTS: CTSSTS Mask */
-
-#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART MODEMSTS: CTSACTLV Position */
-#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART MODEMSTS: CTSACTLV Mask */
-
-#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART FIFOSTS: RXOVIF Position */
-#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART FIFOSTS: RXOVIF Mask */
-
-#define UART_FIFOSTS_SCERR_Pos (2) /*!< UART FIFOSTS: SCERR Position */
-#define UART_FIFOSTS_SCERR_Msk (0x1ul << UART_FIFOSTS_SCERR_Pos) /*!< UART FIFOSTS: SCERR Mask */
-
-#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART FIFOSTS: ADDRDETF Position */
-#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART FIFOSTS: ADDRDETF Mask */
-
-#define UART_FIFOSTS_PEF_Pos (4) /*!< UART FIFOSTS: PEF Position */
-#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART FIFOSTS: PEF Mask */
-
-#define UART_FIFOSTS_FEF_Pos (5) /*!< UART FIFOSTS: FEF Position */
-#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART FIFOSTS: FEF Mask */
-
-#define UART_FIFOSTS_BIF_Pos (6) /*!< UART FIFOSTS: BIF Position */
-#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART FIFOSTS: BIF Mask */
-
-#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART FIFOSTS: RXPTR Position */
-#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART FIFOSTS: RXPTR Mask */
-
-#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART FIFOSTS: RXEMPTY Position */
-#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART FIFOSTS: RXEMPTY Mask */
-
-#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART FIFOSTS: RXFULL Position */
-#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART FIFOSTS: RXFULL Mask */
-
-#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART FIFOSTS: TXPTR Position */
-#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART FIFOSTS: TXPTR Mask */
-
-#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART FIFOSTS: TXEMPTY Position */
-#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART FIFOSTS: TXEMPTY Mask */
-
-#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART FIFOSTS: TXFULL Position */
-#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART FIFOSTS: TXFULL Mask */
-
-#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART FIFOSTS: TXOVIF Position */
-#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART FIFOSTS: TXOVIF Mask */
-
-#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART FIFOSTS: TXEMPTYF Position */
-#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART FIFOSTS: TXEMPTYF Mask */
-
-#define UART_INTSTS_RDAIF_Pos (0) /*!< UART INTSTS: RDAIF Position */
-#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART INTSTS: RDAIF Mask */
-
-#define UART_INTSTS_THREIF_Pos (1) /*!< UART INTSTS: THREIF Position */
-#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART INTSTS: THREIF Mask */
-
-#define UART_INTSTS_RLSIF_Pos (2) /*!< UART INTSTS: RLSIF Position */
-#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART INTSTS: RLSIF Mask */
-
-#define UART_INTSTS_MODENIF_Pos (3) /*!< UART INTSTS: MODENIF Position */
-#define UART_INTSTS_MODENIF_Msk (0x1ul << UART_INTSTS_MODENIF_Pos) /*!< UART INTSTS: MODENIF Mask */
-
-#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART INTSTS: RXTOIF Position */
-#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART INTSTS: RXTOIF Mask */
-
-#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART INTSTS: BUFERRIF Position */
-#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART INTSTS: BUFERRIF Mask */
-
-#define UART_INTSTS_LINIF_Pos (7) /*!< UART INTSTS: LINIF Position */
-#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART INTSTS: LINIF Mask */
-
-#define UART_INTSTS_RDAINT_Pos (8) /*!< UART INTSTS: RDAINT Position */
-#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART INTSTS: RDAINT Mask */
-
-#define UART_INTSTS_THREINT_Pos (9) /*!< UART INTSTS: THERINT Position */
-#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART INTSTS: THERINT Mask */
-
-#define UART_INTSTS_RLSINT_Pos (10) /*!< UART INTSTS: RLSINT Position */
-#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART INTSTS: RLSINT Mask */
-
-#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART INTSTS: MODEMINT Position */
-#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART INTSTS: MODEMINT Mask */
-
-#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART INTSTS: RXTOINT Position */
-#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART INTSTS: RXTOINT Mask */
-
-#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART INTSTS: BUFERRINT Position */
-#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART INTSTS: BUFERRINT Mask */
-
-#define UART_INTSTS_LININT_Pos (15) /*!< UART INTSTS: LININT Position */
-#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART INTSTS: LININT Mask */
-
-#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART INTSTS: HWRLSIF Position */
-#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART INTSTS: HWRLSIF Mask */
-
-#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART INTSTS: HWMODIF Position */
-#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART INTSTS: HWMODIF Mask */
-
-#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART INTSTS: HWTOIF Position */
-#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART INTSTS: HWTOIF Mask */
-
-#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART INTSTS: HWBUFEIF Position */
-#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART INTSTS: HWBUFEIF Mask */
-
-#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART INTSTS: HWRLSINT Position */
-#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART INTSTS: HWRLSINT Mask */
-
-#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART INTSTS: HWMODINT Position */
-#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART INTSTS: HWMODINT Mask */
-
-#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART INTSTS: HWTOINT Position */
-#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART INTSTS: HWTOINT Mask */
-
-#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART INTSTS: HWBUFEINT Position */
-#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART INTSTS: HWBUFEINT Mask */
-
-#define UART_TOUT_TOIC_Pos (0) /*!< UART TOUT: TOIC Position */
-#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART TOUT: TOIC Mask */
-
-#define UART_TOUT_DLY_Pos (8) /*!< UART TOUT: DLY Position */
-#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART TOUT: DLY Mask */
-
-#define UART_BAUD_BRD_Pos (0) /*!< UART BAUD: BRD Position */
-#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART BAUD: BRD Mask */
-
-#define UART_BAUD_EDIVM1_Pos (24) /*!< UART BAUD: EDIVM1 Position */
-#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART BAUD: EDIVM1 Mask */
-
-#define UART_BAUD_BAUDM0_Pos (28) /*!< UART BAUD: BAUDM0 Position */
-#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART BAUD: BAUDM0 Mask */
-
-#define UART_BAUD_BAUDM1_Pos (29) /*!< UART BAUD: BAUDM1 Position */
-#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART BAUD: BAUDM1 Mask */
-
-#define UART_IRDA_TXEN_Pos (1) /*!< UART IRDA: TXEN Position */
-#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART IRDA: TXEN Mask */
-
-#define UART_IRDA_TXINV_Pos (5) /*!< UART IRDA: TXINV Position */
-#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART IRDA: TXINV Mask */
-
-#define UART_IRDA_RXINV_Pos (6) /*!< UART IRDA: RXINV Position */
-#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART IRDA: RXINV Mask */
-
-#define UART_IRDA_FIXPULSE_Pos (7) /*!< UART IRDA: FIXPULSE Position */
-#define UART_IRDA_FIXPULSE_Msk (0x1ul << UART_IRDA_FIXPULSE_Pos) /*!< UART IRDA: FIXPULSE Mask */
-
-#define UART_ALTCTL_BKFL_Pos (0) /*!< UART ALTCTL: BKFL Position */
-#define UART_ALTCTL_BKFL_Msk (0xful << UART_ALTCTL_BKFL_Pos) /*!< UART ALTCTL: BKFL Mask */
-
-#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART ALTCTL: LINRXEN Position */
-#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART ALTCTL: LINRXEN Mask */
-
-#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART ALTCTL: LINTXEN Position */
-#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART ALTCTL: LINTXEN Mask */
-
-#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART ALTCTL: RS485NMM Position */
-#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART ALTCTL: RS485NMM Mask */
-
-#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART ALTCTL: RS485AAD Position */
-#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART ALTCTL: RS485AAD Mask */
-
-#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART ALTCTL: RS485AUD Position */
-#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART ALTCTL: RS485AUD Mask */
-
-#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART ALTCTL: ADDRDEN Position */
-#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART ALTCTL: ADDRDEN Mask */
-
-#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART ALTCTL: ADDRMV Position */
-#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART ALTCTL: ADDRMV Mask */
-
-#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART FUNCSEL: FUNCSEL Position */
-#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART FUNCSEL: FUNCSEL Mask */
-
-#define UART_LINCTL_SLVEN_Pos (0) /*!< UART LINCTL: SLVEN Position */
-#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART LINCTL: SLVEN Mask */
-
-#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART LINCTL: SLVHDEN Position */
-#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART LINCTL: SLVHDEN Mask */
-
-#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART LINCTL: SLVAREN Position */
-#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART LINCTL: SLVAREN Mask */
-
-#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART LINCTL: SLVDUEN Position */
-#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART LINCTL: SLVDUEN Mask */
-
-#define UART_LINCTL_MUTE_Pos (4) /*!< UART LINCTL: MUTE Position */
-#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART LINCTL: MUTE Mask */
-
-#define UART_LINCTL_SENDH_Pos (8) /*!< UART LINCTL: SENDH Position */
-#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART LINCTL: SENDH Mask */
-
-#define UART_LINCTL_IDPEN_Pos (9) /*!< UART LINCTL: IDPEN Position */
-#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART LINCTL: IDPEN Mask */
-
-#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART LINCTL: BRKDETEN Position */
-#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART LINCTL: BRKDETEN Mask */
-
-#define UART_LINCTL_RXOFF_Pos (11) /*!< UART LINCTL: RXOFF Position */
-#define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /*!< UART LINCTL: RXOFF Mask */
-
-#define UART_LINCTL_BITERREN_Pos (12) /*!< UART LINCTL: BITERREN Position */
-#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART LINCTL: BITERREN Mask */
-
-#define UART_LINCTL_BRKFL_Pos (16) /*!< UART LINCTL: BRKFL Position */
-#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART LINCTL: BRKFL Mask */
-
-#define UART_LINCTL_BSL_Pos (20) /*!< UART LINCTL: BSL Position */
-#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART LINCTL: BSL Mask */
-
-#define UART_LINCTL_HSEL_Pos (22) /*!< UART LINCTL: HSEL Position */
-#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART LINCTL: HSEL Mask */
-
-#define UART_LINCTL_PID_Pos (24) /*!< UART LINCTL: PID Position */
-#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART LINCTL: PID Mask */
-
-#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART LINSTS: SLVHDETF Position */
-#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART LINSTS: SLVHDETF Mask */
-
-#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART LINSTS: SLVHEF Position */
-#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART LINSTS: SLVHEF Mask */
-
-#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART LINSTS: SLVIDPEF Position */
-#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART LINSTS: SLVIDPEF Mask */
-
-#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART LINSTS: SLVSYNCF Position */
-#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART LINSTS: SLVSYNCF Mask */
-
-#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART LINSTS: BRKDETF Position */
-#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART LINSTS: BRKDETF Mask */
-
-#define UART_LINSTS_BITEF_Pos (9) /*!< UART LINSTS: BITEF Position */
-#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART LINSTS: BITEF Mask */
-
-#define UART_LINDEBUG_DEVERRF_Pos (0) /*!< UART LINDEBUG: DEVERRF Position */
-#define UART_LINDEBUG_DEVERRF_Msk (0x1ul << UART_LINDEBUG_DEVERRF_Pos) /*!< UART LINDEBUG: DEVERRF Mask */
-
-#define UART_LINDEBUG_TOF_Pos (1) /*!< UART LINDEBUG: TOF Position */
-#define UART_LINDEBUG_TOF_Msk (0x1ul << UART_LINDEBUG_TOF_Pos) /*!< UART LINDEBUG: TOF Mask */
-
-#define UART_LINDEBUG_FRAMEERRF_Pos (2) /*!< UART LINDEBUG: FRAMEERRF Position */
-#define UART_LINDEBUG_FRAMEERRF_Msk (0x1ul << UART_LINDEBUG_FRAMEERRF_Pos) /*!< UART LINDEBUG: FRAMEERRF Mask */
-
-#define UART_LINDEBUG_SYNCERRF_Pos (3) /*!< UART LINDEBUG: SYNCERRF Position */
-#define UART_LINDEBUG_SYNCERRF_Msk (0x1ul << UART_LINDEBUG_SYNCERRF_Pos) /*!< UART LINDEBUG: SYNCERRF Mask */
-
-/**@}*/ /* UART_CONST */
-/**@}*/ /* end of UART register group */
-
-
-/*---------------------- USB Host Controller -------------------------*/
-/**
- @addtogroup USBH USB Host Controller(USBH)
- Memory Mapped Structure for USBH Controller
-@{ */
-
-typedef struct {
- /**
- * HcRevision
- * ===================================================================================================
- * Offset: 0x00 Host Controller Revision Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |REV |Revision
- * | | |Indicates the Open HCI Specification revision number implemented by the Hardware.
- * | | |Host Controller supports 1.1 specification.
- * | | |(X.Y = XYh).
- */
- __I uint32_t HcRevision;
-
- /**
- * HcControl
- * ===================================================================================================
- * Offset: 0x04 Host Controller Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |CBSR |Control Bulk Service Ratio
- * | | |Specifies the number of Control Endpoints serviced for every Bulk Endpoint.
- * | | |Encoding is N-1 where N is the number of Control Endpoints (i.e.
- * | | |'00' = 1 Control Endpoint; '11' = 3 Control Endpoints).
- * |[2] |PLE |Periodic List Enable Control
- * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list.
- * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
- * |[3] |IE |Isochronous List Enable Control
- * | | |When cleared, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced).
- * | | |While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED.
- * |[4] |CLE |Control List Enable Control
- * | | |When set, this bit enables processing of the Control list.
- * |[5] |BLE |Bulk List Enable Control
- * | | |When set, this bit enables processing of the Bulk list.
- * |[6:7] |HCFS |Host Controller Functional State
- * | | |This field sets the Host Controller state.
- * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
- * | | |States are:.
- * | | |00 = USBSUSPEND.
- * | | |01 = USBOPERATIONAL.
- * | | |10 = USBRESUME.
- * | | |11 = USBRESET.
- * |[9] |RWC |Remote Wake-Up Connected
- * | | |This bit indicated whether the HC supports a remote wake-up signal.
- * | | |This implementation does not support any such signal.
- * | | |The bit is hard-coded to '0.'.
- * |[10] |RWE |Remote Wake-Up Connected Enable Control
- * | | |If a remote wake-up signal is supported, this bit enables that operation.
- * | | |Since there is no remote wake-up signal supported, this bit is ignored.
- */
- __IO uint32_t HcControl;
-
- /**
- * HcCommandStatus
- * ===================================================================================================
- * Offset: 0x08 Host Controller Command Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |HCR |Host Controller Reset
- * | | |This bit is set to initiate the software reset.
- * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
- * |[1] |CLF |Control List Filled
- * | | |Set to indicate there is an active ED on the Control List.
- * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
- * |[2] |BLF |Bulk List Filled
- * | | |Set to indicate there is an active ED on the Bulk List.
- * | | |The bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk List.
- * |[16:17] |SOC |Schedule Overrun Count
- * | | |This field is incremented every time the SchedulingOverrun bit in HcInterruptStatus is set.
- * | | |The count wraps from '11' to '00'.
- */
- __IO uint32_t HcCommandStatus;
-
- /**
- * HcInterruptStatus
- * ===================================================================================================
- * Offset: 0x0C Host Controller Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SO |Scheduling Overrun
- * | | |Set when the List Processor determines a Schedule Overrun has occurred.
- * |[1] |WDH |Write Back Done Head
- * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
- * |[2] |SF |Start Of Frame
- * | | |Set when the Frame Management block signals a 'Start of Frame' event.
- * |[3] |RD |Resume Detected
- * | | |Set when Host Controller detects resume signaling on a downstream port.
- * |[4] |UE |Unrecoverable Error
- * | | |This event is not implemented and is hard-coded to '0.' Writes are ignored.
- * |[5] |FNOF |Frame Number Overflow
- * | | |Set when bit 15 of Frame Number changes value.
- * |[6] |RHSC |Root Hub Status Change
- * | | |This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed.
- */
- __IO uint32_t HcInterruptStatus;
-
- /**
- * HcInterruptEnable
- * ===================================================================================================
- * Offset: 0x10 Host Controller Interrupt Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SO |Scheduling Overrun Enable Control
- * | | |0 = The interrupt function Disabled.
- * | | |1 = Interrupt generation Enabled due to Scheduling Overrun.
- * |[1] |WDH |Write Back Done Head Enable Control
- * | | |0 = The interrupt function Disabled.
- * | | |1 = Interrupt generation Enabled due to Write-back Done Head.
- * |[2] |SF |Start Of Frame Enable Control
- * | | |0 = The interrupt function Disabled.
- * | | |1 = interrupt generation Enabled due to Start of Frame.
- * |[3] |RD |Resume Detected Enable Control
- * | | |0 = The interrupt function Disabled.
- * | | |1 = interrupt generation Enabled due to Resume Detected.
- * |[4] |UE |Unrecoverable Error Enable Control
- * | | |This event is not implemented. All writes to this bit are ignored.
- * |[5] |FNO |Frame Number Overflow Enable Control
- * | | |0 = The interrupt function Disabled.
- * | | |1 = Interrupt generation Enabled due to Frame Number Overflow.
- * |[6] |RHSC |Root Hub Status Change Enable Control
- * | | |0 = The interrupt function Disabled.
- * | | |1 = interrupt generation Enabled due to Root Hub Status Change.
- * |[31] |MIE |Master Interrupt Enable Control
- * | | |This bit is a global interrupt enable.
- * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
- */
- __IO uint32_t HcInterruptEnable;
-
- /**
- * HcInterruptDisable
- * ===================================================================================================
- * Offset: 0x14 Host Controller Interrupt Disable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SO |Scheduling Overrun Disable Control
- * | | |0 = No effect.
- * | | |1 = Interrupt generation Disabled due to Scheduling Overrun.
- * |[1] |WDH |Write Back Done Head Disable Control
- * | | |0 = No effect.
- * | | |1 = Interrupt generation Disabled due to Write-back Done Head.
- * |[2] |SF |Start Of Frame Disable Control
- * | | |0 = No effect.
- * | | |1 = Interrupt generation Disabled due to Start of Frame.
- * |[3] |RD |Resume Detected Disable Control
- * | | |0 = No effect.
- * | | |1 = Interrupt generation Disabled due to Resume Detected.
- * |[4] |UE |Unrecoverable Error Disable Control
- * | | |This event is not implemented. All writes to this bit are ignored.
- * |[5] |FNO |Frame Number Overflow Disable Control
- * | | |0 = No effect.
- * | | |1 = Interrupt generation Disabled due to Frame Number Overflow.
- * |[6] |RHSC |Root Hub Status Change Disable Control
- * | | |0 = No effect.
- * | | |1 = Interrupt generation Disabled due to Root Hub Status Change.
- * |[31] |MIE |Master Interrupt Disable Control
- * | | |Global interrupt disable. Writing '1' to disable all interrupts.
- */
- __IO uint32_t HcInterruptDisable;
-
- /**
- * HcHCCA
- * ===================================================================================================
- * Offset: 0x18 Host Controller Communication Area Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8:31] |HCCA |Host Controller Communication Area
- * | | |Pointer to HCCA base address.
- */
- __IO uint32_t HcHCCA;
-
- /**
- * HcPeriodCurrentED
- * ===================================================================================================
- * Offset: 0x1C Host Controller Period Current ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:31] |PCED |Periodic Current ED
- * | | |Pointer to the current Periodic List ED.
- */
- __IO uint32_t HcPeriodCurrentED;
-
- /**
- * HcControlHeadED
- * ===================================================================================================
- * Offset: 0x20 Host Controller Control Head ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:31] |CHED |Control Head ED
- * | | |Pointer to the Control List Head ED.
- */
- __IO uint32_t HcControlHeadED;
-
- /**
- * HcControlCurrentED
- * ===================================================================================================
- * Offset: 0x24 Host Controller Control Current ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:31] |CCED |Control Current Head ED
- * | | |Pointer to the current Control List Head ED.
- */
- __IO uint32_t HcControlCurrentED;
-
- /**
- * HcBulkHeadED
- * ===================================================================================================
- * Offset: 0x28 Host Controller Bulk Head ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:31] |BHED |Bulk Head ED
- * | | |Pointer to the Bulk List Head ED.
- */
- __IO uint32_t HcBulkHeadED;
-
- /**
- * HcBulkCurrentED
- * ===================================================================================================
- * Offset: 0x2C Host Controller Bulk Current ED Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:31] |BCED |Bulk Current Head ED
- * | | |Pointer to the current Bulk List Head ED.
- */
- __IO uint32_t HcBulkCurrentED;
-
- /**
- * HcDoneHead
- * ===================================================================================================
- * Offset: 0x30 Host Controller Done Head Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[4:31] |DH |Done Head
- * | | |Pointer to the current Done List Head ED.
- */
- __IO uint32_t HcDoneHead;
-
- /**
- * HcFmInterval
- * ===================================================================================================
- * Offset: 0x34 Host Controller Frame Interval Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:13] |FI |Frame Interval
- * | | |This field specifies the length of a frame as (bit times - 1).
- * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
- * |[16:30] |FSMPS |FS Largest Data Packet
- * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
- * |[31] |FIT |Frame Interval Toggle
- * | | |This bit is toggled by HCD when it loads a new value into Frame Interval.
- */
- __IO uint32_t HcFmInterval;
-
- /**
- * HcFmRemaining
- * ===================================================================================================
- * Offset: 0x38 Host Controller Frame Remaining Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:13] |FR |Frame Remaining
- * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
- * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
- * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
- * |[31] |FRT |Frame Remaining Toggle
- * | | |Loaded with Frame Interval Toggle when FrameRemaining is loaded.
- */
- __I uint32_t HcFmRemaining;
-
- /**
- * HcFmNumber
- * ===================================================================================================
- * Offset: 0x3C Host Controller Frame Number Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |FN |Frame Number
- * | | |This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining.
- * | | |The count rolls over from 'FFFFh' to '0h.'.
- */
- __I uint32_t HcFmNumber;
-
- /**
- * HcPeriodicStart
- * ===================================================================================================
- * Offset: 0x40 Host Controller Periodic Start Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:13] |PS |Periodic Start
- * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
- */
- __IO uint32_t HcPeriodicStart;
-
- /**
- * HcLSThreshold
- * ===================================================================================================
- * Offset: 0x44 Host Controller Low-speed Threshold Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |LST |Low-Speed Threshold
- * | | |This field contains a value which is compared to the FrameRemaining field prior to initiating a Low-speed transaction.
- * | | |The transaction is started only if FrameRemaining >= this field.
- * | | |The value is calculated by HCD with the consideration of transmission and setup overhead.
- */
- __IO uint32_t HcLSThreshold;
-
- /**
- * HcRhDescriptorA
- * ===================================================================================================
- * Offset: 0x48 Host Controller Root Hub Descriptor A Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |NDP |Number Downstream Ports
- * | | |Root Hub supports two downstream ports. It's 2 in this Root Hub.
- * |[8] |PSM |Power Switching Mode
- * | | |Global power switching mode implemented in Root Hub.
- * | | |This bit is only valid when NPS bit is cleared.
- * | | |This bit should be written '0'.
- * | | |0 = Global Switching.
- * | | |1 = Individual Switching.
- * |[9] |NPS |No Power Switching
- * | | |Global power switching implemented in Root Hub.
- * | | |This bit should be written to support the external system port power switching implementation.
- * | | |0 = Ports are power switched.
- * | | |1 = Ports are always powered on.
- * |[10] |DT |Device Type
- * | | |The OHCI Root Hub is not a compound device.
- * |[11] |OCPM |Overcurrent Protection Mode
- * | | |Global overcurrent reporting implemented in Root Hub.
- * | | |This bit should be written 0 and is only valid when NOCP bit is cleared.
- * | | |0 = Global Overcurrent.
- * | | |1 = Individual Overcurrent.
- * |[12] |NOCP |No Overcurrent Protection
- * | | |Global overcurrent reporting implemented in Root Hub.
- * | | |This bit should be written to support the external system port overcurrent implementation.
- * | | |0 = Overcurrent status is reported.
- * | | |1 = Overcurrent status is not reported.
- * |[24:31] |POTGT |Power On To Power Good Time
- * | | |This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms.
- * | | |Only bits [25:24] are implemented as R/W.
- * | | |The remaining bits are read only as '0'.
- * | | |It is not expected that these bits be written to anything other than 1h, but limited adjustment is provided.
- * | | |This field should be written to support system implementation.
- * | | |This field should always be written to a non-zero value.
- */
- __IO uint32_t HcRhDescriptorA;
-
- /**
- * HcRhDescriptorB
- * ===================================================================================================
- * Offset: 0x4C Host Controller Root Hub Descriptor B Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |DR |Device Removable
- * | | |Root Hub ports default to removable devices.
- * | | |0 = Device not removable.
- * | | |1 = Device removable.
- * | | |Port Bit relationship:
- * | | |DevRemove[0] = Reserved.
- * | | |DevRemove[1] = Port 1.
- * | | |DevRemove[2] = Port 2.
- */
- __IO uint32_t HcRhDescriptorB;
-
- /**
- * HcRhStatus
- * ===================================================================================================
- * Offset: 0x50 Host Controller Root Hub Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |LPS |LocalPowerStatus (Read)
- * | | |Not Supported. Always read '0'.
- * | | |ClearGlobalPower (Write)
- * | | |Writing '1' issues a ClearGlobalPower command to the ports. Writing '0' has no effect.
- * |[1] |OCI |Overcurrent Indicator
- * | | |This bit reflects the state of the OVRCUR pin.
- * | | |This field is only valid if NOCP (RHDESA[12]) and OCPM (RHDESA[11]) are cleared.
- * | | |0 = No overcurrent condition.
- * | | |1 = Overcurrent condition.
- * |[15] |DRWE |Device Remote Wake-Up Enable Control (Read)
- * | | |This bit enables ports' CC (HcRhPtr[0]) as a remote wake-up event.
- * | | |0 = Disabled.
- * | | |1 = Enabled.
- * | | |Set Remote Wake-up Enable Control (Write)
- * | | |Writing 1' sets DRWEn. Writing '0' has no effect.
- * |[16] |LPSC |Local Power Status Change (Read)
- * | | |Not supported. Always read '0'.
- * | | |SetGlobalPower (Write)
- * | | |Writing '1' issues a SetGlobalPower command to the ports. Writing '0' has no effect.
- * |[17] |OCIC |Overcurrent Indicator Change
- * | | |This bit is set when OC bit changes.
- * | | |Writing '1' clears this bit. Writing '0' has no effect.
- * |[31] |CRWE |Clear Remote Wake-Up Enable Control
- * | | |Writing '1' to this bit clears DRWEn (HcRhStatus[15]). Writing '0' has no effect.
- */
- __IO uint32_t HcRhStatus;
-
- /**
- * HcRhPortStatus1/HcRhPortStatus2
- * ===================================================================================================
- * Offset: 0x54,0x58 Host Controller Root Hub Port Status [1/2]
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |CCS |Current Connect Status (Read)
- * | | |0 = No device connected.
- * | | |1 = Device connected.
- * | | |Clear Port Enable Control (Write)
- * | | |Writing '1' a clears PE. Writing '0' has no effect.
- * |[1] |PES |Port Enable Status (Read)
- * | | |0 = Port Disabled.
- * | | |1 = Port Enabled.
- * | | |SetPortEnable (Write)
- * | | |Writing '1' sets PE. Writing '0' has no effect.
- * |[2] |PSS |PortSuspendStatus (Read)
- * | | |0 = Port is not suspended.
- * | | |1 = Port is selectively suspended.
- * | | |SetPortSuspend (Write)
- * | | |Writing '1' sets PortSuspendStatus. Writing '0' has no effect.
- * |[3] |POCI |PortOverCurrentIndicator (Read)
- * | | |Root Hub supports global overcurrent reporting.
- * | | |This bit reflects the state of the OVRCUR pin dedicated to this port.
- * | | |This field is only valid if NOCP (RHDESA[12]) is cleared and OCPM (RHDESA[11]) is set.
- * | | |0 = No overcurrent condition.
- * | | |1 = Overcurrent condition.
- * | | |ClearPortSuspend (Write)
- * | | |Writing '1' initiates the selective resume sequence for the port. Writing '0' has no effect.
- * |[4] |PRS |PortResetStatus (Read)
- * | | |This bit reflects the power state of the port regardless of the power switching mode.
- * | | |0 = Port reset signal is not active.
- * | | |1 = Port reset signal is active.
- * | | |SetPortReset (Write)
- * | | |Writing '1' sets PR. Writing '0' has no effect.
- * |[8] |PPS |PortPowerStatus (Read)
- * | | |This bit reflects the power state of the port regardless of the power switching mode.
- * | | |0 = Port power is off.
- * | | |1 = Port power is on.
- * | | |Note: If NPS (RHDESA[9]) is set, this bit is always read as '1'.
- * | | |SetPortPower (Write)
- * | | |Writing '1' sets PPS. Writing '0' has no effect.
- * |[9] |LSDA |LowSpeedDeviceAttached (Read)
- * | | |This bit defines the speed (and bud idle) of the attached device. It is only valid when CC bit is set.
- * | | |0 = Full Speed device.
- * | | |1 = Low-speed device.
- * | | |ClearPortPower (Write)
- * | | |Writing '1' clears PPS bit. Writing '0' has no effect.
- * |[16] |CSC |Connect Status Change
- * | | |This bit indicates connect or disconnect event has been detected.
- * | | |Writing '1' clears this bit.
- * | | |Writing '0' has no effect.
- * | | |0 = No connect/disconnect event.
- * | | |1 = Hardware detection of connect/disconnect event.
- * | | |Note: If DevRemove (HcRhDescriptorB[2:0]) is set, this bit resets to '1'.
- * |[17] |PESC |Port Enable Status Change
- * | | |This bit indicates that the port has been disabled due to a hardware event (cleared PE bit).
- * | | |0 = No port enable change event.
- * | | |1 = Port enable state has been changed.
- * |[18] |PSSC |Port Reset Status Change
- * | | |This bit indicates the completion of the selective resume sequence for the port.
- * | | |0 = Port is not resumed.
- * | | |1 = Port resume is complete.
- * |[19] |OCIC |Port Overcurrent Indicator Change
- * | | |This bit is set when OC (HcRhStatus[1]) changes. Writing '1' clears this bit. Writing '0' has no effect.
- * |[20] |PRSC |Port Reset Status Change
- * | | |This bit indicates that the port reset signal has completed.
- * | | |0 = Port reset is not complete.
- * | | |1 = Port reset is complete.
- */
- __IO uint32_t HcRhPortStatus[2];
-
- uint32_t RESERVE0[105];
-
-
- /**
- * HcPhyControl
- * ===================================================================================================
- * Offset: 0x200 USB PHY Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[27] |STBYEN |USB Transceiver Standby Enable Control
- * | | |This bit controls if USB 1.1 transceiver could enter the standby mode to reduce power consumption.
- * | | |If this bit is low, the USB 1.1 transceiver would never enter the standby mode.
- * | | |If this bit is high, the USB 1.1 transceiver will enter standby mode while port is in power off state (port power is inactive).
- */
- __IO uint32_t HcPhyControl;
-
- /**
- * HcMiscControl
- * ===================================================================================================
- * Offset: 0x204 USB Operational Mode Enable Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |DBR16 |Data Buffer Region 16
- * | | |When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes.
- * |[1] |ABORT |AHB Bus ERROR Response
- * | | |This bit indicates there is an ERROR response received in AHB bus.
- * | | |0 = No ERROR response received.
- * | | |1 = ERROR response received.
- * |[3] |OCA |Overcurrent Active Low
- * | | |This bit controls the polarity of overcurrent flag from external power IC.
- * | | |0 = Overcurrent flag is high active.
- * | | |1 = Overcurrent flag is low active.
- * |[4] |PCAL |Port Power Control Active Low
- * | | |This bit controls the polarity of port power control to external power IC.
- * | | |0 = Port power control is high active.
- * | | |1 = Port power control is low active.
- * |[8] |SIEPD |SIE Pipeline Disable Control
- * | | |When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor.
- * | | |This is a fail safe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz.
- * |[16] |DPRT1 |Port 1 Disable Control
- * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
- * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
- * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
- * | | |0 = The connection between USB host controller and transceiver of port 1 is enabled.
- * | | |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
- * |[17] |DPRT2 |Port 2 Disable Control
- * | | |This bit controls if the connection between USB host controller and transceiver of port 2 is disabled.
- * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
- * | | |Set this bit high, the transceiver of port 2 will also be forced into the standby mode no matter what USB host controller operation is.
- * | | |0 = The connection between USB host controller and transceiver of port 2 is enabled.
- * | | |1 = The connection between USB host controller and transceiver of port 2 is disabled and the transceiver of port 2 will also be forced into the standby mode.
- */
- __IO uint32_t HcMiscControl;
-
-} USBH_T;
-
-/**
- @addtogroup USBH_CONST USBH Bit Field Definition
- Constant Definitions for USBH Controller
-@{ */
-
-#define USBH_HcRevision_REV_Pos (0) /*!< USBH HcRevision: REV Position */
-#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH HcRevision: REV Mask */
-
-#define USBH_HcControl_CBSR_Pos (0) /*!< USBH HcControl: CBSR Position */
-#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH HcControl: CBSR Mask */
-
-#define USBH_HcControl_PLE_Pos (2) /*!< USBH HcControl: CBSR Position */
-#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH HcControl: CBSR Mask */
-
-#define USBH_HcControl_IE_Pos (3) /*!< USBH HcControl: IE Position */
-#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH HcControl: IE Mask */
-
-#define USBH_HcControl_CLE_Pos (4) /*!< USBH HcControl: CLE Position */
-#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH HcControl: CLE Mask */
-
-#define USBH_HcControl_BLE_Pos (5) /*!< USBH HcControl: BLE Position */
-#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH HcControl: BLE Mask */
-
-#define USBH_HcControl_HCFS_Pos (6) /*!< USBH HcControl: HCFS Position */
-#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH HcControl: HCFS Mask */
-
-#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH HcCommandStatus: HCR Position */
-#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH HcCommandStatus: HCR Mask */
-
-#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH HcCommandStatus: CLF Position */
-#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH HcCommandStatus: CLF Mask */
-
-#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH HcCommandStatus: BLF Position */
-#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH HcCommandStatus: BLF Mask */
-
-#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH HcCommandStatus: SOC Position */
-#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH HcCommandStatus: SOC Mask */
-
-#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH HcInterruptStatus: SO Position */
-#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH HcInterruptStatus: SO Mask */
-
-#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH HcInterruptStatus: WDH Position */
-#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH HcInterruptStatus: WDH Mask */
-
-#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH HcInterruptStatus: SF Position */
-#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH HcInterruptStatus: SF Mask */
-
-#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH HcInterruptStatus: RD Position */
-#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH HcInterruptStatus: RD Mask */
-
-#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH HcInterruptStatus: FNO Position */
-#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH HcInterruptStatus: FNO Mask */
-
-#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH HcInterruptStatus: RHSC Position */
-#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH HcInterruptStatus: RHSC Mask */
-
-#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH HcInterruptEnable: SO Position */
-#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH HcInterruptEnable: SO Mask */
-
-#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH HcInterruptEnable: WDH Position */
-#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH HcInterruptEnable: WDH Mask */
-
-#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH HcInterruptEnable: SF Position */
-#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH HcInterruptEnable: SF Mask */
-
-#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH HcInterruptEnable: RD Position */
-#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH HcInterruptEnable: RD Mask */
-
-#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH HcInterruptEnable: FNO Position */
-#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH HcInterruptEnable: FNO Mask */
-
-#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH HcInterruptEnable: RHSC Position */
-#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH HcInterruptEnable: RHSC Mask */
-
-#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH HcInterruptEnable: MIE Position */
-#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH HcInterruptEnable: MIE Mask */
-
-#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH HcInterruptDisable: SO Position */
-#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH HcInterruptDisable: SO Mask */
-
-#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH HcInterruptDisable: WDH Position */
-#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH HcInterruptDisable: WDH Mask */
-
-#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH HcInterruptDisable: SF Position */
-#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH HcInterruptDisable: SF Mask */
-
-#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH HcInterruptDisable: RD Position */
-#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH HcInterruptDisable: RD Mask */
-
-#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH HcInterruptDisable: FNO Position */
-#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH HcInterruptDisable: FNO Mask */
-
-#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH HcInterruptDisable: RHSC Position */
-#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH HcInterruptDisable: RHSC Mask */
-
-#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH HcInterruptDisable: MIE Position */
-#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH HcInterruptDisable: MIE Mask */
-
-#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH HcHCCA: HCCA Position */
-#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH HcHCCA: HCCA Mask */
-
-#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH HcPeriodCurrentED: PCED Position */
-#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH HcPeriodCurrentED: PCED Mask */
-
-#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH HcControlHeadED: CHED Position */
-#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH HcControlHeadED: CHED Mask */
-
-#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH HcControlCurrentED: CCED Position */
-#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH HcControlCurrentED: CCED Mask */
-
-#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH HcBulkHeadED: BHED Position */
-#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH HcBulkHeadED: BHED Mask */
-
-#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH HcBulkCurrentED: BCED Position */
-#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH HcBulkCurrentED: BCED Mask */
-
-#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH HcDoneHead: DH Position */
-#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH HcDoneHead: DH Mask */
-
-#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH HcFmInterval: FI Position */
-#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH HcFmInterval: FI Mask */
-
-#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH HcFmInterval: FSMPS Position */
-#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH HcFmInterval: FSMPS Mask */
-
-#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH HcFmInterval: FIT Position */
-#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH HcFmInterval: FIT Mask */
-
-#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH HcFmRemaining: FR Position */
-#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH HcFmRemaining: FR Mask */
-
-#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH HcFmRemaining: FRT Position */
-#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH HcFmRemaining: FRT Mask */
-
-#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH HcFmNumber: FN Position */
-#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH HcFmNumber: FN Mask */
-
-#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH HcPeriodicStart: PS Position */
-#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH HcPeriodicStart: PS Mask */
-
-#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH HcLSThreshold: LST Position */
-#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH HcLSThreshold: LST Mask */
-
-#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH HcRhDescriptorA: NDP Position */
-#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH HcRhDescriptorA: NDP Mask */
-
-#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH HcRhDescriptorA: PSM Position */
-#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH HcRhDescriptorA: PSM Mask */
-
-#define USBH_HcRhDescriptorA_NPS_Pos (9) /*!< USBH HcRhDescriptorA: NPS Position */
-#define USBH_HcRhDescriptorA_NPS_Msk (0x1ul << USBH_HcRhDescriptorA_NPS_Pos) /*!< USBH HcRhDescriptorA: NPS Mask */
-
-#define USBH_HcRhDescriptorA_DT_Pos (10) /*!< USBH HcRhDescriptorA: DT Position */
-#define USBH_HcRhDescriptorA_DT_Msk (0x1ul << USBH_HcRhDescriptorA_DT_Pos) /*!< USBH HcRhDescriptorA: DT Mask */
-
-#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH HcRhDescriptorA: OCPM Position */
-#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH HcRhDescriptorA: OCPM Mask */
-
-#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH HcRhDescriptorA: NOCP Position */
-#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH HcRhDescriptorA: NOCP Mask */
-
-#define USBH_HcRhDescriptorA_POTPGT_Pos (24) /*!< USBH HcRhDescriptorA: POTPGT Position */
-#define USBH_HcRhDescriptorA_POTPGT_Msk (0xfful << USBH_HcRhDescriptorA_POTPGT_Pos) /*!< USBH HcRhDescriptorA: POTPGT Mask */
-
-#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH HcRhDescriptorB: PPCM Position */
-#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH HcRhDescriptorB: PPCM Mask */
-
-#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH HcRhStatus: LPS Position */
-#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH HcRhStatus: LPS Mask */
-
-#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH HcRhStatus: OCI Position */
-#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH HcRhStatus: OCI Mask */
-
-#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH HcRhStatus: DRWE Position */
-#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH HcRhStatus: DRWE Mask */
-
-#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH HcRhStatus: LPSC Position */
-#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH HcRhStatus: LPSC Mask */
-
-#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH HcRhStatus: OCIC Position */
-#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH HcRhStatus: OCIC Mask */
-
-#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH HcRhStatus: CRWE Position */
-#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH HcRhStatus: CRWE Mask */
-
-#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH HcRhPortStatus: CCS Position */
-#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH HcRhPortStatus: CCS Mask */
-
-#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH HcRhPortStatus: PES Position */
-#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH HcRhPortStatus: PES Mask */
-
-#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH HcRhPortStatus: PSS Position */
-#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH HcRhPortStatus: PSS Mask */
-
-#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH HcRhPortStatus: POCI Position */
-#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH HcRhPortStatus: POCI Mask */
-
-#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH HcRhPortStatus: PRS Position */
-#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH HcRhPortStatus: PRS Mask */
-
-#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH HcRhPortStatus: PPS Position */
-#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH HcRhPortStatus: PPS Mask */
-
-#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH HcRhPortStatus: LSDA Position */
-#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH HcRhPortStatus: LSDA Mask */
-
-#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH HcRhPortStatus: CSC Position */
-#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH HcRhPortStatus: CSC Mask */
-
-#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH HcRhPortStatus: PESC Position */
-#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH HcRhPortStatus: PESC Mask */
-
-#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH HcRhPortStatus: PSSC Position */
-#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH HcRhPortStatus: PSSC Mask */
-
-#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH HcRhPortStatus: OCIC Position */
-#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH HcRhPortStatus: OCIC Mask */
-
-#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH HcRhPortStatus: PRSC Position */
-#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH HcRhPortStatus: PRSC Mask */
-
-#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH HcPhyControl: STBYEN Position */
-#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH HcPhyControl: STBYEN Mask */
-
-#define USBH_HcMiscControl_DBR16_Pos (0) /*!< USBH HcMiscControl: DBR16 Position */
-#define USBH_HcMiscControl_DBR16_Msk (0x1ul << USBH_HcMiscControl_DBR16_Pos) /*!< USBH HcMiscControl: DBR16 Mask */
-
-#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH HcMiscControl: ABORT Position */
-#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH HcMiscControl: ABORT Mask */
-
-#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH HcMiscControl: OCAL Position */
-#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH HcMiscControl: OCAL Mask */
-
-#define USBH_HcMiscControl_PCAL_Pos (4) /*!< USBH HcMiscControl: PCAL Position */
-#define USBH_HcMiscControl_PCAL_Msk (0x1ul << USBH_HcMiscControl_PCAL_Pos) /*!< USBH HcMiscControl: PCAL Mask */
-
-#define USBH_HcMiscControl_SIEPD_Pos (8) /*!< USBH HcMiscControl: SIEPD Position */
-#define USBH_HcMiscControl_SIEPD_Msk (0x1ul << USBH_HcMiscControl_SIEPD_Pos) /*!< USBH HcMiscControl: SIEPD Mask */
-
-#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH HcMiscControl: DPRT1 Position */
-#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH HcMiscControl: DPRT1 Mask */
-
-#define USBH_HcMiscControl_DPRT2_Pos (17) /*!< USBH HcMiscControl: DPRT2 Position */
-#define USBH_HcMiscControl_DPRT2_Msk (0x1ul << USBH_HcMiscControl_DPRT2_Pos) /*!< USBH HcMiscControl: DPRT2 Mask */
-
-/**@}*/ /* USBH_CONST */
-/**@}*/ /* end of USBH register group */
-
-
-/*---------------------- USB Device Controller -------------------------*/
-/**
- @addtogroup USBD USB Device Controller(USBD)
- Memory Mapped Structure for USBD Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * GINTSTS
- * ===================================================================================================
- * Offset: 0x00 Interrupt Status Low Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |USBIF |USB Interrupt
- * | | |This bit conveys the interrupt status for USB specific events endpoint.
- * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[1] |CEPIF |Control Endpoint Interrupt
- * | | |This bit conveys the interrupt status for control endpoint.
- * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[2] |EPAIF |Endpoints A Interrupt
- * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[3] |EPBIF |Endpoints B Interrupt
- * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[4] |EPCIF |Endpoints C Interrupt
- * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[5] |EPDIF |Endpoints D Interrupt
- * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[6] |EPEIF |Endpoints E Interrupt
- * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[7] |EPFIF |Endpoints F Interrupt
- * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[8] |EPGIF |Endpoints G Interrupt
- * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[9] |EPHIF |Endpoints H Interrupt
- * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[10] |EPIIF |Endpoints I Interrupt
- * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[11] |EPJIF |Endpoints J Interrupt
- * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[12] |EPKIF |Endpoints K Interrupt
- * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- * |[13] |EPLIF |Endpoints L Interrupt
- * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
- * | | |0 = No interrupt event occurred.
- * | | |1 = The related interrupt event is occurred.
- */
- __I uint32_t GINTSTS;
- uint32_t RESERVE0[1];
-
-
- /**
- * GINTEN
- * ===================================================================================================
- * Offset: 0x08 Interrupt Enable Low Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |USBIE |USB Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[1] |CEPIE |Control Endpoint Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[2] |EPAIE |Interrupt Enable Control For Endpoint A
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[3] |EPBIE |Interrupt Enable Control For Endpoint B
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[4] |EPCIE |Interrupt Enable Control For Endpoint C
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[5] |EPDIE |Interrupt Enable Control For Endpoint D
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[6] |EPEIE |Interrupt Enable Control For Endpoint E
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[7] |EPFIE |Interrupt Enable Control For Endpoint F
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[8] |EPGIE |Interrupt Enable Control For Endpoint G
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[9] |EPHIE |Interrupt Enable Control For Endpoint H
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[10] |EPIIE |Interrupt Enable Control For Endpoint I
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[11] |EPJIE |Interrupt Enable Control For Endpoint J
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[12] |EPKIE |Interrupt Enable Control For Endpoint K
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- * |[13] |EPLIE |Interrupt Enable Control For Endpoint L
- * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L
- * | | |0 = The related interrupt Disabled.
- * | | |1 = The related interrupt Enabled.
- */
- __IO uint32_t GINTEN;
- uint32_t RESERVE1[1];
-
-
- /**
- * BUSINTSTS
- * ===================================================================================================
- * Offset: 0x10 USB Bus Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SOFIF |SOF Receive Control
- * | | |This bit indicates when a start-of-frame packet has been received.
- * | | |0 = No start-of-frame packet has been received.
- * | | |1 = Start-of-frame packet has been received.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[1] |RSTIF |Reset Status
- * | | |When set, this bit indicates that either the USB root port reset is end.
- * | | |0 = No USB root port reset is end.
- * | | |1 = USB root port reset is end.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[2] |RESUMEIF |Resume
- * | | |When set, this bit indicates that a device resume has occurred.
- * | | |0 = No device resume has occurred.
- * | | |1 = Device resume has occurred.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |SUSPENDIF |Suspend Request
- * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset.
- * | | |This bit is also set when a USB Suspend request is detected from the host.
- * | | |0 = No USB Suspend request is detected from the host.
- * | | |1= USB Suspend request is detected from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |HISPDIF |High-Speed Settle
- * | | |0 = No valid high-speed reset protocol is detected.
- * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |DMADONEIF |DMA Completion Interrupt
- * | | |0 = No DMA transfer over.
- * | | |1 = DMA transfer is over.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |PHYCLKVLDIF|Usable Clock Interrupt
- * | | |0 = Usable clock is not available.
- * | | |1 = Usable clock is available from the transceiver.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |VBUSDETIF |VBUS Detection Interrupt Status
- * | | |0 = No VBUS is plug-in.
- * | | |1 = VBUS is plug-in.
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t BUSINTSTS;
-
- /**
- * BUSINTEN
- * ===================================================================================================
- * Offset: 0x14 USB Bus Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SOFIEN |SOF Interrupt
- * | | |This bit enables the SOF interrupt.
- * | | |0 = SOF interrupt Disabled.
- * | | |1 = SOF interrupt Enabled.
- * |[1] |RSTIEN |Reset Status
- * | | |This bit enables the USB-Reset interrupt.
- * | | |0 = USB-Reset interrupt Disabled.
- * | | |1 = USB-Reset interrupt Enabled.
- * |[2] |RESUMEIEN |Resume
- * | | |This bit enables the Resume interrupt.
- * | | |0 = Resume interrupt Disabled.
- * | | |1 = Resume interrupt Enabled.
- * |[3] |SUSPENDIEN|Suspend Request
- * | | |This bit enables the Suspend interrupt.
- * | | |0 = Suspend interrupt Disabled.
- * | | |1 = Suspend interrupt Enabled.
- * |[4] |HISPDIEN |High-Speed Settle
- * | | |This bit enables the high-speed settle interrupt.
- * | | |0 = High-speed settle interrupt Disabled.
- * | | |1 = High-speed settle interrupt Enabled.
- * |[5] |DMADONEIEN|DMA Completion Interrupt
- * | | |This bit enables the DMA completion interrupt
- * | | |0 = DMA completion interrupt Disabled.
- * | | |1 = DMA completion interrupt Enabled.
- * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt
- * | | |This bit enables the usable clock interrupt.
- * | | |0 = Usable clock interrupt Disabled.
- * | | |1 = Usable clock interrupt Enabled.
- * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Control
- * | | |This bit enables the VBUS floating detection interrupt.
- * | | |0 = VBUS floating detection interrupt Disabled.
- * | | |1 = VBUS floating detection interrupt Enabled.
- */
- __IO uint32_t BUSINTEN;
-
- /**
- * OPER
- * ===================================================================================================
- * Offset: 0x18 USB Operational Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RESUMEEN |Generate Resume
- * | | |0 = No Resume sequence to be initiated to the host.
- * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled.
- * | | |This bit is self-clearing.
- * |[1] |HISPDEN |USB High-Speed
- * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host.
- * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol.
- * |[2] |CURSPD |USB Current Speed
- * | | |0 = The device has settled in Full Speed.
- * | | |1 = The USB device controller has settled in High-speed.
- */
- __IO uint32_t OPER;
-
- /**
- * FRAMECNT
- * ===================================================================================================
- * Offset: 0x1C USB Frame Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |MFRAMECNT |Micro-Frame Counter
- * | | |This field contains the micro-frame number for the frame number in the frame counter field.
- * |[3:13] |FRAMECNT |Frame Counter
- * | | |This field contains the frame count from the most recent start-of-frame packet.
- */
- __I uint32_t FRAMECNT;
-
- /**
- * FADDR
- * ===================================================================================================
- * Offset: 0x20 USB Function Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:6] |FADDR |USB Function Address
- * | | |This field contains the current USB address of the device.
- * | | |This field is cleared when a root port reset is detected.
- */
- __IO uint32_t FADDR;
-
- /**
- * TEST
- * ===================================================================================================
- * Offset: 0x24 USB Test Mode Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:2] |TESTMODE |Test Mode Selection
- * | | |000 = Normal Operation.
- * | | |001 = Test_J.
- * | | |010 = Test_K.
- * | | |011 = Test_SE0_NAK.
- * | | |100 = Test_Packet.
- * | | |101 = Test_Force_Enable.
- * | | |110 = Reserved.
- * | | |111 = Reserved.
- * | | |Note: This field is cleared when root port reset is detected.
- */
- __IO uint32_t TEST;
-
- union {
-
- /**
- * CEPDAT
- * ===================================================================================================
- * Offset: 0x28 Control-Endpoint Data Buffer
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DAT |Control-Endpoint Data Buffer
- * | | |Control endpoint data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t CEPDAT;
- /**
- * CEPDAT_BYTE
- * ===================================================================================================
- * Offset: 0x28 Control-Endpoint Data Buffer for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |DAT |Control-Endpoint Data Buffer
- * | | |Control endpoint data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t CEPDAT_BYTE;
-
- };///< Define Control-Endpoint Data Register 32-bit or 8-bit access
-
- /**
- * CEPCTL
- * ===================================================================================================
- * Offset: 0x2C Control-Endpoint Control and Status
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |NAKCLR |No Acknowledge Control
- * | | |This bit plays a crucial role in any control transfer.
- * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase.
- * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request.
- * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received.
- * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit.
- * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
- * |[1] |STALLEN |Stall Enable Control
- * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter.
- * | | |This is typically used for response to invalid/unsupported requests.
- * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL.
- * | | |It is automatically cleared on receipt of a next setup-token.
- * | | |So, the local CPU need not write again to clear this bit.
- * | | |0 = No sends a stall handshake in response to any in or out token thereafter.
- * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter.
- * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
- * |[2] |ZEROLEN |Zero Packet Length
- * | | |This bit is valid for Auto Validation mode only.
- * | | |0 = No zero length packet to the host during Data stage to an IN token.
- * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token.
- * | | |This bit gets cleared once the zero length data packet is sent.
- * | | |So, the local CPU need not write again to clear this bit.
- * |[3] |FLUSH |CEP-FLUSH Bit
- * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
- * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
- * | | |This bit is self-cleaning.
- */
- __IO uint32_t CEPCTL;
-
- /**
- * CEPINTEN
- * ===================================================================================================
- * Offset: 0x30 Control-Endpoint Interrupt Enable
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Control
- * | | |0 = The SETUP token interrupt in Control Endpoint Disabled.
- * | | |1 = The SETUP token interrupt in Control Endpoint Enabled.
- * |[1] |SETUPPKIEN|Setup Packet Interrupt
- * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled.
- * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled.
- * |[2] |OUTTKIEN |Out Token Interrupt
- * | | |0 = The OUT token interrupt in Control Endpoint Disabled.
- * | | |1 = The OUT token interrupt in Control Endpoint Enabled.
- * |[3] |INTKIEN |In Token Interrupt
- * | | |0 = The IN token interrupt in Control Endpoint Disabled.
- * | | |1 = The IN token interrupt in Control Endpoint Enabled.
- * |[4] |PINGIEN |Ping Token Interrupt
- * | | |0 = The ping token interrupt in Control Endpoint Disabled.
- * | | |1 = The ping token interrupt Control Endpoint Enabled.
- * |[5] |TXPKIEN |Data Packet Transmitted Interrupt
- * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled.
- * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled.
- * |[6] |RXPKIEN |Data Packet Received Interrupt
- * | | |0 = The data received interrupt in Control Endpoint Disabled.
- * | | |1 = The data received interrupt in Control Endpoint Enabled.
- * |[7] |NAKIEN |NAK Sent Interrupt
- * | | |0 = The NAK sent interrupt in Control Endpoint Disabled.
- * | | |1 = The NAK sent interrupt in Control Endpoint Enabled.
- * |[8] |STALLIEN |STALL Sent Interrupt
- * | | |0 = The STALL sent interrupt in Control Endpoint Disabled.
- * | | |1 = The STALL sent interrupt in Control Endpoint Enabled.
- * |[9] |ERRIEN |USB Error Interrupt
- * | | |0 = The USB Error interrupt in Control Endpoint Disabled.
- * | | |1 = The USB Error interrupt in Control Endpoint Enabled.
- * |[10] |STSDONEIEN|Status Completion Interrupt
- * | | |0 = The Status Completion interrupt in Control Endpoint Disabled.
- * | | |1 = The Status Completion interrupt in Control Endpoint Enabled.
- * |[11] |BUFFULLIEN|Buffer Full Interrupt
- * | | |0 = The buffer full interrupt in Control Endpoint Disabled.
- * | | |1 = The buffer full interrupt in Control Endpoint Enabled.
- * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |0 = The buffer empty interrupt in Control Endpoint Disabled.
- * | | |1= The buffer empty interrupt in Control Endpoint Enabled.
- */
- __IO uint32_t CEPINTEN;
-
- /**
- * CEPINTSTS
- * ===================================================================================================
- * Offset: 0x34 Control-Endpoint Interrupt Status
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |SETUPTKIF |Setup Token Interrupt
- * | | |0 = Not a Setup token is received.
- * | | |1 = A Setup token is received. Writing 1 clears this status bit
- * | | |Note: Write 1 to clear this bit to 0.
- * |[1] |SETUPPKIF |Setup Packet Interrupt
- * | | |This bit must be cleared (by writing 1) before the next setup packet can be received.
- * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.
- * | | |0 = Not a Setup packet has been received from the host.
- * | | |1 = A Setup packet has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[2] |OUTTKIF |Out Token Interrupt
- * | | |0 = The control-endpoint does not received an OUT token from the host.
- * | | |1 = The control-endpoint receives an OUT token from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |INTKIF |In Token Interrupt
- * | | |0 = The control-endpoint does not received an IN token from the host.
- * | | |1 = The control-endpoint receives an IN token from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |PINGIF |Ping Token Interrupt
- * | | |0 = The control-endpoint does not received a ping token from the host.
- * | | |1 = The control-endpoint receives a ping token from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
- * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
- * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |NAKIF |NAK Sent Interrupt
- * | | |0 = Not a NAK-token is sent in response to an IN/OUT token.
- * | | |1 = A NAK-token is sent in response to an IN/OUT token.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |STALLIF |STALL Sent Interrupt
- * | | |0 = Not a stall-token is sent in response to an IN/OUT token.
- * | | |1 = A stall-token is sent in response to an IN/OUT token.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |ERRIF |USB Error Interrupt
- * | | |0 = No error had occurred during the transaction.
- * | | |1 = An error had occurred during the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |STSDONEIF |Status Completion Interrupt
- * | | |0 = Not a USB transaction has completed successfully.
- * | | |1 = The status stage of a USB transaction has completed successfully.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |BUFFULLIF |Buffer Full Interrupt
- * | | |0 = The control-endpoint buffer is not full.
- * | | |1 = The control-endpoint buffer is full.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |BUFEMPTYIF|Buffer Empty Interrupt
- * | | |0 = The control-endpoint buffer is not empty.
- * | | |1 = The control-endpoint buffer is empty.
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t CEPINTSTS;
-
- /**
- * CEPTXCNT
- * ===================================================================================================
- * Offset: 0x38 Control-Endpoint In-transfer Data Count
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |TXCNT |In-Transfer Data Count
- * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register.
- * | | |When zero is written into this field, a zero length packet is sent to the host.
- * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS.
- */
- __IO uint32_t CEPTXCNT;
-
- /**
- * CEPRXCNT
- * ===================================================================================================
- * Offset: 0x3C Control-Endpoint Out-transfer Data Count
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |RXCNT |Out-Transfer Data Count
- * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
- */
- __I uint32_t CEPRXCNT;
-
- /**
- * CEPDATCNT
- * ===================================================================================================
- * Offset: 0x40 Control-Endpoint data count
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Control-Endpoint Data Count
- * | | |The USB device controller maintains the count of the data of control-endpoint.
- */
- __I uint32_t CEPDATCNT;
-
- /**
- * SETUP1_0
- * ===================================================================================================
- * Offset: 0x44 Setup1 & Setup0 bytes
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SETUP0 |Setup Byte 0[7:0]
- * | | |This register provides byte 0 of the last setup packet received.
- * | | |For a Standard Device Request, the following bmRequestType information is returned.
- * | | |Bit 7(Direction):
- * | | | 0: Host to device
- * | | | 1: Device to host
- * | | |Bit 6-5 (Type):
- * | | | 00: Standard
- * | | | 01: Class
- * | | | 10: Vendor
- * | | | 11: Reserved
- * | | |Bit 4-0 (Recipient)
- * | | | 00000: Device
- * | | | 00001: Interface
- * | | | 00010: Endpoint
- * | | | 00011: Other
- * | | | Others: Reserved
- * |[8:15] |SETUP1 |Setup Byte 1[15:8]
- * | | |This register provides byte 1 of the last setup packet received.
- * | | |For a Standard Device Request, the following bRequest Code information is returned.
- * | | |00000000 = Get Status.
- * | | |00000001 = Clear Feature.
- * | | |00000010 = Reserved.
- * | | |00000011 = Set Feature.
- * | | |00000100 = Reserved.
- * | | |00000101 = Set Address.
- * | | |00000110 = Get Descriptor.
- * | | |00000111 = Set Descriptor.
- * | | |00001000 = Get Configuration.
- * | | |00001001 = Set Configuration.
- * | | |00001010 = Get Interface.
- * | | |00001011 = Set Interface.
- * | | |00001100 = Synch Frame.
- */
- __I uint32_t SETUP1_0;
-
- /**
- * SETUP3_2
- * ===================================================================================================
- * Offset: 0x48 Setup3 & Setup2 Bytes
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SETUP2 |Setup Byte 2 [7:0]
- * | | |This register provides byte 2 of the last setup packet received.
- * | | |For a Standard Device Request, the least significant byte of the wValue field is returned.
- * |[8:15] |SETUP3 |Setup Byte 3 [15:8]
- * | | |This register provides byte 3 of the last setup packet received.
- * | | |For a Standard Device Request, the most significant byte of the wValue field is returned.
- */
- __I uint32_t SETUP3_2;
-
- /**
- * SETUP5_4
- * ===================================================================================================
- * Offset: 0x4C Setup5 & Setup4 Bytes
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SETUP4 |Setup Byte 4[7:0]
- * | | |This register provides byte 4 of the last setup packet received.
- * | | |For a Standard Device Request, the least significant byte of the wIndex is returned.
- * |[8:15] |SETUP5 |Setup Byte 5[15:8]
- * | | |This register provides byte 5 of the last setup packet received.
- * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned.
- */
- __I uint32_t SETUP5_4;
-
- /**
- * SETUP7_6
- * ===================================================================================================
- * Offset: 0x50 Setup7 & Setup6 Bytes
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |SETUP6 |Setup Byte 6[7:0]
- * | | |This register provides byte 6 of the last setup packet received.
- * | | |For a Standard Device Request, the least significant byte of the wLength field is returned.
- * |[8:15] |SETUP7 |Setup Byte 7[15:8]
- * | | |This register provides byte 7 of the last setup packet received.
- * | | |For a Standard Device Request, the most significant byte of the wLength field is returned.
- */
- __I uint32_t SETUP7_6;
-
- /**
- * CEPBUFSTART
- * ===================================================================================================
- * Offset: 0x54 Control Endpoint RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Control-Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the control-endpoint.
- */
- __IO uint32_t CEPBUFSTART;
-
- /**
- * CEPBUFEND
- * ===================================================================================================
- * Offset: 0x58 Control Endpoint RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Control-Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the control-endpoint.
- */
- __IO uint32_t CEPBUFEND;
-
- /**
- * DMACTL
- * ===================================================================================================
- * Offset: 0x5C DMA Control Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:3] |EPNUM |DMA Endpoint Address Bits
- * | | |Used to define the Endpoint Address
- * |[4] |DMARD |DMA Operation
- * | | |0 = the operation is a DMA write.
- * | | |1 = the operation is a DMA read.
- * |[5] |DMAEN |DMA Enable Control
- * | | |0 = DMA function Disabled.
- * | | |1 = DMA function Enabled.
- * |[6] |SGEN |Scatter Gather Function Enable Control
- * | | |0 = Scatter gather function Disabled.
- * | | |1 = Scatter gather function Enabled.
- * |[7] |DMARST |Reset DMA State Machine
- * | | |0 = No reset the DMA state machine.
- * | | |1 = Reset the DMA state machine.
- */
- __IO uint32_t DMACTL;
-
- /**
- * DMACNT
- * ===================================================================================================
- * Offset: 0x60 DMA Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:19] |DMACNT |DMA Transfer Count
- * | | |The transfer count of the DMA operation to be performed is written to this register.
- */
- __IO uint32_t DMACNT;
-
- union {
-
- /**
- * EPADAT
- * ===================================================================================================
- * Offset: 0x64 Endpoint A Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPADAT;
- /**
- * EPADAT_BYTE
- * ===================================================================================================
- * Offset: 0x64 Endpoint A Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPADAT_BYTE;
-
- }; ///< Define EPA Data Register 32-bit or 8-bit access
-
- /**
- * EPAINTSTS
- * ===================================================================================================
- * Offset: 0x68 Endpoint A Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPAINTSTS;
-
- /**
- * EPAINTEN
- * ===================================================================================================
- * Offset: 0x6C Endpoint A Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPAINTEN;
-
- /**
- * EPADATCNT
- * ===================================================================================================
- * Offset: 0x70 Endpoint A Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPADATCNT;
-
- /**
- * EPARSPCTL
- * ===================================================================================================
- * Offset: 0x74 Endpoint A Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPARSPCTL;
-
- /**
- * EPAMPS
- * ===================================================================================================
- * Offset: 0x78 Endpoint A Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPAMPS;
-
- /**
- * EPATXCNT
- * ===================================================================================================
- * Offset: 0x7C Endpoint A Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPATXCNT;
-
- /**
- * EPACFG
- * ===================================================================================================
- * Offset: 0x80 Endpoint A Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPACFG;
-
- /**
- * EPABUFSTART
- * ===================================================================================================
- * Offset: 0x84 Endpoint A RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPABUFSTART;
-
- /**
- * EPABUFEND
- * ===================================================================================================
- * Offset: 0x88 Endpoint A RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPABUFEND;
-
- union {
-
- /**
- * EPBDAT
- * ===================================================================================================
- * Offset: 0x8C Endpoint B Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPBDAT;
- /**
- * EPBDAT_BYTE
- * ===================================================================================================
- * Offset: 0x8C Endpoint B Data Register or Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPBDAT_BYTE;
-
- }; ///< Define EPB Data Register 32-bit or 8-bit access
-
- /**
- * EPBINTSTS
- * ===================================================================================================
- * Offset: 0x90 Endpoint B Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPBINTSTS;
-
- /**
- * EPBINTEN
- * ===================================================================================================
- * Offset: 0x94 Endpoint B Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPBINTEN;
-
- /**
- * EPBDATCNT
- * ===================================================================================================
- * Offset: 0x98 Endpoint B Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPBDATCNT;
-
- /**
- * EPBRSPCTL
- * ===================================================================================================
- * Offset: 0x9C Endpoint B Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPBRSPCTL;
-
- /**
- * EPBMPS
- * ===================================================================================================
- * Offset: 0xA0 Endpoint B Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPBMPS;
-
- /**
- * EPBTXCNT
- * ===================================================================================================
- * Offset: 0xA4 Endpoint B Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPBTXCNT;
-
- /**
- * EPBCFG
- * ===================================================================================================
- * Offset: 0xA8 Endpoint B Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPBCFG;
-
- /**
- * EPBBUFSTART
- * ===================================================================================================
- * Offset: 0xAC Endpoint B RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPBBUFSTART;
-
- /**
- * EPBBUFEND
- * ===================================================================================================
- * Offset: 0xB0 Endpoint B RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPBBUFEND;
-
- union {
-
- /**
- * EPCDAT
- * ===================================================================================================
- * Offset: 0xB4 Endpoint C Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPCDAT;
- /**
- * EPCDAT_BYTE
- * ===================================================================================================
- * Offset: 0xB4 Endpoint C Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPCDAT_BYTE;
-
- }; ///< Define EPC Data Register 32-bit or 8-bit access
-
- /**
- * EPCINTSTS
- * ===================================================================================================
- * Offset: 0xB8 Endpoint C Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPCINTSTS;
-
- /**
- * EPCINTEN
- * ===================================================================================================
- * Offset: 0xBC Endpoint C Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPCINTEN;
-
- /**
- * EPCDATCNT
- * ===================================================================================================
- * Offset: 0xC0 Endpoint C Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPCDATCNT;
-
- /**
- * EPCRSPCTL
- * ===================================================================================================
- * Offset: 0xC4 Endpoint C Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPCRSPCTL;
-
- /**
- * EPCMPS
- * ===================================================================================================
- * Offset: 0xC8 Endpoint C Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPCMPS;
-
- /**
- * EPCTXCNT
- * ===================================================================================================
- * Offset: 0xCC Endpoint C Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPCTXCNT;
-
- /**
- * EPCCFG
- * ===================================================================================================
- * Offset: 0xD0 Endpoint C Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPCCFG;
-
- /**
- * EPCBUFSTART
- * ===================================================================================================
- * Offset: 0xD4 Endpoint C RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPCBUFSTART;
-
- /**
- * EPCBUFEND
- * ===================================================================================================
- * Offset: 0xD8 Endpoint C RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPCBUFEND;
-
- union {
-
- /**
- * EPDDAT
- * ===================================================================================================
- * Offset: 0xDC Endpoint D Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPDDAT;
- /**
- * EPDDAT_BYTE
- * ===================================================================================================
- * Offset: 0xDC Endpoint D Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPDDAT_BYTE;
-
- }; ///< Define EPD Data Register 32-bit or 8-bit access
-
- /**
- * EPDINTSTS
- * ===================================================================================================
- * Offset: 0xE0 Endpoint D Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPDINTSTS;
-
- /**
- * EPDINTEN
- * ===================================================================================================
- * Offset: 0xE4 Endpoint D Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPDINTEN;
-
- /**
- * EPDDATCNT
- * ===================================================================================================
- * Offset: 0xE8 Endpoint D Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPDDATCNT;
-
- /**
- * EPDRSPCTL
- * ===================================================================================================
- * Offset: 0xEC Endpoint D Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPDRSPCTL;
-
- /**
- * EPDMPS
- * ===================================================================================================
- * Offset: 0xF0 Endpoint D Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPDMPS;
-
- /**
- * EPDTXCNT
- * ===================================================================================================
- * Offset: 0xF4 Endpoint D Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPDTXCNT;
-
- /**
- * EPDCFG
- * ===================================================================================================
- * Offset: 0xF8 Endpoint D Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPDCFG;
-
- /**
- * EPDBUFSTART
- * ===================================================================================================
- * Offset: 0xFC Endpoint D RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPDBUFSTART;
-
- /**
- * EPDBUFEND
- * ===================================================================================================
- * Offset: 0x100 Endpoint D RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPDBUFEND;
-
- union {
-
- /**
- * EPEDAT
- * ===================================================================================================
- * Offset: 0x104 Endpoint E Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPEDAT;
- /**
- * EPEDAT_BYTE
- * ===================================================================================================
- * Offset: 0x104 Endpoint E Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPEDAT_BYTE;
-
- }; ///< Define EPE Data Register 32-bit or 8-bit access
-
- /**
- * EPEINTSTS
- * ===================================================================================================
- * Offset: 0x108 Endpoint E Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPEINTSTS;
-
- /**
- * EPEINTEN
- * ===================================================================================================
- * Offset: 0x10C Endpoint E Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPEINTEN;
-
- /**
- * EPEDATCNT
- * ===================================================================================================
- * Offset: 0x110 Endpoint E Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPEDATCNT;
-
- /**
- * EPERSPCTL
- * ===================================================================================================
- * Offset: 0x114 Endpoint E Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPERSPCTL;
-
- /**
- * EPEMPS
- * ===================================================================================================
- * Offset: 0x118 Endpoint E Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPEMPS;
-
- /**
- * EPETXCNT
- * ===================================================================================================
- * Offset: 0x11C Endpoint E Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPETXCNT;
-
- /**
- * EPECFG
- * ===================================================================================================
- * Offset: 0x120 Endpoint E Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPECFG;
-
- /**
- * EPEBUFSTART
- * ===================================================================================================
- * Offset: 0x124 Endpoint E RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPEBUFSTART;
-
- /**
- * EPEBUFEND
- * ===================================================================================================
- * Offset: 0x128 Endpoint E RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPEBUFEND;
-
- union {
-
- /**
- * EPFDAT
- * ===================================================================================================
- * Offset: 0x12C Endpoint F Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPFDAT;
- /**
- * EPFDAT_BYTE
- * ===================================================================================================
- * Offset: 0x12C Endpoint F Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPFDAT_BYTE;
-
- }; ///< Define EPF Data Register 32-bit or 8-bit access
-
- /**
- * EPFINTSTS
- * ===================================================================================================
- * Offset: 0x130 Endpoint F Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPFINTSTS;
-
- /**
- * EPFINTEN
- * ===================================================================================================
- * Offset: 0x134 Endpoint F Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPFINTEN;
-
- /**
- * EPFDATCNT
- * ===================================================================================================
- * Offset: 0x138 Endpoint F Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPFDATCNT;
-
- /**
- * EPFRSPCTL
- * ===================================================================================================
- * Offset: 0x13C Endpoint F Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPFRSPCTL;
-
- /**
- * EPFMPS
- * ===================================================================================================
- * Offset: 0x140 Endpoint F Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPFMPS;
-
- /**
- * EPFTXCNT
- * ===================================================================================================
- * Offset: 0x144 Endpoint F Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPFTXCNT;
-
- /**
- * EPFCFG
- * ===================================================================================================
- * Offset: 0x148 Endpoint F Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPFCFG;
-
- /**
- * EPFBUFSTART
- * ===================================================================================================
- * Offset: 0x14C Endpoint F RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPFBUFSTART;
-
- /**
- * EPFBUFEND
- * ===================================================================================================
- * Offset: 0x150 Endpoint F RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPFBUFEND;
-
- union {
-
- /**
- * EPGDAT
- * ===================================================================================================
- * Offset: 0x154 Endpoint G Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPGDAT;
- /**
- * EPGDAT_BYTE
- * ===================================================================================================
- * Offset: 0x154 Endpoint G Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPGDAT_BYTE;
-
- }; ///< Define EPG Data Register 32-bit or 8-bit access
-
- /**
- * EPGINTSTS
- * ===================================================================================================
- * Offset: 0x158 Endpoint G Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPGINTSTS;
-
- /**
- * EPGINTEN
- * ===================================================================================================
- * Offset: 0x15C Endpoint G Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPGINTEN;
-
- /**
- * EPGDATCNT
- * ===================================================================================================
- * Offset: 0x160 Endpoint G Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPGDATCNT;
-
- /**
- * EPGRSPCTL
- * ===================================================================================================
- * Offset: 0x164 Endpoint G Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPGRSPCTL;
-
- /**
- * EPGMPS
- * ===================================================================================================
- * Offset: 0x168 Endpoint G Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPGMPS;
-
- /**
- * EPGTXCNT
- * ===================================================================================================
- * Offset: 0x16C Endpoint G Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPGTXCNT;
-
- /**
- * EPGCFG
- * ===================================================================================================
- * Offset: 0x170 Endpoint G Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPGCFG;
-
- /**
- * EPGBUFSTART
- * ===================================================================================================
- * Offset: 0x174 Endpoint G RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPGBUFSTART;
-
- /**
- * EPGBUFEND
- * ===================================================================================================
- * Offset: 0x178 Endpoint G RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPGBUFEND;
-
- union {
-
- /**
- * EPHDAT
- * ===================================================================================================
- * Offset: 0x17C Endpoint H Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPHDAT;
- /**
- * EPHDAT_BYTE
- * ===================================================================================================
- * Offset: 0x17C Endpoint H Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPHDAT_BYTE;
-
- }; ///< Define EPH Data Register 32-bit or 8-bit access
-
- /**
- * EPHINTSTS
- * ===================================================================================================
- * Offset: 0x180 Endpoint H Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPHINTSTS;
-
- /**
- * EPHINTEN
- * ===================================================================================================
- * Offset: 0x184 Endpoint H Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPHINTEN;
-
- /**
- * EPHDATCNT
- * ===================================================================================================
- * Offset: 0x188 Endpoint H Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPHDATCNT;
-
- /**
- * EPHRSPCTL
- * ===================================================================================================
- * Offset: 0x18C Endpoint H Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPHRSPCTL;
-
- /**
- * EPHMPS
- * ===================================================================================================
- * Offset: 0x190 Endpoint H Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPHMPS;
-
- /**
- * EPHTXCNT
- * ===================================================================================================
- * Offset: 0x194 Endpoint H Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPHTXCNT;
-
- /**
- * EPHCFG
- * ===================================================================================================
- * Offset: 0x198 Endpoint H Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPHCFG;
-
- /**
- * EPHBUFSTART
- * ===================================================================================================
- * Offset: 0x19C Endpoint H RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPHBUFSTART;
-
- /**
- * EPHBUFEND
- * ===================================================================================================
- * Offset: 0x1A0 Endpoint H RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPHBUFEND;
-
- union {
-
- /**
- * EPIDAT
- * ===================================================================================================
- * Offset: 0x1A4 Endpoint I Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPIDAT;
- /**
- * EPIDAT_BYTE
- * ===================================================================================================
- * Offset: 0x1A4 Endpoint I Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPIDAT_BYTE;
-
- }; ///< Define EPI Data Register 32-bit or 8-bit access
-
- /**
- * EPIINTSTS
- * ===================================================================================================
- * Offset: 0x1A8 Endpoint I Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPIINTSTS;
-
- /**
- * EPIINTEN
- * ===================================================================================================
- * Offset: 0x1AC Endpoint I Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPIINTEN;
-
- /**
- * EPIDATCNT
- * ===================================================================================================
- * Offset: 0x1B0 Endpoint I Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPIDATCNT;
-
- /**
- * EPIRSPCTL
- * ===================================================================================================
- * Offset: 0x1B4 Endpoint I Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPIRSPCTL;
-
- /**
- * EPIMPS
- * ===================================================================================================
- * Offset: 0x1B8 Endpoint I Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPIMPS;
-
- /**
- * EPITXCNT
- * ===================================================================================================
- * Offset: 0x1BC Endpoint I Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPITXCNT;
-
- /**
- * EPICFG
- * ===================================================================================================
- * Offset: 0x1C0 Endpoint I Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPICFG;
-
- /**
- * EPIBUFSTART
- * ===================================================================================================
- * Offset: 0x1C4 Endpoint I RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPIBUFSTART;
-
- /**
- * EPIBUFEND
- * ===================================================================================================
- * Offset: 0x1C8 Endpoint I RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPIBUFEND;
-
- union {
-
- /**
- * EPJDAT
- * ===================================================================================================
- * Offset: 0x1CC Endpoint J Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPJDAT;
- /**
- * EPJDAT_BYTE
- * ===================================================================================================
- * Offset: 0x1CC Endpoint J Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPJDAT_BYTE;
-
- }; ///< Define EPJ Data Register 32-bit or 8-bit access
-
- /**
- * EPJINTSTS
- * ===================================================================================================
- * Offset: 0x1D0 Endpoint J Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPJINTSTS;
-
- /**
- * EPJINTEN
- * ===================================================================================================
- * Offset: 0x1D4 Endpoint J Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPJINTEN;
-
- /**
- * EPJDATCNT
- * ===================================================================================================
- * Offset: 0x1D8 Endpoint J Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPJDATCNT;
-
- /**
- * EPJRSPCTL
- * ===================================================================================================
- * Offset: 0x1DC Endpoint J Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPJRSPCTL;
-
- /**
- * EPJMPS
- * ===================================================================================================
- * Offset: 0x1E0 Endpoint J Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPJMPS;
-
- /**
- * EPJTXCNT
- * ===================================================================================================
- * Offset: 0x1E4 Endpoint J Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPJTXCNT;
-
- /**
- * EPJCFG
- * ===================================================================================================
- * Offset: 0x1E8 Endpoint J Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPJCFG;
-
- /**
- * EPJBUFSTART
- * ===================================================================================================
- * Offset: 0x1EC Endpoint J RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPJBUFSTART;
-
- /**
- * EPJBUFEND
- * ===================================================================================================
- * Offset: 0x1F0 Endpoint J RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPJBUFEND;
-
- union {
-
- /**
- * EPKDAT
- * ===================================================================================================
- * Offset: 0x1F4 Endpoint K Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPKDAT;
- /**
- * EPKDAT_BYTE
- * ===================================================================================================
- * Offset: 0x1F4 Endpoint K Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPKDAT_BYTE;
-
- }; ///< Define EPK Data Register 32-bit or 8-bit access
-
- /**
- * EPKINTSTS
- * ===================================================================================================
- * Offset: 0x1F8 Endpoint K Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPKINTSTS;
-
- /**
- * EPKINTEN
- * ===================================================================================================
- * Offset: 0x1FC Endpoint K Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPKINTEN;
-
- /**
- * EPKDATCNT
- * ===================================================================================================
- * Offset: 0x200 Endpoint K Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPKDATCNT;
-
- /**
- * EPKRSPCTL
- * ===================================================================================================
- * Offset: 0x204 Endpoint K Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPKRSPCTL;
-
- /**
- * EPKMPS
- * ===================================================================================================
- * Offset: 0x208 Endpoint K Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPKMPS;
-
- /**
- * EPKTXCNT
- * ===================================================================================================
- * Offset: 0x20C Endpoint K Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPKTXCNT;
-
- /**
- * EPKCFG
- * ===================================================================================================
- * Offset: 0x210 Endpoint K Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPKCFG;
-
- /**
- * EPKBUFSTART
- * ===================================================================================================
- * Offset: 0x214 Endpoint K RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPKBUFSTART;
-
- /**
- * EPKBUFEND
- * ===================================================================================================
- * Offset: 0x218 Endpoint K RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPKBUFEND;
-
- union {
-
- /**
- * EPLDAT
- * ===================================================================================================
- * Offset: 0x21C Endpoint L Data Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint32_t EPLDAT;
- /**
- * EPLDAT_BYTE
- * ===================================================================================================
- * Offset: 0x21C Endpoint L Data Register for Byte Access
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:7] |EPDAT |Endpoint A~L Data Register
- * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
- * | | |Note: Only word or byte access are supported.
- */
- __IO uint8_t EPLDAT_BYTE;
-
- }; ///< Define EPL Data Register 32-bit or 8-bit access
-
- /**
- * EPLINTSTS
- * ===================================================================================================
- * Offset: 0x220 Endpoint L Interrupt Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIF |Buffer Full
- * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
- * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
- * | | |0 = The endpoint packet buffer is not full.
- * | | |1 = The endpoint packet buffer is full.
- * | | |Note: This bit is read-only.
- * |[1] |BUFEMPTYIF|Buffer Empty
- * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
- * | | |0 = The endpoint buffer is not empty.
- * | | |1 = The endpoint buffer is empty.
- * | | |For an OUT endpoint:
- * | | |0 = The currently selected buffer has not a count of 0.
- * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
- * | | |Note: This bit is read-only.
- * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
- * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
- * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[3] |TXPKIF |Data Packet Transmitted Interrupt
- * | | |0 = Not a data packet is transmitted from the endpoint to the host.
- * | | |1 = A data packet is transmitted from the endpoint to the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[4] |RXPKIF |Data Packet Received Interrupt
- * | | |0 = No data packet is received from the host by the endpoint.
- * | | |1 = A data packet is received from the host by the endpoint.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[5] |OUTTKIF |Data OUT Token Interrupt
- * | | |0 = A Data OUT token has not been received from the host.
- * | | |1 = A Data OUT token has been received from the host.
- * | | |This bit also set by PING tokens(in high-speed only).
- * | | |Note: Write 1 to clear this bit to 0.
- * |[6] |INTKIF |Data IN Token Interrupt
- * | | |0 = Not Data IN token has been received from the host.
- * | | |1 = A Data IN token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[7] |PINGIF |PING Token Interrupt
- * | | |0 = A Data PING token has not been received from the host.
- * | | |1 = A Data PING token has been received from the host.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[8] |NAKIF |USB NAK Sent
- * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
- * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[9] |STALLIF |USB STALL Sent
- * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[10] |NYETIF |NYET Sent
- * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
- * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[11] |ERRIF |ERR Sent
- * | | |0 = No any error in the transaction.
- * | | |1 = There occurs any error in the transaction.
- * | | |Note: Write 1 to clear this bit to 0.
- * |[12] |SHORTRXIF |Bulk Out Short Packet Received
- * | | |0 = No bulk out short packet is received.
- * | | |1 = Received bulk out short packet (including zero length packet ).
- * | | |Note: Write 1 to clear this bit to 0.
- */
- __IO uint32_t EPLINTSTS;
-
- /**
- * EPLINTEN
- * ===================================================================================================
- * Offset: 0x224 Endpoint L Interrupt Enable Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |BUFFULLIEN|Buffer Full Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
- * | | |0 = Buffer full interrupt Disabled.
- * | | |1 = Buffer full interrupt Enabled.
- * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
- * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
- * | | |0 = Buffer empty interrupt Disabled.
- * | | |1 = Buffer empty interrupt Enabled.
- * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
- * | | |0 = Short data packet interrupt Disabled.
- * | | |1 = Short data packet interrupt Enabled.
- * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
- * | | |0 = Data packet has been received from the host interrupt Disabled.
- * | | |1 = Data packet has been received from the host interrupt Enabled.
- * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
- * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
- * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
- * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
- * | | |0 = Data OUT token interrupt Disabled.
- * | | |1 = Data OUT token interrupt Enabled.
- * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
- * | | |0 = Data IN token interrupt Disabled.
- * | | |1 = Data IN token interrupt Enabled.
- * |[7] |PINGIEN |PING Token Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
- * | | |0 = PING token interrupt Disabled.
- * | | |1 = PING token interrupt Enabled.
- * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
- * | | |0 = NAK token interrupt Disabled.
- * | | |1 = NAK token interrupt Enabled.
- * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
- * | | |0 = STALL token interrupt Disabled.
- * | | |1 = STALL token interrupt Enabled.
- * |[10] |NYETIEN |NYET Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
- * | | |0 = NYET condition interrupt Disabled.
- * | | |1 = NYET condition interrupt Enabled.
- * |[11] |ERRIEN |ERR Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
- * | | |0 = Error event interrupt Disabled.
- * | | |1 = Error event interrupt Enabled.
- * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
- * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
- * | | |0 = Bulk out interrupt Disabled.
- * | | |1 = Bulk out interrupt Enabled.
- */
- __IO uint32_t EPLINTEN;
-
- /**
- * EPLDATCNT
- * ===================================================================================================
- * Offset: 0x228 Endpoint L Data Available Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:15] |DATCNT |Data Count
- * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
- * |[16:30] |DMALOOP |DMA Loop
- * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
- */
- __I uint32_t EPLDATCNT;
-
- /**
- * EPLRSPCTL
- * ===================================================================================================
- * Offset: 0x22C Endpoint L Response Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |FLUSH |Buffer Flush
- * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
- * | | |This bit is self-clearing.
- * | | |This bit should always be written after an configuration event.
- * | | |0 = The packet buffer is not flushed.
- * | | |1 = The packet buffer is flushed by user.
- * |[1:2] |MODE |Mode Control
- * | | |The two bits decide the operation mode of the in-endpoint.
- * | | |00: Auto-Validate Mode
- * | | |01: Manual-Validate Mode
- * | | |10: Fly Mode
- * | | |11: Reserved
- * | | |These bits are not valid for an out-endpoint.
- * | | |The auto validate mode will be activated when the reserved mode is selected.
- * |[3] |TOGGLE |Endpoint Toggle
- * | | |This bit is used to clear the endpoint data toggle bit.
- * | | |Reading this bit returns the current state of the endpoint data toggle bit.
- * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
- * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
- * | | |0 = Not clear the endpoint data toggle bit.
- * | | |1 = Clear the endpoint data toggle bit.
- * |[4] |HALT |Endpoint Halt
- * | | |This bit is used to send a STALL handshake as response to the token from the host.
- * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
- * | | |0 = Not send a STALL handshake as response to the token from the host.
- * | | |1 = Send a STALL handshake as response to the token from the host.
- * |[5] |ZEROLEN |Zero Length
- * | | |This bit is used to send a zero-length packet n response to an IN-token.
- * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
- * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
- * | | |1 = A zero packet is sent to the host on reception of an IN-token.
- * |[6] |SHORTTXEN |Short Packet Transfer Enable
- * | | |This bit is applicable only in case of Auto-Validate Method.
- * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
- * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
- * |[7] |DISBUF |Buffer Disable Control
- * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
- * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
- * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
- */
- __IO uint32_t EPLRSPCTL;
-
- /**
- * EPLMPS
- * ===================================================================================================
- * Offset: 0x230 Endpoint L Maximum Packet Size Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |EPMPS |Endpoint Maximum Packet Size
- * | | |This field determines the Maximum Packet Size of the Endpoint.
- */
- __IO uint32_t EPLMPS;
-
- /**
- * EPLTXCNT
- * ===================================================================================================
- * Offset: 0x234 Endpoint L Transfer Count Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:10] |TXCNT |Endpoint Transfer Count
- * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
- * | | |For OUT endpoints, this field has no effect.
- */
- __IO uint32_t EPLTXCNT;
-
- /**
- * EPLCFG
- * ===================================================================================================
- * Offset: 0x238 Endpoint L Configuration Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |EPEN |Endpoint Valid
- * | | |When set, this bit enables this endpoint.
- * | | |This bit has no effect on Endpoint 0, which is always enabled.
- * | | |0 = The endpoint Disabled.
- * | | |1 = The endpoint Enabled.
- * |[1:2] |EPTYPE |Endpoint Type
- * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
- * | | |00 = Reserved.
- * | | |01 = Bulk.
- * | | |10 = Interrupt.
- * | | |11 = Isochronous.
- * |[3] |EPDIR |Endpoint Direction
- * | | |0 = out-endpoint (Host OUT to Device).
- * | | |1 = in-endpoint (Host IN to Device).
- * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
- * |[4:7] |EPNUM |Endpoint Number
- * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
- */
- __IO uint32_t EPLCFG;
-
- /**
- * EPLBUFSTART
- * ===================================================================================================
- * Offset: 0x23C Endpoint L RAM Start Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |SADDR |Endpoint Start Address
- * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPLBUFSTART;
-
- /**
- * EPLBUFEND
- * ===================================================================================================
- * Offset: 0x240 Endpoint L RAM End Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:11] |EADDR |Endpoint End Address
- * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
- */
- __IO uint32_t EPLBUFEND;
-
- uint32_t RESERVE2[303];
-
-
- /**
- * DMAADDR
- * ===================================================================================================
- * Offset: 0x700 AHB DMA Address Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |DMAADDR |DMAADDR
- * | | |The register specifies the address from which the DMA has to read / write.
- * | | |The address must WORD (32-bit) aligned.
- */
- __IO uint32_t DMAADDR;
-
- /**
- * PHYCTL
- * ===================================================================================================
- * Offset: 0x704 USB PHY Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[8] |DPPUEN |DP Pull-Up
- * | | |0 = Pull-up resistor on D+ Disabled.
- * | | |1 = Pull-up resistor on D+ Enabled.
- * |[9] |PHYEN |PHY Suspend Enable Control
- * | | |0 = The USB PHY is suspend.
- * | | |1 = The USB PHY is not suspend.
- * |[24] |WKEN |Wake-Up Enable Control
- * | | |0 = The wake-up function Disabled.
- * | | |1 = The wake-up function Enabled.
- * |[31] |VBUSDET |VBUS Status
- * | | |0 = The VBUS is not detected yet.
- * | | |1 = The VBUS is detected.
- */
- __IO uint32_t PHYCTL;
-
-} USBD_T;
-
-/**
- @addtogroup USBD_CONST USBD Bit Field Definition
- Constant Definitions for USBD Controller
-@{ */
-
-#define USBD_GINTSTS_USBIF_Pos (0) /*!< USBD GINTSTS: USBIF Position */
-#define USBD_GINTSTS_USBIF_Msk (0x1ul << USBD_GINTSTS_USBIF_Pos) /*!< USBD GINTSTS: USBIF Mask */
-
-#define USBD_GINTSTS_CEPIF_Pos (1) /*!< USBD GINTSTS: CEPIF Position */
-#define USBD_GINTSTS_CEPIF_Msk (0x1ul << USBD_GINTSTS_CEPIF_Pos) /*!< USBD GINTSTS: CEPIF Mask */
-
-#define USBD_GINTSTS_EPAIF_Pos (2) /*!< USBD GINTSTS: EPAIF Position */
-#define USBD_GINTSTS_EPAIF_Msk (0x1ul << USBD_GINTSTS_EPAIF_Pos) /*!< USBD GINTSTS: EPAIF Mask */
-
-#define USBD_GINTSTS_EPBIF_Pos (3) /*!< USBD GINTSTS: EPBIF Position */
-#define USBD_GINTSTS_EPBIF_Msk (0x1ul << USBD_GINTSTS_EPBIF_Pos) /*!< USBD GINTSTS: EPBIF Mask */
-
-#define USBD_GINTSTS_EPCIF_Pos (4) /*!< USBD GINTSTS: EPCIF Position */
-#define USBD_GINTSTS_EPCIF_Msk (0x1ul << USBD_GINTSTS_EPCIF_Pos) /*!< USBD GINTSTS: EPCIF Mask */
-
-#define USBD_GINTSTS_EPDIF_Pos (5) /*!< USBD GINTSTS: EPDIF Position */
-#define USBD_GINTSTS_EPDIF_Msk (0x1ul << USBD_GINTSTS_EPDIF_Pos) /*!< USBD GINTSTS: EPDIF Mask */
-
-#define USBD_GINTSTS_EPEIF_Pos (6) /*!< USBD GINTSTS: EPEIF Position */
-#define USBD_GINTSTS_EPEIF_Msk (0x1ul << USBD_GINTSTS_EPEIF_Pos) /*!< USBD GINTSTS: EPEIF Mask */
-
-#define USBD_GINTSTS_EPFIF_Pos (7) /*!< USBD GINTSTS: EPFIF Position */
-#define USBD_GINTSTS_EPFIF_Msk (0x1ul << USBD_GINTSTS_EPFIF_Pos) /*!< USBD GINTSTS: EPFIF Mask */
-
-#define USBD_GINTSTS_EPGIF_Pos (8) /*!< USBD GINTSTS: EPGIF Position */
-#define USBD_GINTSTS_EPGIF_Msk (0x1ul << USBD_GINTSTS_EPGIF_Pos) /*!< USBD GINTSTS: EPGIF Mask */
-
-#define USBD_GINTSTS_EPHIF_Pos (9) /*!< USBD GINTSTS: EPHIF Position */
-#define USBD_GINTSTS_EPHIF_Msk (0x1ul << USBD_GINTSTS_EPHIF_Pos) /*!< USBD GINTSTS: EPHIF Mask */
-
-#define USBD_GINTSTS_EPIIF_Pos (10) /*!< USBD GINTSTS: EPIIF Position */
-#define USBD_GINTSTS_EPIIF_Msk (0x1ul << USBD_GINTSTS_EPIIF_Pos) /*!< USBD GINTSTS: EPIIF Mask */
-
-#define USBD_GINTSTS_EPJIF_Pos (11) /*!< USBD GINTSTS: EPJIF Position */
-#define USBD_GINTSTS_EPJIF_Msk (0x1ul << USBD_GINTSTS_EPJIF_Pos) /*!< USBD GINTSTS: EPJIF Mask */
-
-#define USBD_GINTSTS_EPKIF_Pos (12) /*!< USBD GINTSTS: EPKIF Position */
-#define USBD_GINTSTS_EPKIF_Msk (0x1ul << USBD_GINTSTS_EPKIF_Pos) /*!< USBD GINTSTS: EPKIF Mask */
-
-#define USBD_GINTSTS_EPLIF_Pos (13) /*!< USBD GINTSTS: EPLIF Position */
-#define USBD_GINTSTS_EPLIF_Msk (0x1ul << USBD_GINTSTS_EPLIF_Pos) /*!< USBD GINTSTS: EPLIF Mask */
-
-#define USBD_GINTEN_USBIE_Pos (0) /*!< USBD GINTEN: USBIE Position */
-#define USBD_GINTEN_USBIE_Msk (0x1ul << USBD_GINTEN_USBIE_Pos) /*!< USBD GINTEN: USBIE Mask */
-
-#define USBD_GINTEN_CEPIE_Pos (1) /*!< USBD GINTEN: CEPIE Position */
-#define USBD_GINTEN_CEPIE_Msk (0x1ul << USBD_GINTEN_CEPIE_Pos) /*!< USBD GINTEN: CEPIE Mask */
-
-#define USBD_GINTEN_EPAIE_Pos (2) /*!< USBD GINTEN: EPAIE Position */
-#define USBD_GINTEN_EPAIE_Msk (0x1ul << USBD_GINTEN_EPAIE_Pos) /*!< USBD GINTEN: EPAIE Mask */
-
-#define USBD_GINTEN_EPBIE_Pos (3) /*!< USBD GINTEN: EPBIE Position */
-#define USBD_GINTEN_EPBIE_Msk (0x1ul << USBD_GINTEN_EPBIE_Pos) /*!< USBD GINTEN: EPBIE Mask */
-
-#define USBD_GINTEN_EPCIE_Pos (4) /*!< USBD GINTEN: EPCIE Position */
-#define USBD_GINTEN_EPCIE_Msk (0x1ul << USBD_GINTEN_EPCIE_Pos) /*!< USBD GINTEN: EPCIE Mask */
-
-#define USBD_GINTEN_EPDIE_Pos (5) /*!< USBD GINTEN: EPDIE Position */
-#define USBD_GINTEN_EPDIE_Msk (0x1ul << USBD_GINTEN_EPDIE_Pos) /*!< USBD GINTEN: EPDIE Mask */
-
-#define USBD_GINTEN_EPEIE_Pos (6) /*!< USBD GINTEN: EPEIE Position */
-#define USBD_GINTEN_EPEIE_Msk (0x1ul << USBD_GINTEN_EPEIE_Pos) /*!< USBD GINTEN: EPEIE Mask */
-
-#define USBD_GINTEN_EPFIE_Pos (7) /*!< USBD GINTEN: EPFIE Position */
-#define USBD_GINTEN_EPFIE_Msk (0x1ul << USBD_GINTEN_EPFIE_Pos) /*!< USBD GINTEN: EPFIE Mask */
-
-#define USBD_GINTEN_EPGIE_Pos (8) /*!< USBD GINTEN: EPGIE Position */
-#define USBD_GINTEN_EPGIE_Msk (0x1ul << USBD_GINTEN_EPGIE_Pos) /*!< USBD GINTEN: EPGIE Mask */
-
-#define USBD_GINTEN_EPHIE_Pos (9) /*!< USBD GINTEN: EPHIE Position */
-#define USBD_GINTEN_EPHIE_Msk (0x1ul << USBD_GINTEN_EPHIE_Pos) /*!< USBD GINTEN: EPHIE Mask */
-
-#define USBD_GINTEN_EPIIE_Pos (10) /*!< USBD GINTEN: EPIIE Position */
-#define USBD_GINTEN_EPIIE_Msk (0x1ul << USBD_GINTEN_EPIIE_Pos) /*!< USBD GINTEN: EPIIE Mask */
-
-#define USBD_GINTEN_EPJIE_Pos (11) /*!< USBD GINTEN: EPJIE Position */
-#define USBD_GINTEN_EPJIE_Msk (0x1ul << USBD_GINTEN_EPJIE_Pos) /*!< USBD GINTEN: EPJIE Mask */
-
-#define USBD_GINTEN_EPKIE_Pos (12) /*!< USBD GINTEN: EPKIE Position */
-#define USBD_GINTEN_EPKIE_Msk (0x1ul << USBD_GINTEN_EPKIE_Pos) /*!< USBD GINTEN: EPKIE Mask */
-
-#define USBD_GINTEN_EPLIE_Pos (13) /*!< USBD GINTEN: EPLIE Position */
-#define USBD_GINTEN_EPLIE_Msk (0x1ul << USBD_GINTEN_EPLIE_Pos) /*!< USBD GINTEN: EPLIE Mask */
-
-#define USBD_BUSINTSTS_SOFIF_Pos (0) /*!< USBD BUSINTSTS: SOFIF Position */
-#define USBD_BUSINTSTS_SOFIF_Msk (0x1ul << USBD_BUSINTSTS_SOFIF_Pos) /*!< USBD BUSINTSTS: SOFIF Mask */
-
-#define USBD_BUSINTSTS_RSTIF_Pos (1) /*!< USBD BUSINTSTS: RSTIF Position */
-#define USBD_BUSINTSTS_RSTIF_Msk (0x1ul << USBD_BUSINTSTS_RSTIF_Pos) /*!< USBD BUSINTSTS: RSTIF Mask */
-
-#define USBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< USBD BUSINTSTS: RESUMEIF Position */
-#define USBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos) /*!< USBD BUSINTSTS: RESUMEIF Mask */
-
-#define USBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< USBD BUSINTSTS: SUSPENDIF Position */
-#define USBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos) /*!< USBD BUSINTSTS: SUSPENDIF Mask */
-
-#define USBD_BUSINTSTS_HISPDIF_Pos (4) /*!< USBD BUSINTSTS: HISPDIF Position */
-#define USBD_BUSINTSTS_HISPDIF_Msk (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos) /*!< USBD BUSINTSTS: HISPDIF Mask */
-
-#define USBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< USBD BUSINTSTS: DMADONEIF Position */
-#define USBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos) /*!< USBD BUSINTSTS: DMADONEIF Mask */
-
-#define USBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< USBD BUSINTSTS: PHYCLKVLDIF Position */
-#define USBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< USBD BUSINTSTS: PHYCLKVLDIF Mask */
-
-#define USBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< USBD BUSINTSTS: VBUSDETIF Position */
-#define USBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos) /*!< USBD BUSINTSTS: VBUSDETIF Mask */
-
-#define USBD_BUSINTEN_SOFIEN_Pos (0) /*!< USBD BUSINTEN: SOFIEN Position */
-#define USBD_BUSINTEN_SOFIEN_Msk (0x1ul << USBD_BUSINTEN_SOFIEN_Pos) /*!< USBD BUSINTEN: SOFIEN Mask */
-
-#define USBD_BUSINTEN_RSTIEN_Pos (1) /*!< USBD BUSINTEN: RSTIEN Position */
-#define USBD_BUSINTEN_RSTIEN_Msk (0x1ul << USBD_BUSINTEN_RSTIEN_Pos) /*!< USBD BUSINTEN: RSTIEN Mask */
-
-#define USBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< USBD BUSINTEN: RESUMEIEN Position */
-#define USBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos) /*!< USBD BUSINTEN: RESUMEIEN Mask */
-
-#define USBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< USBD BUSINTEN: SUSPENDIEN Position */
-#define USBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos) /*!< USBD BUSINTEN: SUSPENDIEN Mask */
-
-#define USBD_BUSINTEN_HISPDIEN_Pos (4) /*!< USBD BUSINTEN: HISPDIEN Position */
-#define USBD_BUSINTEN_HISPDIEN_Msk (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos) /*!< USBD BUSINTEN: HISPDIEN Mask */
-
-#define USBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< USBD BUSINTEN: DMADONEIEN Position */
-#define USBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos) /*!< USBD BUSINTEN: DMADONEIEN Mask */
-
-#define USBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< USBD BUSINTEN: PHYCLKVLDIEN Position */
-#define USBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< USBD BUSINTEN: PHYCLKVLDIEN Mask */
-
-#define USBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< USBD BUSINTEN: VBUSDETIEN Position */
-#define USBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos) /*!< USBD BUSINTEN: VBUSDETIEN Mask */
-
-#define USBD_OPER_RESUMEEN_Pos (0) /*!< USBD OPER: RESUMEEN Position */
-#define USBD_OPER_RESUMEEN_Msk (0x1ul << USBD_OPER_RESUMEEN_Pos) /*!< USBD OPER: RESUMEEN Mask */
-
-#define USBD_OPER_HISPDEN_Pos (1) /*!< USBD OPER: HISPDEN Position */
-#define USBD_OPER_HISPDEN_Msk (0x1ul << USBD_OPER_HISPDEN_Pos) /*!< USBD OPER: HISPDEN Mask */
-
-#define USBD_OPER_CURSPD_Pos (2) /*!< USBD OPER: CURSPD Position */
-#define USBD_OPER_CURSPD_Msk (0x1ul << USBD_OPER_CURSPD_Pos) /*!< USBD OPER: CURSPD Mask */
-
-#define USBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< USBD FRAMECNT: MFRAMECNT Position */
-#define USBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos) /*!< USBD FRAMECNT: MFRAMECNT Mask */
-
-#define USBD_FRAMECNT_FRAMECNT_Pos (3) /*!< USBD FRAMECNT: FRAMECNT Position */
-#define USBD_FRAMECNT_FRAMECNT_Msk (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos) /*!< USBD FRAMECNT: FRAMECNT Mask */
-
-#define USBD_FADDR_FADDR_Pos (0) /*!< USBD FADDR: FADDR Position */
-#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD FADDR: FADDR Mask */
-
-#define USBD_TEST_TESTMODE_Pos (0) /*!< USBD TEST: TESTMODE Position */
-#define USBD_TEST_TESTMODE_Msk (0x7ul << USBD_TEST_TESTMODE_Pos) /*!< USBD TEST: TESTMODE Mask */
-
-#define USBD_CEPDAT_DAT_Pos (0) /*!< USBD CEPDAT: DAT Position */
-#define USBD_CEPDAT_DAT_Msk (0xfffffffful << USBD_CEPDAT_DAT_Pos) /*!< USBD CEPDAT: DAT Mask */
-
-#define USBD_CEPCTL_NAKCLR_Pos (0) /*!< USBD CEPCTL: NAKCLR Position */
-#define USBD_CEPCTL_NAKCLR_Msk (0x1ul << USBD_CEPCTL_NAKCLR_Pos) /*!< USBD CEPCTL: NAKCLR Mask */
-
-#define USBD_CEPCTL_STALLEN_Pos (1) /*!< USBD CEPCTL: STALLEN Position */
-#define USBD_CEPCTL_STALLEN_Msk (0x1ul << USBD_CEPCTL_STALLEN_Pos) /*!< USBD CEPCTL: STALLEN Mask */
-
-#define USBD_CEPCTL_ZEROLEN_Pos (2) /*!< USBD CEPCTL: ZEROLEN Position */
-#define USBD_CEPCTL_ZEROLEN_Msk (0x1ul << USBD_CEPCTL_ZEROLEN_Pos) /*!< USBD CEPCTL: ZEROLEN Mask */
-
-#define USBD_CEPCTL_FLUSH_Pos (3) /*!< USBD CEPCTL: FLUSH Position */
-#define USBD_CEPCTL_FLUSH_Msk (0x1ul << USBD_CEPCTL_FLUSH_Pos) /*!< USBD CEPCTL: FLUSH Mask */
-
-#define USBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< USBD CEPINTEN: SETUPTKIEN Position */
-#define USBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos) /*!< USBD CEPINTEN: SETUPTKIEN Mask */
-
-#define USBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< USBD CEPINTEN: SETUPPKIEN Position */
-#define USBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos) /*!< USBD CEPINTEN: SETUPPKIEN Mask */
-
-#define USBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< USBD CEPINTEN: OUTTKIEN Position */
-#define USBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos) /*!< USBD CEPINTEN: OUTTKIEN Mask */
-
-#define USBD_CEPINTEN_INTKIEN_Pos (3) /*!< USBD CEPINTEN: INTKIEN Position */
-#define USBD_CEPINTEN_INTKIEN_Msk (0x1ul << USBD_CEPINTEN_INTKIEN_Pos) /*!< USBD CEPINTEN: INTKIEN Mask */
-
-#define USBD_CEPINTEN_PINGIEN_Pos (4) /*!< USBD CEPINTEN: PINGIEN Position */
-#define USBD_CEPINTEN_PINGIEN_Msk (0x1ul << USBD_CEPINTEN_PINGIEN_Pos) /*!< USBD CEPINTEN: PINGIEN Mask */
-
-#define USBD_CEPINTEN_TXPKIEN_Pos (5) /*!< USBD CEPINTEN: TXPKIEN Position */
-#define USBD_CEPINTEN_TXPKIEN_Msk (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos) /*!< USBD CEPINTEN: TXPKIEN Mask */
-
-#define USBD_CEPINTEN_RXPKIEN_Pos (6) /*!< USBD CEPINTEN: RXPKIEN Position */
-#define USBD_CEPINTEN_RXPKIEN_Msk (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos) /*!< USBD CEPINTEN: RXPKIEN Mask */
-
-#define USBD_CEPINTEN_NAKIEN_Pos (7) /*!< USBD CEPINTEN: NAKIEN Position */
-#define USBD_CEPINTEN_NAKIEN_Msk (0x1ul << USBD_CEPINTEN_NAKIEN_Pos) /*!< USBD CEPINTEN: NAKIEN Mask */
-
-#define USBD_CEPINTEN_STALLIEN_Pos (8) /*!< USBD CEPINTEN: STALLIEN Position */
-#define USBD_CEPINTEN_STALLIEN_Msk (0x1ul << USBD_CEPINTEN_STALLIEN_Pos) /*!< USBD CEPINTEN: STALLIEN Mask */
-
-#define USBD_CEPINTEN_ERRIEN_Pos (9) /*!< USBD CEPINTEN: ERRIEN Position */
-#define USBD_CEPINTEN_ERRIEN_Msk (0x1ul << USBD_CEPINTEN_ERRIEN_Pos) /*!< USBD CEPINTEN: ERRIEN Mask */
-
-#define USBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< USBD CEPINTEN: STSDONEIEN Position */
-#define USBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos) /*!< USBD CEPINTEN: STSDONEIEN Mask */
-
-#define USBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< USBD CEPINTEN: BUFFULLIEN Position */
-#define USBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos) /*!< USBD CEPINTEN: BUFFULLIEN Mask */
-
-#define USBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< USBD CEPINTEN: BUFEMPTYIEN Position */
-#define USBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< USBD CEPINTEN: BUFEMPTYIEN Mask */
-
-#define USBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< USBD CEPINTSTS: SETUPTKIF Position */
-#define USBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos) /*!< USBD CEPINTSTS: SETUPTKIF Mask */
-
-#define USBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< USBD CEPINTSTS: SETUPPKIF Position */
-#define USBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos) /*!< USBD CEPINTSTS: SETUPPKIF Mask */
-
-#define USBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< USBD CEPINTSTS: OUTTKIF Position */
-#define USBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos) /*!< USBD CEPINTSTS: OUTTKIF Mask */
-
-#define USBD_CEPINTSTS_INTKIF_Pos (3) /*!< USBD CEPINTSTS: INTKIF Position */
-#define USBD_CEPINTSTS_INTKIF_Msk (0x1ul << USBD_CEPINTSTS_INTKIF_Pos) /*!< USBD CEPINTSTS: INTKIF Mask */
-
-#define USBD_CEPINTSTS_PINGIF_Pos (4) /*!< USBD CEPINTSTS: PINGIF Position */
-#define USBD_CEPINTSTS_PINGIF_Msk (0x1ul << USBD_CEPINTSTS_PINGIF_Pos) /*!< USBD CEPINTSTS: PINGIF Mask */
-
-#define USBD_CEPINTSTS_TXPKIF_Pos (5) /*!< USBD CEPINTSTS: TXPKIF Position */
-#define USBD_CEPINTSTS_TXPKIF_Msk (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos) /*!< USBD CEPINTSTS: TXPKIF Mask */
-
-#define USBD_CEPINTSTS_RXPKIF_Pos (6) /*!< USBD CEPINTSTS: RXPKIF Position */
-#define USBD_CEPINTSTS_RXPKIF_Msk (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos) /*!< USBD CEPINTSTS: RXPKIF Mask */
-
-#define USBD_CEPINTSTS_NAKIF_Pos (7) /*!< USBD CEPINTSTS: NAKIF Position */
-#define USBD_CEPINTSTS_NAKIF_Msk (0x1ul << USBD_CEPINTSTS_NAKIF_Pos) /*!< USBD CEPINTSTS: NAKIF Mask */
-
-#define USBD_CEPINTSTS_STALLIF_Pos (8) /*!< USBD CEPINTSTS: STALLIF Position */
-#define USBD_CEPINTSTS_STALLIF_Msk (0x1ul << USBD_CEPINTSTS_STALLIF_Pos) /*!< USBD CEPINTSTS: STALLIF Mask */
-
-#define USBD_CEPINTSTS_ERRIF_Pos (9) /*!< USBD CEPINTSTS: ERRIF Position */
-#define USBD_CEPINTSTS_ERRIF_Msk (0x1ul << USBD_CEPINTSTS_ERRIF_Pos) /*!< USBD CEPINTSTS: ERRIF Mask */
-
-#define USBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< USBD CEPINTSTS: STSDONEIF Position */
-#define USBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos) /*!< USBD CEPINTSTS: STSDONEIF Mask */
-
-#define USBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< USBD CEPINTSTS: BUFFULLIF Position */
-#define USBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos) /*!< USBD CEPINTSTS: BUFFULLIF Mask */
-
-#define USBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< USBD CEPINTSTS: BUFEMPTYIF Position */
-#define USBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< USBD CEPINTSTS: BUFEMPTYIF Mask */
-
-#define USBD_CEPTXCNT_TXCNT_Pos (0) /*!< USBD CEPTXCNT: TXCNT Position */
-#define USBD_CEPTXCNT_TXCNT_Msk (0xfful << USBD_CEPTXCNT_TXCNT_Pos) /*!< USBD CEPTXCNT: TXCNT Mask */
-
-#define USBD_CEPRXCNT_RXCNT_Pos (0) /*!< USBD CEPRXCNT: RXCNT Position */
-#define USBD_CEPRXCNT_RXCNT_Msk (0xfful << USBD_CEPRXCNT_RXCNT_Pos) /*!< USBD CEPRXCNT: RXCNT Mask */
-
-#define USBD_CEPDATCNT_DATCNT_Pos (0) /*!< USBD CEPDATCNT: DATCNT Position */
-#define USBD_CEPDATCNT_DATCNT_Msk (0xfffful << USBD_CEPDATCNT_DATCNT_Pos) /*!< USBD CEPDATCNT: DATCNT Mask */
-
-#define USBD_SETUP1_0_SETUP0_Pos (0) /*!< USBD SETUP1_0: SETUP0 Position */
-#define USBD_SETUP1_0_SETUP0_Msk (0xfful << USBD_SETUP1_0_SETUP0_Pos) /*!< USBD SETUP1_0: SETUP0 Mask */
-
-#define USBD_SETUP1_0_SETUP1_Pos (8) /*!< USBD SETUP1_0: SETUP1 Position */
-#define USBD_SETUP1_0_SETUP1_Msk (0xfful << USBD_SETUP1_0_SETUP1_Pos) /*!< USBD SETUP1_0: SETUP1 Mask */
-
-#define USBD_SETUP3_2_SETUP2_Pos (0) /*!< USBD SETUP3_2: SETUP2 Position */
-#define USBD_SETUP3_2_SETUP2_Msk (0xfful << USBD_SETUP3_2_SETUP2_Pos) /*!< USBD SETUP3_2: SETUP2 Mask */
-
-#define USBD_SETUP3_2_SETUP3_Pos (8) /*!< USBD SETUP3_2: SETUP3 Position */
-#define USBD_SETUP3_2_SETUP3_Msk (0xfful << USBD_SETUP3_2_SETUP3_Pos) /*!< USBD SETUP3_2: SETUP3 Mask */
-
-#define USBD_SETUP5_4_SETUP4_Pos (0) /*!< USBD SETUP5_4: SETUP4 Position */
-#define USBD_SETUP5_4_SETUP4_Msk (0xfful << USBD_SETUP5_4_SETUP4_Pos) /*!< USBD SETUP5_4: SETUP4 Mask */
-
-#define USBD_SETUP5_4_SETUP5_Pos (8) /*!< USBD SETUP5_4: SETUP5 Position */
-#define USBD_SETUP5_4_SETUP5_Msk (0xfful << USBD_SETUP5_4_SETUP5_Pos) /*!< USBD SETUP5_4: SETUP5 Mask */
-
-#define USBD_SETUP7_6_SETUP6_Pos (0) /*!< USBD SETUP7_6: SETUP6 Position */
-#define USBD_SETUP7_6_SETUP6_Msk (0xfful << USBD_SETUP7_6_SETUP6_Pos) /*!< USBD SETUP7_6: SETUP6 Mask */
-
-#define USBD_SETUP7_6_SETUP7_Pos (8) /*!< USBD SETUP7_6: SETUP7 Position */
-#define USBD_SETUP7_6_SETUP7_Msk (0xfful << USBD_SETUP7_6_SETUP7_Pos) /*!< USBD SETUP7_6: SETUP7 Mask */
-
-#define USBD_CEPBUFSTART_SADDR_Pos (0) /*!< USBD CEPBUFSTART: SADDR Position */
-#define USBD_CEPBUFSTART_SADDR_Msk (0xffful << USBD_CEPBUFSTART_SADDR_Pos) /*!< USBD CEPBUFSTART: SADDR Mask */
-
-#define USBD_CEPBUFEND_EADDR_Pos (0) /*!< USBD CEPBUFEND: EADDR Position */
-#define USBD_CEPBUFEND_EADDR_Msk (0xffful << USBD_CEPBUFEND_EADDR_Pos) /*!< USBD CEPBUFEND: EADDR Mask */
-
-#define USBD_DMACTL_EPNUM_Pos (0) /*!< USBD DMACTL: EPNUM Position */
-#define USBD_DMACTL_EPNUM_Msk (0xful << USBD_DMACTL_EPNUM_Pos) /*!< USBD DMACTL: EPNUM Mask */
-
-#define USBD_DMACTL_DMARD_Pos (4) /*!< USBD DMACTL: DMARD Position */
-#define USBD_DMACTL_DMARD_Msk (0x1ul << USBD_DMACTL_DMARD_Pos) /*!< USBD DMACTL: DMARD Mask */
-
-#define USBD_DMACTL_DMAEN_Pos (5) /*!< USBD DMACTL: DMAEN Position */
-#define USBD_DMACTL_DMAEN_Msk (0x1ul << USBD_DMACTL_DMAEN_Pos) /*!< USBD DMACTL: DMAEN Mask */
-
-#define USBD_DMACTL_SGEN_Pos (6) /*!< USBD DMACTL: SGEN Position */
-#define USBD_DMACTL_SGEN_Msk (0x1ul << USBD_DMACTL_SGEN_Pos) /*!< USBD DMACTL: SGEN Mask */
-
-#define USBD_DMACTL_DMARST_Pos (7) /*!< USBD DMACTL: DMARST Position */
-#define USBD_DMACTL_DMARST_Msk (0x1ul << USBD_DMACTL_DMARST_Pos) /*!< USBD DMACTL: DMARST Mask */
-
-#define USBD_DMACNT_DMACNT_Pos (0) /*!< USBD DMACNT: DMACNT Position */
-#define USBD_DMACNT_DMACNT_Msk (0xffffful << USBD_DMACNT_DMACNT_Pos) /*!< USBD DMACNT: DMACNT Mask */
-
-#define USBD_EPDAT_EPDAT_Pos (0) /*!< USBD EPDAT: EPDAT Position */
-#define USBD_EPDAT_EPDAT_Msk (0xfffffffful << USBD_EPDAT_EPDAT_Pos) /*!< USBD EPDAT: EPDAT Mask */
-
-#define USBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< USBD EPINTSTS: BUFFULLIF Position */
-#define USBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos) /*!< USBD EPINTSTS: BUFFULLIF Mask */
-
-#define USBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< USBD EPINTSTS: BUFEMPTYIF Position */
-#define USBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< USBD EPINTSTS: BUFEMPTYIF Mask */
-
-#define USBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< USBD EPINTSTS: SHORTTXIF Position */
-#define USBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos) /*!< USBD EPINTSTS: SHORTTXIF Mask */
-
-#define USBD_EPINTSTS_TXPKIF_Pos (3) /*!< USBD EPINTSTS: TXPKIF Position */
-#define USBD_EPINTSTS_TXPKIF_Msk (0x1ul << USBD_EPINTSTS_TXPKIF_Pos) /*!< USBD EPINTSTS: TXPKIF Mask */
-
-#define USBD_EPINTSTS_RXPKIF_Pos (4) /*!< USBD EPINTSTS: RXPKIF Position */
-#define USBD_EPINTSTS_RXPKIF_Msk (0x1ul << USBD_EPINTSTS_RXPKIF_Pos) /*!< USBD EPINTSTS: RXPKIF Mask */
-
-#define USBD_EPINTSTS_OUTTKIF_Pos (5) /*!< USBD EPINTSTS: OUTTKIF Position */
-#define USBD_EPINTSTS_OUTTKIF_Msk (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos) /*!< USBD EPINTSTS: OUTTKIF Mask */
-
-#define USBD_EPINTSTS_INTKIF_Pos (6) /*!< USBD EPINTSTS: INTKIF Position */
-#define USBD_EPINTSTS_INTKIF_Msk (0x1ul << USBD_EPINTSTS_INTKIF_Pos) /*!< USBD EPINTSTS: INTKIF Mask */
-
-#define USBD_EPINTSTS_PINGIF_Pos (7) /*!< USBD EPINTSTS: PINGIF Position */
-#define USBD_EPINTSTS_PINGIF_Msk (0x1ul << USBD_EPINTSTS_PINGIF_Pos) /*!< USBD EPINTSTS: PINGIF Mask */
-
-#define USBD_EPINTSTS_NAKIF_Pos (8) /*!< USBD EPINTSTS: NAKIF Position */
-#define USBD_EPINTSTS_NAKIF_Msk (0x1ul << USBD_EPINTSTS_NAKIF_Pos) /*!< USBD EPINTSTS: NAKIF Mask */
-
-#define USBD_EPINTSTS_STALLIF_Pos (9) /*!< USBD EPINTSTS: STALLIF Position */
-#define USBD_EPINTSTS_STALLIF_Msk (0x1ul << USBD_EPINTSTS_STALLIF_Pos) /*!< USBD EPINTSTS: STALLIF Mask */
-
-#define USBD_EPINTSTS_NYETIF_Pos (10) /*!< USBD EPINTSTS: NYETIF Position */
-#define USBD_EPINTSTS_NYETIF_Msk (0x1ul << USBD_EPINTSTS_NYETIF_Pos) /*!< USBD EPINTSTS: NYETIF Mask */
-
-#define USBD_EPINTSTS_ERRIF_Pos (11) /*!< USBD EPINTSTS: ERRIF Position */
-#define USBD_EPINTSTS_ERRIF_Msk (0x1ul << USBD_EPINTSTS_ERRIF_Pos) /*!< USBD EPINTSTS: ERRIF Mask */
-
-#define USBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< USBD EPINTSTS: SHORTRXIF Position */
-#define USBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos) /*!< USBD EPINTSTS: SHORTRXIF Mask */
-
-#define USBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< USBD EPINTEN: BUFFULLIEN Position */
-#define USBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos) /*!< USBD EPINTEN: BUFFULLIEN Mask */
-
-#define USBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< USBD EPINTEN: BUFEMPTYIEN Position */
-#define USBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< USBD EPINTEN: BUFEMPTYIEN Mask */
-
-#define USBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< USBD EPINTEN: SHORTTXIEN Position */
-#define USBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos) /*!< USBD EPINTEN: SHORTTXIEN Mask */
-
-#define USBD_EPINTEN_TXPKIEN_Pos (3) /*!< USBD EPINTEN: TXPKIEN Position */
-#define USBD_EPINTEN_TXPKIEN_Msk (0x1ul << USBD_EPINTEN_TXPKIEN_Pos) /*!< USBD EPINTEN: TXPKIEN Mask */
-
-#define USBD_EPINTEN_RXPKIEN_Pos (4) /*!< USBD EPINTEN: RXPKIEN Position */
-#define USBD_EPINTEN_RXPKIEN_Msk (0x1ul << USBD_EPINTEN_RXPKIEN_Pos) /*!< USBD EPINTEN: RXPKIEN Mask */
-
-#define USBD_EPINTEN_OUTTKIEN_Pos (5) /*!< USBD EPINTEN: OUTTKIEN Position */
-#define USBD_EPINTEN_OUTTKIEN_Msk (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos) /*!< USBD EPINTEN: OUTTKIEN Mask */
-
-#define USBD_EPINTEN_INTKIEN_Pos (6) /*!< USBD EPINTEN: INTKIEN Position */
-#define USBD_EPINTEN_INTKIEN_Msk (0x1ul << USBD_EPINTEN_INTKIEN_Pos) /*!< USBD EPINTEN: INTKIEN Mask */
-
-#define USBD_EPINTEN_PINGIEN_Pos (7) /*!< USBD EPINTEN: PINGIEN Position */
-#define USBD_EPINTEN_PINGIEN_Msk (0x1ul << USBD_EPINTEN_PINGIEN_Pos) /*!< USBD EPINTEN: PINGIEN Mask */
-
-#define USBD_EPINTEN_NAKIEN_Pos (8) /*!< USBD EPINTEN: NAKIEN Position */
-#define USBD_EPINTEN_NAKIEN_Msk (0x1ul << USBD_EPINTEN_NAKIEN_Pos) /*!< USBD EPINTEN: NAKIEN Mask */
-
-#define USBD_EPINTEN_STALLIEN_Pos (9) /*!< USBD EPINTEN: STALLIEN Position */
-#define USBD_EPINTEN_STALLIEN_Msk (0x1ul << USBD_EPINTEN_STALLIEN_Pos) /*!< USBD EPINTEN: STALLIEN Mask */
-
-#define USBD_EPINTEN_NYETIEN_Pos (10) /*!< USBD EPINTEN: NYETIEN Position */
-#define USBD_EPINTEN_NYETIEN_Msk (0x1ul << USBD_EPINTEN_NYETIEN_Pos) /*!< USBD EPINTEN: NYETIEN Mask */
-
-#define USBD_EPINTEN_ERRIEN_Pos (11) /*!< USBD EPINTEN: ERRIEN Position */
-#define USBD_EPINTEN_ERRIEN_Msk (0x1ul << USBD_EPINTEN_ERRIEN_Pos) /*!< USBD EPINTEN: ERRIEN Mask */
-
-#define USBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< USBD EPINTEN: SHORTRXIEN Position */
-#define USBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos) /*!< USBD EPINTEN: SHORTRXIEN Mask */
-
-#define USBD_EPDATCNT_DATCNT_Pos (0) /*!< USBD EPDATCNT: DATCNT Position */
-#define USBD_EPDATCNT_DATCNT_Msk (0xfffful << USBD_EPDATCNT_DATCNT_Pos) /*!< USBD EPDATCNT: DATCNT Mask */
-
-#define USBD_EPDATCNT_DMALOOP_Pos (16) /*!< USBD EPDATCNT: DMALOOP Position */
-#define USBD_EPDATCNT_DMALOOP_Msk (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos) /*!< USBD EPDATCNT: DMALOOP Mask */
-
-#define USBD_EPRSPCTL_FLUSH_Pos (0) /*!< USBD EPRSPCTL: FLUSH Position */
-#define USBD_EPRSPCTL_FLUSH_Msk (0x1ul << USBD_EPRSPCTL_FLUSH_Pos) /*!< USBD EPRSPCTL: FLUSH Mask */
-
-#define USBD_EPRSPCTL_MODE_Pos (1) /*!< USBD EPRSPCTL: MODE Position */
-#define USBD_EPRSPCTL_MODE_Msk (0x3ul << USBD_EPRSPCTL_MODE_Pos) /*!< USBD EPRSPCTL: MODE Mask */
-
-#define USBD_EPRSPCTL_TOGGLE_Pos (3) /*!< USBD EPRSPCTL: TOGGLE Position */
-#define USBD_EPRSPCTL_TOGGLE_Msk (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos) /*!< USBD EPRSPCTL: TOGGLE Mask */
-
-#define USBD_EPRSPCTL_HALT_Pos (4) /*!< USBD EPRSPCTL: HALT Position */
-#define USBD_EPRSPCTL_HALT_Msk (0x1ul << USBD_EPRSPCTL_HALT_Pos) /*!< USBD EPRSPCTL: HALT Mask */
-
-#define USBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< USBD EPRSPCTL: ZEROLEN Position */
-#define USBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos) /*!< USBD EPRSPCTL: ZEROLEN Mask */
-
-#define USBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< USBD EPRSPCTL: SHORTTXEN Position */
-#define USBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos) /*!< USBD EPRSPCTL: SHORTTXEN Mask */
-
-#define USBD_EPRSPCTL_DISBUF_Pos (7) /*!< USBD EPRSPCTL: DISBUF Position */
-#define USBD_EPRSPCTL_DISBUF_Msk (0x1ul << USBD_EPRSPCTL_DISBUF_Pos) /*!< USBD EPRSPCTL: DISBUF Mask */
-
-#define USBD_EPMPS_EPMPS_Pos (0) /*!< USBD EPMPS: EPMPS Position */
-#define USBD_EPMPS_EPMPS_Msk (0x7fful << USBD_EPMPS_EPMPS_Pos) /*!< USBD EPMPS: EPMPS Mask */
-
-#define USBD_EPTXCNT_TXCNT_Pos (0) /*!< USBD EPTXCNT: TXCNT Position */
-#define USBD_EPTXCNT_TXCNT_Msk (0x7fful << USBD_EPTXCNT_TXCNT_Pos) /*!< USBD EPTXCNT: TXCNT Mask */
-
-#define USBD_EPCFG_EPEN_Pos (0) /*!< USBD EPCFG: EPEN Position */
-#define USBD_EPCFG_EPEN_Msk (0x1ul << USBD_EPCFG_EPEN_Pos) /*!< USBD EPCFG: EPEN Mask */
-
-#define USBD_EPCFG_EPTYPE_Pos (1) /*!< USBD EPCFG: EPTYPE Position */
-#define USBD_EPCFG_EPTYPE_Msk (0x3ul << USBD_EPCFG_EPTYPE_Pos) /*!< USBD EPCFG: EPTYPE Mask */
-
-#define USBD_EPCFG_EPDIR_Pos (3) /*!< USBD EPCFG: EPDIR Position */
-#define USBD_EPCFG_EPDIR_Msk (0x1ul << USBD_EPCFG_EPDIR_Pos) /*!< USBD EPCFG: EPDIR Mask */
-
-#define USBD_EPCFG_EPNUM_Pos (4) /*!< USBD EPCFG: EPNUM Position */
-#define USBD_EPCFG_EPNUM_Msk (0xful << USBD_EPCFG_EPNUM_Pos) /*!< USBD EPCFG: EPNUM Mask */
-
-#define USBD_EPBUFSTART_SADDR_Pos (0) /*!< USBD EPBUFSTART: SADDR Position */
-#define USBD_EPBUFSTART_SADDR_Msk (0xffful << USBD_EPBUFSTART_SADDR_Pos) /*!< USBD EPBUFSTART: SADDR Mask */
-
-#define USBD_EPBUFEND_EADDR_Pos (0) /*!< USBD EPBUFEND: EADDR Position */
-#define USBD_EPBUFEND_EADDR_Msk (0xffful << USBD_EPBUFEND_EADDR_Pos) /*!< USBD EPBUFEND: EADDR Mask */
-
-#define USBD_DMAADDR_DMAADDR_Pos (0) /*!< USBD DMAADDR: DMAADDR Position */
-#define USBD_DMAADDR_DMAADDR_Msk (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos) /*!< USBD DMAADDR: DMAADDR Mask */
-
-#define USBD_PHYCTL_DPPUEN_Pos (8) /*!< USBD PHYCTL: DPPUEN Position */
-#define USBD_PHYCTL_DPPUEN_Msk (0x1ul << USBD_PHYCTL_DPPUEN_Pos) /*!< USBD PHYCTL: DPPUEN Mask */
-
-#define USBD_PHYCTL_PHYEN_Pos (9) /*!< USBD PHYCTL: PHYEN Position */
-#define USBD_PHYCTL_PHYEN_Msk (0x1ul << USBD_PHYCTL_PHYEN_Pos) /*!< USBD PHYCTL: PHYEN Mask */
-
-#define USBD_PHYCTL_WKEN_Pos (24) /*!< USBD PHYCTL: WKEN Position */
-#define USBD_PHYCTL_WKEN_Msk (0x1ul << USBD_PHYCTL_WKEN_Pos) /*!< USBD PHYCTL: WKEN Mask */
-
-#define USBD_PHYCTL_VBUSDET_Pos (31) /*!< USBD PHYCTL: VBUSDET Position */
-#define USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) /*!< USBD PHYCTL: VBUSDET Mask */
-
-/**@}*/ /* USBD_CONST */
-/**@}*/ /* end of USBD register group */
-
-
-/*---------------------- Watch Dog Timer Controller -------------------------*/
-/**
- @addtogroup WDT Watch Dog Timer Controller(WDT)
- Memory Mapped Structure for WDT Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x00 Watchdog Timer Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |RSTCNT |Clear Watchdog Timer (Write Protect)
- * | | |0 = No effect.
- * | | |1 = Reset the internal 18-bit WDT counter.
- * | | |Note: This bit will be automatically cleared by hardware.
- * |[1] |RSTEN |Watchdog Timer Reset Enable Control (Write Protect)
- * | | |Setting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires.
- * | | |0 = Watchdog Timer time-out reset function Disabled.
- * | | |1 = Watchdog Timer time-out reset function Enabled.
- * |[2] |RSTF |Watchdog Timer Reset Flag
- * | | |This bit indicates the system has been reset by WDT time-out reset or not.
- * | | |0 = Watchdog Timer time-out reset did not occur.
- * | | |1 = Watchdog Timer time-out reset occurred.
- * | | |Note: This bit is cleared by writing 1 to this bit.
- * |[3] |IF |Watchdog Timer Interrupt Flag
- * | | |This bit will set to 1 while WDT counter value reaches the selected WDT time-out interval
- * | | |0 = Watchdog Timer time-out interrupt did not occur.
- * | | |1 = Watchdog Timer time-out interrupt occurred.
- * | | |Note: This bit is cleared by writing 1 to this bit.
- * |[4] |WKEN |Watchdog Timer Wake-Up Function Enable Control (Write Protect)
- * | | |If this bit is set to 1, while WDT interrupt flag (WDT_CTL[3] IF) is generated to 1 and INTEN (WDT_CTL[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
- * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
- * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
- * | | |Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
- * |[5] |WKF |Watchdog Timer Wake-Up Flag
- * | | |This bit indicates the interrupt wake-up flag status of WDT
- * | | |0 = Watchdog Timer does not cause chip wake-up.
- * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[6] |INTEN |Watchdog Timer Interrupt Enable Control (Write Protect)
- * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
- * | | |0 = Watchdog Timer interrupt Disabled.
- * | | |1 = Watchdog Timer interrupt Enabled.
- * |[7] |WDTEN |Watchdog Timer Enable Control (Write Protect)
- * | | |0 = Watchdog Timer Disabled (This action will reset the internal counter).
- * | | |1 = Watchdog Timer Enabled.
- * | | |Note: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0.
- * |[8:10] |TOUTSEL |Watchdog Timer Time-Out Interval Selection (Write Protect)
- * | | |These three bits select the time-out interval period for the Watchdog Timer.
- * | | |000 = 2^4 * TWDT.
- * | | |001 = 2^6 * TWDT.
- * | | |010 = 2^8 * TWDT.
- * | | |011 = 2^10 * TWDT.
- * | | |100 = 2^12 * TWDT.
- * | | |101 = 2^14 * TWDT.
- * | | |110 = 2^16 * TWDT.
- * | | |111 = 2^18 * TWDT.
- * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
- * | | |0 = ICE debug mode acknowledgement affects Watchdog Timer counting.
- * | | |Watchdog Timer counter will be held while CPU is held by ICE.
- * | | |1 = ICE debug mode acknowledgement Disabled.
- * | | |Watchdog Timer counter will keep going no matter CPU is held by ICE or not.
- */
- __IO uint32_t CTL;
-
- /**
- * ALTCTL
- * ===================================================================================================
- * Offset: 0x04 Watchdog Timer Alternative Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:1] |RSTDSEL |Watchdog Timer Reset Delay Selection (Write Protect)
- * | | |When WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened.
- * | | |Software can select a suitable value of WDT reset delay period for different WDT time-out period.
- * | | |00 = Watchdog Timer reset delay period is (1024+2) * WDT_CLK.
- * | | |01 = Watchdog Timer reset delay period is (128+2) * WDT_CLK.
- * | | |10 = Watchdog Timer reset delay period is (16+2) * WDT_CLK.
- * | | |11 = Watchdog Timer reset delay period is (1+2) * WDT_CLK.
- * | | |Note: This register will be reset to 0 if WDT time-out reset happened
- */
- __IO uint32_t ALTCTL;
-
-} WDT_T;
-
-/**
- @addtogroup WDT_CONST WDT Bit Field Definition
- Constant Definitions for WDT Controller
-@{ */
-
-#define WDT_CTL_RSTCNT_Pos (0) /*!< WDT CTL: RSTCNT Position */
-#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT CTL: RSTCNT Mask */
-
-#define WDT_CTL_RSTEN_Pos (1) /*!< WDT CTL: RSTEN Position */
-#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT CTL: RSTEN Mask */
-
-#define WDT_CTL_RSTF_Pos (2) /*!< WDT CTL: RSTF Position */
-#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT CTL: RSTF Mask */
-
-#define WDT_CTL_IF_Pos (3) /*!< WDT CTL: IF Position */
-#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT CTL: IF Mask */
-
-#define WDT_CTL_WKEN_Pos (4) /*!< WDT CTL: WKEN Position */
-#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT CTL: WKEN Mask */
-
-#define WDT_CTL_WKF_Pos (5) /*!< WDT CTL: WKF Position */
-#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT CTL: WKF Mask */
-
-#define WDT_CTL_INTEN_Pos (6) /*!< WDT CTL: INTEN Position */
-#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT CTL: INTEN Mask */
-
-#define WDT_CTL_WDTEN_Pos (7) /*!< WDT CTL: WDTEN Position */
-#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT CTL: WDTEN Mask */
-
-#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT CTL: TOUTSEL Position */
-#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT CTL: TOUTSEL Mask */
-
-#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT CTL: ICEDEBUG Position */
-#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT CTL: ICEDEBUG Mask */
-
-#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT ALTCTL: RSTDSEL Position */
-#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT ALTCTL: RSTDSEL Mask */
-
-/**@}*/ /* WDT_CONST */
-/**@}*/ /* end of WDT register group */
-
-
-/*---------------------- Window Watchdog Timer -------------------------*/
-/**
- @addtogroup WWDT Window Watchdog Timer(WWDT)
- Memory Mapped Structure for WWDT Controller
-@{ */
-
-typedef struct {
-
-
- /**
- * RLDCNT
- * ===================================================================================================
- * Offset: 0x00 Window Watchdog Timer Reload Counter Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:31] |RLDCNT |WWDT Reload Counter Bit
- * | | |Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
- * | | |Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
- * | | |If software writes RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.
- */
- __O uint32_t RLDCNT;
-
- /**
- * CTL
- * ===================================================================================================
- * Offset: 0x04 Window Watchdog Timer Control Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WWDTEN |WWDT Enable Control
- * | | |Set this bit to enable Window Watchdog Timer counter counting.
- * | | |0 = Window Watchdog Timer counter is stopped.
- * | | |1 = Window Watchdog Timer counter is starting counting.
- * |[1] |INTEN |WWDT Interrupt Enable Control
- * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
- * | | |0 = WWDT counter compare match interrupt Disabled.
- * | | |1 = WWDT counter compare match interrupt Enabled.
- * |[8:11] |PSCSEL |WWDT Counter Prescale Period Selection
- * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
- * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
- * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
- * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
- * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
- * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
- * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
- * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
- * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
- * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
- * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
- * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
- * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
- * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
- * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
- * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
- * |[16:21] |CMPDAT |WWDT Window Compare Bits
- * | | |Set this register to adjust the valid reload window.
- * | | |Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
- * | | |If Software writes RLDCNT when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
- * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
- * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
- * | | |WWDT down counter will be held while CPU is held by ICE.
- * | | |1 = ICE debug mode acknowledgement Disabled.
- * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
- */
- __IO uint32_t CTL;
-
- /**
- * STATUS
- * ===================================================================================================
- * Offset: 0x08 Window Watchdog Timer Status Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
- * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.
- * | | |0 = No effect.
- * | | |1 = WWDT counter value matches CMPDAT value.
- * | | |Note: This bit is cleared by writing 1 to it.
- * |[1] |WWDTRF |WWDT Timer-Out Reset Flag
- * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
- * | | |0 = WWDT time-out reset did not occur.
- * | | |1 = WWDT time-out reset occurred.
- * | | |Note: This bit is cleared by writing 1 to it.
- */
- __IO uint32_t STATUS;
-
- /**
- * CNT
- * ===================================================================================================
- * Offset: 0x0C Window Watchdog Timer Counter Value Register
- * ---------------------------------------------------------------------------------------------------
- * |Bits |Field |Descriptions
- * | :----: | :----: | :---- |
- * |[0:5] |CNTDAT |WWDT Counter Value
- * | | |This register reflects the current WWDT counter value and is read only.
- */
- __I uint32_t CNT;
-
-} WWDT_T;
-
-/**
- @addtogroup WWDT_CONST WWDT Bit Field Definition
- Constant Definitions for WWDT Controller
-@{ */
-
-#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT RLDCNT: RLDCNT Position */
-#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT RLDCNT: RLDCNT Mask */
-
-#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT CTL: WWDTEN Position */
-#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT CTL: WWDTEN Mask */
-
-#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT CTL: INTEN Position */
-#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT CTL: INTEN Mask */
-
-#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT CTL: PSCSEL Position */
-#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT CTL: PSCSEL Mask */
-
-#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT CTL: CMPDAT Position */
-#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT CTL: CMPDAT Mask */
-
-#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT CTL: ICEDEBUG Position */
-#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT CTL: ICEDEBUG Mask */
-
-#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT STATUS: WWDTIF Position */
-#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT STATUS: WWDTIF Mask */
-
-#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT STATUS: WWDTRF Position */
-#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT STATUS: WWDTRF Mask */
-
-#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT CNT: CNTDAT Position */
-#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT CNT: CNTDAT Mask */
-
-/**@}*/ /* WWDT_CONST */
-/**@}*/ /* end of WWDT register group */
-
-#if defined ( __CC_ARM )
-#pragma no_anon_unions
-#endif
-
-
-/*@}*/ /* end of group NUC472_442_Peripherals */
-
-/** @addtogroup NUC472_442_PERIPHERAL_MEM_MAP NUC472/NUC442 Peripheral Memory Base
- Memory Mapped Structure for NUC472/NUC442 Peripheral
- @{
- */
-/* Peripheral and SRAM base address */
-#define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */
-#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */
-#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000) /*!< APB Base Address */
-
-/*!< AHB peripherals */
-#define SYS_BASE (AHBPERIPH_BASE + 0x00000)
-#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
-#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
-#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
-#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
-#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
-#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
-#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
-#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180)
-#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0)
-#define GPIOI_BASE (AHBPERIPH_BASE + 0x04200)
-#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
-#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
-#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
-#define USBH_BASE (AHBPERIPH_BASE + 0x09000)
-#define EMAC_BASE (AHBPERIPH_BASE + 0x0B000)
-#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
-#define SD_BASE (AHBPERIPH_BASE + 0x0D000)
-#define EBI_BASE (AHBPERIPH_BASE + 0x10000)
-#define UDC20_BASE (AHBPERIPH_BASE + 0x19000)
-#define CAP_BASE (AHBPERIPH_BASE + 0x30000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x31000)
-#define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000)
-
-/*!< APB2 peripherals */
-#define WDT_BASE (APBPERIPH_BASE + 0x00000)
-#define WWDT_BASE (APBPERIPH_BASE + 0x00100)
-#define OPA_BASE (APBPERIPH_BASE + 0x06000)
-#define I2S0_BASE (APBPERIPH_BASE + 0x08000)
-#define TIMER0_BASE (APBPERIPH_BASE + 0x10000)
-#define TIMER1_BASE (APBPERIPH_BASE + 0x10020)
-#define PWM0_BASE (APBPERIPH_BASE + 0x18000)
-#define EPWM0_BASE (APBPERIPH_BASE + 0x1C000)
-#define SPI0_BASE (APBPERIPH_BASE + 0x20000)
-#define SPI2_BASE (APBPERIPH_BASE + 0x22000)
-#define UART0_BASE (APBPERIPH_BASE + 0x30000)
-#define UART2_BASE (APBPERIPH_BASE + 0x32000)
-#define UART4_BASE (APBPERIPH_BASE + 0x34000)
-#define I2C0_BASE (APBPERIPH_BASE + 0x40000)
-#define I2C2_BASE (APBPERIPH_BASE + 0x42000)
-#define I2C4_BASE (APBPERIPH_BASE + 0x44000)
-#define SC0_BASE (APBPERIPH_BASE + 0x50000)
-#define SC2_BASE (APBPERIPH_BASE + 0x52000)
-#define SC4_BASE (APBPERIPH_BASE + 0x54000)
-#define CAN0_BASE (APBPERIPH_BASE + 0x60000)
-#define QEI0_BASE (APBPERIPH_BASE + 0x70000)
-#define ECAP0_BASE (APBPERIPH_BASE + 0x74000)
-#define PS2D_BASE (APBPERIPH_BASE + 0xA0000)
-
-/*!< APB1 peripherals */
-#define RTC_BASE (APBPERIPH_BASE + 0x01000)
-#define ADC_BASE (APBPERIPH_BASE + 0x03000)
-#define EADC_BASE (APBPERIPH_BASE + 0x04000)
-#define ACMP_BASE (APBPERIPH_BASE + 0x05000)
-#define I2S1_BASE (APBPERIPH_BASE + 0x09000)
-#define OTG_BASE (APBPERIPH_BASE + 0x0D000)
-#define TIMER2_BASE (APBPERIPH_BASE + 0x11000)
-#define TIMER3_BASE (APBPERIPH_BASE + 0x11020)
-#define PWM1_BASE (APBPERIPH_BASE + 0x19000)
-#define EPWM1_BASE (APBPERIPH_BASE + 0x1D000)
-#define SPI1_BASE (APBPERIPH_BASE + 0x21000)
-#define SPI3_BASE (APBPERIPH_BASE + 0x23000)
-#define UART1_BASE (APBPERIPH_BASE + 0x31000)
-#define UART3_BASE (APBPERIPH_BASE + 0x33000)
-#define UART5_BASE (APBPERIPH_BASE + 0x35000)
-#define I2C1_BASE (APBPERIPH_BASE + 0x41000)
-#define I2C3_BASE (APBPERIPH_BASE + 0x43000)
-#define SC1_BASE (APBPERIPH_BASE + 0x51000)
-#define SC3_BASE (APBPERIPH_BASE + 0x53000)
-#define SC5_BASE (APBPERIPH_BASE + 0x55000)
-#define CAN1_BASE (APBPERIPH_BASE + 0x61000)
-#define QEI1_BASE (APBPERIPH_BASE + 0x71000)
-#define ECAP1_BASE (APBPERIPH_BASE + 0x75000)
-#define CRPT_BASE (0x50080000UL)
-
-/*@}*/ /* end of group NUC472_442_PERIPHERAL_MEM_MAP */
-
-
-/** @addtogroup NUC472_442_PERIPHERAL_DECLARATION NUC472/NUC442 Peripheral Pointer
- The Declaration of NUC472/NUC442 Peripheral
- @{
- */
-
-#define SYS ((SYS_T *) SYS_BASE)
-#define CLK ((CLK_T *) CLK_BASE)
-#define PA ((GPIO_T *) GPIOA_BASE)
-#define PB ((GPIO_T *) GPIOB_BASE)
-#define PC ((GPIO_T *) GPIOC_BASE)
-#define PD ((GPIO_T *) GPIOD_BASE)
-#define PE ((GPIO_T *) GPIOE_BASE)
-#define PF ((GPIO_T *) GPIOF_BASE)
-#define PG ((GPIO_T *) GPIOG_BASE)
-#define PH ((GPIO_T *) GPIOH_BASE)
-#define GPA ((GPIO_T *) GPIOA_BASE)
-#define GPB ((GPIO_T *) GPIOB_BASE)
-#define GPC ((GPIO_T *) GPIOC_BASE)
-#define GPD ((GPIO_T *) GPIOD_BASE)
-#define GPE ((GPIO_T *) GPIOE_BASE)
-#define GPF ((GPIO_T *) GPIOF_BASE)
-#define GPG ((GPIO_T *) GPIOG_BASE)
-#define GPH ((GPIO_T *) GPIOH_BASE)
-#define GPI ((GPIO_T *) GPIOI_BASE)
-#define GPIO ((GPIO_DB_T *) GPIO_DBCTL_BASE)
-#define PDMA ((PDMA_T *) PDMA_BASE)
-#define USBH ((USBH_T *) USBH_BASE)
-#define EMAC ((EMAC_T *) EMAC_BASE)
-#define FMC ((FMC_T *) FMC_BASE)
-#define SD ((SDH_T *) SD_BASE)
-#define SIC ((SIC_T *) SIC_BASE)
-#define EBI ((EBI_T *) EBI_BASE)
-#define ICAP ((CAP_T *) CAP_BASE)
-#define SPACC ((SPACC_T *) SPACC_BASE)
-#define CRC ((CRC_T *) CRC_BASE)
-#define TAMPER ((TAMPER_T *) TAMPER_BASE)
-
-#define WDT ((WDT_T *) WDT_BASE)
-#define WWDT ((WWDT_T *) WWDT_BASE)
-#define RTC ((RTC_T *) RTC_BASE)
-#define ADC ((ADC_T *) ADC_BASE)
-#define EADC ((EADC_T *) EADC_BASE)
-#define ACMP ((ACMP_T *) ACMP_BASE)
-
-#define I2S0 ((I2S_T *) I2S0_BASE)
-#define I2S1 ((I2S_T *) I2S1_BASE)
-#define USBD ((USBD_T *) UDC20_BASE)
-#define OTG ((OTG_T *) OTG_BASE)
-#define TIMER0 ((TIMER_T *) TIMER0_BASE)
-#define TIMER1 ((TIMER_T *) TIMER1_BASE)
-#define TIMER2 ((TIMER_T *) TIMER2_BASE)
-#define TIMER3 ((TIMER_T *) TIMER3_BASE)
-#define PWM0 ((PWM_T *) PWM0_BASE)
-#define PWM1 ((PWM_T *) PWM1_BASE)
-#define EPWM0 ((EPWM_T *) EPWM0_BASE)
-#define EPWM1 ((EPWM_T *) EPWM1_BASE)
-#define ECAP0 ((ECAP_T *) ECAP0_BASE)
-#define ECAP1 ((ECAP_T *) ECAP1_BASE)
-#define QEI0 ((QEI_T *) QEI0_BASE)
-#define QEI1 ((QEI_T *) QEI1_BASE)
-#define SPI0 ((SPI_T *) SPI0_BASE)
-#define SPI1 ((SPI_T *) SPI1_BASE)
-#define SPI2 ((SPI_T *) SPI2_BASE)
-#define SPI3 ((SPI_T *) SPI3_BASE)
-#define UART0 ((UART_T *) UART0_BASE)
-#define UART1 ((UART_T *) UART1_BASE)
-#define UART2 ((UART_T *) UART2_BASE)
-#define UART3 ((UART_T *) UART3_BASE)
-#define UART4 ((UART_T *) UART4_BASE)
-#define UART5 ((UART_T *) UART5_BASE)
-#define I2C0 ((I2C_T *) I2C0_BASE)
-#define I2C1 ((I2C_T *) I2C1_BASE)
-#define I2C2 ((I2C_T *) I2C2_BASE)
-#define I2C3 ((I2C_T *) I2C3_BASE)
-#define I2C4 ((I2C_T *) I2C4_BASE)
-#define SC0 ((SC_T *) SC0_BASE)
-#define SC1 ((SC_T *) SC1_BASE)
-#define SC2 ((SC_T *) SC2_BASE)
-#define SC3 ((SC_T *) SC3_BASE)
-#define SC4 ((SC_T *) SC4_BASE)
-#define SC5 ((SC_T *) SC5_BASE)
-#define CAN0 ((CAN_T *) CAN0_BASE)
-#define CAN1 ((CAN_T *) CAN1_BASE)
-#define PS2 ((PS2_T *) PS2D_BASE)
-#define CRPT ((CRPT_T *) CRPT_BASE)
-/*@}*/ /* end of group NUC472_442_PERIPHERAL_DECLARATION */
-
-/** @addtogroup NUC472_442_IO_ROUTINE NUC472/NUC442 I/O Routines
- The Declaration of NUC472/NUC442 I/O Routines
- @{
- */
-
-typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
-typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
-typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
-
-/**
- * @brief Get a 8-bit unsigned value from specified address
- * @param[in] addr Address to get 8-bit data from
- * @return 8-bit unsigned value stored in specified address
- */
-#define M8(addr) (*((vu8 *) (addr)))
-
-/**
- * @brief Get a 16-bit unsigned value from specified address
- * @param[in] addr Address to get 16-bit data from
- * @return 16-bit unsigned value stored in specified address
- * @note The input address must be 16-bit aligned
- */
-#define M16(addr) (*((vu16 *) (addr)))
-
-/**
- * @brief Get a 32-bit unsigned value from specified address
- * @param[in] addr Address to get 32-bit data from
- * @return 32-bit unsigned value stored in specified address
- * @note The input address must be 32-bit aligned
- */
-#define M32(addr) (*((vu32 *) (addr)))
-
-/**
- * @brief Set a 32-bit unsigned value to specified I/O port
- * @param[in] port Port address to set 32-bit data
- * @param[in] value Value to write to I/O port
- * @return None
- * @note The output port must be 32-bit aligned
- */
-#define outpw(port,value) *((volatile unsigned int *)(port)) = value
-
-/**
- * @brief Get a 32-bit unsigned value from specified I/O port
- * @param[in] port Port address to get 32-bit data from
- * @return 32-bit unsigned value stored in specified I/O port
- * @note The input port must be 32-bit aligned
- */
-#define inpw(port) (*((volatile unsigned int *)(port)))
-
-/**
- * @brief Set a 16-bit unsigned value to specified I/O port
- * @param[in] port Port address to set 16-bit data
- * @param[in] value Value to write to I/O port
- * @return None
- * @note The output port must be 16-bit aligned
- */
-#define outps(port,value) *((volatile unsigned short *)(port)) = value
-
-/**
- * @brief Get a 16-bit unsigned value from specified I/O port
- * @param[in] port Port address to get 16-bit data from
- * @return 16-bit unsigned value stored in specified I/O port
- * @note The input port must be 16-bit aligned
- */
-#define inps(port) (*((volatile unsigned short *)(port)))
-
-/**
- * @brief Set a 8-bit unsigned value to specified I/O port
- * @param[in] port Port address to set 8-bit data
- * @param[in] value Value to write to I/O port
- * @return None
- */
-#define outpb(port,value) *((volatile unsigned char *)(port)) = value
-
-/**
- * @brief Get a 8-bit unsigned value from specified I/O port
- * @param[in] port Port address to get 8-bit data from
- * @return 8-bit unsigned value stored in specified I/O port
- */
-#define inpb(port) (*((volatile unsigned char *)(port)))
-
-/**
- * @brief Set a 32-bit unsigned value to specified I/O port
- * @param[in] port Port address to set 32-bit data
- * @param[in] value Value to write to I/O port
- * @return None
- * @note The output port must be 32-bit aligned
- */
-#define outp32(port,value) *((volatile unsigned int *)(port)) = value
-
-/**
- * @brief Get a 32-bit unsigned value from specified I/O port
- * @param[in] port Port address to get 32-bit data from
- * @return 32-bit unsigned value stored in specified I/O port
- * @note The input port must be 32-bit aligned
- */
-#define inp32(port) (*((volatile unsigned int *)(port)))
-
-/**
- * @brief Set a 16-bit unsigned value to specified I/O port
- * @param[in] port Port address to set 16-bit data
- * @param[in] value Value to write to I/O port
- * @return None
- * @note The output port must be 16-bit aligned
- */
-#define outp16(port,value) *((volatile unsigned short *)(port)) = value
-
-/**
- * @brief Get a 16-bit unsigned value from specified I/O port
- * @param[in] port Port address to get 16-bit data from
- * @return 16-bit unsigned value stored in specified I/O port
- * @note The input port must be 16-bit aligned
- */
-#define inp16(port) (*((volatile unsigned short *)(port)))
-
-/**
- * @brief Set a 8-bit unsigned value to specified I/O port
- * @param[in] port Port address to set 8-bit data
- * @param[in] value Value to write to I/O port
- * @return None
- */
-#define outp8(port,value) *((volatile unsigned char *)(port)) = value
-
-/**
- * @brief Get a 8-bit unsigned value from specified I/O port
- * @param[in] port Port address to get 8-bit data from
- * @return 8-bit unsigned value stored in specified I/O port
- */
-#define inp8(port) (*((volatile unsigned char *)(port)))
-
-
-/*@}*/ /* end of group NUC472_442_IO_ROUTINE */
-
-/******************************************************************************/
-/* Legacy Constants */
-/******************************************************************************/
-/** @addtogroup NUC472_442_legacy_Constants NUC472/NUC442 Legacy Constants
- NUC472/NUC442 Legacy Constants
- @{
-*/
-
-#ifndef NULL
-#define NULL (0) ///< NULL pointer
-#endif
-
-#define TRUE (1) ///< Boolean true, define to use in API parameters or return value
-#define FALSE (0) ///< Boolean false, define to use in API parameters or return value
-
-#define ENABLE (1) ///< Enable, define to use in API parameters
-#define DISABLE (0) ///< Disable, define to use in API parameters
-
-/* Define one bit mask */
-#define BIT0 (0x00000001) ///< Bit 0 mask of an 32 bit integer
-#define BIT1 (0x00000002) ///< Bit 1 mask of an 32 bit integer
-#define BIT2 (0x00000004) ///< Bit 2 mask of an 32 bit integer
-#define BIT3 (0x00000008) ///< Bit 3 mask of an 32 bit integer
-#define BIT4 (0x00000010) ///< Bit 4 mask of an 32 bit integer
-#define BIT5 (0x00000020) ///< Bit 5 mask of an 32 bit integer
-#define BIT6 (0x00000040) ///< Bit 6 mask of an 32 bit integer
-#define BIT7 (0x00000080) ///< Bit 7 mask of an 32 bit integer
-#define BIT8 (0x00000100) ///< Bit 8 mask of an 32 bit integer
-#define BIT9 (0x00000200) ///< Bit 9 mask of an 32 bit integer
-#define BIT10 (0x00000400) ///< Bit 10 mask of an 32 bit integer
-#define BIT11 (0x00000800) ///< Bit 11 mask of an 32 bit integer
-#define BIT12 (0x00001000) ///< Bit 12 mask of an 32 bit integer
-#define BIT13 (0x00002000) ///< Bit 13 mask of an 32 bit integer
-#define BIT14 (0x00004000) ///< Bit 14 mask of an 32 bit integer
-#define BIT15 (0x00008000) ///< Bit 15 mask of an 32 bit integer
-#define BIT16 (0x00010000) ///< Bit 16 mask of an 32 bit integer
-#define BIT17 (0x00020000) ///< Bit 17 mask of an 32 bit integer
-#define BIT18 (0x00040000) ///< Bit 18 mask of an 32 bit integer
-#define BIT19 (0x00080000) ///< Bit 19 mask of an 32 bit integer
-#define BIT20 (0x00100000) ///< Bit 20 mask of an 32 bit integer
-#define BIT21 (0x00200000) ///< Bit 21 mask of an 32 bit integer
-#define BIT22 (0x00400000) ///< Bit 22 mask of an 32 bit integer
-#define BIT23 (0x00800000) ///< Bit 23 mask of an 32 bit integer
-#define BIT24 (0x01000000) ///< Bit 24 mask of an 32 bit integer
-#define BIT25 (0x02000000) ///< Bit 25 mask of an 32 bit integer
-#define BIT26 (0x04000000) ///< Bit 26 mask of an 32 bit integer
-#define BIT27 (0x08000000) ///< Bit 27 mask of an 32 bit integer
-#define BIT28 (0x10000000) ///< Bit 28 mask of an 32 bit integer
-#define BIT29 (0x20000000) ///< Bit 29 mask of an 32 bit integer
-#define BIT30 (0x40000000) ///< Bit 30 mask of an 32 bit integer
-#define BIT31 (0x80000000) ///< Bit 31 mask of an 32 bit integer
-
-/* Byte Mask Definitions */
-#define BYTE0_Msk (0x000000FF) ///< Mask to get bit0~bit7 from a 32 bit integer
-#define BYTE1_Msk (0x0000FF00) ///< Mask to get bit8~bit15 from a 32 bit integer
-#define BYTE2_Msk (0x00FF0000) ///< Mask to get bit16~bit23 from a 32 bit integer
-#define BYTE3_Msk (0xFF000000) ///< Mask to get bit24~bit31 from a 32 bit integer
-
-#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
-#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
-#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
-#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
-
-/*@}*/ /* end of group NUC472_442_legacy_Constants */
-
-
-/******************************************************************************/
-/* Peripheral header files */
-/******************************************************************************/
-#include "nuc472_sys.h"
-#include "nuc472_clk.h"
-
-#include "nuc472_acmp.h"
-#include "nuc472_adc.h"
-#include "nuc472_eadc.h"
-#include "nuc472_cap.h"
-#include "nuc472_crypto.h"
-#include "nuc472_pdma.h"
-#include "nuc472_ebi.h"
-#include "nuc472_emac.h"
-#include "nuc472_fmc.h"
-#include "nuc472_gpio.h"
-#include "nuc472_i2c.h"
-#include "nuc472_pwm.h"
-#include "nuc472_rtc.h"
-#include "nuc472_sc.h"
-#include "nuc472_scuart.h"
-#include "nuc472_spi.h"
-#include "nuc472_timer.h"
-#include "nuc472_uart.h"
-#include "nuc472_usbd.h"
-#include "nuc472_wdt.h"
-#include "nuc472_wwdt.h"
-#include "nuc472_i2s.h"
-#include "nuc472_can.h"
-#include "nuc472_sd.h"
-#include "nuc472_ps2.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __NUC472_442_H__ */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_acmp.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/**************************************************************************//**
- * @file acmp.c
- * @version V1.00
- * $Revision: 3 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 Analog Comparator(ACMP) driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_ACMP_Driver ACMP Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
- @{
-*/
-
-
-/**
- * @brief Configure the specified ACMP module
- *
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum comparator number, could be 0, 1, 2
- * @param[in] u32NegSrc is comparator negative input selection. Including:
- * - \ref ACMP_VNEG_PIN
- * - \ref ACMP_VNEG_BANDGAP
- * - \ref ACMP_VNEG_4_OVER_24_VDD
- * - \ref ACMP_VNEG_5_OVER_24_VDD
- * - \ref ACMP_VNEG_6_OVER_24_VDD
- * - \ref ACMP_VNEG_7_OVER_24_VDD
- * - \ref ACMP_VNEG_8_OVER_24_VDD
- * - \ref ACMP_VNEG_9_OVER_24_VDD
- * - \ref ACMP_VNEG_10_OVER_24_VDD
- * - \ref ACMP_VNEG_11_OVER_24_VDD
- * - \ref ACMP_VNEG_12_OVER_24_VDD
- * - \ref ACMP_VNEG_13_OVER_24_VDD
- * - \ref ACMP_VNEG_14_OVER_24_VDD
- * - \ref ACMP_VNEG_15_OVER_24_VDD
- * - \ref ACMP_VNEG_16_OVER_24_VDD
- * - \ref ACMP_VNEG_17_OVER_24_VDD
- * - \ref ACMP_VNEG_18_OVER_24_VDD
- * - \ref ACMP_VNEG_19_OVER_24_VDD
- * - \ref ACMP_VNEG_4_OVER_24_IREF
- * - \ref ACMP_VNEG_5_OVER_24_IREF
- * - \ref ACMP_VNEG_6_OVER_24_IREF
- * - \ref ACMP_VNEG_7_OVER_24_IREF
- * - \ref ACMP_VNEG_8_OVER_24_IREF
- * - \ref ACMP_VNEG_9_OVER_24_IREF
- * - \ref ACMP_VNEG_10_OVER_24_IREF
- * - \ref ACMP_VNEG_11_OVER_24_IREF
- * - \ref ACMP_VNEG_12_OVER_24_IREF
- * - \ref ACMP_VNEG_13_OVER_24_IREF
- * - \ref ACMP_VNEG_14_OVER_24_IREF
- * - \ref ACMP_VNEG_15_OVER_24_IREF
- * - \ref ACMP_VNEG_16_OVER_24_IREF
- * - \ref ACMP_VNEG_17_OVER_24_IREF
- * - \ref ACMP_VNEG_18_OVER_24_IREF
- * - \ref ACMP_VNEG_19_OVER_24_IREF
- *
- * @param[in] u32HysteresisEn is the hysteresis function option. Including:
- * - \ref ACMP_HYSTERESIS_ENABLE
- * - \ref ACMP_HYSTERESIS_DISABLE
- * @return None
- */
-void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
-{
- if(u32NegSrc != ACMP_VNEG_PIN)
- ACMP->VREF = u32NegSrc;
- ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSEN_Msk))) |
- ((u32NegSrc != ACMP_VNEG_PIN ? ACMP_CTL_NEGSEL_Msk : 0) | u32HysteresisEn | ACMP_CTL_ACMPEN_Msk);
-}
-
-/**
- * @brief This function close comparator
- *
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum comparator number.
- *
- * @return None
- */
-void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
-{
- ACMP->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
-}
-
-
-
-/*@}*/ /* end of group NUC472_442_ACMP_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_ACMP_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_acmp.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,333 +0,0 @@
-/**************************************************************************//**
- * @file acmp.h
- * @version V1.00
- * $Revision: 4 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 Analog Comparator(ACMP) driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __ACMP_H__
-#define __ACMP_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_ACMP_Driver ACMP Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* ACMP_CR constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define ACMP_VNEG_PIN (0xFFUL) ///< Selecting the voltage of ACMP negative input pin as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_BANDGAP (0x00UL) ///< Selecting band-gap voltage as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_4_OVER_24_VDD (0x80UL) ///< Selecting 4/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_5_OVER_24_VDD (0x81UL) ///< Selecting 5/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_6_OVER_24_VDD (0x82UL) ///< Selecting 6/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_7_OVER_24_VDD (0x83UL) ///< Selecting 7/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_8_OVER_24_VDD (0x84UL) ///< Selecting 8/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_9_OVER_24_VDD (0x85UL) ///< Selecting 9/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_10_OVER_24_VDD (0x86UL) ///< Selecting 10/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_11_OVER_24_VDD (0x87UL) ///< Selecting 11/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_12_OVER_24_VDD (0x88UL) ///< Selecting 12/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_13_OVER_24_VDD (0x89UL) ///< Selecting 13/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_14_OVER_24_VDD (0x8AUL) ///< Selecting 14/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_15_OVER_24_VDD (0x8BUL) ///< Selecting 15/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_16_OVER_24_VDD (0x8CUL) ///< Selecting 16/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_17_OVER_24_VDD (0x8DUL) ///< Selecting 17/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_18_OVER_24_VDD (0x8EUL) ///< Selecting 18/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_19_OVER_24_VDD (0x8FUL) ///< Selecting 19/24 VDD as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_4_OVER_24_IREF (0xC0UL) ///< Selecting 4/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_5_OVER_24_IREF (0xC1UL) ///< Selecting 5/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_6_OVER_24_IREF (0xC2UL) ///< Selecting 6/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_7_OVER_24_IREF (0xC3UL) ///< Selecting 7/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_8_OVER_24_IREF (0xC4UL) ///< Selecting 8/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_9_OVER_24_IREF (0xC5UL) ///< Selecting 9/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_10_OVER_24_IREF (0xC6UL) ///< Selecting 10/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_11_OVER_24_IREF (0xC7UL) ///< Selecting 11/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_12_OVER_24_IREF (0xC8UL) ///< Selecting 12/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_13_OVER_24_IREF (0xC9UL) ///< Selecting 13/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_14_OVER_24_IREF (0xCAUL) ///< Selecting 14/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_15_OVER_24_IREF (0xCBUL) ///< Selecting 15/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_16_OVER_24_IREF (0xCCUL) ///< Selecting 16/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_17_OVER_24_IREF (0xCDUL) ///< Selecting 17/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_18_OVER_24_IREF (0xCEUL) ///< Selecting 18/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_VNEG_19_OVER_24_IREF (0xCFUL) ///< Selecting 19/24 IREF as the source of ACMP V- \hideinitializer
-#define ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSEN_Pos) ///< Enable hysteresis function \hideinitializer
-#define ACMP_HYSTERESIS_DISABLE (0UL) ///< Disable hysteresis function \hideinitializer
-#define ACMP_CH0_POSPIN_P0 (0UL) ///< Selecting ACMP0_P0 as ACMP Channel 0 positive input source \hideinitializer
-#define ACMP_CH0_POSPIN_P1 (1UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP0_P1 as ACMP Channel 0 positive input source \hideinitializer
-#define ACMP_CH0_POSPIN_P2 (2UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP0_P2 as ACMP Channel 0 positive input source \hideinitializer
-#define ACMP_CH0_POSPIN_P3 (3UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP0_P3 as ACMP Channel 0 positive input source \hideinitializer
-#define ACMP_CH0_POS_OPA0 (4UL << ACMP_CTL_POSSEL_Pos) ///< Selecting OPA0 as ACMP Channel 0 positive input source \hideinitializer
-#define ACMP_CH1_POSPIN_P0 (0UL) ///< Selecting ACMP1_P0 as ACMP Channel 1 positive input source \hideinitializer
-#define ACMP_CH1_POSPIN_P1 (1UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP1_P1 as ACMP Channel 1 positive input source \hideinitializer
-#define ACMP_CH1_POSPIN_P2 (2UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP1_P2 as ACMP Channel 1 positive input source \hideinitializer
-#define ACMP_CH1_POSPIN_P3 (3UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP1_P3 as ACMP Channel 1 positive input source \hideinitializer
-#define ACMP_CH1_POS_OPA1 (4UL << ACMP_CTL_POSSEL_Pos) ///< Selecting OPA1 as ACMP Channel 1 positive input source \hideinitializer
-#define ACMP_CH2_POSPIN_P0 (0UL) ///< Selecting ACMP2_P0 as ACMP Channel 2 positive input source \hideinitializer
-#define ACMP_CH2_POSPIN_P1 (1UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP2_P1 as ACMP Channel 2 positive input source \hideinitializer
-#define ACMP_CH2_POSPIN_P2 (2UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP2_P2 as ACMP Channel 2 positive input source \hideinitializer
-#define ACMP_CH2_POSPIN_P3 (3UL << ACMP_CTL_POSSEL_Pos) ///< Selecting ACMP2_P3 as ACMP Channel 2 positive input source \hideinitializer
-
-
-/*@}*/ /* end of group NUC472_442_ACMP_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
- @{
-*/
-
-/**
- * @brief This macro is used to select ACMP negative input source
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @param[in] u32Src is comparator negative input selection. Including :
- * - \ref ACMP_VNEG_PIN
- * - \ref ACMP_VNEG_BANDGAP
- * - \ref ACMP_VNEG_4_OVER_24_VDD
- * - \ref ACMP_VNEG_5_OVER_24_VDD
- * - \ref ACMP_VNEG_6_OVER_24_VDD
- * - \ref ACMP_VNEG_7_OVER_24_VDD
- * - \ref ACMP_VNEG_8_OVER_24_VDD
- * - \ref ACMP_VNEG_9_OVER_24_VDD
- * - \ref ACMP_VNEG_10_OVER_24_VDD
- * - \ref ACMP_VNEG_11_OVER_24_VDD
- * - \ref ACMP_VNEG_12_OVER_24_VDD
- * - \ref ACMP_VNEG_13_OVER_24_VDD
- * - \ref ACMP_VNEG_14_OVER_24_VDD
- * - \ref ACMP_VNEG_15_OVER_24_VDD
- * - \ref ACMP_VNEG_16_OVER_24_VDD
- * - \ref ACMP_VNEG_17_OVER_24_VDD
- * - \ref ACMP_VNEG_18_OVER_24_VDD
- * - \ref ACMP_VNEG_19_OVER_24_VDD
- * - \ref ACMP_VNEG_4_OVER_24_IREF
- * - \ref ACMP_VNEG_5_OVER_24_IREF
- * - \ref ACMP_VNEG_6_OVER_24_IREF
- * - \ref ACMP_VNEG_7_OVER_24_IREF
- * - \ref ACMP_VNEG_8_OVER_24_IREF
- * - \ref ACMP_VNEG_9_OVER_24_IREF
- * - \ref ACMP_VNEG_10_OVER_24_IREF
- * - \ref ACMP_VNEG_11_OVER_24_IREF
- * - \ref ACMP_VNEG_12_OVER_24_IREF
- * - \ref ACMP_VNEG_13_OVER_24_IREF
- * - \ref ACMP_VNEG_14_OVER_24_IREF
- * - \ref ACMP_VNEG_15_OVER_24_IREF
- * - \ref ACMP_VNEG_16_OVER_24_IREF
- * - \ref ACMP_VNEG_17_OVER_24_IREF
- * - \ref ACMP_VNEG_18_OVER_24_IREF
- * - \ref ACMP_VNEG_19_OVER_24_IREF
- *
- * @return None
- * @note The V- setting is shared by all comparators if input source is not coming from PIN
- * \hideinitializer
- */
-#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) do{\
- if(u32Src == ACMP_VNEG_PIN)\
- ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk;\
- else {\
- ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk;\
- ACMP->VREF = u32Src\
- }\
- }while(0)
-
-/**
- * @brief This macro is used to enable hysteresis function
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSEN_Msk)
-
-/**
- * @brief This macro is used to disable hysteresis function
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSEN_Msk)
-
-/**
- * @brief This macro is used to enable interrupt
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_ENABLE_INT(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
-
-/**
- * @brief This macro is used to disable interrupt
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_DISABLE_INT(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
-
-
-/**
- * @brief This macro is used to enable ACMP
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_ENABLE(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
-
-/**
- * @brief This macro is used to disable ACMP
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_DISABLE(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
-
-/**
- * @brief This macro is used to get ACMP output value
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return 1 or 0
- * \hideinitializer
- */
-#define ACMP_GET_OUTPUT(acmp, u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
-
-/**
- * @brief This macro is used to get ACMP interrupt flag
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return ACMP interrupt occurred or not
- * \hideinitializer
- */
-#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
-
-/**
- * @brief This macro is used to clear ACMP interrupt flag
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
-
-/**
- * @brief This macro is used to select the V+ pin of ACMP
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @param[in] u32Pin The input pin. For channel 0, valid values are \ref ACMP_CH0_POSPIN_P0,
- * \ref ACMP_CH0_POSPIN_P1, \ref ACMP_CH0_POSPIN_P2, \ref ACMP_CH0_POSPIN_P3, and \ref ACMP_CH0_POS_OPA0.
- * For channel 1, valid values are , \ref ACMP_CH1_POSPIN_P0, \ref ACMP_CH1_POSPIN_P1, \ref ACMP_CH1_POSPIN_P2,
- * \ref ACMP_CH1_POSPIN_P3, and \ref ACMP_CH1_POS_OPA1. For channel 2, valid values are , \ref ACMP_CH2_POSPIN_P0,
- * \ref ACMP_CH2_POSPIN_P1, \ref ACMP_CH2_POSPIN_P2, and \ref ACMP_CH2_POSPIN_P3.
- * @return None
- * @note Except this setting, multi-function pin also needs to be configured
- * \hideinitializer
- */
-#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | u32Pin)
-/**
- * @brief This macro is used to set the level of CRV (Comparator Reference Voltage)
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32Level CRV level, possible values are
- * - \ref ACMP_VNEG_4_OVER_24_VDD
- * - \ref ACMP_VNEG_5_OVER_24_VDD
- * - \ref ACMP_VNEG_6_OVER_24_VDD
- * - \ref ACMP_VNEG_7_OVER_24_VDD
- * - \ref ACMP_VNEG_8_OVER_24_VDD
- * - \ref ACMP_VNEG_9_OVER_24_VDD
- * - \ref ACMP_VNEG_10_OVER_24_VDD
- * - \ref ACMP_VNEG_11_OVER_24_VDD
- * - \ref ACMP_VNEG_12_OVER_24_VDD
- * - \ref ACMP_VNEG_13_OVER_24_VDD
- * - \ref ACMP_VNEG_14_OVER_24_VDD
- * - \ref ACMP_VNEG_15_OVER_24_VDD
- * - \ref ACMP_VNEG_16_OVER_24_VDD
- * - \ref ACMP_VNEG_17_OVER_24_VDD
- * - \ref ACMP_VNEG_18_OVER_24_VDD
- * - \ref ACMP_VNEG_19_OVER_24_VDD
- * - \ref ACMP_VNEG_4_OVER_24_IREF
- * - \ref ACMP_VNEG_5_OVER_24_IREF
- * - \ref ACMP_VNEG_6_OVER_24_IREF
- * - \ref ACMP_VNEG_7_OVER_24_IREF
- * - \ref ACMP_VNEG_8_OVER_24_IREF
- * - \ref ACMP_VNEG_9_OVER_24_IREF
- * - \ref ACMP_VNEG_10_OVER_24_IREF
- * - \ref ACMP_VNEG_11_OVER_24_IREF
- * - \ref ACMP_VNEG_12_OVER_24_IREF
- * - \ref ACMP_VNEG_13_OVER_24_IREF
- * - \ref ACMP_VNEG_14_OVER_24_IREF
- * - \ref ACMP_VNEG_15_OVER_24_IREF
- * - \ref ACMP_VNEG_16_OVER_24_IREF
- * - \ref ACMP_VNEG_17_OVER_24_IREF
- * - \ref ACMP_VNEG_18_OVER_24_IREF
- * - \ref ACMP_VNEG_19_OVER_24_IREF
- * @return None
- * @note This macro does not enable CRV. Please use \ref ACMP_ENABLE_CRV to enable CRV.
- * \hideinitializer
- */
-#define ACMP_CRV_SEL(acmp, u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_IREFSEL_Msk) | (u32Level & ~ACMP_VREF_IREFSEL_Msk))
-/**
- * @brief This macro is used to enable CRV(Comparator Reference Voltage)
- * @param[in] acmp The base address of ACMP module
- * @return None
- * \hideinitializer
- */
-#define ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
-/**
- * @brief This macro is used to disable CRV(Comparator Reference Voltage)
- * @param[in] acmp The base address of ACMP module
- * @return None
- * \hideinitializer
- */
-#define ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
-
-/**
- * @brief This macro is used to enable ACMP output inverse function
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_ENABLE_OUTPUT_INVERSE (acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPOINV_Msk)
-
-/**
- * @brief This macro is used to disable ACMP output inverse function
- * @param[in] acmp The base address of ACMP module
- * @param[in] u32ChNum The ACMP number, could 0, 1, or 2
- * @return None
- * \hideinitializer
- */
-#define ACMP_DISABLE_OUTPUT_INVERSE (acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPOINV_Msk)
-
-
-void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
-void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
-
-/*@}*/ /* end of group NUC472_442_ACMP_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_ACMP_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__ACMP_H__
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_adc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,176 +0,0 @@
-/**************************************************************************//**
- * @file adc.c
- * @version V1.00
- * $Revision: 13 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 ADC driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_ADC_Driver ADC Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
- @{
-*/
-
-/**
- * @brief This API configures ADC module to be ready for convert the input from selected channel
- * @param[in] adc Base address of ADC module
- * @param[in] u32InputMode Input mode (single-end/differential). Valid values are:
- * - \ref ADC_INPUT_MODE_SINGLE_END
- * - \ref ADC_INPUT_MODE_DIFFERENTIAL
- * @param[in] u32OpMode Operation mode (single/single cycle/continuous). Valid values are:
- * - \ref ADC_OPERATION_MODE_SINGLE
- * - \ref ADC_OPERATION_MODE_SINGLE_CYCLE
- * - \ref ADC_OPERATION_MODE_CONTINUOUS
- * @param[in] u32ChMask Channel enable bit. Valid values are:
- * - \ref ADC_CH_0_MASK
- * - \ref ADC_CH_1_MASK
- * - \ref ADC_CH_2_MASK
- * - \ref ADC_CH_3_MASK
- * - \ref ADC_CH_4_MASK
- * - \ref ADC_CH_5_MASK
- * - \ref ADC_CH_6_MASK
- * - \ref ADC_CH_7_MASK
- * - \ref ADC_CH_8_MASK
- * - \ref ADC_CH_9_MASK
- * - \ref ADC_CH_10_MASK
- * - \ref ADC_CH_11_MASK
- * - \ref ADC_CH_TS_MASK
- * - \ref ADC_CH_BG_MASK
- * @return None
- * @note This API does not turn on ADC power nor does trigger ADC conversion
- */
-void ADC_Open(ADC_T *adc,
- uint32_t u32InputMode,
- uint32_t u32OpMode,
- uint32_t u32ChMask)
-{
-
- ADC->CTL |= u32InputMode;
- ADC->CTL |= u32OpMode;
- ADC->CHEN = (ADC->CHEN & ~(ADC_CHEN_CHEN_Msk | ADC_CHEN_ADBGEN_Msk | ADC_CHEN_ADTSEN_Msk)) | u32ChMask;
- return;
-}
-
-/**
- * @brief Disable ADC module
- * @param[in] adc Base address of ADC module
- * @return None
- */
-void ADC_Close(ADC_T *adc)
-{
- SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
- return;
-
-}
-
-/**
- * @brief Configure the hardware trigger condition and enable hardware trigger
- * @param[in] adc Base address of ADC module
- * @param[in] u32Source Decides the hardware trigger source. Valid values are:
- * - \ref ADC_TRIGGER_BY_EXT_PIN
- * - \ref ADC_TRIGGER_BY_PWM
- * @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
- * trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
- * time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
- * is used to set trigger condition. Valid values are:
- * - \ref ADC_LOW_LEVEL_TRIGGER
- * - \ref ADC_HIGH_LEVEL_TRIGGER
- * - \ref ADC_FALLING_EDGE_TRIGGER
- * - \ref ADC_RISING_EDGE_TRIGGER
- * @return None
- */
-void ADC_EnableHWTrigger(ADC_T *adc,
- uint32_t u32Source,
- uint32_t u32Param)
-{
- ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
- if(u32Source == ADC_TRIGGER_BY_EXT_PIN) {
- ADC->CTL &= ~(ADC_CTL_HWTRGSEL_Msk | ADC_CTL_HWTRGCOND_Msk);
- ADC->CTL |= u32Source | u32Param | ADC_CTL_HWTRGEN_Msk;
- } else {
- ADC->CTL &= ~(ADC_CTL_HWTRGSEL_Msk | ADC_CTL_PWMTRGDLY_Msk);
- ADC->CTL |= u32Source | (u32Param << ADC_CTL_PWMTRGDLY_Pos) | ADC_CTL_HWTRGEN_Msk;
- }
-
- return;
-}
-
-/**
- * @brief Disable hardware trigger ADC function.
- * @param[in] adc Base address of ADC module
- * @return None
- */
-void ADC_DisableHWTrigger(ADC_T *adc)
-{
- ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
- return;
-}
-
-/**
- * @brief Enable the interrupt(s) selected by u32Mask parameter.
- * @param[in] adc Base address of ADC module
- * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
- * corresponds to a interrupt status. This parameter decides which
- * interrupts will be enabled.
- * - \ref ADC_ADF_INT
- * - \ref ADC_CMP0_INT
- * - \ref ADC_CMP1_INT
- * @return None
- */
-void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
-{
- if(u32Mask & ADC_ADF_INT)
- ADC->CTL |= ADC_CTL_ADCIEN_Msk;
- if(u32Mask & ADC_CMP0_INT)
- ADC->CMP[0] |= ADC_CMP0_ADCMPIE_Msk;
- if(u32Mask & ADC_CMP1_INT)
- ADC->CMP[1] |= ADC_CMP1_ADCMPIE_Msk;
-
- return;
-}
-
-/**
- * @brief Disable the interrupt(s) selected by u32Mask parameter.
- * @param[in] adc Base address of ADC module
- * @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
- * corresponds to a interrupt status. This parameter decides which
- * interrupts will be disabled.
- * - \ref ADC_ADF_INT
- * - \ref ADC_CMP0_INT
- * - \ref ADC_CMP1_INT
- * @return None
- */
-void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
-{
- if(u32Mask & ADC_ADF_INT)
- ADC->CTL &= ~ADC_CTL_ADCIEN_Msk;
- if(u32Mask & ADC_CMP0_INT)
- ADC->CMP[0] &= ~ADC_CMP0_ADCMPIE_Msk;
- if(u32Mask & ADC_CMP1_INT)
- ADC->CMP[1] &= ~ADC_CMP1_ADCMPIE_Msk;
-
- return;
-}
-
-
-
-/*@}*/ /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_ADC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_adc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,305 +0,0 @@
-/**************************************************************************//**
- * @file adc.h
- * @version V1.00
- * $Revision: 22 $
- * $Date: 14/10/06 5:51p $
- * @brief NUC472/NUC442 ADC driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __ADC_H__
-#define __ADC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_ADC_Driver ADC Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_ADC_EXPORTED_CONSTANTS ADC Exported Constants
- @{
-*/
-
-#define ADC_CH_0_MASK (1UL << 0) /*!< ADC channel 0 mask \hideinitializer */
-#define ADC_CH_1_MASK (1UL << 1) /*!< ADC channel 1 mask \hideinitializer */
-#define ADC_CH_2_MASK (1UL << 2) /*!< ADC channel 2 mask \hideinitializer */
-#define ADC_CH_3_MASK (1UL << 3) /*!< ADC channel 3 mask \hideinitializer */
-#define ADC_CH_4_MASK (1UL << 4) /*!< ADC channel 4 mask \hideinitializer */
-#define ADC_CH_5_MASK (1UL << 5) /*!< ADC channel 5 mask \hideinitializer */
-#define ADC_CH_6_MASK (1UL << 6) /*!< ADC channel 6 mask \hideinitializer */
-#define ADC_CH_7_MASK (1UL << 7) /*!< ADC channel 7 mask \hideinitializer */
-#define ADC_CH_8_MASK (1UL << 8) /*!< ADC channel 8 mask \hideinitializer */
-#define ADC_CH_9_MASK (1UL << 9) /*!< ADC channel 9 mask \hideinitializer */
-#define ADC_CH_10_MASK (1UL << 10) /*!< ADC channel 10 mask \hideinitializer */
-#define ADC_CH_11_MASK (1UL << 11) /*!< ADC channel 11 mask \hideinitializer */
-#define ADC_CH_BG_MASK (1UL << 16) /*!< ADC channel 12 (band-gap ) mask \hideinitializer */
-#define ADC_CH_TS_MASK (1UL << 17) /*!< ADC channel 13 (temperature sensor) mask \hideinitializer */
-#define ADC_CMP_LESS_THAN (0UL) /*!< ADC compare condition less than \hideinitializer */
-#define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMP0_CMPCOND_Msk) /*!< ADC compare condition greater or equal to \hideinitializer */
-#define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC pin \hideinitializer */
-#define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk) /*!< ADC trigger by PWM events \hideinitializer */
-#define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin low level trigger ADC \hideinitializer */
-#define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin high level trigger ADC \hideinitializer */
-#define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin falling edge trigger ADC \hideinitializer */
-#define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CTL_HWTRGCOND_Pos) /*!< External pin rising edge trigger ADC \hideinitializer */
-#define ADC_ADF_INT (ADC_STATUS0_ADIF_Msk) /*!< ADC convert complete interrupt \hideinitializer */
-#define ADC_CMP0_INT (ADC_STATUS0_ADCMPF0_Msk) /*!< ADC comparator 0 interrupt \hideinitializer */
-#define ADC_CMP1_INT (ADC_STATUS0_ADCMPF1_Msk) /*!< ADC comparator 1 interrupt \hideinitializer */
-#define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CTL_DIFFEN_Pos) /*!< ADC input mode set to single end \hideinitializer */
-#define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CTL_DIFFEN_Pos) /*!< ADC input mode set to differential \hideinitializer */
-#define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CTL_OPMODE_Pos) /*!< ADC operation mode set to single conversion \hideinitializer */
-#define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CTL_OPMODE_Pos) /*!< ADC operation mode set to single cycle scan \hideinitializer */
-#define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CTL_OPMODE_Pos) /*!< ADC operation mode set to continuous scan \hideinitializer */
-#define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CTL_OPMODE_Pos) /*!< ADC differential mode output format with unsigned \hideinitializer */
-#define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CTL_OPMODE_Pos) /*!< ADC differential mode output format with 2's complement \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_ADC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
- @{
-*/
-
-/**
- * @brief Get the latest ADC conversion data
- * @param[in] adc Base address of ADC module
- * @param[in] u32ChNum Channel number
- * @return Latest ADC conversion data
- * \hideinitializer
- */
-#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ( ADC->DAT[u32ChNum] & ADC_DAT0_RESULT_Msk)
-
-/**
- * @brief Return the user-specified interrupt flags
- * @param[in] adc Base address of ADC module
- * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
- * - \ref ADC_ADF_INT
- * - \ref ADC_CMP0_INT
- * - \ref ADC_CMP1_INT
- * @return User specified interrupt flags
- * \hideinitializer
- */
-#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->STATUS0 & (u32Mask))
-
-/**
- * @brief This macro clear the selected interrupt status bits
- * @param[in] adc Base address of ADC module
- * @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
- * - \ref ADC_ADF_INT
- * - \ref ADC_CMP0_INT
- * - \ref ADC_CMP1_INT
- * @return None
- * \hideinitializer
- */
-#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->STATUS0 = (ADC->STATUS0 & ~(ADC_STATUS0_ADIF_Msk | \
- ADC_STATUS0_ADCMPF0_Msk | \
- ADC_STATUS0_ADCMPF1_Msk)) | (u32Mask))
-
-/**
- * @brief Get the busy state of ADC
- * @param[in] adc Base address of ADC module
- * @return busy state of ADC
- * @retval 0 ADC is not busy
- * @retval 1 ADC is busy
- * \hideinitializer
- */
-#define ADC_IS_BUSY(adc) (ADC->STATUS0 & ADC_STATUS0_BUSY_Msk ? 1 : 0)
-
-/**
- * @brief Check if the ADC conversion data is over written or not
- * @param[in] adc Base address of ADC module
- * @param[in] u32ChNum Currently not used
- * @return Over run state of ADC data
- * @retval 0 ADC data is not overrun
- * @retval 1 ADC data us overrun
- * \hideinitializer
- */
-#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_OV_Pos + u32ChNum)) ? 1 : 0)
-
-/**
- * @brief Check if the ADC conversion data is valid or not
- * @param[in] adc Base address of ADC module
- * @param[in] u32ChNum Currently not used
- * @return Valid state of ADC data
- * @retval 0 ADC data is not valid
- * @retval 1 ADC data us valid
- * \hideinitializer
- */
-#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_VALID_Pos + u32ChNum)) ? 1 : 0)
-
-/**
- * @brief Power down ADC module
- * @param[in] adc Base address of ADC module
- * @return None
- * \hideinitializer
- */
-#define ADC_POWER_DOWN(adc) (ADC->CTL &= ~ADC_CTL_ADCEN_Msk)
-
-/**
- * @brief Power on ADC module
- * @param[in] adc Base address of ADC module
- * @return None
- * \hideinitializer
- */
-#define ADC_POWER_ON(adc) (ADC->CTL |= ADC_CTL_ADCEN_Msk)
-
-/**
- * @brief Configure the comparator 0 and enable it
- * @param[in] adc Base address of ADC module
- * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
- * @param[in] u32Condition Specifies the compare condition
- * - \ref ADC_CMP_LESS_THAN
- * - \ref ADC_CMP_GREATER_OR_EQUAL_TO
- * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
- * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
- * @return None
- * @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
- * Means ADC will assert comparator 0 flag if channel 5 conversion result is
- * greater or equal to 0x800 for 10 times continuously.
- * \hideinitializer
- */
-#define ADC_ENABLE_CMP0(adc, \
- u32ChNum, \
- u32Condition, \
- u32Data, \
- u32MatchCount) (ADC->CMP[0] = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
- (u32Condition) | \
- ((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
- (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
- ADC_CMP0_ADCMPEN_Msk)
-
-/**
- * @brief Disable comparator 0
- * @param[in] adc Base address of ADC module
- * \hideinitializer
- */
-#define ADC_DISABLE_CMP0(adc) (ADC->CMP[0] = 0)
-
-/**
- * @brief Configure the comparator 1 and enable it
- * @param[in] adc Base address of ADC module
- * @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
- * @param[in] u32Condition Specifies the compare condition
- * - \ref ADC_CMP_LESS_THAN
- * - \ref ADC_CMP_GREATER_OR_EQUAL_TO
- * @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
- * @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
- * @return None
- * @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
- * Means ADC will assert comparator 1 flag if channel 5 conversion result is
- * greater or equal to 0x800 for 10 times continuously.
- * \hideinitializer
- */
-#define ADC_ENABLE_CMP1(adc, \
- u32ChNum, \
- u32Condition, \
- u32Data, \
- u32MatchCount) (ADC->CMP[1] = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
- (u32Condition) | \
- ((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
- ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
- ADC_CMP1_ADCMPEN_Msk)
-
-/**
- * @brief Disable comparator 1
- * @param[in] adc Base address of ADC module
- * \hideinitializer
- */
-#define ADC_DISABLE_CMP1(adc) (ADC->CMP[1] = 0)
-
-/**
- * @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
- * @param[in] adc Base address of ADC module
- * @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- * \hideinitializer
- */
-#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN_Msk) | (u32Mask))
-
-/**
- * @brief Start the A/D conversion.
- * @param[in] adc Base address of ADC module
- * @return None
- * \hideinitializer
- */
-#define ADC_START_CONV(adc) (ADC->CTL |= ADC_CTL_SWTRG_Msk)
-
-/**
- * @brief Stop the A/D conversion.
- * @param[in] adc Base address of ADC module
- * @return None
- * \hideinitializer
- */
-#define ADC_STOP_CONV(adc) (ADC->CTL &= ~ADC_CTL_SWTRG_Msk)
-
-/**
- * @brief Set the output format in differential input mode.
- * @param[in] adc Base address of ADC module
- * @param[in] u32Format Differential input mode output format. Valid values are:
- * - \ref ADC_DMODE_OUT_FORMAT_UNSIGNED
- * - \ref ADC_DMODE_OUT_FORMAT_2COMPLEMENT
- * @return None
- * \hideinitializer
- */
-#define ADC_SET_DMOF(adc, u32Format) (ADC->CTL = (ADC->CTL & ~ADC_CTL_DMOF_Msk) | u32Format)
-
-/**
- * @brief Enable PDMA transfer.
- * @param[in] adc Base address of ADC module
- * @return None
- * \hideinitializer
- */
-#define ADC_ENABLE_PDMA(adc) (ADC->CTL |= ADC_CTL_PDMAEN_Msk)
-
-/**
- * @brief Disable PDMA transfer.
- * @param[in] adc Base address of ADC module
- * @return None
- * \hideinitializer
- */
-#define ADC_DISABLE_PDMA(adc) (ADC->CTL &= ~ADC_CTL_PDMAEN_Msk)
-
-/**
- * @brief Get PDMA current transfer data
- * @param[in] adc Base address of ADC module
- * @return PDMA current transfer data
- * \hideinitializer
- */
-#define ADC_GET_PDMA_DATA(adc) ( ADC->CURDAT & ADC_CURDAT_CURDAT_Msk)
-
-void ADC_Open(ADC_T *adc,
- uint32_t u32InputMode,
- uint32_t u32OpMode,
- uint32_t u32ChMask);
-void ADC_Close(ADC_T *adc);
-void ADC_EnableHWTrigger(ADC_T *adc,
- uint32_t u32Source,
- uint32_t u32Param);
-void ADC_DisableHWTrigger(ADC_T *adc);
-void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
-void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
-
-
-
-/*@}*/ /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_ADC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__ADC_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,750 +0,0 @@
-/**************************************************************************//**
- * @file CAN.c
- * @version V1.00
- * $Revision: 14 $
- * $Date: 14/10/06 5:38p $
- * @brief NUC472/NUC442 CAN driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CAN_Driver CAN Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_CAN_EXPORTED_FUNCTIONS CAN Exported Functions
- @{
-*/
-
-#include <stdio.h>
-
-
-/// @cond HIDDEN_SYMBOLS
-
-
-static uint32_t GetFreeIF(CAN_T *tCAN);
-
-
-//#define DEBUG_PRINTF printf
-#define DEBUG_PRINTF(...)
-
-/**
- * @brief Check if SmartCard slot is presented.
- * @param[in] tCAN The base address of can module.
- * @retval 0 IF0 is free
- * @retval 1 IF1 is free
- * @retval 2 No IF is free
- * @details Search the first free message interface, starting from 0.
- */
-static uint32_t GetFreeIF(CAN_T *tCAN)
-{
- if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
- return 0;
- else if((tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0)
- return 1;
- else
- return 2;
-}
-
-/**
- * @brief Enter initialization mode
- * @param[in] tCAN The base address of can module.
- * @return None
- * @details This function is used to set CAN to enter initialization mode and enable access bit timing
- * register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
- * to leave initialization mode and lock bit timing register to let new configuration
- * take effect.
- */
-void CAN_EnterInitMode(CAN_T *tCAN)
-{
- tCAN->CON |= CAN_CON_INIT_Msk;
- tCAN->CON |= CAN_CON_CCE_Msk;
-}
-
-
-/**
- * @brief Leave initialization mode
- * @param[in] tCAN The base address of can module.
- * @return None
- * @details This function is used to set CAN to leave initialization mode to let
- * bit timing configuration take effect after configuration ready.
- */
-void CAN_LeaveInitMode(CAN_T *tCAN)
-{
- tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
-
- while(tCAN->CON & CAN_CON_INIT_Msk); /* Check INIT bit is released */
-}
-
-/**
- * @brief Wait message into message buffer in basic mode.
- * @param[in] tCAN The base address of can module.
- * @return None
- * @details This function is used to wait message into message buffer in basic mode. Please notice the
- * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
- */
-void CAN_WaitMsg(CAN_T *tCAN)
-{
- tCAN->STATUS = 0x0; /* clr status */
-
- while (1) {
- if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) { /* check new data */
- DEBUG_PRINTF("New Data IN\n");
- break;
- }
- if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
- DEBUG_PRINTF("Rx OK\n");
-
- if(tCAN->STATUS & CAN_STATUS_LEC_Msk) {
- DEBUG_PRINTF("Error\n");
- }
- }
-}
-
-/**
- * @brief Get current bit rate
- * @param[in] tCAN The base address of can module.
- * @return Current Bit-Rate (kilo bit per second)
- * @details Return current CAN bit rate according to the user bit-timing parameter settings
- */
-uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
-{
- uint8_t u8Tseg1,u8Tseg2;
- uint32_t u32Bpr;
-
- u8Tseg1 = (tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos;
- u8Tseg2 = (tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos;
- u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk) | (tCAN->BRPE << 6);
-
- return (SystemCoreClock/(u32Bpr+1)/(u8Tseg1 + u8Tseg2 + 3));
-}
-
-/**
- * @brief Switch the CAN into test mode.
- * @param[in] tCAN The base address of can module.
- * @param[in] u8TestMask Specifies the configuration in test modes
- * CAN_TEST_BASIC_Msk : Enable basic mode of test mode
- * CAN_TESTR_SILENT_Msk : Enable silent mode of test mode
- * CAN_TESTR_LBACK_Msk : Enable Loop Back Mode of test mode
- * CAN_TESTR_TX0_Msk/CAN_TESTR_TX1_Msk: Control CAN_TX pin bit field
- * @return None
- * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
- * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
- * must call CAN_LeaveInitMode() to let the setting take effect.
- */
-void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
-{
- tCAN->CON |= CAN_CON_TEST_Msk;
- tCAN->TEST = u8TestMask;
-}
-
-
-/**
- * @brief Leave the test mode
- * @param[in] tCAN The base address of can module.
- * @return None
- * @details This function is used to Leave the test mode (switch into normal mode).
- */
-void CAN_LeaveTestMode(CAN_T *tCAN)
-{
- tCAN->CON |= CAN_CON_TEST_Msk;
- tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
- tCAN->CON &= (~CAN_CON_TEST_Msk);
-}
-
-/**
- * @brief Get the waiting status of a received message.
- * @param[in] tCAN The base address of can module.
- * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
- * @retval non-zero The corresponding message object has a new data bit is set.
- * @retval 0 No message object has new data.
- * @details This function is used to get the waiting status of a received message.
- */
-uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
-{
- return (u8MsgObj < 16 ? tCAN->NDAT1 & (1 << u8MsgObj) : tCAN->NDAT2 & (1 << (u8MsgObj-16)));
-}
-
-
-/**
- * @brief Send CAN message in BASIC mode of test mode
- * @param[in] tCAN The base address of can module.
- * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
- * @return TRUE: Transmission OK
- * FALSE: Check busy flag of interface 0 is timeout
- * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
- * the user should be call CAN_EnterTestMode(CAN_TESTR_BASIC) and let CAN controller enter
- * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
- */
-int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
-{
- uint32_t i=0;
- while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk);
-
- tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
-
- tCAN->IF[0].CMASK = CAN_IF_CMASK_WRRD_Msk;
-
- if (pCanMsg->IdType == CAN_STD_ID) {
- /* standard ID*/
- tCAN->IF[0].ARB1 = 0;
- tCAN->IF[0].ARB2 = (((pCanMsg->Id)&0x7FF)<<2) ;
- } else {
- /* extended ID*/
- tCAN->IF[0].ARB1 = (pCanMsg->Id)&0xFFFF;
- tCAN->IF[0].ARB2 = ((pCanMsg->Id)&0x1FFF0000)>>16 | CAN_IF_ARB2_XTD_Msk;
-
- }
-
- if(pCanMsg->FrameType)
- tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
- else
- tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
-
- tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
- tCAN->IF[0].DAT_A1 = ((uint16_t)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];
- tCAN->IF[0].DAT_A2 = ((uint16_t)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];
- tCAN->IF[0].DAT_B1 = ((uint16_t)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];
- tCAN->IF[0].DAT_B2 = ((uint16_t)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];
-
- /* request transmission*/
- tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
- if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) {
- DEBUG_PRINTF("Cannot clear busy for sending ...\n");
- return FALSE;
- }
-
- tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; // sending
-
- for ( i=0; i<0xFFFFF; i++) {
- if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) break;
- }
-
- if ( i >= 0xFFFFF ) {
- DEBUG_PRINTF("Cannot send out...\n");
- return FALSE;
- }
-
- return TRUE;
-}
-
-
-/**
- * @brief Get a message information in BASIC mode.
- *
- * @param[in] tCAN The base address of can module.
- * @param[out] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @return FALSE No any message received. \n
- * TRUE Receive a message success.
- *
- */
-int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
-{
- if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0) { /* In basic mode, receive data always save in IF2 */
- return FALSE;
- }
-
- tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
-
- tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
- | CAN_IF_CMASK_CONTROL_Msk
- | CAN_IF_CMASK_DATAA_Msk
- | CAN_IF_CMASK_DATAB_Msk;
-
- if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0) {
- /* standard ID*/
- pCanMsg->IdType = CAN_STD_ID;
- pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FF;
-
- } else {
- /* extended ID*/
- pCanMsg->IdType = CAN_EXT_ID;
- pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFF)<<16;
- pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
- }
-
- pCanMsg->FrameType = !((tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) >> CAN_IF_ARB2_DIR_Pos);
-
- pCanMsg->DLC = tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk;
- pCanMsg->Data[0] = tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
- pCanMsg->Data[1] = (tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
- pCanMsg->Data[2] = tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
- pCanMsg->Data[3] = (tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
- pCanMsg->Data[4] = tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
- pCanMsg->Data[5] = (tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
- pCanMsg->Data[6] = tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
- pCanMsg->Data[7] = (tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
-
- return TRUE;
-}
-
-/**
- * @brief Set Rx message object
- * @param[in] tCAN The base address of can module.
- * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
- * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
- * This parameter can be one of the following values:
- * CAN_STD_ID (standard ID, 11-bit)
- * CAN_EXT_ID (extended ID, 29-bit)
- * @param[in] u32id Specifies the identifier used for acceptance filtering.
- * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
- * This parameter can be one of the following values:
- * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
- * FALSE: for a FIFO receive object that is not the last one.
- * @retval TRUE SUCCESS
- * @retval FALSE No useful interface
- * @details The function is used to configure a receive message object.
- */
-int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
-{
- uint8_t u8MsgIfNum=0;
-
- if ((u8MsgIfNum = GetFreeIF(tCAN)) == 2) { /* Check Free Interface for configure */
- return FALSE;
- }
- /* Command Setting */
- tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
- CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
-
- if (u8idType == CAN_STD_ID) { /* According STD/EXT ID format,Configure Mask and Arbitration register */
- tCAN->IF[u8MsgIfNum].ARB1 = 0;
- tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FF)<< 2;
- } else {
- tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFF;
- tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000)>>16;
- }
-
- tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
- if(u8singleOrFifoLast)
- tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
- else
- tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
-
- tCAN->IF[u8MsgIfNum].DAT_A1 = 0;
- tCAN->IF[u8MsgIfNum].DAT_A2 = 0;
- tCAN->IF[u8MsgIfNum].DAT_B1 = 0;
- tCAN->IF[u8MsgIfNum].DAT_B2 = 0;
-
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u8MsgObj;
-
- return TRUE;
-}
-
-
-/**
- * @brief Gets the message
- * @param[in] tCAN The base address of can module.
- * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
- * @param[in] u8Release Specifies the message release indicator.
- * This parameter can be one of the following values:
- * TRUE: the message object is released when getting the data.
- * FALSE:the message object is not released.
- * @param[out] pCanMsg Pointer to the message structure where received data is copied.
- * @retval TRUE Success
- * @retval FALSE No any message received
- * @details Gets the message, if received.
- */
-int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)
-{
- if (!CAN_IsNewDataReceived(tCAN, u8MsgObj)) {
- return FALSE;
- }
-
- tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
-
- /* read the message contents*/
- tCAN->IF[1].CMASK = CAN_IF_CMASK_MASK_Msk
- | CAN_IF_CMASK_ARB_Msk
- | CAN_IF_CMASK_CONTROL_Msk
- | CAN_IF_CMASK_CLRINTPND_Msk
- | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0)
- | CAN_IF_CMASK_DATAA_Msk
- | CAN_IF_CMASK_DATAB_Msk;
-
- tCAN->IF[1].CREQ = 1 + u8MsgObj;
-
- while (tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) {
- /*Wait*/
- }
-
- if ((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0) {
- /* standard ID*/
- pCanMsg->IdType = CAN_STD_ID;
- pCanMsg->Id = (tCAN->IF[1].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2;
- } else {
- /* extended ID*/
- pCanMsg->IdType = CAN_EXT_ID;
- pCanMsg->Id = (((tCAN->IF[1].ARB2) & 0x1FFF)<<16) | tCAN->IF[1].ARB1;
- }
-
- pCanMsg->DLC = tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk;
- pCanMsg->Data[0] = tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk;
- pCanMsg->Data[1] = (tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos;
- pCanMsg->Data[2] = tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk;
- pCanMsg->Data[3] = (tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos;
- pCanMsg->Data[4] = tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk;
- pCanMsg->Data[5] = (tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos;
- pCanMsg->Data[6] = tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk;
- pCanMsg->Data[7] = (tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos;
-
- return TRUE;
-}
-
-/// @endcond HIDDEN_SYMBOLS
-
-
-/**
- * @brief The function is used to set bus timing parameter according current clock and target baud-rate.
- *
- * @param[in] tCAN The base address of can module
- * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz
- *
- * @return u32CurrentBitRate Real baud-rate value
- */
-uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
-{
- uint8_t u8Tseg1,u8Tseg2;
- uint32_t u32Brp;
- uint32_t u32Value;
-
- CAN_EnterInitMode(tCAN);
-
- SystemCoreClockUpdate();
-
-#if 0 // original implementation got 5% inaccuracy.
- u32Value = SystemCoreClock;
-
- if(u32BaudRate * 8 < (u32Value/2)) {
- u8Tseg1 = 2;
- u8Tseg2 = 3;
- } else {
- u8Tseg1 = 2;
- u8Tseg2 = 1;
- }
-#else
- u32Value = SystemCoreClock / u32BaudRate;
- /* Fix for most standard baud rates, include 125K */
-
- u8Tseg1 = 3;
- u8Tseg2 = 2;
- while(1)
- {
- if(((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0) | (u8Tseg1 >= 15))
- break;
-
- u8Tseg1++;
-
- if((u32Value % (u8Tseg1 + u8Tseg2 + 3)) == 0)
- break;
-
- if(u8Tseg2 < 7)
- u8Tseg2++;
- }
-#endif
- u32Brp = SystemCoreClock/(u32BaudRate) / (u8Tseg1 + u8Tseg2 + 3) -1;
-
- u32Value = ((uint32_t)u8Tseg2 << CAN_BTIME_TSEG2_Pos) | ((uint32_t)u8Tseg1 << CAN_BTIME_TSEG1_Pos) |
- (u32Brp & CAN_BTIME_BRP_Msk) | (tCAN->BTIME & CAN_BTIME_SJW_Msk);
- tCAN->BTIME = u32Value;
- tCAN->BRPE = (u32Brp >> 6) & 0x0F;
-
- CAN_LeaveInitMode(tCAN);
-
- return (CAN_GetCANBitRate(tCAN));
-
-}
-
-/**
- * @brief The function is used to disable all CAN interrupt.
- *
- * @param[in] tCAN The base address of can module
- *
- * @return None
- */
-void CAN_Close(CAN_T *tCAN)
-{
- CAN_DisableInt(tCAN, (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk));
-}
-
-/**
- * @brief The function is sets bus timing parameter according current clock and target baud-rate. And set CAN operation mode.
- *
- * @param[in] tCAN The base address of can module
- * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz
- * @param[in] u32Mode The CAN operation mode. ( \ref CAN_NORMAL_MODE / \ref CAN_BASIC_MODE)
- *
- * @return u32CurrentBitRate Real baud-rate value
- */
-uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
-{
- uint32_t u32CurrentBitRate;
-
- u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
-
- if(u32Mode == CAN_BASIC_MODE)
- CAN_EnterTestMode(tCAN, CAN_TEST_BASIC_Msk);
-
- return u32CurrentBitRate;
-}
-
-/**
- * @brief The function is used to configure a transmit object.
- *
- * @param[in] tCAN The base address of can module.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31
- * @param[in] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @return FALSE: No useful interface. \n
- * TRUE : Config message object success.
- *
- */
-int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
-{
- uint8_t u8MsgIfNum=0;
- uint32_t i=0;
-
- while((u8MsgIfNum = GetFreeIF(tCAN)) == 2) {
- i++;
- if(i > 0x10000000)
- return FALSE;
- }
-
- /* update the contents needed for transmission*/
- tCAN->IF[u8MsgIfNum].CMASK = 0xF3; /*CAN_CMASK_WRRD_Msk | CAN_CMASK_MASK_Msk | CAN_CMASK_ARB_Msk
- | CAN_CMASK_CONTROL_Msk | CAN_CMASK_DATAA_Msk | CAN_CMASK_DATAB_Msk ; */
-
- if (pCanMsg->IdType == CAN_STD_ID) {
- /* standard ID*/
- tCAN->IF[u8MsgIfNum].ARB1 = 0;
- tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id)&0x7FF)<<2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
- } else {
- /* extended ID*/
- tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id)&0xFFFF;
- tCAN->IF[u8MsgIfNum].ARB2 = ((pCanMsg->Id)&0x1FFF0000)>>16 | CAN_IF_ARB2_DIR_Msk
- | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
- }
-
- if(pCanMsg->FrameType)
- tCAN->IF[u8MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk;
- else
- tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
-
- tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint16_t)pCanMsg->Data[1]<<8) | pCanMsg->Data[0];
- tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint16_t)pCanMsg->Data[3]<<8) | pCanMsg->Data[2];
- tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint16_t)pCanMsg->Data[5]<<8) | pCanMsg->Data[4];
- tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint16_t)pCanMsg->Data[7]<<8) | pCanMsg->Data[6];
-
- tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC |CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
- tCAN->IF[u8MsgIfNum].CREQ = 1 + u32MsgNum;
-
- return TRUE;
-}
-
-/**
- * @brief Set transmit request bit
- *
- * @param[in] tCAN The base address of can module.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
- *
- * @return TRUE: Start transmit message.
- */
-int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum)
-{
- STR_CANMSG_T rMsg;
- CAN_ReadMsgObj(tCAN, u32MsgNum,TRUE, &rMsg);
- tCAN->IF[0].CMASK = CAN_IF_CMASK_WRRD_Msk |CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
- tCAN->IF[0].CREQ = 1 + u32MsgNum;
-
- return TRUE;
-}
-
-/**
- * @brief Enable CAN interrupt
- *
- * @param[in] tCAN The base address of can module.
- * @param[in] u32Mask Interrupt Mask. ( \ref CAN_CON_IE_Msk / \ref CAN_CON_SIE_Msk / \ref CAN_CON_EIE_Msk)
- *
- * @return None
- */
-void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
-{
- CAN_EnterInitMode(tCAN);
-
- tCAN->CON = (tCAN->CON & 0xF1) | ((u32Mask & CAN_CON_IE_Msk )? CAN_CON_IE_Msk :0)
- | ((u32Mask & CAN_CON_SIE_Msk )? CAN_CON_SIE_Msk:0)
- | ((u32Mask & CAN_CON_EIE_Msk )? CAN_CON_EIE_Msk:0);
-
-
- CAN_LeaveInitMode(tCAN);
-}
-
-/**
- * @brief Disable CAN interrupt
- *
- * @param[in] tCAN The base address of can module.
- * @param[in] u32Mask Interrupt Mask. ( \ref CAN_CON_IE_Msk / \ref CAN_CON_SIE_Msk / \ref CAN_CON_EIE_Msk)
- *
- * @return None
- */
-void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
-{
- CAN_EnterInitMode(tCAN);
-
- tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | ((u32Mask & CAN_CON_SIE_Msk)?CAN_CON_SIE_Msk:0)
- | ((u32Mask & CAN_CON_EIE_Msk)?CAN_CON_EIE_Msk:0));
-
- CAN_LeaveInitMode(tCAN);
-}
-
-
-/**
- * @brief The function is used to configure a receive message object
- *
- * @param[in] tCAN The base address of can module.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31
- * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. ( \ref CAN_STD_ID / \ref CAN_EXT_ID)
- * @param[in] u32ID Specifies the identifier used for acceptance filtering.
- *
- * @return FALSE: No useful interface \n
- * TRUE : Configure a receive message object success.
- *
- */
-int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID)
-{
- uint32_t u32TimeOutCount = 0;
-
- while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, TRUE) == FALSE) {
- u32TimeOutCount++;
-
- if(u32TimeOutCount >= 0x10000000) return FALSE;
- }
-
- return TRUE;
-}
-
-/**
- * @brief The function is used to configure several receive message objects
- *
- * @param[in] tCAN The base address of can module.
- * @param[in] u32MsgNum The starting MSG RAM number. (0 ~ 31)
- * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
- * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. ( \ref CAN_STD_ID / \ref CAN_EXT_ID)
- * @param[in] u32ID Specifies the identifier used for acceptance filtering.
- *
- * @return FALSE: No useful interface \n
- * TRUE : Configure receive message objects success.
- *
- */
-int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
-{
- uint32_t i = 0;
- uint32_t u32TimeOutCount;
- uint32_t u32EOB_Flag = 0;
-
- for(i= 1; i < u32MsgCount; i++) {
- u32TimeOutCount = 0;
-
- u32MsgNum += (i - 1);
-
- if(i == u32MsgCount) u32EOB_Flag = 1;
-
- while(CAN_SetRxMsgObj(tCAN, u32MsgNum, u32IDType, u32ID, u32EOB_Flag) == FALSE) {
- u32TimeOutCount++;
-
- if(u32TimeOutCount >= 0x10000000) return FALSE;
- }
- }
-
- return TRUE;
-}
-
-
-/**
- * @brief Send CAN message.
- * @param[in] tCAN The base address of can module.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31
- * @param[in] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @return FALSE: When operation in basic mode: Transmit message time out, or when operation in normal mode: No useful interface. \n
- * TRUE : Transmit Message success.
- */
-int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
-{
- if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk)) {
- return (CAN_BasicSendMsg(tCAN, pCanMsg));
- } else {
- if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == FALSE)
- return FALSE;
- CAN_TriggerTxMsg(tCAN, u32MsgNum);
- }
-
- return TRUE;
-}
-
-
-/**
- * @brief Gets the message, if received.
- * @param[in] tCAN The base address of can module.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31
- * @param[out] pCanMsg Pointer to the message structure where received data is copied.
- *
- * @return FALSE: No any message received. \n
- * TRUE : Receive Message success.
- */
-int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg)
-{
- if((tCAN->CON & CAN_CON_TEST_Msk) && (tCAN->TEST & CAN_TEST_BASIC_Msk)) {
- return (CAN_BasicReceiveMsg(tCAN, pCanMsg));
- } else {
- return CAN_ReadMsgObj(tCAN, u32MsgNum, TRUE, pCanMsg);
- }
-}
-
-/**
- * @brief Clear interrupt pending bit.
- * @param[in] tCAN The base address of can module.
- * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31
- *
- * @return None
- *
- */
-void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
-{
- uint32_t u32MsgIfNum = 0;
- uint32_t u32IFBusyCount = 0;
-
- while(u32IFBusyCount < 0x10000000) {
- if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) {
- u32MsgIfNum = 0;
- break;
- } else if((tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0) {
- u32MsgIfNum = 1;
- break;
- }
-
- u32IFBusyCount++;
- }
-
- tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
- tCAN->IF[u32MsgIfNum].CREQ = 1 + u32MsgNum;
-
-}
-
-
-/*@}*/ /* end of group NUC472_442_CAN_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_CAN_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_can.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,176 +0,0 @@
-/**************************************************************************//**
- * @file can.h
- * @version V1.00
- * $Revision: 8 $
- * $Date: 14/09/26 3:38p $
- * @brief NUC472/NUC442 CAN driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __CAN_H__
-#define __CAN_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CAN_Driver CAN Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CAN_EXPORTED_TYPEDEF CAN Exported Type Defines
- @{
-*/
-
-/**
- * @details Message ID types.
- */
-typedef enum {
- CAN_STD_ID = 0, /*!< Standard Identifier */
- CAN_EXT_ID = 1 /*!< Extended Identifier */
-} E_CAN_ID_TYPE;
-
-/**
- * @details Message Frame types.
- */
-typedef enum {
- REMOTE_FRAME = 0, /*!< Remote Frame */
- DATA_FRAME = 1 /*!< Data Frame */
-} E_CAN_FRAME_TYPE;
-
-/**
- * @details CAN message structure.
- */
-typedef struct {
- uint32_t IdType; /*!< Identifier Type */
- uint32_t FrameType; /*!< Frame Type */
- uint32_t Id; /*!< Message Identifier */
- uint8_t DLC; /*!< Data Length Code */
- uint8_t Data[8]; /*!< Data byte 0 ~ 7 */
-} STR_CANMSG_T;
-
-/**
- * @details CAN mask message structure.
- */
-typedef struct {
- uint8_t u8Xtd; /*!< Extended Identifier */
- uint8_t u8Dir; /*!< Message Direction */
- uint32_t u32Id; /*!< Message Identifier */
- uint8_t u8IdType; /*!< Identifier Type */
-} STR_CANMASK_T;
-
-/**
- * @details CAN operation mode: normal/basic mode.
- */
-typedef enum {
- CAN_NORMAL_MODE = 1, /*!< Normal Mode */
- CAN_BASIC_MODE = 2 /*!< Basic Mode */
-} CAN_MODE_SELECT;
-
-#define ALL_MSG 32 /*!< All Message ram number */
-#define MSG(id) id /*!< Message ram number */
-
-
-/*@}*/ /* end of group NUC472_442_CAN_EXPORTED_TYPEDEF */
-
-
-/** @addtogroup NUC472_442_CAN_EXPORTED_FUNCTIONS CAN Exported Functions
- @{
-*/
-
-/**
- * @brief Get interrupt status
- *
- * @param[in] can The base address of can module
- *
- * @return CAN module status register value
- * \hideinitializer
- */
-#define CAN_GET_INT_STATUS(can) (can->STATUS)
-
-/**
- * @brief Get specified interrupt pending status
- *
- * @param[in] can The base address of can module
- *
- * @return The source of the interrupt.
- * \hideinitializer
- */
-#define CAN_GET_INT_PENDING_STATUS(can) (can->IIDR)
-
-/**
- * @brief Disable Wakeup function
- *
- * @param[in] can The base address of can module
- *
- * @return None
- * \hideinitializer
- */
-#define CAN_DISABLE_WAKEUP(can) (can->WU_IE = 0)
-
-/**
- * @brief Enable Wakeup function
- *
- * @param[in] can The base address of can module
- *
- * @return None
- * \hideinitializer
- */
-#define CAN_ENABLE_WAKEUP(can) (can->WU_IE = CAN_WUEN_WAKUP_EN_Msk)
-
-/**
- * @brief Get specified Message Object new data into bit value
- *
- * @param[in] can The base address of can module
- * @param[in] u32MsgNum Specified Message Object number. (0 ~ 31)
- *
- * @return Specified Message Object new data into bit value.
- * \hideinitializer
- */
-#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) (u32MsgNum < 16 ? can->NDAT1 & (1 << u32MsgNum) : can->NDAT2 & (1 << (u32MsgNum-16)))
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define CAN functions prototype */
-/*---------------------------------------------------------------------------------------------------------*/
-uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
-uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
-int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
-int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
-void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
-void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
-void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
-int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
-int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
-int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
-int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);
-uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
-void CAN_EnterInitMode(CAN_T *tCAN);
-void CAN_LeaveInitMode(CAN_T *tCAN);
-void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
-void CAN_LeaveTestMode(CAN_T *tCAN);
-
-/*@}*/ /* end of group NUC472_442_CAN_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_CAN_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__CAN_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
-
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_cap.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,370 +0,0 @@
-/**************************************************************************//**
- * @file cap.c
- * @version V0.10
- * $Revision: 17 $
- * $Date: 14/10/06 3:41p $
- * @brief NUC472/NUC442 CAP driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CAP_Driver CAP Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_CAP_EXPORTED_FUNCTIONS CAP Exported Functions
- @{
-*/
-
-/**
- * @brief Open engine clock and sensor clock
- *
- * @param[in] u32InFormat The bits corresponding VSP, HSP, PCLK, INFMT, SNRTYPE, OUTFMT, PDORD and PNFMT configurations.
- * - VSP should be ether \ref CAP_PAR_VSP_LOW or \ref CAP_PAR_VSP_HIGH
- * - HSP should be ether \ref CAP_PAR_HSP_LOW or \ref CAP_PAR_HSP_HIGH
- * - PCLK should be ether \ref CAP_PAR_PCLKP_LOW or \ref CAP_PAR_PCLKP_HIGH
- * - INFMT should be ether \ref CAP_PAR_INFMT_YUV422 or \ref CAP_PAR_INFMT_RGB565
- * - SNRTYPE should be ether \ref CAP_PAR_SENTYPE_CCIR601 or \ref CAP_PAR_SENTYPE_CCIR656
- * - OUTFMT should be one of the following setting
- * - \ref CAP_PAR_OUTFMT_YUV422
- * - \ref CAP_PAR_OUTFMT_ONLY_Y
- * - \ref CAP_PAR_OUTFMT_RGB555
- * - \ref CAP_PAR_OUTFMT_RGB565
- * - PDORD should be one of the following setting
- * - \ref CAP_PAR_INDATORD_YUYV
- * - \ref CAP_PAR_INDATORD_YVYU
- * - \ref CAP_PAR_INDATORD_UYVY
- * - \ref CAP_PAR_INDATORD_VYUY
- * - \ref CAP_PAR_INDATORD_RGGB
- * - \ref CAP_PAR_INDATORD_BGGR
- * - \ref CAP_PAR_INDATORD_GBRG
- * - \ref CAP_PAR_INDATORD_GRBG
- * - PNFMT should be one of the following setting
- * - \ref CAP_PAR_PLNFMT_YUV422
- * - \ref CAP_PAR_PLNFMT_YUV420
- *
- * @param[in] u32OutFormet Capture output format, should be one of following setting
- * - \ref CAP_CTL_PKTEN
- * - \ref CAP_CTL_PLNEN
- *
- * @return None
- *
- * @details Initialize the Image Capture Interface. Register a call back for driver internal using
- */
-void CAP_Open(uint32_t u32InFormat, uint32_t u32OutFormet)
-{
- ICAP->PAR = (ICAP->PAR & ~0x000007BF) | u32InFormat;
- ICAP->CTL = (ICAP->CTL & ~0x00000060) | u32OutFormet;
-}
-
-/**
- * @brief Set Cropping Window Starting Address and Size
- *
- * @param[in] u32VStart: Cropping Window Vertical Starting Address. It should be 0 ~ 0x7FF.
- *
- * @param[in] u32HStart: Cropping Window Horizontal Starting Address. It should be 0 ~ 0x7FF.
- *
- * @param[in] u32Height: Cropping Window Height . It should be 0 ~ 0x7FF.
- *
- * @param[in] u32Width: Cropping Window Width. It should be 0 ~ 0x7FF.
- *
- * @return None
- *
- * @details Set Cropping Window Starting Address Register
- */
-void CAP_SetCroppingWindow(uint32_t u32VStart,uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width)
-{
- ICAP->CWSP = (ICAP->CWSP & ~(CAP_CWSP_CWSADDRV_Msk | CAP_CWSP_CWSADDRH_Msk))
- | (((u32VStart << 16) | u32HStart));
-
- ICAP->CWS = (ICAP->CWS & ~(CAP_CWS_CWH_Msk | CAP_CWS_CWW_Msk))
- | ((u32Height << 16)| u32Width);
-}
-
-
-/**
- * @brief Set System Memory Packet Base Address0 Register
- *
- * @param[in] u32Address : set PKTBA0 register, It should be 0x0 ~ 0xFFFFFFFF
- *
- * @return None
- *
- * @details Set System Memory Packet Base Address Register
- */
-void CAP_SetPacketBuf(uint32_t u32Address )
-{
- ICAP->PKTBA0 = u32Address;
- ICAP->CTL |= CAP_CTL_UPDATE_Msk;
-}
-
-/**
- * @brief Set System Memory Planar Y, U and V Base Address Registers.
- *
- * @param[in] u32YAddr : set YBA register, It should be 0x0 ~ 0xFFFFFFFF
- *
- * @param[in] u32UAddr : set UBA register, It should be 0x0 ~ 0xFFFFFFFF
- *
- * @param[in] u32VAddr : set VBA register, It should be 0x0 ~ 0xFFFFFFFF
- *
- * @return None
- *
- * @details Set System Memory Planar Y,U and V Base Address Registers
- */
-void CAP_SetPlanarBuf(uint32_t u32YAddr, uint32_t u32UAddr, uint32_t u32VAddr)
-{
- ICAP->YBA = u32YAddr;
- ICAP->UBA = u32UAddr;
- ICAP->VBA = u32VAddr;
- ICAP->CTL |= CAP_CTL_UPDATE_Msk;
-}
-
-
-/**
- * @brief Close Image Capture Interface
- *
- * @return None
- */
-void CAP_Close(void)
-{
- ICAP->CTL &= ~CAP_CTL_CAPEN;
-}
-
-
-/**
- * @brief Set CAP Interrupt
- *
- * @param[in] u32IntMask Interrupt settings. It could be
- * - \ref CAP_INT_VIEN_Msk
- * - \ref CAP_INT_MEIEN_Msk
- * - \ref CAP_INT_ADDRMIEN_Msk
- * - \ref CAP_INT_MDIEN_Msk
- * @return None
- *
- * @details Set Video Frame End Interrupt Enable,
- * System Memory Error Interrupt Enable,
- * Address Match Interrupt Enable,
- * Motion Detection Output Finish Interrupt Enable.
- */
-void CAP_EnableInt(uint32_t u32IntMask)
-{
- ICAP->INT = (ICAP->INT & ~(CAP_INT_VIEN_Msk | CAP_INT_MEIEN_Msk | CAP_INT_ADDRMIEN_Msk | CAP_INT_MDIEN_Msk ) )
- | u32IntMask;
-}
-
-/**
- * @brief Disable CAP Interrupt
- *
- * @param[in] u32IntMask Interrupt settings. It could be
- * - \ref CAP_INT_VINTF_Msk
- * - \ref CAP_INT_MEINTF_Msk
- * - \ref CAP_INT_ADDRMINTF_Msk
- * - \ref CAP_INT_MDINTF_Msk
- * @return None
- *
- * @details Disable Video Frame End Interrupt ,
- * System Memory Error Interrupt ,
- * Address Match Interrupt and
- * Motion Detection Output Finish Interrupt .
- */
-void CAP_DisableInt(uint32_t u32IntMask)
-{
- ICAP->INT = (ICAP->INT & ~(u32IntMask) ) ;
-}
-
-/**
- * @brief Start Image Capture Interface
- *
- * @return None
- */
-void CAP_Start(void)
-{
- ICAP->CTL |= CAP_CTL_CAPEN;
-}
-
-/**
- * @brief Stop Image Capture Interface
- *
- * @param[in] u32FrameComplete :
- * TRUE: Capture module automatically disable the CAP module after a frame had been captured
- * FALSE: Stop Capture module now
- * @return None
- *
- * @details if u32FrameComplete is set to TRUE then get a new frame and disable CAP module
- */
-void CAP_Stop(uint32_t u32FrameComplete)
-{
- if(u32FrameComplete==TRUE)
- ICAP->CTL &= ~CAP_CTL_CAPEN;
- else {
- ICAP->CTL |= CAP_CTL_SHUTTER_Msk;
- while(CAP_IS_STOPPED());
- }
-}
-
-/**
- * @brief Set Packet Scaling Vertical and Horizontal Factor Register
- *
- * @param[in] u32VNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF.
- *
- * @param[in] u32VDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF.
- *
- * @param[in] u32HNumerator: Packet Scaling Vertical Factor N. It should be 0 ~ FFFF.
- *
- * @param[in] u32HDenominator: Packet Scaling Vertical Factor M. It should be 0 ~ FFFF.
- *
- * @return None
- *
- */
-void CAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator)
-{
- uint32_t u32NumeratorL, u32NumeratorH;
- uint32_t u32DenominatorL, u32DenominatorH;
-
- u32NumeratorL = u32VNumerator&0xFF;
- u32NumeratorH=u32VNumerator>>8;
- u32DenominatorL = u32VDenominator&0xFF;
- u32DenominatorH = u32VDenominator>>8;
- ICAP->PKTSL = (ICAP->PKTSL & ~(CAP_PKTSL_PKTSVNL_Msk | CAP_PKTSL_PKTSVML_Msk))
- | ((u32NumeratorL << 24)| (u32DenominatorL << 16));
- ICAP->PKTSM = (ICAP->PKTSM & ~(CAP_PKTSM_PKTSVNH_Msk | CAP_PKTSM_PKTSVMH_Msk))
- | ((u32NumeratorH << 24) | (u32DenominatorH << 16));
-
- u32NumeratorL = u32HNumerator&0xFF;
- u32NumeratorH=u32HNumerator>>8;
- u32DenominatorL = u32HDenominator&0xFF;
- u32DenominatorH = u32HDenominator>>8;
- ICAP->PKTSL = (ICAP->PKTSL & ~(CAP_PKTSL_PKTSHNL_Msk | CAP_PKTSL_PKTSHML_Msk))
- | ((u32NumeratorL << 8)| u32DenominatorL);
- ICAP->PKTSM = (ICAP->PKTSM & ~(CAP_PKTSM_PKTSHNH_Msk | CAP_PKTSM_PKTSHMH_Msk))
- | ((u32NumeratorH << 8) | u32DenominatorH);
-}
-
-/**
- * @brief Set Planar Scaling Vertical and Horizontal Factor Register
- *
- * @param[in] u32VNumerator: Planar Scaling Vertical Factor N. It should be 0 ~ FFFF.
- *
- * @param[in] u32VDenominator: Planar Scaling Vertical Factor M. It should be 0 ~ FFFF.
- *
- * @param[in] u32HNumerator: Planar Scaling Vertical Factor N. It should be 0 ~ FFFF.
- *
- * @param[in] u32HDenominator: Planar Scaling Vertical Factor M. It should be 0 ~ FFFF.
- *
- * @return None
- *
- */
-void CAP_SetPlanarScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator)
-{
- uint32_t u32NumeratorL, u32NumeratorH;
- uint32_t u32DenominatorL, u32DenominatorH;
-
- u32NumeratorL = u32VNumerator&0xFF;
- u32NumeratorH = u32VNumerator>>8;
- u32DenominatorL = u32VDenominator&0xFF;
- u32DenominatorH = u32VDenominator>>8;
- ICAP->PLNSL = (ICAP->PLNSL & ~(CAP_PLNSL_PLNSVNL_Msk | CAP_PLNSL_PLNSVML_Msk))
- | ((u32NumeratorL << 24)| (u32DenominatorL << 16));
- ICAP->PLNSM = (ICAP->PLNSM & ~(CAP_PLNSM_PLNSVNH_Msk | CAP_PLNSM_PLNSVMH_Msk))
- | ((u32NumeratorH << 24)| (u32DenominatorH << 16));
-
- u32NumeratorL = u32HNumerator&0xFF;
- u32NumeratorH = u32HNumerator>>8;
- u32DenominatorL = u32HDenominator&0xFF;
- u32DenominatorH = u32HDenominator>>8;
- ICAP->PLNSL = (ICAP->PLNSL & ~(CAP_PLNSL_PLNSHNL_Msk | CAP_PLNSL_PLNSHML_Msk))
- | ((u32NumeratorL << 8)| u32DenominatorL);
- ICAP->PLNSM = (ICAP->PLNSM & ~(CAP_PLNSM_PLNSHNH_Msk | CAP_PLNSM_PLNSHMH_Msk))
- | ((u32NumeratorH << 8)| u32DenominatorH);
-}
-
-/**
- * @brief Set Packet Frame Output Pixel Stride Width.
- *
- * @param[in] u32Stride : set PKTSTRIDE register, It should be 0x0 ~ 0x3FFF
- *
- * @return None
- *
- * @details Set Packet Frame Output Pixel Stride Width
- */
-void CAP_SetPacketStride(uint32_t u32Stride )
-{
- ICAP->STRIDE = (ICAP->STRIDE & ~CAP_STRIDE_PKTSTRIDE_Msk) | u32Stride;
-}
-
-/**
- * @brief Set Planar Frame Output Pixel Stride Width.
- *
- * @param[in] u32Stride : set PLNSTRIDE register, It should be 0x0 ~ 0x3FFF
- *
- * @return None
- *
- * @details Set Planar Frame Output Pixel Stride Width
- */
-void CAP_SetPlanarStride(uint32_t u32Stride )
-{
- ICAP->STRIDE = (ICAP->STRIDE & ~CAP_STRIDE_PLNSTRIDE_Msk) | u32Stride<<CAP_STRIDE_PLNSTRIDE_Pos;
-}
-
-
-/**
- * @brief Enable Motion Detection Function
- *
- * @param[in] u32Freq: Motion Detection Detect Frequency. It should be 0x0 ~ 0x3.
- *
- * @param[in] u32BlockSize: Motion Detection Block Size
- * FALSE : 16x16
- * TRUE : 8x8
- *
- * @param[in] u32Format: Motion Detection Save Mode
- * FALSE : 1 bit DIFF + 7 Y Differential
- * TRUE : 1 bit DIFF only
- *
- * @param[in] u32Threshold: Motion Detection Detect Threshold. It should be 0x0 ~ 0x1F.
- *
- * @param[in] u32YDetAddr : Motion Detection Detect Temp Y Output Address
- *
- * @param[in] u32DetAddr: Motion Detection Detect Address
- *
- * @return None
- *
- * @details Set Planar Frame Output Pixel Stride Width
- */
-void CAP_EnableMotionDet(uint32_t u32Freq, uint32_t u32BlockSize, uint32_t u32Format, uint32_t u32Threshold, uint32_t u32YDetAddr, uint32_t u32DetAddr)
-{
- ICAP->MD = (ICAP->MD & ~(CAP_MD_MDSM_Msk | CAP_MD_MDBS_Msk | CAP_MD_MDEN_Msk)) |
- ((CAP_MD_MDEN_Msk | (u32BlockSize?CAP_MD_MDBS_Msk:0)) |
- (u32Format?CAP_MD_MDSM_Msk:0));
-
- ICAP->MD = (ICAP->MD & ~CAP_MD_MDDF_Msk) | (u32Freq<<CAP_MD_MDDF_Pos);
- ICAP->MD = (ICAP->MD & ~CAP_MD_MDTHR_Msk) | (u32Threshold<<CAP_MD_MDTHR_Pos);
-
- ICAP->MDYADDR = u32YDetAddr;
- ICAP->MDADDR = u32DetAddr;
-}
-
-/**
- * @brief Enable Motion Detection Function
- *
- * @return None
- *
- * @details Set Planar Frame Output Pixel Stride Width
- */
-void CAP_DisableMotionDet(void)
-{
- ICAP->MD &= ~CAP_MD_MDEN_Msk;
-}
-
-/*@}*/ /* end of group NUC472_442_CAP_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_CAP_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_cap.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,169 +0,0 @@
-/**************************************************************************//**
- * @file cap.h
- * @version V0.10
- * $Revision: 16 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC470 series Image Capture Driver Header File
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __CAP_H__
-#define __CAP_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CAP_Driver CAP Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CAP_EXPORTED_CONSTANTS CAP Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* VINCTRL constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CAP_CTL_CAPEN (1ul<<CAP_CTL_CAPEN_Pos) /*!< CAP CTL setting for enabling capture engine mode \hideinitializer */
-#define CAP_CTL_ADDRSW (1ul<<CAP_CTL_ADDRSW_Pos) /*!< CAP CTL setting for packet buffer address switch \hideinitializer */
-#define CAP_CTL_PKTEN (1ul<<CAP_CTL_PKTEN_Pos) /*!< CAP CTL setting for enabling packet output mode \hideinitializer */
-#define CAP_CTL_PLNEN (1ul<<CAP_CTL_PLNEN_Pos) /*!< CAP CTL setting for enabling planar output mode \hideinitializer */
-#define CAP_CTL_SHUTTER (1ul<<CAP_CTL_SHUTTER_Pos) /*!< CAP CTL setting for enabling shutter mode \hideinitializer */
-#define CAP_CTL_UPDATE (1ul<<CAP_CTL_UPDATE_Pos) /*!< CAP CTL setting for enabling update register at new frame \hideinitializer */
-#define CAP_CTL_RESET (1ul<<CAP_CTL_VPRST_Pos) /*!< CAP CTL setting for capture reset \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CAPPAR constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CAP_PAR_INFMT_YUV422 (0ul<<CAP_PAR_INFMT_Pos) /*!< CAP PAR setting for Sensor Input Data YUV422 Format \hideinitializer */
-#define CAP_PAR_INFMT_RGB565 (1ul<<CAP_PAR_INFMT_Pos) /*!< CAP PAR setting for Sensor Input Data RGB565 Format \hideinitializer */
-
-#define CAP_PAR_SENTYPE_CCIR601 (0ul<<CAP_PAR_SENTYPE_Pos) /*!< CAP PAR setting for Sensor Input CCIR601 Type \hideinitializer */
-#define CAP_PAR_SENTYPE_CCIR656 (1ul<<CAP_PAR_SENTYPE_Pos) /*!< CAP PAR setting for Sensor Input CCIR656 Type \hideinitializer */
-
-#define CAP_PAR_INDATORD_YUYV (0x0ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, YUYV \hideinitializer */
-#define CAP_PAR_INDATORD_YVYU (0x1ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, YVYU \hideinitializer */
-#define CAP_PAR_INDATORD_UYVY (0x2ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, UYVY \hideinitializer */
-#define CAP_PAR_INDATORD_VYUY (0x3ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, VYUY \hideinitializer */
-
-#define CAP_PAR_INDATORD_RGGB (0x0ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: R[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
-#define CAP_PAR_INDATORD_BGGR (0x1ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: b[0:4] G[5:8], 1byte G[0:2] R[3:8] \hideinitializer */
-#define CAP_PAR_INDATORD_GBRG (0x2ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
-#define CAP_PAR_INDATORD_GRBG (0x3ul<<CAP_PAR_INDATORD_Pos) /*!< CAP PAR setting for Sensor Input Data Order, 0byte: G[0:3] G[4:8], 1byte G[0:4] G[5:8] \hideinitializer */
-
-#define CAP_PAR_OUTFMT_YUV422 (0x0ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data YUV422 Format Output to System Memory \hideinitializer */
-#define CAP_PAR_OUTFMT_ONLY_Y (0x1ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data ONLY_Y Format Output to System Memory \hideinitializer */
-#define CAP_PAR_OUTFMT_RGB555 (0x2ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data RGB555 Format Output to System Memory \hideinitializer */
-#define CAP_PAR_OUTFMT_RGB565 (0x3ul<<CAP_PAR_OUTFMT_Pos) /*!< CAP PAR setting for Image Data RGB565 Format Output to System Memory \hideinitializer */
-
-#define CAP_PAR_PLNFMT_YUV422 (0x0ul<<CAP_PAR_PLNFMT_Pos) /*!< CAP PAR setting for Planar Output YUV422 Format \hideinitializer */
-#define CAP_PAR_PLNFMT_YUV420 (0x1ul<<CAP_PAR_PLNFMT_Pos) /*!< CAP PAR setting for Planar Output YUV420 Format \hideinitializer */
-
-#define CAP_PAR_VSP_LOW (0x0ul<<CAP_PAR_VSP_Pos) /*!< CAP PAR setting for Sensor Vsync Polarity \hideinitializer */
-#define CAP_PAR_VSP_HIGH (0x1ul<<CAP_PAR_VSP_Pos) /*!< CAP PAR setting for Sensor Vsync Polarity \hideinitializer */
-#define CAP_PAR_HSP_LOW (0x0ul<<CAP_PAR_HSP_Pos) /*!< CAP PAR setting for Sensor Hsync Polarity \hideinitializer */
-#define CAP_PAR_HSP_HIGH (0x1ul<<CAP_PAR_HSP_Pos) /*!< CAP PAR setting for Sensor Hsync Polarity \hideinitializer */
-#define CAP_PAR_PCLKP_LOW (0x0ul<<CAP_PAR_PCLKP_Pos) /*!< CAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
-#define CAP_PAR_PCLKP_HIGH (0x1ul<<CAP_PAR_PCLKP_Pos) /*!< CAP PAR setting for Sensor Pixel Clock Polarity \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* VININT constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CAP_INT_VIEN_ENABLE (0x1ul<<CAP_INT_VIEN_Pos) /*!< VININT setting for Frame End Interrupt enable \hideinitializer */
-#define CAP_INT_MEIEN_ENABLE (0x1ul<<CAP_INT_MEIEN_Pos) /*!< VININT setting for Bus Master Transfer Error Interrupt enable \hideinitializer */
-#define CAP_INT_ADDRMIEN_ENABLE (0x1ul<<CAP_INT_ADDRMIEN_Pos) /*!< VININT setting for Memory Address Match Interrupt enable \hideinitializer */
-#define CAP_INT_MDIEN_ENABLE (0x1ul<<CAP_INT_MDIEN_Pos) /*!< VININT setting for Motion Detection Output Finish Interrupt Enable enable \hideinitializer */
-
-
-static uint32_t u32EscapeFrame = 0;
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define Error Code */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CAP_INVALID_INT ((int32_t)(0xFFFFFFFF-1))
-#define CAP_INVALID_BUF ((int32_t)(0xFFFFFFFF-2))
-#define CAP_INVALID_PIPE ((int32_t)(0xFFFFFFFF-3))
-
-
-/*@}*/ /* end of group NUC472_442_CAP_EXPORTED_CONSTANTS */
-
-
-
-/** @addtogroup NUC472_442_CAP_EXPORTED_FUNCTIONS CAP Exported Functions
- @{
-*/
-
-/**
- * @brief Is CAP module Enable
- *
- * @return FALSE(Enable) or TRUE(Disable)
- *
- * @details Check Image Capture Interface module Enable or Disable
- * \hideinitializer
- */
-#define CAP_IS_STOPPED() ((ICAP->CTL & CAP_CTL_CAPEN_Msk)?0:1)
-
-/**
- * @brief Clear CAP flag
- *
- * @param[in] u32IntMask interrupt flags settings. It could be
- * - \ref CAP_INT_VINTF_Msk
- * - \ref CAP_INT_MEINTF_Msk
- * - \ref CAP_INT_ADDRMINTF_Msk
- * - \ref CAP_INT_MDINTF_Msk
- *
- * @return TRUE(Enable) or FALSE(Disable)
- *
- * @details Clear Image Capture Interface interrupt flag
- * \hideinitializer
- */
-#define CAP_CLR_INT_FLAG(u32IntMask) (CAP->CAPINT |=u32IntMask)
-
-/**
- * @brief Get CAP Interrupt status
- *
- * @return TRUE(Enable) or FALSE(Disable)
- *
- * @details Get Image Capture Interface interrupt status.
- * \hideinitializer
- */
-#define CAP_GET_INT_STS() (CAP->CAPINT)
-
-void CAP_Open(uint32_t u32InFormat, uint32_t u32OutFormet);
-void CAP_SetCroppingWindow(uint32_t u32VStart,uint32_t u32HStart, uint32_t u32Height, uint32_t u32Width);
-void CAP_SetPacketBuf(uint32_t u32Address );
-void CAP_SetPlanarBuf(uint32_t u32YAddr, uint32_t u32UAddr, uint32_t u32VAddr);
-void CAP_Close(void);
-void CAP_EnableInt(uint32_t u32IntMask);
-void CAP_DisableInt(uint32_t u32IntMask);
-void CAP_Start(void);
-void CAP_Stop(uint32_t u32FrameComplete);
-void CAP_SetPacketScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
-void CAP_SetPlanarScaling(uint32_t u32VNumerator, uint32_t u32VDenominator, uint32_t u32HNumerator, uint32_t u32HDenominator);
-void CAP_SetPacketStride(uint32_t u32Stride );
-void CAP_SetPlanarStride(uint32_t u32Stride );
-void CAP_EnableMotionDet(uint32_t u32Freq, uint32_t u32BlockSize, uint32_t u32Format, uint32_t u32Threshold, uint32_t u32YDetAddr, uint32_t u32DetAddr);
-void CAP_DisableMotionDet(void);
-
-/*@}*/ /* end of group NUC472_442_CAP_EXPORTED_FUNCTIONS */
-
-
-
-/*@}*/ /* end of group NUC472_442_CAP_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__CAP_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,744 +0,0 @@
-/**************************************************************************//**
- * @file clk.c
- * @version V1.00
- * $Revision: 29 $
- * $Date: 14/09/26 2:10p $
- * @brief NUC472/NUC442 CLK driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CLK_Driver CLK Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
- @{
-*/
-
-
-/**
- * @brief Disable frequency output function
- * @return None
- * @details This function disable frequency output function.
- */
-void CLK_DisableCKO(void)
-{
- /* Disable CKO clock source */
- CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
-}
-
-/**
- * @brief This function enable frequency divider module clock,
- * enable frequency divider clock function and configure frequency divider.
- * @param[in] u32ClkSrc is frequency divider function clock source
- * - \ref CLK_CLKSEL1_CLKOSEL_HXT
- * - \ref CLK_CLKSEL1_CLKOSEL_LXT
- * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
- * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
- * @param[in] u32ClkDiv is system reset source
- * @param[in] u32ClkDivBy1En is frequency divided by one enable.
- * @return None
- *
- * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
- * The formula is:
- * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
- * This function is just used to set CKO clock.
- * User must enable I/O for CKO clock output pin by themselves.
- */
-void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
-{
- /* CKO = clock source / 2^(u32ClkDiv + 1) */
- CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_CLKOCTL_DIV1EN_Pos;
-
- /* Enable CKO clock source */
- CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;
-
- /* Select CKO clock source */
- CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | u32ClkSrc;
-}
-
-/**
- * @brief Enter to Power-down mode
- * @return None
- * @details This function let system enter to Power-down mode.
- */
-void CLK_PowerDown(void)
-{
- SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
- CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWKDLY_Msk );
- __WFI();
-}
-
-/**
- * @brief Enter to Idle mode.
- * @return None
- * @details This function let system enter to Idle mode.
- */
-void CLK_Idle(void)
-{
- CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk );
- __WFI();
-}
-
-
-/**
- * @brief This function get PCLK frequency. The frequency unit is Hz.
- * @return PCLK frequency
- */
-uint32_t CLK_GetPCLKFreq(void)
-{
- SystemCoreClockUpdate();
- if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLKSEL_Msk)
- return SystemCoreClock/2;
- else
- return SystemCoreClock;
-}
-
-/**
- * @brief Get external high speed crystal clock frequency
- * @return External high frequency crystal frequency
- * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetHXTFreq(void)
-{
- if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk )
- return __HXT;
- else
- return 0;
-}
-
-/**
- * @brief Get external low speed crystal clock frequency
- * @return External low speed crystal clock frequency
- * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetLXTFreq(void)
-{
- if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk )
- return __LXT;
- else
- return 0;
-}
-
-
-/**
- * @brief Get HCLK frequency
- * @return HCLK frequency
- * @details This function get HCLK frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetHCLKFreq(void)
-{
- SystemCoreClockUpdate();
- return SystemCoreClock;
-}
-
-/**
- * @brief Get CPU frequency
- * @return CPU frequency
- * @details This function get CPU frequency. The frequency unit is Hz.
- */
-uint32_t CLK_GetCPUFreq(void)
-{
- SystemCoreClockUpdate();
- return SystemCoreClock;
-}
-
-/**
- * @brief This function get PLL frequency. The frequency unit is Hz.
- * @return PLL frequency
- */
-uint32_t CLK_GetPLLClockFreq(void)
-{
- uint32_t u32Freq =0, u32PLLSrc;
- uint32_t u32NO,u32NF,u32NR,u32PllReg;
-
- u32PllReg = CLK->PLLCTL;
-
- if((u32PllReg & CLK_PLLCTL_PLLREMAP_Msk))
- return 0;
-
- if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
- u32PLLSrc = __HIRC;
- else
- u32PLLSrc = __HXT;
-
- u32NO=(u32PllReg & CLK_PLLCTL_OUTDV_Msk)>>CLK_PLLCTL_OUTDV_Pos;
- switch(u32NO) {
- case 0:
- u32NO=1;
- break;
- case 1:
- case 2:
- u32NO=2;
- break;
- case 3:
- u32NO=4;
- break;
- }
-
- u32NF = (u32PllReg & CLK_PLLCTL_FBDIV_Msk) + 2;
- u32NR = ( (u32PllReg & CLK_PLLCTL_INDIV_Msk)>>CLK_PLLCTL_INDIV_Pos ) + 2;
-
- u32Freq = u32PLLSrc * u32NF / u32NR / u32NO ;
-
- return u32Freq;
-}
-
-/**
- * @brief Set HCLK frequency
- * @param[in] u32Hclk is HCLK frequency
- * @return HCLK frequency
- * @details This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 24 MHz ~ 96 MHz.
- */
-uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
-{
- uint32_t u32ClkSrc,u32NR, u32NF,u32Register;
- u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
-
- if(u32Hclk < FREQ_24MHZ)
- u32Hclk =FREQ_24MHZ;
-
- if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) {
- u32Register = 0<<CLK_PLLCTL_PLLSRC_Pos;
- u32ClkSrc = __HXT;
- } else {
- u32Register = 1<<CLK_PLLCTL_PLLSRC_Pos;
- u32ClkSrc = __HIRC;
- }
-
- if(u32Hclk<FREQ_50MHZ) {
- u32Hclk <<=2;
- u32Register |= (0x3<<CLK_PLLCTL_OUTDV_Pos);
- } else {
- u32Hclk <<=1;
- u32Register |= (0x1<<CLK_PLLCTL_OUTDV_Pos);
- }
- u32NF = u32Hclk / 1000000;
- u32NR = u32ClkSrc / 1000000;
- while( u32NR>(0xF+2) || u32NF>(0xFF+2) ) {
- u32NR = u32NR>>1;
- u32NF = u32NF>>1;
- }
- CLK->PLLCTL = u32Register | ((u32NR - 2)<<9) | (u32NF - 2) ;
- CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
-
- CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1));
-
- /* Update System Core Clock */
- SystemCoreClockUpdate();
-
- return SystemCoreClock;
-}
-
-/**
- * @brief This function set HCLK clock source and HCLK clock divider
- * @param[in] u32ClkSrc is HCLK clock source. Including :
- * - \ref CLK_CLKSEL0_HCLKSEL_HXT
- * - \ref CLK_CLKSEL0_HCLKSEL_LXT
- * - \ref CLK_CLKSEL0_HCLKSEL_PLL
- * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
- * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
- * @param[in] u32ClkDiv is HCLK clock divider. Including :
- * - \ref CLK_CLKDIV0_HCLK(x)
- * @return None
- */
-void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
-{
- CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | u32ClkDiv;
- CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc;
- SystemCoreClockUpdate();
-}
-
-/**
- * @brief This function set selected module clock source and module clock divider
- * @param[in] u32ModuleIdx is module index.
- * @param[in] u32ClkSrc is module clock source.
- * @param[in] u32ClkDiv is module clock divider.
- * @return None
- * @details Valid parameter combinations listed in following table:
- *
- * |Module index |Clock source |Divider |
- * | :------------------- | :------------------------------- | :------------------------- |
- * |\ref PDMA_MODULE | x | x |
- * |\ref ISP_MODULE | x | x |
- * |\ref EBI_MODULE | x | x |
- * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
- * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBHSEL_PLL2 |\ref CLK_CLKDIV0_USB(x) |
- * |\ref EMAC_MODULE |\ref CLK_CLKSEL0_EMACSEL_PLL |\ref CLK_CLKDIV3_EMAC(x) |
- * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HXT |\ref CLK_CLKDIV0_SDH(x) |
- * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_PLL |\ref CLK_CLKDIV0_SDH(x) |
- * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HCLK |\ref CLK_CLKDIV0_SDH(x) |
- * |\ref SDH_MODULE |\ref CLK_CLKSEL0_SDHSEL_HIRC |\ref CLK_CLKDIV0_SDH(x) |
- * |\ref CRC_MODULE | x | x |
- * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HXT |\ref CLK_CLKDIV3_CAP(x) |
- * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_PLL2 |\ref CLK_CLKDIV3_CAP(x) |
- * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HCLK |\ref CLK_CLKDIV3_CAP(x) |
- * |\ref CAP_MODULE |\ref CLK_CLKSEL0_CAPSEL_HIRC |\ref CLK_CLKDIV3_CAP(x) |
- * |\ref SENCLK_MODULE | x | x |
- * |\ref USBD_MODULE | x | x |
- * |\ref CRPT_MODULE | x | x |
- * |\ref ECAP1_MODULE | x | x |
- * |\ref ECAP0_MODULE | x | x |
- * |\ref EADC_MODULE | x | x |
- * |\ref OPA_MODULE | x | x |
- * |\ref TAMPER_MODULE | x | x |
- * |\ref TAMPER_MODULE | x | x |
- * |\ref QEI1_MODULE | x | x |
- * |\ref QEI0_MODULE | x | x |
- * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HXT | x |
- * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LXT | x |
- * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_PCLK | x |
- * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_LIRC | x |
- * |\ref PWM1CH45_MODULE |\ref CLK_CLKSEL2_PWM1CH45SEL_HIRC | x |
- * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HXT | x |
- * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LXT | x |
- * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_PCLK | x |
- * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_LIRC | x |
- * |\ref PWM1CH23_MODULE |\ref CLK_CLKSEL2_PWM1CH23SEL_HIRC | x |
- * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HXT | x |
- * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LXT | x |
- * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_PCLK | x |
- * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_LIRC | x |
- * |\ref PWM1CH01_MODULE |\ref CLK_CLKSEL2_PWM1CH01SEL_HIRC | x |
- * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HXT | x |
- * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LXT | x |
- * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_PCLK | x |
- * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_LIRC | x |
- * |\ref PWM0CH45_MODULE |\ref CLK_CLKSEL2_PWM0CH45SEL_HIRC | x |
- * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HXT | x |
- * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LXT | x |
- * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_PCLK | x |
- * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_LIRC | x |
- * |\ref PWM0CH23_MODULE |\ref CLK_CLKSEL2_PWM0CH23SEL_HIRC | x |
- * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HXT | x |
- * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LXT | x |
- * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_PCLK | x |
- * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_LIRC | x |
- * |\ref PWM0CH01_MODULE |\ref CLK_CLKSEL2_PWM0CH01SEL_HIRC | x |
- * |\ref I2C4_MODULE | x | x |
- * |\ref SC5_MODULE | x | x |
- * |\ref SC4_MODULE | x | x |
- * |\ref SC3_MODULE | x | x |
- * |\ref SC2_MODULE | x | x |
- * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HXT |\ref CLK_CLKDIV2_SC5(x) |
- * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PLL |\ref CLK_CLKDIV2_SC5(x) |
- * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_PCLK |\ref CLK_CLKDIV2_SC5(x) |
- * |\ref SC5_MODULE |\ref CLK_CLKSEL3_SC5SEL_HIRC |\ref CLK_CLKDIV2_SC5(x) |
- * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HXT |\ref CLK_CLKDIV2_SC4(x) |
- * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PLL |\ref CLK_CLKDIV2_SC4(x) |
- * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_PCLK |\ref CLK_CLKDIV2_SC4(x) |
- * |\ref SC4_MODULE |\ref CLK_CLKSEL3_SC4SEL_HIRC |\ref CLK_CLKDIV2_SC4(x) |
- * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HXT |\ref CLK_CLKDIV1_SC3(x) |
- * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PLL |\ref CLK_CLKDIV1_SC3(x) |
- * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_PCLK |\ref CLK_CLKDIV1_SC3(x) |
- * |\ref SC3_MODULE |\ref CLK_CLKSEL3_SC3SEL_HIRC |\ref CLK_CLKDIV1_SC3(x) |
- * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
- * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |
- * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK |\ref CLK_CLKDIV1_SC2(x) |
- * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
- * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |
- * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) |
- * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK |\ref CLK_CLKDIV1_SC1(x) |
- * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
- * |\ref PS2_MODULE | x | x |
- * |\ref I2S1_MODULE | x | x |
- * |\ref I2S0_MODULE | x | x |
- * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HXT |\ref CLK_CLKDIV0_ADC(x) |
- * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV0_ADC(x) |
- * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PCLK |\ref CLK_CLKDIV0_ADC(x) |
- * |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV0_ADC(x) |
- * |\ref OTG_MODULE | x | x |
- * |\ref CAN1_MODULE | x | x |
- * |\ref CAN0_MODULE | x | x |
- * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART5_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART4_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
- * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
- * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PLL | x |
- * |\ref SPI3_MODULE |\ref CLK_CLKSEL1_SPI3SEL_PCLK | x |
- * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PLL | x |
- * |\ref SPI2_MODULE |\ref CLK_CLKSEL1_SPI2SEL_PCLK | x |
- * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PLL | x |
- * |\ref SPI1_MODULE |\ref CLK_CLKSEL1_SPI1SEL_PCLK | x |
- * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PLL | x |
- * |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPI0SEL_PCLK | x |
- * |\ref I2C3_MODULE | x | x |
- * |\ref I2C2_MODULE | x | x |
- * |\ref I2C1_MODULE | x | x |
- * |\ref I2C0_MODULE | x | x |
- * |\ref ACMP_MODULE | x | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
- * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x |
- * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x |
- * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x |
- * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x |
- * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
- * |\ref RTC_MODULE | x | x |
- * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
- * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
- * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
- * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
- * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
- *
- */
-
-void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
-{
- uint32_t u32tmp=0,u32sel=0,u32div=0;
-
- if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
- u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4);
- u32tmp = *(volatile uint32_t *)(u32div);
- u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
- *(volatile uint32_t *)(u32div) = u32tmp;
- }
-
- if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
- u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
- u32tmp = *(volatile uint32_t *)(u32sel);
- u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
- *(volatile uint32_t *)(u32sel) = u32tmp;
- }
-}
-
-/**
- * @brief This function enable clock source
- * @param u32ClkMask is clock source mask. Including:
- * - \ref CLK_PWRCTL_HXTEN_Msk
- * - \ref CLK_PWRCTL_LXTEN_Msk
- * - \ref CLK_PWRCTL_HIRCEN_Msk
- * - \ref CLK_PWRCTL_LIRCEN_Msk
- * @return None
- */
-void CLK_EnableXtalRC(uint32_t u32ClkMask)
-{
- CLK->PWRCTL |= u32ClkMask;
-}
-
-/**
- * @brief This function disable clock source
- * @param u32ClkMask is clock source mask. Including:
- * - \ref CLK_PWRCTL_HXTEN_Msk
- * - \ref CLK_PWRCTL_LXTEN_Msk
- * - \ref CLK_PWRCTL_HIRCEN_Msk
- * - \ref CLK_PWRCTL_LIRCEN_Msk
- * @return None
- */
-void CLK_DisableXtalRC(uint32_t u32ClkMask)
-{
- CLK->PWRCTL &= ~u32ClkMask;
-}
-
-/**
- * @brief This function enable module clock
- * @param[in] u32ModuleIdx is module index. Including :
- * - \ref PDMA_MODULE
- * - \ref ISP_MODULE
- * - \ref EBI_MODULE
- * - \ref USBH_MODULE
- * - \ref EMAC_MODULE
- * - \ref SDH_MODULE
- * - \ref CRC_MODULE
- * - \ref CAP_MODULE
- * - \ref SENCLK_MODULE
- * - \ref USBD_MODULE
- * - \ref CRPT_MODULE
- * - \ref WDT_MODULE
- * - \ref WWDT_MODULE
- * - \ref RTC_MODULE
- * - \ref TMR0_MODULE
- * - \ref TMR1_MODULE
- * - \ref TMR2_MODULE
- * - \ref TMR3_MODULE
- * - \ref CLKO_MODULE
- * - \ref ACMP_MODULE
- * - \ref I2C0_MODULE
- * - \ref I2C1_MODULE
- * - \ref I2C2_MODULE
- * - \ref I2C3_MODULE
- * - \ref SPI0_MODULE
- * - \ref SPI1_MODULE
- * - \ref SPI2_MODULE
- * - \ref SPI3_MODULE
- * - \ref UART0_MODULE
- * - \ref UART1_MODULE
- * - \ref UART2_MODULE
- * - \ref UART3_MODULE
- * - \ref UART4_MODULE
- * - \ref UART5_MODULE
- * - \ref CAN0_MODULE
- * - \ref CAN1_MODULE
- * - \ref OTG_MODULE
- * - \ref ADC_MODULE
- * - \ref I2S0_MODULE
- * - \ref I2S1_MODULE
- * - \ref PS2_MODULE
- * - \ref SC0_MODULE
- * - \ref SC1_MODULE
- * - \ref SC2_MODULE
- * - \ref SC3_MODULE
- * - \ref SC4_MODULE
- * - \ref SC5_MODULE
- * - \ref I2C4_MODULE
- * - \ref PWM0CH01_MODULE
- * - \ref PWM0CH23_MODULE
- * - \ref PWM0CH45_MODULE
- * - \ref PWM1CH01_MODULE
- * - \ref PWM1CH23_MODULE
- * - \ref PWM1CH45_MODULE
- * - \ref QEI0_MODULE
- * - \ref QEI1_MODULE
- * - \ref TAMPER_MODULE
- * - \ref ECAP0_MODULE
- * - \ref ECAP1_MODULE
- * - \ref EPWM0_MODULE
- * - \ref EPWM1_MODULE
- * - \ref OPA_MODULE
- * - \ref EADC_MODULE
- * @return None
- */
-void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
-{
- *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_AHPBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
-}
-
-/**
- * @brief This function disable module clock
- * @param[in] u32ModuleIdx is module index. Including :
- * - \ref PDMA_MODULE
- * - \ref ISP_MODULE
- * - \ref EBI_MODULE
- * - \ref USBH_MODULE
- * - \ref EMAC_MODULE
- * - \ref SDH_MODULE
- * - \ref CRC_MODULE
- * - \ref CAP_MODULE
- * - \ref SENCLK_MODULE
- * - \ref USBD_MODULE
- * - \ref CRPT_MODULE
- * - \ref WDT_MODULE
- * - \ref WWDT_MODULE
- * - \ref RTC_MODULE
- * - \ref TMR0_MODULE
- * - \ref TMR1_MODULE
- * - \ref TMR2_MODULE
- * - \ref TMR3_MODULE
- * - \ref CLKO_MODULE
- * - \ref ACMP_MODULE
- * - \ref I2C0_MODULE
- * - \ref I2C1_MODULE
- * - \ref I2C2_MODULE
- * - \ref I2C3_MODULE
- * - \ref SPI0_MODULE
- * - \ref SPI1_MODULE
- * - \ref SPI2_MODULE
- * - \ref SPI3_MODULE
- * - \ref UART0_MODULE
- * - \ref UART1_MODULE
- * - \ref UART2_MODULE
- * - \ref UART3_MODULE
- * - \ref UART4_MODULE
- * - \ref UART5_MODULE
- * - \ref CAN0_MODULE
- * - \ref CAN1_MODULE
- * - \ref OTG_MODULE
- * - \ref ADC_MODULE
- * - \ref I2S0_MODULE
- * - \ref I2S1_MODULE
- * - \ref PS2_MODULE
- * - \ref SC0_MODULE
- * - \ref SC1_MODULE
- * - \ref SC2_MODULE
- * - \ref SC3_MODULE
- * - \ref SC4_MODULE
- * - \ref SC5_MODULE
- * - \ref I2C4_MODULE
- * - \ref PWM0CH01_MODULE
- * - \ref PWM0CH23_MODULE
- * - \ref PWM0CH45_MODULE
- * - \ref PWM1CH01_MODULE
- * - \ref PWM1CH23_MODULE
- * - \ref PWM1CH45_MODULE
- * - \ref QEI0_MODULE
- * - \ref QEI1_MODULE
- * - \ref TAMPER_MODULE
- * - \ref ECAP0_MODULE
- * - \ref ECAP1_MODULE
- * - \ref EPWM0_MODULE
- * - \ref EPWM1_MODULE
- * - \ref OPA_MODULE
- * - \ref EADC_MODULE
- * @return None
- */
-void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
-{
- *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_AHPBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
-}
-
-/**
- * @brief This function set PLL frequency
- * @param[in] u32PllClkSrc is PLL clock source. Including :
- * - \ref CLK_PLLCTL_PLLSRC_HIRC
- * - \ref CLK_PLLCTL_PLLSRC_HXT
- * @param[in] u32PllFreq is PLL frequency
- * @return None
- */
-uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
-{
- uint32_t u32Register,u32ClkSrc,u32NF,u32NR;
-
- if(u32PllClkSrc==CLK_PLLCTL_PLLSRC_HIRC) {
- CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PD_Msk) | (CLK_PLLCTL_PLLSRC_HIRC);
- u32Register = 1<<CLK_PLLCTL_PLLSRC_Pos;
- u32ClkSrc = __HIRC;
- } else {
- CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PD_Msk);
- u32Register = 0<<CLK_PLLCTL_PLLSRC_Pos;
- u32ClkSrc = __HXT;
- }
-
- if(u32PllFreq<FREQ_50MHZ) {
- u32PllFreq <<=2;
- u32Register |= (0x3<<CLK_PLLCTL_OUTDV_Pos);
- } else {
- u32PllFreq <<=1;
- u32Register |= (0x1<<CLK_PLLCTL_OUTDV_Pos);
- }
- u32NF = u32PllFreq / 1000000;
- u32NR = u32ClkSrc / 1000000;
- while( u32NR>(0xF+2) || u32NF>(0xFF+2) ) {
- u32NR = u32NR>>1;
- u32NF = u32NF>>1;
- }
- CLK->PLLCTL = u32Register | ((u32NR - 2)<<9) | (u32NF - 2) ;
- CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
-
- return CLK_GetPLLClockFreq();
-}
-
-/**
- * @brief This function disable PLL
- * @return None
- */
-void CLK_DisablePLL(void)
-{
- CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
-}
-
-/**
- * @brief This function set SysTick clock source
- * @param[in] u32ClkSrc is SysTick clock source. Including :
- * - \ref CLK_CLKSEL0_STCLKSEL_HXT
- * - \ref CLK_CLKSEL0_STCLKSEL_LXT
- * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
- * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
- * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
- * @return None
- */
-void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
-{
- CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc ;
-}
-/**
- * @brief This function execute delay function.
- * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
- * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
- * @return None
- * @details Use the SysTick to generate the delay time and the UNIT is in us.
- * The SysTick clock source is from HCLK, i.e the same as system core clock.
- */
-void CLK_SysTickDelay(uint32_t us)
-{
- SysTick->LOAD = us * CyclesPerUs;
- SysTick->VAL = (0x00);
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
-
- /* Waiting for down-count to zero */
- while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
-}
-
-/**
- * @brief This function check selected clock source status
- * @param[in] u32ClkMask is selected clock source. Including
- * - \ref CLK_STATUS_CLKSFAIL_Msk
- * - \ref CLK_STATUS_HIRCSTB_Msk
- * - \ref CLK_STATUS_LIRCSTB_Msk
- * - \ref CLK_STATUS_PLLSTB_Msk
- * - \ref CLK_STATUS_LXTSTB_Msk
- * - \ref CLK_STATUS_HXTSTB_Msk
- *
- * @return 0 clock is not stable
- * 1 clock is stable
- *
- * @details To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)
- */
-uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
-{
- int32_t i32TimeOutCnt;
-
- i32TimeOutCnt = __HSI / 200; /* About 5ms */
-
- while((CLK->STATUS & u32ClkMask) != u32ClkMask) {
- if(i32TimeOutCnt-- <= 0)
- return 0;
- }
- return 1;
-}
-
-
-/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_CLK_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_clk.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,411 +0,0 @@
-/**************************************************************************//**
- * @file CLK.h
- * @version V1.0
- * $Revision 1 $
- * $Date: 14/10/06 1:50p $
- * @brief NUC472/NUC442 CLK Header File
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- ******************************************************************************/
-#ifndef __CLK_H__
-#define __CLK_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CLK_Driver CLK Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_CLK_EXPORTED_CONSTANTS CLK Exported Constants
-@{
-*/
-
-#define FREQ_50MHZ 50000000
-#define FREQ_24MHZ 24000000
-#define FREQ_22MHZ 22000000
-#define FREQ_32KHZ 32767
-#define FREQ_10KHZ 10000
-/*---------------------------------------------------------------------------------------------------------*/
-/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_PLLCTL_PLLSRC_HIRC (0x1UL<<CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is internal RC clock. 4MHz < FIN < 24MHz \hideinitializer */
-#define CLK_PLLCTL_PLLSRC_HXT (0x0UL<<CLK_PLLCTL_PLLSRC_Pos) /*!< For PLL clock source is external crystal. 4MHz < FIN < 24MHz \hideinitializer */
-
-#define CLK_PLLCTL_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 15MHz \hideinitializer */
-#define CLK_PLLCTL_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 100MHz < FIN*NF/NR < 200MHz. (120MHz < FIN*NF/NR < 200MHz is preferred.) \hideinitializer */
-
-#define CLK_PLLCTL_NO_1 (0x0UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 1 \hideinitializer */
-#define CLK_PLLCTL_NO_2 (0x1UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 2 \hideinitializer */
-#define CLK_PLLCTL_NO_4 (0x3UL<<CLK_PLLCTL_OUTDV_Pos) /*!< For output divider is 4 \hideinitializer */
-
-#if (__HXT == 12000000)
-#define CLK_PLLCTL_FOR_I2S (0xA54) /*!< Predefined PLLCTL setting for 147428571.428571Hz PLL output with 12MHz XTAL \hideinitializer */
-#define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 28) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 84MHz PLL output with 12MHz XTAL \hideinitializer */
-#define CLK_PLLCTL_50MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 25) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50MHz PLL output with 12MHz XTAL \hideinitializer */
-#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF(112) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with 12MHz XTAL \hideinitializer */
-#define CLK_PLLCTL_36MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(7) | CLK_PLLCTL_NF( 84) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 36MHz PLL output with 12MHz XTAL \hideinitializer */
-#define CLK_PLLCTL_32MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(6) | CLK_PLLCTL_NF( 64) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 32MHz PLL output with 12MHz XTAL \hideinitializer */
-#define CLK_PLLCTL_24MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 16) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 24MHz PLL output with 12MHz XTAL \hideinitializer */
-#else
-# error "The PLL pre-definitions are only valid when external crystal is 12MHz"
-#endif
-
-#define CLK_PLLCTL_50MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF( 59) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 50.1918MHz PLL output with 22.1184MHz IRC \hideinitializer */
-#define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13) | CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48.064985MHz PLL output with 22.1184MHz IRC \hideinitializer */
-#define CLK_PLLCTL_36MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(12) | CLK_PLLCTL_NF( 78) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 35.9424MHz PLL output with 22.1184MHz IRC \hideinitializer */
-#define CLK_PLLCTL_32MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 9) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 31.9488MHz PLL output with 22.1184MHz IRC \hideinitializer */
-#define CLK_PLLCTL_24MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR( 3) | CLK_PLLCTL_NF( 13) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 23.9616MHz PLL output with 22.1184MHz IRC \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* PLL2CTL constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_PLL2CTL_USPLL(x) (((x)-1) << CLK_PLL2CTL_PLL2DIV_Pos) /*!< USBPLL clock frequency = (480 MHz) / 2 / (USB_N + 1). It could be 1~256, Max. PLL frequency :480MHz / 2 when XTL12M. \hideinitializer */
-#define CLK_PLL2CTL_USBPLL_DIS (0x00UL<<CLK_PLL2CTL_PLL2CKEN_Pos) /*!< USB PHY PLL (480MHz) Disable \hideinitializer */
-#define CLK_PLL2CTL_PLL2CKEN (0x01UL<<CLK_PLL2CTL_PLL2CKEN_Pos) /*!< USB PHY PLL (480MHz) Enable \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL0 constant definitions. (Write-protection) */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as PLL output \hideinitializer */
-#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 10KHz RC clock \hideinitializer */
-#define CLK_CLKSEL0_HCLKSEL_USBPLL (0x04UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as USBPLL clock \hideinitializer */
-#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as external XTAL/2 \hideinitializer */
-#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */
-#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock/2 \hideinitializer */
-
-#define CLK_CLKSEL0_PCLKSEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
-#define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLKSEL_Pos) /*!< Setting clock source as HCLK/2 \hideinitializer */
-
-#define CLK_CLKSEL0_USBHSEL_PLL2 (0x00UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
-#define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting clock source as PLL \hideinitializer */
-
-#define CLK_CLKSEL0_EMACSEL_PLL (0x01UL<<10) /*!< Setting clock source as PLL \hideinitializer */
-
-#define CLK_CLKSEL0_CAPSEL_HXT (0x00UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL0_CAPSEL_PLL2 (0x01UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
-#define CLK_CLKSEL0_CAPSEL_HCLK (0x02UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
-#define CLK_CLKSEL0_CAPSEL_HIRC (0x03UL<<CLK_CLKSEL0_CAPSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL0_SDHSEL_HXT (0x00UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL0_SDHSEL_PLL (0x01UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as PLL2 \hideinitializer */
-#define CLK_CLKSEL0_SDHSEL_HCLK (0x02UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as HCLK \hideinitializer */
-#define CLK_CLKSEL0_SDHSEL_HIRC (0x03UL<<CLK_CLKSEL0_SDHSEL_Pos) /*!< Setting clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL1 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 \hideinitializer */
-#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as internal 10KHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_ADCSEL_HXT (0x0UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL1_ADCSEL_PLL (0x1UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as PLL \hideinitializer */
-#define CLK_CLKSEL1_ADCSEL_PCLK (0x2UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL1_ADCSEL_HIRC (0x3UL<<CLK_CLKSEL1_ADCSEL_Pos) /*!< Setting ADC clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_SPI0SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL1_SPI0SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK \hideinitializer */
-
-#define CLK_CLKSEL1_SPI1SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL1_SPI1SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK \hideinitializer */
-
-#define CLK_CLKSEL1_SPI2SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL1_SPI2SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK \hideinitializer */
-
-#define CLK_CLKSEL1_SPI3SEL_PLL (0x0UL<<CLK_CLKSEL1_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL1_SPI3SEL_PCLK (0x1UL<<CLK_CLKSEL1_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK \hideinitializer */
-
-#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL1_TMR0SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger \hideinitializer */
-#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 10KHz RC clock \hideinitializer */
-#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL1_TMR1SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger \hideinitializer */
-#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal 10KHz RC clock \hideinitializer */
-#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL1_TMR2SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger \hideinitializer */
-#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal 10KHz RC clock \hideinitializer */
-#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL1_TMR3SEL_PCLK (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger \hideinitializer */
-#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal 10KHz RC clock \hideinitializer */
-#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_UARTSEL_HXT (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL1_UARTSEL_PLL (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external PLL \hideinitializer */
-#define CLK_CLKSEL1_UARTSEL_HIRC (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos) /*!< Setting UR clock source as external internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK \hideinitializer */
-#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as external internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting CLKO clock source as HCLK/2048 \hideinitializer */
-#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting CLKO clock source as internal 10KHz RC clock \hideinitializer */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL2 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL2_PWM0CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL2_PWM0CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL2_PWM0CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock \hideinitializer */
-#define CLK_CLKSEL2_PWM0CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL2_PWM1CH01SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH01SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH01SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH01SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 22.1184MHz RC clock \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH01SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< Setting PWM0 and PWM1 clock source as internal 10KHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL2_PWM1CH23SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH23SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH23SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH23SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 22.1184MHz RC clock \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH23SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< Setting PWM2 and PWM3 clock source as internal 10KHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL2_PWM1CH45SEL_HXT (0x0UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH45SEL_LXT (0x1UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as external XTAL 32.768KHz \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH45SEL_PCLK (0x2UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH45SEL_HIRC (0x3UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 22.1184MHz RC clock \hideinitializer */
-#define CLK_CLKSEL2_PWM1CH45SEL_LIRC (0x7UL<<CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< Setting PWM4 and PWM5 clock source as internal 10KHz RC clock \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKSEL3 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_SC0SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_SC1SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_SC2SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL3_SC3SEL_HXT (0x0UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_SC3SEL_PLL (0x1UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_SC3SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_SC3SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC3SEL_Pos) /*!< Setting SC3 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL3_SC4SEL_HXT (0x0UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_SC4SEL_PLL (0x1UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_SC4SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_SC4SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC4SEL_Pos) /*!< Setting SC4 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL3_SC5SEL_HXT (0x0UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_SC5SEL_PLL (0x1UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_SC5SEL_PCLK (0x2UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_SC5SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC5SEL_Pos) /*!< Setting SC5 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_I2S0SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-#define CLK_CLKSEL3_I2S1SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as external XTAL \hideinitializer */
-#define CLK_CLKSEL3_I2S1SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as PLL \hideinitializer */
-#define CLK_CLKSEL3_I2S1SEL_PCLK (0x2UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as PCLK \hideinitializer */
-#define CLK_CLKSEL3_I2S1SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S1SEL_Pos) /*!< Setting I2S1 clock source as internal 22.1184MHz RC clock \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKDIV0 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
-#define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBHDIV_Pos) /*!< CLKDIV Setting for USB clock divider. It could be 1~16 \hideinitializer */
-#define CLK_CLKDIV0_UART(x) (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLKDIV Setting for UR clock divider. It could be 1~16 \hideinitializer */
-#define CLK_CLKDIV0_ADC(x) (((x)-1) << CLK_CLKDIV0_ADCDIV_Pos) /*!< CLKDIV Setting for ADC clock divider. It could be 1~256 \hideinitializer */
-#define CLK_CLKDIV0_SDH(x) (((x)-1) << CLK_CLKDIV0_SDHDIV_Pos) /*!< CLKDIV Setting for SDIO clock divider. It could be 1~256 \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKDIV1 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
-#define CLK_CLKDIV1_SC1(x) (((x)-1) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
-#define CLK_CLKDIV1_SC2(x) (((x)-1) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
-#define CLK_CLKDIV1_SC3(x) (((x)-1) << CLK_CLKDIV1_SC3DIV_Pos) /*!< CLKDIV Setting for SC3 clock divider. It could be 1~256 \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKDIV2 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKDIV2_SC4(x) (((x)-1) << CLK_CLKDIV2_SC4DIV_Pos) /*!< CLKDIV Setting for SC4 clock divider. It could be 1~256 \hideinitializer */
-#define CLK_CLKDIV2_SC5(x) (((x)-1) << CLK_CLKDIV2_SC5DIV_Pos) /*!< CLKDIV Setting for SC5 clock divider. It could be 1~256 \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* CLKDIV3 constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define CLK_CLKDIV3_CAP(x) (((x)-1) << CLK_CLKDIV3_ICAPDIV_Pos) /*!< CLKDIV Setting for CAP Engine clock divider. It could be 1~256 \hideinitializer */
-#define CLK_CLKDIV3_VASENSOR(x) (((x)-1) << CLK_CLKDIV3_VASENSORDIV_Pos) /*!< CLKDIV Setting for Video Pixel clock divider. It could be 1~256 \hideinitializer */
-#define CLK_CLKDIV3_EMAC(x) (((x)-1) << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLKDIV Setting for EMAC_MDCLK clock divider. It could be 1~256 \hideinitializer */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* MODULE constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define MODULE_AHPBCLK(x) ((x >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index \hideinitializer */
-#define MODULE_CLKSEL(x) ((x >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index \hideinitializer */
-#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
-#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
-#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index \hideinitializer */
-#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
-#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
-#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
-#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index \hideinitializer */
-/*--------------------------------------------------------------------------------------------------------------------------------------*/
-/* AHBCLK/APBCLK(2) | CLKSEL(2) | CLKSEL_Msk(3) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
-/*--------------------------------------------------------------------------------------------------------------------------------------*/
-#define PDMA_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_PDMACKEN_Pos) /*!< PDMA Module \hideinitializer */
-#define ISP_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_ISPCKEN_Pos) /*!< ISP Module \hideinitializer */
-#define EBI_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_EBICKEN_Pos) /*!< EBI Module \hideinitializer */
-#define USBH_MODULE ((0UL<<30)|(0<<28)|(1<<25) |( 8<<20)|(0<<18)|(0xF<<10) |( 4<<5)|CLK_AHBCLK_USBHCKEN_Pos) /*!< USBH Module \hideinitializer */
-#define EMAC_MODULE ((0UL<<30)|(0<<28)|(1<<25) |(10<<20)|(3<<18)|(0xFF<<10) |(16<<5)|CLK_AHBCLK_EMACCKEN_Pos) /*!< EMAC Module \hideinitializer */
-#define SDH_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(20<<20)|(0<<18)|(0xFF<<10) |(24<<5)|CLK_AHBCLK_SDHCKEN_Pos) /*!< SDH Module \hideinitializer */
-#define CRC_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRCCKEN_Pos) /*!< CRC Module \hideinitializer */
-#define CAP_MODULE ((0UL<<30)|(0<<28)|(3<<25) |(16<<20)|(3<<18)|(0xFF<<10) |( 0<<5)|CLK_AHBCLK_ICAPCKEN_Pos) /*!< CAP Module \hideinitializer */
-#define SENCLK_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(3<<18)|(0xFF<<10) |( 8<<5)|CLK_AHBCLK_SENCLKCKEN_Pos) /*!< Sensor Clock Module \hideinitializer */
-#define USBD_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_USBDCKEN_Pos) /*!< USBD Module \hideinitializer */
-#define CRPT_MODULE ((0UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_AHBCLK_CRPTCKEN_Pos) /*!< CRYPTO Module \hideinitializer */
-
-#define WDT_MODULE ((1UL<<30)|(3<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Watchdog Timer Module \hideinitializer */
-#define WWDT_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(30<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_WDTCKEN_Pos) /*!< Window Watchdog Timer Module \hideinitializer */
-#define RTC_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_RTCCKEN_Pos) /*!< RTC Module \hideinitializer */
-#define TMR0_MODULE ((1UL<<30)|(1<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR0CKEN_Pos) /*!< Timer0 Module \hideinitializer */
-#define TMR1_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR1CKEN_Pos) /*!< Timer1 Module \hideinitializer */
-#define TMR2_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR2CKEN_Pos) /*!< Timer2 Module \hideinitializer */
-#define TMR3_MODULE ((1UL<<30)|(1<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_TMR3CKEN_Pos) /*!< Timer3 Module \hideinitializer */
-#define CLKO_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(28<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLKO Module \hideinitializer */
-#define ACMP_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_ACMPCKEN_Pos) /*!< ACMP Module \hideinitializer */
-#define I2C0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C0CKEN_Pos) /*!< I2C0 Module \hideinitializer */
-#define I2C1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C1CKEN_Pos) /*!< I2C1 Module \hideinitializer */
-#define I2C2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C2CKEN_Pos) /*!< I2C2 Module \hideinitializer */
-#define I2C3_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2C3CKEN_Pos) /*!< I2C3 Module \hideinitializer */
-#define SPI0_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI0CKEN_Pos) /*!< SPI0 Module \hideinitializer */
-#define SPI1_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 5<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI1CKEN_Pos) /*!< SPI1 Module \hideinitializer */
-#define SPI2_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 6<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI2CKEN_Pos) /*!< SPI2 Module \hideinitializer */
-#define SPI3_MODULE ((1UL<<30)|(1<<28)|(1<<25) |( 7<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_SPI3CKEN_Pos) /*!< SPI3 Module \hideinitializer */
-#define UART0_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART0CKEN_Pos) /*!< UART0 Module \hideinitializer */
-#define UART1_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART1CKEN_Pos) /*!< UART1 Module \hideinitializer */
-#define UART2_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART2CKEN_Pos) /*!< UART2 Module \hideinitializer */
-#define UART3_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART3CKEN_Pos) /*!< UART3 Module \hideinitializer */
-#define UART4_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART4CKEN_Pos) /*!< UART4 Module \hideinitializer */
-#define UART5_MODULE ((1UL<<30)|(1<<28)|(3<<25) |(24<<20)|(0<<18)|(0xF<<10) |( 8<<5)|CLK_APBCLK0_UART5CKEN_Pos) /*!< UART5 Module \hideinitializer */
-#define CAN0_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN0CKEN_Pos) /*!< CAN0 Module \hideinitializer */
-#define CAN1_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_CAN1CKEN_Pos) /*!< CAN1 Module \hideinitializer */
-#define OTG_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_OTGCKEN_Pos) /*!< OTG Module \hideinitializer */
-#define ADC_MODULE ((1UL<<30)|(1<<28)|(3<<25) |( 2<<20)|(0<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK0_ADCCKEN_Pos) /*!< ADC Module \hideinitializer */
-#define I2S0_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S0CKEN_Pos) /*!< I2S0 Module \hideinitializer */
-#define I2S1_MODULE ((1UL<<30)|(3<<28)|(3<<25) |(18<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_I2S1CKEN_Pos) /*!< I2S1 Module \hideinitializer */
-#define PS2_MODULE ((1UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK0_PS2CKEN_Pos) /*!< PS2 Module \hideinitializer */
-
-#define SC0_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 0<<20)|(1<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC0CKEN_Pos) /*!< SmartCard0 Module \hideinitializer */
-#define SC1_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 2<<20)|(1<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC1CKEN_Pos) /*!< SmartCard1 Module \hideinitializer */
-#define SC2_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 4<<20)|(1<<18)|(0xFF<<10) |(16<<5)|CLK_APBCLK1_SC2CKEN_Pos) /*!< SmartCard2 Module \hideinitializer */
-#define SC3_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 6<<20)|(1<<18)|(0xFF<<10) |(24<<5)|CLK_APBCLK1_SC3CKEN_Pos) /*!< SmartCard3 Module \hideinitializer */
-#define SC4_MODULE ((2UL<<30)|(3<<28)|(3<<25) |( 8<<20)|(2<<18)|(0xFF<<10) |( 0<<5)|CLK_APBCLK1_SC4CKEN_Pos) /*!< SmartCard4 Module \hideinitializer */
-#define SC5_MODULE ((2UL<<30)|(3<<28)|(3<<25) |(10<<20)|(2<<18)|(0xFF<<10) |( 8<<5)|CLK_APBCLK1_SC5CKEN_Pos) /*!< SmartCard5 Module \hideinitializer */
-#define I2C4_MODULE ((2UL<<30)|(0<<28)|(0<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos) /*!< I2C4 Module */
-#define PWM0CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH01CKEN_Pos) /*!< PWM0CH01 Module \hideinitializer */
-#define PWM0CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 4<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH23CKEN_Pos) /*!< PWM0CH23 Module \hideinitializer */
-#define PWM0CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |( 8<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM0CH45CKEN_Pos) /*!< PWM0CH45 Module \hideinitializer */
-#define PWM1CH01_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(12<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH01CKEN_Pos) /*!< PWM1CH01 Module \hideinitializer */
-#define PWM1CH23_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(16<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH23CKEN_Pos) /*!< PWM1CH23 Module \hideinitializer */
-#define PWM1CH45_MODULE ((2UL<<30)|(2<<28)|(7<<25) |(20<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_PWM1CH45CKEN_Pos) /*!< PWM1CH45 Module \hideinitializer */
-#define QEI0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI0CKEN_Pos) /*!< QEI0 Module \hideinitializer */
-#define QEI1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_QEI1CKEN_Pos) /*!< QEI1 Module \hideinitializer */
-#define TAMPER_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_TAMPERCKEN_Pos) /*!< TAMPER Module \hideinitializer */
-#define ECAP0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP0CKEN_Pos) /*!< ECAP0 Module \hideinitializer */
-#define ECAP1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_ECAP1CKEN_Pos) /*!< ECAP1 Module \hideinitializer */
-#define EPWM0_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM0CKEN_Pos) /*!< EPWM0 Module \hideinitializer */
-#define EPWM1_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EPWM1CKEN_Pos) /*!< EPWM1 Module \hideinitializer */
-#define OPA_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_OPACKEN_Pos) /*!< OPA Module \hideinitializer */
-#define EADC_MODULE ((2UL<<30)|(0<<28)|(MODULE_NoMsk<<25)|( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_EADCCKEN_Pos) /*!< EADC Module \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
- @{
-*/
-
-void CLK_DisableCKO(void);
-void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
-void CLK_PowerDown(void);
-void CLK_Idle(void);
-uint32_t CLK_GetHXTFreq(void);
-uint32_t CLK_GetLXTFreq(void);
-uint32_t CLK_GetHCLKFreq(void);
-uint32_t CLK_GetPCLKFreq(void);
-uint32_t CLK_GetCPUFreq(void);
-uint32_t CLK_GetPLLClockFreq(void);
-uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
-void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
-void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
-void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
-void CLK_EnableXtalRC(uint32_t u32ClkMask);
-void CLK_DisableXtalRC(uint32_t u32ClkMask);
-void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
-void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
-uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
-void CLK_DisablePLL(void);
-void CLK_SysTickDelay(uint32_t us);
-uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
-
-/*@}*/ /* end of group NUC472_442_CLK_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_CLK_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__CLK_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,348 +0,0 @@
-/**************************************************************************//**
- * @file crypto.c
- * @version V1.10
- * $Revision: 11 $
- * $Date: 14/10/03 1:54p $
- * @brief Cryptographic Accelerator driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include <string.h>
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CRYPTO_Driver CRYPTO Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
- @{
-*/
-
-/// @cond HIDDEN_SYMBOLS
-
-static uint32_t g_AES_CTL[4];
-static uint32_t g_TDES_CTL[4];
-
-/// @endcond HIDDEN_SYMBOLS
-
-/**
- * @brief Open PRNG function
- * @param[in] u32KeySize is PRNG key size, including:
- * - \ref PRNG_KEY_SIZE_64
- * - \ref PRNG_KEY_SIZE_128
- * - \ref PRNG_KEY_SIZE_192
- * - \ref PRNG_KEY_SIZE_256
- * @param[in] u32SeedReload is PRNG seed reload or not, including:
- * - \ref PRNG_SEED_CONT
- * - \ref PRNG_SEED_RELOAD
- * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD.
- * @return None
- */
-void PRNG_Open(uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed)
-{
- if (u32SeedReload)
- CRPT->PRNG_SEED = u32Seed;
-
- CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
- (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
-}
-
-/**
- * @brief Start to generate one PRNG key.
- * @param None
- * @return None
- */
-void PRNG_Start(void)
-{
- CRPT->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk;
-}
-
-/**
- * @brief Read the PRNG key.
- * @param[out] u32RandKey The key buffer to store newly generated PRNG key.
- * @return None
- */
-void PRNG_Read(uint32_t u32RandKey[])
-{
- int i, wcnt;
-
- wcnt = (((CRPT->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk)>>CRPT_PRNG_CTL_KEYSZ_Pos)+1)*2;
- for (i = 0; i < wcnt; i++)
- u32RandKey[i] = *(uint32_t *)((uint32_t)&(CRPT->PRNG_KEY0) + (i * 4));
-}
-
-
-/**
- * @brief Open AES encrypt/decrypt function.
- * @param[in] u32Channel AES channel. Must be 0~3.
- * @param[in] u32EncDec 1: AES encode; 0: AES decode
- * @param[in] u32OpMode AES operation mode, including:
- * - \ref AES_MODE_ECB
- * - \ref AES_MODE_CBC
- * - \ref AES_MODE_CFB
- * - \ref AES_MODE_OFB
- * - \ref AES_MODE_CTR
- * - \ref AES_MODE_CBC_CS1
- * - \ref AES_MODE_CBC_CS2
- * - \ref AES_MODE_CBC_CS3
- * @param[in] u32KeySize is AES key size, including:
- * - \ref AES_KEY_SIZE_128
- * - \ref AES_KEY_SIZE_192
- * - \ref AES_KEY_SIZE_256
- * @param[in] u32SwapType is AES input/output data swap control, including:
- * - \ref AES_NO_SWAP
- * - \ref AES_OUT_SWAP
- * - \ref AES_IN_SWAP
- * - \ref AES_IN_OUT_SWAP
- * @return None
- */
-void AES_Open(uint32_t u32Channel, uint32_t u32EncDec,
- uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType)
-{
- CRPT->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) |
- (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) |
- (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) |
- (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) |
- (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos);
- g_AES_CTL[u32Channel] = CRPT->AES_CTL;
-}
-
-/**
- * @brief Start AES encrypt/decrypt
- * @param[in] u32Channel AES channel. Must be 0~3.
- * @param[in] u32DMAMode AES DMA control, including:
- * - \ref CRYPTO_DMA_ONE_SHOT One shop AES encrypt/decrypt.
- * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt.
- * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start.
- * @return None
- */
-void AES_Start(int32_t u32Channel, uint32_t u32DMAMode)
-{
- CRPT->AES_CTL = g_AES_CTL[u32Channel];
- CRPT->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos);
-}
-
-/**
- * @brief Set AES keys
- * @param[in] u32Channel AES channel. Must be 0~3.
- * @param[in] au32Keys An word array contains AES keys.
- * @param[in] u32KeySize is AES key size, including:
- * - \ref AES_KEY_SIZE_128
- * - \ref AES_KEY_SIZE_192
- * - \ref AES_KEY_SIZE_256
- * @return None
- */
-void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)
-{
- int i, wcnt;
- uint32_t *key_ptr;
-
- key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_KEY0 + (u32Channel * 0x3C));
- wcnt = 4 + u32KeySize*2;
- for (i = 0; i < wcnt; i++, key_ptr++)
- *key_ptr = au32Keys[i];
-}
-
-/**
- * @brief Set AES initial vectors
- * @param[in] u32Channel AES channel. Must be 0~3.
- * @param[in] au32IV A four entry word array contains AES initial vectors.
- * @return None
- */
-void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[])
-{
- int i;
- uint32_t *key_ptr;
-
- key_ptr = (uint32_t *)((uint32_t)&CRPT->AES0_IV0 + (u32Channel * 0x3C));
- for (i = 0; i < 4; i++, key_ptr++)
- *key_ptr = au32IV[i];
-}
-
-/**
- * @brief Set AES DMA transfer configuration.
- * @param[in] u32Channel AES channel. Must be 0~3.
- * @param[in] u32SrcAddr AES DMA source address
- * @param[in] u32DstAddr AES DMA destination address
- * @param[in] u32TransCnt AES DMA transfer byte count
- * @return None
- */
-void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
- uint32_t u32DstAddr, uint32_t u32TransCnt)
-{
- *(uint32_t *)((uint32_t)&CRPT->AES0_SADDR + (u32Channel * 0x3C)) = u32SrcAddr;
- *(uint32_t *)((uint32_t)&CRPT->AES0_DADDR + (u32Channel * 0x3C)) = u32DstAddr;
- *(uint32_t *)((uint32_t)&CRPT->AES0_CNT + (u32Channel * 0x3C)) = u32TransCnt;
-}
-
-/**
- * @brief Open TDES encrypt/decrypt function.
- * @param[in] u32Channel TDES channel. Must be 0~3.
- * @param[in] u32EncDec 1: TDES encode; 0: TDES decode
- * @param[in] u32OpMode TDES operation mode, including:
- * - \ref TDES_MODE_ECB
- * - \ref TDES_MODE_CBC
- * - \ref TDES_MODE_CFB
- * - \ref TDES_MODE_OFB
- * - \ref TDES_MODE_CTR
- * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including:
- * - \ref TDES_NO_SWAP
- * - \ref TDES_WHL_SWAP
- * - \ref TDES_OUT_SWAP
- * - \ref TDES_OUT_WHL_SWAP
- * - \ref TDES_IN_SWAP
- * - \ref TDES_IN_WHL_SWAP
- * - \ref TDES_IN_OUT_SWAP
- * - \ref TDES_IN_OUT_WHL_SWAP
- * @return None
- */
-void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType)
-{
- g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) |
- (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) |
- u32OpMode |
- (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos);
-}
-
-/**
- * @brief Start TDES encrypt/decrypt
- * @param[in] u32Channel TDES channel. Must be 0~3.
- * @param[in] u32DMAMode TDES DMA control, including:
- * - \ref CRYPTO_DMA_ONE_SHOT One shop TDES encrypt/decrypt.
- * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt.
- * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of TDES_Start.
- * @return None
- */
-void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode)
-{
- g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos);
- CRPT->TDES_CTL = g_TDES_CTL[u32Channel];
-}
-
-/**
- * @brief Set TDES keys
- * @param[in] u32Channel TDES channel. Must be 0~3.
- * @param[in] au8Keys The TDES keys.
- * @return None
- */
-void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8])
-{
- int i;
- uint8_t *pu8TKey;
-
- pu8TKey = (uint8_t *)((uint32_t)&CRPT->TDES0_KEY1H + (0x40 * u32Channel));
- for (i = 0; i < 3; i++, pu8TKey+=8)
- memcpy(pu8TKey, &au8Keys[i][0], 8);
-}
-
-/**
- * @brief Set TDES initial vectors
- * @param[in] u32Channel TDES channel. Must be 0~3.
- * @param[in] u32IVH TDES initial vector high word.
- * @param[in] u32IVL TDES initial vector low word.
- * @return None
- */
-void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL)
-{
- *(uint32_t *)((uint32_t)&CRPT->TDES0_IVH + 0x40 * u32Channel) = u32IVH;
- *(uint32_t *)((uint32_t)&CRPT->TDES0_IVL + 0x40 * u32Channel) = u32IVL;
-}
-
-/**
- * @brief Set TDES DMA transfer configuration.
- * @param[in] u32Channel TDES channel. Must be 0~3.
- * @param[in] u32SrcAddr TDES DMA source address
- * @param[in] u32DstAddr TDES DMA destination address
- * @param[in] u32TransCnt TDES DMA transfer byte count
- * @return None
- */
-void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr,
- uint32_t u32DstAddr, uint32_t u32TransCnt)
-{
- *(uint32_t *)((uint32_t)&CRPT->TDES0_SADDR + (u32Channel * 0x40)) = u32SrcAddr;
- *(uint32_t *)((uint32_t)&CRPT->TDES0_DADDR + (u32Channel * 0x40)) = u32DstAddr;
- *(uint32_t *)((uint32_t)&CRPT->TDES0_CNT + (u32Channel * 0x40)) = u32TransCnt;
-}
-
-/**
- * @brief Open SHA encrypt function.
- * @param[in] u32OpMode SHA operation mode, including:
- * - \ref SHA_MODE_SHA1
- * - \ref SHA_MODE_SHA224
- * - \ref SHA_MODE_SHA256
- * @param[in] u32SwapType is SHA input/output data swap control, including:
- * - \ref SHA_NO_SWAP
- * - \ref SHA_OUT_SWAP
- * - \ref SHA_IN_SWAP
- * - \ref SHA_IN_OUT_SWAP
- * @return None
- */
-void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType)
-{
- CRPT->SHA_CTL = (u32OpMode << CRPT_SHA_CTL_OPMODE_Pos) |
- (u32SwapType << CRPT_SHA_CTL_OUTSWAP_Pos);
-}
-
-/**
- * @brief Start SHA encrypt
- * @param[in] u32DMAMode TDES DMA control, including:
- * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt.
- * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt.
- * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start.
- * @return None
- */
-void SHA_Start(uint32_t u32DMAMode)
-{
- CRPT->SHA_CTL &= ~(0x7 << CRPT_SHA_CTL_DMALAST_Pos);
- CRPT->SHA_CTL |= CRPT_SHA_CTL_START_Msk | (u32DMAMode << CRPT_SHA_CTL_DMALAST_Pos);
-}
-
-/**
- * @brief Set SHA DMA transfer
- * @param[in] u32SrcAddr SHA DMA source address
- * @param[in] u32TransCnt SHA DMA transfer byte count
- * @return None
- */
-void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt)
-{
- CRPT->SHA_SADDR = u32SrcAddr;
- CRPT->SHA_DMACNT = u32TransCnt;
-}
-
-/**
- * @brief Read the SHA digest.
- * @param[out] u32Digest The SHA encrypt output digest.
- * @return None
- */
-void SHA_Read(uint32_t u32Digest[])
-{
- uint32_t i, wcnt;
-
- i = (CRPT->SHA_CTL & CRPT_SHA_CTL_OPMODE_Msk) >> CRPT_SHA_CTL_OPMODE_Pos;
- if (i == SHA_MODE_SHA1)
- wcnt = 5;
- else if (i == SHA_MODE_SHA224)
- wcnt = 7;
- else
- wcnt = 8;
-
- for (i = 0; i < wcnt; i++)
- u32Digest[i] = *(uint32_t *)((uint32_t)&(CRPT->SHA_DGST0) + (i * 4));
-}
-
-
-/*@}*/ /* end of group NUC472_442_CRYPTO_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_CRYPTO_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_crypto.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,302 +0,0 @@
-/**************************************************************************//**
- * @file crypto.h
- * @version V1.10
- * $Revision: 14 $
- * $Date: 14/10/06 1:49p $
- * @brief Cryptographic Accelerator driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- ******************************************************************************/
-#ifndef __CRYPTO_H__
-#define __CRYPTO_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_CRYPTO_Driver CRYPTO Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
- @{
-*/
-
-#define PRNG_KEY_SIZE_64 0 /*!< Select to generate 64-bit random key \hideinitializer */
-#define PRNG_KEY_SIZE_128 1 /*!< Select to generate 128-bit random key \hideinitializer */
-#define PRNG_KEY_SIZE_192 2 /*!< Select to generate 192-bit random key \hideinitializer */
-#define PRNG_KEY_SIZE_256 3 /*!< Select to generate 256-bit random key \hideinitializer */
-
-#define PRNG_SEED_CONT 0 /*!< PRNG using current seed \hideinitializer */
-#define PRNG_SEED_RELOAD 1 /*!< PRNG reload new seed \hideinitializer */
-
-#define AES_KEY_SIZE_128 0 /*!< AES select 128-bit key length \hideinitializer */
-#define AES_KEY_SIZE_192 1 /*!< AES select 192-bit key length \hideinitializer */
-#define AES_KEY_SIZE_256 2 /*!< AES select 256-bit key length \hideinitializer */
-
-#define AES_MODE_ECB 0 /*!< AES select ECB mode \hideinitializer */
-#define AES_MODE_CBC 1 /*!< AES select CBC mode \hideinitializer */
-#define AES_MODE_CFB 2 /*!< AES select CFB mode \hideinitializer */
-#define AES_MODE_OFB 3 /*!< AES select OFB mode \hideinitializer */
-#define AES_MODE_CTR 4 /*!< AES select CTR mode \hideinitializer */
-#define AES_MODE_CBC_CS1 0x10 /*!< AES select CBC CS1 mode \hideinitializer */
-#define AES_MODE_CBC_CS2 0x11 /*!< AES select CBC CS2 mode \hideinitializer */
-#define AES_MODE_CBC_CS3 0x12 /*!< AES select CBC CS3 mode \hideinitializer */
-
-#define AES_NO_SWAP 0 /*!< AES do not swap input and output data \hideinitializer */
-#define AES_OUT_SWAP 1 /*!< AES swap output data \hideinitializer */
-#define AES_IN_SWAP 2 /*!< AES swap input data \hideinitializer */
-#define AES_IN_OUT_SWAP 3 /*!< AES swap both input and output data \hideinitializer */
-
-#define DES_MODE_ECB 0x000 /*!< DES select ECB mode \hideinitializer */
-#define DES_MODE_CBC 0x100 /*!< DES select CBC mode \hideinitializer */
-#define DES_MODE_CFB 0x200 /*!< DES select CFB mode \hideinitializer */
-#define DES_MODE_OFB 0x300 /*!< DES select OFB mode \hideinitializer */
-#define DES_MODE_CTR 0x400 /*!< DES select CTR mode \hideinitializer */
-#define TDES_MODE_ECB 0x004 /*!< TDES select ECB mode \hideinitializer */
-#define TDES_MODE_CBC 0x104 /*!< TDES select CBC mode \hideinitializer */
-#define TDES_MODE_CFB 0x204 /*!< TDES select CFB mode \hideinitializer */
-#define TDES_MODE_OFB 0x304 /*!< TDES select OFB mode \hideinitializer */
-#define TDES_MODE_CTR 0x404 /*!< TDES select CTR mode \hideinitializer */
-
-#define TDES_NO_SWAP 0 /*!< TDES do not swap data \hideinitializer */
-#define TDES_WHL_SWAP 1 /*!< TDES swap high-low word \hideinitializer */
-#define TDES_OUT_SWAP 2 /*!< TDES swap output data \hideinitializer */
-#define TDES_OUT_WHL_SWAP 3 /*!< TDES swap output data and high-low word \hideinitializer */
-#define TDES_IN_SWAP 4 /*!< TDES swap input data \hideinitializer */
-#define TDES_IN_WHL_SWAP 5 /*!< TDES swap input data and high-low word \hideinitializer */
-#define TDES_IN_OUT_SWAP 6 /*!< TDES swap both input and output data \hideinitializer */
-#define TDES_IN_OUT_WHL_SWAP 7 /*!< TDES swap input, output and high-low word \hideinitializer */
-
-#define SHA_MODE_SHA1 0 /*!< SHA select SHA-1 160-bit \hideinitializer */
-#define SHA_MODE_SHA224 5 /*!< SHA select SHA-224 224-bit \hideinitializer */
-#define SHA_MODE_SHA256 4 /*!< SHA select SHA-256 256-bit \hideinitializer */
-
-#define SHA_NO_SWAP 0 /*!< SHA do not swap input and output data \hideinitializer */
-#define SHA_OUT_SWAP 1 /*!< SHA swap output data \hideinitializer */
-#define SHA_IN_SWAP 2 /*!< SHA swap input data \hideinitializer */
-#define SHA_IN_OUT_SWAP 3 /*!< SHA swap both input and output data \hideinitializer */
-
-#define CRYPTO_DMA_ONE_SHOT 0x5 /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */
-#define CRYPTO_DMA_CONTINUE 0x6 /*!< Do one continuous encrypt/decrypt with DMA \hideinitializer */
-#define CRYPTO_DMA_LAST 0x6 /*!< Do last encrypt/decrypt with DMA \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_CRYPTO_EXPORTED_CONSTANTS */
-
-
-
-
-/** @addtogroup NUC472_442_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
- @{
-*/
-
-/*----------------------------------------------------------------------------------------------*/
-/* Macros */
-/*----------------------------------------------------------------------------------------------*/
-
-/**
- * @brief This macro enables PRNG interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define PRNG_ENABLE_INT() (CRPT->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
-
-/**
- * @brief This macro disables PRNG interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define PRNG_DISABLE_INT() (CRPT->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
-
-/**
- * @brief This macro gets PRNG interrupt flag.
- * @param None
- * @return PRNG interrupt flag.
- * \hideinitializer
- */
-#define PRNG_GET_INT_FLAG() (CRPT->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
-
-/**
- * @brief This macro clears PRNG interrupt flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define PRNG_CLR_INT_FLAG() (CRPT->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
-
-/**
- * @brief This macro enables AES interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define AES_ENABLE_INT() (CRPT->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESERRIEN_Msk))
-
-/**
- * @brief This macro disables AES interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define AES_DISABLE_INT() (CRPT->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESERRIEN_Msk))
-
-/**
- * @brief This macro gets AES interrupt flag.
- * @param None
- * @return AES interrupt flag.
- * \hideinitializer
- */
-#define AES_GET_INT_FLAG() (CRPT->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESERRIF_Msk))
-
-/**
- * @brief This macro clears AES interrupt flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define AES_CLR_INT_FLAG() (CRPT->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESERRIF_Msk))
-
-/**
- * @brief This macro enables AES key protection.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define AES_ENABLE_KEY_PROTECT() (CRPT->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
-
-/**
- * @brief This macro disables AES key protection.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define AES_DISABLE_KEY_PROTECT() (CRPT->AES_CTL = (CRPT->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16<<CRPT_AES_CTL_KEYUNPRT_Pos))
-
-/**
- * @brief This macro enables TDES interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define TDES_ENABLE_INT() (CRPT->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESERRIEN_Msk))
-
-/**
- * @brief This macro disables TDES interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define TDES_DISABLE_INT() (CRPT->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESERRIEN_Msk))
-
-/**
- * @brief This macro gets TDES interrupt flag.
- * @param None
- * @return TDES interrupt flag.
- * \hideinitializer
- */
-#define TDES_GET_INT_FLAG() (CRPT->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESERRIF_Msk))
-
-/**
- * @brief This macro clears TDES interrupt flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define TDES_CLR_INT_FLAG() (CRPT->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESERRIF_Msk))
-
-/**
- * @brief This macro enables TDES key protection.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define TDES_ENABLE_KEY_PROTECT() (CRPT->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
-
-/**
- * @brief This macro disables TDES key protection.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define TDES_DISABLE_KEY_PROTECT() (CRPT->TDES_CTL = (CRPT->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16<<CRPT_TDES_CTL_KEYUNPRT_Pos))
-
-/**
- * @brief This macro enables SHA interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define SHA_ENABLE_INT() (CRPT->INTEN |= (CRPT_INTEN_SHAIEN_Msk|CRPT_INTEN_SHAERRIEN_Msk))
-
-/**
- * @brief This macro disables SHA interrupt.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define SHA_DISABLE_INT() (CRPT->INTEN &= ~(CRPT_INTEN_SHAIEN_Msk|CRPT_INTEN_SHAERRIEN_Msk))
-
-/**
- * @brief This macro gets SHA interrupt flag.
- * @param None
- * @return SHA interrupt flag.
- * \hideinitializer
- */
-#define SHA_GET_INT_FLAG() (CRPT->INTSTS & (CRPT_INTSTS_SHAIF_Msk|CRPT_INTSTS_SHAERRIF_Msk))
-
-/**
- * @brief This macro clears SHA interrupt flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define SHA_CLR_INT_FLAG() (CRPT->INTSTS = (CRPT_INTSTS_SHAIF_Msk|CRPT_INTSTS_SHAERRIF_Msk))
-
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Functions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-void PRNG_Open(uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
-void PRNG_Start(void);
-void PRNG_Read(uint32_t u32RandKey[]);
-void AES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
-void AES_Start(int32_t u32Channel, uint32_t u32DMAMode);
-void AES_SetKey(uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
-void AES_SetInitVect(uint32_t u32Channel, uint32_t au32IV[]);
-void AES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
-void TDES_Open(uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32SwapType);
-void TDES_Start(int32_t u32Channel, uint32_t u32DMAMode);
-void TDES_SetKey(uint32_t u32Channel, uint8_t au8Keys[3][8]);
-void TDES_SetInitVect(uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
-void TDES_SetDMATransfer(uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
-void SHA_Open(uint32_t u32OpMode, uint32_t u32SwapType);
-void SHA_Start(uint32_t u32DMAMode);
-void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt);
-void SHA_Read(uint32_t u32Digest[]);
-
-
-/*@}*/ /* end of group NUC472_442_CRYPTO_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_CRYPTO_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __CRYPTO_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_eadc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,188 +0,0 @@
-/**************************************************************************//**
- * @file eadc.c
- * @version V1.00
- * $Revision: 4 $
- * $Date: 14/10/07 4:46p $
- * @brief NUC472/NUC442 EADC driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EADC_Driver EADC Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_EADC_EXPORTED_FUNCTIONS EADC Exported Functions
- @{
-*/
-
-/**
- * @brief This function make EADC_module be ready to convert.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32InputMode This parameter is not used.
- * @return None
- * @details This function is used to set analog input mode and enable A/D Converter.
- * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
- * @note
- */
-void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
-{
- eadc->CTL |= EADC_CTL_ADCEN_Msk;
-}
-
-/**
- * @brief Disable EADC_module.
- * @param[in] eadc Base address of EADC module..
- * @return None
- * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
- */
-void EADC_Close(EADC_T *eadc)
-{
- eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
-}
-
-/**
- * @brief Configure the sample control logic module.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC0_SAMPLE_MODULE4 : EADC0 SAMPLE module 4
- * - \ref EADC0_SAMPLE_MODULE5 : EADC0 SAMPLE module 5
- * - \ref EADC0_SAMPLE_MODULE6 : EADC0 SAMPLE module 6
- * - \ref EADC0_SAMPLE_MODULE7 : EADC0 SAMPLE module 7
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE4 : EADC1 SAMPLE module 4
- * - \ref EADC1_SAMPLE_MODULE5 : EADC1 SAMPLE module 5
- * - \ref EADC1_SAMPLE_MODULE6 : EADC1 SAMPLE module 6
- * - \ref EADC1_SAMPLE_MODULE7 : EADC1 SAMPLE module 7
- * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
- * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
- * - \ref EADC_STADC_TRIGGER : STADC pin trigger
- * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger
- * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger
- * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
- * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
- * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
- * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
- * - \ref EADC_EPWM0CH0_TRIGGER : EPWM0CH0 trigger
- * - \ref EADC_EPWM0CH2_TRIGGER : EPWM0CH2 trigger
- * - \ref EADC_EPWM0CH4_TRIGGER : EPWM0CH4 trigger
- * - \ref EADC_EPWM1CH0_TRIGGER : EPWM0CH0 trigger
- * - \ref EADC_EPWM1CH2_TRIGGER : EPWM0CH2 trigger
- * - \ref EADC_EPWM1CH4_TRIGGER : EPWM0CH4 trigger
- * - \ref EADC_PWM0CH0_TRIGGER : PWM0CH0 trigger
- * - \ref EADC_PWM0CH1_TRIGGER : PWM0CH1 trigger
- * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
- * @return None
- * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
- * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
- */
-void EADC_ConfigSampleModule(EADC_T *eadc, \
- uint32_t u32ModuleNum, \
- uint32_t u32TriggerSrc, \
- uint32_t u32Channel)
-{
- *(__IO uint32_t *)(&eadc->AD0SPCTL0 + u32ModuleNum) &= ~(EADC_AD0SPCTL0_TRGSEL_Msk | EADC_AD0SPCTL0_CHSEL_Msk);
- *(__IO uint32_t *)(&eadc->AD0SPCTL0 + u32ModuleNum) |= (u32TriggerSrc | u32Channel);
- if (u32TriggerSrc == EADC_STADC_TRIGGER)
- *(__IO uint32_t *)(&eadc->AD0SPCTL0 + u32ModuleNum) |= (EADC_AD0SPCTL0_EXTREN_Msk | EADC_AD0SPCTL0_EXTFEN_Msk);
-
-}
-
-
-/**
- * @brief Set trigger delay time.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC0_SAMPLE_MODULE4 : EADC0 SAMPLE module 4
- * - \ref EADC0_SAMPLE_MODULE5 : EADC0 SAMPLE module 5
- * - \ref EADC0_SAMPLE_MODULE6 : EADC0 SAMPLE module 6
- * - \ref EADC0_SAMPLE_MODULE7 : EADC0 SAMPLE module 7
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE4 : EADC1 SAMPLE module 4
- * - \ref EADC1_SAMPLE_MODULE5 : EADC1 SAMPLE module 5
- * - \ref EADC1_SAMPLE_MODULE6 : EADC1 SAMPLE module 6
- * - \ref EADC1_SAMPLE_MODULE7 : EADC1 SAMPLE module 7
- * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
- * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
- * - \ref EADC_SPCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1
- * - \ref EADC_SPCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2
- * - \ref EADC_SPCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4
- * - \ref EADC_SPCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16
- * @return None
- * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=8~15).
- * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
- */
-void EADC_SetTriggerDelayTime(EADC_T *eadc, \
- uint32_t u32ModuleNum, \
- uint32_t u32TriggerDelayTime, \
- uint32_t u32DelayClockDivider)
-{
- *(__IO uint32_t *)(&eadc->AD0SPCTL0 + u32ModuleNum) &= ~(EADC_AD0SPCTL0_TRGDLYDIV_Msk | EADC_AD0SPCTL0_TRGDLYCNT_Msk);
- *(__IO uint32_t *)(&eadc->AD0SPCTL0 + u32ModuleNum) |= ((u32TriggerDelayTime << EADC_AD0SPCTL0_TRGDLYCNT_Pos) | u32DelayClockDivider);
-}
-
-
-/**
- * @brief Set ADC extend sample time.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC0_SAMPLE_MODULE4 : EADC0 SAMPLE module 4
- * - \ref EADC0_SAMPLE_MODULE5 : EADC0 SAMPLE module 5
- * - \ref EADC0_SAMPLE_MODULE6 : EADC0 SAMPLE module 6
- * - \ref EADC0_SAMPLE_MODULE7 : EADC0 SAMPLE module 7
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE4 : EADC1 SAMPLE module 4
- * - \ref EADC1_SAMPLE_MODULE5 : EADC1 SAMPLE module 5
- * - \ref EADC1_SAMPLE_MODULE6 : EADC1 SAMPLE module 6
- * - \ref EADC1_SAMPLE_MODULE7 : EADC1 SAMPLE module 7
- * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
- * @return None
- * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
- * user can extend A/D sampling time after trigger source is coming to get enough sampling time.
- */
-void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
-{
- if (u32ModuleNum < EADC1_SAMPLE_MODULE0) {
- eadc->EXTSMPT &= ~EADC_EXTSMPT_EXTSMPT0_Msk;
- eadc->EXTSMPT |= u32ExtendSampleTime;
- } else {
- eadc->EXTSMPT &= ~EADC_EXTSMPT_EXTSMPT1_Msk;
- eadc->EXTSMPT |= (u32ExtendSampleTime << EADC_EXTSMPT_EXTSMPT1_Pos);
- }
-}
-
-/*@}*/ /* end of group NUC472_442_EADC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_EADC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_eadc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,513 +0,0 @@
-/**************************************************************************//**
- * @file eadc.h
- * @version V1.00
- * $Revision: 9 $
- * $Date: 14/10/07 4:02p $
- * @brief NUC472/NUC442 ADC driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __EADC_H__
-#define __EADC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EADC_Driver EADC Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EADC_EXPORTED_CONSTANTS EADC Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC SAMPLE module number Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EADC0_SAMPLE_MODULE0 0 /*!< EADC0 SAMPLE module 0 \hideinitializer */
-#define EADC0_SAMPLE_MODULE1 1 /*!< EADC0 SAMPLE module 1 \hideinitializer */
-#define EADC0_SAMPLE_MODULE2 2 /*!< EADC0 SAMPLE module 2 \hideinitializer */
-#define EADC0_SAMPLE_MODULE3 3 /*!< EADC0 SAMPLE module 3 \hideinitializer */
-#define EADC0_SAMPLE_MODULE4 4 /*!< EADC0 SAMPLE module 4 \hideinitializer */
-#define EADC0_SAMPLE_MODULE5 5 /*!< EADC0 SAMPLE module 5 \hideinitializer */
-#define EADC0_SAMPLE_MODULE6 6 /*!< EADC0 SAMPLE module 6 \hideinitializer */
-#define EADC0_SAMPLE_MODULE7 7 /*!< EADC0 SAMPLE module 7 \hideinitializer */
-#define EADC1_SAMPLE_MODULE0 8 /*!< EADC1 SAMPLE module 0 \hideinitializer */
-#define EADC1_SAMPLE_MODULE1 9 /*!< EADC1 SAMPLE module 1 \hideinitializer */
-#define EADC1_SAMPLE_MODULE2 10 /*!< EADC1 SAMPLE module 2 \hideinitializer */
-#define EADC1_SAMPLE_MODULE3 11 /*!< EADC1 SAMPLE module 3 \hideinitializer */
-#define EADC1_SAMPLE_MODULE4 12 /*!< EADC1 SAMPLE module 4 \hideinitializer */
-#define EADC1_SAMPLE_MODULE5 13 /*!< EADC1 SAMPLE module 5 \hideinitializer */
-#define EADC1_SAMPLE_MODULE6 14 /*!< EADC1 SAMPLE module 6 \hideinitializer */
-#define EADC1_SAMPLE_MODULE7 15 /*!< EADC1 SAMPLE module 7 \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC_ADnSPCTLx Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EADC_SCTL_CHSEL(x) ((x) << EADC_AD0SPCTL0_CHSEL_Pos) /*!< A/D sample module channel selection \hideinitializer */
-#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection \hideinitializer */
-#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_AD0SPCTL0_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time \hideinitializer */
-
-#define EADC_SOFTWARE_TRIGGER (0UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< Software trigger \hideinitializer */
-#define EADC_STADC_TRIGGER (1UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< External pin STADC trigger \hideinitializer */
-#define EADC_ADINT0_TRIGGER (2UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger \hideinitializer */
-#define EADC_ADINT1_TRIGGER (3UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger \hideinitializer */
-#define EADC_TIMER0_TRIGGER (4UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger \hideinitializer */
-#define EADC_TIMER1_TRIGGER (5UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger \hideinitializer */
-#define EADC_TIMER2_TRIGGER (6UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger \hideinitializer */
-#define EADC_TIMER3_TRIGGER (7UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger \hideinitializer */
-#define EADC_EPWM0CH0_TRIGGER (8UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EPWM0CH0 trigger \hideinitializer */
-#define EADC_EPWM0CH2_TRIGGER (9UL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EPWM0CH2 trigger \hideinitializer */
-#define EADC_EPWM0CH4_TRIGGER (0xAUL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EPWM0CH4 trigger \hideinitializer */
-#define EADC_EPWM1CH0_TRIGGER (0xBUL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EPWM1CH0 trigger \hideinitializer */
-#define EADC_EPWM1CH2_TRIGGER (0xCUL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EPWM1CH2 trigger \hideinitializer */
-#define EADC_EPWM1CH4_TRIGGER (0xDUL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EPWM1CH4 trigger \hideinitializer */
-#define EADC_PWM0CH0_TRIGGER (0xEUL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< PWM0CH0 trigger \hideinitializer */
-#define EADC_PWM0CH1_TRIGGER (0xFUL << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< PWM0CH1 trigger \hideinitializer */
-
-#define EADC_SPCTL_TRGDLYDIV_DIVIDER_1 (0 << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 \hideinitializer */
-#define EADC_SPCTL_TRGDLYDIV_DIVIDER_2 (0x1UL << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 \hideinitializer */
-#define EADC_SPCTL_TRGDLYDIV_DIVIDER_4 (0x2UL << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 \hideinitializer */
-#define EADC_SPCTL_TRGDLYDIV_DIVIDER_16 (0x3UL << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 \hideinitializer */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC_CMP Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define EADC_CMP_CMPCOND_LESS_THAN (0UL << EADC_CMP0_CMPCOND_Pos) /*!< The compare condition is "less than" \hideinitializer */
-#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL << EADC_CMP0_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" \hideinitializer */
-#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP0_ADCMPIE_Msk) /*!< A/D result compare interrupt enable \hideinitializer */
-#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP0_ADCMPIE_Msk) /*!< A/D result compare interrupt disable \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_EADC_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_EADC_EXPORTED_FUNCTIONS EADC Exported Functions
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* EADC Macro Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-/**
- * @brief A/D Converter Control Circuits Reset.
- * @param[in] eadc Base address of EADC module.
- * @return None
- * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
- * \hideinitializer
- */
-#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
-
-/**
- * @brief Enable double buffer mode.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * @return None
- * @details The ADC controller supports a double buffer mode in eadc0/1 sample module 0~3.
- * \hideinitializer
- */
-#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->DBMEN |= (1 << u32ModuleNum))
-
-/**
- * @brief Disable double buffer mode.
- * @param[in] eadc Base address of EADC module..
- * @param[in] u32ModuleNum Decides the sample module number, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * @return None
- * @details Sample has one sample result register.
- * \hideinitializer
- */
-#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->DBMEN &= ~(1 << u32ModuleNum))
-
-/**
- * @brief Enable the interrupt.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
- * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
- * @return None
- * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS1[n]) upon the end of specific sample module A/D conversion.
- * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
- * \hideinitializer
- */
-#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
-
-/**
- * @brief Disable the interrupt.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
- * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
- * @return None
- * @details Specific sample module A/D ADINT0 interrupt function Disabled.
- * \hideinitializer
- */
-#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
-
-/**
- * @brief Enable the sample module interrupt.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
- * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
- * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0xFFFF.
- * @return None
- * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
- * \hideinitializer
- */
-#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
-
-/**
- * @brief Disable the sample module interrupt.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
- * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
- * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0xFFFF.
- * @return None
- * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
- * \hideinitializer
- */
-#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
-
-/**
- * @brief Start the A/D conversion.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
- * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
- * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
- * @return None
- * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
- * \hideinitializer
- */
-#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
-
-/**
- * @brief Get the conversion pending flag.
- * @param[in] eadc Base address of EADC module.
- * @return Return the conversion pending sample module.
- * @return None
- * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
- * the STPFn (n=0~18) bit is automatically cleared to 0.
- * \hideinitializer
- */
-#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
-
-/**
- * @brief Get the conversion data of the user-specified sample module.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC0_SAMPLE_MODULE4 : EADC0 SAMPLE module 4
- * - \ref EADC0_SAMPLE_MODULE5 : EADC0 SAMPLE module 5
- * - \ref EADC0_SAMPLE_MODULE6 : EADC0 SAMPLE module 6
- * - \ref EADC0_SAMPLE_MODULE7 : EADC0 SAMPLE module 7
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE4 : EADC1 SAMPLE module 4
- * - \ref EADC1_SAMPLE_MODULE5 : EADC1 SAMPLE module 5
- * - \ref EADC1_SAMPLE_MODULE6 : EADC1 SAMPLE module 6
- * - \ref EADC1_SAMPLE_MODULE7 : EADC1 SAMPLE module 7
- * @return Return the conversion data of the user-specified sample module.
- * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
- * \hideinitializer
- */
-#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) (*(__IO uint32_t *)(&((eadc)->AD0DAT0) + (u32ModuleNum)) & EADC_AD0DAT0_RESULT_Msk)
-
-/**
- * @brief Get the data overrun flag of the user-specified sample module.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
- * @return Return the data overrun flag of the user-specified sample module.
- * @details This macro is used to read OV bit (EADC_STATUS0[31:16]) field to get data overrun status.
- * \hideinitializer
- */
-#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) (((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) & (u32ModuleMask))
-
-/**
- * @brief Get the data valid flag of the user-specified sample module.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
- * @return Return the data valid flag of the user-specified sample module.
- * @details This macro is used to read VALID bit of EADC_STATUS0[15:0] to get data valid status.
- * \hideinitializer
- */
-#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) (((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) & (u32ModuleMask))
-
-/**
- * @brief Get the double data of the user-specified sample module.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum Decides the sample module number, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * @return Return the double data of the user-specified sample module.
- * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
- * \hideinitializer
- */
-#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) (*(__IO uint32_t *)(&((eadc)->AD0DDAT0) + (u32ModuleNum)) & EADC_AD0DDAT0_RESULT_Msk)
-
-/**
- * @brief Get the user-specified interrupt flags.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
- * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
- * Bit 4 is ADCMPO0, bit 5 is ADCMPO1, bit 6 is ADCMPF0, bit 7 is ADCMPF1.
- * @return Return the user-specified interrupt flags.
- * @details This macro is used to get the user-specified interrupt flags.
- * \hideinitializer
- */
-#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS1 & (u32Mask))
-
-/**
- * @brief Get the user-specified sample module overrun flags.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0xFFFF.
- * @return Return the user-specified sample module overrun flags.
- * @details This macro is used to get the user-specified sample module overrun flags.
- * \hideinitializer
- */
-#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) (((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) & u32ModuleMask)
-
-/**
- * @brief Clear the selected interrupt status bits.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
- * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
- * Bit 4 is ADCMPO0, bit 5 is ADCMPO1, bit 6 is ADCMPF0, bit 7 is ADCMPF1.
- * @return None
- * @details This macro is used to clear clear the selected interrupt status bits.
- * \hideinitializer
- */
-#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS1 = (u32Mask))
-
-/**
- * @brief Check all sample module A/D result data register overrun flags.
- * @param[in] eadc Base address of EADC module.
- * @retval 0 None of sample module data register overrun flag is set to 1.
- * @retval 1 Any one of sample module data register overrun flag is set to 1.
- * @details The AOV bit (EADC_STATUS1[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
- * \hideinitializer
- */
-#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS1 & EADC_STATUS1_AOV_Msk) >> EADC_STATUS1_AOV_Pos)
-
-/**
- * @brief Check all sample module A/D result data register valid flags.
- * @param[in] eadc Base address of EADC module.
- * @retval 0 None of sample module data register valid flag is set to 1.
- * @retval 1 Any one of sample module data register valid flag is set to 1.
- * @details The AVALID bit (EADC_STATUS1[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
- * \hideinitializer
- */
-#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS1 & EADC_STATUS1_AVALID_Msk) >> EADC_STATUS1_AVALID_Pos)
-
-/**
- * @brief Check all A/D sample module start of conversion overrun flags.
- * @param[in] eadc Base address of EADC module.
- * @retval 0 None of sample module event overrun flag is set to 1.
- * @retval 1 Any one of sample module event overrun flag is set to 1.
- * @details The STOVF bit (EADC_STATUS1[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
- * \hideinitializer
- */
-#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS1 & EADC_STATUS1_STOVF_Msk) >> EADC_STATUS1_STOVF_Pos)
-
-/**
- * @brief Check all A/D interrupt flag overrun bits.
- * @param[in] eadc Base address of EADC module.
- * @retval 0 None of ADINT interrupt flag is overwritten to 1.
- * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
- * @details The ADOVIF bit (EADC_STATUS1[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS1[11:8]) is overwritten to 1.
- * \hideinitializer
- */
-#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS1 & EADC_STATUS1_ADOVIF_Msk) >> EADC_STATUS1_ADOVIF_Pos)
-
-/**
- * @brief Get the busy state of EADC.
- * @param[in] eadc Base address of EADC module.
- * @param[in] converter Which converter, it should be 0 or 1.
- * @retval 0 Idle state.
- * @retval 1 Busy state.
- * @details This macro is used to read BUSY0(EADC_STATUS1[8]) or BUSY1(EADC_STATUS1[16]) to get busy state.
- * \hideinitializer
- */
-#define EADC_IS_BUSY(eadc, converter) (((((eadc)->STATUS1 >> (EADC_STATUS1_BUSY0_Pos + (8 * converter)))) & EADC_STATUS1_BUSY0_Msk) )
-
-/**
- * @brief Configure the comparator 0 and enable it.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum specifies the compare sample module, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC0_SAMPLE_MODULE4 : EADC0 SAMPLE module 4
- * - \ref EADC0_SAMPLE_MODULE5 : EADC0 SAMPLE module 5
- * - \ref EADC0_SAMPLE_MODULE6 : EADC0 SAMPLE module 6
- * - \ref EADC0_SAMPLE_MODULE7 : EADC0 SAMPLE module 7
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE4 : EADC1 SAMPLE module 4
- * - \ref EADC1_SAMPLE_MODULE5 : EADC1 SAMPLE module 5
- * - \ref EADC1_SAMPLE_MODULE6 : EADC1 SAMPLE module 6
- * - \ref EADC1_SAMPLE_MODULE7 : EADC1 SAMPLE module 7
- * @param[in] u32Condition specifies the compare condition. Valid values are:
- * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
- * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
- * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
- * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
- * @return None
- * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
- * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
- * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
- * \hideinitializer
- */
-#define EADC_ENABLE_CMP0(eadc,\
- u32ModuleNum,\
- u32Condition,\
- u16CMPData,\
- u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP0_CMPSPL_Pos)|\
- (u32Condition) |\
- ((u16CMPData) << EADC_CMP0_CMPDAT_Pos)| \
- (((u32MatchCount) - 1) << EADC_CMP0_CMPMCNT_Pos)|\
- EADC_CMP0_ADCMPEN_Msk))
-
-/**
- * @brief Configure the comparator 1 and enable it.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32ModuleNum specifies the compare sample module, valid values are:
- * - \ref EADC0_SAMPLE_MODULE0 : EADC0 SAMPLE module 0
- * - \ref EADC0_SAMPLE_MODULE1 : EADC0 SAMPLE module 1
- * - \ref EADC0_SAMPLE_MODULE2 : EADC0 SAMPLE module 2
- * - \ref EADC0_SAMPLE_MODULE3 : EADC0 SAMPLE module 3
- * - \ref EADC0_SAMPLE_MODULE4 : EADC0 SAMPLE module 4
- * - \ref EADC0_SAMPLE_MODULE5 : EADC0 SAMPLE module 5
- * - \ref EADC0_SAMPLE_MODULE6 : EADC0 SAMPLE module 6
- * - \ref EADC0_SAMPLE_MODULE7 : EADC0 SAMPLE module 7
- * - \ref EADC1_SAMPLE_MODULE0 : EADC1 SAMPLE module 0
- * - \ref EADC1_SAMPLE_MODULE1 : EADC1 SAMPLE module 1
- * - \ref EADC1_SAMPLE_MODULE2 : EADC1 SAMPLE module 2
- * - \ref EADC1_SAMPLE_MODULE3 : EADC1 SAMPLE module 3
- * - \ref EADC1_SAMPLE_MODULE4 : EADC1 SAMPLE module 4
- * - \ref EADC1_SAMPLE_MODULE5 : EADC1 SAMPLE module 5
- * - \ref EADC1_SAMPLE_MODULE6 : EADC1 SAMPLE module 6
- * - \ref EADC1_SAMPLE_MODULE7 : EADC1 SAMPLE module 7
- * @param[in] u32Condition specifies the compare condition. Valid values are:
- * - EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
- * - EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
- * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
- * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
- * @return None
- * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
- * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
- * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
- * \hideinitializer
- */
-#define EADC_ENABLE_CMP1(eadc,\
- u32ModuleNum,\
- u32Condition,\
- u16CMPData,\
- u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP1_CMPSPL_Pos)|\
- (u32Condition) |\
- ((u16CMPData) << EADC_CMP1_CMPDAT_Pos)| \
- (((u32MatchCount) - 1) << EADC_CMP1_CMPMCNT_Pos)|\
- EADC_CMP1_ADCMPEN_Msk))
-
-/**
- * @brief Enable the compare interrupt.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32CMP Specifies the compare register, valid value are 0 and 1.
- * @return None
- * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~1)
- * and CMPMCNT (EADC_CMPn[11:8], n=0~1), ADCMPFn (EADC_STATUS1[7:6], n=0~1) will be asserted, in the meanwhile,
- * if ADCMPIE is set to 1, a compare interrupt request is generated.
- * \hideinitializer
- */
-#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP0_ADCMPIE_Msk)
-
-/**
- * @brief Disable the compare interrupt.
- * @param[in] eadc Base address of EADC module.
- * @param[in] u32CMP Specifies the compare register, valid value are 0 and 1.
- * @return None
- * @details This macro is used to disable the compare interrupt.
- * \hideinitializer
- */
-#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP0_ADCMPIE_Msk)
-
-/**
- * @brief Disable comparator 0.
- * @param[in] eadc Base address of EADC module.
- * @return None
- * @details This macro is used to disable comparator 0.
- * \hideinitializer
- */
-#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
-
-/**
- * @brief Disable comparator 1.
- * @param[in] eadc Base address of EADC module.
- * @return None
- * @details This macro is used to disable comparator 1.
- * \hideinitializer
- */
-#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define EADC functions prototype */
-/*---------------------------------------------------------------------------------------------------------*/
-void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
-void EADC_Close(EADC_T *eadc);
-void EADC_ConfigSampleModule(EADC_T *eadc, \
- uint32_t u32ModuleNum, \
- uint32_t u32TriggerSource, \
- uint32_t u32Channel);
-void EADC_SetTriggerDelayTime(EADC_T *eadc, \
- uint32_t u32ModuleNum, \
- uint32_t u32TriggerDelayTime, \
- uint32_t u32DelayClockDivider);
-void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
-
-/*@}*/ /* end of group NUC472_442_EADC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_EADC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__EADC_H__
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_ebi.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,245 +0,0 @@
-/****************************************************************************//**
- * @file ebi.c
- * @version V0.10
- * $Revision: 7 $
- * $Date: 14/09/30 1:10p $
- * @brief NUC472/NUC442 EBI driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-//#include "ebi.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EBI_Driver EBI Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
- @{
-*/
-
-/**
- * @brief Initialize EBI for Bank 0~3
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- * - \ref EBI_BANK2
- * - \ref EBI_BANK3
- * @param[in] u32DataWidth Data bus width. Valid values are:
- * - \ref EBI_BUSWIDTH_8BIT
- * - \ref EBI_BUSWIDTH_16BIT
- * @param[in] u32TimingClass Default timing configuration. Valid values are:
- * - \ref EBI_TIMING_FASTEST
- * - \ref EBI_TIMING_VERYFAST
- * - \ref EBI_TIMING_FAST
- * - \ref EBI_TIMING_NORMAL
- * - \ref EBI_TIMING_SLOW
- * - \ref EBI_TIMING_VERYSLOW
- * - \ref EBI_TIMING_SLOWEST
- * @param[in] u32BusMode Enable EBI separate mode. Valid values are:
- * - \ref EBI_SEPARATEMODE_ENABLE
- * - \ref EBI_SEPARATEMODE_DISABLE
- * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
- * - \ref EBI_CS_ACTIVE_HIGH
- * - \ref EBI_CS_ACTIVE_LOW
- * @return none
- */
-void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
-{
- /* Enable EBI channel */
- EBI->TCTL[u32Bank] |= EBI_TCTL_CSEN_Msk;
-
- /* Configure data bus to 8 or 16bit */
- if(u32DataWidth == EBI_BUSWIDTH_8BIT)
- EBI->TCTL[u32Bank] &= ~EBI_TCTL_DW16_Msk;
- else
- EBI->TCTL[u32Bank] |= EBI_TCTL_DW16_Msk;
-
- /* Enable separate mode */
- if(u32BusMode)
- EBI->TCTL[u32Bank] |= EBI_TCTL_SEPEN_Msk;
- else
- EBI->TCTL[u32Bank] &= ~EBI_TCTL_SEPEN_Msk;
-
- /* Setup active level of chip select */
- switch(u32Bank) {
- case EBI_BANK0:
- if(u32CSActiveLevel)
- EBI->CTL |= (0x1ul << EBI_CTL_CSPOLINV_Pos);
- else
- EBI->CTL &= ~(0x1ul << EBI_CTL_CSPOLINV_Pos);
- break;
-
- case EBI_BANK1:
- if(u32CSActiveLevel)
- EBI->CTL |= (0x2ul << EBI_CTL_CSPOLINV_Pos);
- else
- EBI->CTL &= ~(0x2ul << EBI_CTL_CSPOLINV_Pos);
- break;
-
- case EBI_BANK2:
- if(u32CSActiveLevel)
- EBI->CTL |= (0x4ul << EBI_CTL_CSPOLINV_Pos);
- else
- EBI->CTL &= ~(0x4ul << EBI_CTL_CSPOLINV_Pos);
- break;
-
- case EBI_BANK3:
- if(u32CSActiveLevel)
- EBI->CTL |= (0x8ul << EBI_CTL_CSPOLINV_Pos);
- else
- EBI->CTL &= ~(0x8ul << EBI_CTL_CSPOLINV_Pos);
- break;
- }
-
- /* Clear R2R/R2W/R2X/TAHD/TACC/TALE entries for safety */
- EBI->TCTL[u32Bank] &= ~0x0F0FF7FF;
-
- /* Setup EBI timing */
- switch(u32TimingClass) {
- case EBI_TIMING_FASTEST:
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_1 << 8);
- break;
-
- case EBI_TIMING_VERYFAST:
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_1 << 8);
- EBI->TCTL[u32Bank] |= 0x0303331B;
- break;
-
- case EBI_TIMING_FAST:
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_2 << 8);
- break;
-
- case EBI_TIMING_NORMAL:
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_2 << 8);
- EBI->TCTL[u32Bank] |= 0x0303331B;
- break;
-
- case EBI_TIMING_SLOW:
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_2 << 8);
- EBI->TCTL[u32Bank] |= 0x0707773F;
- break;
-
- case EBI_TIMING_VERYSLOW:
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_4 << 8);
- EBI->TCTL[u32Bank] |= 0x0707773F;
- break;
-
- case EBI_TIMING_SLOWEST:
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | ( EBI_MCLKDIV_8 << 8);
- EBI->TCTL[u32Bank] |= 0x0707773F;
- break;
- }
-}
-
-/**
- * @brief Disable EBI for bank 0~3.
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- * - \ref EBI_BANK2
- * - \ref EBI_BANK3
- * @return none
- */
-void EBI_Close(uint32_t u32Bank)
-{
- EBI->TCTL[u32Bank] &= ~EBI_TCTL_CSEN_Msk;
-}
-
-/**
- * @brief Set EBI bus timings
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- * - \ref EBI_BANK2
- * - \ref EBI_BANK3
- * @param[in] u32TimingConfig The new EBI timing settings.
- * @param[in] u32MclkDiv Divider for MCLK. Valid values are:
- * - \ref EBI_MCLKDIV_1
- * - \ref EBI_MCLKDIV_2
- * - \ref EBI_MCLKDIV_4
- * - \ref EBI_MCLKDIV_8
- * - \ref EBI_MCLKDIV_16
- * - \ref EBI_MCLKDIV_32
- * @return none
- */
-void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
-{
- EBI->CTL = (EBI->CTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
- EBI->TCTL[u32Bank] |= u32TimingConfig;
-}
-
-/**
- * @brief Enable encrypt/decrypt function and set key for EBI bank 0~3.
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- * - \ref EBI_BANK2
- * - \ref EBI_BANK3
- * @param[in] *u32Key 128-bits encrypt/decrypt key array.
- * @return none
- */
-void EBI_EnableCrypto(uint32_t u32Bank, uint32_t *u32Key)
-{
- switch(u32Bank) {
- case EBI_BANK0:
- EBI->CTL |= (0x1ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- case EBI_BANK1:
- EBI->CTL |= (0x2ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- case EBI_BANK2:
- EBI->CTL |= (0x4ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- case EBI_BANK3:
- EBI->CTL |= (0x8ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- }
-
- /* Setup 128-bits key */
- EBI->KEY0 = u32Key[0];
- EBI->KEY1 = u32Key[1];
- EBI->KEY2 = u32Key[2];
- EBI->KEY3 = u32Key[3];
-}
-
-/**
- * @brief Disable encrypt/decrypt function for EBI bank 0~3.
- * @param[in] u32Bank Bank number for EBI. Valid values are:
- * - \ref EBI_BANK0
- * - \ref EBI_BANK1
- * - \ref EBI_BANK2
- * - \ref EBI_BANK3
- * @return none
- */
-void EBI_DisbleCrypto(uint32_t u32Bank)
-{
- switch(u32Bank) {
- case EBI_BANK0:
- EBI->CTL &= ~(0x1ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- case EBI_BANK1:
- EBI->CTL &= ~(0x2ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- case EBI_BANK2:
- EBI->CTL &= ~(0x4ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- case EBI_BANK3:
- EBI->CTL &= ~(0x8ul << EBI_CTL_CRYPTOEN_Pos);
- break;
- }
-}
-
-/*@}*/ /* end of group NUC472_442_EBI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_EBI_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_ebi.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,136 +0,0 @@
-/****************************************************************************//**
- * @file ebi.h
- * @version V0.10
- * $Revision: 6 $
- * $Date: 14/09/30 1:12p $
- * @brief NUC472/NUC442 EBI driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __EBI_H__
-#define __EBI_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EBI_Driver EBI Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EBI_EXPORTED_CONSTANTS EBI Exported Constants
- @{
-*/
-
-/* Bank-0 constants */
-#define EBI0_BASE_ADDR 0x60000000 ///<EBI bank 0 base address , 0x60000000 ~ 0x63FFFFFF \hideinitializer
-#define EBI0_MAX_SIZE 0x400000 ///<EBI bank 0 max. size \hideinitializer
-
-#define EBI0_READ_DATA8(Addr) *((volatile unsigned char *)(EBI0_BASE_ADDR+Addr)) ///< Read 8-bit data from EBI bank 0 \hideinitializer
-#define EBI0_WRITE_DATA8(Addr, Data) *((volatile unsigned char *)(EBI0_BASE_ADDR+Addr))=Data ///< Write 8-bit data to EBI bank 0 \hideinitializer
-#define EBI0_READ_DATA16(Addr) *((volatile unsigned short *)(EBI0_BASE_ADDR+Addr)) ///< Read 16-bit data from EBI bank 0 \hideinitializer
-#define EBI0_WRITE_DATA16(Addr, Data) *((volatile unsigned short *)(EBI0_BASE_ADDR+Addr))=Data ///< Write 16-bit data to EBI bank 0 \hideinitializer
-#define EBI0_READ_DATA32(Addr) *((volatile unsigned int *)(EBI0_BASE_ADDR+Addr)) ///< Read 32-bit data from EBI bank 0 \hideinitializer
-#define EBI0_WRITE_DATA32(Addr, Data) *((volatile unsigned int *)(EBI0_BASE_ADDR+Addr))=Data ///< Write 32-bit data to EBI bank 0 \hideinitializer
-
-/* Bank-1 constants */
-#define EBI1_BASE_ADDR 0x64000000 ///<EBI bank 1 base address , 0x64000000 ~ 0x67FFFFFF \hideinitializer
-#define EBI1_MAX_SIZE 0x400000 ///<EBI bank 1 max. size \hideinitializer
-
-#define EBI1_READ_DATA8(Addr) *((volatile unsigned char *)(EBI1_BASE_ADDR+Addr)) ///< Read 8-bit data from EBI bank 0 \hideinitializer
-#define EBI1_WRITE_DATA8(Addr, Data) *((volatile unsigned char *)(EBI1_BASE_ADDR+Addr))=Data ///< Write 8-bit data to EBI bank 0 \hideinitializer
-#define EBI1_READ_DATA16(Addr) *((volatile unsigned short *)(EBI1_BASE_ADDR+Addr)) ///< Read 16-bit data from EBI bank 0 \hideinitializer
-#define EBI1_WRITE_DATA16(Addr, Data) *((volatile unsigned short *)(EBI1_BASE_ADDR+Addr))=Data ///< Write 16-bit data to EBI bank 0 \hideinitializer
-#define EBI1_READ_DATA32(Addr) *((volatile unsigned int *)(EBI1_BASE_ADDR+Addr)) ///< Read 32-bit data from EBI bank 0 \hideinitializer
-#define EBI1_WRITE_DATA32(Addr, Data) *((volatile unsigned int *)(EBI1_BASE_ADDR+Addr))=Data ///< Write 32-bit data to EBI bank 0 \hideinitializer
-
-/* Bank-2 constants */
-#define EBI2_BASE_ADDR 0x68000000 ///<EBI bank 2 base address , 0x68000000 ~ 0x6BFFFFFF
-#define EBI2_MAX_SIZE 0x400000 ///<EBI bank 2 max. size
-
-#define EBI2_READ_DATA8(Addr) *((volatile unsigned char *)(EBI2_BASE_ADDR+Addr)) ///< Read 8-bit data from EBI bank 0 \hideinitializer
-#define EBI2_WRITE_DATA8(Addr, Data) *((volatile unsigned char *)(EBI2_BASE_ADDR+Addr))=Data ///< Write 8-bit data to EBI bank 0 \hideinitializer
-#define EBI2_READ_DATA16(Addr) *((volatile unsigned short *)(EBI2_BASE_ADDR+Addr)) ///< Read 16-bit data from EBI bank 0 \hideinitializer
-#define EBI2_WRITE_DATA16(Addr, Data) *((volatile unsigned short *)(EBI2_BASE_ADDR+Addr))=Data ///< Write 16-bit data to EBI bank 0 \hideinitializer
-#define EBI2_READ_DATA32(Addr) *((volatile unsigned int *)(EBI2_BASE_ADDR+Addr)) ///< Read 32-bit data from EBI bank 0 \hideinitializer
-#define EBI2_WRITE_DATA32(Addr, Data) *((volatile unsigned int *)(EBI2_BASE_ADDR+Addr))=Data ///< Write 32-bit data to EBI bank 0 \hideinitializer
-
-/* Bank-3 constants */
-#define EBI3_BASE_ADDR 0x6C000000 ///<EBI bank 3 base address , 0x6C000000 ~ 0x6FFFFFFF \hideinitializer
-#define EBI3_MAX_SIZE 0x400000 ///<EBI bank 3 max. size \hideinitializer
-
-#define EBI3_READ_DATA8(Addr) *((volatile unsigned char *)(EBI3_BASE_ADDR+Addr)) ///< Read 8-bit data from EBI bank 0 \hideinitializer
-#define EBI3_WRITE_DATA8(Addr, Data) *((volatile unsigned char *)(EBI3_BASE_ADDR+Addr))=Data ///< Write 8-bit data to EBI bank 0 \hideinitializer
-#define EBI3_READ_DATA16(Addr) *((volatile unsigned short *)(EBI3_BASE_ADDR+Addr)) ///< Read 16-bit data from EBI bank 0 \hideinitializer
-#define EBI3_WRITE_DATA16(Addr, Data) *((volatile unsigned short *)(EBI3_BASE_ADDR+Addr))=Data ///< Write 16-bit data to EBI bank 0 \hideinitializer
-#define EBI3_READ_DATA32(Addr) *((volatile unsigned int *)(EBI3_BASE_ADDR+Addr)) ///< Read 32-bit data from EBI bank 0 \hideinitializer
-#define EBI3_WRITE_DATA32(Addr, Data) *((volatile unsigned int *)(EBI3_BASE_ADDR+Addr))=Data ///< Write 32-bit data to EBI bank 0 \hideinitializer
-
-
-/* Constants for EBI bank number */
-#define EBI_BANK0 0 ///< EBI bank 0 \hideinitializer
-#define EBI_BANK1 0x1 ///< EBI bank 1 \hideinitializer
-#define EBI_BANK2 0x2 ///< EBI bank 2 \hideinitializer
-#define EBI_BANK3 0x3 ///< EBI bank 3 \hideinitializer
-
-/* Constants for EBI CS Active Level */
-#define EBI_CS_ACTIVE_HIGH 1 ///< EBI CS active level is high \hideinitializer
-#define EBI_CS_ACTIVE_LOW 0 ///< EBI CS active level is low \hideinitializer
-
-/* Constants for EBI data bus width */
-#define EBI_BUSWIDTH_8BIT 8 ///< EBI bus width is 8-bit \hideinitializer
-#define EBI_BUSWIDTH_16BIT 16 ///< EBI bus width is 16-bit \hideinitializer
-
-/* Constants for EBI separate mode */
-#define EBI_SEPARATEMODE_ENABLE 0x1 ///< Enable EBI separate mode \hideinitializer
-#define EBI_SEPARATEMODE_DISABLE 0 ///< Disable EBI separate mode \hideinitializer
-
-/* Constants for EBI MCLK divider */
-#define EBI_MCLKDIV_1 0 ///< EBI clock is MCLK div 1 \hideinitializer
-#define EBI_MCLKDIV_2 0x1 ///< EBI clock is MCLK div 2 \hideinitializer
-#define EBI_MCLKDIV_4 0x2 ///< EBI clock is MCLK div 4 \hideinitializer
-#define EBI_MCLKDIV_8 0x3 ///< EBI clock is MCLK div 8 \hideinitializer
-#define EBI_MCLKDIV_16 0x4 ///< EBI clock is MCLK div 16 \hideinitializer
-#define EBI_MCLKDIV_32 0x5 ///< EBI clock is MCLK div 32 \hideinitializer
-
-#define EBI_TIMING_FASTEST 0x0 ///< EBI timing is the fastest \hideinitializer
-#define EBI_TIMING_VERYFAST 0x1 ///< EBI timing is very fast \hideinitializer
-#define EBI_TIMING_FAST 0x2 ///< EBI timing is fast \hideinitializer
-#define EBI_TIMING_NORMAL 0x3 ///< EBI timing is normal \hideinitializer
-#define EBI_TIMING_SLOW 0x4 ///< EBI timing is slow \hideinitializer
-#define EBI_TIMING_VERYSLOW 0x5 ///< EBI timing is very slow \hideinitializer
-#define EBI_TIMING_SLOWEST 0x6 ///< EBI timing is the slowest \hideinitializer
-
-/*@}*/ /* end of group NUC472_442_EBI_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_EBI_EXPORTED_FUNCTIONS EBI Exported Functions
- @{
-*/
-void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
-void EBI_Close(uint32_t u32Bank);
-void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
-void EBI_EnableCrypto(uint32_t u32Bank, uint32_t *u32Key);
-void EBI_DisbleCrypto(uint32_t u32Bank);
-
-
-/*@}*/ /* end of group NUC472_442_EBI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_EBI_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__EBI_H__
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_emac.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,874 +0,0 @@
-/**************************************************************************//**
- * @file emac.c
- * @version V1.00
- * $Revision: 14 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 EMAC driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include <stdio.h>
-#include <string.h>
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EMAC_Driver EMAC Driver
- @{
-*/
-
-
-// Below are structure, definitions, static variables used locally by EMAC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined
-/// @cond HIDDEN_SYMBOLS
-
-/** @addtogroup NUC472_442_EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
- @{
-*/
-// Un-comment to print EMAC debug message
-//#define EMAC_DBG
-#ifndef EMAC_DBG
-#define printf(...)
-#endif
-
-// PHY Register Description
-#define PHY_CNTL_REG 0x00 ///< PHY control register address
-#define PHY_STATUS_REG 0x01 ///< PHY status register address
-#define PHY_ID1_REG 0x02 ///< PHY ID1 register
-#define PHY_ID2_REG 0x03 ///< PHY ID2 register
-#define PHY_ANA_REG 0x04 ///< PHY auto-negotiation advertisement register
-#define PHY_ANLPA_REG 0x05 ///< PHY auto-negotiation link partner availability register
-#define PHY_ANE_REG 0x06 ///< PHY auto-negotiation expansion register
-
-//PHY Control Register
-#define PHY_CNTL_RESET_PHY (1 << 15)
-#define PHY_CNTL_DR_100MB (1 << 13)
-#define PHY_CNTL_ENABLE_AN (1 << 12)
-#define PHY_CNTL_POWER_DOWN (1 << 11)
-#define PHY_CNTL_RESTART_AN (1 << 9)
-#define PHY_CNTL_FULLDUPLEX (1 << 8)
-
-// PHY Status Register
-#define PHY_STATUS_AN_COMPLETE (1 << 5)
-#define PHY_STATUS_LINK_VALID (1 << 3)
-
-// PHY Auto-negotiation Advertisement Register
-#define PHY_ANA_DR100_TX_FULL (1 << 8)
-#define PHY_ANA_DR100_TX_HALF (1 << 7)
-#define PHY_ANA_DR10_TX_FULL (1 << 6)
-#define PHY_ANA_DR10_TX_HALF (1 << 5)
-#define PHY_ANA_IEEE_802_3_CSMA_CD (1 << 0)
-
-// PHY Auto-negotiation Link Partner Advertisement Register
-#define PHY_ANLPA_DR100_TX_FULL (1 << 8)
-#define PHY_ANLPA_DR100_TX_HALF (1 << 7)
-#define PHY_ANLPA_DR10_TX_FULL (1 << 6)
-#define PHY_ANLPA_DR10_TX_HALF (1 << 5)
-
-// EMAC Tx/Rx descriptor's owner bit
-#define EMAC_DESC_OWN_EMAC 0x80000000 ///< Set owner to EMAC
-#define EMAC_DESC_OWN_CPU 0x00000000 ///< Set owner to CPU
-
-// Rx Frame Descriptor Status
-#define EMAC_RXFD_RTSAS 0x0080 ///< Time Stamp Available
-#define EMAC_RXFD_RP 0x0040 ///< Runt Packet
-#define EMAC_RXFD_ALIE 0x0020 ///< Alignment Error
-#define EMAC_RXFD_RXGD 0x0010 ///< Receiving Good packet received
-#define EMAC_RXFD_PTLE 0x0008 ///< Packet Too Long Error
-#define EMAC_RXFD_CRCE 0x0002 ///< CRC Error
-#define EMAC_RXFD_RXINTR 0x0001 ///< Interrupt on receive
-
-// Tx Frame Descriptor's Control bits
-#define EMAC_TXFD_TTSEN 0x08 ///< Tx time stamp enable
-#define EMAC_TXFD_INTEN 0x04 ///< Tx interrupt enable
-#define EMAC_TXFD_CRCAPP 0x02 ///< Append CRC
-#define EMAC_TXFD_PADEN 0x01 ///< Padding mode enable
-
-// Tx Frame Descriptor Status
-#define EMAC_TXFD_TXINTR 0x0001 ///< Interrupt on Transmit
-#define EMAC_TXFD_DEF 0x0002 ///< Transmit deferred
-#define EMAC_TXFD_TXCP 0x0008 ///< Transmission Completion
-#define EMAC_TXFD_EXDEF 0x0010 ///< Exceed Deferral
-#define EMAC_TXFD_NCS 0x0020 ///< No Carrier Sense Error
-#define EMAC_TXFD_TXABT 0x0040 ///< Transmission Abort
-#define EMAC_TXFD_LC 0x0080 ///< Late Collision
-#define EMAC_TXFD_TXHA 0x0100 ///< Transmission halted
-#define EMAC_TXFD_PAU 0x0200 ///< Paused
-#define EMAC_TXFD_SQE 0x0400 ///< SQE error
-#define EMAC_TXFD_TTSAS 0x0800 ///< Time Stamp available
-
-/*@}*/ /* end of group NUC472_442_EMAC_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_EMAC_EXPORTED_TYPEDEF EMAC Exported Type Defines
- @{
-*/
-
-/** Tx/Rx buffer descriptor structure */
-typedef struct {
- uint32_t u32Status1; ///< Status word 1
- uint32_t u32Data; ///< Pointer to data buffer
- uint32_t u32Status2; ///< Status word 2
- uint32_t u32Next; ///< Pointer to next descriptor
- uint32_t u32Backup1; ///< For backup descriptor fields over written by time stamp
- uint32_t u32Backup2; ///< For backup descriptor fields over written by time stamp
-} EMAC_DESCRIPTOR_T;
-
-/** Tx/Rx buffer structure */
-typedef struct {
- uint8_t au8Buf[1520];
-} EMAC_FRAME_T;
-
-/*@}*/ /* end of group NUC472_442_EMAC_EXPORTED_TYPEDEF */
-
-// local variables
-static volatile EMAC_DESCRIPTOR_T rx_desc[EMAC_RX_DESC_SIZE];
-static volatile EMAC_FRAME_T rx_buf[EMAC_RX_DESC_SIZE];
-static volatile EMAC_DESCRIPTOR_T tx_desc[EMAC_TX_DESC_SIZE];
-static volatile EMAC_FRAME_T tx_buf[EMAC_TX_DESC_SIZE];
-
-
-static uint32_t u32CurrentTxDesc, u32NextTxDesc, u32CurrentRxDesc;
-static uint32_t s_u32EnableTs = 0;
-
-/** @addtogroup NUC472_442_EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
- @{
-*/
-
-/**
- * @brief Trigger EMAC Rx function
- * @param None
- * @return None
- */
-#define EMAC_TRIGGER_RX() do{EMAC->RXST = 0;}while(0)
-
-/**
- * @brief Trigger EMAC Tx function
- * @param None
- * @return None
- */
-#define EMAC_TRIGGER_TX() do{EMAC->TXST = 0;}while(0)
-
-/**
- * @brief Write PHY register
- * @param[in] u32Reg PHY register number
- * @param[in] u32Addr PHY address, this address is board dependent
- * @param[in] u32Data data to write to PHY register
- * @return None
- */
-static void EMAC_MdioWrite(uint32_t u32Reg, uint32_t u32Addr, uint32_t u32Data)
-{
- // Set data register
- EMAC->MIIMDAT = u32Data ;
- // Set PHY address, PHY register address, busy bit and write bit
- EMAC->MIIMCTL = u32Reg | (u32Addr << 8) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk;
- // Wait write complete by polling busy bit.
- while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
-
-}
-
-/**
- * @brief Read PHY register
- * @param[in] u32Reg PHY register number
- * @param[in] u32Addr PHY address, this address is board dependent
- * @return Value read from PHY register
- */
-static uint32_t EMAC_MdioRead(uint32_t u32Reg, uint32_t u32Addr)
-{
- // Set PHY address, PHY register address, busy bit
- EMAC->MIIMCTL = u32Reg | (u32Addr << EMAC_MIIMCTL_PHYADDR_Pos) | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
- // Wait read complete by polling busy bit
- while(EMAC->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
- // Get return data
- return EMAC->MIIMDAT;
-}
-
-
-/**
- * @brief Initialize PHY chip, check for the auto-negotiation result.
- * @param None
- * @return None
- */
-static void EMAC_PhyInit(void)
-{
- uint32_t reg;
-
- // Reset Phy Chip
- EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, PHY_CNTL_RESET_PHY);
-
- // Wait until reset complete
- while (1) {
- reg = EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) ;
- if ((reg & PHY_CNTL_RESET_PHY)==0)
- break;
- }
-
- if(!EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID) { // Cable not connected
- printf("Unplug\n..");
- EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
- EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
- return;
- }
- // Configure auto negotiation capability
- EMAC_MdioWrite(PHY_ANA_REG, EMAC_PHY_ADDR, PHY_ANA_DR100_TX_FULL |
- PHY_ANA_DR100_TX_HALF |
- PHY_ANA_DR10_TX_FULL |
- PHY_ANA_DR10_TX_HALF |
- PHY_ANA_IEEE_802_3_CSMA_CD);
- // Restart auto negotiation
- EMAC_MdioWrite(PHY_CNTL_REG, EMAC_PHY_ADDR, EMAC_MdioRead(PHY_CNTL_REG, EMAC_PHY_ADDR) | PHY_CNTL_RESTART_AN);
-
- // Wait for auto-negotiation complete
- while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_AN_COMPLETE));
-
- // Check link valid again. Some PHYs needs to check result after link valid bit set
- while(!(EMAC_MdioRead(PHY_STATUS_REG, EMAC_PHY_ADDR) & PHY_STATUS_LINK_VALID));
-
- // Check link partner capability
- reg = EMAC_MdioRead(PHY_ANLPA_REG, EMAC_PHY_ADDR) ;
- if (reg & PHY_ANLPA_DR100_TX_FULL) {
- printf("100F\n");
- EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
- EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
- } else if (reg & PHY_ANLPA_DR100_TX_HALF) {
- printf("100H\n");
- EMAC->CTL |= EMAC_CTL_OPMODE_Msk;
- EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
- } else if (reg & PHY_ANLPA_DR10_TX_FULL) {
- printf("10F\n");
- EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
- EMAC->CTL |= EMAC_CTL_FUDUP_Msk;
- } else {
- printf("10H\n");
- EMAC->CTL &= ~EMAC_CTL_OPMODE_Msk;
- EMAC->CTL &= ~EMAC_CTL_FUDUP_Msk;
- }
-}
-
-/**
- * @brief Initial EMAC Tx descriptors and get Tx descriptor base address
- * @param None
- * @return None
- */
-static void EMAC_TxDescInit(void)
-{
- uint32_t i;
-
- // Get Frame descriptor's base address.
- EMAC->TXDSA = (uint32_t)&tx_desc[0];
- u32NextTxDesc = u32CurrentTxDesc = (uint32_t)&tx_desc[0];
-
- for(i = 0; i < EMAC_TX_DESC_SIZE; i++) {
-
- if(s_u32EnableTs)
- tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN;
- else
- tx_desc[i].u32Status1 = EMAC_TXFD_PADEN | EMAC_TXFD_CRCAPP | EMAC_TXFD_INTEN | EMAC_TXFD_TTSEN;
-
- tx_desc[i].u32Data = (uint32_t)((uint32_t)&tx_buf[i]);
- tx_desc[i].u32Backup1 = tx_desc[i].u32Data;
- tx_desc[i].u32Status2 = 0;
- tx_desc[i].u32Next = (uint32_t)&tx_desc[(i + 1) % EMAC_TX_DESC_SIZE];
- tx_desc[i].u32Backup2 = tx_desc[i].u32Next;
-
- }
-
-}
-
-
-/**
- * @brief Initial EMAC Rx descriptors and get Rx descriptor base address
- * @param None
- * @return None
- */
-static void EMAC_RxDescInit(void)
-{
-
- uint32_t i;
-
- // Get Frame descriptor's base address.
- EMAC->RXDSA = (uint32_t)&rx_desc[0];
- u32CurrentRxDesc = (uint32_t)&rx_desc[0];
-
- for(i=0; i < EMAC_RX_DESC_SIZE; i++) {
- rx_desc[i].u32Status1 = EMAC_DESC_OWN_EMAC;
- rx_desc[i].u32Data = (uint32_t)((uint32_t)&rx_buf[i]);
- rx_desc[i].u32Backup1 = rx_desc[i].u32Data;
- rx_desc[i].u32Status2 = 0;
- rx_desc[i].u32Next = (uint32_t)&rx_desc[(i + 1) % EMAC_RX_DESC_SIZE];
- rx_desc[i].u32Backup2 = rx_desc[i].u32Next;
- }
-
-}
-
-/**
- * @brief Convert subsecond value to nano second
- * @param[in] subsec Subsecond value to be convert
- * @return Nano second
- */
-static uint32_t EMAC_Subsec2Nsec(uint32_t subsec)
-{
- // 2^31 subsec == 10^9 ns
- uint64_t i;
- i = 1000000000ll * subsec;
- i >>= 31;
- return(i);
-}
-
-/**
- * @brief Convert nano second to subsecond value
- * @param[in] nsec Nano second to be convert
- * @return Subsecond
- */
-static uint32_t EMAC_Nsec2Subsec(uint32_t nsec)
-{
- // 10^9 ns = 2^31 subsec
- uint64_t i;
- i = (1ll << 31) * nsec;
- i /= 1000000000;
- return(i);
-}
-
-
-/*@}*/ /* end of group NUC472_442_EMAC_EXPORTED_FUNCTIONS */
-
-
-
-/// @endcond HIDDEN_SYMBOLS
-
-
-/** @addtogroup NUC472_442_EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
- @{
-*/
-
-
-// Basic configuration functions
-/**
- * @brief Initialize EMAC interface, including descriptors, MAC address, and PHY.
- * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address
- * @return None
- * @note This API sets EMAC to work in RMII mode, but could configure to MII mode later with \ref EMAC_ENABLE_MII_INTF macro
- * @note This API configures EMAC to receive all broadcast and multicast packets, but could configure to other settings with
- * \ref EMAC_ENABLE_RECV_BCASTPKT, \ref EMAC_DISABLE_RECV_BCASTPKT, \ref EMAC_ENABLE_RECV_MCASTPKT, and \ref EMAC_DISABLE_RECV_MCASTPKT
- * @note Receive(RX) and transmit(TX) are not enabled yet, application must call \ref EMAC_ENABLE_RX and \ref EMAC_ENABLE_TX to
- * enable receive and transmit function.
- */
-void EMAC_Open(uint8_t *pu8MacAddr)
-{
- // Enable transmit and receive descriptor
- EMAC_TxDescInit();
- EMAC_RxDescInit();
-
- // Set the CAM Control register and the MAC address value
- EMAC_SetMacAddr(pu8MacAddr);
-
- // Configure the MAC interrupt enable register.
- EMAC->INTEN = EMAC_INTEN_RXIEN_Msk |
- EMAC_INTEN_TXIEN_Msk |
- EMAC_INTEN_RXGDIEN_Msk |
- EMAC_INTEN_TXCPIEN_Msk |
- EMAC_INTEN_RXBEIEN_Msk |
- EMAC_INTEN_TXBEIEN_Msk |
- EMAC_INTEN_RDUIEN_Msk |
- EMAC_INTEN_TSALMIEN_Msk |
- EMAC_INTEN_WOLIEN_Msk;
-
- // Configure the MAC control register.
- EMAC->CTL = EMAC_CTL_STRIPCRC_Msk |
- EMAC_CTL_RMIIEN_Msk |
- EMAC_CTL_RMIIRXCTL_Msk;
-
- //Accept packets for us and all broadcast and multicast packets
- EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk |
- EMAC_CAMCTL_AMP_Msk |
- EMAC_CAMCTL_ABP_Msk;
-
- EMAC_PhyInit();
-}
-
-/**
- * @brief This function stop all receive and transmit activity and disable MAC interface
- * @param None
- * @return None
- */
-
-void EMAC_Close(void)
-{
- EMAC->CTL |= EMAC_CTL_RST_Msk;
-}
-
-/**
- * @brief Set the device MAC address
- * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address
- * @return None
- */
-void EMAC_SetMacAddr(uint8_t *pu8MacAddr)
-{
- EMAC_EnableCamEntry(0, pu8MacAddr);
-
-}
-
-/**
- * @brief Fill a CAM entry for MAC address comparison.
- * @param[in] u32Entry MAC entry to fill. Entry 0 is used to store device MAC address, do not overwrite the setting in it.
- * @param[in] pu8MacAddr Pointer to uint8_t array holds MAC address
- * @return None
- */
-void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t *pu8MacAddr)
-{
- uint32_t u32Lsw, u32Msw;
-
- u32Lsw = (pu8MacAddr[4] << 24) |
- (pu8MacAddr[5] << 16);
- u32Msw = (pu8MacAddr[0] << 24)|
- (pu8MacAddr[1] << 16)|
- (pu8MacAddr[2] << 8)|
- pu8MacAddr[3];
-
- *(uint32_t volatile *)(&EMAC->CAM0M + u32Entry * 4) = u32Msw;
- *(uint32_t volatile *)(&EMAC->CAM0L + u32Entry * 4) = u32Lsw;
-
- EMAC->CAMEN |= (1 << u32Entry);
-}
-
-/**
- * @brief Disable a specified CAM entry
- * @param[in] u32Entry CAM entry to be disabled
- * @return None
- */
-void EMAC_DisableCamEntry(uint32_t u32Entry)
-{
- EMAC->CAMEN &= ~(1 << u32Entry);
-}
-
-// Receive functions
-/**
- * @brief Receive an Ethernet packet
- * @param[in] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
- * @param[in] pu32Size Received packet size (without 4 byte CRC).
- * @return Packet receive success or not
- * @retval 0 No packet available for receive
- * @retval 1 A packet is received
- * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
- */
-uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size)
-{
- EMAC_DESCRIPTOR_T *desc;
- uint32_t status, reg;
- uint32_t u32Count = 0;
-
- // Clear Rx interrupt flags
- reg = EMAC->INTSTS;
- EMAC->INTSTS = reg & 0xFFFF; // Clear all RX related interrupt status
-
- if (reg & EMAC_INTSTS_RXBEIF_Msk) {
- // Bus error occurred, this is usually a bad sign about software bug and will occur again...
- printf("RX bus error\n");
- } else {
-
- // Get Rx Frame Descriptor
- desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
-
- // If we reach last recv Rx descriptor, leave the loop
- if(EMAC->CRXDSA == (uint32_t)desc)
- return(0);
- if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) { // ownership=CPU
-
- status = desc->u32Status1 >> 16;
-
- // If Rx frame is good, process received frame
- if(status & EMAC_RXFD_RXGD) {
- // lower 16 bit in descriptor status1 stores the Rx packet length
- *pu32Size = desc->u32Status1 & 0xffff;
- memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size);
- u32Count = 1;
- } else {
- // Save Error status if necessary
- if (status & EMAC_RXFD_RP);
- if (status & EMAC_RXFD_ALIE);
- if (status & EMAC_RXFD_PTLE);
- if (status & EMAC_RXFD_CRCE);
- }
- }
- }
- return(u32Count);
-}
-
-/**
- * @brief Receive an Ethernet packet and the time stamp while it's received
- * @param[out] pu8Data Pointer to a buffer to store received packet (4 byte CRC removed)
- * @param[out] pu32Size Received packet size (without 4 byte CRC).
- * @param[out] pu32Sec Second value while packet sent
- * @param[out] pu32Nsec Nano second value while packet sent
- * @return Packet receive success or not
- * @retval 0 No packet available for receive
- * @retval 1 A packet is received
- * @note Return 0 doesn't guarantee the packet will be sent and received successfully.
- * @note Largest Ethernet packet is 1514 bytes after stripped CRC, application must give
- * a buffer large enough to store such packet
- */
-uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec)
-{
- EMAC_DESCRIPTOR_T *desc;
- uint32_t status, reg;
- uint32_t u32Count = 0;
-
- // Clear Rx interrupt flags
- reg = EMAC->INTSTS;
- EMAC->INTSTS = reg & 0xFFFF; // Clear all Rx related interrupt status
-
- if (reg & EMAC_INTSTS_RXBEIF_Msk) {
- // Bus error occurred, this is usually a bad sign about software bug and will occur again...
- printf("RX bus error\n");
- } else {
-
- // Get Rx Frame Descriptor
- desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
-
- // If we reach last recv Rx descriptor, leave the loop
- if(EMAC->CRXDSA == (uint32_t)desc)
- return(0);
- if ((desc->u32Status1 | EMAC_DESC_OWN_EMAC) != EMAC_DESC_OWN_EMAC) { // ownership=CPU
-
- status = desc->u32Status1 >> 16;
-
- // If Rx frame is good, process received frame
- if(status & EMAC_RXFD_RXGD) {
- // lower 16 bit in descriptor status1 stores the Rx packet length
- *pu32Size = desc->u32Status1 & 0xffff;
- memcpy(pu8Data, (uint8_t *)desc->u32Backup1, *pu32Size);
-
- *pu32Sec = desc->u32Next; // second stores in descriptor's NEXT field
- *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); // Sub nano second store in DATA field
-
- u32Count = 1;
- } else {
- // Save Error status if necessary
- if (status & EMAC_RXFD_RP);
- if (status & EMAC_RXFD_ALIE);
- if (status & EMAC_RXFD_PTLE);
- if (status & EMAC_RXFD_CRCE);
- }
- }
- }
- return(u32Count);
-}
-
-/**
- * @brief Clean up process after a packet is received
- * @param None
- * @return None
- * @details EMAC Rx interrupt service routine \b must call this API to release the resource use by receive process
- * @note Application can only call this function once every time \ref EMAC_RecvPkt or \ref EMAC_RecvPktTS returns 1
- */
-void EMAC_RecvPktDone(void)
-{
- EMAC_DESCRIPTOR_T *desc;
- // Get Rx Frame Descriptor
- desc = (EMAC_DESCRIPTOR_T *)u32CurrentRxDesc;
-
- // restore descriptor link list and data pointer they will be overwrite if time stamp enabled
- desc->u32Data = desc->u32Backup1;
- desc->u32Next = desc->u32Backup2;
-
- // Change ownership to DMA for next use
- desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
-
- // Get Next Frame Descriptor pointer to process
- desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
-
- // Save last processed Rx descriptor
- u32CurrentRxDesc = (uint32_t)desc;
-
- EMAC_TRIGGER_RX();
-}
-
-// Transmit functions
-
-/**
- * @brief Send an Ethernet packet
- * @param[in] pu8Data Pointer to a buffer holds the packet to transmit
- * @param[in] u32Size Packet size (without 4 byte CRC).
- * @return Packet transmit success or not
- * @retval 0 Transmit failed due to descriptor unavailable.
- * @retval 1 Packet is copied to descriptor and triggered to transmit.
- * @note Return 1 doesn't guarantee the packet will be sent and received successfully.
- */
-uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size)
-{
- EMAC_DESCRIPTOR_T *desc;
- uint32_t status;
-
- // Get Tx frame descriptor & data pointer
- desc = (EMAC_DESCRIPTOR_T *)u32NextTxDesc;
-
- status = desc->u32Status1;
-
- // Check descriptor ownership
- if((status & EMAC_DESC_OWN_EMAC))
- return(0);
-
- memcpy((uint8_t *)desc->u32Data, pu8Data, u32Size);
-
- // Set Tx descriptor transmit byte count
- desc->u32Status2 = u32Size;
-
- // Change descriptor ownership to EMAC
- desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
-
- // Get next Tx descriptor
- u32NextTxDesc = (uint32_t)(desc->u32Next);
-
- // Trigger EMAC to send the packet
- EMAC_TRIGGER_TX();
-
- return(1);
-}
-
-
-/**
- * @brief Clean up process after packet(s) are sent
- * @param None
- * @return Number of packet sent between two function calls
- * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDoneTS to
- * release the resource use by transmit process
- */
-uint32_t EMAC_SendPktDone(void)
-{
- EMAC_DESCRIPTOR_T *desc;
- uint32_t status, reg;
- uint32_t last_tx_desc;
- uint32_t u32Count = 0;
-
- reg = EMAC->INTSTS;
- // Clear Tx interrupt flags
- EMAC->INTSTS = reg & (0xFFFF0000 & ~EMAC_INTSTS_TSALMIF_Msk);
-
-
- if (reg & EMAC_INTSTS_TXBEIF_Msk) {
- // Bus error occurred, this is usually a bad sign about software bug and will occur again...
- printf("TX bus error\n");
- } else {
- // Process the descriptor(s).
- last_tx_desc = EMAC->CTXDSA ;
- // Get our first descriptor to process
- desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc;
- do {
- // Descriptor ownership is still EMAC, so this packet haven't been send.
- if(desc->u32Status1 & EMAC_DESC_OWN_EMAC)
- break;
- // Get Tx status stored in descriptor
- status = desc->u32Status2 >> 16;
- if (status & EMAC_TXFD_TXCP) {
- u32Count++;
- } else {
- // Do nothing here on error.
- if (status & EMAC_TXFD_TXABT);
- if (status & EMAC_TXFD_DEF);
- if (status & EMAC_TXFD_PAU);
- if (status & EMAC_TXFD_EXDEF);
- if (status & EMAC_TXFD_NCS);
- if (status & EMAC_TXFD_SQE);
- if (status & EMAC_TXFD_LC);
- if (status & EMAC_TXFD_TXHA);
- }
-
- // restore descriptor link list and data pointer they will be overwrite if time stamp enabled
- desc->u32Data = desc->u32Backup1;
- desc->u32Next = desc->u32Backup2;
- // go to next descriptor in link
- desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
- } while (last_tx_desc != (uint32_t)desc); // If we reach last sent Tx descriptor, leave the loop
- // Save last processed Tx descriptor
- u32CurrentTxDesc = (uint32_t)desc;
- }
- return(u32Count);
-}
-
-/**
- * @brief Clean up process after a packet is sent, and get the time stamp while packet is sent
- * @param[in] pu32Sec Second value while packet sent
- * @param[in] pu32Nsec Nano second value while packet sent
- * @return If a packet sent successfully
- * @retval 0 No packet sent successfully, and the value in *pu32Sec and *pu32Nsec are meaningless
- * @retval 1 A packet sent successfully, and the value in *pu32Sec and *pu32Nsec is the time stamp while packet sent
- * @details EMAC Tx interrupt service routine \b must call this API or \ref EMAC_SendPktDone to
- * release the resource use by transmit process
- */
-uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec)
-{
-
- EMAC_DESCRIPTOR_T *desc;
- uint32_t status, reg;
- uint32_t u32Count = 0;
-
- reg = EMAC->INTSTS;
- // Clear Tx interrupt flags
- EMAC->INTSTS = reg & (0xFFFF0000 & ~EMAC_INTSTS_TSALMIF_Msk);
-
-
- if (reg & EMAC_INTSTS_TXBEIF_Msk) {
- // Bus error occurred, this is usually a bad sign about software bug and will occur again...
- printf("TX bus error\n");
- } else {
- // Process the descriptor.
- // Get our first descriptor to process
- desc = (EMAC_DESCRIPTOR_T *) u32CurrentTxDesc;
-
- // Descriptor ownership is still EMAC, so this packet haven't been send.
- if(desc->u32Status1 & EMAC_DESC_OWN_EMAC)
- return(0);
- // Get Tx status stored in descriptor
- status = desc->u32Status2 >> 16;
- if (status & EMAC_TXFD_TXCP) {
- u32Count = 1;
- *pu32Sec = desc->u32Next; // second stores in descriptor's NEXT field
- *pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); // Sub nano second store in DATA field
- } else {
- // Do nothing here on error.
- if (status & EMAC_TXFD_TXABT);
- if (status & EMAC_TXFD_DEF);
- if (status & EMAC_TXFD_PAU);
- if (status & EMAC_TXFD_EXDEF);
- if (status & EMAC_TXFD_NCS);
- if (status & EMAC_TXFD_SQE);
- if (status & EMAC_TXFD_LC);
- if (status & EMAC_TXFD_TXHA);
- }
-
- // restore descriptor link list and data pointer they will be overwrite if time stamp enabled
- desc->u32Data = desc->u32Backup1;
- desc->u32Next = desc->u32Backup2;
- // go to next descriptor in link
- desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
-
- // Save last processed Tx descriptor
- u32CurrentTxDesc = (uint32_t)desc;
- }
-
- return(u32Count);
-}
-
-// IEEE 1588 functions
-/**
- * @brief Enable IEEE1588 time stamp function and set current time
- * @param[in] u32Sec Second value
- * @param[in] u32Nsec Nano second value
- * @return None
- */
-void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec)
-{
- double f;
- uint32_t reg;
- EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
- EMAC->UPDSEC = u32Sec; // Assume current time is 0 sec + 0 nano sec
- EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
-
- // PTP source clock is 84MHz (Real chip using PLL). Each tick is 11.90ns
- // Assume we want to set each tick to 100ns.
- // Increase register = (100 * 2^31) / (10^9) = 214.71 =~ 215 = 0xD7
- // Addend register = 2^32 * tick_freq / (84MHz), where tick_freq = (2^31 / 215) MHz
- // From above equation, addend register = 2^63 / (84M * 215) ~= 510707200 = 0x1E70C600
- // So:
- // EMAC->TSIR = 0xD7;
- // EMAC->TSAR = 0x1E70C600;
- f = (100.0 * 2147483648.0) / (1000000000.0) + 0.5;
- EMAC->TSINC = (reg = (uint32_t)f);
- f = (double)9223372036854775808.0 / ((double)(CLK_GetHCLKFreq()) * (double)reg);
- EMAC->TSADDEND = (uint32_t)f;
- EMAC->TSCTL |= (EMAC_TSCTL_TSUPDATE_Msk | EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk); // Fine update
-}
-
-/**
- * @brief Disable IEEE1588 time stamp function
- * @param None
- * @return None
- */
-void EMAC_DisableTS(void)
-{
- EMAC->TSCTL = 0;
-}
-
-/**
- * @brief Get current time stamp
- * @param[out] pu32Sec Current second value
- * @param[out] pu32Nsec Current nano second value
- * @return None
- */
-void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec)
-{
- // Must read TSLSR firstly. Hardware will preserve TSMSR value at the time TSLSR read.
- *pu32Nsec = EMAC_Subsec2Nsec(EMAC->TSSUBSEC);
- *pu32Sec = EMAC->TSSEC;
-}
-
-/**
- * @brief Set current time stamp
- * @param[in] u32Sec Second value
- * @param[in] u32Nsec Nano second value
- * @return None
- */
-void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec)
-{
- // Disable time stamp counter before update time value (clear EMAC_TSCTL_TSIEN_Msk)
- EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;
- EMAC->UPDSEC = u32Sec;
- EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
- EMAC->TSCTL |= (EMAC_TSCTL_TSIEN_Msk | EMAC_TSCTL_TSMODE_Msk);
-
-}
-
-/**
- * @brief Enable alarm function and set alarm time
- * @param[in] u32Sec Second value to trigger alarm
- * @param[in] u32Nsec Nano second value to trigger alarm
- * @return None
- */
-void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec)
-{
-
- EMAC->ALMSEC = u32Sec;
- EMAC->ALMSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
- EMAC->TSCTL |= EMAC_TSCTL_TSALMEN_Msk;
-
-}
-
-/**
- * @brief Disable alarm function
- * @param None
- * @return None
- */
-void EMAC_DisableAlarm(void)
-{
-
- EMAC->TSCTL &= ~EMAC_TSCTL_TSALMEN_Msk;
-
-}
-
-/**
- * @brief Add a offset to current time
- * @param[in] u32Neg Offset is negative value (u32Neg == 1) or positive value (u32Neg == 0).
- * @param[in] u32Sec Second value to add to current time
- * @param[in] u32Nsec Nano second value to add to current time
- * @return None
- */
-void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec)
-{
- EMAC->UPDSEC = u32Sec;
- EMAC->UPDSUBSEC = EMAC_Nsec2Subsec(u32Nsec);
- if(u32Neg)
- EMAC->UPDSUBSEC |= BIT31; // Set bit 31 indicates this is a negative value
-
- EMAC->TSCTL |= EMAC_TSCTL_TSUPDATE_Msk;
-
-}
-
-
-/*@}*/ /* end of group NUC472_442_EMAC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_EMAC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_emac.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,194 +0,0 @@
-/**************************************************************************//**
- * @file emac.h
- * @version V1.00
- * $Revision: 9 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 EMAC driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __EMAC_H__
-#define __EMAC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EMAC_Driver EMAC Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
- @{
-*/
-
-#define EMAC_PHY_ADDR 1 ///< PHY address, this address is board dependent
-
-#define EMAC_RX_DESC_SIZE 4 ///< Number of Rx Descriptors, should be 2 at least
-#define EMAC_TX_DESC_SIZE 4 ///< Number of Tx Descriptors, should be 2 at least
-
-
-/*@}*/ /* end of group NUC472_442_EMAC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions
- @{
-*/
-
-
-/**
- * @brief Enable EMAC Tx function
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk)
-
-
-/**
- * @brief Enable EMAC Rx function
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0)
-
-/**
- * @brief Disable EMAC Tx function
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk)
-
-
-/**
- * @brief Disable EMAC Rx function
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk)
-
-/**
- * @brief Enable EMAC Magic Packet Wakeup function
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk)
-
-
-/**
- * @brief Disable EMAC Magic Packet Wakeup function
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk)
-
-/**
- * @brief Enable EMAC MII interface
- * @param None
- * @return None
- * @details After calling \ref EMAC_Open, EMAC use RMII interface by default, but can switch to
- * MII interface by calling this macro
- * \hideinitializer
- */
-#define EMAC_ENABLE_MII_INTF() (EMAC->CTL &= ~(EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk))
-
-/**
- * @brief Enable EMAC to receive broadcast packets
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk)
-
-/**
- * @brief Disable EMAC to receive broadcast packets
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk)
-
-/**
- * @brief Enable EMAC to receive multicast packets
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk)
-
-/**
- * @brief Disable EMAC Magic Packet Wakeup function
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk)
-
-/**
- * @brief Check if EMAC time stamp alarm interrupt occurred or not
- * @param None
- * @return If time stamp alarm interrupt occurred or not
- * @retval 0 Alarm interrupt does not occur
- * @retval 1 Alarm interrupt occurred
- * \hideinitializer
- */
-#define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0)
-
-/**
- * @brief Clear EMAC time stamp alarm interrupt flag
- * @param None
- * @return None
- * \hideinitializer
- */
-#define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk)
-
-
-void EMAC_Open(uint8_t *pu8MacAddr);
-void EMAC_Close(void);
-void EMAC_SetMacAddr(uint8_t *pu8MacAddr);
-void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t *pu8MacAddr);
-void EMAC_DisableCamEntry(uint32_t u32Entry);
-
-uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size);
-uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec);
-void EMAC_RecvPktDone(void);
-
-uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size);
-uint32_t EMAC_SendPktDone(void);
-uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec);
-
-void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec);
-void EMAC_DisableTS(void);
-void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec);
-void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec);
-void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec);
-void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec);
-void EMAC_DisableAlarm(void);
-
-
-
-/*@}*/ /* end of group NUC472_442_EMAC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_EMAC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__EMAC_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_fmc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,432 +0,0 @@
-/**************************************************************************//**
- * @file fmc.c
- * @version V1.10
- * $Revision: 16 $
- * $Date: 14/10/06 11:57a $
- * @brief NUC472/NUC442 FMC driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-//* Includes ------------------------------------------------------------------*/
-#include <stdio.h>
-#include "NUC472_442.h"
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_FMC_Driver FMC Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
- @{
-*/
-
-
-/**
- * @brief Set boot from APROM or LDROM of next software reset.
- * @param[in] i32BootSrc Next software boot selection.
- * - \ref IS_BOOT_FROM_LDROM
- * - \ref IS_BOOT_FROM_APROM
- * @return None
- */
-void FMC_SetBootSource (int32_t i32BootSrc)
-{
- if (i32BootSrc == 1)
- FMC->ISPCTL |= FMC_ISPCTL_BS_Msk;
- else
- FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;
-}
-
-
-/**
- * @brief Disable FMC ISP function.
- * @return None
- */
-void FMC_Close(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
-}
-
-
-/**
- * @brief Disable ISP erase/program APROM function.
- * @return None
- */
-void FMC_DisableAPUpdate(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk;
-}
-
-
-/**
- * @brief Disable ISP erase/program User Configuration function.
- * @return None
- */
-void FMC_DisableConfigUpdate(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk;
-}
-
-
-/**
- * @brief Disable ISP erase/program LDROM function.
- * @return None
- */
-void FMC_DisableLDUpdate(void)
-{
- FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk;
-}
-
-
-/**
- * @brief Enable ISP erase/program APROM function.
- * @return None
- */
-void FMC_EnableAPUpdate(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk;
-}
-
-
-/**
- * @brief Enable ISP erase/program User Configuration function.
- * @return None
- */
-void FMC_EnableConfigUpdate(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk;
-}
-
-
-/**
- * @brief Enable ISP erase/program LDROM function.
- * @return None
- */
-void FMC_EnableLDUpdate(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk;
-}
-
-
-/**
- * @brief Erase a page. The page size is 2048 bytes.
- * @param[in] u32PageAddr Flash page address. Must be a 2048-byte aligned address.
- * @return Success or not.
- * @retval 0 Success
- * @retval -1 Erase failed
- */
-int32_t FMC_Erase(uint32_t u32PageAddr)
-{
- FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
- FMC->ISPADDR = u32PageAddr;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
-
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-
- if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
- FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
- return -1;
- }
- return 0;
-}
-
-
-/**
- * @brief Get the current boot source.
- * @return The current boot source.
- * @retval 0 Is boot from APROM.
- * @retval 1 Is boot from LDROM.
- */
-int32_t FMC_GetBootSource (void)
-{
- if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
- return 1;
- else
- return 0;
-}
-
-
-/**
- * @brief Enable FMC ISP function
- * @return None
- */
-void FMC_Open(void)
-{
- FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
-}
-
-
-/**
- * @brief Execute ISP command to read a word from flash.
- * @param[in] u32Addr Address of the flash location to be read.
- * It must be a word aligned address.
- * @return The word data read from specified flash address.
- */
-uint32_t FMC_Read(uint32_t u32Addr)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ;
- FMC->ISPADDR = u32Addr;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
-
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-
- return FMC->ISPDAT;
-}
-
-
-/**
- * @brief Execute ISP 64-bits read command to read two words from flash.
- * @param[in] u32Addr Flash word address. Must be a double word aligned address.
- * @param[out] u32Data0 The first word read from flash.
- * @param[out] u32Data1 The second word read from flash.
- * @return None
- */
-void FMC_Read_64(uint32_t u32Addr, uint32_t *u32Data0, uint32_t *u32Data1)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_64;
- FMC->ISPADDR = u32Addr;
- FMC->ISPDAT = 0x0;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
-
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-
- *u32Data0 = FMC->MPDAT0;
- *u32Data1 = FMC->MPDAT1;
-}
-
-
-/**
- * @brief Read company ID.
- * @return The company ID.
- */
-uint32_t FMC_ReadCID(void)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_CID;
- FMC->ISPADDR = 0x0;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
- return FMC->ISPDAT;
-}
-
-
-/**
- * @brief Read device ID.
- * @return The device ID.
- */
-uint32_t FMC_ReadDID(void)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_DID;
- FMC->ISPADDR = 0;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
- return FMC->ISPDAT;
-}
-
-
-/**
- * @brief Read product ID.
- * @return The product ID.
- */
-uint32_t FMC_ReadPID(void)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_DID;
- FMC->ISPADDR = 0x04;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
- return FMC->ISPDAT;
-}
-
-
-/**
- * @brief This function reads one of the four UCID.
- * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
- * @return The UCID.
- */
-uint32_t FMC_ReadUCID(uint32_t u32Index)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_UID;
- FMC->ISPADDR = (0x04 * u32Index) + 0x10;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
-
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-
- return FMC->ISPDAT;
-}
-
-
-/**
- * @brief This function reads one of the three UID.
- * @param[in] u32Index Index of the UID to read. u32Index must be 0, 1, or 2.
- * @return The UID.
- */
-uint32_t FMC_ReadUID(uint32_t u32Index)
-{
- FMC->ISPCMD = FMC_ISPCMD_READ_UID;
- FMC->ISPADDR = 0x04 * u32Index;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
-
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-
- return FMC->ISPDAT;
-}
-
-
-/**
- * @brief Get the base address of Data Flash if enabled.
- * @return Base address of Data Flash
- */
-uint32_t FMC_ReadDataFlashBaseAddr(void)
-{
- return FMC->DFBA;
-}
-
-
-/**
- * @brief This function will force re-map assigned flash page to CPU address 0x0.
- * @param[in] u32PageAddr Address of the page to be mapped to CPU address 0x0.
- * @return None
- */
-void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
-{
- FMC->ISPCMD = FMC_ISPCMD_VECMAP;
- FMC->ISPADDR = u32PageAddr;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-}
-
-
-/**
- * @brief Execute ISP command to program a word to flash.
- * @param[in] u32Addr Address of the flash location to be programmed.
- * It must be a word aligned address.
- * @param[out] u32Data The word data to be programmed.
- * @return None
- */
-void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
-{
- FMC->ISPCMD = FMC_ISPCMD_WRITE;
- FMC->ISPADDR = u32Addr;
- FMC->ISPDAT = u32Data;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-}
-
-
-/**
- * @brief Execute ISP 64-bits write command to program two words to flash.
- * @param[in] u32Addr Destination address. It must be double word aligned.
- * @param[in] u32Data0 First word data to be written.
- * @param[in] u32Data1 Second word data to be written.
- * @return None
- */
-void FMC_Write_64(uint32_t u32Addr, uint32_t u32Data0, uint32_t u32Data1)
-{
- FMC->ISPCMD = FMC_ISPCMD_WRITE_64;
- FMC->ISPADDR = u32Addr;
- FMC->MPDAT0 = u32Data0;
- FMC->MPDAT1 = u32Data0;
- FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
- while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
-}
-
-
-/**
- * @brief CRC8 Calculator
- * @param[in] au32Data CRC8 input data words.
- * @param[in] i32Count Number of words in au32Data[].
- * @return The CRC8 value.
- */
-uint32_t FMC_CRC8(uint32_t au32Data[], int i32Count)
-{
- int i32ByteIdx;
- uint8_t i, u8Cnt, u8InData;
- uint8_t au8CRC[4] = { 0xff, 0xff, 0xff, 0xff };
-
- for (i32ByteIdx = 0; i32ByteIdx < 4; i32ByteIdx++) {
- for (u8Cnt = 0; u8Cnt < i32Count; u8Cnt++) {
- for (i = 0x80; i != 0; i /= 2) {
- if ((au8CRC[i32ByteIdx] & 0x80)!=0) {
- au8CRC[i32ByteIdx] *= 2;
- au8CRC[i32ByteIdx] ^= 7;
- } else
- au8CRC[i32ByteIdx] *= 2;
-
- u8InData = (au32Data[u8Cnt] >> (i32ByteIdx * 8)) & 0xff;
-
- if ((u8InData & i) != 0)
- au8CRC[i32ByteIdx]^=0x7;
- }
- }
- }
- return (au8CRC[0] | au8CRC[1] << 8 | au8CRC[2] << 16 | au8CRC[3] << 24);
-}
-
-
-/**
- * @brief Read the User Configuration words.
- * @param[out] u32Config: The word array to store words read from flash.
- * @param[in] u32Count: Maximum length of u32Config.
- * @return Success or not.
- * @retval 0 Success
- * @retval -1 User Configuration CRC check error
- */
-int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
-{
- int i;
-
- for (i = 0; i < u32Count; i++) {
- u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i*4);
- }
-
- if (FMC->ISPSTS & FMC_ISPSTS_CFGCRCF_Msk)
- return -1;
-
- return 0;
-}
-
-
-/**
- * @brief Write User Configuration
- * @param[in] u32Config The word array to store data. MUST be a four word array.
- * @param[in] u32Count MUST be 4.
- * @return Success or not.
- * @retval 0 Success
- * @retval -1 Failed
- */
-int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
-{
- uint32_t i, u32CRC, u32Data;
-
- FMC_Erase(FMC_CONFIG_BASE);
-
- u32CRC = FMC_CRC8(u32Config, 3);
-
- for (i = 0; i < 4; i++) {
- FMC_Write(FMC_CONFIG_BASE + i * 4, (i < 3) ? u32Config[i] : u32CRC);
- }
-
- for (i = 0; i < 4; i++) {
- u32Data = FMC_Read(FMC_CONFIG_BASE + i * 4);
-
- if (u32Data != ((i < 3) ? u32Config[i] : u32CRC))
- return -1;
- }
- return 0;
-}
-
-
-/*@}*/ /* end of group NUC472_442_FMC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_FMC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_fmc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,219 +0,0 @@
-/**************************************************************************//**
- * @file fmc.h
- * @version V1.10
- * $Revision: 11 $
- * $Date: 14/10/06 1:47p $
- * @brief NUC472/NUC442 Flash Memory Controller Driver Header File
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *
- ******************************************************************************/
-#ifndef __FMC_H__
-#define __FMC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_FMC_Driver FMC Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_FMC_EXPORTED_CONSTANTS FMC Exported Constants
- @{
-*/
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define Base Address */
-/*---------------------------------------------------------------------------------------------------------*/
-#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address \hideinitializer */
-#define FMC_APROM_END 0x00080000UL /*!< APROM End Address \hideinitializer */
-#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address \hideinitializer */
-#define FMC_LDROM_END 0x00104000UL /*!< LDROM End Address \hideinitializer */
-#define FMC_CONFIG_BASE 0x00300000UL /*!< User Configuration Address \hideinitializer */
-
-#define FMC_FLASH_PAGE_SIZE 0x800 /*!< Flash Page Size (2 Kbytes) \hideinitializer */
-#define FMC_LDROM_SIZE 0x4000 /*!< LDROM Size (16 Kbytes) \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* ISPCMD constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read flash word \hideinitializer */
-#define FMC_ISPCMD_READ_64 0x40 /*!< ISP Command: Read flash double word \hideinitializer */
-#define FMC_ISPCMD_WRITE 0x21 /*!< ISP Command: Write flash word \hideinitializer */
-#define FMC_ISPCMD_WRITE_64 0x61 /*!< ISP Command: Write flash double word \hideinitializer */
-#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash \hideinitializer */
-#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID \hideinitializer */
-#define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID \hideinitializer */
-#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID \hideinitializer */
-#define ISP_ISPCMD_MULTI_WRITE 0x27 /*!< ISP Command: Multiple program \hideinitializer */
-#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Vector Page Remap \hideinitializer */
-
-#define IS_BOOT_FROM_APROM 0 /*!< Is booting from APROM \hideinitializer */
-#define IS_BOOT_FROM_LDROM 1 /*!< Is booting from LDROM \hideinitializer */
-
-
-/*@}*/ /* end of group NUC472_442_FMC_EXPORTED_CONSTANTS */
-
-
-
-/** @addtogroup NUC472_442_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
- @{
-*/
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Macros */
-/*---------------------------------------------------------------------------------------------------------*/
-
-/**
- * @brief This macro selects booting from APROM.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk)
-
-/**
- * @brief This macro selects booting from LDROM.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk)
-
-/**
- * @brief This macro enables APROM update function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk)
-
-/**
- * @brief This macro disables APROM update function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)
-
-/**
- * @brief This macro enables User Configuration update function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk)
-
-/**
- * @brief This macro disables User Configuration update function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk)
-
-/**
- * @brief This macro enables LDROM update function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk)
-
-/**
- * @brief This macro disables LDROM update function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)
-
-/**
- * @brief This macro enables ISP function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function \hideinitializer */
-
-/**
- * @brief This macro disables ISP function.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)
-
-/**
- * @brief This macro gets ISP fail flag value.
- * @param None
- * @return ISP fail flag value.
- * \hideinitializer
- */
-#define FMC_GET_FAIL_FLAG() (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
-
-/**
- * @brief This macro clears ISP fail flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define FMC_CLR_FAIL_FLAG() (FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk) /*!< Clear ISP fail flag \hideinitializer */
-
-
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Functions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-extern void FMC_SetBootSource(int32_t i32BootSrc);
-extern void FMC_Close(void);
-extern void FMC_DisableAPUpdate(void);
-extern void FMC_DisableConfigUpdate(void);
-extern void FMC_DisableLDUpdate(void);
-extern void FMC_EnableAPUpdate(void);
-extern void FMC_EnableConfigUpdate(void);
-extern void FMC_EnableLDUpdate(void);
-extern int32_t FMC_Erase(uint32_t u32PageAddr);
-extern int32_t FMC_GetBootSource(void);
-extern void FMC_Open(void);
-extern uint32_t FMC_Read(uint32_t u32Addr);
-extern void FMC_Read_64(uint32_t u32Addr, uint32_t *u32Data0, uint32_t *u32Data1);
-extern uint32_t FMC_ReadCID(void);
-extern uint32_t FMC_ReadDID(void);
-extern uint32_t FMC_ReadPID(void);
-extern uint32_t FMC_ReadUCID(uint32_t u32Index);
-extern uint32_t FMC_ReadUID(uint32_t u32Index);
-extern uint32_t FMC_ReadDataFlashBaseAddr(void);
-extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
-extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
-extern void FMC_Write_64(uint32_t u32Addr, uint32_t u32Data0, uint32_t u32Data1);
-extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
-extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
-extern uint32_t FMC_CRC8(uint32_t au32Data[], int i32Count);
-
-
-/*@}*/ /* end of group NUC472_442_FMC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_FMC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_gpio.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/**************************************************************************//**
- * @file gpio.c
- * @version V1.00
- * $Revision: 9 $
- * $Date: 14/10/06 11:47a $
- * @brief NUC472/NUC442 GPIO driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_GPIO_Driver GPIO Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
- @{
-*/
-
-/**
- * @brief Set GPIO operation mode
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- * @param[in] u32Mode Operation mode. \ref GPIO_MODE_INPUT, \ref GPIO_MODE_OUTPUT, \ref GPIO_MODE_OPEN_DRAIN, \ref GPIO_MODE_QUASI
- *
- * @return None
- *
- * @details This function is used to set specified GPIO operation mode.
- */
-void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode)
-{
- uint32_t i;
-
- for (i=0; i<GPIO_PIN_MAX; i++) {
- if (u32PinMask & (1 << i)) {
- gpio->MODE = (gpio->MODE & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
- }
- }
-}
-
-/**
- * @brief Enable GPIO interrupt
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
- * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
- * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, GPIO_INT_LOW
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs)
-{
- gpio->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
- gpio->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
-}
-
-
-/**
- * @brief Disable GPIO interrupt
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
- *
- * @return None
- *
- * @details This function is used to disable specified GPIO pin interrupt.
- */
-void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin)
-{
- gpio->INTTYPE &= ~(1UL << u32Pin);
- gpio->INTEN &= ~((0x00010001UL) << u32Pin);
-}
-
-
-
-/*@}*/ /* end of group NUC472_442_GPIO_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_GPIO_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_gpio.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,509 +0,0 @@
-/**************************************************************************//**
- * @file gpio.h
- * @version V1.00
- * $Revision: 12 $
- * $Date: 14/10/06 11:46a $
- * @brief NUC472/NUC442 GPIO driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __GPIO_H__
-#define __GPIO_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_GPIO_Driver GPIO Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
- @{
-*/
-#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* MODE Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
-#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
-#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
-#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* GPIO Interrupt Type Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
-#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
-#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
-#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
-#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* IMD Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_IMD_EDGE 0UL /*!< IMD Setting for Edge Trigger Mode */
-#define GPIO_IMD_LEVEL 1UL /*!< IMD Setting for Edge Level Mode */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* DBCTL Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< DBCTL setting for all IO pins edge detection circuit is always active after reset */
-#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
-
-#define GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL /*!< DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
-#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< DBCTL setting for de-bounce counter clock source is the internal HCLK */
-
-#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< DBCTL setting for sampling cycle = 1 clocks */
-#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< DBCTL setting for sampling cycle = 2 clocks */
-#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< v setting for sampling cycle = 4 clocks */
-#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< DBCTL setting for sampling cycle = 8 clocks */
-#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< DBCTL setting for sampling cycle = 16 clocks */
-#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< DBCTL setting for sampling cycle = 32 clocks */
-#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< DBCTL setting for sampling cycle = 64 clocks */
-#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< DBCTL setting for sampling cycle = 128 clocks */
-#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< DBCTL setting for sampling cycle = 256 clocks */
-#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< DBCTL setting for sampling cycle = 512 clocks */
-#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< DBCTL setting for sampling cycle = 1024 clocks */
-#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< DBCTL setting for sampling cycle = 2048 clocks */
-#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< DBCTL setting for sampling cycle = 4096 clocks */
-#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< DBCTL setting for sampling cycle = 8192 clocks */
-#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< DBCTL setting for sampling cycle = 16384 clocks */
-#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< DBCTL setting for sampling cycle = 32768 clocks */
-
-/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
- * Example 1:
- *
- * PA0 = 1;
- *
- * It is used to set PA0 to high;
- *
- * Example 2:
- *
- * if (PA0)
- * PA0 = 0;
- *
- * If PA0 pin status is high, then set PA0 data output to low.
- */
-#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
-#define PA0 GPIO_PIN_ADDR(0, 0) /*!< Specify PA0 Pin Data Input/Output */
-#define PA1 GPIO_PIN_ADDR(0, 1) /*!< Specify PA1 Pin Data Input/Output */
-#define PA2 GPIO_PIN_ADDR(0, 2) /*!< Specify PA2 Pin Data Input/Output */
-#define PA3 GPIO_PIN_ADDR(0, 3) /*!< Specify PA3 Pin Data Input/Output */
-#define PA4 GPIO_PIN_ADDR(0, 4) /*!< Specify PA4 Pin Data Input/Output */
-#define PA5 GPIO_PIN_ADDR(0, 5) /*!< Specify PA5 Pin Data Input/Output */
-#define PA6 GPIO_PIN_ADDR(0, 6) /*!< Specify PA6 Pin Data Input/Output */
-#define PA7 GPIO_PIN_ADDR(0, 7) /*!< Specify PA7 Pin Data Input/Output */
-#define PA8 GPIO_PIN_ADDR(0, 8) /*!< Specify PA8 Pin Data Input/Output */
-#define PA9 GPIO_PIN_ADDR(0, 9) /*!< Specify PA9 Pin Data Input/Output */
-#define PA10 GPIO_PIN_ADDR(0, 10) /*!< Specify PA10 Pin Data Input/Output */
-#define PA11 GPIO_PIN_ADDR(0, 11) /*!< Specify PA11 Pin Data Input/Output */
-#define PA12 GPIO_PIN_ADDR(0, 12) /*!< Specify PA12 Pin Data Input/Output */
-#define PA13 GPIO_PIN_ADDR(0, 13) /*!< Specify PA13 Pin Data Input/Output */
-#define PA14 GPIO_PIN_ADDR(0, 14) /*!< Specify PA14 Pin Data Input/Output */
-#define PA15 GPIO_PIN_ADDR(0, 15) /*!< Specify PA15 Pin Data Input/Output */
-
-#define PB0 GPIO_PIN_ADDR(1, 0) /*!< Specify PB0 Pin Data Input/Output */
-#define PB1 GPIO_PIN_ADDR(1, 1) /*!< Specify PB1 Pin Data Input/Output */
-#define PB2 GPIO_PIN_ADDR(1, 2) /*!< Specify PB2 Pin Data Input/Output */
-#define PB3 GPIO_PIN_ADDR(1, 3) /*!< Specify PB3 Pin Data Input/Output */
-#define PB4 GPIO_PIN_ADDR(1, 4) /*!< Specify PB4 Pin Data Input/Output */
-#define PB5 GPIO_PIN_ADDR(1, 5) /*!< Specify PB5 Pin Data Input/Output */
-#define PB6 GPIO_PIN_ADDR(1, 6) /*!< Specify PB6 Pin Data Input/Output */
-#define PB7 GPIO_PIN_ADDR(1, 7) /*!< Specify PB7 Pin Data Input/Output */
-#define PB8 GPIO_PIN_ADDR(1, 8) /*!< Specify PB8 Pin Data Input/Output */
-#define PB9 GPIO_PIN_ADDR(1, 9) /*!< Specify PB9 Pin Data Input/Output */
-#define PB10 GPIO_PIN_ADDR(1, 10) /*!< Specify PB10 Pin Data Input/Output */
-#define PB11 GPIO_PIN_ADDR(1, 11) /*!< Specify PB11 Pin Data Input/Output */
-#define PB12 GPIO_PIN_ADDR(1, 12) /*!< Specify PB12 Pin Data Input/Output */
-#define PB13 GPIO_PIN_ADDR(1, 13) /*!< Specify PB13 Pin Data Input/Output */
-#define PB14 GPIO_PIN_ADDR(1, 14) /*!< Specify PB14 Pin Data Input/Output */
-#define PB15 GPIO_PIN_ADDR(1, 15) /*!< Specify PB15 Pin Data Input/Output */
-
-#define PC0 GPIO_PIN_ADDR(2, 0) /*!< Specify PC0 Pin Data Input/Output */
-#define PC1 GPIO_PIN_ADDR(2, 1) /*!< Specify PC1 Pin Data Input/Output */
-#define PC2 GPIO_PIN_ADDR(2, 2) /*!< Specify PC2 Pin Data Input/Output */
-#define PC3 GPIO_PIN_ADDR(2, 3) /*!< Specify PC3 Pin Data Input/Output */
-#define PC4 GPIO_PIN_ADDR(2, 4) /*!< Specify PC4 Pin Data Input/Output */
-#define PC5 GPIO_PIN_ADDR(2, 5) /*!< Specify PC5 Pin Data Input/Output */
-#define PC6 GPIO_PIN_ADDR(2, 6) /*!< Specify PC6 Pin Data Input/Output */
-#define PC7 GPIO_PIN_ADDR(2, 7) /*!< Specify PC7 Pin Data Input/Output */
-#define PC8 GPIO_PIN_ADDR(2, 8) /*!< Specify PC8 Pin Data Input/Output */
-#define PC9 GPIO_PIN_ADDR(2, 9) /*!< Specify PC9 Pin Data Input/Output */
-#define PC10 GPIO_PIN_ADDR(2, 10) /*!< Specify PC10 Pin Data Input/Output */
-#define PC11 GPIO_PIN_ADDR(2, 11) /*!< Specify PC11 Pin Data Input/Output */
-#define PC12 GPIO_PIN_ADDR(2, 12) /*!< Specify PC12 Pin Data Input/Output */
-#define PC13 GPIO_PIN_ADDR(2, 13) /*!< Specify PC13 Pin Data Input/Output */
-#define PC14 GPIO_PIN_ADDR(2, 14) /*!< Specify PC14 Pin Data Input/Output */
-#define PC15 GPIO_PIN_ADDR(2, 15) /*!< Specify PC15 Pin Data Input/Output */
-
-#define PD0 GPIO_PIN_ADDR(3, 0) /*!< Specify PD0 Pin Data Input/Output */
-#define PD1 GPIO_PIN_ADDR(3, 1) /*!< Specify PD1 Pin Data Input/Output */
-#define PD2 GPIO_PIN_ADDR(3, 2) /*!< Specify PD2 Pin Data Input/Output */
-#define PD3 GPIO_PIN_ADDR(3, 3) /*!< Specify PD3 Pin Data Input/Output */
-#define PD4 GPIO_PIN_ADDR(3, 4) /*!< Specify PD4 Pin Data Input/Output */
-#define PD5 GPIO_PIN_ADDR(3, 5) /*!< Specify PD5 Pin Data Input/Output */
-#define PD6 GPIO_PIN_ADDR(3, 6) /*!< Specify PD6 Pin Data Input/Output */
-#define PD7 GPIO_PIN_ADDR(3, 7) /*!< Specify PD7 Pin Data Input/Output */
-#define PD8 GPIO_PIN_ADDR(3, 8) /*!< Specify PD8 Pin Data Input/Output */
-#define PD9 GPIO_PIN_ADDR(3, 9) /*!< Specify PD9 Pin Data Input/Output */
-#define PD10 GPIO_PIN_ADDR(3, 10) /*!< Specify PD10 Pin Data Input/Output */
-#define PD11 GPIO_PIN_ADDR(3, 11) /*!< Specify PD11 Pin Data Input/Output */
-#define PD12 GPIO_PIN_ADDR(3, 12) /*!< Specify PD12 Pin Data Input/Output */
-#define PD13 GPIO_PIN_ADDR(3, 13) /*!< Specify PD13 Pin Data Input/Output */
-#define PD14 GPIO_PIN_ADDR(3, 14) /*!< Specify PD14 Pin Data Input/Output */
-#define PD15 GPIO_PIN_ADDR(3, 15) /*!< Specify PD15 Pin Data Input/Output */
-
-#define PE0 GPIO_PIN_ADDR(4, 0) /*!< Specify PE0 Pin Data Input/Output */
-#define PE1 GPIO_PIN_ADDR(4, 1) /*!< Specify PE1 Pin Data Input/Output */
-#define PE2 GPIO_PIN_ADDR(4, 2) /*!< Specify PE2 Pin Data Input/Output */
-#define PE3 GPIO_PIN_ADDR(4, 3) /*!< Specify PE3 Pin Data Input/Output */
-#define PE4 GPIO_PIN_ADDR(4, 4) /*!< Specify PE4 Pin Data Input/Output */
-#define PE5 GPIO_PIN_ADDR(4, 5) /*!< Specify PE5 Pin Data Input/Output */
-#define PE6 GPIO_PIN_ADDR(4, 6) /*!< Specify PE6 Pin Data Input/Output */
-#define PE7 GPIO_PIN_ADDR(4, 7) /*!< Specify PE7 Pin Data Input/Output */
-#define PE8 GPIO_PIN_ADDR(4, 8) /*!< Specify PE8 Pin Data Input/Output */
-#define PE9 GPIO_PIN_ADDR(4, 9) /*!< Specify PE9 Pin Data Input/Output */
-#define PE10 GPIO_PIN_ADDR(4, 10) /*!< Specify PE10 Pin Data Input/Output */
-#define PE11 GPIO_PIN_ADDR(4, 11) /*!< Specify PE11 Pin Data Input/Output */
-#define PE12 GPIO_PIN_ADDR(4, 12) /*!< Specify PE12 Pin Data Input/Output */
-#define PE13 GPIO_PIN_ADDR(4, 13) /*!< Specify PE13 Pin Data Input/Output */
-#define PE14 GPIO_PIN_ADDR(4, 14) /*!< Specify PE14 Pin Data Input/Output */
-#define PE15 GPIO_PIN_ADDR(4, 15) /*!< Specify PE15 Pin Data Input/Output */
-
-#define PF0 GPIO_PIN_ADDR(5, 0) /*!< Specify PF0 Pin Data Input/Output */
-#define PF1 GPIO_PIN_ADDR(5, 1) /*!< Specify PF1 Pin Data Input/Output */
-#define PF2 GPIO_PIN_ADDR(5, 2) /*!< Specify PF2 Pin Data Input/Output */
-#define PF3 GPIO_PIN_ADDR(5, 3) /*!< Specify PF3 Pin Data Input/Output */
-#define PF4 GPIO_PIN_ADDR(5, 4) /*!< Specify PF4 Pin Data Input/Output */
-#define PF5 GPIO_PIN_ADDR(5, 5) /*!< Specify PF5 Pin Data Input/Output */
-#define PF6 GPIO_PIN_ADDR(5, 6) /*!< Specify PF6 Pin Data Input/Output */
-#define PF7 GPIO_PIN_ADDR(5, 7) /*!< Specify PF7 Pin Data Input/Output */
-#define PF8 GPIO_PIN_ADDR(5, 8) /*!< Specify PF8 Pin Data Input/Output */
-#define PF9 GPIO_PIN_ADDR(5, 9) /*!< Specify PF9 Pin Data Input/Output */
-#define PF10 GPIO_PIN_ADDR(5, 10) /*!< Specify PF10 Pin Data Input/Output */
-#define PF11 GPIO_PIN_ADDR(5, 11) /*!< Specify PF11 Pin Data Input/Output */
-#define PF12 GPIO_PIN_ADDR(5, 12) /*!< Specify PF12 Pin Data Input/Output */
-#define PF13 GPIO_PIN_ADDR(5, 13) /*!< Specify PF13 Pin Data Input/Output */
-#define PF14 GPIO_PIN_ADDR(5, 14) /*!< Specify PF14 Pin Data Input/Output */
-#define PF15 GPIO_PIN_ADDR(5, 15) /*!< Specify PF15 Pin Data Input/Output */
-
-#define PG0 GPIO_PIN_ADDR(6, 0) /*!< Specify PG0 Pin Data Input/Output */
-#define PG1 GPIO_PIN_ADDR(6, 1) /*!< Specify PG1 Pin Data Input/Output */
-#define PG2 GPIO_PIN_ADDR(6, 2) /*!< Specify PG2 Pin Data Input/Output */
-#define PG3 GPIO_PIN_ADDR(6, 3) /*!< Specify PG3 Pin Data Input/Output */
-#define PG4 GPIO_PIN_ADDR(6, 4) /*!< Specify PG4 Pin Data Input/Output */
-#define PG5 GPIO_PIN_ADDR(6, 5) /*!< Specify PG5 Pin Data Input/Output */
-#define PG6 GPIO_PIN_ADDR(6, 6) /*!< Specify PG6 Pin Data Input/Output */
-#define PG7 GPIO_PIN_ADDR(6, 7) /*!< Specify PG7 Pin Data Input/Output */
-#define PG8 GPIO_PIN_ADDR(6, 8) /*!< Specify PG8 Pin Data Input/Output */
-#define PG9 GPIO_PIN_ADDR(6, 9) /*!< Specify PG9 Pin Data Input/Output */
-#define PG10 GPIO_PIN_ADDR(6, 10) /*!< Specify PG10 Pin Data Input/Output */
-#define PG11 GPIO_PIN_ADDR(6, 11) /*!< Specify PG11 Pin Data Input/Output */
-#define PG12 GPIO_PIN_ADDR(6, 12) /*!< Specify PG12 Pin Data Input/Output */
-#define PG13 GPIO_PIN_ADDR(6, 13) /*!< Specify PG13 Pin Data Input/Output */
-#define PG14 GPIO_PIN_ADDR(6, 14) /*!< Specify PG14 Pin Data Input/Output */
-#define PG15 GPIO_PIN_ADDR(6, 15) /*!< Specify PG15 Pin Data Input/Output */
-
-#define PH0 GPIO_PIN_ADDR(7, 0) /*!< Specify PH0 Pin Data Input/Output */
-#define PH1 GPIO_PIN_ADDR(7, 1) /*!< Specify PH1 Pin Data Input/Output */
-#define PH2 GPIO_PIN_ADDR(7, 2) /*!< Specify PH2 Pin Data Input/Output */
-#define PH3 GPIO_PIN_ADDR(7, 3) /*!< Specify PH3 Pin Data Input/Output */
-#define PH4 GPIO_PIN_ADDR(7, 4) /*!< Specify PH4 Pin Data Input/Output */
-#define PH5 GPIO_PIN_ADDR(7, 5) /*!< Specify PH5 Pin Data Input/Output */
-#define PH6 GPIO_PIN_ADDR(7, 6) /*!< Specify PH6 Pin Data Input/Output */
-#define PH7 GPIO_PIN_ADDR(7, 7) /*!< Specify PH7 Pin Data Input/Output */
-#define PH8 GPIO_PIN_ADDR(7, 8) /*!< Specify PH8 Pin Data Input/Output */
-#define PH9 GPIO_PIN_ADDR(7, 9) /*!< Specify PH9 Pin Data Input/Output */
-#define PH10 GPIO_PIN_ADDR(7, 10) /*!< Specify PH10 Pin Data Input/Output */
-#define PH11 GPIO_PIN_ADDR(7, 11) /*!< Specify PH11 Pin Data Input/Output */
-#define PH12 GPIO_PIN_ADDR(7, 12) /*!< Specify PH12 Pin Data Input/Output */
-#define PH13 GPIO_PIN_ADDR(7, 13) /*!< Specify PH13 Pin Data Input/Output */
-#define PH14 GPIO_PIN_ADDR(7, 14) /*!< Specify PH14 Pin Data Input/Output */
-#define PH15 GPIO_PIN_ADDR(7, 15) /*!< Specify PH15 Pin Data Input/Output */
-
-#define PI0 GPIO_PIN_ADDR(8, 0) /*!< Specify PI0 Pin Data Input/Output */
-#define PI1 GPIO_PIN_ADDR(8, 1) /*!< Specify PI1 Pin Data Input/Output */
-#define PI2 GPIO_PIN_ADDR(8, 2) /*!< Specify PI2 Pin Data Input/Output */
-#define PI3 GPIO_PIN_ADDR(8, 3) /*!< Specify PI3 Pin Data Input/Output */
-#define PI4 GPIO_PIN_ADDR(8, 4) /*!< Specify PI4 Pin Data Input/Output */
-#define PI5 GPIO_PIN_ADDR(8, 5) /*!< Specify PI5 Pin Data Input/Output */
-#define PI6 GPIO_PIN_ADDR(8, 6) /*!< Specify PI6 Pin Data Input/Output */
-#define PI7 GPIO_PIN_ADDR(8, 7) /*!< Specify PI7 Pin Data Input/Output */
-#define PI8 GPIO_PIN_ADDR(8, 8) /*!< Specify PI8 Pin Data Input/Output */
-#define PI9 GPIO_PIN_ADDR(8, 9) /*!< Specify PI9 Pin Data Input/Output */
-#define PI10 GPIO_PIN_ADDR(8, 10) /*!< Specify PI10 Pin Data Input/Output */
-#define PI11 GPIO_PIN_ADDR(8, 11) /*!< Specify PI11 Pin Data Input/Output */
-#define PI12 GPIO_PIN_ADDR(8, 12) /*!< Specify PI12 Pin Data Input/Output */
-#define PI13 GPIO_PIN_ADDR(8, 13) /*!< Specify PI13 Pin Data Input/Output */
-#define PI14 GPIO_PIN_ADDR(8, 14) /*!< Specify PI14 Pin Data Input/Output */
-#define PI15 GPIO_PIN_ADDR(8, 15) /*!< Specify PI15 Pin Data Input/Output */
-
-/*@}*/ /* end of group NUC472_442_GPIO_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
- @{
-*/
-
-/**
- * @brief Clear GPIO Pin Interrupt Flag
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @return None
- *
- * @details Clear the interrupt status of specified GPIO pin.
- */
-#define GPIO_CLR_INT_FLAG(gpio, u32PinMask) ((gpio)->INTSRC = u32PinMask)
-
-/**
- * @brief Disable Pin De-bounce Function
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @return None
- *
- * @details Disable the interrupt de-bounce function of specified GPIO pin.
- */
-#define GPIO_DISABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
-
-/**
- * @brief Enable Pin De-bounce Function
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @return None
- *
- * @details Enable the interrupt de-bounce function of specified GPIO pin.
- */
-#define GPIO_ENABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN |= u32PinMask)
-
-/**
- * @brief Disable I/O Digital Input Path
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @return None
- *
- * @details Disable I/O digital input path of specified GPIO pin.
- */
-#define GPIO_DISABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
-
-/**
- * @brief Enable I/O Digital Input Path
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @return None
- *
- * @details Enable I/O digital input path of specified GPIO pin.
- */
-#define GPIO_ENABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
-
-/**
- * @brief Disable I/O DOUT mask
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @return None
- *
- * @details Disable I/O DOUT mask of specified GPIO pin.
- */
-#define GPIO_DISABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DATMSK |= u32PinMask)
-
-/**
- * @brief Enable I/O DOUT mask
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @return None
- *
- * @details Enable I/O DOUT mask of specified GPIO pin.
- */
-#define GPIO_ENABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
-
-/**
- * @brief Get GPIO Pin Interrupt Flag
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32PinMask The single or multiple pins of specified GPIO port.
- *
- * @retval 0 No interrupt at specified GPIO pin
- * @retval 1 The specified GPIO pin generate an interrupt
- *
- * @details Get the interrupt status of specified GPIO pin.
- */
-#define GPIO_GET_INT_FLAG(gpio, u32PinMask) ((gpio)->INTSRC & u32PinMask)
-
-/**
- * @brief Set De-bounce Sampling Cycle Time
- *
- * @param[in] u32ClkSrc The de-bounce counter clock source. It could be \ref GPIO_DBCTL_DBCLKSRC_HCLK or \ref GPIO_DBCTL_DBCLKSRC_IRC10K.
- * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be \n
- * \ref GPIO_DBCTL_DBCLKSEL_1, \ref GPIO_DBCTL_DBCLKSEL_2, \ref GPIO_DBCTL_DBCLKSEL_4, \ref GPIO_DBCTL_DBCLKSEL_8, \n
- * \ref GPIO_DBCTL_DBCLKSEL_16, \ref GPIO_DBCTL_DBCLKSEL_32, \ref GPIO_DBCTL_DBCLKSEL_64, \ref GPIO_DBCTL_DBCLKSEL_128, \n
- * \ref GPIO_DBCTL_DBCLKSEL_256, \ref GPIO_DBCTL_DBCLKSEL_512, \ref GPIO_DBCTL_DBCLKSEL_1024, \ref GPIO_DBCTL_DBCLKSEL_2048, \n
- * \ref GPIO_DBCTL_DBCLKSEL_4096, \ref GPIO_DBCTL_DBCLKSEL_8192, \ref GPIO_DBCTL_DBCLKSEL_16384, \ref GPIO_DBCTL_DBCLKSEL_32768.
- *
- * @return None
- *
- * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
- * Example: _GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_IRC10K, GPIO_DBCTL_DBCLKSEL_4). \n
- * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
- * Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us,
- * and system will sampling interrupt input once per 1600 us.
- */
-#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = (GPIO_DBCTL_ICLKON_Msk | u32ClkSrc | u32ClkSel))
-
-/**
- * @brief Get GPIO Port IN Data
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- *
- * @retval The specified port data
- *
- * @details Get the PIN register of specified GPIO port.
- */
-#define GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
-
-/**
- * @brief Set GPIO Port OUT Data
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Data GPIO port data.
- *
- * @retval None
- *
- * @details Set the Data into specified GPIO port.
- */
-#define GPIO_SET_OUT_DATA(gpio, u32Data) ((gpio)->DOUT = (u32Data))
-
-
-/**
- * @brief Toggle Specified GPIO pin
- *
- * @param[in] u32Pin Pxy
- *
- * @retval None
- *
- * @details Toggle the specified GPIO pint.
- */
-#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
-
-/**
- * @brief Enable External GPIO interrupt 0
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port.
- * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
- * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-#define GPIO_EnableEINT0 GPIO_EnableInt
-
-
-/**
- * @brief Disable External GPIO interrupt 0
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-#define GPIO_DisableEINT0 GPIO_DisableInt
-
-
-/**
- * @brief Enable External GPIO interrupt 1
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port.
- * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
- * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-#define GPIO_EnableEINT1 GPIO_EnableInt
-
-
-/**
- * @brief Disable External GPIO interrupt 1
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-#define GPIO_DisableEINT1 GPIO_DisableInt
-
-/**
- * @brief Enable External GPIO interrupt n
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port.
- * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
- * \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-#define GPIO_EnableEINT GPIO_EnableInt
-
-
-/**
- * @brief Disable External GPIO interrupt n
- *
- * @param[in] gpio GPIO port. It could be \ref PA, \ref PB, ... or \ref GPI
- * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
- *
- * @return None
- *
- * @details This function is used to enable specified GPIO pin interrupt.
- */
-#define GPIO_DisableEINT GPIO_DisableInt
-
-
-void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode);
-void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs);
-void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin);
-
-
-
-/*@}*/ /* end of group NUC472_442_GPIO_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_GPIO_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__GPIO_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_i2c.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,310 +0,0 @@
-/****************************************************************************//**
- * @file i2c.c
- * @version V0.10
- * $Revision: 13 $
- * $Date: 14/09/30 1:10p $
- * @brief NUC472/NUC442 I2C driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_I2C_Driver I2C Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
- @{
-*/
-
-/**
- * @brief This function make I2C module be ready and set the wanted bus clock.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u32BusClock is the target bus speed of I2C module.
- * @return Actual I2C bus clock frequency.
- */
-uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
-{
- uint32_t u32Div;
- uint32_t u32Pclk = CLK_GetPCLKFreq();
-
- u32Div = (uint32_t) ((( u32Pclk * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
- i2c->CLKDIV = u32Div;
-
- /* Enable I2C */
- i2c->CTL |= I2C_CTL_I2CEN_Msk;
-
- return ( u32Pclk / ((u32Div+1)<<2) );
-}
-
-/**
- * @brief This function closes the I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- */
-void I2C_Close(I2C_T *i2c)
-{
- /* Reset SPI */
- if((uint32_t)i2c == I2C0_BASE) {
- SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
- } else if((uint32_t)i2c == I2C1_BASE) {
- SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
- } else if((uint32_t)i2c == I2C2_BASE) {
- SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk;
- } else {
- SYS->IPRST1 |= SYS_IPRST1_I2C3RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2C3RST_Msk;
- }
-
- /* Disable I2C */
- i2c->CTL &= ~I2C_CTL_I2CEN_Msk;
-}
-
-/**
- * @brief This function clears the time-out flag.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- */
-void I2C_ClearTimeoutFlag(I2C_T *i2c)
-{
- i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
-}
-
-/**
- * @brief This function sets the control bit of the I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u8Start sets START bit to I2C module.
- * @param[in] u8Stop sets STOP bit to I2C module.
- * @param[in] u8Si sets SI bit to I2C module.
- * @param[in] u8Ack sets ACK bit to I2C module.
- * @return none
- */
-void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
-{
- uint32_t u32Reg = 0;
- uint32_t u32Val = i2c->CTL & ~(I2C_STA | I2C_STO | I2C_AA);
-
- if (u8Start)
- u32Reg |= I2C_STA;
- if (u8Stop)
- u32Reg |= I2C_STO;
- if (u8Si)
- u32Reg |= I2C_SI;
- if (u8Ack)
- u32Reg |= I2C_AA;
-
- i2c->CTL = u32Val | u32Reg;
-}
-
-/**
- * @brief This function disables the interrupt of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- */
-void I2C_DisableInt(I2C_T *i2c)
-{
- i2c->CTL &= ~I2C_CTL_INTEN_Msk;
-}
-
-/**
- * @brief This function enables the interrupt (EI bit) of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- */
-void I2C_EnableInt(I2C_T *i2c)
-{
- i2c->CTL |= I2C_CTL_INTEN_Msk;
-}
-
-/**
- * @brief This function returns the real bus clock of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return Actual I2C bus clock frequency.
- */
-uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
-{
- uint32_t u32Divider = i2c->CLKDIV;
-
- return ( CLK_GetPCLKFreq() / ((u32Divider+1)<<2) );
-}
-
-/**
- * @brief This function sets bus frequency of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u32BusClock is the target bus speed of I2C module.
- * @return Actual I2C bus clock frequency.
- */
-uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
-{
- uint32_t u32Div;
- uint32_t u32Pclk = CLK_GetPCLKFreq();
-
- u32Div = (uint32_t) (((u32Pclk * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
- i2c->CLKDIV = u32Div;
-
- return ( u32Pclk / ((u32Div+1)<<2) );
-}
-
-/**
- * @brief This function gets the interrupt flag of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return Interrupt flag.
- * @retval 0 Flag is not set.
- * @retval 1 Flag is set.
- */
-uint32_t I2C_GetIntFlag(I2C_T *i2c)
-{
- return ( (i2c->CTL & I2C_CTL_SI_Msk) == I2C_CTL_SI_Msk ? 1:0 );
-}
-
-/**
- * @brief This function returns the status of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return I2C status
- */
-uint32_t I2C_GetStatus(I2C_T *i2c)
-{
- return ( i2c->STATUS );
-}
-
-/**
- * @brief This function returns the data stored in data register of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return I2C data.
- */
-uint32_t I2C_GetData(I2C_T *i2c)
-{
- return ( i2c->DAT );
-}
-
-/**
- * @brief This function writes the data to data register of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u8Data is the data which will be write to data register of I2C module.
- * @return none
- */
-void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
-{
- i2c->DAT = u8Data;
-}
-
-/**
- * @brief Configure slave address and enable GC mode.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u8SlaveNo is the set number of salve address.
- * @param[in] u8SlaveAddr is the slave address.
- * @param[in] u8GCMode GC mode enable or not. Valid values are:
- * - \ref I2C_GCMODE_ENABLE
- * - \ref I2C_GCMODE_DISABLE
- * @return none
- */
-void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
-{
- switch (u8SlaveNo) {
- case 0:
- i2c->ADDR0 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- case 1:
- i2c->ADDR1 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- case 2:
- i2c->ADDR2 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- case 3:
- i2c->ADDR3 = (u8SlaveAddr << 1) | u8GCMode;
- break;
- default:
- i2c->ADDR0 = (u8SlaveAddr << 1) | u8GCMode;
- }
-}
-
-/**
- * @brief Configure the mask of slave address. The corresponding address bit is "Don't Care".
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u8SlaveNo is the set number of salve address.
- * @param[in] u8SlaveAddrMask is the slave address mask.
- * @return none
- */
-void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
-{
- switch (u8SlaveNo) {
- case 0:
- i2c->ADDRMSK0 = u8SlaveAddrMask << 1;
- break;
- case 1:
- i2c->ADDRMSK1 = u8SlaveAddrMask << 1;
- break;
- case 2:
- i2c->ADDRMSK2 = u8SlaveAddrMask << 1;
- break;
- case 3:
- i2c->ADDRMSK3 = u8SlaveAddrMask << 1;
- break;
- default:
- i2c->ADDRMSK0 = u8SlaveAddrMask << 1;
- }
-}
-
-/**
- * @brief This function enables timeout function and configures DIV4 function to support long timeout.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u8LongTimeout Enable timeout counter input clock is divide by 4.
- * @return none
- */
-void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
-{
- if(u8LongTimeout)
- i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
- else
- i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
-
- i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
-}
-
-/**
- * @brief This function disables time-out function.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- */
-void I2C_DisableTimeout(I2C_T *i2c)
-{
- i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
-}
-
-/**
- * @brief This function enables the wakeup function of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- */
-void I2C_EnableWakeup(I2C_T *i2c)
-{
- i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
-}
-
-/**
- * @brief This function disables the wakeup function of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- */
-void I2C_DisableWakeup(I2C_T *i2c)
-{
- i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
-}
-
-/*@}*/ /* end of group NUC472_442_I2C_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_I2C_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_i2c.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-/****************************************************************************//**
- * @file i2c.h
- * @version V1.00
- * $Revision: 12 $
- * $Date: 14/09/30 1:12p $
- * @brief NUC472/NUC442 I2C driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __I2C_H__
-#define __I2C_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_I2C_Driver I2C Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_I2C_EXPORTED_CONSTANTS I2C Exported Constants
- @{
-*/
-
-#define I2C_STA 0x20 /*!< I2C START bit value \hideinitializer */
-#define I2C_STO 0x10 /*!< I2C STOP bit value \hideinitializer */
-#define I2C_SI 0x08 /*!< I2C SI bit value \hideinitializer */
-#define I2C_AA 0x04 /*!< I2C ACK bit value \hideinitializer */
-
-#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
-#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_I2C_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
- @{
-*/
-
-/**
- * @brief This macro sets the I2C control register at one time.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u8Ctrl is the register value of I2C control register.
- * @return none
- * \hideinitializer
- */
-#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
-
-/**
- * @brief This macro only set START bit to the control register of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- * \hideinitializer
- */
-#define I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
-
-/**
- * @brief This macro only set STOP bit to the control register of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- * \hideinitializer
- */
-#define I2C_STOP(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | I2C_CTL_SI_Msk | I2C_CTL_STO_Msk )
-
-/**
- * @brief This macro will return when I2C module is ready.
- * @param[in] i2c is the base address of I2C module.
- * @return none
- * \hideinitializer
- */
-#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
-
-/**
- * @brief This macro returns the data stored in data register of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return Data.
- * \hideinitializer
- */
-#define I2C_GET_DATA(i2c) ( (i2c)->DAT )
-
-/**
- * @brief This macro writes the data to data register of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @param[in] u8Data is the data which will be write to data register of I2C module.
- * @return none
- * \hideinitializer
- */
-#define I2C_SET_DATA(i2c, u8Data) ( (i2c)->DAT = u8Data )
-
-/**
- * @brief This macro returns the status of I2C module.
- * @param[in] i2c is the base address of I2C module.
- * @return Status.
- * \hideinitializer
- */
-#define I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
-
-/**
- * @brief This macro returns time-out flag.
- * @param[in] i2c is the base address of I2C module.
- * @return Status.
- * @retval 0 Flag is not set.
- * @retval 1 Flag is set.
- * \hideinitializer
- */
-#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
-
-/**
- * @brief This macro returns wakeup flag.
- * @param[in] i2c is the base address of I2C module.
- * @return Status.
- * @retval 0 Flag is not set.
- * @retval 1 Flag is set.
- * \hideinitializer
- */
-#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
-
-uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
-void I2C_Close(I2C_T *i2c);
-void I2C_ClearTimeoutFlag(I2C_T *i2c);
-void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
-void I2C_DisableInt(I2C_T *i2c);
-void I2C_EnableInt(I2C_T *i2c);
-uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
-uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
-uint32_t I2C_GetIntFlag(I2C_T *i2c);
-uint32_t I2C_GetStatus(I2C_T *i2c);
-uint32_t I2C_GetData(I2C_T *i2c);
-void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
-void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
-void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
-void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
-void I2C_DisableTimeout(I2C_T *i2c);
-void I2C_EnableWakeup(I2C_T *i2c);
-void I2C_DisableWakeup(I2C_T *i2c);
-
-/*@}*/ /* end of group NUC472_442_I2C_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_I2C_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__I2C_H__
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_i2s.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,205 +0,0 @@
-/******************************************************************************
- * @file i2s.c
- * @version V0.10
- * $Revision: 14 $
- * $Date: 14/09/30 1:10p $
- * @brief NUC472/NUC442 I2S driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include <stdio.h>
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_I2S_Driver I2S Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
- @{
-*/
-
-/**
- * @brief This function is used to get I2S source clock frequency.
- * @param[in] i2s is the base address of I2S module.
- * @return I2S source clock frequency (Hz).
- */
-static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
-{
- uint32_t u32Freq, u32ClkSrcSel;
-
- // get I2S selection clock source
- if((uint32_t)i2s == I2S0_BASE)
- u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S0SEL_Msk;
- else
- u32ClkSrcSel = CLK->CLKSEL3 & CLK_CLKSEL3_I2S1SEL_Msk;
-
- switch (u32ClkSrcSel) {
- case CLK_CLKSEL3_I2S0SEL_HXT:
- u32Freq = __HXT;
- break;
-
- case CLK_CLKSEL3_I2S0SEL_PLL:
- case CLK_CLKSEL3_I2S1SEL_PLL:
- u32Freq = CLK_GetPLLClockFreq();
- break;
-
- case CLK_CLKSEL3_I2S0SEL_HIRC:
- case CLK_CLKSEL3_I2S1SEL_HIRC:
- u32Freq = __HIRC;
- break;
-
- case CLK_CLKSEL3_I2S0SEL_PCLK:
- case CLK_CLKSEL3_I2S1SEL_PCLK:
- u32Freq = SystemCoreClock;
- break;
-
- default:
- u32Freq = __HIRC;
- break;
- }
-
- return u32Freq;
-}
-
-/**
- * @brief This function configures some parameters of I2S interface for general purpose use.
- * The sample rate may not be used from the parameter, it depends on system's clock settings,
- * but real sample rate used by system will be returned for reference.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32MasterSlave I2S operation mode. Valid values are:
- * - \ref I2S_MODE_MASTER
- * - \ref I2S_MODE_SLAVE
- * @param[in] u32SampleRate Sample rate
- * @param[in] u32WordWidth Data length. Valid values are:
- * - \ref I2S_DATABIT_8
- * - \ref I2S_DATABIT_16
- * - \ref I2S_DATABIT_24
- * - \ref I2S_DATABIT_32
- * @param[in] u32Channels: Audio format. Valid values are:
- * - \ref I2S_MONO
- * - \ref I2S_STEREO
- * @param[in] u32DataFormat: Data format. Valid values are:
- * - \ref I2S_FORMAT_I2S
- * - \ref I2S_FORMAT_MSB
- * - \ref I2S_FORMAT_PCMA
- * - \ref I2S_FORMAT_PCMB
- * @param[in] u32AudioInterface: Audio interface. Valid values are:
- * - \ref I2S_I2S
- * - \ref I2S_PCM
- * @return Real sample rate.
- */
-uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface)
-{
- uint16_t u16Divider;
- uint32_t u32BitRate, u32SrcClk;
-
- if((uint32_t)i2s == I2S0_BASE) {
- SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;
- } else {
- SYS->IPRST1 |= SYS_IPRST1_I2S1RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_I2S1RST_Msk;
- }
-
- i2s->CTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat | u32AudioInterface | I2S_FIFO_TX_LEVEL_WORD_4 | I2S_FIFO_RX_LEVEL_WORD_4;
-
- u32SrcClk = I2S_GetSourceClockFreq(i2s);
-
- u32BitRate = u32SampleRate * (((u32WordWidth>>4) & 0x3) + 1) * 16;
- u16Divider = ((u32SrcClk/u32BitRate) >> 1) - 1;
- i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | (u16Divider << 8);
-
- //calculate real sample rate
- u32BitRate = u32SrcClk / (2*(u16Divider+1));
- u32SampleRate = u32BitRate / ((((u32WordWidth>>4) & 0x3) + 1) * 16);
-
- i2s->CTL |= I2S_CTL_I2SEN_Msk;
-
- return u32SampleRate;
-}
-
-/**
- * @brief Disable I2S function and I2S clock.
- * @param[in] i2s is the base address of I2S module.
- * @return none
- */
-void I2S_Close(I2S_T *i2s)
-{
- i2s->CTL &= ~I2S_CTL_I2SEN_Msk;
-}
-
-/**
- * @brief This function enables the interrupt according to the mask parameter.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32Mask is the combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt bit.
- * @return none
- */
-void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
-{
- i2s->IEN |= u32Mask;
-}
-
-/**
- * @brief This function disables the interrupt according to the mask parameter.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32Mask is the combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt bit.
- * @return none
- */
-void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
-{
- i2s->IEN &= ~u32Mask;
-}
-
-/**
- * @brief Enable MCLK .
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32BusClock is the target MCLK clock
- * @return Actual MCLK clock
- */
-uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
-{
- uint8_t u8Divider;
- uint32_t u32SrcClk, u32Reg;
-
- u32SrcClk = I2S_GetSourceClockFreq(i2s);
- if (u32BusClock == u32SrcClk)
- u8Divider = 0;
- else
- u8Divider = (u32SrcClk/u32BusClock) >> 1;
-
- i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;
-
- i2s->CTL |= I2S_CTL_MCLKEN_Msk;
-
- u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;
-
- if (u32Reg == 0)
- return u32SrcClk;
- else
- return ((u32SrcClk >> 1) / u32Reg);
-}
-
-/**
- * @brief Disable MCLK .
- * @param[in] i2s is the base address of I2S module.
- * @return none
- */
-void I2S_DisableMCLK(I2S_T *i2s)
-{
- i2s->CTL &= ~I2S_CTL_MCLKEN_Msk;
-}
-/*@}*/ /* end of group NUC472_442_I2S_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_I2S_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_i2s.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,308 +0,0 @@
-/******************************************************************************
- * @file i2s.h
- * @version V0.10
- * $Revision: 10 $
- * $Date: 14/09/30 1:12p $
- * @brief NUC472/NUC442 I2S driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __I2S_H__
-#define __I2S_H__
-
-#include "NUC472_442.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_I2S_Driver I2S Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_I2S_EXPORTED_CONSTANTS I2S Exported Constants
- @{
-*/
-#define I2S_DATABIT_8 (0 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
-#define I2S_DATABIT_16 (1 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
-#define I2S_DATABIT_24 (2 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
-#define I2S_DATABIT_32 (3 << I2S_CTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
-
-/* Audio Format */
-#define I2S_MONO I2S_CTL_MONO_Msk /*!< Mono channel \hideinitializer */
-#define I2S_STEREO 0 /*!< Stereo channel \hideinitializer */
-
-/* I2S Data Format */
-#define I2S_FORMAT_MSB I2S_CTL_FORMAT_Msk /*!< MSB data format \hideinitializer */
-#define I2S_FORMAT_I2S 0 /*!< I2S data format \hideinitializer */
-#define I2S_FORMAT_PCMB I2S_CTL_FORMAT_Msk /*!< PCMB data format \hideinitializer */
-#define I2S_FORMAT_PCMA 0 /*!< PCMA data format \hideinitializer */
-
-/* I2S Interface */
-#define I2S_PCM I2S_CTL_PCMEN_Msk /*!< PCM interface is selected \hideinitializer */
-#define I2S_I2S 0 /*!< I2S interface is selected \hideinitializer */
-
-/* I2S Operation mode */
-#define I2S_MODE_SLAVE I2S_CTL_SLAVE_Msk /*!< As slave mode \hideinitializer */
-#define I2S_MODE_MASTER 0 /*!< As master mode \hideinitializer */
-
-/* I2S FIFO Threshold */
-#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word \hideinitializer */
-#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
-#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
-#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
-#define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
-#define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
-#define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
-#define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTL_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
-
-#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word \hideinitializer */
-#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
-#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
-#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
-#define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
-#define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
-#define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
-#define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTL_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
-
-/* I2S Record Channel */
-#define I2S_MONO_RIGHT 0 /*!< Record mono right channel \hideinitializer */
-#define I2S_MONO_LEFT I2S_CTL_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
-
-/* I2S Channel */
-#define I2S_RIGHT 0 /*!< Select right channel \hideinitializer */
-#define I2S_LEFT 1 /*!< Select left channel \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_I2S_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_I2S_EXPORTED_FUNCTIONS I2S Exported Functions
- @{
-*/
-/*---------------------------------------------------------------------------------------------------------*/
-/* inline functions */
-/*---------------------------------------------------------------------------------------------------------*/
-/**
- * @brief Enable zero cross detect function.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32ChMask is the mask for left or right channel. Valid values are:
- * - \ref I2S_RIGHT
- * - \ref I2S_LEFT
- * @return none
- * \hideinitializer
- */
-static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
-{
- if(u32ChMask == I2S_RIGHT)
- i2s->CTL |= I2S_CTL_RZCEN_Msk;
- else
- i2s->CTL |= I2S_CTL_LZCEN_Msk;
-}
-
-/**
- * @brief Disable zero cross detect function.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32ChMask is the mask for left or right channel. Valid values are:
- * - \ref I2S_RIGHT
- * - \ref I2S_LEFT
- * @return none
- * \hideinitializer
- */
-static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
-{
- if(u32ChMask == I2S_RIGHT)
- i2s->CTL &= ~I2S_CTL_RZCEN_Msk;
- else
- i2s->CTL &= ~I2S_CTL_LZCEN_Msk;
-}
-
-/**
- * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_TXPDMAEN_Msk )
-
-/**
- * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXPDMAEN_Msk )
-
-/**
- * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL |= I2S_CTL_RXPDMAEN_Msk )
-
-/**
- * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXPDMAEN_Msk )
-
-/**
- * @brief Enable I2S Tx function .
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL |= I2S_CTL_TXEN_Msk )
-
-/**
- * @brief Disable I2S Tx function .
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL &= ~I2S_CTL_TXEN_Msk )
-
-/**
- * @brief Enable I2S Rx function .
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL |= I2S_CTL_RXEN_Msk )
-
-/**
- * @brief Disable I2S Rx function .
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL &= ~I2S_CTL_RXEN_Msk )
-
-/**
- * @brief Enable Tx Mute function .
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL |= I2S_CTL_MUTE_Msk )
-
-/**
- * @brief Disable Tx Mute function .
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL &= ~I2S_CTL_MUTE_Msk )
-
-/**
- * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_TXCLR_Msk )
-
-/**
- * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
- * @param[in] i2s is the base address of I2S module.
- * @return none
- * \hideinitializer
- */
-#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL |= I2S_CTL_RXCLR_Msk )
-
-/**
- * @brief This function sets the recording source channel when mono mode is used.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32Ch left or right channel. Valid values are:
- * - \ref I2S_MONO_LEFT
- * - \ref I2S_MONO_RIGHT
- * @return none
- * \hideinitializer
- */
-static __INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
-{
- u32Ch == I2S_MONO_LEFT ?
- (i2s->CTL |= I2S_CTL_RXLCH_Msk) :
- (i2s->CTL &= ~I2S_CTL_RXLCH_Msk);
-}
-
-/**
- * @brief Write data to I2S Tx FIFO.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32Data: The data written to FIFO.
- * @return none
- * \hideinitializer
- */
-#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = u32Data )
-
-/**
- * @brief Read Rx FIFO.
- * @param[in] i2s is the base address of I2S module.
- * @return Data in Rx FIFO.
- * \hideinitializer
- */
-#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
-
-/**
- * @brief This function gets the interrupt flag according to the mask parameter.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32Mask is the mask for the all interrupt flags.
- * @return The masked bit value of interrupt flag.
- * \hideinitializer
- */
-#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS & u32Mask )
-
-/**
- * @brief This function clears the interrupt flag according to the mask parameter.
- * @param[in] i2s is the base address of I2S module.
- * @param[in] u32Mask is the mask for the all interrupt flags.
- * @return none
- * \hideinitializer
- */
-#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS |= u32Mask )
-
-/**
- * @brief Get transmit FIFO level
- * @param[in] i2s is the base address of I2S module.
- * @return FIFO level
- * \hideinitializer
- */
-#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_TXCNT_Msk) >> I2S_STATUS_TXCNT_Pos) & 0xF )
-
-/**
- * @brief Get receive FIFO level
- * @param[in] i2s is the base address of I2S module.
- * @return FIFO level
- * \hideinitializer
- */
-#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS & I2S_STATUS_RXCNT_Msk) >> I2S_STATUS_RXCNT_Pos) & 0xF )
-
-uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat, uint32_t u32AudioInterface);
-void I2S_Close(I2S_T *i2s);
-void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
-void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
-uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
-void I2S_DisableMCLK(I2S_T *i2s);
-
-/*@}*/ /* end of group NUC472_442_I2S_EXPORTED_FUNCTIONS */
-
-
-/*@}*/ /* end of group NUC472_442_I2S_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pdma.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,313 +0,0 @@
-/**************************************************************************//**
- * @file pdma.c
- * @version V1.00
- * $Revision: 7 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 PDMA driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-
-static uint8_t u32ChSelect[PDMA_CH_MAX];
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PDMA_Driver PDMA Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
- @{
-*/
-
-/**
- * @brief PDMA Open
- *
- * @param[in] u32Mask Channel enable bits.
- *
- * @return None
- *
- * @details This function enable the PDMA channels.
- */
-void PDMA_Open(uint32_t u32Mask)
-{
- int volatile i;
-
- for (i=0; i<PDMA_CH_MAX; i++) {
- PDMA->DSCT[i].CTL = 0;
- u32ChSelect[i] = 0x1f;
- }
-
- PDMA->CHCTL |= u32Mask;
-}
-
-/**
- * @brief PDMA Close
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function disable all PDMA channels.
- */
-void PDMA_Close(void)
-{
- PDMA->CHCTL = 0;
-}
-
-/**
- * @brief Set PDMA Transfer Count
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Width Data width. PDMA_WIDTH_8, PDMA_WIDTH_16, or PDMA_WIDTH_32
- * @param[in] u32TransCount Transfer count
- *
- * @return None
- *
- * @details This function set the selected channel data width and transfer count.
- */
-void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
-{
- PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
- PDMA->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount-1) << PDMA_DSCT_CTL_TXCNT_Pos));
-}
-
-/**
- * @brief Set PDMA Transfer Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32SrcAddr Source address
- * @param[in] u32SrcCtrl Source control attribute. PDMA_SAR_INC or PDMA_SAR_FIX
- * @param[in] u32DstAddr destination address
- * @param[in] u32DstCtrl destination control attribute. PDMA_DAR_INC or PDMA_DAR_FIX
- *
- * @return None
- *
- * @details This function set the selected channel source/destination address and attribute.
- */
-void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
-{
- PDMA->DSCT[u32Ch].ENDSA = u32SrcAddr;
- PDMA->DSCT[u32Ch].ENDDA = u32DstAddr;
- PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
- PDMA->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
-}
-
-/**
- * @brief Set PDMA Transfer Mode
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Peripheral The selected peripheral. PDMA_SPI0_TX, PDMA_UART0_TX, PDMA_I2S_TX,...PDMA_MEM
- * @param[in] u32ScatterEn Scatter-gather mode enable
- * @param[in] u32DescAddr Scatter-gather descriptor address
- *
- * @return None
- *
- * @details This function set the selected channel transfer mode. Include peripheral setting.
- */
-void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
-{
- u32ChSelect[u32Ch] = u32Peripheral;
- switch (u32Ch) {
- case 0:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
- break;
- case 1:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
- break;
- case 2:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
- break;
- case 3:
- PDMA->REQSEL0_3 = (PDMA->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
- break;
- case 4:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
- break;
- case 5:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
- break;
- case 6:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
- break;
- case 7:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
- break;
- case 8:
- PDMA->REQSEL8_11 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
- break;
- case 9:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
- break;
- case 10:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
- break;
- case 11:
- PDMA->REQSEL4_7 = (PDMA->REQSEL4_7 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
- break;
- case 12:
- PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral;
- break;
- case 13:
- PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos);
- break;
- case 14:
- PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos);
- break;
- case 15:
- PDMA->REQSEL12_15 = (PDMA->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos);
- break;
- default:
- ;
- }
-
- if (u32ScatterEn) {
- PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
- PDMA->DSCT[u32Ch].NEXT = u32DescAddr - (PDMA->SCATBA);
- } else
- PDMA->DSCT[u32Ch].CTL = (PDMA->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
-}
-
-/**
- * @brief Set PDMA Burst Type
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32BurstType Burst mode or single mode
- * @param[in] u32BurstSize Set the size of burst mode
- *
- * @return None
- *
- * @details This function set the selected channel burst type and size.
- */
-void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
-{
- PDMA->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
- PDMA->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
-}
-
-/**
- * @brief Set PDMA TimeOut Count
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32OnOff Enable/disable time out function
- * @param[in] u32TimeOutCnt Timeout count
- *
- * @return None
- *
- * @details This function set the timeout count.
- */
-void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
-{
- switch(u32Ch) {
- case 0:
- PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
- break;
- case 1:
- PDMA->TOC0_1 = (PDMA->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
- break;
- case 2:
- PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
- break;
- case 3:
- PDMA->TOC2_3 = (PDMA->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos);
- break;
- case 4:
- PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
- break;
- case 5:
- PDMA->TOC4_5 = (PDMA->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
- break;
- case 6:
- PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
- break;
- case 7:
- PDMA->TOC6_7 = (PDMA->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
- break;
- case 8:
- PDMA->TOC8_9 = (PDMA->TOC8_9 & ~PDMA_TOC8_9_TOC8_Msk) | u32TimeOutCnt;
- break;
- case 9:
- PDMA->TOC8_9 = (PDMA->TOC8_9 & ~PDMA_TOC8_9_TOC9_Msk) | (u32TimeOutCnt << PDMA_TOC8_9_TOC9_Pos);
- break;
- case 10:
- PDMA->TOC10_11 = (PDMA->TOC10_11 & ~PDMA_TOC10_11_TOC10_Msk) | u32TimeOutCnt;
- break;
- case 11:
- PDMA->TOC10_11 = (PDMA->TOC10_11 & ~PDMA_TOC10_11_TOC11_Msk) | (u32TimeOutCnt << PDMA_TOC10_11_TOC11_Pos);
- break;
- case 12:
- PDMA->TOC12_13 = (PDMA->TOC12_13 & ~PDMA_TOC12_13_TOC12_Msk) | u32TimeOutCnt;
- break;
- case 13:
- PDMA->TOC12_13 = (PDMA->TOC12_13 & ~PDMA_TOC12_13_TOC13_Msk) | (u32TimeOutCnt << PDMA_TOC12_13_TOC13_Pos);
- break;
- case 14:
- PDMA->TOC14_15 = (PDMA->TOC14_15 & ~PDMA_TOC14_15_TOC14_Msk) | u32TimeOutCnt;
- break;
- case 15:
- PDMA->TOC14_15 = (PDMA->TOC14_15 & ~PDMA_TOC14_15_TOC15_Msk) | (u32TimeOutCnt << PDMA_TOC14_15_TOC15_Pos);
- break;
- default:
- ;
- }
-}
-
-
-/**
- * @brief Trigger PDMA
- *
- * @param[in] u32Ch The selected channel
- *
- * @return None
- *
- * @details This function trigger the selected channel.
- */
-void PDMA_Trigger(uint32_t u32Ch)
-{
- if (u32ChSelect[u32Ch] == PDMA_MEM)
- PDMA->SWREQ = (1 << u32Ch);
-}
-
-/**
- * @brief Enable Interrupt
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Mask The Interrupt Type
- *
- * @return None
- *
- * @details This function enable the selected channel interrupt.
- */
-void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
-{
- PDMA->INTEN |= (1 << u32Ch);
-}
-
-/**
- * @brief Disable Interrupt
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Mask The Interrupt Type
- *
- * @return None
- *
- * @details This function disable the selected channel interrupt.
- */
-void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
-{
- PDMA->INTEN &= ~(1 << u32Ch);
-}
-
-/*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_PDMA_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pdma.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,305 +0,0 @@
-/**************************************************************************//**
- * @file pdma.h
- * @version V1.00
- * $Revision: 8 $
- * $Date: 14/06/05 5:16p $
- * @brief NUC472/NUC442 PDMA driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __PDMA_H__
-#define __PDMA_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PDMA_Driver PDMA Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
- @{
-*/
-#define PDMA_CH_MAX 16 /*!< Specify Maximum Channels of PDMA \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* operation Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
-#define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
-#define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Data Width Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
-#define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
-#define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Address Attribute Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
-#define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
-#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
-#define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Burst Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
-#define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
-
-#define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
-#define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
-#define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
-#define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
-#define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
-#define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
-#define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
-#define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Peripheral Transfer Mode Constant Definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_SPI0_TX 0x00000000UL /*!<DMA Connect to SPI0 TX \hideinitializer */
-#define PDMA_SPI1_TX 0x00000001UL /*!<DMA Connect to SPI1 TX \hideinitializer */
-#define PDMA_SPI2_TX 0x00000002UL /*!<DMA Connect to SPI2 TX \hideinitializer */
-#define PDMA_SPI3_TX 0x00000003UL /*!<DMA Connect to SPI3 TX \hideinitializer */
-#define PDMA_UART0_TX 0x00000004UL /*!<DMA Connect to UART0 TX \hideinitializer */
-#define PDMA_UART1_TX 0x00000005UL /*!<DMA Connect to UART1 TX \hideinitializer */
-#define PDMA_UART2_TX 0x00000006UL /*!<DMA Connect to UART2 TX \hideinitializer */
-#define PDMA_UART3_TX 0x00000007UL /*!<DMA Connect to UART3 TX \hideinitializer */
-#define PDMA_UART4_TX 0x00000008UL /*!<DMA Connect to UART4 TX \hideinitializer */
-#define PDMA_UART5_TX 0x00000009UL /*!<DMA Connect to UART5 TX \hideinitializer */
-#define PDMA_I2S0_TX 0x0000000BUL /*!<DMA Connect to I2S TX \hideinitializer */
-#define PDMA_I2S1_TX 0x0000000CUL /*!<DMA Connect to I2S1 TX \hideinitializer */
-#define PDMA_SPI0_RX 0x0000000DUL /*!<DMA Connect to SPI0 RX \hideinitializer */
-#define PDMA_SPI1_RX 0x0000000EUL /*!<DMA Connect to SPI1 RX \hideinitializer */
-#define PDMA_SPI2_RX 0x0000000FUL /*!<DMA Connect to SPI2 RX \hideinitializer */
-#define PDMA_SPI3_RX 0x00000010UL /*!<DMA Connect to SPI3 RX \hideinitializer */
-#define PDMA_UART0_RX 0x00000011UL /*!<DMA Connect to UART0 RX \hideinitializer */
-#define PDMA_UART1_RX 0x00000012UL /*!<DMA Connect to UART1 RX \hideinitializer */
-#define PDMA_UART2_RX 0x00000013UL /*!<DMA Connect to UART2 RX \hideinitializer */
-#define PDMA_UART3_RX 0x00000014UL /*!<DMA Connect to UART3 RX \hideinitializer */
-#define PDMA_UART4_RX 0x00000015UL /*!<DMA Connect to UART4 RX \hideinitializer */
-#define PDMA_UART5_RX 0x00000016UL /*!<DMA Connect to UART5 RX \hideinitializer */
-#define PDMA_ADC 0x00000018UL /*!<DMA Connect to ADC \hideinitializer */
-#define PDMA_I2S0_RX 0x00000019UL /*!<DMA Connect to I2S TX \hideinitializer */
-#define PDMA_I2S1_RX 0x0000001AUL /*!<DMA Connect to I2S1 TX \hideinitializer */
-#define PDMA_MEM 0x0000001FUL /*!<DMA Connect to Memory \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
- @{
-*/
-
-/**
- * @brief Get PDMA Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This macro gets the interrupt status.
- * \hideinitializer
- */
-#define PDMA_GET_INT_STATUS() ((uint32_t)(PDMA->INTSTS))
-
-/**
- * @brief Get Transfer Done Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details Get the transfer done Interrupt status.
- * \hideinitializer
- */
-#define PDMA_GET_TD_STS() ((uint32_t)(PDMA->TDSTS))
-
-/**
- * @brief Clear Transfer Done Interrupt Status
- *
- * @param[in] u32Mask The channel mask
- *
- * @return None
- *
- * @details Clear the transfer done Interrupt status.
- * \hideinitializer
- */
-#define PDMA_CLR_TD_FLAG(u32Mask) ((uint32_t)(PDMA->TDSTS = u32Mask))
-
-/**
- * @brief Get Target Abort Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details Get the target abort Interrupt status.
- * \hideinitializer
- */
-#define PDMA_GET_ABORT_STS() ((uint32_t)(PDMA->ABTSTS))
-
-/**
- * @brief Clear Target Abort Interrupt Status
- *
- * @param[in] u32Mask The channel mask
- *
- * @return None
- *
- * @details Clear the target abort Interrupt status.
- * \hideinitializer
- */
-#define PDMA_CLR_ABORT_FLAG(u32Mask) ((uint32_t)(PDMA->ABTSTS = u32Mask))
-
-/**
- * @brief Get Scatter-Gather Table Empty Interrupt Status
- *
- * @param[in] None
- *
- * @return None
- *
- * @details Get the scatter-gather table empty Interrupt status.
- * \hideinitializer
- */
-#define PDMA_GET_EMPTY_STS() ((uint32_t)(PDMA->SCATSTS))
-
-/**
- * @brief Clear Scatter-Gather Table Empty Interrupt Status
- *
- * @param[in] u32Mask The channel mask
- *
- * @return None
- *
- * @details Clear the scatter-gather table empty Interrupt status.
- * \hideinitializer
- */
-#define PDMA_CLR_EMPTY_FLAG(u32Mask) ((uint32_t)(PDMA->SCATSTS = u32Mask))
-
-/**
- * @brief Clear Timeout Interrupt Status
- *
- * @param[in] u32Ch The selected channel
- *
- * @return None
- *
- * @details Clear the selected channel timeout interrupt status.
- * \hideinitializer
- */
-#define PDMA_CLR_TMOUT_FLAG(u32Ch) ((uint32_t)(PDMA->INTSTS = (1 << (u32Ch + 8))))
-
-/**
- * @brief Check Channel Status
- *
- * @param[in] u32Ch The selected channel
- *
- * @return 0 = idle; 1 = busy
- *
- * @details Check the selected channel is busy or not.
- * \hideinitializer
- */
-#define PDMA_IS_CH_BUSY(u32Ch) ((uint32_t)(PDMA->TRGSTS & (1 << u32Ch))? 1 : 0)
-
-/**
- * @brief Set Source Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Addr The selected address
- *
- * @return None
- *
- * @details This macro set the selected channel source address.
- * \hideinitializer
- */
-#define PDMA_SET_SRC_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].ENDSA = u32Addr))
-
-/**
- * @brief Set Destination Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Addr The selected address
- *
- * @return None
- *
- * @details This macro set the selected channel destination address.
- * \hideinitializer
- */
-#define PDMA_SET_DST_ADDR(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].ENDDA = u32Addr))
-
-/**
- * @brief Set Transfer Count
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Count Transfer Count
- *
- * @return None
- *
- * @details This macro set the selected channel transfer count.
- * \hideinitializer
- */
-#define PDMA_SET_TRANS_CNT(u32Ch, u32Count) ((uint32_t)(PDMA->DSCT[u32Ch].CTL=(PDMA->DSCT[u32Ch].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|((u32Count-1) << PDMA_DSCT_CTL_TXCNT_Pos))
-
-/**
- * @brief Set Scatter-gather descriptor Address
- *
- * @param[in] u32Ch The selected channel
- * @param[in] u32Addr The descriptor address
- *
- * @return None
- *
- * @details This macro set the selected channel scatter-gather descriptor address.
- * \hideinitializer
- */
-#define PDMA_SET_SCATTER_DESC(u32Ch, u32Addr) ((uint32_t)(PDMA->DSCT[u32Ch].NEXT = u32Addr - (PDMA->SCATBA)))
-
-/**
- * @brief Stop the channel
- *
- * @param[in] u32Ch The selected channel
- *
- * @return None
- *
- * @details This macro stop the selected channel.
- * \hideinitializer
- */
-#define PDMA_STOP(u32Ch) ((uint32_t)(PDMA->STOP = (1 << u32Ch)))
-
-
-
-void PDMA_Open(uint32_t u32Mask);
-void PDMA_Close(void);
-void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
-void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
-void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
-void PDMA_SetBurstType(uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
-void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
-void PDMA_Trigger(uint32_t u32Ch);
-void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask);
-void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask);
-
-
-
-/*@}*/ /* end of group NUC472_442_PDMA_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_PDMA_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__PDMA_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_ps2.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-/******************************************************************************
- * @file ps2.c
- * @version V1.00
- * $Revision: 5 $
- * $Date: 14/10/03 11:59a $
- * @brief NUC472/NUC442 PS2 driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include <stdio.h>
-#include "NUC472_442.h"
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Includes of local headers */
-/*---------------------------------------------------------------------------------------------------------*/
-//#include "ps2.h"
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PS2_Driver PS2 Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_PS2_EXPORTED_FUNCTIONS PS2 Exported Functions
- @{
-*/
-
-
-/**
- * @brief The function is used to enable PS2 specified interrupt.
- *
- * @param[in] u32Mask The specified interrupt of PS2 module:
- * - \ref PS2_CTL_TXIEN_Msk : PS2 Tx interrupt
- * - \ref PS2_CTL_RXIEN_Msk : PS2 Rx interrupt
- *
- * @return None
- */
-void PS2_EnableInt(uint32_t u32Mask)
-{
- PS2->CTL |= u32Mask;
-}
-
-/**
- * @brief The function is used to disable PS2 specified interrupt.
- *
- * @param[in] u32Mask The specified interrupt of PS2 module:
- * - \ref PS2_CTL_TXIEN_Msk : PS2 Tx interrupt
- * - \ref PS2_CTL_RXIEN_Msk : PS2 Rx interrupt
- *
- * @return None
- */
-void PS2_DisableInt(uint32_t u32Mask)
-{
- PS2->CTL &= ~u32Mask;
-}
-
-/**
- * @brief This function use to enable PS2 function and set one byte per trnasfer.
- *
- * @param None
- *
- * @return None
- */
-void PS2_Open(void)
-{
- /* Reset PS2 device */
- SYS->IPRST1 |= SYS_IPRST1_PS2RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_PS2RST_Msk;
-
- /* Enable PS2 module */
- PS2->CTL |= PS2_CTL_PS2EN_Msk;
-
- /* Set One byte per trnasfer */
- PS2->CTL &= ~PS2_CTL_TXFDEPTH_Msk;
-
- /* Clear Tx FIFO */
- PS2->CTL |= PS2_CTL_CLRFIFO_Msk;
- PS2->CTL &= (~PS2_CTL_CLRFIFO_Msk);
-}
-
-/**
- * @brief This function use to disable PS2 function.
- *
- * @param None
- *
- * @return None
- */
-void PS2_Close(void)
-{
- /* Enable PS2 module */
- PS2->CTL &= ~PS2_CTL_PS2EN_Msk;
-}
-
-/**
- * @brief This function use to read PS2 Rx data.
- *
- * @param None
- *
- * @return Rx data
- */
-uint8_t PS2_Read(void)
-{
- return (uint8_t)(PS2->RXDAT & PS2_RXDAT_DAT_Msk);
-}
-
-/**
- * @brief This function use to transmit PS2 data.
- *
- * @param[in] pu32Buf The buffer to send the data to PS2 transmission FIFO.
- * @param[in] u32ByteCount The byte number of data.
- *
- * @return FALSE: transmit data time-out
- * TRUE: transmit data successful
- */
-int32_t PS2_Write(uint32_t *pu32Buf, uint32_t u32ByteCount)
-{
- uint32_t u32TxFIFO_Depth = 16;
- uint32_t u32delayno, txcnt, remainder;
- uint8_t i=0;
-
- txcnt = u32ByteCount / u32TxFIFO_Depth;
-
- remainder = u32ByteCount % u32TxFIFO_Depth;
- if(remainder) txcnt++;
-
- u32delayno = 0;
- while (!(PS2->STATUS & PS2_STATUS_TXEMPTY_Msk)) {
- u32delayno++;
- if (u32delayno >= 0xF0000000)
- return FALSE; // Time Out
- }
-
- if(u32ByteCount >= u32TxFIFO_Depth)//Tx fifo is 16 bytes
- PS2_SET_TX_BYTE_CNT(u32TxFIFO_Depth);
-
- do {
- u32delayno = 0;
- while (!(PS2->STATUS & PS2_STATUS_TXEMPTY_Msk)) {
- u32delayno++;
- if(u32delayno >= 0xF0000000)
- return FALSE; // Time Out
- }
-
- if((txcnt == 1) && (remainder != 0))
- PS2_SET_TX_BYTE_CNT(u32ByteCount);
-
- PS2->TXDAT0 = pu32Buf[i];
- PS2->TXDAT1 = pu32Buf[i+1];
- PS2->TXDAT2 = pu32Buf[i+2];
- PS2->TXDAT3 = pu32Buf[i+3];
-
- i = i + 4;
-
- } while(--txcnt);
-
- u32delayno = 0;
- while(!(PS2->STATUS & PS2_STATUS_TXEMPTY_Msk)) {
- u32delayno++;
- if(u32delayno >= 0xF0000000)
- return FALSE; // Time Out
- }
-
- return TRUE;
-
-}
-
-
-/*@}*/ /* end of group NUC472_442_PS2_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_PS2_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_ps2.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,231 +0,0 @@
-/**************************************************************************//**
- * @file PS2.h
- * @version V0.10
- * $Revision: 6 $
- * $Date: 14/10/06 1:58p $
- * @brief NUC472/NUC442 PS2 Driver Header File
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- ******************************************************************************/
-#ifndef __PS2_H__
-#define __PS2_H__
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Include related headers */
-/*---------------------------------------------------------------------------------------------------------*/
-#include "NUC472_442.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PS2_Driver PS2 Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_PS2_EXPORTED_FUNCTIONS PS2 Exported Functions
- @{
-*/
-
-
-/**
- * @brief This function use to set TX FIFO length.
- *
- * @param[in] u32Count TX FIFO length
- *
- * @return None
- * \hideinitializer
- */
-#define PS2_SET_TX_BYTE_CNT(u32Count) (PS2->CTL = (PS2->CTL & ~PS2_CTL_TXFDEPTH_Msk) \
- | ((u32Count-1) << PS2_CTL_TXFDEPTH_Pos))
-
-/**
- * @brief This function use to get PS2 status.
- *
- * @param None
- *
- * @return PS2 status
- * \hideinitializer
- */
-#define PS2_GET_STATUS() (PS2->STATUS)
-
-/**
- * @brief This function use to clear PS2 status.
- *
- * @param[in] u32Mask Clear the specified status of Ps2 module:
- * \ref PS2_STATUS_FRAMEERR_Msk , \ref PS2_STATUS_RXOV_Msk
- *
- * @return None
- */
-#define PS2_CLR_STATUS(u32Mask) (PS2D->PS2STATUS = u32Mask)
-
-/**
- * @brief This function use to clear PS2 Tx FIFO.
- *
- * @param None
- *
- * @return None
- * \hideinitializer
- */
-__STATIC_INLINE void PS2_CLEAR_TX_FIFO(void)
-{
- PS2->CTL |= PS2_CTL_CLRFIFO_Msk;
- PS2->CTL &= ~PS2_CTL_CLRFIFO_Msk;
-}
-
-/**
- * @brief This function use to clear PS2 Rx interrupt.
- *
- * @param None
- *
- * @return None
- * \hideinitializer
- */
-#define PS2_CLR_RX_INT_FLAG() (PS2->INTSTS = PS2_INTSTS_RXIF_Msk)
-
-/**
- * @brief This function use to clear PS2 Tx interrupt.
- *
- * @param None
- *
- * @return None
- * \hideinitializer
- */
-#define PS2_CLR_TX_INT_FLAG() (PS2->INTSTS = PS2_INTSTS_TXIF_Msk)
-
-/**
- * @brief This function use to get PS2 interrupt.
- *
- * @param[in] u32IntFlag interrupt flag: \ref PS2_INTSTS_TXIF_Msk , \ref PS2_INTSTS_RXIF_Msk
- *
- * @return 1: interrupt occurs
- * 0: interrupt not occurs
- * \hideinitializer
- */
-#define PS2_GET_INT_FLAG(u32IntFlag) ((PS2->INTSTS & u32IntFlag)?1:0)
-
-/**
- * @brief This function use to set PS2CLK and PS2DATA pins are controlled by hardware.
- *
- * @param None
- *
- * @return None
- * \hideinitializer
- */
-#define PS2_DISABLE_OVERRIDE() (PS2->CTL &= ~PS2_CTL_PS2EN_Msk)
-
-/**
- * @brief This function use to set PS2CLK and PS2DATA pins are controlled by software.
- *
- * @param None
- *
- * @return None
- * \hideinitializer
- */
-#define PS2_ENABLE_OVERRIDE() (PS2->CTL |= PS2_CTL_PS2EN_Msk)
-
-/**
- * @brief This function use to get indicates which data byte in transmit data shift register.
- *
- * @param None
- *
- * @return The indicates which data byte in transmit data shift register.
- * \hideinitializer
- */
-#define PS2_GET_TX_BYTE_INDEX() ((PS2->STATUS & PS2_STATUS_BYTEIDX_Msk) >> PS2_STATUS_BYTEIDX_Pos)
-
-/**
- * @brief This function use to set PS2DATA Pin low.
- *
- * @param None
- *
- * @return None.
- * \hideinitializer
- */
-#define PS2_SET_DATA_LOW() (PS2->CTL &= ~PS2_CTL_FPS2DAT_Msk)
-
-/**
- * @brief This function use to set PS2DATA Pin high.
- *
- * @param None
- *
- * @return None.
- * \hideinitializer
- */
-#define PS2_SET_DATA_HIGH() (PS2->CTL |= PS2_CTL_FPS2DAT_Msk)
-
-/**
- * @brief This function use to set PS2CLK Pin low.
- *
- * @param None
- *
- * @return None.
- * \hideinitializer
- */
-#define PS2_SET_CLK_LOW() (PS2->CTL &= ~PS2_CTL_FPS2CLK_Msk)
-
-/**
- * @brief This function use to set PS2CLK Pin high.
- *
- * @param None
- *
- * @return None.
- * \hideinitializer
- */
-#define PS2_SET_CLK_HIGH() (PS2->CTL |= PS2_CTL_FPS2CLK_Msk)
-
-/**
- * @brief If Parity error or Stop bit is Not Received Correctly, Acknowledge will Not be Sent to host at 12th clock.
- *
- * @param None
- *
- * @return None.
- * \hideinitializer
- */
-#define PS2_DISABLE_ACK_ALWAYS() (PS2->CTL |= PS2_CTL_ACK_Msk)
-
-/**
- * @brief Always sends acknowledge to host at 12th clock for host to device communication.
- *
- * @param None
- *
- * @return None.
- * \hideinitializer
- */
-#define PS2_ENABLE_ACK_ALWAYS() (PS2->CTL &= ~PS2_CTL_ACK_Msk)
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Define Function Prototypes */
-/*---------------------------------------------------------------------------------------------------------*/
-
-void PS2_Open(void);
-void PS2_Close(void);
-uint8_t PS2_Read(void);
-int32_t PS2_Write(uint32_t *pu32Buf, uint32_t u32ByteCount);
-void PS2_EnableInt(uint32_t u32Mask);
-void PS2_DisableInt(uint32_t u32Mask);
-
-
-/*@}*/ /* end of group NUC472_442_PS2_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_PS2_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__PS2_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,803 +0,0 @@
-/**************************************************************************//**
- * @file PWM.c
- * @version V1.00
- * $Revision: 26 $
- * $Date: 15/11/18 2:34p $
- * @brief NUC472/NUC442 PWM driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PWM_Driver PWM Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
- @{
-*/
-
-/**
- * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Frequency Target generator frequency
- * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
- * @return Nearest frequency clock in nano second
- * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
- * existing frequency of other channel.
- */
-uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32Frequency,
- uint32_t u32DutyCycle)
-{
- return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1);
-}
-
-/**
- * @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2
- * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
- * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2
- * @return Nearest frequency clock in nano second
- * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
- * existing frequency of other channel.
- */
-uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32Frequency,
- uint32_t u32DutyCycle,
- uint32_t u32Frequency2)
-{
- uint32_t i;
- uint32_t u32PWM_CLock = __HIRC;
- uint8_t u8Divider = 1, u8Prescale = 0xFF;
- uint16_t u16CNR = 0xFFFF;
-
- if (pwm == PWM0) {
- if (u32ChannelNum < 2) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 4) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 6) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __LIRC;
- }
- } else if (pwm == PWM1) {
- if (u32ChannelNum < 2) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 4) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 6) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __LIRC;
- }
- }
-
- for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
- // Note: Support frequency < 1
- i = (uint64_t) u32PWM_CLock * u32Frequency2 / u32Frequency / u8Divider;
- // If target value is larger than CNR * prescale, need to use a larger divider
- if(i > (0x10000 * 0x100))
- continue;
-
- // CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
- u8Prescale = (i + 0xFFFF)/ 0x10000;
-
- // u8Prescale must at least be 2, otherwise the output stop
- if(u8Prescale < 3)
- u8Prescale = 2;
-
- i /= u8Prescale;
-
- if(i <= 0x10000) {
- if(i == 1)
- u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
- else
- u16CNR = i;
- break;
- }
-
- }
- // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
- i = u32PWM_CLock / (u8Prescale * u8Divider * u16CNR);
-
- u8Prescale -= 1;
- u16CNR -= 1;
- // convert to real register value
- if(u8Divider == 1)
- u8Divider = 4;
- else if (u8Divider == 2)
- u8Divider = 0;
- else if (u8Divider == 4)
- u8Divider = 1;
- else if (u8Divider == 8)
- u8Divider = 2;
- else // 16
- u8Divider = 3;
-
- // every two channels share a prescaler
- while((pwm->SBS[u32ChannelNum] & 1) == 1);
- pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
- pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
- pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
- if(u32DutyCycle == 0)
- pwm->CMPDAT[u32ChannelNum] = 0;
- else
- pwm->CMPDAT[u32ChannelNum] = u32DutyCycle * (u16CNR + 1) / 100 - 1;
- pwm->PERIOD[u32ChannelNum] = u16CNR;
-
- return(i);
-}
-
-/**
- * @brief This function config PWM capture and get the nearest unit time
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32UnitTimeNsec Unit time of counter
- * @param[in] u32CaptureEdge Condition to latch the counter
- * @return Nearest unit time in nano second
- * @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
- * existing frequency of other channel.
- */
-uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32UnitTimeNsec,
- uint32_t u32CaptureEdge)
-{
- uint32_t i;
- uint32_t u32PWM_CLock = __HIRC;
- uint8_t u8Divider = 1, u8Prescale = 0xFF;
- uint16_t u16CNR = 0xFFFF;
-
- if (pwm == PWM0) {
- if (u32ChannelNum < 2) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 0)
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 1)
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 2)
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 3)
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH01SEL_Msk) == 4)
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 4) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH23SEL_Pos))
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 6) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM0CH45SEL_Pos))
- u32PWM_CLock = __LIRC;
- }
- } else if (pwm == PWM1) {
- if (u32ChannelNum < 2) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 4) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
- u32PWM_CLock = __LIRC;
- } else if (u32ChannelNum < 6) {
- if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __HXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __LXT;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = SystemCoreClock;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __HIRC;
- else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH45SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH45SEL_Pos))
- u32PWM_CLock = __LIRC;
- }
- }
-
- for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
- i = ((u32PWM_CLock / u8Divider) * u32UnitTimeNsec) / 1000000000;
-
- // If target value is larger than 0xFF, need to use a larger divider
- if(i > (0xFF))
- continue;
-
- u8Prescale = i;
-
- // u8Prescale must at least be 2, otherwise the output stop
- if(u8Prescale < 3)
- u8Prescale = 2;
-
- break;
- }
-
- // Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
- i = (u8Prescale * u8Divider) * 1000000000/ u32PWM_CLock;
-
- u8Prescale -= 1;
- u16CNR -= 1;
- // convert to real register value
- if(u8Divider == 1)
- u8Divider = 4;
- else if (u8Divider == 2)
- u8Divider = 0;
- else if (u8Divider == 4)
- u8Divider = 1;
- else if (u8Divider == 8)
- u8Divider = 2;
- else // 16
- u8Divider = 3;
-
- // every two channels share a prescaler
- while((pwm->SBS[u32ChannelNum] & 1) == 1);
- pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
- pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
- pwm->CTL |= 1 << (PWM_CTL_CNTMODE_Pos + u32ChannelNum);
- pwm->PERIOD[u32ChannelNum] = u16CNR;
-
- return(i);
-}
-
-/**
- * @brief This function start PWM module
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- */
-void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
-{
- pwm->CNTEN |= u32ChannelMask;
-}
-
-/**
- * @brief This function stop PWM module
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- */
-void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
-{
- uint32_t i;
- for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
- if(u32ChannelMask & (1 << i)) {
- *(__IO uint32_t *) (&pwm->CNTEN + 1 * i) = 0;
- }
- }
-
-}
-
-/**
- * @brief This function stop PWM generation immediately by clear channel enable bit
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Bit 0 is channel 0, bit 1 is channel 1...
- * @return None
- */
-void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
-{
- pwm->CNTEN &= ~u32ChannelMask;
-}
-
-/**
- * @brief This function enable selected channel to trigger ADC
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
- * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
- * - \ref PWM_TRIGGER_ADC_CENTER_POINT
- * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
- * - \ref PWM_TRIGGER_ADC_RISING_EDGE_POINT
- * @return None
- */
-void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
-{
- pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
- PWM_TRIGGER_ADC_CENTER_POINT |
- PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
- PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum))) | (u32Condition << (1 * u32ChannelNum));
-}
-
-/**
- * @brief This function disable selected channel to trigger ADC
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- */
-void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- pwm->TRGADCTL = (pwm->TRGADCTL & ~((PWM_TRIGGER_ADC_PERIOD_POINT |
- PWM_TRIGGER_ADC_CENTER_POINT |
- PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
- PWM_TRIGGER_ADC_RISING_EDGE_POINT ) << (1 * u32ChannelNum)));
-}
-
-/**
- * @brief This function clear selected channel trigger ADC flag
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Condition PWM triggered ADC flag to be cleared. A combination of following flags:
- * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
- * - \ref PWM_TRIGGER_ADC_CENTER_POINT
- * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
- * - \ref PWM_TRIGGER_ADC_RISING_EDGE_POINT
- * @return None
- */
-void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
-{
- pwm->TRGADCSTS |= (u32Condition << (1 * u32ChannelNum));
-}
-
-/**
- * @brief This function get selected channel trigger ADC flag
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Combination of following trigger conditions which triggered ADC
- * - \ref PWM_TRIGGER_ADC_PERIOD_POINT
- * - \ref PWM_TRIGGER_ADC_CENTER_POINT
- * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
- * - \ref PWM_TRIGGER_ADC_FALLING_EDGE_POINT
- */
-uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- uint32_t u32Ret;
-
- u32Ret = pwm->TRGADCSTS >> u32ChannelNum;
-
- return (u32Ret & (PWM_TRIGGER_ADC_PERIOD_POINT |
- PWM_TRIGGER_ADC_CENTER_POINT |
- PWM_TRIGGER_ADC_FALLING_EDGE_POINT |
- PWM_TRIGGER_ADC_FALLING_EDGE_POINT));
-}
-
-/**
- * @brief This function enable fault brake of selected channels
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask This parameter is not used
- * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
- * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
- * , bit 6 represent D6, and bit 7 represents D7
- * @param[in] u32BrakeSource Fault brake source, could be one of following source
- * - \ref PWM_BRK0_BKP0
- * - \ref PWM_BRK0_CPO0
- * - \ref PWM_BRK0_CPO1
- * - \ref PWM_BRK0_CPO2
- * - \ref PWM_BRK1_LVDBK
- * - \ref PWM_BK1SEL_BKP1
- * - \ref PWM_BK1SEL_CPO0
- * - \ref PWM_BK1SEL_CPO1
- * @return None
- */
-void PWM_EnableFaultBrake (PWM_T *pwm,
- uint32_t u32ChannelMask,
- uint32_t u32LevelMask,
- uint32_t u32BrakeSource)
-{
- if ((u32BrakeSource == PWM_BRK0_BKP0)||(u32BrakeSource == PWM_BRK0_CPO0)||(u32BrakeSource == PWM_BRK0_CPO1)||(u32BrakeSource == PWM_BRK0_CPO2))
- pwm->BRKCTL |= (u32BrakeSource | PWM_BRKCTL_BRK0EN_Msk);
- else if (u32BrakeSource == PWM_BRK1_LVDBK)
- pwm->BRKCTL |= PWM_BRKCTL_LVDBKEN_Msk;
- else
- pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BK1SEL_Msk) | u32BrakeSource | PWM_BRKCTL_BRK1EN_Msk;
-
- pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BKOD_Msk) | (u32LevelMask << PWM_BRKCTL_BKOD_Pos);
-
-}
-
-/**
- * @brief This function clear fault brake flag
- * @param[in] pwm The base address of PWM module
- * @param[in] u32BrakeSource Fault brake source 0 or 1
- * 0: brake 0, 1: brake 1
- * @return None
- * @note After fault brake occurred, application must clear fault brake source before re-enable PWM output
- */
-void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
-{
- if (u32BrakeSource == 0)
- pwm->INTSTS = (PWM_INTSTS_BRKLK0_Msk | PWM_INTSTS_BRKIF0_Msk);
- else
- pwm->INTSTS = PWM_INTSTS_BRKIF1_Msk;
-}
-
-/**
- * @brief This function enables PWM capture of selected channels
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
- * @return None
- */
-void PWM_EnableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
-{
- pwm->CAPCTL |= u32ChannelMask;
- pwm->CAPINEN |= u32ChannelMask;
- pwm->CTL |= (u32ChannelMask << PWM_CTL_CNTMODE_Pos);
-}
-
-/**
- * @brief This function disables PWM capture of selected channels
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
- * @return None
- */
-void PWM_DisableCapture (PWM_T *pwm, uint32_t u32ChannelMask)
-{
- pwm->CAPCTL &= ~u32ChannelMask;
- pwm->CAPINEN &= ~u32ChannelMask;
-}
-
-/**
- * @brief This function enables PWM output generation of selected channels
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
- * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
- * @return None
- */
-void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
-{
- pwm->POEN |= u32ChannelMask;
-}
-
-/**
- * @brief This function disables PWM output generation of selected channels
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
- * @return None
- */
-void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
-{
- pwm->POEN &= ~u32ChannelMask;
-}
-
-/**
- * @brief This function enable Dead zone of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no
- * dead zone.
- * @return None
- */
-void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
-{
- // every two channels shares the same setting
- u32ChannelNum >>= 1;
- // set duration
- pwm->DTCTL = (pwm->DTCTL & ~(PWM_DTCTL_DTCNT01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
- // enable dead zone
- pwm->DTCTL |= (PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
-}
-
-/**
- * @brief This function disable Dead zone of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- */
-void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- // every two channels shares the same setting
- u32ChannelNum >>= 1;
- // enable dead zone
- pwm->DTCTL &= ~(PWM_DTCTL_DTEN01_Msk << u32ChannelNum);
-}
-
-/**
- * @brief This function enable capture interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Edge Capture interrupt type. It could be either
- * - \ref PWM_FALLING_LATCH_INT_ENABLE
- * - \ref PWM_RISING_LATCH_INT_ENABLE
- * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
- * @return None
- */
-void PWM_EnableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
-{
- // enable capture interrupt
- pwm->INTEN |= (u32Edge << u32ChannelNum);
-}
-
-/**
- * @brief This function disable capture interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Edge Capture interrupt type. It could be either
- * - \ref PWM_FALLING_LATCH_INT_ENABLE
- * - \ref PWM_RISING_LATCH_INT_ENABLE
- * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
- * @return None
- */
-void PWM_DisableCaptureInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
-{
- // disable capture interrupt
- pwm->INTEN &= ~(u32Edge << u32ChannelNum);
-}
-
-/**
- * @brief This function clear capture interrupt flag of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Edge Capture interrupt type. It could be either
- * - \ref PWM_FALLING_LATCH_INT_ENABLE
- * - \ref PWM_RISING_LATCH_INT_ENABLE
- * - \ref PWM_RISING_FALLING_LATCH_INT_ENABLE
- * @return None
- */
-void PWM_ClearCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
-{
- // disable capture interrupt flag
- pwm->INTSTS = (u32Edge << u32ChannelNum);
-}
-
-/**
- * @brief This function get capture interrupt flag of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Capture interrupt flag of specified channel
- * @retval 0 Capture interrupt did not occurred
- * @retval PWM_RISING_LATCH_INT_FLAG Rising edge latch interrupt occurred
- * @retval PWM_FALLING_LATCH_INT_FLAG Falling edge latch interrupt occurred
- * @retval PWM_RISING_FALLING_LATCH_INT_FLAG Rising and falling edge latch interrupt occurred
- */
-uint32_t PWM_GetCaptureIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return ((pwm->INTSTS >> u32ChannelNum) & PWM_RISING_FALLING_LATCH_INT_FLAG);
-}
-
-/**
- * @brief This function enable duty interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32IntDutyType Duty interrupt type. It could be either
- * - \ref PWM_DUTY_INT_MATCH_CMR_UP
- * - \ref PWM_DUTY_INT_MATCH_CMR_DN
- * @return None
- */
-void PWM_EnableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
-{
- // set duty interrupt type
- pwm->INTCTL = (pwm->INTCTL & ~(PWM_DUTY_INT_MATCH_CMR_UP << u32ChannelNum)) | (u32IntDutyType << u32ChannelNum);
- // enable duty interrupt
- pwm->INTEN |= ((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
-}
-
-/**
- * @brief This function disable duty interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- */
-void PWM_DisableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- pwm->INTEN &= ~((1 << PWM_INTEN_DIEN_Pos) << u32ChannelNum);
-}
-
-/**
- * @brief This function clears duty interrupt flag of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- */
-void PWM_ClearDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- // write 1 clear
- pwm->INTSTS = (1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum;
-}
-
-/**
- * @brief This function get duty interrupt flag of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Duty interrupt flag of specified channel
- * @retval 0 Duty interrupt did not occurred
- * @retval 1 Duty interrupt occurred
- */
-uint32_t PWM_GetDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return(pwm->INTSTS & ((1 << PWM_INTSTS_DIF_Pos) << u32ChannelNum) ? 1 : 0);
-}
-
-/**
- * @brief This function enable fault brake interrupt
- * @param[in] pwm The base address of PWM module
- * @param[in] u32BrakeSource This parameter is not used
- * @return None
- */
-void PWM_EnableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
-{
- pwm->INTEN |= PWM_INTEN_BRKIEN_Msk;
-}
-
-/**
- * @brief This function disable fault brake interrupt
- * @param[in] pwm The base address of PWM module
- * @param[in] u32BrakeSource This parameter is not used
- * @return None
- */
-void PWM_DisableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
-{
- pwm->INTEN &= ~PWM_INTEN_BRKIEN_Msk;
-}
-
-/**
- * @brief This function clear fault brake interrupt of selected source
- * @param[in] pwm The base address of PWM module
- * @param[in] u32BrakeSource Fault brake source, could be either
- * - \ref PWM_INTSTS_BRKIF0_Msk, or
- * - \ref PWM_INTSTS_BRKIF1_Msk
- * @return None
- */
-void PWM_ClearFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
-{
- pwm->INTSTS = u32BrakeSource;
-}
-
-/**
- * @brief This function get fault brake interrupt of selected source
- * @param[in] pwm The base address of PWM module
- * @param[in] u32BrakeSource Fault brake source, could be either
- * - \ref PWM_INTSTS_BRKIF0_Msk, or
- * - \ref PWM_INTSTS_BRKIF1_Msk
- * @return Fault brake interrupt flag of specified source
- * @retval 0 Fault brake interrupt did not occurred
- * @retval 1 Fault brake interrupt occurred
- */
-uint32_t PWM_GetFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
-{
- return (pwm->INTSTS & u32BrakeSource ? 1 : 0);
-}
-
-/**
- * @brief This function enable period interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32IntPeriodType Period interrupt type, could be either
- * - \ref PWM_PERIOD_INT_UNDERFLOW
- * - \ref PWM_PERIOD_INT_MATCH_CNR
- * @return None
- * @note All channels share the same period interrupt type setting.
- */
-void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
-{
- // set period interrupt type
- pwm->INTCTL = (pwm->INTCTL & ~(PWM_PERIOD_INT_MATCH_CNR << u32ChannelNum)) | (u32IntPeriodType << u32ChannelNum);
- // enable period interrupt
- pwm->INTEN |= ((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
-}
-
-/**
- * @brief This function disable period interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- */
-void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- pwm->INTEN &= ~((1 << PWM_INTEN_PIEN_Pos) << u32ChannelNum);
-}
-
-/**
- * @brief This function clear period interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- */
-void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- // write 1 clear
- pwm->INTSTS = ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum);
-}
-
-/**
- * @brief This function get period interrupt of selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return Period interrupt flag of specified channel
- * @retval 0 Period interrupt did not occurred
- * @retval 1 Period interrupt occurred
- */
-uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
-{
- return(pwm->INTSTS & ((1 << PWM_INTSTS_PIF_Pos) << u32ChannelNum) ? 1 : 0);
-}
-
-
-
-/*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_PWM_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,301 +0,0 @@
-/**************************************************************************//**
- * @file pwm.h
- * @version V1.00
- * $Revision: 22 $
- * $Date: 15/11/16 2:08p $
- * @brief NUC472/NUC442 PWM driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __PWM_H__
-#define __PWM_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PWM_Driver PWM Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_PWM_EXPORTED_CONSTANTS PWM Exported Constants
- @{
-*/
-#define PWM_CHANNEL_NUM (6) /*!< PWM channel number \hideinitializer */
-#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
-#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
-#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
-#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
-#define PWM_CH4 (4UL) /*!< PWM channel 4 \hideinitializer */
-#define PWM_CH5 (5UL) /*!< PWM channel 5 \hideinitializer */
-#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
-#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
-#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
-#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
-#define PWM_CH_4_MASK (16UL) /*!< PWM channel 4 mask \hideinitializer */
-#define PWM_CH_5_MASK (32UL) /*!< PWM channel 5 mask \hideinitializer */
-#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
-#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
-#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
-#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */
-#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */
-#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */
-#define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */
-#define PWM_TRIGGER_ADC_RISING_EDGE_POINT (0x1000000UL) /*!< PWM trigger ADC while output rising edge is detected \hideinitializer */
-#define PWM_TRIGGER_ADC_FALLING_EDGE_POINT (0x10000UL) /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */
-#define PWM_TRIGGER_ADC_CENTER_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */
-#define PWM_TRIGGER_ADC_PERIOD_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
-#define PWM_BRK0_BKP0 (PWM_BRKCTL_BRK0EN_Msk) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
-#define PWM_BRK0_CPO0 (PWM_BRKCTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
-#define PWM_BRK0_CPO1 (PWM_BRKCTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
-#define PWM_BRK0_CPO2 (PWM_BRKCTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
-#define PWM_BRK1_LVDBK (PWM_BRKCTL_LVDBKEN_Msk) /*!< Brake1 signal source from level detect \hideinitializer */
-#define PWM_BK1SEL_BKP1 (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
-#define PWM_BK1SEL_CPO0 (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
-#define PWM_BK1SEL_CPO1 (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
-#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow \hideinitializer */
-#define PWM_PERIOD_INT_MATCH_CNR (1UL) /*!< PWM period interrupt trigger if counter match CNR \hideinitializer */
-#define PWM_DUTY_INT_MATCH_CMR_DN (0) /*!< PWM duty interrupt if counter match CNR during down counting \hideinitializer */
-#define PWM_DUTY_INT_MATCH_CMR_UP (0x100UL) /*!< PWM duty interrupt if counter match CNR during up counting \hideinitializer */
-#define PWM_FALLING_LATCH_INT_ENABLE (0x1000000UL) /*!< PWM falling latch interrupt enable \hideinitializer */
-#define PWM_RISING_LATCH_INT_ENABLE (0x10000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
-#define PWM_RISING_FALLING_LATCH_INT_ENABLE (0x1010000UL) /*!< PWM rising latch interrupt enable \hideinitializer */
-#define PWM_FALLING_LATCH_INT_FLAG (PWM_FALLING_LATCH_INT_ENABLE) /*!< PWM falling latch condition happened \hideinitializer */
-#define PWM_RISING_LATCH_INT_FLAG (PWM_RISING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
-#define PWM_RISING_FALLING_LATCH_INT_FLAG (PWM_RISING_FALLING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_PWM_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
- @{
-*/
-
-/**
- * @brief This macro enable complementary mode
- * @param[in] pwm The base address of PWM module
- * @return None
- * \hideinitializer
- */
-#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_OUTMODE_Msk)
-
-/**
- * @brief This macro disable complementary mode, and enable independent mode.
- * @param[in] pwm The base address of PWM module
- * @return None
- * \hideinitializer
- */
-#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_OUTMODE_Msk)
-
-/**
- * @brief This macro enable group mode
- * @param[in] pwm The base address of PWM module
- * @return None
- * \hideinitializer
- */
-#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_GROUPEN_Msk)
-
-/**
- * @brief This macro disable group mode
- * @param[in] pwm The base address of PWM module
- * @return None
- * \hideinitializer
- */
-#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_GROUPEN_Msk)
-
-/**
- * @brief This macro enable synchronous mode
- * @param[in] pwm The base address of PWM module
- * @return None
- * \hideinitializer
- */
-#define PWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_SYNCEN_Msk)
-
-/**
- * @brief This macro disable synchronous mode, and enable independent mode.
- * @param[in] pwm The base address of PWM module
- * @return None
- * \hideinitializer
- */
-#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_SYNCEN_Msk)
-
-/**
- * @brief This macro enable output inverter of specified channel(s)
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @return None
- * \hideinitializer
- */
-#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->CTL = (((pwm)->CTL & ~PWM_CTL_PINV_Msk) | ((u32ChannelMask) << PWM_CTL_PINV_Pos)))
-
-/**
- * @brief This macro get captured rising data
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * \hideinitializer
- */
-#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->RCAPDAT0 + 2 * (u32ChannelNum)))
-
-/**
- * @brief This macro get captured falling data
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @return None
- * \hideinitializer
- */
-#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->FCAPDAT0 + 2 * (u32ChannelNum)))
-
-/**
- * @brief This macro mask output output logic to high or low
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @param[in] u32LevelMask Output logic to high or low
- * @return None
- * \hideinitializer
- */
-#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) ((pwm)->MSKEN |= (u32ChannelMask))
-
-/**
- * @brief This macro set the prescaler of the selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
- * @return None
- * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
- * channel 1 will also be affected.
- * \hideinitializer
- */
-#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
- (pwm->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
-
-/**
- * @brief This macro set the divider of the selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32Divider Clock divider of specified channel. Valid values are
- * - \ref PWM_CLK_DIV_1
- * - \ref PWM_CLK_DIV_2
- * - \ref PWM_CLK_DIV_4
- * - \ref PWM_CLK_DIV_8
- * - \ref PWM_CLK_DIV_16
- * @return None
- * \hideinitializer
- */
-#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
- ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
-
-/**
- * @brief This macro set the duty of the selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
- * @return None
- * @note This new setting will take effect on next PWM period
- * \hideinitializer
- */
-#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
-
-/**
- * @brief This macro set the period of the selected channel
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
- * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
- * @return None
- * @note This new setting will take effect on next PWM period
- * @note PWM counter will stop if period length set to 0
- * \hideinitializer
- */
-#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
-
-/**
- * @brief This macro set the PWM aligned type
- * @param[in] pwm The base address of PWM module
- * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
- * Bit 0 represents channel 0, bit 1 represents channel 1...
- * @param[in] u32AlignedType PWM aligned type, valid values are:
- * - \ref PWM_EDGE_ALIGNED
- * - \ref PWM_CENTER_ALIGNED
- * @return None
- * \hideinitializer
- */
-#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
-do { \
- (pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk); \
- if ((u32AlignedType) == PWM_CENTER_ALIGNED) \
- (pwm)->CTL = ((pwm)->CTL | ((u32ChannelMask) << PWM_CTL_CNTTYPE_Pos)); \
-} while(0)
-
-
-uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32Frequency,
- uint32_t u32DutyCycle);
-uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32Frequency,
- uint32_t u32DutyCycle,
- uint32_t u32Frequency2);
-uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
- uint32_t u32ChannelNum,
- uint32_t u32UnitTimeNsec,
- uint32_t u32CaptureEdge);
-void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
-void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
-uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableFaultBrake(PWM_T *pwm,
- uint32_t u32ChannelMask,
- uint32_t u32LevelMask,
- uint32_t u32BrakeSource);
-void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
-void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
-void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
-void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
-void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
-void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
-uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
-void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
-void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
-void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
-uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
-void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
-void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
-void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
-
-
-
-/*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_PWM_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__PWM_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,858 +0,0 @@
-/**************************************************************************//**
- * @file rtc.c
- * @version V1.00
- * $Revision: 17 $
- * $Date: 14/10/03 11:51a $
- * @brief NUC472/NUC442 RTC driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-
-#include <stdio.h>
-#include "NUC472_442.h"
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Includes of local headers */
-/*---------------------------------------------------------------------------------------------------------*/
-
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_RTC_Driver RTC Driver
- @{
-*/
-/// @cond HIDDEN_SYMBOLS
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Macro, type and constant definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define RTC_GLOBALS
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Global file scope (static) variables */
-/*---------------------------------------------------------------------------------------------------------*/
-static volatile uint32_t g_u32Reg, g_u32Reg1,g_u32hiYear,g_u32loYear,g_u32hiMonth,g_u32loMonth,g_u32hiDay,g_u32loDay;
-static volatile uint32_t g_u32hiHour,g_u32loHour,g_u32hiMin,g_u32loMin,g_u32hiSec,g_u32loSec;
-
-/// @endcond HIDDEN_SYMBOLS
-
-/** @addtogroup NUC472_442_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
- @{
-*/
-
-
-/**
- * @brief Set Frequency Compensation Data
- *
- * @param[in] i32FrequencyX100 Specify the RTC clock X100, ex: 3277365 means 32773.65.
- *
- * @return None
- *
- */
-void RTC_32KCalibration(int32_t i32FrequencyX100)
-{
- int32_t i32RegInt,i32RegFra ;
-
- /* Compute Integer and Fraction for RTC register*/
- i32RegInt = (i32FrequencyX100/100) - RTC_FCR_REFERENCE;
- i32RegFra = (((i32FrequencyX100%100)) * 60) / 100;
-
- /* Judge Integer part is reasonable */
- if ( (i32RegInt < 0) | (i32RegInt > 15) ) {
- return;
- }
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->FREQADJ = (uint32_t)((i32RegInt<<8) | i32RegFra);
-
-}
-
-/**
- * @brief This function is used to:
- * 1. Write initial key to let RTC start count. \n
- * 2. Input parameter indicates start time. \n
- * Null pointer for using default starting time. \n
- *
- * @param[in] sPt \n
- * Specify the time property and current time. It includes: \n
- * u32Year: Year value. \n
- * u32Month: Month value. \n
- * u32Day: Day value. \n
- * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
- * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
- * \ref RTC_SATURDAY] \n
- * u32Hour: Hour value. \n
- * u32Minute: Minute value. \n
- * u32Second: Second value. \n
- * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n
- * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n
- *
- * @return None
- *
- */
-void RTC_Open (S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32Reg;
-
- volatile int32_t i32delay=1000;
-
- if(RTC->INIT != 0x1) {
- RTC->INIT = RTC_INIT_KEY;
-
- while(RTC->INIT != 0x1);
- }
-
- if(sPt == NULL)
- return;
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Second, set RTC 24/12 hour setting */
- /*-----------------------------------------------------------------------------------------------------*/
- if (sPt->u32TimeScale == RTC_CLOCK_12) {
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
-
- /*-------------------------------------------------------------------------------------------------*/
- /* important, range of 12-hour PM mode is 21 up to 32 */
- /*-------------------------------------------------------------------------------------------------*/
- if (sPt->u32AmPm == RTC_PM)
- sPt->u32Hour += 20;
- } else { /* RTC_CLOCK_24 */
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC Calender Loading */
- /*-----------------------------------------------------------------------------------------------------*/
- u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
- u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
- u32Reg |= ((sPt->u32Month / 10) << 12);
- u32Reg |= ((sPt->u32Month % 10) << 8);
- u32Reg |= ((sPt->u32Day / 10) << 4);
- u32Reg |= (sPt->u32Day % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->CAL = (uint32_t)g_u32Reg;
-
- /*-----------------------------------------------------------------------------------------------------*/
- /* Set RTC Time Loading */
- /*-----------------------------------------------------------------------------------------------------*/
- u32Reg = ((sPt->u32Hour / 10) << 20);
- u32Reg |= ((sPt->u32Hour % 10) << 16);
- u32Reg |= ((sPt->u32Minute / 10) << 12);
- u32Reg |= ((sPt->u32Minute % 10) << 8);
- u32Reg |= ((sPt->u32Second / 10) << 4);
- u32Reg |= (sPt->u32Second % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->TIME = (uint32_t)g_u32Reg;
-
- RTC->WEEKDAY = sPt->u32DayOfWeek;
-
- /* Waiting for RTC settings stable */
- while(i32delay--);
-
-}
-
-/**
- * @brief Read current date/time from RTC setting
- *
- * @param[out] sPt \n
- * Specify the time property and current time. It includes: \n
- * u32Year: Year value \n
- * u32Month: Month value \n
- * u32Day: Day value \n
- * u32DayOfWeek: Day of week \n
- * u32Hour: Hour value \n
- * u32Minute: Minute value \n
- * u32Second: Second value \n
- * u32TimeScale: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24 \n
- * u8AmPm: \ref RTC_AM / \ref RTC_PM \n
- *
- * @return None
- *
- */
-void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32Tmp;
-
- sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
- sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of week */
-
- g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
- g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
- g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
- g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
- g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
- g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk);
-
- g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
- g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
- g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
- g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
- g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
- g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk);
-
- u32Tmp = (g_u32hiYear * 10); /* Compute to 20XX year */
- u32Tmp += g_u32loYear;
- sPt->u32Year = u32Tmp + RTC_YEAR2000;
-
- u32Tmp = (g_u32hiMonth * 10); /* Compute 0~12 month */
- sPt->u32Month = u32Tmp + g_u32loMonth;
-
- u32Tmp = (g_u32hiDay * 10); /* Compute 0~31 day */
- sPt->u32Day = u32Tmp + g_u32loDay;
-
- if (sPt->u32TimeScale == RTC_CLOCK_12) { /* Compute12/24 hour */
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp+= g_u32loHour;
- sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
-
- if (sPt->u32Hour >= 21) {
- sPt->u32AmPm = RTC_PM;
- sPt->u32Hour -= 20;
- } else {
- sPt->u32AmPm = RTC_AM;
- }
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp+= g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp+= g_u32loSec;
- sPt->u32Second = u32Tmp;
-
- } else {
- /* RTC_CLOCK_24 */
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp += g_u32loHour;
- sPt->u32Hour = u32Tmp;
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp += g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp += g_u32loSec;
- sPt->u32Second = u32Tmp;
- }
-
-}
-
-
-
-/**
- * @brief Read alarm date/time from RTC setting
- *
- * @param[out] sPt \n
- * Specify the time property and current time. It includes: \n
- * u32Year: Year value \n
- * u32Month: Month value \n
- * u32Day: Day value \n
- * u32DayOfWeek: Day of week \n
- * u32Hour: Hour value \n
- * u32Minute: Minute value \n
- * u32Second: Second value \n
- * u32TimeScale: \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24 \n
- * u8AmPm: \ref RTC_AM / \ref RTC_PM \n
- *
- * @return None
- *
- */
-void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32Tmp;
-
- sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */
- sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of week */
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
- g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
- g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
- g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
- g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
- g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk);
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
- g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
- g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
- g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
- g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
- g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk);
-
- u32Tmp = (g_u32hiYear * 10); /* Compute to 20XX year */
- u32Tmp += g_u32loYear;
- sPt->u32Year = u32Tmp + RTC_YEAR2000;
-
- u32Tmp = (g_u32hiMonth * 10); /* Compute 0~12 month */
- sPt->u32Month = u32Tmp + g_u32loMonth;
-
- u32Tmp = (g_u32hiDay * 10); /* Compute 0~31 day */
- sPt->u32Day = u32Tmp + g_u32loDay;
-
- if (sPt->u32TimeScale == RTC_CLOCK_12) { /* Compute12/24 hour */
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp += g_u32loHour;
- sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
-
- if (sPt->u32Hour >= 21) {
- sPt->u32AmPm = RTC_PM;
- sPt->u32Hour -= 20;
- } else {
- sPt->u32AmPm = RTC_AM;
- }
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp += g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp += g_u32loSec;
- sPt->u32Second = u32Tmp;
-
- } else {
- /* RTC_CLOCK_24 */
- u32Tmp = (g_u32hiHour * 10);
- u32Tmp += g_u32loHour;
- sPt->u32Hour = u32Tmp;
-
- u32Tmp = (g_u32hiMin * 10);
- u32Tmp+= g_u32loMin;
- sPt->u32Minute = u32Tmp;
-
- u32Tmp = (g_u32hiSec * 10);
- u32Tmp += g_u32loSec;
- sPt->u32Second = u32Tmp;
- }
-
-}
-
-
-
-/**
- * @brief This function is used to update date/time to RTC.
- *
- * @param[in] sPt \n
- * Specify the time property and current time. It includes: \n
- * u32Year: Year value. \n
- * u32Month: Month value. \n
- * u32Day: Day value. \n
- * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
- * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
- * \ref RTC_SATURDAY] \n
- * u32Hour: Hour value. \n
- * u32Minute: Minute value. \n
- * u32Second: Second value. \n
- * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n
- * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n
- *
- *
- * @return None
- *
- *
- */
-void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if (sPt->u32TimeScale == RTC_CLOCK_12) {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
-
- /*-----------------------------------------------------------------------------------------*/
- /* important, range of 12-hour PM mode is 21 up to 32 */
- /*-----------------------------------------------------------------------------------------*/
- if (sPt->u32AmPm == RTC_PM)
- sPt->u32Hour += 20;
- } else { /* RTC_CLOCK_24 */
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- RTC->WEEKDAY = sPt->u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
-
- u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
- u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
- u32Reg |= ((sPt->u32Month / 10) << 12);
- u32Reg |= ((sPt->u32Month % 10) << 8);
- u32Reg |= ((sPt->u32Day / 10) << 4);
- u32Reg |= (sPt->u32Day % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->CAL = (uint32_t)g_u32Reg;
-
- u32Reg = ((sPt->u32Hour / 10) << 20);
- u32Reg |= ((sPt->u32Hour % 10) << 16);
- u32Reg |= ((sPt->u32Minute / 10) << 12);
- u32Reg |= ((sPt->u32Minute % 10) << 8);
- u32Reg |= ((sPt->u32Second / 10) << 4);
- u32Reg |= (sPt->u32Second % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->TIME = (uint32_t)g_u32Reg;
-
-}
-
-/**
- * @brief This function is used to set alarm date/time to RTC.
- *
- * @param[in] sPt \n
- * Specify the time property and current time. It includes: \n
- * u32Year: Year value. \n
- * u32Month: Month value. \n
- * u32Day: Day value. \n
- * u32DayOfWeek: Day of week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
- * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
- * \ref RTC_SATURDAY] \n
- * u32Hour: Hour value. \n
- * u32Minute: Minute value. \n
- * u32Second: Second value. \n
- * u32TimeScale: [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24] \n
- * u8AmPm: [ \ref RTC_AM / \ref RTC_PM] \n
- *
- * @return None
- *
- */
-void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
-{
- uint32_t u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if (sPt->u32TimeScale == RTC_CLOCK_12) {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
-
- /*-----------------------------------------------------------------------------------------*/
- /* important, range of 12-hour PM mode is 21 up to 32 */
- /*-----------------------------------------------------------------------------------------*/
- if (sPt->u32AmPm == RTC_PM)
- sPt->u32Hour += 20;
- } else { /* RTC_CLOCK_24 */
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- RTC->WEEKDAY = sPt->u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
-
-
- u32Reg = ((sPt->u32Year - RTC_YEAR2000) / 10) << 20;
- u32Reg |= (((sPt->u32Year - RTC_YEAR2000) % 10) << 16);
- u32Reg |= ((sPt->u32Month / 10) << 12);
- u32Reg |= ((sPt->u32Month % 10) << 8);
- u32Reg |= ((sPt->u32Day / 10) << 4);
- u32Reg |= (sPt->u32Day % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->CALM = (uint32_t)g_u32Reg;
-
- u32Reg = ((sPt->u32Hour / 10) << 20);
- u32Reg |= ((sPt->u32Hour % 10) << 16);
- u32Reg |= ((sPt->u32Minute / 10) << 12);
- u32Reg |= ((sPt->u32Minute % 10) << 8);
- u32Reg |= ((sPt->u32Second / 10) << 4);
- u32Reg |= (sPt->u32Second % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->TALM = (uint32_t)g_u32Reg;
-
-}
-
-
-/**
- * @brief This function is used to update date to RTC
- *
- * @param[in] u32Year The Year Calendar Digit of Alarm Setting
- * @param[in] u32Month The Month Calendar Digit of Alarm Setting
- * @param[in] u32Day The Day Calendar Digit of Alarm Setting
- * @param[in] u32DayOfWeek The Day of Week. [ \ref RTC_SUNDAY / \ref RTC_MONDAY / \ref RTC_TUESDAY /
- * \ref RTC_WEDNESDAY / \ref RTC_THURSDAY / \ref RTC_FRIDAY /
- * \ref RTC_SATURDAY]
- *
- * @return None
- *
- */
-void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
-{
- __IO uint32_t u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
-
- u32Reg = ((u32Year - RTC_YEAR2000) / 10) << 20;
- u32Reg |= (((u32Year - RTC_YEAR2000) % 10) << 16);
- u32Reg |= ((u32Month / 10) << 12);
- u32Reg |= ((u32Month % 10) << 8);
- u32Reg |= ((u32Day / 10) << 4);
- u32Reg |= (u32Day % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->CAL = (uint32_t)g_u32Reg;
-
-}
-
-/**
- * @brief This function is used to update time to RTC.
- *
- * @param[in] u32Hour The Hour Time Digit of Alarm Setting.
- * @param[in] u32Minute The Month Calendar Digit of Alarm Setting
- * @param[in] u32Second The Day Calendar Digit of Alarm Setting
- * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24]
- * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [ \ref RTC_AM / \ref RTC_PM]
- *
- * @return None
- *
- */
-void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
-{
- __IO uint32_t u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if (u32TimeMode == RTC_CLOCK_12) {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
-
- if (u32AmPm == RTC_PM) /* important, range of 12-hour PM mode is 21 up to 32 */
- u32Hour += 20;
- } else if(u32TimeMode == RTC_CLOCK_24) {
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- u32Reg = ((u32Hour / 10) << 20);
- u32Reg |= ((u32Hour % 10) << 16);
- u32Reg |= ((u32Minute / 10) << 12);
- u32Reg |= ((u32Minute % 10) << 8);
- u32Reg |= ((u32Second / 10) << 4);
- u32Reg |= (u32Second % 10);
-
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->TIME = (uint32_t)g_u32Reg;
-
-}
-
-/**
- * @brief This function is used to set alarm date to RTC
- *
- * @param[in] u32Year The Year Calendar Digit of Alarm Setting
- * @param[in] u32Month The Month Calendar Digit of Alarm Setting
- * @param[in] u32Day The Day Calendar Digit of Alarm Setting
- *
- * @return None
- *
- */
-void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
-{
- __IO uint32_t u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- u32Reg = ((u32Year - RTC_YEAR2000) / 10) << 20;
- u32Reg |= (((u32Year - RTC_YEAR2000) % 10) << 16);
- u32Reg |= ((u32Month / 10) << 12);
- u32Reg |= ((u32Month % 10) << 8);
- u32Reg |= ((u32Day / 10) << 4);
- u32Reg |= (u32Day % 10);
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->CALM = (uint32_t)g_u32Reg;
-
-}
-
-/**
- * @brief This function is used to set alarm date to RTC
- *
- * @param[in] u32Hour The Hour Time Digit of Alarm Setting.
- * @param[in] u32Minute The Minute Time Digit of Alarm Setting
- * @param[in] u32Second The Second Time Digit of Alarm Setting
- * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [ \ref RTC_CLOCK_12 / \ref RTC_CLOCK_24]
- * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [ \ref RTC_AM / \ref RTC_PM]
- *
- * @return None
- *
- */
-void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
-{
- __IO uint32_t u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if (u32TimeMode == RTC_CLOCK_12) {
- RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
-
- if (u32AmPm == RTC_PM) /* important, range of 12-hour PM mode is 21 up to 32 */
- u32Hour += 20;
- } else if(u32TimeMode == RTC_CLOCK_24) {
- RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
- }
-
- u32Reg = ((u32Hour / 10) << 20);
- u32Reg |= ((u32Hour % 10) << 16);
- u32Reg |= ((u32Minute / 10) << 12);
- u32Reg |= ((u32Minute % 10) << 8);
- u32Reg |= ((u32Second / 10) << 4);
- u32Reg |= (u32Second % 10);
-
- g_u32Reg = u32Reg;
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->TALM = (uint32_t)g_u32Reg;
-
-}
-
-
-/**
- * @brief The spare registers access enable
- *
- * @return None
- *
- */
-void RTC_EnableSpareAccess(void)
-{
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
-
- while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
-}
-
-
-/**
- * @brief This function is used to:
- * 1. Enable tamper detection function. \n
- * 2. Set tamper detect pin number. \n
- * 3. Set tamper control register, interrupt. \n
- * 4. Clear tamper status. \n
- * 5. Destroy Spare Register when tamper detected \n
- *
- * @param[in] u32PinNumber tamper detect pin number. [ \ref RTC_TAMPER_0 / \ref RTC_TAMPER_1]
- * @param[in] u32PinCondition set tamper detection condition: 1=High level detect, 0=Low level detect
- * @param[in] u32IntFlag Enable/Disable tamper interrupt: 1=Enable, 0=Disable
- * @param[in] u32ClearFlag Clear tamper status
- * @param[in] u32DestroyEn Enable/Disable Destroy Spare Register when tamper detected: 1=Enable, 0=Disable
- *
- * @return None
- *
- */
-void RTC_EnableTamperDetection(uint32_t u32PinNumber, uint32_t u32PinCondition, uint32_t u32IntFlag, uint32_t u32ClearFlag, uint32_t u32DestroyEn)
-{
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if(u32PinNumber == RTC_TAMPER_0) {
- if(u32ClearFlag)
- RTC->TAMPSTS |= RTC_TAMPSTS_TAMPSTS0_Msk;
-
- if(u32PinCondition)
- RTC->TAMPCTL |= RTC_TAMPCTL_TAMPLV0_Msk;
- else
- RTC->TAMPCTL &= ~RTC_TAMPCTL_TAMPLV0_Msk;
-
- RTC->TAMPCTL |= RTC_TAMPCTL_TAMPDBEN0_Msk;
- RTC->TAMPCTL |= RTC_TAMPCTL_TAMPEN0_Msk;
- } else if(u32PinNumber == RTC_TAMPER_1) {
- if(u32ClearFlag)
- RTC->TAMPSTS |= RTC_TAMPSTS_TAMPSTS1_Msk;
-
- if(u32PinCondition)
- RTC->TAMPCTL |= RTC_TAMPCTL_TAMPLV1_Msk;
- else
- RTC->TAMPCTL &= ~RTC_TAMPCTL_TAMPLV1_Msk;
-
- RTC->TAMPCTL |= RTC_TAMPCTL_TAMPDBEN1_Msk;
- RTC->TAMPCTL |= RTC_TAMPCTL_TAMPEN1_Msk;
- }
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if(u32IntFlag)
- RTC->TAMPCTL |= RTC_TAMPCTL_TIEN_Msk;
- else
- RTC->TAMPCTL &= ~RTC_TAMPCTL_TIEN_Msk;
-
- if(u32DestroyEn)
- RTC->TAMPCTL |= RTC_TAMPCTL_DESTROYEN_Msk;
- else
- RTC->TAMPCTL &= ~RTC_TAMPCTL_DESTROYEN_Msk;
-
-}
-
-/**
- * @brief This function is used to disable tamper detection function.
- *
- * @param[in] u32PinNumber tamper detect pin number: \ref RTC_TAMPER_0, \ref RTC_TAMPER_1
- *
- * @return None
- *
- */
-void RTC_DisableTamperDetection(uint32_t u32PinNumber)
-{
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if(u32PinNumber == RTC_TAMPER_0) {
- RTC->TAMPCTL &= ~RTC_TAMPCTL_TAMPEN0_Msk;
- } else if(u32PinNumber == RTC_TAMPER_1) {
- RTC->TAMPCTL &= ~RTC_TAMPCTL_TAMPEN1_Msk;
- }
-
-}
-
-/**
- * @brief This function is used to get day of week.
- *
- * @param None
- *
- * @return Day of week
- *
- */
-uint32_t RTC_GetDayOfWeek(void)
-{
- return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
-}
-
-/**
- * @brief The function is used to set time tick period for periodic time tick Interrupt.
- *
- * @param[in] u32TickSelection
- * It is used to set the RTC time tick period for Periodic Time Tick Interrupt request.
- * It consists of: \n
- * - \ref RTC_TICK_1_SEC : Time tick is 1 second \n
- * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second \n
- * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second \n
- * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second \n
- * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second \n
- * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second \n
- * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second \n
- * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
- *
- * @return None
- *
- */
-void RTC_SetTickPeriod(uint32_t u32TickSelection)
-{
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->TICK = RTC->TICK & ~RTC_TICK_TICKSEL_Msk | u32TickSelection;
-}
-
-/**
- * @brief The function is used to enable specified interrupt.
- *
- * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n
- * \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt \n
- * \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt \n
- *
- * @return None
- *
- */
-void RTC_EnableInt(uint32_t u32IntFlagMask)
-{
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->INTEN |= u32IntFlagMask;
-}
-
-/**
- * @brief The function is used to disable specified interrupt.
- *
- * @param[in] u32IntFlagMask The structure of interrupt source. It consists of: \n
- * \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt \n
- * \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt \n
- *
- * @return None
- *
- */
-void RTC_DisableInt(uint32_t u32IntFlagMask)
-{
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- if(u32IntFlagMask & RTC_INTEN_TICKIEN_Msk) {
- RTC->INTEN &= ~RTC_INTEN_TICKIEN_Msk;
- RTC->INTSTS |= RTC_INTSTS_TICKIF_Msk;
- }
-
- if(u32IntFlagMask & RTC_INTEN_ALMIEN_Msk) {
- RTC->INTEN &= ~RTC_INTEN_ALMIEN_Msk;
- RTC->INTSTS |= RTC_INTSTS_ALMIF_Msk;
- }
-
-}
-
-/**
- * @brief Disable RTC clock.
- *
- * @return None
- *
- */
-void RTC_Close (void)
-{
- CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
-}
-
-
-/*@}*/ /* end of group NUC472_442_RTC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_RTC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,235 +0,0 @@
-/**************************************************************************//**
- * @file rtc.h
- * @version V1.00
- * $Revision: 18 $
- * $Date: 14/10/01 2:43p $
- * @brief NUC472/NUC442 RTC driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#ifndef __RTC_H
-#define __RTC_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_RTC_Driver RTC Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_RTC_EXPORTED_CONSTANTS RTC Exported Constants
- @{
-*/
-
-
-#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Access Key \hideinitializer */
-#define RTC_WRITE_KEY 0xA965 /*!< RTC Access Key \hideinitializer */
-
-#define RTC_WAIT_COUNT 0xFFFFFFFF /*!< Initial Time Out Value \hideinitializer */
-
-#define RTC_YEAR2000 2000 /*!< RTC Reference \hideinitializer */
-#define RTC_FCR_REFERENCE 32761 /*!< RTC Reference \hideinitializer */
-
-#define RTC_CLOCK_12 0 /*!< RTC 12 Hour \hideinitializer */
-#define RTC_CLOCK_24 1 /*!< RTC 24 Hour \hideinitializer */
-
-#define RTC_AM 1 /*!< RTC AM \hideinitializer */
-#define RTC_PM 2 /*!< RTC PM \hideinitializer */
-
-#define RTC_TICK_1_SEC ((uint32_t) 0x00000000) /*!< Time tick is 1 second \hideinitializer */
-#define RTC_TICK_1_2_SEC ((uint32_t) 0x00000001) /*!< Time tick is 1/2 second \hideinitializer */
-#define RTC_TICK_1_4_SEC ((uint32_t) 0x00000002) /*!< Time tick is 1/4 second \hideinitializer */
-#define RTC_TICK_1_8_SEC ((uint32_t) 0x00000003) /*!< Time tick is 1/8 second \hideinitializer */
-#define RTC_TICK_1_16_SEC ((uint32_t) 0x00000004) /*!< Time tick is 1/16 second \hideinitializer */
-#define RTC_TICK_1_32_SEC ((uint32_t) 0x00000005) /*!< Time tick is 1/32 second \hideinitializer */
-#define RTC_TICK_1_64_SEC ((uint32_t) 0x00000006) /*!< Time tick is 1/64 second \hideinitializer */
-#define RTC_TICK_1_128_SEC ((uint32_t) 0x00000007) /*!< Time tick is 1/128 second \hideinitializer */
-
-#define RTC_SUNDAY ((uint32_t) 0x00000000) /*!< Day of week is sunday \hideinitializer */
-#define RTC_MONDAY ((uint32_t) 0x00000001) /*!< Day of week is monday \hideinitializer */
-#define RTC_TUESDAY ((uint32_t) 0x00000002) /*!< Day of week is tuesday \hideinitializer */
-#define RTC_WEDNESDAY ((uint32_t) 0x00000003) /*!< Day of week is wednesday \hideinitializer */
-#define RTC_THURSDAY ((uint32_t) 0x00000004) /*!< Day of week is thuesday \hideinitializer */
-#define RTC_FRIDAY ((uint32_t) 0x00000005) /*!< Day of week is friday \hideinitializer */
-#define RTC_SATURDAY ((uint32_t) 0x00000006) /*!< Day of week is saturday \hideinitializer */
-
-#define RTC_TAMPER_0 0 /*!< Select Tamper 0 pin \hideinitializer */
-#define RTC_TAMPER_1 1 /*!< Select Tamper 0 pin \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_RTC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_RTC_EXPORTED_STRUCTS RTC Exported Structs
- @{
-*/
-
-/**
- * @brief RTC define Time Data Struct
- */
-typedef struct {
- uint32_t u32Year; /*!< Year value */
- uint32_t u32Month; /*!< Month value */
- uint32_t u32Day; /*!< Day value */
- uint32_t u32DayOfWeek; /*!< Day of week value */
- uint32_t u32Hour; /*!< Hour value */
- uint32_t u32Minute; /*!< Minute value */
- uint32_t u32Second; /*!< Second value */
- uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
- uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
-} S_RTC_TIME_DATA_T;
-
-/*@}*/ /* end of group NUC472_442_RTC_EXPORTED_STRUCTS */
-
-
-
-
-
-/** @addtogroup NUC472_442_RTC_EXPORTED_FUNCTIONS RTC Exported Functions
- @{
-*/
-
-
-/**
- * @brief Read spare register
- *
- * @param[in] u32RegNum The spare register number(0~23)
- *
- * @return Spare register content.
- * \hideinitializer
- */
-#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[u32RegNum])
-
-/**
- * @brief Write spare register
- *
- * @param[in] u32RegNum The spare register number(0~23)
- * @param[in] u32RegValue The spare register value
- *
- * @return None
- * \hideinitializer
- */
-#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[u32RegNum] = u32RegValue)
-
-/**
- * @brief According to current time, return this year is leap year or not
- *
- * @param None
- *
- * @return 0 = This year is not a leap year. \n
- * 1 = This year is a leap year.
- * \hideinitializer
- */
-#define RTC_IS_LEAP_YEAR ((RTC->LEAPYEAR & (RTC_LEAPYEAR_LEAPYEAR_Msk))?1:0)
-
-/**
- * @brief Clear alarm interrupt status.
- *
- * @param None
- *
- * @return None
- * \hideinitializer
- */
-#define RTC_CLEAR_ALARM_INT_FLAG (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
-
-/**
- * @brief Clear tick interrupt status.
- *
- * @param None
- *
- * @return None
- * \hideinitializer
- */
-#define RTC_CLEAR_TICK_INT_FLAG (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
-
-/**
- * @brief Clear tamper detect pin status.
- *
- * @param[in] u32PinNum tamper detect pin number. [ \ref RTC_TAMPER_0 / \ref RTC_TAMPER_1]
- *
- * @return None
- * \hideinitializer
- */
-#define RTC_CLEAR_TAMPER_FLAG(u32PinNum) (RTC->TAMPSTS = (1 << u32PinNum))
-
-/**
- * @brief Get alarm interrupt status.
- *
- * @param None
- *
- * @return Alarm interrupt status
- * \hideinitializer
- */
-#define RTC_GET_ALARM_INT_FLAG ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk) >> RTC_INTSTS_ALMIF_Pos)
-
-/**
- * @brief Get alarm interrupt status.
- *
- * @param None
- *
- * @return Alarm interrupt status
- * \hideinitializer
- */
-#define RTC_GET_TICK_INT_FLAG ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk) >> RTC_INTSTS_TICKIF_Pos)
-
-/**
- * @brief Get tamper detect pin status.
- *
- * @param[in] u32PinNum tamper detect pin number. [ \ref RTC_TAMPER_0 / \ref RTC_TAMPER_1]
- *
- * @return Tamper detect pin status
- * \hideinitializer
- */
-#define RTC_GET_TAMPER_FLAG(u32PinNum) ( (RTC->TAMPSTS & (1 << u32PinNum)) >> u32PinNum)
-
-
-
-void RTC_Open(S_RTC_TIME_DATA_T *sPt);
-void RTC_Close(void);
-void RTC_32KCalibration(int32_t i32FrequencyX100);
-void RTC_SetTickPeriod(uint32_t u32TickSelection);
-void RTC_EnableInt(uint32_t u32IntFlagMask);
-void RTC_DisableInt(uint32_t u32IntFlagMask);
-uint32_t RTC_GetDayOfWeek(void);
-void RTC_DisableTamperDetection(uint32_t u32PinNumber);
-void RTC_EnableTamperDetection(uint32_t u32PinNumber, uint32_t u32PinCondition, uint32_t u32IntFlag, uint32_t u32ClearFlag, uint32_t u32DestroyEn);
-void RTC_EnableSpareAccess(void);
-void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
-void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
-void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
-void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
-void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
-void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
-void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
-void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
-
-
-
-/*@}*/ /* end of group NUC472_442_RTC_EXPORTED_FUNCTIONS */
-
-
-/*@}*/ /* end of group NUC472_442_RTC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __RTC_H */
-
-
-/*** (C) COPYRIGHT 2012 Nuvoton Technology Corp. ***/
-
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sc.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,281 +0,0 @@
-/**************************************************************************//**
- * @file sc.c
- * @version V1.00
- * $Revision: 6 $
- * $Date: 14/08/12 7:25p $
- * @brief NUC472/NUC442 Smartcard(SC) driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-// Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined
-/// @cond HIDDEN_SYMBOLS
-static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0, 0, 0, 0, 0, 0};
-
-/// @endcond HIDDEN_SYMBOLS
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SC_Driver SC Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_SC_EXPORTED_FUNCTIONS SC Exported Functions
- @{
-*/
-
-/**
- * @brief This function indicates specified smartcard slot status
- * @param[in] sc Base address of smartcard module
- * @return Card insert status
- * @retval TRUE Card insert
- * @retval FALSE Card remove
- */
-uint32_t SC_IsCardInserted(SC_T *sc)
-{
- // put conditions into two variable to remove IAR compilation warning
- uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
- uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
-
- if(sc == SC0 && u32CardStateIgnore[0] == 1)
- return TRUE;
- else if(sc == SC1 && u32CardStateIgnore[1] == 1)
- return TRUE;
- else if(sc == SC2 && u32CardStateIgnore[2] == 1)
- return TRUE;
- else if(sc == SC3 && u32CardStateIgnore[3] == 1)
- return TRUE;
- else if(sc == SC4 && u32CardStateIgnore[4] == 1)
- return TRUE;
- else if(sc == SC5 && u32CardStateIgnore[5] == 1)
- return TRUE;
- else if(cond1 != cond2)
- return FALSE;
- else
- return TRUE;
-}
-
-/**
- * @brief This function reset both transmit and receive FIFO of specified smartcard module
- * @param[in] sc Base address of smartcard module
- * @return None
- */
-void SC_ClearFIFO(SC_T *sc)
-{
- sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
-}
-
-/**
- * @brief This function disable specified smartcard module
- * @param[in] sc Base address of smartcard module
- * @return None
- */
-void SC_Close(SC_T *sc)
-{
- sc->INTEN = 0;
- while(sc->PINCTL & SC_PINCTL_SYNC_Msk);
- sc->PINCTL = 0;
- sc->ALTCTL = 0;
- while(sc->CTL & SC_CTL_SYNC_Msk);
- sc->CTL = 0;
-}
-
-/**
- * @brief This function initialized smartcard module
- * @param[in] sc Base address of smartcard module
- * @param[in] u32CD Card detect polarity, select the CD pin state which indicates card insert. Could be
- * -\ref SC_PIN_STATE_HIGH
- * -\ref SC_PIN_STATE_LOW
- * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present
- * @param[in] u32PWR Power on polarity, select the PWR pin state which could set smartcard VCC to high level. Could be
- * -\ref SC_PIN_STATE_HIGH
- * -\ref SC_PIN_STATE_LOW
- * @return None
- */
-void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR)
-{
- uint32_t u32Reg = 0, u32Intf;
-
- if(sc == SC0)
- u32Intf = 0;
- else if(sc == SC1)
- u32Intf = 1;
- else if(sc == SC2)
- u32Intf = 2;
- else if(sc == SC3)
- u32Intf = 3;
- else if(sc == SC4)
- u32Intf = 4;
- else
- u32Intf = 5;
-
- if(u32CD != SC_PIN_STATE_IGNORE) {
- u32Reg = u32CD ? 0: SC_CTL_CDLV_Msk;
- u32CardStateIgnore[u32Intf] = 0;
- } else {
- u32CardStateIgnore[u32Intf] = 1;
- }
- sc->PINCTL = u32PWR ? 0 : SC_PINCTL_PWRINV_Msk;
- while(sc->CTL & SC_CTL_SYNC_Msk);
- sc->CTL = SC_CTL_SCEN_Msk | u32Reg;
-}
-
-/**
- * @brief This function reset specified smartcard module to its default state for activate smartcard
- * @param[in] sc Base address of smartcard module
- * @return None
- */
-void SC_ResetReader(SC_T *sc)
-{
- uint32_t u32Intf;
-
- if(sc == SC0)
- u32Intf = 0;
- else if(sc == SC1)
- u32Intf = 1;
- else if(sc == SC2)
- u32Intf = 2;
- else if(sc == SC3)
- u32Intf = 3;
- else if(sc == SC4)
- u32Intf = 4;
- else
- u32Intf = 5;
-
- // Reset FIFO, enable auto de-activation while card removal
- sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
- // Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry)
- while(sc->CTL & SC_CTL_SYNC_Msk);
- sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | SC_CTL_CDDBSEL_Msk | SC_CTL_TXRTY_Msk | SC_CTL_RXRTY_Msk);
- // Enable auto convention, and all three smartcard internal timers
- sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
- // Disable Rx timeout
- sc->RXTOUT = 0;
- // 372 clocks per ETU by default
- sc->ETUCTL= 371;
-
-
- /* Enable necessary interrupt for smartcard operation */
- if(u32CardStateIgnore[u32Intf]) // Do not enable card detect interrupt if card present state ignore
- sc->INTEN = (SC_INTEN_RDAIEN_Msk |
- SC_INTEN_TERRIEN_Msk |
- SC_INTEN_TMR0IEN_Msk |
- SC_INTEN_TMR1IEN_Msk |
- SC_INTEN_TMR2IEN_Msk |
- SC_INTEN_BGTIEN_Msk |
- SC_INTEN_ACERRIEN_Msk);
- else
- sc->INTEN = (SC_INTEN_RDAIEN_Msk |
- SC_INTEN_TERRIEN_Msk |
- SC_INTEN_TMR0IEN_Msk |
- SC_INTEN_TMR1IEN_Msk |
- SC_INTEN_TMR2IEN_Msk |
- SC_INTEN_BGTIEN_Msk |
- SC_INTEN_CDIEN_Msk |
- SC_INTEN_ACERRIEN_Msk);
-
- return;
-}
-
-/**
- * @brief This function block guard time (BGT) of specified smartcard module
- * @param[in] sc Base address of smartcard module
- * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32
- * @return None
- */
-void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
-{
- sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1) << SC_CTL_BGT_Pos);
-}
-
-/**
- * @brief This function character guard time (CGT) of specified smartcard module
- * @param[in] sc Base address of smartcard module
- * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267
- * @return None
- */
-void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
-{
- u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11: 12;
- sc->EGT = u32CGT;
-}
-
-/**
- * @brief This function stop all smartcard timer of specified smartcard module
- * @param[in] sc Base address of smartcard module
- * @return None
- * @note This function stop the timers within smartcard module, \b not timer module
- */
-void SC_StopAllTimer(SC_T *sc)
-{
- sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
-}
-
-/**
- * @brief This function configure and start a smartcard timer of specified smartcard module
- * @param[in] sc Base address of smartcard module
- * @param[in] u32TimerNum Timer(s) to start. Valid values are 0, 1, 2.
- * @param[in] u32Mode Timer operating mode, valid values are:
- * - \ref SC_TMR_MODE_0
- * - \ref SC_TMR_MODE_1
- * - \ref SC_TMR_MODE_2
- * - \ref SC_TMR_MODE_3
- * - \ref SC_TMR_MODE_4
- * - \ref SC_TMR_MODE_5
- * - \ref SC_TMR_MODE_6
- * - \ref SC_TMR_MODE_7
- * - \ref SC_TMR_MODE_8
- * - \ref SC_TMR_MODE_F
- * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1~0x1000000ETUs.
- * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs
- * @return None
- * @note This function start the timer within smartcard module, \b not timer module
- * @note Depend on the timer operating mode, timer may not start counting immediately
- */
-void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
-{
- uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1));
-
- if(u32TimerNum == 0) {
- sc->TMRCTL0 = reg;
- sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
- } else if(u32TimerNum == 1) {
- sc->TMRCTL1 = reg;
- sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
- } else { // timer 2
- sc->TMRCTL2 = reg;
- sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
- }
-}
-
-/**
- * @brief This function stop a smartcard timer of specified smartcard module
- * @param[in] sc Base address of smartcard module
- * @param[in] u32TimerNum Timer(s) to stop. Valid values are 0, 1, 2.
- * @return None
- * @note This function stop the timer within smartcard module, \b not timer module
- */
-void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
-{
- if(u32TimerNum == 0)
- sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
- else if(u32TimerNum == 1)
- sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
- else // timer 2
- sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
-}
-
-
-
-/*@}*/ /* end of group NUC472_442_SC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sc.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,246 +0,0 @@
-/**************************************************************************//**
- * @file sc.h
- * @version V1.00
- * $Revision: 10 $
- * $Date: 14/09/29 2:01p $
- * @brief NUC472/NUC442 Smartcard (SC) driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __SC_H__
-#define __SC_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SC_Driver SC Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SC_EXPORTED_CONSTANTS SC Exported Constants
- @{
-*/
-#define SC_INTERFACE_NUM 6 /*!< Smartcard interface numbers \hideinitializer */
-#define SC_PIN_STATE_HIGH 1 /*!< Smartcard pin status high \hideinitializer */
-#define SC_PIN_STATE_LOW 0 /*!< Smartcard pin status low \hideinitializer */
-#define SC_PIN_STATE_IGNORE 0xFFFFFFFF /*!< Ignore pin status \hideinitializer */
-#define SC_CLK_ON 1 /*!< Smartcard clock on \hideinitializer */
-#define SC_CLK_OFF 0 /*!< Smartcard clock off \hideinitializer */
-
-#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 0, down count \hideinitializer */
-#define SC_TMR_MODE_1 (1ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit \hideinitializer */
-#define SC_TMR_MODE_2 (2ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit \hideinitializer */
-#define SC_TMR_MODE_3 (3ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode \hideinitializer */
-#define SC_TMR_MODE_4 (4ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout \hideinitializer */
-#define SC_TMR_MODE_5 (5ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout \hideinitializer */
-#define SC_TMR_MODE_6 (6ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout \hideinitializer */
-#define SC_TMR_MODE_7 (7ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit \hideinitializer */
-#define SC_TMR_MODE_8 (8ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 8, up count \hideinitializer */
-#define SC_TMR_MODE_F (0xF << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit \hideinitializer */
-
-
-/*@}*/ /* end of group NUC472_442_SC_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_SC_EXPORTED_FUNCTIONS SC Exported Functions
- @{
-*/
-
-/**
- * @brief This macro enable smartcard interrupt
- * @param[in] sc Base address of smartcard module
- * @param[in] u32Mask Interrupt mask to be enabled. A combination of
- * - \ref SC_INTEN_ACERRIEN_Msk
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_INITIEN_Msk
- * - \ref SC_INTEN_CDIEN_Msk
- * - \ref SC_INTEN_BGTIEN_Msk
- * - \ref SC_INTEN_TMR2IEN_Msk
- * - \ref SC_INTEN_TMR1IEN_Msk
- * - \ref SC_INTEN_TMR0IEN_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * \hideinitializer
- */
-#define SC_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
-
-/**
- * @brief This macro disable smartcard interrupt
- * @param[in] sc Base address of smartcard module
- * @param[in] u32Mask Interrupt mask to be disabled. A combination of
- * - \ref SC_INTEN_ACERRIEN_Msk
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_INITIEN_Msk
- * - \ref SC_INTEN_CDIEN_Msk
- * - \ref SC_INTEN_BGTIEN_Msk
- * - \ref SC_INTEN_TMR2IEN_Msk
- * - \ref SC_INTEN_TMR1IEN_Msk
- * - \ref SC_INTEN_TMR0IEN_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * \hideinitializer
- */
-#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
-
-/**
- * @brief This macro set VCC pin state of smartcard interface
- * @param[in] sc Base address of smartcard module
- * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
- * @return None
- * \hideinitializer
- */
-#define SC_SET_VCC_PIN(sc, u32State) \
- do {\
- while(sc->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32State)\
- (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
- else\
- (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
- }while(0)
-
-
-/**
- * @brief This macro turns CLK output on or off
- * @param[in] sc Base address of smartcard module
- * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF
- * @return None
- * \hideinitializer
- */
-#define SC_SET_CLK_PIN(sc, u32OnOff)\
- do {\
- while(sc->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32OnOff)\
- (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
- else\
- (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
- }while(0)
-
-/**
- * @brief This macro set I/O pin state of smartcard interface
- * @param[in] sc Base address of smartcard module
- * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
- * @return None
- * \hideinitializer
- */
-#define SC_SET_IO_PIN(sc, u32State)\
- do {\
- while(sc->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32State)\
- (sc)->PINCTL |= SC_PINCTL_SCDOUT_Msk;\
- else\
- (sc)->PINCTL &= ~SC_PINCTL_SCDOUT_Msk;\
- }while(0)
-
-/**
- * @brief This macro set RST pin state of smartcard interface
- * @param[in] sc Base address of smartcard module
- * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW
- * @return None
- * \hideinitializer
- */
-#define SC_SET_RST_PIN(sc, u32State)\
- do {\
- while(sc->PINCTL & SC_PINCTL_SYNC_Msk);\
- if(u32State)\
- (sc)->PINCTL |= SC_PINCTL_SCRST_Msk;\
- else\
- (sc)->PINCTL &= ~SC_PINCTL_SCRST_Msk;\
- }while(0)
-
-/**
- * @brief This macro read one byte from smartcard module receive FIFO
- * @param[in] sc Base address of smartcard module
- * @return One byte read from receive FIFO
- * \hideinitializer
- */
-#define SC_READ(sc) ((char)((sc)->DAT))
-
-/**
- * @brief This macro write one byte to smartcard module transmit FIFO
- * @param[in] sc Base address of smartcard module
- * @param[in] u8Data Data to write to transmit FIFO
- * @return None
- * \hideinitializer
- */
-#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
-
-/**
- * @brief This macro set smartcard stop bit length
- * @param[in] sc Base address of smartcard module
- * @param[in] u32Len Stop bit length, ether 1 or 2.
- * @return None
- * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
- * \hideinitializer
- */
-#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (u32Len == 1 ? 1 : 0))
-
-/**
- * @brief Enable/Disable Tx error retry, and set Tx error retry count
- * @param[in] sc Base address of smartcard module
- * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry
- * @return None
- */
-__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
-{
- while(sc->CTL & SC_CTL_SYNC_Msk);
- if(u32Count == 0) { // disable Tx error retry
- sc->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
- } else {
- sc->CTL = (sc->CTL & ~SC_CTL_TXRTY_Msk) | ((u32Count - 1) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
- }
-}
-
-/**
- * @brief Enable/Disable Rx error retry, and set Rx error retry count
- * @param[in] sc Base address of smartcard module
- * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry
- * @return None
- */
-__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
-{
- while(sc->CTL & SC_CTL_SYNC_Msk);
- if(u32Count == 0) { // disable Rx error retry
- sc->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
- } else {
- sc->CTL = (sc->CTL & ~SC_CTL_RXRTY_Msk) | ((u32Count - 1) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
- }
-}
-
-
-uint32_t SC_IsCardInserted(SC_T *sc);
-void SC_ClearFIFO(SC_T *sc);
-void SC_Close(SC_T *sc);
-void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
-void SC_ResetReader(SC_T *sc);
-void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
-void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
-void SC_StopAllTimer(SC_T *sc);
-void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
-void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
-
-
-/*@}*/ /* end of group NUC472_442_SC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SC_H__
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_scuart.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,206 +0,0 @@
-/**************************************************************************//**
- * @file scuart.c
- * @version V1.00
- * $Revision: 6 $
- * $Date: 14/08/12 7:25p $
- * @brief NUC472/NUC442 Smartcard UART mode (SCUART) driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SCUART_Driver SCUART Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
- @{
-*/
-
-/**
- * @brief The function is used to disable smartcard interface UART mode.
- * @param sc The base address of smartcard module.
- * @return None
- */
-void SCUART_Close(SC_T* sc)
-{
- sc->INTEN = 0;
- sc->UARTCTL = 0;
- sc->CTL = 0;
-
-}
-/// @cond HIDDEN_SYMBOLS
-/**
- * @brief This function returns module clock of specified SC interface
- * @param[in] sc The base address of smartcard module.
- * @return Module clock of specified SC interface
- */
-static uint32_t SCUART_GetClock(SC_T *sc)
-{
- uint32_t u32ClkSrc, u32Num, u32Clk;
-
- if(sc == SC0)
- u32Num = 0;
- else if(sc == SC1)
- u32Num = 1;
- else if(sc == SC2)
- u32Num = 2;
- else if(sc == SC3)
- u32Num = 3;
- else if(sc == SC4)
- u32Num = 4;
- else
- u32Num = 5;
-
- u32ClkSrc = (CLK->CLKSEL3 >> (2 * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk;
-
- // Get smartcard module clock
- if(u32ClkSrc == 0)
- u32Clk = __HXT;
- else if(u32ClkSrc == 1)
- u32Clk = CLK_GetPLLClockFreq();
- else if(u32ClkSrc == 2)
- u32Clk = CLK_GetPCLKFreq();
- else
- u32Clk = __HIRC;
-
- if(u32Num < 4) {
- u32Clk /= (((CLK->CLKDIV1 >> (8 * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1);
- } else {
- u32Clk /= (((CLK->CLKDIV2 >> (8 * (u32Num - 4))) & CLK_CLKDIV2_SC4DIV_Msk) + 1);
- }
-
- return u32Clk;
-}
-
-/// @endcond HIDDEN_SYMBOLS
-
-/**
- * @brief This function use to enable smartcard module UART mode and set baudrate.
- * @param[in] sc The base address of smartcard module.
- * @param[in] u32baudrate Target baudrate of smartcard module.
- * @return Actual baudrate of smartcard mode
- * @note This function configures character width to 8 bits, 1 stop bit, and no parity.
- * And can use \ref SCUART_SetLineConfig function to update these settings
- */
-uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate)
-{
- uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
-
- // Calculate divider for target baudrate
- u32Div = (u32Clk + (u32baudrate >> 1) - 1) / u32baudrate - 1;
-
- sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; // Enable smartcard interface and stop bit = 1
- sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; // Enable UART mode, disable parity and 8 bit per character
- sc->ETUCTL = u32Div;
-
- return(u32Clk / u32Div);
-}
-
-/**
- * @brief The function is used to read Rx data from RX FIFO.
- * @param[in] sc The base address of smartcard module.
- * @param[in] pu8RxBuf The buffer to store receive the data
- * @param[in] u32ReadBytes Target number of characters to receive
- * @return Actual character number reads to buffer
- * @note This function does not block and return immediately if there's no data available
- */
-uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
-{
- uint32_t u32Count;
-
- for(u32Count = 0; u32Count < u32ReadBytes; u32Count++) {
- if(SCUART_GET_RX_EMPTY(sc)) { // no data available
- break;
- }
- pu8RxBuf[u32Count] = SCUART_READ(sc); // get data from FIFO
- }
-
- return u32Count;
-}
-
-/**
- * @brief This function use to config smartcard UART mode line setting.
- * @param[in] sc The base address of smartcard module.
- * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change.
- * @param[in] u32DataWidth The data length, could be
- * - \ref SCUART_CHAR_LEN_5
- * - \ref SCUART_CHAR_LEN_6
- * - \ref SCUART_CHAR_LEN_7
- * - \ref SCUART_CHAR_LEN_8
- * @param[in] u32Parity The parity setting, could be
- * - \ref SCUART_PARITY_NONE
- * - \ref SCUART_PARITY_ODD
- * - \ref SCUART_PARITY_EVEN
- * @param[in] u32StopBits The stop bit length, could be
- * - \ref SCUART_STOP_BIT_1
- * - \ref SCUART_STOP_BIT_2
- * @return Actual baudrate of smartcard
- */
-uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
-{
-
- uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
-
- if(u32Baudrate == 0) { // keep original baudrate setting
- u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
- } else {
- // Calculate divider for target baudrate
- u32Div = (u32Clk + (u32Baudrate >> 1) - 1)/ u32Baudrate - 1;
- sc->ETUCTL = u32Div;
- }
-
- sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; // Set stop bit
- sc->UARTCTL = u32Parity | u32StopBits | SC_UARTCTL_UARTEN_Msk; // Set character width and parity
-
- return(u32Clk / u32Div);
-}
-
-/**
- * @brief This function use to set receive timeout count.
- * @param[in] sc The base address of smartcard module.
- * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF,
- * set this value to 0 will disable timeout counter
- * @return None
- * @details The time-out counter resets and starts counting whenever the RX buffer received a
- * new data word. Once the counter decrease to 1 and no new data is received or CPU
- * does not read any data from FIFO, a receiver time-out interrupt will be generated.
- */
-void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
-{
- sc->RXTOUT= u32TOC;
-}
-
-
-/**
- * @brief This function is to write data into transmit FIFO to send data out.
- * @param[in] sc The base address of smartcard module.
- * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
- * @param[in] u32WriteBytes Number of data to send.
- * @return None
- * @note This function blocks until all data write into FIFO
- */
-void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
-{
- uint32_t u32Count;
-
- for(u32Count = 0; u32Count != u32WriteBytes; u32Count++) {
- while(SCUART_GET_TX_FULL(sc)); // Wait 'til FIFO not full
- sc->DAT = pu8TxBuf[u32Count]; // Write 1 byte to FIFO
- }
-}
-
-
-/*@}*/ /* end of group NUC472_442_SCUART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SCUART_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_scuart.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,260 +0,0 @@
-/**************************************************************************//**
- * @file sc.h
- * @version V1.00
- * $Revision: 8 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 Smartcard UART mode (SCUART) driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __SCUART_H__
-#define __SCUART_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SCUART_Driver SCUART Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
- @{
-*/
-#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */
-#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */
-#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */
-#define SCUART_CHAR_LEN_8 (0) /*!< Set SCUART word length to 8 bits \hideinitializer */
-
-#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */
-#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */
-#define SCUART_PARITY_EVEN (0) /*!< Set SCUART transfer with even parity \hideinitializer */
-
-#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */
-#define SCUART_STOP_BIT_2 (0) /*!< Set SCUART transfer with two stop bits \hideinitializer */
-
-
-/*@}*/ /* end of group NUC472_442_SCUART_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
- @{
-*/
-
-/* TX Macros */
-/**
- * @brief Write Data to Tx data register
- * @param[in] sc The base address of smartcard module.
- * @param[in] u8Data Data byte to transmit
- * @return None
- * \hideinitializer
- */
-#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
-
-/**
- * @brief Get TX FIFO empty flag status from register
- * @param[in] sc The base address of smartcard module
- * @return Transmit FIFO empty status
- * @retval 0 Transmit FIFO is not empty
- * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
- * \hideinitializer
- */
-#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
-
-/**
- * @brief Get TX FIFO full flag status from register
- * @param[in] sc The base address of smartcard module
- * @return Transmit FIFO full status
- * @retval 0 Transmit FIFO is not full
- * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
- * \hideinitializer
- */
-#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
-
-/**
- * @brief Wait specified smartcard port transmission complete
- * @param[in] sc The base address of smartcard module
- * @return None
- * @note This Macro blocks until transmit complete.
- * \hideinitializer
- */
-#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
-
-/**
- * @brief Check specified smartcard port transmit FIFO is full or not
- * @param[in] sc The base address of smartcard module
- * @return Transmit FIFO full status
- * @retval 0 Transmit FIFO is not full
- * @retval 1 Transmit FIFO is full
- * \hideinitializer
- */
-#define SCUART_IS_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0)
-
-/**
- * @brief Check specified smartcard port transmission is over
- * @param[in] sc The base address of smartcard module
- * @return Transmit complete status
- * @retval 0 Transmit is not complete
- * @retval 1 Transmit complete
- * \hideinitializer
- */
-#define SCUART_IS_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1)
-
-
-/* RX Macros */
-
-/**
- * @brief Read Rx data register
- * @param[in] sc The base address of smartcard module
- * @return The oldest data byte in RX FIFO
- * \hideinitializer
- */
-#define SCUART_READ(sc) ((sc)->DAT)
-
-/**
- * @brief Get RX FIFO empty flag status from register
- * @param[in] sc The base address of smartcard module
- * @return Receive FIFO empty status
- * @retval 0 Receive FIFO is not empty
- * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
- * \hideinitializer
- */
-#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
-
-
-/**
- * @brief Get RX FIFO full flag status from register
- * @param[in] sc The base address of smartcard module
- * @return Receive FIFO full status
- * @retval 0 Receive FIFO is not full
- * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full
- * \hideinitializer
- */
-#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
-
-/**
- * @brief Check if receive data number in FIFO reach FIFO trigger level or not
- * @param[in] sc The base address of smartcard module
- * @return Receive FIFO data status
- * @retval 0 The number of bytes in receive FIFO is less than trigger level
- * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level
- * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO
- * \hideinitializer
- */
-#define SCUART_IS_RX_READY(sc) ((sc)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0)
-
-/**
- * @brief Check specified smartcard port receive FIFO is full or not
- * @param[in] sc The base address of smartcard module
- * @return Receive FIFO full status
- * @retval 0 Receive FIFO is not full
- * @retval 1 Receive FIFO is full
- * \hideinitializer
- */
-#define SCUART_IS_RX_FULL(sc) ((sc)->STATUS & SC_SR_RX_FULL_F_Msk ? 1 : 0)
-
-/* Interrupt Macros */
-
-/**
- * @brief Enable specified interrupts
- * @param[in] sc The base address of smartcard module
- * @param[in] u32Mask Interrupt masks to enable, a combination of following bits
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * \hideinitializer
- */
-#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
-
-/**
- * @brief Disable specified interrupts
- * @param[in] sc The base address of smartcard module
- * @param[in] u32Mask Interrupt masks to disable, a combination of following bits
- * - \ref SC_INTEN_RXTOIF_Msk
- * - \ref SC_INTEN_TERRIEN_Msk
- * - \ref SC_INTEN_TBEIEN_Msk
- * - \ref SC_INTEN_RDAIEN_Msk
- * @return None
- * \hideinitializer
- */
-#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
-
-/**
- * @brief Get specified interrupt flag/status
- * @param[in] sc The base address of smartcard module
- * @param[in] u32Type Interrupt flag/status to check, could be one of following value
- * - \ref SC_INTSTS_RBTOIF_Msk
- * - \ref SC_INTSTS_TERRIF_Msk
- * - \ref SC_INTSTS_TBEIF_Msk
- * - \ref SC_INTSTS_RDAIF_Msk
- * @return The status of specified interrupt
- * @retval 0 Specified interrupt does not happened
- * @retval 1 Specified interrupt happened
- * \hideinitializer
- */
-#define SCUART_GET_INT_FLAG(sc, u32Type) ((sc)->INTSTS & u32Type ? 1 : 0)
-
-/**
- * @brief Clear specified interrupt flag/status
- * @param[in] sc The base address of smartcard module
- * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values
- * - \ref SC_INTSTS_RBTOIF_Msk
- * - \ref SC_INTSTS_TERRIF_Msk
- * - \ref SC_INTSTS_TBEIF_Msk
- * @return None
- * \hideinitializer
- */
-#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = u32Type)
-
-/**
- * @brief Get receive error flag/status
- * @param[in] sc The base address of smartcard module
- * @return Current receive error status, could one of following errors:
- * @retval SC_STATUS_PEF_Msk Parity error
- * @retval SC_STATUS_FEF_Msk Frame error
- * @retval SC_STATUS_BEF_Msk Break error
- * \hideinitializer
- */
-#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
-
-/**
- * @brief Clear specified receive error flag/status
- * @param[in] sc The base address of smartcard module
- * @param[in] u32Mask Receive error flag/status to clear, combination following values
- * - \ref SC_STATUS_PEF_Msk
- * - \ref SC_STATUS_FEF_Msk
- * - \ref SC_STATUS_BEF_Msk
- * @return None
- * \hideinitializer
- */
-#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = u32Mask)
-
-void SCUART_Close(SC_T* sc);
-uint32_t SCUART_Open(SC_T* sc, uint32_t u32baudrate);
-uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
-uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
-void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
-void SCUART_Write(SC_T* sc,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
-
-/*@}*/ /* end of group NUC472_442_SCUART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SCUART_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SCUART_H__
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1043 +0,0 @@
-/**************************************************************************//**
- * @file SD.c
- * @version V1.00
- * $Revision: 16 $
- * $Date: 15/11/26 10:45a $
- * @brief NUC472/NUC442 SD driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SD_Driver SD Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_SD_EXPORTED_FUNCTIONS SD Exported Functions
- @{
-*/
-#define SD_BLOCK_SIZE 512
-
-/// @cond HIDDEN_SYMBOLS
-
-// global variables
-// For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still
-// calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag
-// _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error
-uint32_t _sd_uR3_CMD=0;
-uint32_t _sd_uR7_CMD=0;
-uint8_t volatile _sd_SDDataReady = FALSE;
-
-uint8_t *_sd_pSDHCBuffer;
-uint32_t _sd_ReferenceClock;
-
-#if defined (__CC_ARM)
-__align(4096) uint8_t _sd_ucSDHCBuffer[512];
-#elif defined ( __ICCARM__ ) /*!< IAR Compiler */
-#pragma data_alignment = 4096
-uint8_t _sd_ucSDHCBuffer[512];
-#elif defined ( __GNUC__ )
-uint8_t _sd_ucSDHCBuffer[512] __attribute__((aligned (4096)));
-#endif
-
-int sd0_ok = 0;
-int sd1_ok = 0;
-
-uint8_t pSD0_offset = 0;
-uint8_t pSD1_offset = 0;
-
-DISK_DATA_T SD_DiskInfo0;
-DISK_DATA_T SD_DiskInfo1;
-
-SD_INFO_T SD0;
-SD_INFO_T SD1;
-
-void SD_CheckRB()
-{
- while(1) {
- SD->CTL |= SDH_CTL_CLK8OEN_Msk;
- while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
- if (SD->INTSTS & SDH_INTSTS_DAT0STS_Msk)
- break;
- }
-}
-
-
-int SD_SDCommand(SD_INFO_T *pSD, uint8_t ucCmd, uint32_t uArg)
-{
- volatile int buf;
-
- SD->CMDARG = uArg;
- buf = (SD->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk);
- SD->CTL = buf;
-
- while(SD->CTL & SDH_CTL_COEN_Msk) {
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
- return Successful;
-}
-
-
-int SD_SDCmdAndRsp(SD_INFO_T *pSD, uint8_t ucCmd, uint32_t uArg, int ntickCount)
-{
- volatile int buf;
-
- SD->CMDARG = uArg;
- buf = (SD->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk);
- SD->CTL = buf;
-
- if (ntickCount > 0) {
- while(SD->CTL & SDH_CTL_RIEN_Msk) {
- if(ntickCount-- == 0) {
- SD->CTL |= SDH_CTL_CTLRST_Msk; // reset SD engine
- return 2;
- }
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
- } else {
- while(SD->CTL & SDH_CTL_RIEN_Msk) {
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
- }
-
- if (_sd_uR7_CMD) {
- if (((SD->RESP1 & 0xff) != 0x55) && ((SD->RESP0 & 0xf) != 0x01)) {
- _sd_uR7_CMD = 0;
- return SD_CMD8_ERROR;
- }
- }
-
- if (!_sd_uR3_CMD) {
- if (SD->INTSTS & SDH_INTSTS_CRC7_Msk) // check CRC7
- return Successful;
- else {
- return SD_CRC7_ERROR;
- }
- } else { // ignore CRC error for R3 case
- _sd_uR3_CMD = 0;
- SD->INTSTS = SDH_INTSTS_CRCIF_Msk;
- return Successful;
- }
-}
-
-
-int SD_Swap32(int val)
-{
-#if 1
- int buf;
-
- buf = val;
- val <<= 24;
- val |= (buf<<8)&0xff0000;
- val |= (buf>>8)&0xff00;
- val |= (buf>>24)&0xff;
- return val;
-
-#else
- return ((val<<24) | ((val<<8)&0xff0000) | ((val>>8)&0xff00) | (val>>24));
-#endif
-}
-
-// Get 16 bytes CID or CSD
-int SD_SDCmdAndRsp2(SD_INFO_T *pSD, uint8_t ucCmd, uint32_t uArg, uint32_t *puR2ptr)
-{
- unsigned int i, buf;
- unsigned int tmpBuf[5];
-
- SD->CMDARG = uArg;
- buf = (SD->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|(SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk);
- SD->CTL = buf;
-
- while(SD->CTL & SDH_CTL_R2EN_Msk) {
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- if (SD->INTSTS & SDH_INTSTS_CRC7_Msk) {
- for (i=0; i<5; i++) {
- tmpBuf[i] = SD_Swap32(*(int*)(SD_BASE+i*4));
- }
- for (i=0; i<4; i++)
- *puR2ptr++ = ((tmpBuf[i] & 0x00ffffff)<<8) | ((tmpBuf[i+1] & 0xff000000)>>24);
- return Successful;
- } else
- return SD_CRC7_ERROR;
-}
-
-
-int SD_SDCmdAndRspDataIn(SD_INFO_T *pSD, uint8_t ucCmd, uint32_t uArg)
-{
- volatile int buf;
-
- SD->CMDARG = uArg;
- buf = (SD->CTL&(~SDH_CTL_CMDCODE_Msk))|(ucCmd << 8)|
- (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
-
- SD->CTL = buf;
-
- while (SD->CTL & SDH_CTL_RIEN_Msk) {
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- while (SD->CTL & SDH_CTL_DIEN_Msk) {
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- if (!(SD->INTSTS & SDH_INTSTS_CRC7_Msk)) { // check CRC7
- return SD_CRC7_ERROR;
- }
-
- if (!(SD->INTSTS & SDH_INTSTS_CRC16_Msk)) { // check CRC16
- return SD_CRC16_ERROR;
- }
- return Successful;
-}
-
-// there are 8 bits for divider0, maximum is 256
-#define SD_CLK_DIV0_MAX 256
-
-void SD_Set_clock(uint32_t sd_clock_khz)
-{
- uint32_t rate, div1, i;
- uint32_t u32SD_ClkSrc;
-
- if(sd_clock_khz >= 24000) {
- sd_clock_khz = 24000;
- }
-
- u32SD_ClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDHSEL_Msk);
-
- if(u32SD_ClkSrc == CLK_CLKSEL0_SDHSEL_HXT)
- _sd_ReferenceClock = (CLK_GetHXTFreq() / 1000);
- else if(u32SD_ClkSrc == CLK_CLKSEL0_SDHSEL_HIRC)
- _sd_ReferenceClock = (__HIRC / 1000);
- else if(u32SD_ClkSrc == CLK_CLKSEL0_SDHSEL_PLL)
- _sd_ReferenceClock = (CLK_GetPLLClockFreq() / 1000);
- else if(u32SD_ClkSrc == CLK_CLKSEL0_SDHSEL_HCLK)
- _sd_ReferenceClock = (CLK_GetHCLKFreq() / 1000);
-
- rate = _sd_ReferenceClock / sd_clock_khz;
-
- // choose slower clock if system clock cannot divisible by wanted clock
- if (_sd_ReferenceClock % sd_clock_khz != 0)
- rate++;
-
- if(rate >= SD_CLK_DIV0_MAX) {
- rate = SD_CLK_DIV0_MAX;
- }
-
- //--- calculate the second divider CLKDIV0[SDHOST_N]
- div1 = ((rate -1) & 0xFF);
-
- //--- setup register
- CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDHDIV_Msk;
- CLK->CLKDIV0 |= (div1 << CLK_CLKDIV0_SDHDIV_Pos);
-
- for(i=0; i<1000; i++); // waiting for clock become stable
- return;
-}
-
-void SD_CardSelect(int cardSel)
-{
- if(cardSel == 0) {
- SD->CTL |= (SD->CTL & ~SDH_CTL_SDPORT_Msk);
- } else if(cardSel == 1) {
- SD->CTL |= ((SD->CTL & ~SDH_CTL_SDPORT_Msk) | (1 << SDH_CTL_SDPORT_Pos));
- }
-}
-
-uint32_t SD_CardDetection(uint32_t u32CardNum)
-{
- uint32_t i;
-
- if (u32CardNum == SD_PORT0) {
- if(SD->INTEN & SDH_INTEN_CDSRC0_Msk) { // Card detect pin from GPIO
- if(SD->INTSTS & SDH_INTSTS_CDSTS0_Msk) { // Card remove
- SD0.IsCardInsert = FALSE;
- return FALSE;
- } else
- SD0.IsCardInsert = TRUE;
- } else if(!(SD->INTEN & SDH_INTEN_CDSRC0_Msk)) {
- SD->CTL |= SDH_CTL_CLKKEEP0_Msk;
- for(i= 0; i < 5000; i++);
-
- if(SD->INTSTS & SDH_INTSTS_CDSTS0_Msk) // Card insert
- SD0.IsCardInsert = TRUE;
- else {
- SD0.IsCardInsert = FALSE;
- return FALSE;
- }
-
- SD->CTL &= ~SDH_CTL_CLKKEEP0_Msk;
- }
-
- } else if (u32CardNum == SD_PORT1) {
- if(SD->INTEN & SDH_INTEN_CDSRC1_Msk) { // Card detect pin from GPIO
- if(SD->INTSTS & SDH_INTSTS_CDSTS1_Msk) { // Card remove
- SD1.IsCardInsert = FALSE;
- return FALSE;
- } else
- SD1.IsCardInsert = TRUE;
- } else if(!(SD->INTEN & SDH_INTEN_CDSRC1_Msk)) {
- SD->CTL |= SDH_CTL_CLKKEEP1_Msk;
- for(i= 0; i < 5000; i++);
-
- if(SD->INTSTS & SDH_INTSTS_CDSTS1_Msk) // Card insert
- SD1.IsCardInsert = TRUE;
- else {
- SD1.IsCardInsert = FALSE;
- return FALSE;
- }
-
- SD->CTL &= ~SDH_CTL_CLKKEEP1_Msk;
- }
-
- }
-
- return TRUE;
-}
-
-
-// Initial
-int SD_Init(SD_INFO_T *pSD)
-{
- int volatile i, status;
- unsigned int resp;
- unsigned int CIDBuffer[4];
- unsigned int volatile u32CmdTimeOut;
-
- // set the clock to 200KHz
- //SD_Set_clock(200);
- SD_Set_clock(100);
-
- // power ON 74 clock
- SD->CTL |= SDH_CTL_CLK74OEN_Msk;
-
- while(SD->CTL & SDH_CTL_CLK74OEN_Msk) {
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- SD_SDCommand(pSD, 0, 0); // reset all cards
- for (i=0x1000; i>0; i--);
-
- // initial SDHC
- _sd_uR7_CMD = 1;
- //u32CmdTimeOut = 5000;
- u32CmdTimeOut = 0xFFFFF;
- //u32CmdTimeOut = 0;
-
- i = SD_SDCmdAndRsp(pSD, 8, 0x00000155, u32CmdTimeOut);
- if (i == Successful) {
- // SD 2.0
- SD_SDCmdAndRsp(pSD, 55, 0x00, u32CmdTimeOut);
- _sd_uR3_CMD = 1;
- SD_SDCmdAndRsp(pSD, 41, 0x40ff8000, u32CmdTimeOut); // 2.7v-3.6v
- resp = SD->RESP0;
-
- while (!(resp & 0x00800000)) { // check if card is ready
- SD_SDCmdAndRsp(pSD, 55, 0x00, u32CmdTimeOut);
- _sd_uR3_CMD = 1;
- SD_SDCmdAndRsp(pSD, 41, 0x40ff8000, u32CmdTimeOut); // 3.0v-3.4v
- resp = SD->RESP0;
- }
- if (resp & 0x00400000)
- pSD->CardType = SD_TYPE_SD_HIGH;
- else
- pSD->CardType = SD_TYPE_SD_LOW;
- } else {
- // SD 1.1
- SD_SDCommand(pSD, 0, 0); // reset all cards
- for (i=0x100; i>0; i--);
-
- i = SD_SDCmdAndRsp(pSD, 55, 0x00, u32CmdTimeOut);
- if (i == 2) { // MMC memory
-
- SD_SDCommand(pSD, 0, 0); // reset
- for (i=0x100; i>0; i--);
-
- _sd_uR3_CMD = 1;
-
- if (SD_SDCmdAndRsp(pSD, 1, 0x40ff8000, u32CmdTimeOut) != 2) { // eMMC memory
- resp = SD->RESP0;
- while (!(resp & 0x00800000)) { // check if card is ready
- _sd_uR3_CMD = 1;
-
- SD_SDCmdAndRsp(pSD, 1, 0x40ff8000, u32CmdTimeOut); // high voltage
- resp = SD->RESP0;
- }
-
- if(resp & 0x00400000)
- pSD->CardType = SD_TYPE_EMMC;
- else
- pSD->CardType = SD_TYPE_MMC;
- } else {
- pSD->CardType = SD_TYPE_UNKNOWN;
- return SD_ERR_DEVICE;
- }
- } else if (i == 0) { // SD Memory
- _sd_uR3_CMD = 1;
- SD_SDCmdAndRsp(pSD, 41, 0x00ff8000, u32CmdTimeOut); // 3.0v-3.4v
- resp = SD->RESP0;
- while (!(resp & 0x00800000)) { // check if card is ready
- SD_SDCmdAndRsp(pSD, 55, 0x00,u32CmdTimeOut);
- _sd_uR3_CMD = 1;
- SD_SDCmdAndRsp(pSD, 41, 0x00ff8000, u32CmdTimeOut); // 3.0v-3.4v
- resp = SD->RESP0;
- }
- pSD->CardType = SD_TYPE_SD_LOW;
- } else {
- pSD->CardType = SD_TYPE_UNKNOWN;
- return SD_INIT_ERROR;
- }
- }
-
- // CMD2, CMD3
- if (pSD->CardType != SD_TYPE_UNKNOWN) {
- SD_SDCmdAndRsp2(pSD, 2, 0x00, CIDBuffer);
- if ((pSD->CardType == SD_TYPE_MMC) || (pSD->CardType == SD_TYPE_EMMC)) {
- if ((status = SD_SDCmdAndRsp(pSD, 3, 0x10000, 0)) != Successful) // set RCA
- return status;
- pSD->RCA = 0x10000;
- } else {
- if ((status = SD_SDCmdAndRsp(pSD, 3, 0x00, 0)) != Successful) // get RCA
- return status;
- else
- pSD->RCA = (SD->RESP0 << 8) & 0xffff0000;
- }
- }
-
- return Successful;
-}
-
-
-int SD_SwitchToHighSpeed(SD_INFO_T *pSD)
-{
- int volatile status=0;
- uint16_t current_comsumption, busy_status0;
-
- SD->DMASA = (uint32_t)_sd_pSDHCBuffer; // set DMA transfer starting address
- SD->BLEN = 63; // 512 bit
-
- if ((status = SD_SDCmdAndRspDataIn(pSD, 6, 0x00ffff01)) != Successful)
- return Fail;
-
- current_comsumption = _sd_pSDHCBuffer[0]<<8 | _sd_pSDHCBuffer[1];
- if (!current_comsumption)
- return Fail;
-
- busy_status0 = _sd_pSDHCBuffer[28]<<8 | _sd_pSDHCBuffer[29];
-
- if (!busy_status0) { // function ready
- SD->DMASA = (uint32_t)_sd_pSDHCBuffer; // set DMA transfer starting address
- SD->BLEN = 63; // 512 bit
-
- if ((status = SD_SDCmdAndRspDataIn(pSD, 6, 0x80ffff01)) != Successful)
- return Fail;
-
- // function change timing: 8 clocks
- SD->CTL |= SDH_CTL_CLK8OEN_Msk;
- while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
-
- current_comsumption = _sd_pSDHCBuffer[0]<<8 | _sd_pSDHCBuffer[1];
- if (!current_comsumption)
- return Fail;
-
- return Successful;
- } else
- return Fail;
-}
-
-
-int SD_SelectCardType(SD_INFO_T *pSD)
-{
- int volatile status=0;
- unsigned int arg;
-
- if ((status = SD_SDCmdAndRsp(pSD, 7, pSD->RCA, 0)) != Successful)
- return status;
-
- SD_CheckRB();
-
- // if SD card set 4bit
- if (pSD->CardType == SD_TYPE_SD_HIGH) {
- _sd_pSDHCBuffer = (uint8_t *)((uint32_t)_sd_ucSDHCBuffer);
- SD->DMASA = (uint32_t)_sd_pSDHCBuffer; // set DMA transfer starting address
- SD->BLEN = 0x07; // 64 bit
-
- if ((status = SD_SDCmdAndRsp(pSD, 55, pSD->RCA, 0)) != Successful)
- return status;
- if ((status = SD_SDCmdAndRspDataIn(pSD, 51, 0x00)) != Successful)
- return status;
-
- if ((_sd_ucSDHCBuffer[0] & 0xf) == 0x2) {
- status = SD_SwitchToHighSpeed(pSD);
- if (status == Successful) {
- /* divider */
- SD_Set_clock(SDHC_FREQ);
- }
- }
-
- if ((status = SD_SDCmdAndRsp(pSD, 55, pSD->RCA, 0)) != Successful)
- return status;
- if ((status = SD_SDCmdAndRsp(pSD, 6, 0x02, 0)) != Successful) // set bus width
- return status;
-
- SD->CTL |= SDH_CTL_DBW_Msk;
- } else if (pSD->CardType == SD_TYPE_SD_LOW) {
- _sd_pSDHCBuffer = (uint8_t *)((uint32_t)_sd_ucSDHCBuffer);
- SD->DMASA = (uint32_t) _sd_pSDHCBuffer; // set DMA transfer starting address
- SD->BLEN = 0x07; // 64 bit
-
- if ((status = SD_SDCmdAndRsp(pSD, 55, pSD->RCA, 0)) != Successful)
- return status;
- if ((status = SD_SDCmdAndRspDataIn(pSD, 51, 0x00)) != Successful)
- return status;
-
- // set data bus width. ACMD6 for SD card, SDCR_DBW for host.
- if ((status = SD_SDCmdAndRsp(pSD, 55, pSD->RCA, 0)) != Successful)
- return status;
-
- if ((status = SD_SDCmdAndRsp(pSD, 6, 0x02, 0)) != Successful) // set bus width
- return status;
-
- SD->CTL |= SDH_CTL_DBW_Msk;
- } else if ((pSD->CardType == SD_TYPE_MMC) ||(pSD->CardType == SD_TYPE_EMMC)) {
-
- if(pSD->CardType == SD_TYPE_MMC)
- SD->CTL &= ~SDH_CTL_DBW_Msk;
-
- //--- sent CMD6 to MMC card to set bus width to 4 bits mode
- // set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode)
- arg = (3 << 24) | (183 << 16) | (1 << 8);
- if ((status = SD_SDCmdAndRsp(pSD, 6, arg, 0)) != Successful)
- return status;
- SD_CheckRB();
-
- SD->CTL |= SDH_CTL_DBW_Msk;; // set bus width to 4-bit mode for SD host controller
-
- }
-
- if ((status = SD_SDCmdAndRsp(pSD, 16, SD_BLOCK_SIZE, 0)) != Successful) // set block length
- return status;
- SD->BLEN = SD_BLOCK_SIZE - 1; // set the block size
-
- SD_SDCommand(pSD, 7, 0);
- SD->CTL |= SDH_CTL_CLK8OEN_Msk;
- while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
-
-#ifdef _SD_USE_INT_
- SD->INTEN |= SDH_INTEN_BLKDIEN_Msk;
-#endif //_SD_USE_INT_
-
- return Successful;
-}
-
-void SD_Get_SD_info(SD_INFO_T *pSD, DISK_DATA_T *_info)
-{
- unsigned int R_LEN, C_Size, MULT, size;
- unsigned int Buffer[4];
- unsigned char *ptr;
-
- SD_SDCmdAndRsp2(pSD, 9, pSD->RCA, Buffer);
-
- if ((pSD->CardType == SD_TYPE_MMC) || (pSD->CardType == SD_TYPE_EMMC)) {
- // for MMC/eMMC card
- if ((Buffer[0] & 0xc0000000) == 0xc0000000) {
- // CSD_STRUCTURE [127:126] is 3
- // CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB
- SD_SDCmdAndRsp(pSD, 7, pSD->RCA, 0);
-
- ptr = (uint8_t *)((uint32_t)_sd_ucSDHCBuffer );
- SD->DMASA = (uint32_t)ptr; // set DMA transfer starting address
- SD->BLEN = 511; // read 512 bytes for EXT_CSD
-
- if (SD_SDCmdAndRspDataIn(pSD, 8, 0x00) != Successful)
- return;
-
- SD_SDCommand(pSD, 7, 0);
- SD->CTL |= SDH_CTL_CLK8OEN_Msk;
- while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
-
- _info->totalSectorN = (*(uint32_t *)(ptr+212));
- _info->diskSize = _info->totalSectorN / 2;
- } else {
- // CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB
- R_LEN = (Buffer[1] & 0x000f0000) >> 16;
- C_Size = ((Buffer[1] & 0x000003ff) << 2) | ((Buffer[2] & 0xc0000000) >> 30);
- MULT = (Buffer[2] & 0x00038000) >> 15;
- size = (C_Size+1) * (1<<(MULT+2)) * (1<<R_LEN);
-
- _info->diskSize = size / 1024;
- _info->totalSectorN = size / 512;
- }
- } else {
- if (Buffer[0] & 0xc0000000) {
- C_Size = ((Buffer[1] & 0x0000003f) << 16) | ((Buffer[2] & 0xffff0000) >> 16);
- size = (C_Size+1) * 512; // Kbytes
-
- _info->diskSize = size;
- _info->totalSectorN = size << 1;
- } else {
- R_LEN = (Buffer[1] & 0x000f0000) >> 16;
- C_Size = ((Buffer[1] & 0x000003ff) << 2) | ((Buffer[2] & 0xc0000000) >> 30);
- MULT = (Buffer[2] & 0x00038000) >> 15;
- size = (C_Size+1) * (1<<(MULT+2)) * (1<<R_LEN);
-
- _info->diskSize = size / 1024;
- _info->totalSectorN = size / 512;
- }
- }
-
- _info->sectorSize = 512;
-}
-
-int SD_ChipErase(SD_INFO_T *pSD, DISK_DATA_T *_info)
-{
- int status=0;
-
- status = SD_SDCmdAndRsp(pSD, 32, 512, 6000);
- if (status < 0) {
- return status;
- }
- status = SD_SDCmdAndRsp(pSD, 33, _info->totalSectorN*512, 6000);
- if (status < 0) {
- return status;
- }
- status = SD_SDCmdAndRsp(pSD, 38, 0, 6000);
- if (status < 0) {
- return status;
- }
- SD_CheckRB();
-
- return 0;
-}
-
-/// @endcond HIDDEN_SYMBOLS
-
-
-/**
- * @brief This function use to reset SD function and select card detection source and pin.
- *
- * @param[in] u32CardDetSrc Select card detection source from SD0 or SD1. ( \ref SD_PORT0 / \ref SD_PORT1) \n
- * And also select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3)
- *
- * @return None
- */
-void SD_Open(uint32_t u32CardDetSrc)
-{
- // Enable SD Card Host Controller operation.
- //CLK->AHBCLK |= CLK_AHBCLK_SDHCKEN_Msk;
-
- // enable DMAC
- SD->DMACTL = SDH_DMACTL_DMARST_Msk;
- while(SD->DMACTL & SDH_DMACTL_DMARST_Msk);
-
- SD->DMACTL = SDH_DMACTL_DMAEN_Msk;
-
- //Reset FMI
- SD->GCTL = SDH_GCTL_GCTLRST_Msk; // Start reset FMI controller.
- while(SD->GCTL & SDH_GCTL_GCTLRST_Msk);
-
-
-//#ifdef _SD_USE_INT_
-// NVIC_EnableIRQ(SD_IRQn);
-//#endif //_SD_USE_INT_
-
- // enable SD
- SD->GCTL = SDH_GCTL_SDEN_Msk;
-
- if(u32CardDetSrc & SD_PORT0) {
- SD->CTL |= (SD->CTL & ~SDH_CTL_SDPORT_Msk);
-
- if(u32CardDetSrc & CardDetect_From_DAT3) {
- SD->INTEN &= ~SDH_INTEN_CDSRC0_Msk;
- } else {
- SD->INTEN |= SDH_INTEN_CDSRC0_Msk;
- }
- } else if(u32CardDetSrc & SD_PORT1) {
- SD->CTL |= ((SD->CTL & ~SDH_CTL_SDPORT_Msk) | (1 << SDH_CTL_SDPORT_Pos));
-
- if(u32CardDetSrc & CardDetect_From_DAT3) {
- SD->INTEN &= ~SDH_INTEN_CDSRC1_Msk;
- } else {
- SD->INTEN |= SDH_INTEN_CDSRC1_Msk;
- }
- }
-
- SD->CTL |= SDH_CTL_CTLRST_Msk; // SD software reset
- while(SD->CTL & SDH_CTL_CTLRST_Msk);
-
- SD->CTL &= ~((0xFF) | (SDH_CTL_CLKKEEP1_Msk)); // disable SD clock output
-
- if(u32CardDetSrc & SD_PORT0) {
- memset(&SD0, 0, sizeof(SD_INFO_T));
- } else if(u32CardDetSrc & SD_PORT1) {
- memset(&SD1, 0, sizeof(SD_INFO_T));
- }
-
-}
-
-/**
- * @brief This function use to initial SD card.
- *
- * @param[in] u32CardNum Select initial SD0 or SD1. ( \ref SD_PORT0 / \ref SD_PORT1)
- *
- * @return None
- */
-void SD_Probe(uint32_t u32CardNum)
-{
- // Disable FMI/SD host interrupt
- SD->GINTEN = 0;
-
- SD->CTL &= ~SDH_CTL_SDNWR_Msk;
- SD->CTL |= 0x09 << SDH_CTL_SDNWR_Pos; // set SDNWR = 9
- SD->CTL &= ~SDH_CTL_BLKCNT_Msk;
- SD->CTL |= 0x01 << SDH_CTL_BLKCNT_Pos; // set BLKCNT = 1
- SD->CTL &= ~SDH_CTL_DBW_Msk; // SD 1-bit data bus
-
- if(!(SD_CardDetection(u32CardNum)))
- return;
-
- if (u32CardNum == SD_PORT0) {
- if (SD_Init(&SD0) < 0)
- return;
-
- /* divider */
- if (SD0.CardType == SD_TYPE_MMC)
- SD_Set_clock(20000);
- else
- SD_Set_clock(SD_FREQ);
-
- SD_Get_SD_info(&SD0, &SD_DiskInfo0);
-
- if (SD_SelectCardType(&SD0))
- return;
-
- sd0_ok = 1;
- } else if (u32CardNum == SD_PORT1) {
- if (SD_Init(&SD1) < 0)
- return;
-
- /* divider */
- if (SD1.CardType == SD_TYPE_MMC)
- SD_Set_clock(20000);
- else
- SD_Set_clock(SD_FREQ);
-
- SD_Get_SD_info(&SD1, &SD_DiskInfo1);
-
- if (SD_SelectCardType(&SD1))
- return;
-
- sd1_ok = 1;
- }
-
-
-}
-
-/**
- * @brief This function use to read data from SD card.
- *
- * @param[in] u32CardNum Select card: SD0 or SD1. ( \ref SD_PORT0 / \ref SD_PORT1)
- * @param[out] pu8BufAddr The buffer to receive the data from SD card.
- * @param[in] u32StartSec The start read sector address.
- * @param[in] u32SecCount The the read sector number of data
- *
- * @return None
- */
-uint32_t SD_Read(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
-{
- char volatile bIsSendCmd = FALSE, buf;
- unsigned int volatile reg;
- int volatile i, loop, status;
- uint32_t blksize = SD_BLOCK_SIZE;
-
- SD_INFO_T *pSD;
-
- if(u32CardNum == SD_PORT0)
- pSD = &SD0;
- else
- pSD = &SD1;
-
- //--- check input parameters
- if (u32SecCount == 0) {
- return SD_SELECT_ERROR;
- }
-
- if ((status = SD_SDCmdAndRsp(pSD, 7, pSD->RCA, 0)) != Successful)
- return status;
- SD_CheckRB();
-
- SD->BLEN = blksize - 1; // the actual byte count is equal to (SDBLEN+1)
-
- if ( (pSD->CardType == SD_TYPE_SD_HIGH) || (pSD->CardType == SD_TYPE_EMMC) )
- SD->CMDARG = u32StartSec;
- else
- SD->CMDARG = u32StartSec * blksize;
-
- SD->DMASA = (uint32_t)pu8BufAddr;
-
- loop = u32SecCount / 255;
- for (i=0; i<loop; i++) {
-#ifdef _SD_USE_INT_
- _sd_SDDataReady = FALSE;
-#endif //_SD_USE_INT_
-
- reg = SD->CTL & ~SDH_CTL_CMDCODE_Msk;
- reg = reg | 0xff0000; // set BLK_CNT to 255
- if (bIsSendCmd == FALSE) {
- SD->CTL = reg|(18<<8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
- bIsSendCmd = TRUE;
- } else
- SD->CTL = reg | SDH_CTL_DIEN_Msk;
-
-#ifdef _SD_USE_INT_
- while(!_sd_SDDataReady)
-#else
- while(1)
-#endif //_SD_USE_INT_
- {
- if(_sd_SDDataReady) break;
-
-#ifndef _SD_USE_INT_
- if ((SD->INTSTS & SDH_INTSTS_BLKDIF_Msk) && (!(SD->CTL & SDH_CTL_DIEN_Msk))) {
- SD->INTSTS = SDH_INTSTS_BLKDIF_Msk;
- break;
- }
-#endif
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- if (!(SD->INTSTS & SDH_INTSTS_CRC7_Msk)) { // check CRC7
- //printf("sdioSD_Read_in_blksize(): response error!\n");
- return SD_CRC7_ERROR;
- }
-
- if (!(SD->INTSTS & SDH_INTSTS_CRC16_Msk)) { // check CRC16
- //printf("sdioSD_Read_in_blksize() :read data error!\n");
- return SD_CRC16_ERROR;
- }
- }
-
- loop = u32SecCount % 255;
- if (loop != 0) {
-#ifdef _SD_USE_INT_
- _sd_SDDataReady = FALSE;
-#endif //_SD_USE_INT_
-
- reg = SD->CTL & (~SDH_CTL_CMDCODE_Msk);
- reg = reg & (~SDH_CTL_BLKCNT_Msk);
- reg |= (loop << 16); // setup SDCR_BLKCNT
-
- if (bIsSendCmd == FALSE) {
- SD->CTL = reg|(18<<8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
- bIsSendCmd = TRUE;
- } else
- SD->CTL = reg | SDH_CTL_DIEN_Msk;
-
-#ifdef _SD_USE_INT_
- while(!_sd_SDDataReady)
-#else
- while(1)
-#endif //_SD_USE_INT_
- {
-
-#ifndef _SD_USE_INT_
- if ((SD->INTSTS & SDH_INTSTS_BLKDIF_Msk) && (!(SD->CTL & SDH_CTL_DIEN_Msk))) {
- SD->INTSTS = SDH_INTSTS_BLKDIF_Msk;
- break;
- }
-#endif
-
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- if (!(SD->INTSTS & SDH_INTSTS_CRC7_Msk)) { // check CRC7
- //printf("sdioSD_Read_in_blksize(): response error!\n");
- return SD_CRC7_ERROR;
- }
-
- if (!(SD->INTSTS & SDH_INTSTS_CRC16_Msk)) { // check CRC16
- //printf("sdioSD_Read_in_blksize(): read data error!\n");
- return SD_CRC16_ERROR;
- }
- }
-
- if (SD_SDCmdAndRsp(pSD, 12, 0, 0)) { // stop command
- //printf("stop command fail !!\n");
- return SD_CRC7_ERROR;
- }
- SD_CheckRB();
-
- SD_SDCommand(pSD, 7, 0);
- SD->CTL |= SDH_CTL_CLK8OEN_Msk;
- while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
-
- return Successful;
-}
-
-
-/**
- * @brief This function use to write data to SD card.
- *
- * @param[in] u32CardNum Select card: SD0 or SD1. ( \ref SD_PORT0 / \ref SD_PORT1)
- * @param[in] pu8BufAddr The buffer to send the data to SD card.
- * @param[in] u32StartSec The start write sector address.
- * @param[in] u32SecCount The the write sector number of data.
- *
- * @return \ref SD_SELECT_ERROR : u32SecCount is zero. \n
- * \ref SD_NO_SD_CARD : SD card be removed. \n
- * \ref SD_CRC_ERROR : CRC error happen. \n
- * \ref SD_CRC7_ERROR : CRC7 error happen. \n
- * \ref Successful : Write data to SD card success.
- */
-uint32_t SD_Write(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
-{
- char volatile bIsSendCmd = FALSE;
- unsigned int volatile reg;
- int volatile i, loop, status;
-
- SD_INFO_T *pSD;
-
- if(u32CardNum == SD_PORT0)
- pSD = &SD0;
- else
- pSD = &SD1;
-
-
- //--- check input parameters
- if (u32SecCount == 0) {
- return SD_SELECT_ERROR;
- }
-
- if ((status = SD_SDCmdAndRsp(pSD, 7, pSD->RCA, 0)) != Successful)
- return status;
-
- SD_CheckRB();
-
- // According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n.
- SD->BLEN = SD_BLOCK_SIZE - 1; // set the block size
-
- if ((pSD->CardType == SD_TYPE_SD_HIGH) || (pSD->CardType == SD_TYPE_EMMC))
- SD->CMDARG = u32StartSec;
- else
- SD->CMDARG = u32StartSec * SD_BLOCK_SIZE; // set start address for SD CMD
-
- SD->DMASA = (uint32_t)pu8BufAddr;
- loop = u32SecCount / 255; // the maximum block count is 0xFF=255 for register SDCR[BLK_CNT]
- for (i=0; i<loop; i++) {
-#ifdef _SD_USE_INT_
- _sd_SDDataReady = FALSE;
-#endif //_SD_USE_INT_
-
- reg = SD->CTL & 0xff00c080;
- reg = reg | 0xff0000; // set BLK_CNT to 0xFF=255
- if (!bIsSendCmd) {
- SD->CTL = reg|(25<<8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
- bIsSendCmd = TRUE;
- } else
- SD->CTL = reg | SDH_CTL_DOEN_Msk;
-
-#ifdef _SD_USE_INT_
- while(!_sd_SDDataReady)
-#else
- while(1)
-#endif //_SD_USE_INT_
- {
-#ifndef _SD_USE_INT_
- if ((SD->INTSTS & SDH_INTSTS_BLKDIF_Msk) && (!(SD->CTL & SDH_CTL_DOEN_Msk))) {
- SD->INTSTS = SDH_INTSTS_BLKDIF_Msk;
- break;
- }
-#endif
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- if ((SD->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0) { // check CRC
- SD->INTSTS = SDH_INTSTS_CRCIF_Msk;
- return SD_CRC_ERROR;
- }
- }
-
- loop = u32SecCount % 255;
- if (loop != 0) {
-#ifdef _SD_USE_INT_
- _sd_SDDataReady = FALSE;
-#endif //_SD_USE_INT_
-
- reg = (SD->CTL & 0xff00c080) | (loop << 16);
- if (!bIsSendCmd) {
- SD->CTL = reg|(25<<8)|(SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
- bIsSendCmd = TRUE;
- } else
- SD->CTL = reg | SDH_CTL_DOEN_Msk;
-
-#ifdef _SD_USE_INT_
- while(!_sd_SDDataReady)
-#else
- while(1)
-#endif //_SD_USE_INT_
- {
-#ifndef _SD_USE_INT_
- if ((SD->INTSTS & SDH_INTSTS_BLKDIF_Msk) && (!(SD->CTL & SDH_CTL_DOEN_Msk))) {
- SD->INTSTS = SDH_INTSTS_BLKDIF_Msk;
- break;
- }
-#endif
- if (pSD->IsCardInsert == FALSE)
- return SD_NO_SD_CARD;
- }
-
- if ((SD->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0) { // check CRC
- SD->INTSTS = SDH_INTSTS_CRCIF_Msk;
- return SD_CRC_ERROR;
- }
- }
- SD->INTSTS = SDH_INTSTS_CRCIF_Msk;
-
- if (SD_SDCmdAndRsp(pSD, 12, 0, 0)) { // stop command
- return SD_CRC7_ERROR;
- }
- SD_CheckRB();
-
- SD_SDCommand(pSD, 7, 0);
- SD->CTL |= SDH_CTL_CLK8OEN_Msk;
- while(SD->CTL & SDH_CTL_CLK8OEN_Msk);
-
- return Successful;
-}
-
-
-/*@}*/ /* end of group NUC472_442_SD_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SD_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
-
-
-
-
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sd.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,201 +0,0 @@
-/**************************************************************************//**
- * @file sd.h
- * @version V1.00
- * $Revision: 12 $
- * $Date: 14/11/04 10:10a $
- * @brief NUC472/NUC442 SD driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include <stdio.h>
-
-#ifndef __SD_H__
-#define __SD_H__
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SD_Driver SD Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_SD_EXPORTED_CONSTANTS SD Exported Constants
- @{
-*/
-
-#define SD_CARD 0
-#define SD_ERR_ID 0xFFFF0100
-
-#define SD_TIMEOUT (SD_ERR_ID|0x01)
-#define SD_NO_MEMORY (SD_ERR_ID|0x02)
-
-//-- function return value
-#define Successful 0
-#define Fail 1
-
-//--- define type of SD card or MMC
-#define SD_TYPE_UNKNOWN 0
-#define SD_TYPE_SD_HIGH 1
-#define SD_TYPE_SD_LOW 2
-#define SD_TYPE_MMC 3
-#define SD_TYPE_EMMC 4
-
-/* SD error */
-#define SD_NO_SD_CARD (SD_ERR_ID|0x10)
-#define SD_ERR_DEVICE (SD_ERR_ID|0x11)
-#define SD_INIT_TIMEOUT (SD_ERR_ID|0x12)
-#define SD_SELECT_ERROR (SD_ERR_ID|0x13)
-#define SD_WRITE_PROTECT (SD_ERR_ID|0x14)
-#define SD_INIT_ERROR (SD_ERR_ID|0x15)
-#define SD_CRC7_ERROR (SD_ERR_ID|0x16)
-#define SD_CRC16_ERROR (SD_ERR_ID|0x17)
-#define SD_CRC_ERROR (SD_ERR_ID|0x18)
-#define SD_CMD8_ERROR (SD_ERR_ID|0x19)
-
-#define SD_FREQ 12000
-#define SDHC_FREQ 12000
-
-#define STOR_STRING_LEN 32
-
-#define SD_PORT0 (1 << 0) /*!< Card select SD0 \hideinitializer */
-#define SD_PORT1 (1 << 2) /*!< Card select SD1 \hideinitializer */
-
-#define CardDetect_From_GPIO (1 << 8) /*!< Card detection pin is GPIO \hideinitializer */
-#define CardDetect_From_DAT3 (1 << 9) /*!< Card detection pin is DAT3 \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_SD_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_SD_EXPORTED_TYPEDEF SD Exported Type Defines
- @{
-*/
-typedef struct SD_info_t {
- uint32_t CardType; /*!< SDHC, SD, or MMC */
- uint32_t RCA; /*!< relative card address */
- uint8_t IsCardInsert; /*!< card insert state */
-} SD_INFO_T;
-
-/* we allocate one of these for every device that we remember */
-typedef struct disk_data_t {
- struct disk_data_t *next; /*!< next device */
-
- /* information about the device -- always good */
- unsigned int totalSectorN; /*!< total sector number */
- unsigned int diskSize; /*!< disk size in Kbytes */
- int sectorSize; /*!< sector size in bytes */
- char vendor[STOR_STRING_LEN]; /*!< SD card vendor */
- char product[STOR_STRING_LEN]; /*!< *SD card product id */
- char serial[STOR_STRING_LEN]; /*!< SD card serial number */
-} DISK_DATA_T;
-
-/*@}*/ /* end of group NUC472_442_SD_EXPORTED_TYPEDEF */
-
-/// @cond HIDDEN_SYMBOLS
-extern SD_INFO_T SD0;
-extern SD_INFO_T SD1;
-/// @endcond HIDDEN_SYMBOLS
-
-/** @addtogroup NUC472_442_SD_EXPORTED_FUNCTIONS SD Exported Functions
- @{
-*/
-
-
-
-
-/**
- * @brief Enable specified interrupt.
- *
- * @param[in] u32IntMask Interrupt type mask:
- * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
- * \ref SDH_INTEN_CDSRC0_Msk / \ref SDH_INTEN_CDSRC1_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
- * \ref SDH_INTEN_WKIEN_Msk
- *
- * @return None.
- * \hideinitializer
- */
-#define SD_ENABLE_INT(u32IntMask) (SD->INTEN |= (u32IntMask))
-
-/**
- * @brief Disable specified interrupt.
- *
- * @param[in] u32IntMask Interrupt type mask:
- * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
- * \ref SDH_INTEN_SDHOST0IEN_Msk / \ref SDH_INTEN_SDHOST1IEN_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
- * \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC0_Msk / \ref SDH_INTEN_CDSRC1_Msk
- *
- * @return None.
- * \hideinitializer
- */
-#define SD_DISABLE_INT(u32IntMask) (SD->INTEN &= ~(u32IntMask))
-
-/**
- * @brief Get specified interrupt flag/status.
- *
- * @param[in] u32IntMask Interrupt type mask:
- * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
- * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / \ref SDH_INTSTS_CDIF0_Msk /
- * \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_SDHOST0IF_Msk / \ref SDH_INTSTS_SDHOST1IF_Msk / \ref SDH_INTSTS_RTOIF_Msk /
- * \ref SDH_INTSTS_DINTOIF_Msk / \ref SDH_INTSTS_CDSTS0_Msk / \ref SDH_INTSTS_CDSTS1_Msk / \ref SDH_INTSTS_DAT1STS_Msk
- *
- *
- * @return 0 = The specified interrupt is not happened.
- * 1 = The specified interrupt is happened.
- * \hideinitializer
- */
-#define SD_GET_INT_FLAG(u32IntMask) ((SD->INTSTS & (u32IntMask))?1:0)
-
-
-/**
- * @brief Clear specified interrupt flag/status.
- *
- * @param[in] u32IntMask Interrupt type mask:
- * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF0_Msk /
- * \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_SDHOST0IF_Msk / \ref SDH_INTSTS_SDHOST1IF_Msk /
- * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DINTOIF_Msk
- *
- *
- * @return None.
- * \hideinitializer
- */
-#define SD_CLR_INT_FLAG(u32IntMask) (SD->INTSTS = u32IntMask)
-
-
-/**
- * @brief Check SD Card inserted or removed.
- *
- * @param[in] u32CardNum Select SD0 or SD1. ( \ref SD_PORT0 / \ref SD_PORT1)
- *
- * @return 1: Card inserted.
- * 0: Card removed.
- * \hideinitializer
- */
-#define SD_IS_CARD_PRESENT(u32CardNum) ((u32CardNum & (SD_PORT0))?(SD0.IsCardInsert):(SD1.IsCardInsert))
-
-/**
- * @brief Get SD Card capacity.
- *
- * @param[in] u32CardNum Select SD0 or SD1. ( \ref SD_PORT0 / \ref SD_PORT1)
- *
- * @return SD Card capacity. (unit: KByte)
- * \hideinitializer
- */
-#define SD_GET_CARD_CAPACITY(u32CardNum) ((u32CardNum & (SD_PORT0))?(SD_DiskInfo0.diskSize):(SD_DiskInfo1.diskSize))
-
-
-void SD_Open(uint32_t u32CardDetSrc);
-void SD_Probe(uint32_t u32CardNum);
-uint32_t SD_Read(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
-uint32_t SD_Write(uint32_t u32CardNum, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
-
-
-
-/*@}*/ /* end of group NUC472_442_ADC_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_ADC_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#endif //end of __SD_H__
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,334 +0,0 @@
-/****************************************************************************//**
- * @file spi.c
- * @version V0.10
- * $Revision: 15 $
- * $Date: 14/09/30 1:10p $
- * @brief NUC472/NUC442 SPI driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SPI_Driver SPI Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
- @{
-*/
-
-/**
- * @brief This function make SPI module be ready to transfer.
- * By default, the SPI transfer sequence is MSB first and
- * the automatic slave select function is disabled. In
- * Slave mode, the u32BusClock must be NULL and the SPI clock
- * divider setting will be 0.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. Valid values are:
- * - \ref SPI_SLAVE
- * - \ref SPI_MASTER
- * @param[in] u32SPIMode decides the transfer timing. Valid values are:
- * - \ref SPI_MODE_0
- * - \ref SPI_MODE_1
- * - \ref SPI_MODE_2
- * - \ref SPI_MODE_3
- * @param[in] u32DataWidth decides the data width of a SPI transaction.
- * @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz.
- * @return Actual frequency of SPI peripheral clock.
- */
-uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
-{
- if(u32DataWidth == 32)
- u32DataWidth = 0;
-
- spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode);
-
- return ( SPI_SetBusClock(spi, u32BusClock) );
-}
-
-/**
- * @brief Reset SPI module and disable SPI peripheral clock.
- * @param[in] spi is the base address of SPI module.
- * @return none
- */
-void SPI_Close(SPI_T *spi)
-{
- /* Reset SPI */
- if((uint32_t)spi == SPI0_BASE) {
- SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
- } else if((uint32_t)spi == SPI1_BASE) {
- SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
- } else if((uint32_t)spi == SPI2_BASE) {
- SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
- } else {
- SYS->IPRST1 |= SYS_IPRST1_SPI3RST_Msk;
- SYS->IPRST1 &= ~SYS_IPRST1_SPI3RST_Msk;
- }
-}
-
-/**
- * @brief Clear Rx FIFO buffer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- */
-void SPI_ClearRxFIFO(SPI_T *spi)
-{
- spi->FIFOCTL |= SPI_FIFOCTL_RXRST_Msk;
-}
-
-/**
- * @brief Clear Tx FIFO buffer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- */
-void SPI_ClearTxFIFO(SPI_T *spi)
-{
- spi->FIFOCTL |= SPI_FIFOCTL_TXRST_Msk;
-}
-
-/**
- * @brief Disable the automatic slave select function.
- * @param[in] spi is the base address of SPI module.
- * @return none
- */
-void SPI_DisableAutoSS(SPI_T *spi)
-{
- spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
-}
-
-/**
- * @brief Enable the automatic slave select function. Only available in Master mode.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32SSPinMask specifies slave select pins. Valid values are:
- * - \ref SPI_SS0
- * - \ref SPI_SS1
- * @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are:
- * - \ref SPI_SS_ACTIVE_HIGH
- * - \ref SPI_SS_ACTIVE_LOW
- * @return none
- */
-void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
-{
- spi->SSCTL |= (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
-}
-
-/**
- * @brief Set the SPI bus clock. Only available in Master mode.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32BusClock is the expected frequency of SPI bus clock.
- * @return Actual frequency of SPI peripheral clock.
- */
-uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
-{
- uint32_t u32ClkSrc, u32Div = 0;
-
- if(spi == SPI0) {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- } else if(spi == SPI1) {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- } else if(spi == SPI2) {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- } else {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- }
-
-
- if(u32BusClock != 0 ) {
- u32Div = (u32ClkSrc / u32BusClock) - 1;
- if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
- u32Div = SPI_CLKDIV_DIVIDER_Msk;
- }
-
- spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
-
- return ( u32ClkSrc / (u32Div+1) );
-}
-
-/**
- * @brief Set Tx FIFO threshold and Rx FIFO threshold configurations.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32TxThreshold decides the Tx FIFO threshold.
- * @param[in] u32RxThreshold decides the Rx FIFO threshold.
- * @return none
- */
-void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
-{
- spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
- (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
- (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
-}
-
-/**
- * @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
- * @param[in] spi is the base address of SPI module.
- * @return Actual SPI bus clock frequency.
- */
-uint32_t SPI_GetBusClock(SPI_T *spi)
-{
- uint32_t u32Div;
- uint32_t u32ClkSrc;
-
- if(spi == SPI0) {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI0SEL_Msk) == CLK_CLKSEL1_SPI0SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- } else if(spi == SPI1) {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI1SEL_Msk) == CLK_CLKSEL1_SPI1SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- } else if(spi == SPI2) {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI2SEL_Msk) == CLK_CLKSEL1_SPI2SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- } else {
- if((CLK->CLKSEL1 & CLK_CLKSEL1_SPI3SEL_Msk) == CLK_CLKSEL1_SPI3SEL_PCLK)
- u32ClkSrc = CLK_GetPCLKFreq();
- else
- u32ClkSrc = CLK_GetPLLClockFreq();
- }
-
- u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk;
- return (u32ClkSrc / (u32Div + 1));
-}
-
-/**
- * @brief Enable FIFO related interrupts specified by u32Mask parameter.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32Mask is the combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt bit.
- * This parameter decides which interrupts will be enabled. Valid values are:
- * - \ref SPI_UNITIEN_MASK
- * - \ref SPI_SSINAIEN_MASK
- * - \ref SPI_SSACTIEN_MASK
- * - \ref SPI_SLVURIEN_MASK
- * - \ref SPI_SLVBEIEN_MASK
- * - \ref SPI_SLVTOIEN_MASK
- * - \ref SPI_FIFO_TXTHIEN_MASK
- * - \ref SPI_FIFO_RXTHIEN_MASK
- * - \ref SPI_FIFO_RXOVIEN_MASK
- * - \ref SPI_FIFO_TXUFIEN_MASK
- * - \ref SPI_FIFO_RXTOIEN_MASK
- * @return none
- */
-void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
-{
- if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK)
- spi->CTL |= SPI_CTL_UNITIEN_Msk;
-
- if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK)
- spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
-
- if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK)
- spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
-
- if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK)
- spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
-
- if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK)
- spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
-
- if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK)
- spi->SSCTL |= SPI_SSCTL_SLVTOIEN_Msk;
-
- if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
-
- if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
-
- if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
-
- if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
-
- if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK)
- spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
-}
-
-/**
- * @brief Disable FIFO related interrupts specified by u32Mask parameter.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32Mask is the combination of all related interrupt enable bits.
- * Each bit corresponds to a interrupt bit.
- * This parameter decides which interrupts will be enabled. Valid values are:
- * - \ref SPI_UNITIEN_MASK
- * - \ref SPI_SSINAIEN_MASK
- * - \ref SPI_SSACTIEN_MASK
- * - \ref SPI_SLVURIEN_MASK
- * - \ref SPI_SLVBEIEN_MASK
- * - \ref SPI_SLVTOIEN_MASK
- * - \ref SPI_FIFO_TXTHIEN_MASK
- * - \ref SPI_FIFO_RXTHIEN_MASK
- * - \ref SPI_FIFO_RXOVIEN_MASK
- * - \ref SPI_FIFO_TXUFIEN_MASK
- * - \ref SPI_FIFO_RXTOIEN_MASK
- * @return none
- */
-void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
-{
- if((u32Mask & SPI_UNITIEN_MASK) == SPI_UNITIEN_MASK)
- spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
-
- if((u32Mask & SPI_SSINAIEN_MASK) == SPI_SSINAIEN_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
-
- if((u32Mask & SPI_SSACTIEN_MASK) == SPI_SSACTIEN_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
-
- if((u32Mask & SPI_SLVURIEN_MASK) == SPI_SLVURIEN_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
-
- if((u32Mask & SPI_SLVBEIEN_MASK) == SPI_SLVBEIEN_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
-
- if((u32Mask & SPI_SLVTOIEN_MASK) == SPI_SLVTOIEN_MASK)
- spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
-
- if((u32Mask & SPI_FIFO_TXTHIEN_MASK) == SPI_FIFO_TXTHIEN_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
-
- if((u32Mask & SPI_FIFO_RXTHIEN_MASK) == SPI_FIFO_RXTHIEN_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
-
- if((u32Mask & SPI_FIFO_RXOVIEN_MASK) == SPI_FIFO_RXOVIEN_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
-
- if((u32Mask & SPI_FIFO_TXUFIEN_MASK) == SPI_FIFO_TXUFIEN_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
-
- if((u32Mask & SPI_FIFO_RXTOIEN_MASK) == SPI_FIFO_RXTOIEN_MASK)
- spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
-}
-
-/*@}*/ /* end of group NUC472_442_SPI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SPI_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_spi.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,491 +0,0 @@
-/****************************************************************************//**
- * @file spi.h
- * @version V1.00
- * $Revision: 18 $
- * $Date: 14/10/06 1:36p $
- * @brief NUC472/NUC442 SPI driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#ifndef __SPI_H__
-#define __SPI_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SPI_Driver SPI Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SPI_EXPORTED_CONSTANTS SPI Exported Constants
- @{
-*/
-
-#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 \hideinitializer */
-#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 \hideinitializer */
-#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 \hideinitializer */
-#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 \hideinitializer */
-
-#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */
-#define SPI_MASTER (0x0) /*!< Set as master \hideinitializer */
-
-#define SPI_SS0 (0x1) /*!< Set SS0 \hideinitializer */
-#define SPI_SS1 (0x2) /*!< Set SS1 \hideinitializer */
-#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */
-#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low \hideinitializer */
-
-#define SPI_UNITIEN_MASK (0x001) /*!< Interrupt enable mask \hideinitializer */
-#define SPI_SSINAIEN_MASK (0x002) /*!< Slave Slave Inactive interrupt enable mask \hideinitializer */
-#define SPI_SSACTIEN_MASK (0x004) /*!< Slave Slave Active interrupt enable mask \hideinitializer */
-#define SPI_SLVURIEN_MASK (0x008) /*!< Slave Mode Error 1 interrupt enable mask \hideinitializer */
-#define SPI_SLVBEIEN_MASK (0x010) /*!< Slave Mode Error 0 interrupt enable mask \hideinitializer */
-#define SPI_SLVTOIEN_MASK (0x020) /*!< Slave Mode Time-out interrupt enable mask \hideinitializer */
-#define SPI_FIFO_TXTHIEN_MASK (0x040) /*!< Transmit FIFO Threshold interrupt enable mask \hideinitializer */
-#define SPI_FIFO_RXTHIEN_MASK (0x080) /*!< Receive FIFO Threshold interrupt enable mask \hideinitializer */
-#define SPI_FIFO_RXOVIEN_MASK (0x100) /*!< Receive FIFO Overrun interrupt enable mask \hideinitializer */
-#define SPI_FIFO_TXUFIEN_MASK (0x200) /*!< Slave Transmit Under Run interrupt enable mask \hideinitializer */
-#define SPI_FIFO_RXTOIEN_MASK (0x400) /*!< Slave Receive Time-out interrupt enable mask \hideinitializer */
-
-
-/*@}*/ /* end of group NUC472_442_SPI_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
- @{
-*/
-
-/**
- * @brief Set time out period for slave.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32TimeoutPeriod is the period of time out.
- * @return none
- * \hideinitializer
- */
-#define SPI_SET_SLAVE_TIMEOUT_PERIOD(spi, u32TimeoutPeriod) ( (spi)->SSCTL = ((spi)->SSCTL & ~SPI_SSCTL_SLVTOCNT_Msk) | (u32TimeoutPeriod & 0xFFFF) )
-
-/**
- * @brief Enable time out clear function for FIFO mode.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_TIMEOUT_FIFO_CLEAR(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLVTORST_Msk )
-
-/**
- * @brief Disable time out clear function for FIFO mode.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_TIMEOUT_FIFO_CLEAR(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLVTORST_Msk )
-
-/**
- * @brief Set data out signal to low (0) if transmit under-run occurs.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_SET_TX_UNDERRUN_DATA_LOW(spi) ( (spi)->FIFOCTL &= ~SPI_FIFOCTL_TXUFPOL_Msk )
-
-/**
- * @brief Set data out signal to high (1) if transmit under-run occurs.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_SET_TX_UNDERRUN_DATA_HIGH(spi) ( (spi)->FIFOCTL |= SPI_FIFOCTL_TXUFPOL_Msk )
-
-/**
- * @brief Get the status flags.
- * @param spi is the base address of SPI module.
- * @return status flags
- * \hideinitializer
- */
-#define SPI_GET_STATUS(spi) ( (spi)->STATUS )
-
-/**
- * @brief Clear the unit transfer interrupt flag.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
-
-/**
- * @brief Disable slave 3-wire mode.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk )
-
-/**
- * @brief Enable slave 3-wire mode.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk )
-
-/**
- * @brief Get the count of available data in RX FIFO.
- * @param[in] spi is the base address of SPI module.
- * @return The count of available data in RX FIFO.
- * \hideinitializer
- */
-#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
-
-/**
- * @brief Get the Rx FIFO empty flag.
- * @param[in] spi is the base address of SPI module.
- * @return Rx FIFO flag
- * @retval 0: Rx FIFO is not empty
- * @retval 1: Rx FIFO is empty
- * \hideinitializer
- */
-#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
-
-/**
- * @brief Get the Tx FIFO empty flag.
- * @param[in] spi is the base address of SPI module.
- * @return Tx FIFO flag
- * @retval 0: Tx FIFO is not empty
- * @retval 1: Tx FIFO is empty
- * \hideinitializer
- */
-#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
-
-/**
- * @brief Get the Tx FIFO full flag.
- * @param[in] spi is the base address of SPI module.
- * @return Tx FIFO flag
- * @retval 0: Tx FIFO is not full
- * @retval 1: Tx FIFO is full
- * \hideinitializer
- */
-#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
-
-/**
- * @brief Get the datum read from R0 FIFO.
- * @param[in] spi is the base address of SPI module.
- * @return data in Rx register
- * \hideinitializer
- */
-#define SPI_READ_RX(spi) ((spi)->RX)
-
-/**
- * @brief Write datum to TX register.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
- * @return none
- * \hideinitializer
- */
-#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
-
-/**
- * @brief Disable automatic slave select function and set SPI_SS pin to high state.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-static __INLINE void SPI_SET_SS0_HIGH(SPI_T *spi)
-{
- spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
- spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
- spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS0;
-}
-
-/**
- * @brief Disable automatic slave select function and set SPI_SS pin to low state.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-static __INLINE void SPI_SET_SS0_LOW(SPI_T *spi)
-{
- spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
- spi->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
- spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS0;
-}
-
-/**
- * @brief Disable automatic slave select function and set SPI_SS pin to high state.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-static __INLINE void SPI_SET_SS1_HIGH(SPI_T *spi)
-{
- spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
- spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
- spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS1;
-}
-
-/**
- * @brief Disable automatic slave select function and set SPI_SS pin to low state.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-static __INLINE void SPI_SET_SS1_LOW(SPI_T *spi)
-{
- spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
- spi->SSCTL |= SPI_SSCTL_SSACTPOL_Msk;
- spi->SSCTL = (spi->SSCTL & ~SPI_SSCTL_SS_Msk) | SPI_SS1;
-}
-
-/**
- * @brief Enable byte reorder function.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
-
-/**
- * @brief Disable byte reorder function.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param [in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
-
-/**
- * @brief Set the length of suspend interval.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32SuspCycle decides the length of suspend interval.
- * @return none
- * \hideinitializer
- */
-#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
-
-/**
- * @brief Set the SPI transfer sequence with LSB first.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
-
-/**
- * @brief Set the SPI transfer sequence with MSB first.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
-
-/**
- * @brief Set the data width of a SPI transaction.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @param[in] u32Width data width
- * @return none
- * \hideinitializer
- */
-static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
-{
- if(u32Width == 32)
- u32Width = 0;
-
- spi->CTL = (spi->CTL & ~SPI_CTL_DWIDTH_Msk) | (u32Width << SPI_CTL_DWIDTH_Pos);
-}
-
-/**
- * @brief Get the SPI busy state.
- * @param[in] spi is the base address of SPI module.
- * @return SPI busy status
- * @retval 0: SPI module is not busy
- * @retval 1: SPI module is busy
- * \hideinitializer
- */
-#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) == SPI_STATUS_BUSY_Msk ? 1:0 )
-
-/**
- * @brief Set the SPIEN bit to trigger SPI transfer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
-
-/**
- * @brief Set the SPIEN bit to trigger SPI transfer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
-
-/**
- * @brief Disable SPI function.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )
-
-/**
- * @brief Enable SPI Dual IO function.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_DUAL_MODE(spi) ( (spi)->CTL |= SPI_CTL_DUALIOEN_Msk )
-
-/**
- * @brief Disable SPI Dual IO function.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_DUAL_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk )
-
-/**
- * @brief Set SPI Dual IO direction to input.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QDIODIR_Msk )
-
-/**
- * @brief Set SPI Dual IO direction to output.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk )
-
-/**
- * @brief Enable SPI QUAD IO function.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_QUAD_MODE(spi) ( (spi)->CTL |= SPI_CTL_QUADIOEN_Msk )
-
-/**
- * @brief Disable SPI Dual IO function.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_QUAD_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk )
-
-/**
- * @brief Set SPI Quad IO direction to input.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_QDIODIR_Msk )
-
-/**
- * @brief Set SPI Quad IO direction to output.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ( (spi)->CTL |= SPI_CTL_QDIODIR_Msk )
-
-/**
- * @brief Trigger RX PDMA transfer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
-
-/**
- * @brief Trigger TX PDMA transfer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
-
-/**
- * @brief Trigger TX/RX PDMA transfer at the same time.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_TRIGGER_TXRX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
-
-/**
- * @brief Disable RX PDMA transfer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
-
-/**
- * @brief Trigger TX PDMA transfer.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
-
-/**
- * @brief Enable 2-bit transfer mode.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_ENABLE_2BIT_MODE(spi) ( (spi)->CTL |= SPI_CTL_TWOBIT_Msk )
-
-/**
- * @brief Disable 2-bit transfer mode.
- * @note Before calling this function, SPI must be stopped first. \ref SPI_DISABLE must be called.
- * @param[in] spi is the base address of SPI module.
- * @return none
- * \hideinitializer
- */
-#define SPI_DISABLE_2BIT_MODE(spi) ( (spi)->CTL &= ~SPI_CTL_TWOBIT_Msk )
-
-uint32_t SPI_Open(SPI_T *spi,uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
-void SPI_Close(SPI_T *spi);
-void SPI_ClearRxFIFO(SPI_T *spi);
-void SPI_ClearTxFIFO(SPI_T *spi);
-void SPI_DisableAutoSS(SPI_T *spi);
-void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
-uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
-void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
-uint32_t SPI_GetBusClock(SPI_T *spi);
-void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
-void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
-
-
-/*@}*/ /* end of group NUC472_442_SPI_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SPI_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SPI_H__
-
-/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sys.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,224 +0,0 @@
-/*************************************************************************//**
- * @file sys.c
- * @version V1.00
- * $Revision: 15 $
- * $Date: 14/10/06 1:06p $
- * @brief NUC472/NUC442 SYS driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SYS_Driver SYS Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
- @{
-*/
-
-/**
- * @brief This function clear the selected system reset source
- * @param[in] u32RstSrc is system reset source. Including:
- * - \ref SYS_RSTSTS_PORF_Msk
- * - \ref SYS_RSTSTS_PINRF_Msk
- * - \ref SYS_RSTSTS_WDTRF_Msk
- * - \ref SYS_RSTSTS_LVRF_Msk
- * - \ref SYS_RSTSTS_BODRF_Msk
- * - \ref SYS_RSTSTS_SYSRF_Msk
- * - \ref SYS_RSTSTS_CPURF_Msk
- * @return None
- */
-void SYS_ClearResetSrc(uint32_t u32RstSrc)
-{
- SYS->RSTSTS |= u32RstSrc;
-}
-
-/**
- * @brief This function get Brown-out detector output status
- * @return 0: System voltage is higher than BODVL setting or BODEN is 0.
- * 1: System voltage is lower than BODVL setting.
- * Note : If the BOD_EN is 0, this function always return 0.
- */
-uint32_t SYS_GetBODStatus()
-{
- return (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk);
-}
-
-/**
- * @brief This function get the system reset source register value
- * @return Reset source
- */
-uint32_t SYS_GetResetSrc(void)
-{
- return (SYS->RSTSTS);
-}
-
-/**
- * @brief This function check register write-protection bit setting
- * @return 0: Write-protection function is disabled.
- * 1: Write-protection function is enabled.
- */
-uint32_t SYS_IsRegLocked(void)
-{
- return (SYS->REGLCTL & SYS_REGLCTL_REGLCTL_Msk);
-}
-
-/**
- * @brief This function enable register write-protection function
- * @return None
- * @details To lock the protected register to forbid write access
- */
-void SYS_LockReg(void)
-{
- SYS->REGLCTL = 0;
-}
-
-
-/**
- * @brief This function disable register write-protection function
- * @return None
- * @details To unlock the protected register to allow write access
- */
-void SYS_UnlockReg(void)
-{
- while(SYS->REGLCTL != SYS_REGLCTL_REGLCTL_Msk) {
- SYS->REGLCTL = 0x59;
- SYS->REGLCTL = 0x16;
- SYS->REGLCTL = 0x88;
- }
-}
-
-/**
- * @brief This function get product ID.
- * @return Product ID
- */
-uint32_t SYS_ReadPDID(void)
-{
- return SYS->PDID;
-}
-
-/**
- * @brief This function reset chip.
- * @return None
- */
-void SYS_ResetChip(void)
-{
- SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
-}
-
-/**
- * @brief This function reset CPU.
- * @return None
- */
-void SYS_ResetCPU(void)
-{
- SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
-}
-
-/**
- * @brief This function reset selected modules.
- * @param[in] u32ModuleIndex is module index. Including :
- * - \ref CHIP_RST
- * - \ref CPU_RST
- * - \ref PDMA_RST
- * - \ref EBI_RST
- * - \ref USBH_RST
- * - \ref EMAC_RST
- * - \ref SDH_RST
- * - \ref CRC_RST
- * - \ref CAP_RST
- * - \ref SPACC_RST
- * - \ref GPIO_RST
- * - \ref TMR0_RST
- * - \ref TMR1_RST
- * - \ref TMR2_RST
- * - \ref TMR3_RST
- * - \ref ACMP_RST
- * - \ref I2C0_RST
- * - \ref I2C1_RST
- * - \ref I2C2_RST
- * - \ref I2C3_RST
- * - \ref SPI0_RST
- * - \ref SPI1_RST
- * - \ref SPI2_RST
- * - \ref SPI3_RST
- * - \ref UART0_RST
- * - \ref UART1_RST
- * - \ref UART2_RST
- * - \ref UART3_RST
- * - \ref UART4_RST
- * - \ref UART5_RST
- * - \ref CAN0_RST
- * - \ref CAN1_RST
- * - \ref OTG_RST
- * - \ref USBD_RST
- * - \ref ADC_RST
- * - \ref I2S0_RST
- * - \ref I2S1_RST
- * - \ref PS2_RST
- * - \ref SC0_RST
- * - \ref SC1_RST
- * - \ref SC2_RST
- * - \ref SC3_RST
- * - \ref SC4_RST
- * - \ref SC5_RST
- * - \ref I2C4_RST
- * - \ref PWM0_RST
- * - \ref PWM1_RST
- * - \ref QEI0_RST
- * - \ref QEI1_RST
- * @return None
- */
-void SYS_ResetModule(uint32_t u32ModuleIndex)
-{
- *(volatile uint32_t *)((uint32_t)&(SYS->IPRST0) + (u32ModuleIndex>>24)) |= 1<<(u32ModuleIndex & 0x00ffffff);
- *(volatile uint32_t *)((uint32_t)&(SYS->IPRST0) + (u32ModuleIndex>>24)) &= ~(1<<(u32ModuleIndex & 0x00ffffff));
-}
-
-/**
- * @brief This function configure BOD function.
- * Configure BOD reset or interrupt mode and set Brown-out voltage level.
- * Enable Brown-out function
- * @param[in] i32Mode is reset or interrupt mode. Including :
- * - \ref SYS_BODCTL_BODRSTEN
- * - \ref SYS_BODCTL_BODINTEN
- * @param[in] u32BODLevel is Brown-out voltage level. Including :
- * - \ref SYS_BODCTL_BODVL_2_2V
- * - \ref SYS_BODCTL_BODVL_2_7V
- * - \ref SYS_BODCTL_BODVL_3_8V
- * - \ref SYS_BODCTL_BODVL_4_5V
- *
- * @return None
- */
-void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
-{
- SYS->BODCTL &= ~(SYS_BODCTL_BODVL_Msk|SYS_BODCTL_BODRSTEN_Msk);
- SYS->BODCTL |=(i32Mode|u32BODLevel|SYS_BODCTL_BODEN_Msk);
-}
-
-/**
- * @brief This function disable BOD function.
- * @return None
- */
-void SYS_DisableBOD(void)
-{
- SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
-}
-
-
-
-/*@}*/ /* end of group NUC472_442_SYS_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SYS_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_sys.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1275 +0,0 @@
-/**************************************************************************//**
- * @file SYS.h
- * @version V1.0
- * $Revision 1 $
- * $Date: 15/10/21 1:35p $
- * @brief NUC472/NUC442 SYS Header File
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- ******************************************************************************/
-
-#ifndef __SYS_H__
-#define __SYS_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SYS_Driver SYS Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_SYS_EXPORTED_CONSTANTS SYS Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Module Reset Control Resister constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define PDMA_RST ((0x0<<24)|SYS_IPRST0_PDMARST_Pos) /*!<Reset PDMA \hideinitializer */
-#define EBI_RST ((0x0<<24)|SYS_IPRST0_EBIRST_Pos) /*!<Reset EBI \hideinitializer */
-#define USBH_RST ((0x0<<24)|SYS_IPRST0_USBHRST_Pos) /*!<Reset USBH \hideinitializer */
-#define EMAC_RST ((0x0<<24)|SYS_IPRST0_EMACRST_Pos) /*!<Reset EMAC \hideinitializer */
-#define SDH_RST ((0x0<<24)|SYS_IPRST0_SDHRST_Pos) /*!<Reset SDIO \hideinitializer */
-#define CRC_RST ((0x0<<24)|SYS_IPRST0_CRCRST_Pos) /*!<Reset CRC \hideinitializer */
-#define CAP_RST ((0x0<<24)|SYS_IPRST0_CAPRST_Pos) /*!<Reset CAP \hideinitializer */
-#define CRYPTO_RST ((0x0<<24)|SYS_IPRST0_CRYPTORST_Pos) /*!<Reset CRYPTO \hideinitializer */
-#define GPIO_RST ((0x4<<24)|SYS_IPRST1_GPIORST_Pos) /*!<Reset GPIO \hideinitializer */
-#define TMR0_RST ((0x4<<24)|SYS_IPRST1_TMR0RST_Pos) /*!<Reset TMR0 \hideinitializer */
-#define TMR1_RST ((0x4<<24)|SYS_IPRST1_TMR1RST_Pos) /*!<Reset TMR1 \hideinitializer */
-#define TMR2_RST ((0x4<<24)|SYS_IPRST1_TMR2RST_Pos) /*!<Reset TMR2 \hideinitializer */
-#define TMR3_RST ((0x4<<24)|SYS_IPRST1_TMR3RST_Pos) /*!<Reset TMR3 \hideinitializer */
-#define ACMP_RST ((0x4<<24)|SYS_IPRST1_ACMPRST_Pos) /*!<Reset ACMP \hideinitializer */
-#define I2C0_RST ((0x4<<24)|SYS_IPRST1_I2C0RST_Pos) /*!<Reset I2C0 \hideinitializer */
-#define I2C1_RST ((0x4<<24)|SYS_IPRST1_I2C1RST_Pos) /*!<Reset I2C1 \hideinitializer */
-#define I2C2_RST ((0x4<<24)|SYS_IPRST1_I2C2RST_Pos) /*!<Reset I2C2 \hideinitializer */
-#define I2C3_RST ((0x4<<24)|SYS_IPRST1_I2C3RST_Pos) /*!<Reset I2C3 \hideinitializer */
-#define SPI0_RST ((0x4<<24)|SYS_IPRST1_SPI0RST_Pos) /*!<Reset SPI0 \hideinitializer */
-#define SPI1_RST ((0x4<<24)|SYS_IPRST1_SPI1RST_Pos) /*!<Reset SPI1 \hideinitializer */
-#define SPI2_RST ((0x4<<24)|SYS_IPRST1_SPI2RST_Pos) /*!<Reset SPI2 \hideinitializer */
-#define SPI3_RST ((0x4<<24)|SYS_IPRST1_SPI3RST_Pos) /*!<Reset SPI3 \hideinitializer */
-#define UART0_RST ((0x4<<24)|SYS_IPRST1_UART0RST_Pos) /*!<Reset UART0 \hideinitializer */
-#define UART1_RST ((0x4<<24)|SYS_IPRST1_UART1RST_Pos) /*!<Reset UART1 \hideinitializer */
-#define UART2_RST ((0x4<<24)|SYS_IPRST1_UART2RST_Pos) /*!<Reset UART2 \hideinitializer */
-#define UART3_RST ((0x4<<24)|SYS_IPRST1_UART3RST_Pos) /*!<Reset UART3 \hideinitializer */
-#define UART4_RST ((0x4<<24)|SYS_IPRST1_UART4RST_Pos) /*!<Reset UART4 \hideinitializer */
-#define UART5_RST ((0x4<<24)|SYS_IPRST1_UART5RST_Pos) /*!<Reset UART5 \hideinitializer */
-#define CAN0_RST ((0x4<<24)|SYS_IPRST1_CAN0RST_Pos) /*!<Reset CAN0 \hideinitializer */
-#define CAN1_RST ((0x4<<24)|SYS_IPRST1_CAN1RST_Pos) /*!<Reset CAN1 \hideinitializer */
-#define OTG_RST ((0x4<<24)|SYS_IPRST1_OTGRST_Pos) /*!<Reset OTG \hideinitializer */
-#define USBD_RST ((0x4<<24)|SYS_IPRST1_USBDRST_Pos) /*!<Reset USBD \hideinitializer */
-#define ADC_RST ((0x4<<24)|SYS_IPRST1_ADCRST_Pos) /*!<Reset ADC \hideinitializer */
-#define I2S0_RST ((0x4<<24)|SYS_IPRST1_I2S0RST_Pos) /*!<Reset I2S0 \hideinitializer */
-#define I2S1_RST ((0x4<<24)|SYS_IPRST1_I2S1RST_Pos) /*!<Reset I2S1 \hideinitializer */
-#define PS2_RST ((0x4<<24)|SYS_IPRST1_PS2RST_Pos) /*!<Reset PS2 \hideinitializer */
-#define SC0_RST ((0x8<<24)|SYS_IPRST2_SC0RST_Pos) /*!<Reset SC0 \hideinitializer */
-#define SC1_RST ((0x8<<24)|SYS_IPRST2_SC1RST_Pos) /*!<Reset SC1 \hideinitializer */
-#define SC2_RST ((0x8<<24)|SYS_IPRST2_SC2RST_Pos) /*!<Reset SC2 \hideinitializer */
-#define SC3_RST ((0x8<<24)|SYS_IPRST2_SC3RST_Pos) /*!<Reset SC3 \hideinitializer */
-#define SC4_RST ((0x8<<24)|SYS_IPRST2_SC4RST_Pos) /*!<Reset SC4 \hideinitializer */
-#define SC5_RST ((0x8<<24)|SYS_IPRST2_SC5RST_Pos) /*!<Reset SC5 \hideinitializer */
-#define I2C4_RST ((0x8<<24)|SYS_IPRST2_I2C4RST_Pos) /*!<Reset I2C4 \hideinitializer */
-#define PWM0_RST ((0x8<<24)|SYS_IPRST2_PWM0RST_Pos) /*!<Reset PWM0 \hideinitializer */
-#define PWM1_RST ((0x8<<24)|SYS_IPRST2_PWM1RST_Pos) /*!<Reset PWM1 \hideinitializer */
-#define QEI0_RST ((0x8<<24)|SYS_IPRST2_QEI0RST_Pos) /*!<Reset QEI0 \hideinitializer */
-#define QEI1_RST ((0x8<<24)|SYS_IPRST2_QEI1RST_Pos) /*!<Reset QEI1 \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* BODCTL constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-#define SYS_BODCTL_BODVL_2_2V (0x0UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 2.2V \hideinitializer */
-#define SYS_BODCTL_BODVL_2_7V (0x1UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 2.7V \hideinitializer */
-#define SYS_BODCTL_BODVL_3_8V (0x2UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 3.82V \hideinitializer */
-#define SYS_BODCTL_BODVL_4_5V (0x3UL<<SYS_BODCTL_BODVL_Pos) /*!<Threshold voltage of BOD is selected 4.5V \hideinitializer */
-#define SYS_BODCTL_BODRSTEN (0x1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!<Enable reset function of BOD. \hideinitializer */
-#define SYS_BODCTL_BODINTEN (0x0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!<Enable interrupt function of BOD. \hideinitializer */
-#define SYS_BODCTL_BODLPM (0x1UL<<SYS_BODCTL_BODLPM_Pos) /*!<BOD work in low power mode. \hideinitializer */
-#define SYS_BODCTL_BODOUT (0x1UL<<SYS_BODCTL_BODOUT_Pos) /*!<Output of BOD IP. \hideinitializer */
-#define SYS_BODCTL_LVREN (0x1UL<<SYS_BODCTL_LVREN_Pos) /*!<Enable LVR function. \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* VREFCTL constant definitions. (Write-Protection Register) */
-/*---------------------------------------------------------------------------------------------------------*/
-#define SYS_VREFCTL_VREF_2_65V (0x03UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 2.56V \hideinitializer */
-#define SYS_VREFCTL_VREF_2_048V (0x07UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 2.048V \hideinitializer */
-#define SYS_VREFCTL_VREF_3_072V (0x0BUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 3.072V \hideinitializer */
-#define SYS_VREFCTL_VREF_4_096V (0x0FUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= 4.096V \hideinitializer */
-#define SYS_VREFCTL_VREF_AVDD (0x10UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< VOUT= AVDD \hideinitializer */
-#define SYS_VREFCTL_ADCMODESEL_EADC (0x1UL<<SYS_VREFCTL_ADCMODESEL_Pos) /*!< EADC mode \hideinitializer */
-#define SYS_VREFCTL_ADCMODESEL_ADC (0x0UL<<SYS_VREFCTL_ADCMODESEL_Pos) /*!< ADC mode \hideinitializer */
-#define SYS_VREFCTL_PWMSYNCMODE_EN (0x1UL<<SYS_VREFCTL_PWMSYNCMODE_Pos)/*!<PWM SYNC MODE ENABLED, PWM engine clock is same as HCLK \hideinitializer */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* USBROLE constant definitions. (Write-Protection Register) */
-/*---------------------------------------------------------------------------------------------------------*/
-#define SYS_USBPHY_USBROLE_OTG_V33_EN (0x1UL<<SYS_USBPHY_LDO33EN_Pos) /*!< USB LDO33 Enabled \hideinitializer */
-#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device \hideinitializer */
-#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host \hideinitializer */
-#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device \hideinitializer */
-#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device \hideinitializer */
-
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Multi-Function constant definitions. */
-/*---------------------------------------------------------------------------------------------------------*/
-/* How to use below #define?
-Example 1: If user want to set PA.0 as SC0_CD in initial function,
- user can issue following command to achieve it.
-
- SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ;
-
-*/
-//GPA_MFPL_PA0MFP
-#define SYS_GPA_MFPL_PA0MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA0MFP_TAMPER0 (0x1UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for TAMPER0 \hideinitializer */
-#define SYS_GPA_MFPL_PA0MFP_SC0_CD (0x2UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CD \hideinitializer */
-#define SYS_GPA_MFPL_PA0MFP_CAN1_RXD (0x3UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for CAN1_RXD \hideinitializer */
-#define SYS_GPA_MFPL_PA0MFP_INT0 (0x8UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for INT0 \hideinitializer */
-
-//GPA_MFPL_PA1MFP
-#define SYS_GPA_MFPL_PA1MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA1MFP_TAMPER1 (0x1UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for TAMPER1 \hideinitializer */
-#define SYS_GPA_MFPL_PA1MFP_SC5_CD (0x2UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC5_CD \hideinitializer */
-#define SYS_GPA_MFPL_PA1MFP_CAN1_TXD (0x3UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for CAN1_TXD \hideinitializer */
-#define SYS_GPA_MFPL_PA1MFP_EBI_A22 (0x7UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EBI_A22 \hideinitializer */
-
-//GPA_MFPL_PA2MFP
-#define SYS_GPA_MFPL_PA2MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA2MFP_SC2_DAT (0x1UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC2_DAT \hideinitializer */
-#define SYS_GPA_MFPL_PA2MFP_SPI3_MISO0 (0x2UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SPI3_MISO0 \hideinitializer */
-#define SYS_GPA_MFPL_PA2MFP_I2S0_MCLK (0x3UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2S0_MCLK \hideinitializer */
-#define SYS_GPA_MFPL_PA2MFP_BRAKE11 (0x4UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for BRAKE11 \hideinitializer */
-#define SYS_GPA_MFPL_PA2MFP_CAP_SFIELD (0x5UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for CAP_SFIELD \hideinitializer */
-#define SYS_GPA_MFPL_PA2MFP_EBI_A12 (0x7UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EBI_A12 \hideinitializer */
-
-//GPA_MFPL_PA3MFP
-#define SYS_GPA_MFPL_PA3MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA3MFP_SC2_CLK (0x1UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC2_CLK \hideinitializer */
-#define SYS_GPA_MFPL_PA3MFP_SPI3_MOSI0 (0x2UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SPI3_MOSI0 \hideinitializer */
-#define SYS_GPA_MFPL_PA3MFP_I2S0_DO (0x3UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2S0_D0 \hideinitializer */
-#define SYS_GPA_MFPL_PA3MFP_BRAKE10 (0x4UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for BRAKE10 \hideinitializer */
-#define SYS_GPA_MFPL_PA3MFP_EBI_A13 (0x7UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EBI_A13 \hideinitializer */
-
-//GPA_MFPL_PA4MFP
-#define SYS_GPA_MFPL_PA4MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA4MFP_SC2_PWR (0x1UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SC2_PWR \hideinitializer */
-#define SYS_GPA_MFPL_PA4MFP_SPI3_CLK (0x2UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI3_CLK \hideinitializer */
-#define SYS_GPA_MFPL_PA4MFP_I2S0_DI (0x3UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for I2S0_DI \hideinitializer */
-#define SYS_GPA_MFPL_PA4MFP_QEI1_Z (0x5UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QEI1_Z \hideinitializer */
-#define SYS_GPA_MFPL_PA4MFP_EBI_A14 (0x7UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EBI_A14 \hideinitializer */
-#define SYS_GPA_MFPL_PA4MFP_ECAP1_IC2 (0x8UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for ECAP1_IC2 \hideinitializer */
-
-//GPA_MFPL_PA5MFP
-#define SYS_GPA_MFPL_PA5MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_SC2_RST (0x1UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SC2_RST \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_SPI3_SS0 (0x2UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI3_SS0 \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_I2S0_BCLK (0x3UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for I2S0_BCLK \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_PWM0_CH0 (0x4UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for PWM0 CH0 \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_QEI1_B (0x5UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QEI1_B \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_EBI_A15 (0x7UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EBI_A15 \hideinitializer */
-#define SYS_GPA_MFPL_PA5MFP_ECAP1_IC1 (0x8UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for ECAP1_IC1 \hideinitializer */
-
-//GPA_MFPL_PA6MFP
-#define SYS_GPA_MFPL_PA6MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA6MFP_SC2_CD (0x1UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SC2_CD \hideinitializer */
-#define SYS_GPA_MFPL_PA6MFP_I2S0_LRCK (0x3UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for I2S0_LRCK \hideinitializer */
-#define SYS_GPA_MFPL_PA6MFP_PWM0_CH1 (0x4UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for PWM1 CH1 \hideinitializer */
-#define SYS_GPA_MFPL_PA6MFP_QEI1_A (0x5UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for QEI1_A \hideinitializer */
-#define SYS_GPA_MFPL_PA6MFP_CAN1_TXD (0x6UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for CAN1_TXD \hideinitializer */
-#define SYS_GPA_MFPL_PA6MFP_EBI_A16 (0x7UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_A16 \hideinitializer */
-#define SYS_GPA_MFPL_PA6MFP_ECAP1_IC0 (0x8UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for ECAP1_IC0 \hideinitializer */
-
-//GPA_MFPL_PA7MFP
-#define SYS_GPA_MFPL_PA7MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPL_PA7MFP_SC0_CLK (0x2UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SC0_CLK \hideinitializer */
-#define SYS_GPA_MFPL_PA7MFP_SPI3_SS0 (0x3UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI3_SS0 \hideinitializer */
-#define SYS_GPA_MFPL_PA7MFP_PWM1_CH3 (0x4UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for PWM1 CH3 \hideinitializer */
-#define SYS_GPA_MFPL_PA7MFP_EPWM0_CH5 (0x5UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EPWM0 CH5 \hideinitializer */
-#define SYS_GPA_MFPL_PA7MFP_EBI_A17 (0x7UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_A17 \hideinitializer */
-
-//GPA_MFPL_PA8MFP
-#define SYS_GPA_MFPH_PA8MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA8MFP_SC0_RST (0x2UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SC0_RST \hideinitializer */
-#define SYS_GPA_MFPH_PA8MFP_SPI3_CLK (0x3UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SPI3_CLK \hideinitializer */
-#define SYS_GPA_MFPH_PA8MFP_PWM1_CH2 (0x4UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for PWM1 CH2 \hideinitializer */
-#define SYS_GPA_MFPH_PA8MFP_EPWM0_CH4 (0x5UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EPWM0_CH4 \hideinitializer */
-#define SYS_GPA_MFPH_PA8MFP_EBI_A18 (0x7UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EBI_A18 \hideinitializer */
-
-//GPA_MFPH_PA9MFP
-#define SYS_GPA_MFPH_PA9MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA9MFP_SC0_PWR (0x2UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SC0_PWR \hideinitializer */
-#define SYS_GPA_MFPH_PA9MFP_SPI3_MISO0 (0x3UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SPI3_MISO0 \hideinitializer */
-#define SYS_GPA_MFPH_PA9MFP_PWM1_CH1 (0x4UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for PWM1 CH1 \hideinitializer */
-#define SYS_GPA_MFPH_PA9MFP_EPWM0_CH3 (0x5UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EPWM0 CH3 \hideinitializer */
-#define SYS_GPA_MFPH_PA9MFP_EBI_A19 (0x7UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EBI_A19 \hideinitializer */
-
-//GPA_MFPH_PA10MFP
-#define SYS_GPA_MFPH_PA10MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA10MFP_SC0_DAT (0x2UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for SC0_DAT \hideinitializer */
-#define SYS_GPA_MFPH_PA10MFP_SPI3_MOSI0 (0x3UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for SPI3_MOSI0 \hideinitializer */
-#define SYS_GPA_MFPH_PA10MFP_PWM1_CH0 (0x4UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for PWM1_CH0 \hideinitializer */
-#define SYS_GPA_MFPH_PA10MFP_EPWM0_CH2 (0x5UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for EPWM0_CH2 \hideinitializer */
-#define SYS_GPA_MFPH_PA10MFP_EBI_A20 (0x7UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for EBI_A20 \hideinitializer */
-
-//GPA_MFPH_PA11MFP
-#define SYS_GPA_MFPH_PA11MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA11MFP_UART0_RTS (0x1UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for UART0_RTS \hideinitializer */
-#define SYS_GPA_MFPH_PA11MFP_SPI3_MISO1 (0x3UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for SPI3_MISO1 \hideinitializer */
-#define SYS_GPA_MFPH_PA11MFP_PWM0_CH5 (0x4UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for PWM0_CH5 \hideinitializer */
-#define SYS_GPA_MFPH_PA11MFP_EPWM0_CH1 (0x5UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for EPWM0_CH1 \hideinitializer */
-#define SYS_GPA_MFPH_PA11MFP_EBI_AD0 (0x7UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for EBI_AD0 \hideinitializer */
-
-//GPA_MFPH_PA12MFP
-#define SYS_GPA_MFPH_PA12MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA12MFP_UART0_CTS (0x1UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for UART0_CTS \hideinitializer */
-#define SYS_GPA_MFPH_PA12MFP_SPI3_MOSI1 (0x3UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SPI3_MOSI1 \hideinitializer */
-#define SYS_GPA_MFPH_PA12MFP_PWM0_CH4 (0x4UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for PWM0_CH4 \hideinitializer */
-#define SYS_GPA_MFPH_PA12MFP_EPWM0_CH0 (0x5UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for EPWM0_CH0 \hideinitializer */
-#define SYS_GPA_MFPH_PA12MFP_EBI_AD1 (0x7UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for EBI_AD1 \hideinitializer */
-
-//GPA_MFPH_PA13MFP
-#define SYS_GPA_MFPH_PA13MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA13MFP_UART0_RXD (0x1UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for UART0_RXD \hideinitializer */
-#define SYS_GPA_MFPH_PA13MFP_SC3_DAT (0x3UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for SC3_DAT \hideinitializer */
-#define SYS_GPA_MFPH_PA13MFP_PWM1_CH4 (0x4UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for PWM1_CH4 \hideinitializer */
-#define SYS_GPA_MFPH_PA13MFP_EBI_AD2 (0x7UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for EBI_AD2 \hideinitializer */
-
-//GPA_MFPH_PA14MFP
-#define SYS_GPA_MFPH_PA14MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x1UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for UART0_TXD \hideinitializer */
-#define SYS_GPA_MFPH_PA14MFP_SC3_CLK (0x3UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for SC3_CLK \hideinitializer */
-#define SYS_GPA_MFPH_PA14MFP_PWM1_CH5 (0x4UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for PWM1_CH5 \hideinitializer */
-#define SYS_GPA_MFPH_PA14MFP_EBI_AD3 (0x7UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for EBI_AD3 \hideinitializer */
-//GPA_MFPH_PA15MFP
-#define SYS_GPA_MFPH_PA15MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for GPIO \hideinitializer */
-#define SYS_GPA_MFPH_PA15MFP_SC3_PWR (0x1UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for SC3_PWR \hideinitializer */
-#define SYS_GPA_MFPH_PA15MFP_UART2_RTS (0x2UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for UART2_RTS \hideinitializer */
-#define SYS_GPA_MFPH_PA15MFP_I2C0_SCL (0x4UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2C0_SCL \hideinitializer */
-#define SYS_GPA_MFPH_PA15MFP_EBI_A21 (0x7UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for EBI_A21 \hideinitializer */
-
-
-//GPB_MFPL_PB0MFP
-#define SYS_GPB_MFPL_PB0MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB0MFP_USB0_OTG5V_ST (0x1UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for USB0_OTG5V_ST \hideinitializer */
-#define SYS_GPB_MFPL_PB0MFP_I2C4_SCL (0x2UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C4_SCL \hideinitializer */
-#define SYS_GPB_MFPL_PB0MFP_INT1 (0x8UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for INT1 \hideinitializer */
-
-//GPB_MFPL_PB1MFP
-#define SYS_GPB_MFPL_PB1MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB1MFP_USB0_OTG5V_EN (0x1UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for USB0_OTG5V_EN \hideinitializer */
-#define SYS_GPB_MFPL_PB1MFP_I2C4_SDA (0x2UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2C4_SDA \hideinitializer */
-#define SYS_GPB_MFPL_PB1MFP_TM1_CNT_OUT (0x3UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for TM1_CNT_OUT \hideinitializer */
-
-//GPB_MFPL_PB2MFP
-#define SYS_GPB_MFPL_PB2MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x1UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD \hideinitializer */
-#define SYS_GPB_MFPL_PB2MFP_SPI2_SS0 (0x2UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI2_SS0 \hideinitializer */
-#define SYS_GPB_MFPL_PB2MFP_USB1_D_N (0x3UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for USB1_D_N \hideinitializer */
-#define SYS_GPB_MFPL_PB2MFP_EBI_AD4 (0x7UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EBI_AD4 \hideinitializer */
-
-//GPB_MFPL_PB3MFP
-#define SYS_GPB_MFPL_PB3MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x1UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD \hideinitializer */
-#define SYS_GPB_MFPL_PB3MFP_SPI2_CLK (0x2UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI2_CLK \hideinitializer */
-#define SYS_GPB_MFPL_PB3MFP_USB1_D_P (0x3UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for USB1_D_P \hideinitializer */
-#define SYS_GPB_MFPL_PB3MFP_EBI_AD5 (0x7UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EBI_AD5 \hideinitializer */
-
-//GPB_MFPL_PB4MFP
-#define SYS_GPB_MFPL_PB4MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB4MFP_UART1_RTS (0x1UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART1_RTS \hideinitializer */
-#define SYS_GPB_MFPL_PB4MFP_SPI2_MISO0 (0x2UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI2_MISO0 \hideinitializer */
-#define SYS_GPB_MFPL_PB4MFP_UART4_RXD (0x3UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART4_RXD \hideinitializer */
-#define SYS_GPB_MFPL_PB4MFP_TM0_CNT_OUT (0x4UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for TM0_CNT_OUT \hideinitializer */
-#define SYS_GPB_MFPL_PB4MFP_EBI_AD6 (0x7UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_AD6 \hideinitializer */
-
-//GPB_MFPL_PB5MFP
-#define SYS_GPB_MFPL_PB5MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB5MFP_UART1_CTS (0x1UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART1_CTS \hideinitializer */
-#define SYS_GPB_MFPL_PB5MFP_SPI2_MOSI0 (0x2UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI2_MOSI0 \hideinitializer */
-#define SYS_GPB_MFPL_PB5MFP_UART4_TXD (0x3UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART4_TXD \hideinitializer */
-#define SYS_GPB_MFPL_PB5MFP_EBI_AD7 (0x7UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_AD7 \hideinitializer */
-
-//GPB_MFPL_PB6MFP
-#define SYS_GPB_MFPL_PB6MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB6MFP_I2C2_SCL (0x1UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for I2C2_SCL \hideinitializer */
-#define SYS_GPB_MFPL_PB6MFP_BRAKE01 (0x2UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for BRAKE01 \hideinitializer */
-#define SYS_GPB_MFPL_PB6MFP_UART4_RTS (0x3UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for UART4_RTS \hideinitializer */
-#define SYS_GPB_MFPL_PB6MFP_PWM1_CH4 (0x4UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for PWM1_CH4 \hideinitializer */
-#define SYS_GPB_MFPL_PB6MFP_EPWM1_CH0 (0x5UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_CH0 \hideinitializer */
-#define SYS_GPB_MFPL_PB6MFP_EBI_AD8 (0x7UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_AD8 \hideinitializer */
-
-//GPB_MFPL_PB7MFP
-#define SYS_GPB_MFPL_PB7MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPL_PB7MFP_I2C2_SDA (0x1UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for I2C2_SDA \hideinitializer */
-#define SYS_GPB_MFPL_PB7MFP_BRAKE00 (0x2UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for BRAKE00 \hideinitializer */
-#define SYS_GPB_MFPL_PB7MFP_UART4_CTS (0x3UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for UART4_CTS \hideinitializer */
-#define SYS_GPB_MFPL_PB7MFP_PWM1_CH5 (0x4UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for PWM1_CH5 \hideinitializer */
-#define SYS_GPB_MFPL_PB7MFP_EPWM1_CH1 (0x5UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_CH1 \hideinitializer */
-#define SYS_GPB_MFPL_PB7MFP_ETM_TRACE_DATA3 (0x6UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ETM_TRACE_DATA3 \hideinitializer */
-#define SYS_GPB_MFPL_PB7MFP_EBI_AD9 (0x7UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_AD9 \hideinitializer */
-
-//GPB_MFPL_PB8MFP
-#define SYS_GPB_MFPH_PB8MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB8MFP_UART5_CTS (0x1UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART5_CTS \hideinitializer */
-#define SYS_GPB_MFPH_PB8MFP_EPWM1_CH2 (0x5UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EPWM1_CH2 \hideinitializer */
-#define SYS_GPB_MFPH_PB8MFP_ETM_TRACE_DATA2 (0x6UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for ETM_TRACE_DATA2 \hideinitializer */
-#define SYS_GPB_MFPH_PB8MFP_EBI_AD10 (0x7UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EBI_AD10 \hideinitializer */
-
-//GPB_MFPH_PB9MFP
-#define SYS_GPB_MFPH_PB9MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB9MFP_UART5_RTS (0x1UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART5_RTS \hideinitializer */
-#define SYS_GPB_MFPH_PB9MFP_EPWM1_CH3 (0x5UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EPWM1_CH3 \hideinitializer */
-#define SYS_GPB_MFPH_PB9MFP_ETM_TRACE_DATA1 (0x6UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for ETM_TRACE_DATA1 \hideinitializer */
-#define SYS_GPB_MFPH_PB9MFP_EBI_AD11 (0x7UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EBI_AD11 \hideinitializer */
-
-//GPB_MFPH_PB10MFP
-#define SYS_GPB_MFPH_PB10MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB10MFP_UART5_TXD (0x1UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for UART5_TXD \hideinitializer */
-#define SYS_GPB_MFPH_PB10MFP_EPWM1_CH4 (0x5UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for EPWM1_CH4 \hideinitializer */
-#define SYS_GPB_MFPH_PB10MFP_ETM_TRACE_DATA0 (0x6UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for ETM_TRACE_DATA0 \hideinitializer */
-#define SYS_GPB_MFPH_PB10MFP_EBI_AD12 (0x7UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for EBI_AD12 \hideinitializer */
-
-//GPB_MFPH_PB11MFP
-#define SYS_GPB_MFPH_PB11MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB11MFP_UART5_RXD (0x1UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for UART5_RXD \hideinitializer */
-#define SYS_GPB_MFPH_PB11MFP_EPWM1_CH5 (0x5UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for EPWM1_CH5 \hideinitializer */
-#define SYS_GPB_MFPH_PB11MFP_ETM_TRACE_CLK (0x6UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for ETM_TRACE_CLK \hideinitializer */
-#define SYS_GPB_MFPH_PB11MFP_EBI_AD13 (0x7UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for EBI_AD13 \hideinitializer */
-
-//GPB_MFPH_PB12MFP
-#define SYS_GPB_MFPH_PB12MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB12MFP_UART4_RTS (0x1UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for UART4_RTS \hideinitializer */
-#define SYS_GPB_MFPH_PB12MFP_SPI2_MISO1 (0x2UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for _SPI2_MISO1 \hideinitializer */
-#define SYS_GPB_MFPH_PB12MFP_CAN0_RXD (0x3UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for CAN0_RXD \hideinitializer */
-#define SYS_GPB_MFPH_PB12MFP_EMAC_MII_MDC (0x6UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for EMAC_MII_MDC \hideinitializer */
-#define SYS_GPB_MFPH_PB12MFP_EBI_AD14 (0x7UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for EBI_AD4 \hideinitializer */
-
-//GPB_MFPH_PB13MFP
-#define SYS_GPB_MFPH_PB13MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB13MFP_UART4_CTS (0x1UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for UART4_CTS \hideinitializer */
-#define SYS_GPB_MFPH_PB13MFP_SPI2_MOSI1 (0x2UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for SPI2_MOSI1 \hideinitializer */
-#define SYS_GPB_MFPH_PB13MFP_CAN0_TXD (0x3UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for CAN0_TXD \hideinitializer */
-#define SYS_GPB_MFPH_PB13MFP_EMAC_MII_MDIO (0x6UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EMAC_MII_MDIO \hideinitializer */
-#define SYS_GPB_MFPH_PB13MFP_EBI_AD15 (0x7UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EBI_AD15 \hideinitializer */
-
-//GPB_MFPH_PB14MFP
-#define SYS_GPB_MFPH_PB14MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB14MFP_I2S1_MCLK (0x1UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for I2S1_MCLK \hideinitializer */
-#define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x2UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for SC1_RST \hideinitializer */
-#define SYS_GPB_MFPH_PB14MFP_BRAKE01 (0x4UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for BRAKE01 \hideinitializer */
-#define SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC (0x6UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EMAC_MII_MDC \hideinitializer */
-
-//GPB_MFPH_PB15MFP
-#define SYS_GPB_MFPH_PB15MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for GPIO \hideinitializer */
-#define SYS_GPB_MFPH_PB15MFP_I2S1_DO (0x1UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for I2S1_DO \hideinitializer */
-#define SYS_GPB_MFPH_PB15MFP_SC1_DAT (0x2UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for SC1_DAT \hideinitializer */
-#define SYS_GPB_MFPH_PB15MFP_BRAKE00 (0x4UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for BRAKE00 \hideinitializer */
-#define SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO (0x6UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPA_MFPH PB15 setting for EMAC_MII_MDIO \hideinitializer */
-
-
-//GPC_MFPL_PC0MFP
-#define SYS_GPC_MFPL_PC0MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC0MFP_I2S1_DI (0x1UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2S1_D1 \hideinitializer */
-#define SYS_GPC_MFPL_PC0MFP_SC1_DAT (0x2UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SC1_DAT \hideinitializer */
-#define SYS_GPC_MFPL_PC0MFP_UART4_RXD (0x3UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART4_RXD \hideinitializer */
-#define SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK (0x6UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EMAC_REFCLK \hideinitializer */
-#define SYS_GPC_MFPL_PC0MFP_EBI_MCLK (0x7UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_MCLK \hideinitializer */
-#define SYS_GPC_MFPL_PC0MFP_INT2 (0x8UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for INT2 \hideinitializer */
-
-
-//GPC_MFPL_PC1MFP
-#define SYS_GPC_MFPL_PC1MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC1MFP_I2S1_BCLK (0x1UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2S1_BCLK \hideinitializer */
-#define SYS_GPC_MFPL_PC1MFP_SC1_CLK (0x2UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SC1_CLK \hideinitializer */
-#define SYS_GPC_MFPL_PC1MFP_UART4_TXD (0x3UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART4_TXD \hideinitializer */
-#define SYS_GPC_MFPL_PC1MFP_TM3_CNT_OUT (0x5UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for TM3_CNT_OUT \hideinitializer */
-#define SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR (0x6UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EMAC_MII_RXERR \hideinitializer */
-#define SYS_GPC_MFPL_PC1MFP_EBI_AD13 (0x7UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD13 \hideinitializer */
-
-//GPC_MFPL_PC2MFP
-#define SYS_GPC_MFPL_PC2MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC2MFP_I2S1_LRCK (0x1UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2S1_LRCK \hideinitializer */
-#define SYS_GPC_MFPL_PC2MFP_SC1_PWR (0x2UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SC1_PWR \hideinitializer */
-#define SYS_GPC_MFPL_PC2MFP_UART4_RTS (0x3UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART4_RTS \hideinitializer */
-#define SYS_GPC_MFPL_PC2MFP_SPI0_SS0 (0x4UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI0_SS0 \hideinitializer */
-#define SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV (0x6UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EMAC_MII_RXDV \hideinitializer */
-#define SYS_GPC_MFPL_PC2MFP_EBI_AD12 (0x7UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD12 \hideinitializer */
-
-//GPC_MFPL_PC3MFP
-#define SYS_GPC_MFPL_PC3MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_I2S1_MCLK (0x1UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2S1_MCLK \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_SC1_CD (0x2UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SC1_CD \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_UART4_CTS (0x3UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART4_CTS \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_SPI0_MISO1 (0x4UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI0_MISO1 \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_QEI0_Z (0x5UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for QEI0_Z \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 (0x6UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EMAC_MII_RXD1 \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_EBI_AD11 (0x7UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD11 \hideinitializer */
-#define SYS_GPC_MFPL_PC3MFP_ECAP0_IC2 (0x8UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for ECAP0_IC2 \hideinitializer */
-
-//GPC_MFPL_PC4MFP
-#define SYS_GPC_MFPL_PC4MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_I2S1_DO (0x1UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2S1_DO \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_SC1_RST (0x2UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SC1_RST \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_SPI0_MOSI1 (0x4UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI0_MOSI1 \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_QEI0_B (0x5UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for QEI0_B \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 (0x6UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EMAC_MII_RXD0 \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_EBI_AD10 (0x7UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD10 \hideinitializer */
-#define SYS_GPC_MFPL_PC4MFP_ECAP0_IC1 (0x8UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for ECAP0_IC1 \hideinitializer */
-
-//GPC_MFPL_PC5MFP
-#define SYS_GPC_MFPL_PC5MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC5MFP_CLK_O (0x1UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for CLK_O \hideinitializer */
-#define SYS_GPC_MFPL_PC5MFP_QEI0_A (0x5UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for QEI0_A \hideinitializer */
-#define SYS_GPC_MFPL_PC5MFP_EMAC_MII_RXCLK (0x6UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EMAC_MII_RXCLK \hideinitializer */
-#define SYS_GPC_MFPL_PC5MFP_EBI_MCLK (0x7UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_MCLK \hideinitializer */
-#define SYS_GPC_MFPL_PC5MFP_ECAP0_IC0 (0x8UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for ECAP0_IC0 \hideinitializer */
-
-//GPC_MFPL_PC6MFP
-#define SYS_GPC_MFPL_PC6MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC6MFP_TM2_EXT (0x1UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM2_EXT \hideinitializer */
-#define SYS_GPC_MFPL_PC6MFP_SPI0_MISO0 (0x4UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SPI0_MISO0 \hideinitializer */
-#define SYS_GPC_MFPL_PC6MFP_TM2_CNT_OUT (0x5UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM2_CNT_OUT \hideinitializer */
-#define SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 (0x6UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EMAC_MII_TXD0 \hideinitializer */
-#define SYS_GPC_MFPL_PC6MFP_EBI_AD9 (0x7UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD9 \hideinitializer */
-
-//GPC_MFPL_PC7MFP
-#define SYS_GPC_MFPL_PC7MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPL_PC7MFP_TM1_EXT (0x1UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for TM1_EXT \hideinitializer */
-#define SYS_GPC_MFPL_PC7MFP_SPI0_MOSI0 (0x4UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SPI0_MOSI0 \hideinitializer */
-#define SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1 (0x6UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EMAC_MII_TXD1 \hideinitializer */
-#define SYS_GPC_MFPL_PC7MFP_EBI_AD8 (0x7UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD8 \hideinitializer */
-
-//GPC_MFPL_PC8MFP
-#define SYS_GPC_MFPH_PC8MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC8MFP_TM0_EXT (0x1UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for TM0_EXT \hideinitializer */
-#define SYS_GPC_MFPH_PC8MFP_SPI0_CLK (0x4UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for SPI0_CLK \hideinitializer */
-#define SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN (0x6UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EMAC_MII_TXEN \hideinitializer */
-
-//GPC_MFPH_PC9MFP
-#define SYS_GPC_MFPH_PC9MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_STADC (0x1UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for STADC \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_UART2_CTS (0x2UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for UART2_CTS \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_SC3_RST (0x3UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SC3_RST \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_I2C0_SDA (0x4UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for I2C0_SDA \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_CAP_DATA1 (0x5UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for CAP_DATA1 \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_I2C3_SCL (0x6UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for I2C3_SCL \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_EBI_A22 (0x7UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_A22 \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_SD1_DAT0 (0x8UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SD1_DAT0 \hideinitializer */
-#define SYS_GPC_MFPH_PC9MFP_EBI_A6 (0x9UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_A6 \hideinitializer */
-//GPC_MFPH_PC10MFP
-#define SYS_GPC_MFPH_PC10MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC10MFP_SC3_CD (0x1UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for SC3_CD \hideinitializer */
-#define SYS_GPC_MFPH_PC10MFP_UART2_RXD (0x2UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for UART2_RXD \hideinitializer */
-#define SYS_GPC_MFPH_PC10MFP_PWM0_CH2 (0x4UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for PWM0_CH2 \hideinitializer */
-#define SYS_GPC_MFPH_PC10MFP_EBI_A23 (0x6UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for EBI_A23 \hideinitializer */
-#define SYS_GPC_MFPH_PC10MFP_EBI_AD2 (0x7UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for EBI_AD2 \hideinitializer */
-
-//GPC_MFPH_PC11MFP
-#define SYS_GPC_MFPH_PC11MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC11MFP_UART2_TXD (0x2UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for UART2_TXD \hideinitializer */
-#define SYS_GPC_MFPH_PC11MFP_PWM0_CH3 (0x4UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for PWM0_CH3 \hideinitializer */
-#define SYS_GPC_MFPH_PC11MFP_EBI_A24 (0x6UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for EBI_A24 \hideinitializer */
-#define SYS_GPC_MFPH_PC11MFP_EBI_AD3 (0x7UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for EBI_AD3 \hideinitializer */
-
-//GPC_MFPH_PC12MFP
-#define SYS_GPC_MFPH_PC12MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC12MFP_SPI1_SS0 (0x1UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SPI1_SS0 \hideinitializer */
-#define SYS_GPC_MFPH_PC12MFP_SC4_CD (0x2UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SC4_CD \hideinitializer */
-#define SYS_GPC_MFPH_PC12MFP_SD1_CDn (0x4UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SD1_CDn \hideinitializer */
-#define SYS_GPC_MFPH_PC12MFP_CAP_DATA7 (0x5UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for CAP_DATA7 \hideinitializer */
-#define SYS_GPC_MFPH_PC12MFP_ETM_TRACE_DATA3 (0x6UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for ETM_TRACE_DATA3 \hideinitializer */
-#define SYS_GPC_MFPH_PC12MFP_EBI_A0 (0x7UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for MFP_EBI_A0 \hideinitializer */
-
-//GPC_MFPH_PC13MFP
-#define SYS_GPC_MFPH_PC13MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC13MFP_SPI1_MOSI1 (0x1UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SPI1_MOSI1 \hideinitializer */
-#define SYS_GPC_MFPH_PC13MFP_SC4_RST (0x2UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SC4_RST \hideinitializer */
-#define SYS_GPC_MFPH_PC13MFP_SD1_CMD (0x4UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SD1_CMD \hideinitializer */
-#define SYS_GPC_MFPH_PC13MFP_CAP_DATA6 (0x5UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for CAP_DATA6 \hideinitializer */
-#define SYS_GPC_MFPH_PC13MFP_ETM_TRACE_DATA2 (0x6UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for ETM_TRACE_DATA2 \hideinitializer */
-#define SYS_GPC_MFPH_PC13MFP_EBI_A1 (0x7UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for EBI_A1 \hideinitializer */
-
-//GPC_MFPH_PC14MFP
-#define SYS_GPC_MFPH_PC14MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC14MFP_SPI1_MISO1 (0x1UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for SPI1_MISO1 \hideinitializer */
-#define SYS_GPC_MFPH_PC14MFP_SC4_PWR (0x2UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for SC4_PWR \hideinitializer */
-#define SYS_GPC_MFPH_PC14MFP_TM3_EXT (0x3UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for TM3_EXT \hideinitializer */
-#define SYS_GPC_MFPH_PC14MFP_SD1_CLK (0x4UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for SD1_CLK \hideinitializer */
-#define SYS_GPC_MFPH_PC14MFP_CAP_DATA5 (0x5UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for CAP_DATA5 \hideinitializer */
-#define SYS_GPC_MFPH_PC14MFP_ETM_TRACE_DATA1 (0x6UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for ETM_TRACE_DATA1 \hideinitializer */
-#define SYS_GPC_MFPH_PC14MFP_EBI_A2 (0x7UL<<SYS_GPC_MFPH_PC14MFP_Pos) /*!< GPC_MFPH PC14 setting for EBI_A2 \hideinitializer */
-
-//GPC_MFPH_PC15MFP
-#define SYS_GPC_MFPH_PC15MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for GPIO \hideinitializer */
-#define SYS_GPC_MFPH_PC15MFP_SPI1_MOSI0 (0x1UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for SPI1_MOSI0 \hideinitializer */
-#define SYS_GPC_MFPH_PC15MFP_SC4_DAT (0x2UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for SC4_DAT \hideinitializer */
-#define SYS_GPC_MFPH_PC15MFP_SD1_DAT3 (0x4UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for SD1_DAT3 \hideinitializer */
-#define SYS_GPC_MFPH_PC15MFP_CAP_DATA4 (0x5UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for CAP_DATA4 \hideinitializer */
-#define SYS_GPC_MFPH_PC15MFP_ETM_TRACE_DATA0 (0x6UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for ETM_TRACE_DATA0 \hideinitializer */
-#define SYS_GPC_MFPH_PC15MFP_EBI_A3 (0x7UL<<SYS_GPC_MFPH_PC15MFP_Pos) /*!< GPC_MFPH PC15 setting for EBI_A3 \hideinitializer */
-
-//GPD_MFPL_PD0MFP
-#define SYS_GPD_MFPL_PD0MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD0MFP_SPI1_MISO0 (0x1UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI1_MISO0 \hideinitializer */
-#define SYS_GPD_MFPL_PD0MFP_SC4_CLK (0x2UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SC4_CLK \hideinitializer */
-#define SYS_GPD_MFPL_PD0MFP_SD1_DAT2 (0x4UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SD1_DAT2 \hideinitializer */
-#define SYS_GPD_MFPL_PD0MFP_CAP_DATA3 (0x5UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for CAP_DATA3 \hideinitializer */
-#define SYS_GPD_MFPL_PD0MFP_ETM_TRACE_CLK (0x6UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for ETM_TRACE_CLK \hideinitializer */
-#define SYS_GPD_MFPL_PD0MFP_EBI_A4 (0x7UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EBI_A4 \hideinitializer */
-#define SYS_GPD_MFPL_PD0MFP_INT3 (0x8UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for INT3 \hideinitializer */
-
-//GPD_MFPL_PD1MFP
-#define SYS_GPD_MFPL_PD1MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD1MFP_SPI1_CLK (0x1UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SPI1_CLK \hideinitializer */
-#define SYS_GPD_MFPL_PD1MFP_TM0_CNT_OUT (0x3UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for TM0_CNT_OUT \hideinitializer */
-#define SYS_GPD_MFPL_PD1MFP_SD1_DAT1 (0x4UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SD1_DAT1 \hideinitializer */
-#define SYS_GPD_MFPL_PD1MFP_CAP_DATA2 (0x5UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for CAP_DATA2 \hideinitializer */
-#define SYS_GPD_MFPL_PD1MFP_EBI_A5 (0x7UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_A5 \hideinitializer */
-
-//GPD_MFPL_PD2MFP
-#define SYS_GPD_MFPL_PD2MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD2MFP_STADC (0x1UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for STADC \hideinitializer */
-#define SYS_GPD_MFPL_PD2MFP_I2C3_SCL (0x2UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for I2C3_SCL \hideinitializer */
-#define SYS_GPD_MFPL_PD2MFP_SD1_DAT0 (0x4UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SD1_DAT0 \hideinitializer */
-#define SYS_GPD_MFPL_PD2MFP_CAP_DATA1 (0x5UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for CAP_DATA1 \hideinitializer */
-#define SYS_GPD_MFPL_PD2MFP_EBI_A6 (0x7UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_A6 \hideinitializer */
-
-//GPD_MFPL_PD3MFP
-#define SYS_GPD_MFPL_PD3MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_SC5_CLK (0x1UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC5_CLK \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_I2C3_SDA (0x2UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for I2C3_SDA \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_ACMP2_O (0x3UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for ACMP2_O \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_SD0_CDn (0x4UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SD0_CDn \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_CAP_DATA0 (0x5UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for CAP_DATA0 \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_JTAG_TDO (0x6UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for JTAG_TDO \hideinitializer */
-#define SYS_GPD_MFPL_PD3MFP_EBI_A7 (0x7UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_A7 \hideinitializer */
-
-//GPD_MFPL_PD4MFP
-#define SYS_GPD_MFPL_PD4MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD4MFP_SC5_CD (0x1UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SC5_CD \hideinitializer */
-#define SYS_GPD_MFPL_PD4MFP_UART3_RXD (0x2UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for UART3_RXD \hideinitializer */
-#define SYS_GPD_MFPL_PD4MFP_ACMP1_O (0x3UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for ACMP1_O \hideinitializer */
-#define SYS_GPD_MFPL_PD4MFP_CAP_SCLK (0x5UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for CAP_SCLK \hideinitializer */
-#define SYS_GPD_MFPL_PD4MFP_JTAG_TDI (0x6UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for JTAG_TDI \hideinitializer */
-#define SYS_GPD_MFPL_PD4MFP_EBI_A8 (0x7UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for EBI_A8 \hideinitializer */
-
-//GPD_MFPL_PD5MFP
-#define SYS_GPD_MFPL_PD5MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD5MFP_SC5_RST (0x1UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SC5_RST \hideinitializer */
-#define SYS_GPD_MFPL_PD5MFP_UART3_TXD (0x2UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for UART3_TXD \hideinitializer */
-#define SYS_GPD_MFPL_PD5MFP_CAP_VSYNC (0x5UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for CAP_VSYNC \hideinitializer */
-#define SYS_GPD_MFPL_PD5MFP_JTAG_nTRST (0x6UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for JTAG_nTRST \hideinitializer */
-#define SYS_GPD_MFPL_PD5MFP_EBI_A9 (0x7UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for EBI_A9 \hideinitializer */
-
-//GPD_MFPL_PD6MFP
-#define SYS_GPD_MFPL_PD6MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD6MFP_SC5_PWR (0x1UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SC5_PWR \hideinitializer */
-#define SYS_GPD_MFPL_PD6MFP_UART3_RTS (0x2UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART3_RTS \hideinitializer */
-#define SYS_GPD_MFPL_PD6MFP_SD0_CMD (0x4UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SD0_CMD \hideinitializer */
-#define SYS_GPD_MFPL_PD6MFP_CAP_HSYNC (0x5UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for CAP_HSYNC \hideinitializer */
-#define SYS_GPD_MFPL_PD6MFP_EBI_A10 (0x7UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for EBI_A10 \hideinitializer */
-
-//GPD_MFPL_PD7MFP
-#define SYS_GPD_MFPL_PD7MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPL_PD7MFP_SC5_DAT (0x1UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SC5_DAT \hideinitializer */
-#define SYS_GPD_MFPL_PD7MFP_UART3_CTS (0x2UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for UART3_CTS \hideinitializer */
-#define SYS_GPD_MFPL_PD7MFP_SD0_CLK (0x4UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SD0_CLK \hideinitializer */
-#define SYS_GPD_MFPL_PD7MFP_CAP_PIXCLK (0x5UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for CAP_PIXCLK \hideinitializer */
-#define SYS_GPD_MFPL_PD7MFP_EBI_A11 (0x7UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for EBI_A11 \hideinitializer */
-
-//GPD_MFPL_PD8MFP
-#define SYS_GPD_MFPH_PD8MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD8MFP_SPI3_MISO1 (0x1UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for SPI3_MISO1 \hideinitializer */
-#define SYS_GPD_MFPH_PD8MFP_I2C0_SCL (0x2UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for I2C0_SCL \hideinitializer */
-
-//GPD_MFPH_PD9MFP
-#define SYS_GPD_MFPH_PD9MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD9MFP_SPI3_MOSI1 (0x1UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for SPI3_MOSI1 \hideinitializer */
-#define SYS_GPD_MFPH_PD9MFP_I2C0_SDA (0x2UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for I2C0_SDA \hideinitializer */
-
-//GPD_MFPH_PD10MFP
-#define SYS_GPD_MFPH_PD10MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD10MFP_SC3_DAT (0x1UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for SC3_DAT \hideinitializer */
-#define SYS_GPD_MFPH_PD10MFP_I2C4_SCL (0x2UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for I2C4_SCL \hideinitializer */
-
-//GPD_MFPH_PD11MFP
-#define SYS_GPD_MFPH_PD11MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD11MFP_SC3_RST (0x1UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for SC3_RST \hideinitializer */
-#define SYS_GPD_MFPH_PD11MFP_TM3_CNT_OUT (0x3UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for TM3_CNT_OUT \hideinitializer */
-
-//GPD_MFPH_PD12MFP
-#define SYS_GPD_MFPH_PD12MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD12MFP_SC3_CLK (0x1UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for SC3_CLK \hideinitializer */
-#define SYS_GPD_MFPH_PD12MFP_I2C4_SDA (0x2UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for I2C4_SDA \hideinitializer */
-
-//GPD_MFPH_PD13MFP
-#define SYS_GPD_MFPH_PD13MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD13MFP_SPI1_SS0 (0x1UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for SPI1_SS0 \hideinitializer */
-#define SYS_GPD_MFPH_PD13MFP_UART5_CTS (0x2UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for UART5_CTS \hideinitializer */
-#define SYS_GPD_MFPH_PD13MFP_ECAP0_IC2 (0x3UL<<SYS_GPD_MFPH_PD13MFP_Pos) /*!< GPD_MFPH PD13 setting for ECAP0_IC2 \hideinitializer */
-
-//GPD_MFPH_PD14MFP
-#define SYS_GPD_MFPH_PD14MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD14MFP_SPI1_CLK (0x1UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for SPI1_CLK \hideinitializer */
-#define SYS_GPD_MFPH_PD14MFP_UART5_RTS (0x2UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for UART5_RTS \hideinitializer */
-#define SYS_GPD_MFPH_PD14MFP_ECAP0_IC1 (0x3UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for ECAP0_IC1 \hideinitializer */
-
-//GPD_MFPH_PD15MFP
-#define SYS_GPD_MFPH_PD15MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for GPIO \hideinitializer */
-#define SYS_GPD_MFPH_PD15MFP_SPI1_MISO0 (0x1UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for SPI1_MISO0 \hideinitializer */
-#define SYS_GPD_MFPH_PD15MFP_UART5_TXD (0x2UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for UART5_TXD \hideinitializer */
-#define SYS_GPD_MFPH_PD15MFP_ECAP0_IC0 (0x3UL<<SYS_GPD_MFPH_PD15MFP_Pos) /*!< GPD_MFPH PD15 setting for ECAP0_IC0 \hideinitializer */
-
-//GPE_MFPL_PE0MFP
-#define SYS_GPE_MFPL_PE0MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE0MFP_ADC0_0 (0x1UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for ADC0_0 \hideinitializer */
-#define SYS_GPE_MFPL_PE0MFP_INT4 (0x8UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for INT4 \hideinitializer */
-
-//GPE_MFPL_PE1MFP
-#define SYS_GPE_MFPL_PE1MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE1MFP_ADC0_1 (0x1UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for ADC0_1 \hideinitializer */
-#define SYS_GPE_MFPL_PE1MFP_TM2_CNT_OUT (0x3UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for TM2_CNT_OUT \hideinitializer */
-
-//GPE_MFPL_PE2MFP
-#define SYS_GPE_MFPL_PE2MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE2MFP_ADC0_2 (0x1UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for ADC0_2 \hideinitializer */
-#define SYS_GPE_MFPL_PE2MFP_ACMP0_O (0x2UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for ACMP0_O \hideinitializer */
-#define SYS_GPE_MFPL_PE2MFP_SPI0_MISO0 (0x3UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI0_MISO0 \hideinitializer */
-
-//GPE_MFPL_PE3MFP
-#define SYS_GPE_MFPL_PE3MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE3MFP_ADC0_3 (0x1UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for ADC0_3 \hideinitializer */
-#define SYS_GPE_MFPL_PE3MFP_ACMP0_P3 (0x2UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for ACMP0_P3 \hideinitializer */
-#define SYS_GPE_MFPL_PE3MFP_SPI0_MOSI0 (0x3UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI0_MOSI0 \hideinitializer */
-
-//GPE_MFPL_PE4MFP
-#define SYS_GPE_MFPL_PE4MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE4MFP_ADC0_4 (0x1UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for ADC0_4 \hideinitializer */
-#define SYS_GPE_MFPL_PE4MFP_ACMP0_P2 (0x2UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for ACMP0_P2 \hideinitializer */
-#define SYS_GPE_MFPL_PE4MFP_SPI0_SS0 (0x3UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI0_SS0 \hideinitializer */
-
-//GPE_MFPL_PE5MFP
-#define SYS_GPE_MFPL_PE5MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE5MFP_ADC0_5 (0x1UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for ADC0_5 \hideinitializer */
-#define SYS_GPE_MFPL_PE5MFP_ACMP0_P1 (0x2UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for ACMP0_P1 \hideinitializer */
-#define SYS_GPE_MFPL_PE5MFP_SPI0_CLK (0x3UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI0_CLK \hideinitializer */
-#define SYS_GPE_MFPL_PE5MFP_SD0_CDn (0x4UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SD0_CDn \hideinitializer */
-
-//GPE_MFPL_PE6MFP
-#define SYS_GPE_MFPL_PE6MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE6MFP_ADC0_6 (0x1UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for ADC0_6 \hideinitializer */
-#define SYS_GPE_MFPL_PE6MFP_ACMP0_P0 (0x2UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for ACMP0_P0 \hideinitializer */
-#define SYS_GPE_MFPL_PE6MFP_SPI0_MISO0 (0x3UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SPI0_MISO0 \hideinitializer */
-#define SYS_GPE_MFPL_PE6MFP_SD0_CMD (0x4UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SD0_CMD \hideinitializer */
-#define SYS_GPE_MFPL_PE6MFP_EBI_nWR (0x7UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for EBI_nWR \hideinitializer */
-
-//GPE_MFPL_PE7MFP
-#define SYS_GPE_MFPL_PE7MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPL_PE7MFP_ADC0_7 (0x1UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for ADC0_7 \hideinitializer */
-#define SYS_GPE_MFPL_PE7MFP_ACMP0_N (0x2UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for ACMP0_N \hideinitializer */
-#define SYS_GPE_MFPL_PE7MFP_SPI0_MOSI0 (0x3UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SPI0_MOSI0 \hideinitializer */
-#define SYS_GPE_MFPL_PE7MFP_SD0_CLK (0x4UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SD0_CLK \hideinitializer */
-#define SYS_GPE_MFPL_PE7MFP_EBI_nRD (0x7UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for _EBI_nRD \hideinitializer */
-
-//GPE_MFPL_PE8MFP
-#define SYS_GPE_MFPH_PE8MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE8MFP_ADC0_8 (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ADC0_8 \hideinitializer */
-#define SYS_GPE_MFPH_PE8MFP_ADC1_0 (0x1UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ADC1_0 \hideinitializer */
-#define SYS_GPE_MFPH_PE8MFP_ACMP1_N (0x2UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ACMP1_N \hideinitializer */
-#define SYS_GPE_MFPH_PE8MFP_TM1_CNT_OUT (0x3UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for TM1_CNT_OUT \hideinitializer */
-#define SYS_GPE_MFPH_PE8MFP_SD0_DAT3 (0x4UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SD0_DAT3 \hideinitializer */
-#define SYS_GPE_MFPH_PE8MFP_EBI_ALE (0x7UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EBI_ALE \hideinitializer */
-
-//GPE_MFPH_PE9MFP
-#define SYS_GPE_MFPH_PE9MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE9MFP_ADC0_9 (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ADC0_9 \hideinitializer */
-#define SYS_GPE_MFPH_PE9MFP_ADC1_1 (0x1UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ADC1_1 \hideinitializer */
-#define SYS_GPE_MFPH_PE9MFP_ACMP1_P0 (0x2UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ACMP1_P0 \hideinitializer */
-#define SYS_GPE_MFPH_PE9MFP_SD0_DAT2 (0x4UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SD0_DAT2 \hideinitializer */
-#define SYS_GPE_MFPH_PE9MFP_EBI_nWRH (0x7UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EBI_nWRH \hideinitializer */
-
-//GPE_MFPH_PE10MFP
-#define SYS_GPE_MFPH_PE10MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE10MFP_ADC0_10 (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for ADC0_10 \hideinitializer */
-#define SYS_GPE_MFPH_PE10MFP_ADC1_2 (0x1UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for ADC1_2 \hideinitializer */
-#define SYS_GPE_MFPH_PE10MFP_ACMP1_P1 (0x2UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for ACMP1_P1 \hideinitializer */
-#define SYS_GPE_MFPH_PE10MFP_SPI0_MISO1 (0x3UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI0_MISO1 \hideinitializer */
-#define SYS_GPE_MFPH_PE10MFP_SD0_DAT1 (0x4UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SD0_DAT1 \hideinitializer */
-#define SYS_GPE_MFPH_PE10MFP_EBI_nWRL (0x7UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for EBI_nWRL \hideinitializer */
-
-//GPE_MFPH_PE11MFP
-#define SYS_GPE_MFPH_PE11MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_ADC0_11 (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ADC0_11 \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_ADC1_3 (0x1UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ADC1_3 \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_ACMP1_P2 (0x2UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ACMP1_P2 \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_SPI0_MOSI1 (0x3UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI0_MOSI1 \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_SD0_DAT0 (0x4UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SD0_DAT0 \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_ACMP2_P3 (0x5UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ACMP2_P3 \hideinitializer */
-#define SYS_GPE_MFPH_PE11MFP_EBI_nCS0 (0x7UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for EBI_nCS0 \hideinitializer */
-
-//GPE_MFPH_PE12MFP
-#define SYS_GPE_MFPH_PE12MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE12MFP_ADC1_4 (0x1UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for ADC1_4 \hideinitializer */
-#define SYS_GPE_MFPH_PE12MFP_ACMP1_P3 (0x2UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for ACMP1_P3 \hideinitializer */
-#define SYS_GPE_MFPH_PE12MFP_ACMP2_P2 (0x3UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for ACMP2_P2 \hideinitializer */
-#define SYS_GPE_MFPH_PE12MFP_EBI_nCS1 (0x7UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for EBI_nCS1 \hideinitializer */
-//GPE_MFPH_PE13MFP
-#define SYS_GPE_MFPH_PE13MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE13MFP_ADC1_5 (0x1UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for ADC1_5 \hideinitializer */
-#define SYS_GPE_MFPH_PE13MFP_ACMP2_P1 (0x3UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for ACMP2_P1 \hideinitializer */
-#define SYS_GPE_MFPH_PE13MFP_EBI_nCS2 (0x7UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for EBI_nCS2 \hideinitializer */
-
-//GPE_MFPH_PE14MFP
-#define SYS_GPE_MFPH_PE14MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE14MFP_ADC1_6 (0x1UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for ADC1_6 \hideinitializer */
-#define SYS_GPE_MFPH_PE14MFP_ACMP2_P0 (0x3UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for ACMP2_P0 \hideinitializer */
-#define SYS_GPE_MFPH_PE14MFP_EBI_nCS3 (0x7UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for EBI_nCS3 \hideinitializer */
-
-//GPE_MFPH_PE15MFP
-#define SYS_GPE_MFPH_PE15MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for GPIO \hideinitializer */
-#define SYS_GPE_MFPH_PE15MFP_ADC1_7 (0x1UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for ADC1_7 \hideinitializer */
-#define SYS_GPE_MFPH_PE15MFP_ACMP2_N (0x3UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for ACMP2_N \hideinitializer */
-
-//GPF_MFPL_PF0MFP
-#define SYS_GPF_MFPL_PF0MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF0MFP_SPI1_MOSI0 (0x1UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for SPI1_MOSI0 \hideinitializer */
-#define SYS_GPF_MFPL_PF0MFP_UART5_RXD (0x2UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART5_RXD \hideinitializer */
-#define SYS_GPF_MFPL_PF0MFP_INT5 (0x8UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for INT5 \hideinitializer */
-
-//GPF_MFPL_PF1MFP
-#define SYS_GPF_MFPL_PF1MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF1MFP_SPI2_MOSI1 (0x1UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for SPI2_MOSI1 \hideinitializer */
-
-//GPF_MFPL_PF2MFP
-#define SYS_GPF_MFPL_PF2MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF2MFP_SPI3_SS0 (0x1UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for SPI3_SS0 \hideinitializer */
-#define SYS_GPF_MFPL_PF2MFP_SD0_DAT3 (0x4UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for SD0_DAT3 \hideinitializer */
-#define SYS_GPF_MFPL_PF2MFP_EMAC_MII_RXD3 (0x6UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for EMAC_MII_RXD3 \hideinitializer */
-
-//GPF_MFPL_PF3MFP
-#define SYS_GPF_MFPL_PF3MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF3MFP_SPI3_CLK (0x1UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for SPI3_CLK \hideinitializer */
-#define SYS_GPF_MFPL_PF3MFP_SD0_DAT2 (0x4UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for SD0_DAT2 \hideinitializer */
-#define SYS_GPF_MFPL_PF3MFP_EMAC_MII_RXD2 (0x6UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for EMAC_MII_RXD2 \hideinitializer */
-
-//GPF_MFPL_PF4MFP
-#define SYS_GPF_MFPL_PF4MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF4MFP_SPI3_MISO0 (0x1UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for SPI3_MISO0 \hideinitializer */
-#define SYS_GPF_MFPL_PF4MFP_SD0_DAT1 (0x4UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for SD0_DAT1 \hideinitializer */
-#define SYS_GPF_MFPL_PF4MFP_EMAC_MII_COL0 (0x6UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for EMAC_MII_COL0 \hideinitializer */
-
-//GPF_MFPL_PF5MFP
-#define SYS_GPF_MFPL_PF5MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF5MFP_SPI3_MOSI0 (0x1UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for SPI3_MOSI0 \hideinitializer */
-#define SYS_GPF_MFPL_PF5MFP_SD0_DAT0 (0x4UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for SD0_DAT0 \hideinitializer */
-#define SYS_GPF_MFPL_PF5MFP_EMAC_MII_CRS (0x6UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EMAC_MII_CRS \hideinitializer */
-
-//GPF_MFPL_PF6MFP
-#define SYS_GPF_MFPL_PF6MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF6MFP_UART2_RXD (0x1UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for UART2_RXD \hideinitializer */
-#define SYS_GPF_MFPL_PF6MFP_SD0_CDn (0x4UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SD0_CDn \hideinitializer */
-#define SYS_GPF_MFPL_PF6MFP_EMAC_MII_TXCLK (0x6UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EMAC_MII_TXCLK \hideinitializer */
-
-//GPF_MFPL_PF7MFP
-#define SYS_GPF_MFPL_PF7MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPL_PF7MFP_UART2_TXD (0x1UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for UART2_TXD \hideinitializer */
-#define SYS_GPF_MFPL_PF7MFP_SD0_CMD (0x4UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SD0_CMD \hideinitializer */
-#define SYS_GPF_MFPL_PF7MFP_EMAC_MII_TXD3 (0x6UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for EMAC_MII_TXD3 \hideinitializer */
-
-//GPF_MFPL_PF8MFP
-#define SYS_GPF_MFPH_PF8MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF8MFP_UART2_RTS (0x1UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for UART2_RTS \hideinitializer */
-#define SYS_GPF_MFPH_PF8MFP_SD0_CLK (0x4UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SD0_CLK \hideinitializer */
-#define SYS_GPF_MFPH_PF8MFP_EMAC_MII_TXD2 (0x6UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for EMAC_MII_TXD2 \hideinitializer */
-
-//GPF_MFPH_PF9MFP
-#define SYS_GPF_MFPH_PF9MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF9MFP_OPA0_IN_P (0x1UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for OPA0_IN_P \hideinitializer */
-#define SYS_GPF_MFPH_PF9MFP_PWM0_CH0 (0x4UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for PWM0_CH0 \hideinitializer */
-
-//GPF_MFPH_PF10MFP
-#define SYS_GPF_MFPH_PF10MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF10MFP_OPA0_IN_N (0x1UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for OPA0_IN_N \hideinitializer */
-#define SYS_GPF_MFPH_PF10MFP_PWM0_CH1 (0x4UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for PWM0_CH1 \hideinitializer */
-
-//GPF_MFPH_PF11MFP
-#define SYS_GPF_MFPH_PF11MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF11MFP_OPA0_O (0x1UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for OPA0_O \hideinitializer */
-#define SYS_GPF_MFPH_PF11MFP_UART1_RTS (0x2UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for UART1_RTS \hideinitializer */
-
-//GPF_MFPH_PF12MFP
-#define SYS_GPF_MFPH_PF12MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF12MFP_Pos) /*!< GPF_MFPH PF12 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF12MFP_OPA1_IN_P (0x1UL<<SYS_GPF_MFPH_PF12MFP_Pos) /*!< GPF_MFPH PF12 setting for OPA1_IN_P \hideinitializer */
-#define SYS_GPF_MFPH_PF12MFP_UART1_CTS (0x2UL<<SYS_GPF_MFPH_PF12MFP_Pos) /*!< GPF_MFPH PF12 setting for UART1_CTS \hideinitializer */
-//GPF_MFPH_PF13MFP
-#define SYS_GPF_MFPH_PF13MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF13MFP_Pos) /*!< GPF_MFPH PF13 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF13MFP_OPA1_IN_N (0x1UL<<SYS_GPF_MFPH_PF13MFP_Pos) /*!< GPF_MFPH PF13 setting for OPA1_IN_N \hideinitializer */
-#define SYS_GPF_MFPH_PF13MFP_UART1_TXD (0x2UL<<SYS_GPF_MFPH_PF13MFP_Pos) /*!< GPF_MFPH PF13 setting for UART1_TXD \hideinitializer */
-
-//GPF_MFPH_PF14MFP
-#define SYS_GPF_MFPH_PF14MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF14MFP_OPA1_O (0x1UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for OPA1_O \hideinitializer */
-#define SYS_GPF_MFPH_PF14MFP_UART1_RXD (0x2UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< GPF_MFPH PF14 setting for UART1_RXD \hideinitializer */
-
-//GPF_MFPH_PF15MFP
-#define SYS_GPF_MFPH_PF15MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for GPIO \hideinitializer */
-#define SYS_GPF_MFPH_PF15MFP_UART0_RTS (0x1UL<<SYS_GPF_MFPH_PF15MFP_Pos) /*!< GPF_MFPH PF15 setting for UART0_RTS \hideinitializer */
-
-
-//GPG_MFPL_PG0MFP
-#define SYS_GPG_MFPL_PG0MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< GPG_MFPL PG0 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG0MFP_UART0_CTS (0x1UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< GPG_MFPL PG0 setting for UART0_CTS \hideinitializer */
-#define SYS_GPG_MFPL_PG0MFP_INT6 (0x8UL<<SYS_GPG_MFPL_PG0MFP_Pos) /*!< GPG_MFPL PG0 setting for INT6 \hideinitializer */
-
-//GPG_MFPL_PG1MFP
-#define SYS_GPG_MFPL_PG1MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< GPG_MFPL PG1 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG1MFP_UART0_RXD (0x1UL<<SYS_GPG_MFPL_PG1MFP_Pos) /*!< GPG_MFPL PG1 setting for UART0_RXD \hideinitializer */
-
-//GPG_MFPL_PG2MFP
-#define SYS_GPG_MFPL_PG2MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG2MFP_UART0_TXD (0x1UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for UART0_TXD \hideinitializer */
-
-//GPG_MFPL_PG3MFP
-#define SYS_GPG_MFPL_PG3MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG3MFP_PS2_CLK (0x1UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for PS2_CLK \hideinitializer */
-#define SYS_GPG_MFPL_PG3MFP_I2S1_DO (0x2UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2S1_DO \hideinitializer */
-#define SYS_GPG_MFPL_PG3MFP_SC1_RST (0x3UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for SC1_RST \hideinitializer */
-//GPG_MFPL_PG4MFP
-#define SYS_GPG_MFPL_PG4MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG4MFP_PS2_DAT (0x1UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for PS2_DAT \hideinitializer */
-#define SYS_GPG_MFPL_PG4MFP_I2S1_DI (0x2UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for I2S1_DI \hideinitializer */
-#define SYS_GPG_MFPL_PG4MFP_SC1_PWR (0x3UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for SC1_PWR \hideinitializer */
-
-//GPG_MFPL_PG5MFP
-#define SYS_GPG_MFPL_PG5MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< GPG_MFPL PG5 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG5MFP_I2S1_BCLK (0x2UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< GPG_MFPL PG5 setting for I2S1_BCLK \hideinitializer */
-#define SYS_GPG_MFPL_PG5MFP_SC1_DAT (0x3UL<<SYS_GPG_MFPL_PG5MFP_Pos) /*!< GPG_MFPL PG5 setting for SC1_DAT \hideinitializer */
-//GPG_MFPL_PG6MFP
-#define SYS_GPG_MFPL_PG6MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< GPG_MFPL PG6 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG6MFP_I2S1_LRCK (0x2UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< GPG_MFPL PG6 setting for I2S1_LRCK \hideinitializer */
-#define SYS_GPG_MFPL_PG6MFP_SC1_CLK (0x3UL<<SYS_GPG_MFPL_PG6MFP_Pos) /*!< GPG_MFPL PG6 setting for SC1_CLK \hideinitializer */
-
-//GPG_MFPL_PG7MFP
-#define SYS_GPG_MFPL_PG7MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPL_PG7MFP_SPI2_MISO0 (0x1UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for SPI2_MISO0 \hideinitializer */
-#define SYS_GPG_MFPL_PG7MFP_I2S1_MCLK (0x2UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for I2S1_MCLK \hideinitializer */
-#define SYS_GPG_MFPL_PG7MFP_SC1_CD (0x3UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for SC1_CD \hideinitializer */
-#define SYS_GPG_MFPL_PG7MFP_SC3_RST (0x4UL<<SYS_GPG_MFPL_PG7MFP_Pos) /*!< GPG_MFPL PG7 setting for SC3_RST \hideinitializer */
-
-//GPG_MFPL_PG8MFP
-#define SYS_GPG_MFPH_PG8MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG8MFP_SPI2_MOSI0 (0x1UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for SPI2_MOSI0 \hideinitializer */
-#define SYS_GPG_MFPH_PG8MFP_I2S1_DO (0x2UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for I2S1_DO \hideinitializer */
-#define SYS_GPG_MFPH_PG8MFP_UART4_RTS (0x3UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for UART4_RTS \hideinitializer */
-#define SYS_GPG_MFPH_PG8MFP_SC3_DAT (0x4UL<<SYS_GPG_MFPH_PG8MFP_Pos) /*!< GPG_MFPH PG8 setting for SC3_DAT \hideinitializer */
-
-//GPG_MFPH_PG9MFP
-#define SYS_GPG_MFPH_PG9MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG9MFP_SPI2_CLK (0x1UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for SPI2_CLK \hideinitializer */
-#define SYS_GPG_MFPH_PG9MFP_I2S1_DI (0x2UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for I2S1_DI \hideinitializer */
-#define SYS_GPG_MFPH_PG9MFP_UART4_CTS (0x3UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for UART4_CTS \hideinitializer */
-#define SYS_GPG_MFPH_PG9MFP_SC3_CLK (0x4UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for SC3_CLK \hideinitializer */
-
-//GPG_MFPH_PG10MFP
-#define SYS_GPG_MFPH_PG10MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG10MFP_ICE_CLK (0x1UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for ICE_CLK \hideinitializer */
-#define SYS_GPG_MFPH_PG10MFP_JTAG_TCLK (0x6UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for JTAG_TCLK \hideinitializer */
-
-//GPG_MFPH_PG11MFP
-#define SYS_GPG_MFPH_PG11MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG11MFP_ICE_DAT (0x1UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for ICE_DAT \hideinitializer */
-#define SYS_GPG_MFPH_PG11MFP_JTAG_TMS (0x6UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for JTAG_TMS \hideinitializer */
-
-//GPG_MFPH_PG12MFP
-#define SYS_GPG_MFPH_PG12MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG12MFP_XT1_OUT (0x1UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for XT1_OUT \hideinitializer */
-
-//GPG_MFPH_PG13MFP
-#define SYS_GPG_MFPH_PG13MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG13MFP_XT1_IN (0x1UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for XT1_IN \hideinitializer */
-
-//GPG_MFPH_PG14MFP
-#define SYS_GPG_MFPH_PG14MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG14MFP_X32K_OUT (0x1UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for X32K_OUT \hideinitializer */
-#define SYS_GPG_MFPH_PG14MFP_I2C1_SDA (0x3UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for I2C1_SDA \hideinitializer */
-
-//GPG_MFPH_PG15MFP
-#define SYS_GPG_MFPH_PG15MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for GPIO \hideinitializer */
-#define SYS_GPG_MFPH_PG15MFP_X32K_IN (0x1UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for X32K_IN \hideinitializer */
-#define SYS_GPG_MFPH_PG15MFP_I2C1_SCL (0x3UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for I2C1_SCL \hideinitializer */
-
-
-//GPH_MFPL_PH0MFP
-#define SYS_GPH_MFPL_PH0MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH0MFP_I2C1_SCL (0x1UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for I2C1_SCL \hideinitializer */
-#define SYS_GPH_MFPL_PH0MFP_UART4_RXD (0x2UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for UART4_RXD \hideinitializer */
-#define SYS_GPH_MFPL_PH0MFP_CAN1_RXD (0x3UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for CAN1_RXD \hideinitializer */
-#define SYS_GPH_MFPL_PH0MFP_INT7 (0x8UL<<SYS_GPH_MFPL_PH0MFP_Pos) /*!< GPH_MFPL PH0 setting for INT7 \hideinitializer */
-
-//GPH_MFPL_PH1MFP
-#define SYS_GPH_MFPL_PH1MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH1MFP_UART4_TXD (0x1UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for UART4_TXD \hideinitializer */
-#define SYS_GPH_MFPL_PH1MFP_I2C1_SDA (0x2UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for I2C1_SDA \hideinitializer */
-#define SYS_GPH_MFPL_PH1MFP_CAN1_TXD (0x3UL<<SYS_GPH_MFPL_PH1MFP_Pos) /*!< GPH_MFPL PH1 setting for CAN1_TXD \hideinitializer */
-
-//GPH_MFPL_PH2MFP
-#define SYS_GPH_MFPL_PH2MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< GPH_MFPL PH2 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH2MFP_UART2_CTS (0x1UL<<SYS_GPH_MFPL_PH2MFP_Pos) /*!< GPH_MFPL PH2 setting for UART2_CTS \hideinitializer */
-
-//GPH_MFPL_PH3MFP
-#define SYS_GPH_MFPL_PH3MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< GPH_MFPL PH3 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH3MFP_I2C3_SCL (0x1UL<<SYS_GPH_MFPL_PH3MFP_Pos) /*!< GPH_MFPL PH3 setting for I2C3_SCL \hideinitializer */
-
-//GPH_MFPL_PH4MFP
-#define SYS_GPH_MFPL_PH4MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH4MFP_I2C3_SDA (0x1UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for I2C3_SDA \hideinitializer */
-
-//GPH_MFPL_PH5MFP
-#define SYS_GPH_MFPL_PH5MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH5MFP_SPI2_SS0 (0x1UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for SPI2_SS0 \hideinitializer */
-
-//GPH_MFPL_PH6MFP
-#define SYS_GPH_MFPL_PH6MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH6MFP_SPI2_CLK (0x1UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for SPI2_CLK \hideinitializer */
-
-//GPH_MFPL_PH7MFP
-#define SYS_GPH_MFPL_PH7MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPL_PH7MFP_SPI2_MISO0 (0x1UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for SPI2_MISO0 \hideinitializer */
-
-//GPH_MFPL_PH8MFP
-#define SYS_GPH_MFPH_PH8MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH8MFP_SPI2_MOSI0 (0x1UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SPI2_MOSI0 \hideinitializer */
-
-//GPH_MFPH_PH9MFP
-#define SYS_GPH_MFPH_PH9MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH9MFP_SPI2_MISO1 (0x1UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SPI2_MISO1 \hideinitializer */
-
-//GPH_MFPH_PH10MFP
-#define SYS_GPH_MFPH_PH10MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH10MFP_SPI2_MOSI1 (0x1UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for SPI2_MOSI1 \hideinitializer */
-
-//GPH_MFPH_PH11MFP
-#define SYS_GPH_MFPH_PH11MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH11MFP_UART3_RXD (0x1UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for UART3_RXD \hideinitializer */
-
-//GPH_MFPH_PH12MFP
-#define SYS_GPH_MFPH_PH12MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH12MFP_Pos) /*!< GPH_MFPH PH12 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH12MFP_UART3_TXD (0x1UL<<SYS_GPH_MFPH_PH12MFP_Pos) /*!< GPH_MFPH PH12 setting for UART3_TXD \hideinitializer */
-
-//GPH_MFPH_PH13MFP
-#define SYS_GPH_MFPH_PH13MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH13MFP_Pos) /*!< GPH_MFPH PH13 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH13MFP_UART3_RTS (0x1UL<<SYS_GPH_MFPH_PH13MFP_Pos) /*!< GPH_MFPH PH13 setting for UART3_RTS \hideinitializer */
-
-//GPH_MFPH_PH14MFP
-#define SYS_GPH_MFPH_PH14MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH14MFP_Pos) /*!< GPH_MFPH PH14 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH14MFP_UART3_CTS (0x1UL<<SYS_GPH_MFPH_PH14MFP_Pos) /*!< GPH_MFPH PH14 setting for UART3_CTS \hideinitializer */
-
-//GPH_MFPH_PH15MFP
-#define SYS_GPH_MFPH_PH15MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH15MFP_Pos) /*!< GPH_MFPH PH15 setting for GPIO \hideinitializer */
-#define SYS_GPH_MFPH_PH15MFP_SC5_CLK (0x2UL<<SYS_GPH_MFPH_PH15MFP_Pos) /*!< GPH_MFPH PH15 setting for SC5_CLK \hideinitializer */
-
-//GPI_MFPL_PI0MFP
-#define SYS_GPI_MFPL_PI0MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI0MFP_Pos) /*!< GPI_MFPL PI0 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI0MFP_SC5_RST (0x2UL<<SYS_GPI_MFPL_PI0MFP_Pos) /*!< GPI_MFPL PI0 setting for SC5_RST \hideinitializer */
-
-//GPI_MFPL_PI1MFP
-#define SYS_GPI_MFPL_PI1MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI1MFP_Pos) /*!< GPI_MFPL PI1 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI1MFP_SC5_PWR (0x2UL<<SYS_GPI_MFPL_PI1MFP_Pos) /*!< GPI_MFPL PI1 setting for SC5_PWR \hideinitializer */
-
-//GPI_MFPL_PI2MFP
-#define SYS_GPI_MFPL_PI2MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI2MFP_Pos) /*!< GPI_MFPL PI2 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI2MFP_SC5_DAT (0x2UL<<SYS_GPI_MFPL_PI2MFP_Pos) /*!< GPI_MFPL PI2 setting for SC5_DAT \hideinitializer */
-
-//GPI_MFPL_PI3MFP
-#define SYS_GPI_MFPL_PI3MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI3MFP_Pos) /*!< GPI_MFPL PI3 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI3MFP_SPI3_SS0 (0x1UL<<SYS_GPI_MFPL_PI3MFP_Pos) /*!< GPI_MFPL PI3 setting for SPI3_SS0 \hideinitializer */
-
-//GPI_MFPL_PI4MFP
-#define SYS_GPI_MFPL_PI4MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI4MFP_Pos) /*!< GPI_MFPL PI4 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI4MFP_SPI3_CLK (0x1UL<<SYS_GPI_MFPL_PI4MFP_Pos) /*!< GPI_MFPL PI4 setting for SPI3_CLK \hideinitializer */
-
-//GPI_MFPL_PI5MFP
-#define SYS_GPI_MFPL_PI5MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI5MFP_Pos) /*!< GPI_MFPL PI5 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI5MFP_SPI3_MISO0 (0x1UL<<SYS_GPI_MFPL_PI5MFP_Pos) /*!< GPI_MFPL PI5 setting for SPI3_MISO0 \hideinitializer */
-
-//GPI_MFPL_PI6MFP
-#define SYS_GPI_MFPL_PI6MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI6MFP_Pos) /*!< GPI_MFPL PI6 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI6MFP_SPI3_MOSI0 (0x1UL<<SYS_GPI_MFPL_PI6MFP_Pos) /*!< GPI_MFPL PI6 setting for SPI3_MOSI0 \hideinitializer */
-
-//GPI_MFPL_PI7MFP
-#define SYS_GPI_MFPL_PI7MFP_GPIO (0x0UL<<SYS_GPI_MFPL_PI7MFP_Pos) /*!< GPI_MFPL PI7 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPL_PI7MFP_I2C2_SCL (0x1UL<<SYS_GPI_MFPL_PI7MFP_Pos) /*!< GPI_MFPL PI7 setting for I2C2_SCL \hideinitializer */
-#define SYS_GPI_MFPL_PI7MFP_SPI3_MISO1 (0x2UL<<SYS_GPI_MFPL_PI7MFP_Pos) /*!< GPI_MFPL PI7 setting for SPI3_MISO1 \hideinitializer */
-
-//GPI_MFPL_PI8MFP
-#define SYS_GPI_MFPH_PI8MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI8MFP_Pos) /*!< GPI_MFPH PI8 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPH_PI8MFP_I2C2_SDA (0x1UL<<SYS_GPI_MFPH_PI8MFP_Pos) /*!< GPI_MFPH PI8 setting for I2C2_SDA \hideinitializer */
-#define SYS_GPI_MFPH_PI8MFP_SPI3_MOSI1 (0x2UL<<SYS_GPI_MFPH_PI8MFP_Pos) /*!< GPI_MFPH PI8 setting for SPI3_MOSI1 \hideinitializer */
-
-//GPI_MFPH_PI9MFP
-#define SYS_GPI_MFPH_PI9MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI9MFP_Pos) /*!< GPI_MFPH PI9 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPH_PI9MFP_I2C4_SCL (0x4UL<<SYS_GPI_MFPH_PI9MFP_Pos) /*!< GPI_MFPH PI9 setting for I2C4_SCL \hideinitializer */
-
-//GPI_MFPH_PI10MFP
-#define SYS_GPI_MFPH_PI10MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI10MFP_Pos) /*!< GPI_MFPH PI10 setting for GPIO \hideinitializer */
-
-//GPI_MFPH_PI11MFP
-#define SYS_GPI_MFPH_PI11MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPH_PI11MFP_SPI2_SS0 (0x1UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for SPI2_SS0 \hideinitializer */
-#define SYS_GPI_MFPH_PI11MFP_I2S1_BCLK (0x2UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for I2S1_BCLK \hideinitializer */
-#define SYS_GPI_MFPH_PI11MFP_I2C4_SCL (0x3UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for I2C4_SCL \hideinitializer */
-#define SYS_GPI_MFPH_PI11MFP_SC3_PWR (0x4UL<<SYS_GPI_MFPH_PI11MFP_Pos) /*!< GPI_MFPH PI11 setting for SC3_PWR \hideinitializer */
-
-//GPI_MFPH_PI12MFP
-#define SYS_GPI_MFPH_PI12MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for GPIO \hideinitializer */
-#define SYS_GPI_MFPH_PI12MFP_SPI2_MISO1 (0x1UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for SPI2_MISO1 \hideinitializer */
-#define SYS_GPI_MFPH_PI12MFP_I2S1_LRCK (0x2UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for I2S1_LRCK \hideinitializer */
-#define SYS_GPI_MFPH_PI12MFP_I2C4_SDA (0x3UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for I2C4_SDA \hideinitializer */
-#define SYS_GPI_MFPH_PI12MFP_SC3_CD (0x4UL<<SYS_GPI_MFPH_PI12MFP_Pos) /*!< GPI_MFPH PI12 setting for SC3_CD \hideinitializer */
-
-//GPI_MFPH_PI13MFP
-#define SYS_GPI_MFPH_PI13MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI13MFP_Pos) /*!< GPI_MFPH PI13 setting for GPIO \hideinitializer */
-
-//GPI_MFPH_PI14MFP
-#define SYS_GPI_MFPH_PI14MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI14MFP_Pos) /*!< GPI_MFPH PI14 setting for GPIO \hideinitializer */
-
-//GPI_MFPH_PI15MFP
-#define SYS_GPI_MFPH_PI15MFP_GPIO (0x0UL<<SYS_GPI_MFPH_PI15MFP_Pos) /*!< GPI_MFPH PI15 setting for GPIO \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_SYS_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
- @{
-*/
-
-/**
- * @brief Clear Brown-out detector interrupt flag
- * @param None
- * @return None
- * @details This macro clear Brown-out detector interrupt flag.
- */
-#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODINTF_Msk)
-
-/**
- * @brief Set Brown-out detector function to normal mode
- * @param None
- * @return None
- * @details This macro set Brown-out detector to normal mode.
- */
-#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
-
-/**
- * @brief Disable Brown-out detector function
- * @param None
- * @return None
- * @details This macro disable Brown-out detector function.
- */
-#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk)
-
-/**
- * @brief Enable Brown-out detector function
- * @param None
- * @return None
- * @details This macro enable Brown-out detector function.
- */
-#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk)
-/**
- * @brief Get Brown-out detector interrupt flag
- * @param None
- * @retval 0 Brown-out detect interrupt flag is not set.
- * @retval >=1 Brown-out detect interrupt flag is set.
- * @details This macro get Brown-out detector interrupt flag.
- */
-#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODINTF_Msk)
-
-/**
- * @brief Get Brown-out detector status
- * @param None
- * @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0.
- * @retval >=1 System voltage is lower than BOD_VL setting.
- * @details This macro get Brown-out detector output status.
- * If the BOD_EN is 0, this function always return 0.
- */
-#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
-
-/**
- * @brief Disable Brown-out detector interrupt function
- * @param None
- * @return None
- * @details This macro enable Brown-out detector interrupt function.
- */
-#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
-
-/**
- * @brief Enable Brown-out detector reset function
- * @param None
- * @return None
- * @details This macro enable Brown-out detect reset function.
- */
-#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
-
-
-/**
- * @brief Set Brown-out detector function low power mode
- * @param None
- * @return None
- * @details This macro set Brown-out detector to low power mode.
- */
-#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
-
-/**
- * @brief Set Brown-out detector voltage level
- * @param[in] u32Level is Brown-out voltage level. Including :
- * - \ref SYS_BODCTL_BODVL_4_5V
- * - \ref SYS_BODCTL_BODVL_3_8V
- * - \ref SYS_BODCTL_BODVL_2_7V
- * - \ref SYS_BODCTL_BODVL_2_2V
- * @return None
- * @details This macro set Brown-out detector voltage level.
- */
-#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32Level)
-
-/**
- * @brief Get reset source is from Brown-out detector reset
- * @param None
- * @retval 0 Previous reset source is not from Brown-out detector reset
- * @retval >=1 Previous reset source is from Brown-out detector reset
- * @details This macro get previous reset source is from Brown-out detect reset or not.
- */
-#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
-
-/**
- * @brief Get reset source is from CPU reset
- * @param None
- * @retval 0 Previous reset source is not from CPU reset
- * @retval >=1 Previous reset source is from CPU reset
- * @details This macro get previous reset source is from CPU reset.
- */
-#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
-
-/**
- * @brief Get reset source is from LVR Reset
- * @param None
- * @retval 0 Previous reset source is not from LVR Reset
- * @retval >=1 Previous reset source is from LVR Reset
- * @details This macro get previous reset source is from Power-on Reset.
- */
-#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
-
-/**
- * @brief Get reset source is from Power-on Reset
- * @param None
- * @retval 0 Previous reset source is not from Power-on Reset
- * @retval >=1 Previous reset source is from Power-on Reset
- * @details This macro get previous reset source is from Power-on Reset.
- */
-#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
-
-/**
- * @brief Get reset source is from reset pin reset
- * @param None
- * @retval 0 Previous reset source is not from reset pin reset
- * @retval >=1 Previous reset source is from reset pin reset
- * @details This macro get previous reset source is from reset pin reset.
- */
-#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
-
-/**
- * @brief Get reset source is from system reset
- * @param None
- * @retval 0 Previous reset source is not from system reset
- * @retval >=1 Previous reset source is from system reset
- * @details This macro get previous reset source is from system reset.
- */
-#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
-
-/**
- * @brief Get reset source is from window watch dog reset
- * @param None
- * @retval 0 Previous reset source is not from window watch dog reset
- * @retval >=1 Previous reset source is from window watch dog reset
- * @details This macro get previous reset source is from window watch dog reset.
- */
-#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
-
-/**
- * @brief Disable Low-Voltage-Reset function
- * @param None
- * @return None
- * @details This macro disable Low-Voltage-Reset function.
- */
-#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk)
-
-/**
- * @brief Enable Low-Voltage-Reset function
- * @param None
- * @return None
- * @details This macro enable Low-Voltage-Reset function.
- */
-#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk)
-
-/**
- * @brief Disable Power-on Reset function
- * @param None
- * @return None
- * @details This macro disable Power-on Reset function.
- */
-#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
-
-/**
- * @brief Enable Power-on Reset function
- * @param None
- * @return None
- * @details This macro enable Power-on Reset function.
- */
-#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
-
-
-/**
- * @brief Clear reset source flag
- * @param[in] u32RstSrc is reset source. Including:
- * - \ref SYS_RSTSTS_PORF_Msk
- * - \ref SYS_RSTSTS_PINRF_Msk
- * - \ref SYS_RSTSTS_WDTRF_Msk
- * - \ref SYS_RSTSTS_LVRF_Msk
- * - \ref SYS_RSTSTS_BODRF_Msk
- * - \ref SYS_RSTSTS_SYSRF_Msk
- * - \ref SYS_RSTSTS_CPURF_Msk
- * @return None
- * @details This macro clear reset source flag.
- */
-#define SYS_CLEAR_RST_SOURCE(u32RstSrc) (SYS->RSTSTS = u32RstSrc )
-
-void SYS_ClearResetSrc(uint32_t u32Src);
-uint32_t SYS_GetBODStatus(void);
-uint32_t SYS_GetResetSrc(void);
-uint32_t SYS_IsRegLocked(void);
-void SYS_LockReg(void);
-void SYS_UnlockReg(void);
-uint32_t SYS_ReadPDID(void);
-void SYS_ResetChip(void);
-void SYS_ResetCPU(void);
-void SYS_ResetModule(uint32_t u32ModuleIndex);
-void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
-void SYS_DisableBOD(void);
-
-/*@}*/ /* end of group NUC472_442_SYS_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_SYS_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__SYS_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_timer.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,229 +0,0 @@
-/**************************************************************************//**
- * @file timer.c
- * @version V1.00
- * $Revision: 6 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 TIMER driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_TIMER_Driver TIMER Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
- @{
-*/
-
-/**
- * @brief This API is used to configure timer to operate in specified mode
- * and frequency. If timer cannot work in target frequency, a closest
- * frequency will be chose and returned.
- * @param[in] timer The base address of Timer module
- * @param[in] u32Mode Operation mode. Possible options are
- * - \ref TIMER_ONESHOT_MODE
- * - \ref TIMER_PERIODIC_MODE
- * - \ref TIMER_TOGGLE_MODE
- * - \ref TIMER_CONTINUOUS_MODE
- * @param[in] u32Freq Target working frequency
- * @return Real Timer working frequency
- * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
- * \ref TIMER_Start macro or program registers directly
- */
-uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
-{
- uint32_t u32Clk = TIMER_GetModuleClock(timer);
- uint32_t u32Cmpr = 0, u32Prescale = 0;
-
- // Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
- if(u32Freq > (u32Clk / 2)) {
- u32Cmpr = 2;
- } else {
- if(u32Clk >= 0x4000000) {
- u32Prescale = 7; // real prescaler value is 8
- u32Clk >>= 3;
- } else if(u32Clk >= 0x2000000) {
- u32Prescale = 3; // real prescaler value is 4
- u32Clk >>= 2;
- } else if(u32Clk >= 0x1000000) {
- u32Prescale = 1; // real prescaler value is 2
- u32Clk >>= 1;
- }
-
- u32Cmpr = u32Clk / u32Freq;
- }
-
- timer->CTL = u32Mode | u32Prescale;
- timer->CMP = u32Cmpr;
-
- return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
-}
-
-/**
- * @brief This API stops Timer counting and disable the Timer interrupt function
- * @param[in] timer The base address of Timer module
- * @return None
- */
-void TIMER_Close(TIMER_T *timer)
-{
- timer->CTL = 0;
- timer->EXTCTL = 0;
-
-}
-
-/**
- * @brief This API is used to create a delay loop for u32usec micro seconds
- * @param[in] timer The base address of Timer module
- * @param[in] u32Usec Delay period in micro seconds with 10 usec every step. Valid values are between 10~1000000 (10 micro second ~ 1 second)
- * @return None
- * @note This API overwrites the register setting of the timer used to count the delay time.
- * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay
- */
-void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
-{
- uint32_t u32Clk = TIMER_GetModuleClock(timer);
- uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk + 1;
- double fCmpr;
-
- // Clear current timer configuration
- timer->CTL = 0;
- timer->EXTCTL = 0;
-
- if(u32Clk == 10000) { // min delay is 100us if timer clock source is LIRC 10k
- u32Usec = ((u32Usec + 99) / 100) * 100;
- } else { // 10 usec every step
- u32Usec = ((u32Usec + 9) / 10) * 10;
- }
-
- if(u32Clk >= 0x4000000) {
- u32Prescale = 7; // real prescaler value is 8
- u32Clk >>= 3;
- } else if(u32Clk >= 0x2000000) {
- u32Prescale = 3; // real prescaler value is 4
- u32Clk >>= 2;
- } else if(u32Clk >= 0x1000000) {
- u32Prescale = 1; // real prescaler value is 2
- u32Clk >>= 1;
- }
-
- // u32Usec * u32Clk might overflow if using uint32_t
- fCmpr = ((double)u32Usec * (double)u32Clk) / 1000000.0;
-
- timer->CMP = (uint32_t)fCmpr;
- timer->CTL = TIMER_CTL_CNTEN_Msk | u32Prescale; // one shot mode
-
- // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
- // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
- for(; delay > 0; delay--) {
- __NOP();
- }
-
- while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
-
-}
-
-/**
- * @brief This API is used to enable timer capture function with specified mode and capture edge
- * @param[in] timer The base address of Timer module
- * @param[in] u32CapMode Timer capture mode. Could be
- * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
- * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
- * @param[in] u32Edge Timer capture edge. Possible values are
- * - \ref TIMER_CAPTURE_FALLING_EDGE
- * - \ref TIMER_CAPTURE_RISING_EDGE
- * - \ref TIMER_CAPTURE_FALLING_THEN_RISING_EDGE
- * - \ref TIMER_CAPTURE_RISING_THEN_FALLING_EDGE
- * @return None
- * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly
- */
-void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
-{
-
- timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk |
- TIMER_EXTCTL_CAPEDGE_Msk)) |
- u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
-}
-
-/**
- * @brief This API is used to disable the Timer capture function
- * @param[in] timer The base address of Timer module
- * @return None
- */
-void TIMER_DisableCapture(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
-
-}
-
-/**
- * @brief This function is used to enable the Timer counter function with specify detection edge
- * @param[in] timer The base address of Timer module
- * @param[in] u32Edge Detection edge of counter pin. Could be ether
- * - \ref TIMER_COUNTER_RISING_EDGE, or
- * - \ref TIMER_COUNTER_FALLING_EDGE
- * @return None
- * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
- * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
- */
-void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
-{
- timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
- timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
-}
-
-/**
- * @brief This API is used to disable the Timer event counter function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-void TIMER_DisableEventCounter(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
-}
-
-/**
- * @brief This API is used to get the clock frequency of Timer
- * @param[in] timer The base address of Timer module
- * @return Timer clock frequency
- * @note This API cannot return correct clock rate if timer source is external clock input.
- */
-uint32_t TIMER_GetModuleClock(TIMER_T *timer)
-{
- uint32_t u32Src;
- const uint32_t au32Clk[] = {__HXT, __LXT, 0, 0, 0, __LIRC, 0, __HIRC};
-
- if(timer == TIMER0)
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
- else if(timer == TIMER1)
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
- else if(timer == TIMER2)
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
- else // Timer 3
- u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
-
- if(u32Src == 2) {
- if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLKSEL_Msk)
- return(SystemCoreClock / 2);
- else
- return(SystemCoreClock);
- }
-
- return(au32Clk[u32Src]);
-
-}
-
-/*@}*/ /* end of group NUC472_442_TIMER_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_TIMER_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_timer.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,325 +0,0 @@
-/**************************************************************************//**
- * @file timer.h
- * @version V1.00
- * $Revision: 6 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 TIMER driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __TIMER_H__
-#define __TIMER_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_TIMER_Driver TIMER Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
- @{
-*/
-
-#define TIMER_ONESHOT_MODE (0UL) /*!< Timer working in one shot mode \hideinitializer */
-#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */
-#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle mode \hideinitializer */
-#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous mode \hideinitializer */
-#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL) /*!< Free counting mode \hideinitializer */
-#define TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk) /*!< Counter reset mode \hideinitializer */
-#define TIMER_CAPTURE_FALLING_EDGE (0UL) /*!< Falling edge trigger timer capture \hideinitializer */
-#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge trigger timer capture \hideinitializer */
-#define TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge then rising edge trigger timer capture \hideinitializer */
-#define TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge then falling edge trigger timer capture \hideinitializer */
-#define TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk) /*!< Counter increase on rising edge \hideinitializer */
-#define TIMER_COUNTER_FALLING_EDGE (0UL) /*!< Counter increase on falling edge \hideinitializer */
-#define TIMER_TOGGLE_OUT1 (TIMER_CTL_TOGDIS2_Msk) /*!< Select PB.4, PB.1, PC.6, PC.1 as timer toggle output pin \hideinitializer */
-#define TIMER_TOGGLE_OUT2 (TIMER_CTL_TOGDIS1_Msk) /*!< Select PD.1, PE.8, PE.1, PD.11 as timer toggle output pin \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_TIMER_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
- @{
-*/
-
-/**
- * @brief This macro is used to set new Timer compared value
- * @param[in] timer The base address of Timer module
- * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF
- * @return None
- * \hideinitializer
- */
-#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
-
-/**
- * @brief This macro is used to set new Timer prescale value
- * @param[in] timer The base address of Timer module
- * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF
- * @return None
- * @note Clock input is divided by (prescale + 1) before it is fed into timer
- * \hideinitializer
- */
-#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
-
-/**
- * @brief This macro is used to check if specify Timer is inactive or active
- * @return timer is activate or inactivate
- * @retval 0 Timer 24-bit up counter is inactive
- * @retval 1 Timer 24-bit up counter is active
- * \hideinitializer
- */
-#define TIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
-
-/**
- * @brief This macro is used to select Timer toggle output pin
- * @param[in] timer The base address of Timer module
- * @param[in] u32ToutSel Toggle output pin selection, valid values are
- * - \ref TIMER_TOGGLE_OUT1
- * - \ref TIMER_TOGGLE_OUT2
- * @return None
- * \hideinitializer
- */
-#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~(TIMER_CTL_TOGDIS2_Msk | TIMER_CTL_TOGDIS1_Msk)) | (u32ToutSel))
-
-
-/**
- * @brief This function is used to start Timer counting
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
-{
- timer->CTL |= TIMER_CTL_CNTEN_Msk;
-}
-
-/**
- * @brief This function is used to stop Timer counting
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
-}
-
-/**
- * @brief This function is used to enable the Timer wake-up function
- * @param[in] timer The base address of Timer module
- * @return None
- * @note To wake the system from power down mode, timer clock source must be ether LXT or LIRC
- */
-__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
-{
- timer->CTL |= TIMER_CTL_WKEN_Msk;
-}
-
-/**
- * @brief This function is used to disable the Timer wake-up function
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_WKEN_Msk;
-}
-
-
-/**
- * @brief This function is used to enable the capture pin detection de-bounce function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
-{
- timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
-}
-
-/**
- * @brief This function is used to disable the capture pin detection de-bounce function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
-}
-
-
-/**
- * @brief This function is used to enable the counter pin detection de-bounce function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
-{
- timer->EXTCTL |= TIMER_EXTCTL_ECNTDBEN_Msk;
-}
-
-/**
- * @brief This function is used to disable the counter pin detection de-bounce function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_ECNTDBEN_Msk;
-}
-
-/**
- * @brief This function is used to enable the Timer time-out interrupt function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
-{
- timer->CTL |= TIMER_CTL_INTEN_Msk;
-}
-
-/**
- * @brief This function is used to disable the Timer time-out interrupt function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
-{
- timer->CTL &= ~TIMER_CTL_INTEN_Msk;
-}
-
-/**
- * @brief This function is used to enable the Timer capture trigger interrupt function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
-{
- timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
-}
-
-/**
- * @brief This function is used to disable the Timer capture trigger interrupt function.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
-{
- timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
-}
-
-/**
- * @brief This function indicates Timer time-out interrupt occurred or not.
- * @param[in] timer The base address of Timer module
- * @return Timer time-out interrupt occurred or not
- * @retval 0 Timer time-out interrupt did not occur
- * @retval 1 Timer time-out interrupt occurred
- */
-__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
-{
- return(timer->INTSTS & TIMER_INTSTS_TIF_Msk ? 1 : 0);
-}
-
-/**
- * @brief This function clears the Timer time-out interrupt flag.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
-{
- timer->INTSTS = TIMER_INTSTS_TIF_Msk;
-}
-
-/**
- * @brief This function indicates Timer capture interrupt occurred or not.
- * @param[in] timer The base address of Timer module
- * @return Timer capture interrupt occurred or not
- * @retval 0 Timer capture interrupt did not occur
- * @retval 1 Timer capture interrupt occurred
- */
-__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
-{
- return timer->EINTSTS;
-}
-
-/**
- * @brief This function clears the Timer capture interrupt flag.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
-{
- timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
-}
-
-/**
- * @brief This function indicates Timer has waked up system or not.
- * @param[in] timer The base address of Timer module
- * @return Timer has waked up system or not
- * @retval 0 Timer did not wake up system
- * @retval 1 Timer wake up system
- */
-__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
-{
- return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
-}
-
-/**
- * @brief This function clears the Timer wakeup interrupt flag.
- * @param[in] timer The base address of Timer module
- * @return None
- */
-__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
-{
- timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
-}
-
-/**
- * @brief This function gets the Timer capture data.
- * @param[in] timer The base address of Timer module
- * @return Timer capture data value
- */
-__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
-{
- return timer->CAP;
-}
-
-/**
- * @brief This function reports the current timer counter value.
- * @param[in] timer The base address of Timer module
- * @return Timer counter value
- */
-__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
-{
- return timer->CNT;
-}
-
-uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
-void TIMER_Close(TIMER_T *timer);
-void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
-void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
-void TIMER_DisableCapture(TIMER_T *timer);
-void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
-void TIMER_DisableEventCounter(TIMER_T *timer);
-uint32_t TIMER_GetModuleClock(TIMER_T *timer);
-
-
-/*@}*/ /* end of group NUC472_442_TIMER_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_TIMER_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__TIMER_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_uart.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,333 +0,0 @@
-/**************************************************************************//**
- * @file uart.c
- * @version V1.00
- * $Revision: 13 $
- * $Date: 14/10/03 1:55p $
- * @brief NUC472/NUC442 UART driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include <stdio.h>
-#include "NUC472_442.h"
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* Includes of local headers */
-/*---------------------------------------------------------------------------------------------------------*/
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_UART_Driver UART Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_UART_EXPORTED_FUNCTIONS UART Exported Functions
- @{
-*/
-
-
-/**
- * @brief The function is used to clear UART specified interrupt flag.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32InterruptFlag The specified interrupt of UART module..
- *
- * @return None
- */
-void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
-{
- if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) { /* clear Receive Line Status Interrupt */
- uart->FIFOSTS |= UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk;
- uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk;
- }
-
- if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* clear Modem Interrupt */
- uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
-
- if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) { /* clear Buffer Error Interrupt */
- uart->FIFOSTS |= UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
- }
-
- if(u32InterruptFlag & UART_INTSTS_RXTOINT_Msk) /* clear Modem Interrupt */
- uart->INTSTS |= UART_INTSTS_RXTOIF_Msk;
-
-}
-
-
-/**
- * @brief The function is used to disable UART.
- *
- * @param[in] uart The base address of UART module.
- *
- * @return None
- */
-void UART_Close(UART_T* uart)
-{
- uart->INTEN = 0;
-}
-
-
-/**
- * @brief The function is used to disable UART auto flow control.
- *
- * @param[in] uart The base address of UART module.
- *
- * @return None
- */
-void UART_DisableFlowCtrl(UART_T* uart)
-{
- uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
-}
-
-
-/**
- * @brief The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32InterruptFlag The specified interrupt of UART module.
- * - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
- * - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
- *
- * @return None
- */
-void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag )
-{
- uart->INTEN &= ~ u32InterruptFlag;
-}
-
-
-
-/**
- * @brief The function is used to Enable UART auto flow control.
- *
- * @param[in] uart The base address of UART module.
- *
- * @return None
- */
-void UART_EnableFlowCtrl(UART_T* uart )
-{
- uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
- uart->MODEM &= UART_MODEM_RTS_Msk;
- uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
- uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
-}
-
-
-/**
- * @brief The function is used to enable UART specified interrupt and disable NVIC UART IRQ.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32InterruptFlag The specified interrupt of UART module:
- * - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
- * - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
- *
- * @return None
- */
-void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag )
-{
- uart->INTEN |= u32InterruptFlag;
-}
-
-
-/**
- * @brief This function use to enable UART function and set baud-rate.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32baudrate The baudrate of UART module.
- *
- * @return None
- */
-void UART_Open(UART_T* uart, uint32_t u32baudrate)
-{
- uint8_t u8UartClkSrcSel;
- uint32_t u32ClkTbl[4] = {__HXT, 0, __HIRC, __HIRC};
- uint32_t u32Clk;
- uint32_t u32Baud_Div;
-
- u32ClkTbl[1] = CLK_GetPLLClockFreq();;
-
- u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
-
- uart->FUNCSEL = UART_FUNCSEL_UART;
- uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
- uart->FIFO = UART_FIFO_RFITL_1BYTE | UART_FIFO_RTSTRGLV_1BYTE;
-
- u32Clk = (u32ClkTbl[u8UartClkSrcSel]) / (((CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos) + 1);
-
- if(u32baudrate != 0) {
- u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32Clk, u32baudrate);
-
- if(u32Baud_Div > 0xFFFF)
- uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32baudrate));
- else
- uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
- }
-}
-
-
-/**
- * @brief The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
- *
- * @param[in] uart The base address of UART module.
- * @param[out] pu8RxBuf The buffer to receive the data of receive FIFO.
- * @param[in] u32ReadBytes The the read bytes number of data.
- *
- * @return u32Count: Receive byte count
- *
- */
-uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
-{
- uint32_t u32Count;
-
- for(u32Count=0; u32Count < u32ReadBytes; u32Count++) {
- if(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) { /* Check RX empty => failed */
- return u32Count;
- }
- pu8RxBuf[u32Count] = uart->DAT; /* Get Data from UART RX */
- }
-
- return u32Count;
-}
-
-
-/**
- * @brief This function use to config UART line setting.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32baudrate The register value of baudrate of UART module.
- * if u32baudrate = 0, UART baudrate will not change.
- * @param[in] u32data_width The data length of UART module. [ \ref UART_WORD_LEN_5 / \ref UART_WORD_LEN_6 / \ref UART_WORD_LEN_7 / \ref UART_WORD_LEN_8]
- * @param[in] u32parity The parity setting (odd/even/none) of UART module. [ \ref UART_PARITY_NONE / \ref UART_PARITY_ODD /
- * \ref UART_PARITY_EVEN / \ref UART_PARITY_MARK / \ref UART_PARITY_SPACE]
- * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. [ \ref UART_STOP_BIT_1 / \ref UART_STOP_BIT_1_5 / \ref UART_STOP_BIT_2]
- *
- * @return None
- */
-void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
-{
- uint8_t u8UartClkSrcSel;
- uint32_t u32ClkTbl[4] = {__HXT, 0, __HIRC, __HIRC};
- uint32_t u32Clk;
- uint32_t u32Baud_Div = 0;
-
- u32ClkTbl[1] = CLK_GetPLLClockFreq();
-
- u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
-
- u32Clk = (u32ClkTbl[u8UartClkSrcSel]) / (((CLK->CLKDIV0 & CLK_CLKDIV0_UARTDIV_Msk) >> CLK_CLKDIV0_UARTDIV_Pos) + 1);
-
- if(u32baudrate != 0) {
- u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32Clk, u32baudrate);
-
- if(u32Baud_Div > 0xFFFF)
- uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32baudrate));
- else
- uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
- }
-
- uart->LINE = u32data_width | u32parity | u32stop_bits;
-}
-
-
-/**
- * @brief This function use to set Rx timeout count.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32TOC Rx timeout counter.
- *
- * @return None
- */
-void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
-{
- uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk)| (u32TOC);
- uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
-}
-
-
-/**
- * @brief The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32Buadrate The baudrate of UART module.
- * @param[in] u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode.
- *
- * @return None
- */
-void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
-{
- uart->BAUD = UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(12000000, 57600);
-
- uart->IRDA &= ~UART_IRDA_TXINV_Msk;
- uart->IRDA |= UART_IRDA_RXINV_Msk;
- uart->IRDA = u32Direction ? uart->IRDA | UART_IRDA_TXEN_Msk : uart->IRDA &~ UART_IRDA_TXEN_Msk;
- uart->FUNCSEL = (0x2 << UART_FUNCSEL_FUNCSEL_Pos);
-}
-
-
-/**
- * @brief The function is used to set RS485 relative setting.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u32Mode The operation mode( \ref UART_ALTCTL_RS485NMM_Msk / \ref UART_ALTCTL_RS485AUD_Msk / \ref UART_ALTCTL_RS485AAD_Msk).
- * @param[in] u32Addr The RS485 address.
- *
- * @return None
- */
-void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
-{
- uart->FUNCSEL = UART_FUNCSEL_RS485;
- uart->ALTCTL = 0;
- uart->ALTCTL |= u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos);
-}
-
-
-/**
- * @brief The function is to write data into TX buffer to transmit data by UART.
- *
- * @param[in] uart The base address of UART module.
- * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
- * @param[in] u32WriteBytes The byte number of data.
- *
- * @return u32Count: transfer byte count
- */
-uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
-{
- uint32_t u32Count;
-
- for(u32Count=0; u32Count != u32WriteBytes; u32Count++) {
- if(uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) { /* Wait Tx empty and Time-out manner */
- return u32Count;
- }
- uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
- }
-
- return u32Count;
-}
-
-
-/*@}*/ /* end of group NUC472_442_UART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_UART_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_uart.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,400 +0,0 @@
-/**************************************************************************//**
- * @file uart.h
- * @version V1.00
- * $Revision: 19 $
- * $Date: 14/10/07 9:28a $
- * @brief NUC472/NUC442 UART driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-
-#ifndef __UART_H__
-#define __UART_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_UART_Driver UART Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_UART_EXPORTED_CONSTANTS UART Exported Constants
- @{
-*/
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_FCR constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-
-#define UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */
-#define UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */
-#define UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */
-#define UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */
-
-#define UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */
-#define UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */
-#define UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */
-#define UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_LCR constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_WORD_LEN_5 (0) /*!< UART_LINE setting to set UART word length to 5 bits */
-#define UART_WORD_LEN_6 (1) /*!< UART_LINE setting to set UART word length to 6 bits */
-#define UART_WORD_LEN_7 (2) /*!< UART_LINE setting to set UART word length to 7 bits */
-#define UART_WORD_LEN_8 (3) /*!< UART_LINE setting to set UART word length to 8 bits */
-
-#define UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */
-#define UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */
-#define UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
-#define UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
-#define UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
-
-#define UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
-#define UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
-#define UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
-
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART RTS LEVEL TRIGGER constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Trigger */
-#define UART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Trigger */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART CTS LEVEL TRIGGER constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_CTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEMSTS_CTSACTLV_Pos) /*!< Set CTS is High Level Trigger */
-#define UART_CTS_IS_LOW_LEV_TRG (0x0 << UART_MODEMSTS_CTSACTLV_Pos) /*!< Set CTS is Low Level Trigger */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART_FUNC_SEL constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_FUNCSEL_UART (0x0 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
-#define UART_FUNCSEL_IrDA (0x2 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
-#define UART_FUNCSEL_RS485 (0x3 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
-
-/*---------------------------------------------------------------------------------------------------------*/
-/* UART BAUDRATE MODE constants definitions */
-/*---------------------------------------------------------------------------------------------------------*/
-#define UART_BAUD_MODE0 (0) /*!< Set UART Baudrate Mode is Mode0 */
-#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */
-
-
-
-/*@}*/ /* end of group NUC472_442_UART_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_UART_EXPORTED_FUNCTIONS UART Exported Functions
- @{
-*/
-
-
-/**
- * @brief Calculate UART baudrate mode0 divider
- *
- * @param[in] u32SrcFreq UART clock frequency
- * @param[in] u32BaudRate Baudrate of UART module
- *
- * @return UART baudrate mode0 divider
- * \hideinitializer
- *
- */
-#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
-
-/**
- * @brief Calculate UART baudrate mode2 divider
- *
- * @param[in] u32SrcFreq UART clock frequency
- * @param[in] u32BaudRate Baudrate of UART module
- *
- * @return UART baudrate mode2 divider
- * \hideinitializer
- */
-#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
-
-
-/**
- * @brief Write Data to Tx data register
- *
- * @param[in] uart The base address of UART module.
- * @param[in] u8Data Data byte to transmit
- *
- * @return None
- * \hideinitializer
- */
-#define UART_WRITE(uart, u8Data) (uart->DAT = (u8Data))
-
-/**
- * @brief Read Rx data register
- *
- * @param[in] uart The base address of UART module.
- *
- * @return The oldest data byte in RX FIFO
- * \hideinitializer
- */
-#define UART_READ(uart) (uart->DAT)
-
-
-/**
- * @brief Get Tx empty register value.
- *
- * @param[in] uart The base address of UART module
- *
- * @return Tx empty register value.
- * \hideinitializer
- */
-#define UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
-
-
-/**
- * @brief Get Rx empty register value.
- *
- * @param[in] uart The base address of UART module
- *
- * @return Rx empty register value.
- * \hideinitializer
- */
-#define UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
-
-/**
- * @brief Check specified uart port transmission is over.
- *
- * @param[in] uart The base address of UART module
- *
- * @return TE_Flag.
- * \hideinitializer
- */
-#define UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
-
-
-/**
- * @brief Wait specified uart port transmission is over
- *
- * @param[in] uart The base address of UART module
- *
- * @return None
- * \hideinitializer
- */
-#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
-
-/**
- * @brief Check RDA_IF is set or not
- *
- * @param[in] uart The base address of UART module
- *
- * @return
- * 0 : The number of bytes in the RX FIFO is less than the RFITL
- * 1 : The number of bytes in the RX FIFO equals or larger than RFITL
- * \hideinitializer
- */
-#define UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
-
-
-/**
- * @brief Check TX FIFO is full or not
- *
- * @param[in] uart The base address of UART module
- *
- * @return
- * 1 = TX FIFO is full
- * 0 = TX FIFO is not full
- * \hideinitializer
- */
-#define UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
-
-/**
- * @brief Check RX FIFO is full or not
- *
- * @param[in] uart The base address of UART module
- *
- * @return
- * 1 = RX FIFO is full
- * 0 = RX FIFO is not full
- * \hideinitializer
- *
- */
-#define UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
-
-
-/**
- * @brief Get Tx full register value
- *
- * @param[in] uart The base address of UART module
- *
- * @return Tx full register value
- * \hideinitializer
- */
-#define UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
-
-
-/**
- * @brief Get Rx full register value
- *
- * @param[in] uart The base address of UART module
- *
- * @return Rx full register value
- * \hideinitializer
- */
-#define UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
-
-
-/**
- * @brief Enable specified interrupt
- *
- * @param[in] uart The base address of UART module
- * @param[in] u32eIntSel Interrupt type select
- * - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
- * - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
- *
- * @return None
- * \hideinitializer
- */
-#define UART_ENABLE_INT(uart, u32eIntSel) (uart->INTEN |= (u32eIntSel))
-
-
-/**
- * @brief Disable specified interrupt
- *
- * @param[in] uart The base address of UART module
- * @param[in] u32eIntSel Interrupt type select
- * - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
- * - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
- * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
- * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
- * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
- * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
- * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
- * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
- * @return None
- * \hideinitializer
- */
-#define UART_DISABLE_INT(uart, u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
-
-
-/**
- * @brief Get specified interrupt flag/status
- *
- * @param[in] uart The base address of UART module
- * @param[in] u32eIntTypeFlag Interrupt type select
- * - \ref UART_INTSTS_HWBUFEINT_Msk : In DMA Mode, Buffer Error Interrupt Indicator.
- * - \ref UART_INTSTS_HWTOINT_Msk : In DMA Mode, Time-out Interrupt Indicator.
- * - \ref UART_INTSTS_HWMODINT_Msk : In DMA Mode, MODEM Status Interrupt Indicator.
- * - \ref UART_INTSTS_HWRLSINT_Msk : In DMA Mode, Receive Line Status Interrupt Indicator.
- * - \ref UART_INTSTS_HWBUFEIF_Msk : In DMA Mode, Buffer Error Interrupt Flag.
- * - \ref UART_INTSTS_HWTOIF_Msk : In DMA Mode, Time-out Interrupt Flag.
- * - \ref UART_INTSTS_HWMODIF_Msk : In DMA Mode, MODEM Interrupt Flag.
- * - \ref UART_INTSTS_HWRLSIF_Msk : In DMA Mode, Receive Line Status Flag.
- * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator.
- * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator.
- * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator.
- * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator.
- * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator.
- * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator.
- * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator.
- * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag.
- * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
- * - \ref UART_INTSTS_RXTOIF_Msk : Rx time-out interrupt Flag
- * - \ref UART_INTSTS_MODENIF_Msk : Modem interrupt Flag
- * - \ref UART_INTSTS_RLSIF_Msk : Rx Line status interrupt Flag
- * - \ref UART_INTSTS_THREIF_Msk : Tx empty interrupt Flag
- * - \ref UART_INTSTS_RDAIF_Msk : Rx ready interrupt Flag
- *
- * @return
- * 0 = The specified interrupt is not happened.
- * 1 = The specified interrupt is happened.
- * \hideinitializer
- */
-#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
-
-
-/**
- * @brief Set RTS pin is low
- *
- * @param[in] uart The base address of UART module
- * @return None
- */
-__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
-{
- uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
- uart->MODEM &= UART_MODEM_RTS_Msk;
-}
-
-/**
- * @brief Set RTS pin is high
- *
- * @param[in] uart The base address of UART module
- * @return None
- */
-__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
-{
- uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
-}
-
-/**
- * @brief Clear RS-485 Address Byte Detection Flag
- *
- * @param[in] uart The base address of UART module
- * @return None
- * \hideinitializer
- */
-#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
-
-
-/**
- * @brief Get RS-485 Address Byte Detection Flag
- *
- * @param[in] uart The base address of UART module
- * @return RS-485 Address Byte Detection Flag
- * \hideinitializer
- */
-#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
-
-
-void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
-void UART_Close(UART_T* uart );
-void UART_DisableFlowCtrl(UART_T* uart );
-void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag );
-void UART_EnableFlowCtrl(UART_T* uart );
-void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag );
-void UART_Open(UART_T* uart, uint32_t u32baudrate);
-uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
-void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
-void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
-void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
-void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
-uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
-
-
-/*@}*/ /* end of group NUC472_442_UART_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_UART_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__UART_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
-
-
-
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_usbd.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,565 +0,0 @@
-/**************************************************************************//**
- * @file usbd.c
- * @version V1.00
- * $Revision: 15 $
- * $Date: 14/10/02 4:14p $
- * @brief NUC472/NUC442 USBD driver source file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_USBD_Driver USBD Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
- @{
-*/
-/*--------------------------------------------------------------------------*/
-/*!< Global variables for Control Pipe */
-S_USBD_CMD_T gUsbCmd;
-S_USBD_INFO_T *g_usbd_sInfo;
-
-VENDOR_REQ g_usbd_pfnVendorRequest = NULL;
-CLASS_REQ g_usbd_pfnClassRequest = NULL;
-SET_INTERFACE_REQ g_usbd_pfnSetInterface = NULL;
-
-static uint8_t *g_usbd_CtrlInPointer = 0;
-static uint32_t g_usbd_UsbConfig = 0;
-static uint32_t g_usbd_UsbAltInterface = 0;
-static uint32_t g_usbd_CtrlMaxPktSize = 64;
-
-#ifdef __ICCARM__
-#pragma data_alignment=4
-static uint8_t g_usbd_buf[12];
-#elif defined (__CC_ARM)
-__align(4) static uint8_t g_usbd_buf[12];
-#elif defined ( __GNUC__ )
-static uint8_t g_usbd_buf[12] __attribute__((aligned (4)));
-#endif
-
-
-uint32_t g_usbd_CtrlZero = 0;
-uint32_t g_usbd_UsbAddr = 0;
-uint32_t g_usbd_CtrlInSize = 0;
-uint32_t g_usbd_ShortPacket = 0;
-uint32_t volatile g_usbd_DmaDone = 0;
-uint32_t g_usbd_Configured = 0;
-
-/**
- * @brief USBD Initial
- *
- * @param[in] param Descriptor
- * @param[in] pfnClassReq Class Request Callback Function
- * @param[in] pfnSetInterface SetInterface Request Callback Function
- *
- * @return None
- *
- * @details This function is used to initial USBD.
- */
-void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
-{
- g_usbd_sInfo = param;
- g_usbd_pfnClassRequest = pfnClassReq;
- g_usbd_pfnSetInterface = pfnSetInterface;
-
- /* get EP0 maximum packet size */
- g_usbd_CtrlMaxPktSize = g_usbd_sInfo->gu8DevDesc[7];
-
- /* Initial USB engine */
- /* Enable PHY */
- USBD_ENABLE_PHY();
- /* wait PHY clock ready */
- while (1) {
- USBD->EPAMPS = 0x20;
- if (USBD->EPAMPS == 0x20)
- break;
- }
- /* Force SE0, and then clear it to connect*/
- USBD_SET_SE0();
-}
-
-/**
- * @brief USBD Start
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function is used to start transfer
- */
-void USBD_Start(void)
-{
- USBD_CLR_SE0();
-}
-
-/**
- * @brief Process Setup Packet
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function is used to process Setup packet.
- */
-void USBD_ProcessSetupPacket(void)
-{
- // Setup packet process
- gUsbCmd.bmRequestType = (uint8_t)(USBD->SETUP1_0 & 0xff);
- gUsbCmd.bRequest = (int8_t)(USBD->SETUP1_0 >> 8) & 0xff;
- gUsbCmd.wValue = (uint16_t)USBD->SETUP3_2;
- gUsbCmd.wIndex = (uint16_t)USBD->SETUP5_4;
- gUsbCmd.wLength = (uint16_t)USBD->SETUP7_6;
-
- /* USB device request in setup packet: offset 0, D[6..5]: 0=Standard, 1=Class, 2=Vendor, 3=Reserved */
- switch (gUsbCmd.bmRequestType & 0x60) {
- case REQ_STANDARD: { // Standard
- USBD_StandardRequest();
- break;
- }
- case REQ_CLASS: { // Class
- if (g_usbd_pfnClassRequest != NULL) {
- g_usbd_pfnClassRequest();
- }
- break;
- }
- case REQ_VENDOR: { // Vendor
- if (g_usbd_pfnVendorRequest != NULL) {
- g_usbd_pfnVendorRequest();
- }
- break;
- }
- default: { // reserved
- /* Setup error, stall the device */
- USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
- break;
- }
- }
-}
-
-/**
- * @brief Get Descriptor request
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function is used to process GetDescriptor request.
- */
-int USBD_GetDescriptor(void)
-{
- uint32_t u32Len;
-
- u32Len = gUsbCmd.wLength;
- g_usbd_CtrlZero = 0;
-
- switch ((gUsbCmd.wValue & 0xff00) >> 8) {
- // Get Device Descriptor
- case DESC_DEVICE: {
- u32Len = Minimum(u32Len, LEN_DEVICE);
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8DevDesc, u32Len);
- break;
- }
- // Get Configuration Descriptor
- case DESC_CONFIG: {
- uint32_t u32TotalLen;
-
- if (USBD->OPER & 0x04) { /* high speed */
- u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[3];
- u32TotalLen = g_usbd_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8);
-
- u32Len = Minimum(u32Len, u32TotalLen);
- if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
- g_usbd_CtrlZero = 1;
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8ConfigDesc, u32Len);
- } else { /* full speed */
- u32TotalLen = g_usbd_sInfo->gu8OtherConfigDesc[3];
- u32TotalLen = g_usbd_sInfo->gu8OtherConfigDesc[2] + (u32TotalLen << 8);
-
- u32Len = Minimum(u32Len, u32TotalLen);
- if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
- g_usbd_CtrlZero = 1;
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8OtherConfigDesc, u32Len);
- }
- break;
- }
- // Get Qualifier Descriptor
- case DESC_QUALIFIER: {
- u32Len = Minimum(u32Len, LEN_QUALIFIER);
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8QualDesc, u32Len);
- break;
- }
- // Get Other Speed Descriptor - Full speed
- case DESC_OTHERSPEED: {
- uint32_t u32TotalLen;
-
- u32TotalLen = g_usbd_sInfo->gu8OtherConfigDesc[3];
- u32TotalLen = g_usbd_sInfo->gu8OtherConfigDesc[2] + (u32TotalLen << 8);
-
- u32Len = Minimum(u32Len, u32TotalLen);
- if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
- g_usbd_CtrlZero = 1;
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8OtherConfigDesc, u32Len);
- break;
- }
- // Get HID Descriptor
- case DESC_HID: {
- u32Len = Minimum(u32Len, LEN_HID);
- USBD_MemCopy(g_usbd_buf, (uint8_t *)&g_usbd_sInfo->gu8ConfigDesc[LEN_CONFIG+LEN_INTERFACE], u32Len);
- USBD_PrepareCtrlIn(g_usbd_buf, u32Len);
- break;
- }
- // Get Report Descriptor
- case DESC_HID_RPT: {
- if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
- g_usbd_CtrlZero = 1;
-
- switch (gUsbCmd.wIndex & 0xff) {
- case 0: {
- u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[0]);
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[0], u32Len);
- break;
- }
- case 1: {
- u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[1]);
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[1], u32Len);
- break;
- }
- case 2: {
- u32Len = Minimum(u32Len, g_usbd_sInfo->gu32HidReportSize[2]);
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8HidReportDesc[2], u32Len);
- break;
- }
- }
- break;
- }
- // Get String Descriptor
- case DESC_STRING: {
- // Get Language
- if ((gUsbCmd.wValue & 0xff) == 0) {
- u32Len = Minimum(u32Len, 4);
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StrLangDesc, u32Len);
- } else {
- // Get String Descriptor
- switch (gUsbCmd.wValue & 0xff) {
- case 1: {
- u32Len = Minimum(u32Len, g_usbd_sInfo->gu8StrVendorDesc[0]);
- if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
- g_usbd_CtrlZero = 1;
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StrVendorDesc, u32Len);
- break;
- }
- case 2: {
- u32Len = Minimum(u32Len, g_usbd_sInfo->gu8StrProductDesc[0]);
- if ((u32Len % g_usbd_CtrlMaxPktSize) == 0)
- g_usbd_CtrlZero = 1;
-
- USBD_PrepareCtrlIn((uint8_t *)g_usbd_sInfo->gu8StrProductDesc, u32Len);
- break;
- }
- default:
- // Not support. Reply STALL.
- USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
- return 1;
- }
- }
- break;
- }
- default:
- // Not support. Reply STALL.
- USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
- return 1;
- }
- return 0;
-}
-
-
-/**
- * @brief Process USB standard request
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function is used to process USB Standard Request.
- */
-void USBD_StandardRequest(void)
-{
- /* clear global variables for new request */
- g_usbd_CtrlInPointer = 0;
- g_usbd_CtrlInSize = 0;
-
- if (gUsbCmd.bmRequestType & 0x80) { /* request data transfer direction */
- // Device to host
- switch (gUsbCmd.bRequest) {
- case GET_CONFIGURATION: {
- // Return current configuration setting
- USBD_PrepareCtrlIn((uint8_t *)&g_usbd_UsbConfig, 1);
-
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
- break;
- }
- case GET_DESCRIPTOR: {
- if (!USBD_GetDescriptor()) {
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
- }
- break;
- }
- case GET_INTERFACE: {
- // Return current interface setting
- USBD_PrepareCtrlIn((uint8_t *)&g_usbd_UsbAltInterface, 1);
-
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
- break;
- }
- case GET_STATUS: {
- // Device
- if (gUsbCmd.bmRequestType == 0x80) {
- if (g_usbd_sInfo->gu8ConfigDesc[7] & 0x40)
- g_usbd_buf[0] = 1; // Self-Powered
- else
- g_usbd_buf[0] = 0; // bus-Powered
- }
- // Interface
- else if (gUsbCmd.bmRequestType == 0x81)
- g_usbd_buf[0] = 0;
- // Endpoint
- else if (gUsbCmd.bmRequestType == 0x82) {
- uint8_t ep = gUsbCmd.wIndex & 0xF;
- g_usbd_buf[0] = USBD_GetStall(ep)? 1 : 0;
- }
- g_usbd_buf[1] = 0;
- USBD_PrepareCtrlIn(g_usbd_buf, 2);
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_INTKIF_Msk);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_INTKIEN_Msk);
- break;
- }
- default: {
- /* Setup error, stall the device */
- USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
- break;
- }
- }
- } else {
- // Host to device
- switch (gUsbCmd.bRequest) {
- case CLEAR_FEATURE: {
- /* Status stage */
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
- USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
- break;
- }
- case SET_ADDRESS: {
- g_usbd_UsbAddr = (uint8_t)gUsbCmd.wValue;
-
- // DATA IN for end of setup
- /* Status Stage */
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
- USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
- break;
- }
- case SET_CONFIGURATION: {
- g_usbd_UsbConfig = (uint8_t)gUsbCmd.wValue;
- g_usbd_Configured = 1;
- // DATA IN for end of setup
- /* Status stage */
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
- USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
- break;
- }
- case SET_FEATURE: {
- /* Status stage */
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
- USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
- break;
- }
- case SET_INTERFACE: {
- g_usbd_UsbAltInterface = (uint8_t)gUsbCmd.wValue;
- if (g_usbd_pfnSetInterface != NULL)
- g_usbd_pfnSetInterface(g_usbd_UsbAltInterface);
- /* Status stage */
- USBD_CLR_CEP_INT_FLAG(USBD_CEPINTSTS_STSDONEIF_Msk);
- USBD_SET_CEP_STATE(USB_CEPCTL_NAKCLR);
- USBD_ENABLE_CEP_INT(USBD_CEPINTEN_STSDONEIEN_Msk);
- break;
- }
- default: {
- /* Setup error, stall the device */
- USBD_SET_CEP_STATE(USBD_CEPCTL_STALLEN_Msk);
- break;
- }
- }
- }
-}
-
-/**
- * @brief Update Device State
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function is used to update Device state when Setup packet complete
- */
-void USBD_UpdateDeviceState(void)
-{
- switch (gUsbCmd.bRequest) {
- case SET_ADDRESS: {
- USBD_SET_ADDR(g_usbd_UsbAddr);
- break;
- }
- case SET_FEATURE: {
- if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT)
- USBD_SetStall(gUsbCmd.wIndex & 0xF);
- break;
- }
- case CLEAR_FEATURE: {
- if(gUsbCmd.wValue == FEATURE_ENDPOINT_HALT)
- USBD_ClearStall(gUsbCmd.wIndex & 0xF);
- break;
- }
- default:
- ;
- }
-}
-
-
-/**
- * @brief Prepare Control IN transaction
- *
- * @param[in] pu8Buf Control IN data pointer
- * @param[in] u32Size IN transfer size
- *
- * @return None
- *
- * @details This function is used to prepare Control IN transfer
- */
-void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size)
-{
- g_usbd_CtrlInPointer = pu8Buf;
- g_usbd_CtrlInSize = u32Size;
-}
-
-
-
-/**
- * @brief Start Control IN transfer
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function is used to start Control IN
- */
-void USBD_CtrlIn(void)
-{
- int volatile i;
- uint32_t volatile count;
-
- // Process remained data
- if(g_usbd_CtrlInSize >= g_usbd_CtrlMaxPktSize) {
- // Data size > MXPLD
- for (i=0; i<(g_usbd_CtrlMaxPktSize >> 2); i++, g_usbd_CtrlInPointer+=4)
- USBD->CEPDAT = *(uint32_t *)g_usbd_CtrlInPointer;
- USBD_START_CEP_IN(g_usbd_CtrlMaxPktSize);
- g_usbd_CtrlInSize -= g_usbd_CtrlMaxPktSize;
- } else {
- // Data size <= MXPLD
- for (i=0; i<(g_usbd_CtrlInSize >> 2); i++, g_usbd_CtrlInPointer+=4)
- USBD->CEPDAT = *(uint32_t *)g_usbd_CtrlInPointer;
-
- count = g_usbd_CtrlInSize % 4;
- for (i=0; i<count; i++)
- USBD->CEPDAT_BYTE = *(uint8_t *)(g_usbd_CtrlInPointer + i);
-
- USBD_START_CEP_IN(g_usbd_CtrlInSize);
- g_usbd_CtrlInPointer = 0;
- g_usbd_CtrlInSize = 0;
- }
-}
-
-/**
- * @brief Start Control OUT transaction
- *
- * @param[in] pu8Buf Control OUT data pointer
- * @param[in] u32Size OUT transfer size
- *
- * @return None
- *
- * @details This function is used to start Control OUT transfer
- */
-void USBD_CtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
-{
- int volatile i;
-
- while(1) {
- if (USBD->CEPINTSTS & USBD_CEPINTSTS_RXPKIF_Msk) {
- for (i=0; i<u32Size; i++)
- *(uint8_t *)(pu8Buf + i) = USBD->CEPDAT_BYTE;
- USBD->CEPINTSTS = USBD_CEPINTSTS_RXPKIF_Msk;
- break;
- }
- }
-}
-
-/**
- * @brief Clear all software flags
- *
- * @param[in] None
- *
- * @return None
- *
- * @details This function is used to clear all software control flag
- */
-void USBD_SwReset(void)
-{
- // Reset all variables for protocol
- g_usbd_UsbAddr = 0;
- g_usbd_DmaDone = 0;
- g_usbd_ShortPacket = 0;
- g_usbd_Configured = 0;
-
- // Reset USB device address
- USBD_SET_ADDR(0);
-}
-
-/**
- * @brief USBD Set Vendor Request
- *
- * @param[in] pfnVendorReq Vendor Request Callback Function
- *
- * @return None
- *
- * @details This function is used to set USBD vendor request callback function
- */
-void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
-{
- g_usbd_pfnVendorRequest = pfnVendorReq;
-}
-
-
-/*@}*/ /* end of group NUC472_442_GPIO_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_GPIO_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_usbd.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,395 +0,0 @@
-/**************************************************************************//**
- * @file usbd.h
- * @version V1.00
- * $Revision: 21 $
- * $Date: 14/10/06 1:29p $
- * @brief NUC472/NUC442 USBD driver header file
- *
- * @note
- * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __USBD_H__
-#define __USBD_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_USBD_Driver USBD Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_USBD_EXPORTED_CONSTANTS USBD Exported Constants
- @{
-*/
-/// @cond HIDDEN_SYMBOLS
-#define USBD_MAX_EP 12
-
-#define Maximum(a,b) (a)>(b) ? (a) : (b)
-#define Minimum(a,b) (a)<(b) ? (a) : (b)
-
-
-#define CEP 0xff /*!< Control Endpoint \hideinitializer */
-#define EPA 0 /*!< Endpoint A \hideinitializer */
-#define EPB 1 /*!< Endpoint B \hideinitializer */
-#define EPC 2 /*!< Endpoint C \hideinitializer */
-#define EPD 3 /*!< Endpoint D \hideinitializer */
-#define EPE 4 /*!< Endpoint E \hideinitializer */
-#define EPF 5 /*!< Endpoint F \hideinitializer */
-#define EPG 6 /*!< Endpoint G \hideinitializer */
-#define EPH 7 /*!< Endpoint H \hideinitializer */
-#define EPI 8 /*!< Endpoint I \hideinitializer */
-#define EPJ 9 /*!< Endpoint J \hideinitializer */
-#define EPK 10 /*!< Endpoint K \hideinitializer */
-#define EPL 11 /*!< Endpoint L \hideinitializer */
-
-/* USB Request Type */
-#define REQ_STANDARD 0x00
-#define REQ_CLASS 0x20
-#define REQ_VENDOR 0x40
-
-/* USB Standard Request */
-#define GET_STATUS 0x00
-#define CLEAR_FEATURE 0x01
-#define SET_FEATURE 0x03
-#define SET_ADDRESS 0x05
-#define GET_DESCRIPTOR 0x06
-#define SET_DESCRIPTOR 0x07
-#define GET_CONFIGURATION 0x08
-#define SET_CONFIGURATION 0x09
-#define GET_INTERFACE 0x0A
-#define SET_INTERFACE 0x0B
-#define SYNC_FRAME 0x0C
-
-/* USB Descriptor Type */
-#define DESC_DEVICE 0x01
-#define DESC_CONFIG 0x02
-#define DESC_STRING 0x03
-#define DESC_INTERFACE 0x04
-#define DESC_ENDPOINT 0x05
-#define DESC_QUALIFIER 0x06
-#define DESC_OTHERSPEED 0x07
-#define DESC_IFPOWER 0x08
-#define DESC_OTG 0x09
-
-/* USB HID Descriptor Type */
-#define DESC_HID 0x21
-#define DESC_HID_RPT 0x22
-
-/* USB Descriptor Length */
-#define LEN_DEVICE 18
-#define LEN_QUALIFIER 10
-#define LEN_CONFIG 9
-#define LEN_INTERFACE 9
-#define LEN_ENDPOINT 7
-#define LEN_OTG 5
-#define LEN_HID 9
-
-/* USB Endpoint Type */
-#define EP_ISO 0x01
-#define EP_BULK 0x02
-#define EP_INT 0x03
-
-#define EP_INPUT 0x80
-#define EP_OUTPUT 0x00
-
-/* USB Feature Selector */
-#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01
-#define FEATURE_ENDPOINT_HALT 0x00
-/// @endcond HIDDEN_SYMBOLS
-/********************* Bit definition of CEPCTL register **********************/
-#define USB_CEPCTL_NAKCLR ((uint32_t)0x00000000) /*!<NAK clear \hideinitializer */
-#define USB_CEPCTL_STALL ((uint32_t)0x00000002) /*!<Stall \hideinitializer */
-#define USB_CEPCTL_ZEROLEN ((uint32_t)0x00000004) /*!<Zero length packet \hideinitializer */
-#define USB_CEPCTL_FLUSH ((uint32_t)0x00000008) /*!<CEP flush \hideinitializer */
-
-/********************* Bit definition of EPxRSPCTL register **********************/
-#define USB_EP_RSPCTL_FLUSH ((uint32_t)0x00000001) /*!<Buffer Flush \hideinitializer */
-#define USB_EP_RSPCTL_MODE_AUTO ((uint32_t)0x00000000) /*!<Auto-Validate Mode \hideinitializer */
-#define USB_EP_RSPCTL_MODE_MANUAL ((uint32_t)0x00000002) /*!<Manual-Validate Mode \hideinitializer */
-#define USB_EP_RSPCTL_MODE_FLY ((uint32_t)0x00000004) /*!<Fly Mode \hideinitializer */
-#define USB_EP_RSPCTL_MODE_MASK ((uint32_t)0x00000006) /*!<Mode Mask \hideinitializer */
-#define USB_EP_RSPCTL_TOGGLE ((uint32_t)0x00000008) /*!<Clear Toggle bit \hideinitializer */
-#define USB_EP_RSPCTL_HALT ((uint32_t)0x00000010) /*!<Endpoint halt \hideinitializer */
-#define USB_EP_RSPCTL_ZEROLEN ((uint32_t)0x00000020) /*!<Zero length packet IN \hideinitializer */
-#define USB_EP_RSPCTL_SHORTTXEN ((uint32_t)0x00000040) /*!<Packet end \hideinitializer */
-#define USB_EP_RSPCTL_DISBUF ((uint32_t)0x00000080) /*!<Disable buffer \hideinitializer */
-
-/********************* Bit definition of EPxCFG register **********************/
-#define USB_EP_CFG_VALID ((uint32_t)0x00000001) /*!<Endpoint Valid \hideinitializer */
-#define USB_EP_CFG_TYPE_BULK ((uint32_t)0x00000002) /*!<Endpoint type - bulk \hideinitializer */
-#define USB_EP_CFG_TYPE_INT ((uint32_t)0x00000004) /*!<Endpoint type - interrupt \hideinitializer */
-#define USB_EP_CFG_TYPE_ISO ((uint32_t)0x00000006) /*!<Endpoint type - isochronous \hideinitializer */
-#define USB_EP_CFG_TYPE_MASK ((uint32_t)0x00000006) /*!<Endpoint type mask \hideinitializer */
-#define USB_EP_CFG_DIR_OUT ((uint32_t)0x00000000) /*!<OUT endpoint \hideinitializer */
-#define USB_EP_CFG_DIR_IN ((uint32_t)0x00000008) /*!<IN endpoint \hideinitializer */
-
-
-/*@}*/ /* end of group NUC472_442_USBD_EXPORTED_CONSTANTS */
-
-/** @addtogroup NUC472_442_USBD_EXPORTED_STRUCT USBD Exported Struct
- @{
-*/
-
-
-typedef struct USBD_CMD_STRUCT {
- uint8_t bmRequestType;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
-
-} S_USBD_CMD_T; /*!<USB Setup Packet Structure */
-
-
-
-
-typedef struct s_usbd_info {
- uint8_t *gu8DevDesc;
- uint8_t *gu8ConfigDesc;
- uint8_t *gu8StrLangDesc;
- uint8_t *gu8StrVendorDesc;
- uint8_t *gu8StrProductDesc;
- uint8_t *gu8QualDesc;
- uint8_t *gu8OtherConfigDesc;
- uint8_t *gu8HidReportDesc[3];
- uint32_t gu32HidReportSize[3];
-
-} S_USBD_INFO_T; /*!<USB Information Structure */
-
-
-/*@}*/ /* end of group NUC472_442_USBD_EXPORTED_STRUCT */
-
-/// @cond HIDDEN_SYMBOLS
-extern uint32_t volatile g_usbd_DmaDone;
-extern uint32_t g_usbd_UsbAddr;
-extern uint32_t g_usbd_CtrlInSize;
-extern uint32_t g_usbd_ShortPacket;
-extern uint32_t g_usbd_CtrlZero;
-extern uint8_t g_usbd_EpHalt[];
-extern S_USBD_INFO_T gsInfo;
-extern S_USBD_CMD_T gUsbCmd;
-extern uint32_t g_usbd_Configured;
-/// @endcond /* HIDDEN_SYMBOLS */
-
-/** @addtogroup NUC472_442_USBD_EXPORTED_MACROS USBD Exported Macros
- @{
-*/
-
-#define USBD_ENABLE_USB() ((uint32_t)(USBD->PHYCTL |= (USBD_PHYCTL_PHYEN_Msk|USBD_PHYCTL_DPPUEN_Msk))) /*!<Enable USB \hideinitializer */
-#define USBD_DISABLE_USB() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable USB \hideinitializer */
-#define USBD_ENABLE_PHY() ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_PHYEN_Msk)) /*!<Enable PHY \hideinitializer */
-#define USBD_DISABLE_PHY() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_PHYEN_Msk)) /*!<Disable PHY \hideinitializer */
-#define USBD_SET_SE0() ((uint32_t)(USBD->PHYCTL &= ~USBD_PHYCTL_DPPUEN_Msk)) /*!<Enable SE0, Force USB PHY Transceiver to Drive SE0 \hideinitializer */
-#define USBD_CLR_SE0() ((uint32_t)(USBD->PHYCTL |= USBD_PHYCTL_DPPUEN_Msk)) /*!<Disable SE0 \hideinitializer */
-#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) /*!<Set USB address \hideinitializer */
-#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) /*!<Get USB address \hideinitializer */
-#define USBD_ENABLE_USB_INT(intr) (USBD->GINTEN = (intr)) /*!<Enable USB Interrupt \hideinitializer */
-#define USBD_ENABLE_BUS_INT(intr) (USBD->BUSINTEN = (intr)) /*!<Enable BUS Interrupt \hideinitializer */
-#define USBD_GET_BUS_INT_FLAG() (USBD->BUSINTSTS) /*!<Clear Bus interrupt flag \hideinitializer */
-#define USBD_CLR_BUS_INT_FLAG(flag) (USBD->BUSINTSTS = flag) /*!<Clear Bus interrupt flag \hideinitializer */
-#define USBD_ENABLE_CEP_INT(intr) (USBD->CEPINTEN = (intr)) /*!<Enable CEP Interrupt \hideinitializer */
-#define USBD_CLR_CEP_INT_FLAG(flag) (USBD->CEPINTSTS = flag) /*!<Clear CEP interrupt flag \hideinitializer */
-#define USBD_SET_CEP_STATE(flag) (USBD->CEPCTL = flag) /*!<Set CEP state \hideinitializer */
-#define USBD_START_CEP_IN(size) (USBD->CEPTXCNT = size) /*!<Start CEP IN Transfer \hideinitializer */
-#define USBD_SET_MAX_PAYLOAD(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAMPS + (uint32_t)((ep)*0x28))) = (size)) /*!<Set EPx Maximum Packet Size \hideinitializer */
-#define USBD_ENABLE_EP_INT(ep, intr) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAINTEN + (uint32_t)((ep)*0x28))) = (intr)) /*!<Enable EPx Interrupt \hideinitializer */
-#define USBD_GET_EP_INT_FLAG(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAINTSTS + (uint32_t)((ep)*0x28)))) /*!<Get EPx interrupt flag \hideinitializer */
-#define USBD_CLR_EP_INT_FLAG(ep, flag) (*((__IO uint32_t *) ((uint32_t)&USBD->EPAINTSTS + (uint32_t)((ep)*0x28))) = (flag)) /*!<Clear EPx interrupt flag \hideinitializer */
-#define USBD_SET_DMA_LEN(len) (USBD->DMACNT = len) /*!<Set DMA transfer length \hideinitializer */
-#define USBD_SET_DMA_ADDR(addr) (USBD->DMAADDR = addr) /*!<Set DMA transfer address \hideinitializer */
-#define USBD_SET_DMA_READ(epnum) (USBD->DMACTL = (USBD->DMACTL & ~USBD_DMACTL_EPNUM_Msk) | USBD_DMACTL_DMARD_Msk | epnum) /*!<Set DMA transfer type to read \hideinitializer */
-#define USBD_SET_DMA_WRITE(epnum) (USBD->DMACTL = (USBD->DMACTL & ~(USBD_DMACTL_EPNUM_Msk | USBD_DMACTL_DMARD_Msk)) | epnum) /*!<Set DMA transfer type to write \hideinitializer */
-#define USBD_ENABLE_DMA() (USBD->DMACTL |= USBD_DMACTL_DMAEN_Msk) /*!<Enable DMA transfer \hideinitializer */
-#define USBD_IS_ATTACHED() ((uint32_t)(USBD->PHYCTL & USBD_PHYCTL_VBUSDET_Msk)) /*!<Check cable connect state \hideinitializer */
-
-
-/*@}*/ /* end of group NUC472_442_USBD_EXPORTED_MACROS */
-
-/** @addtogroup NUC472_442_USBD_EXPORTED_FUNCTIONS USBD Exported Functions
- @{
-*/
-/**
- * @brief USBD_memcpy, Copy bytes hardware limitation
- * @param[in] u8Dst Destination pointer.
- * @param[in] u8Src Source pointer.
- * @param[in] i32Size Copy size.
- * @retval None.
- */
-static __INLINE void USBD_MemCopy(uint8_t *u8Dst, uint8_t *u8Src, int32_t i32Size)
-{
- while (i32Size--) *u8Dst++ = *u8Src++;
-}
-
-/**
- * @brief USBD_ResetDMA
- * @param None
- * @retval None.
- */
-static __INLINE void USBD_ResetDMA(void)
-{
- USBD->DMACNT = 0;
- USBD->DMACTL = 0x80;
- USBD->DMACTL = 0x00;
-}
-/**
- * @brief USBD_SetEpBufAddr, Set Endpoint buffer address
- * @param[in] u32Ep Endpoint Number
- * @param[in] u32Base Buffer Start Address
- * @param[in] u32Len Buffer length
- * @retval None.
- */
-static __INLINE void USBD_SetEpBufAddr(uint32_t u32Ep, uint32_t u32Base, uint32_t u32Len)
-{
- if (u32Ep == CEP) {
- USBD->CEPBUFSTART = u32Base;
- USBD->CEPBUFEND = u32Base + u32Len - 1;
- } else {
- *((__IO uint32_t *) ((uint32_t)&USBD->EPABUFSTART + (uint32_t)(u32Ep*0x28))) = u32Base;
- *((__IO uint32_t *) ((uint32_t)&USBD->EPABUFEND + (uint32_t)(u32Ep*0x28))) = u32Base + u32Len - 1;
- }
-}
-
-/**
- * @brief USBD_ConfigEp, Config Endpoint
- * @param[in] u32Ep USB endpoint
- * @param[in] u32EpNum Endpoint number
- * @param[in] u32EpType Endpoint type
- * @param[in] u32EpDir Endpoint direction
- * @retval None.
- */
-static __INLINE void USBD_ConfigEp(uint32_t u32Ep, uint32_t u32EpNum, uint32_t u32EpType, uint32_t u32EpDir)
-{
- if (u32EpType == USB_EP_CFG_TYPE_BULK)
- *((__IO uint32_t *)((uint32_t)&USBD->EPARSPCTL+(uint32_t)(u32Ep*0x28)))=(USB_EP_RSPCTL_FLUSH|USB_EP_RSPCTL_MODE_AUTO);
- else if (u32EpType == USB_EP_CFG_TYPE_INT)
- *((__IO uint32_t *)((uint32_t)&USBD->EPARSPCTL+(uint32_t)(u32Ep*0x28)))=(USB_EP_RSPCTL_FLUSH|USB_EP_RSPCTL_MODE_MANUAL);
- else if (u32EpType == USB_EP_CFG_TYPE_ISO)
- *((__IO uint32_t *)((uint32_t)&USBD->EPARSPCTL+(uint32_t)(u32Ep*0x28)))=(USB_EP_RSPCTL_FLUSH|USB_EP_RSPCTL_MODE_FLY);
-
- *((__IO uint32_t *)((uint32_t)&USBD->EPACFG+(uint32_t)(u32Ep*0x28)))=(u32EpType|u32EpDir|USB_EP_CFG_VALID|(u32EpNum << 4));
-}
-
-/**
- * @brief Set USB endpoint stall state
- *
- * @param[in] u32Ep USB endpoint
- * @return None
- *
- * @details Set USB endpoint stall state, endpoint will return STALL token.
- */
-static __INLINE void USBD_SetStall(uint32_t u32Ep)
-{
- uint32_t u32CfgAddr;
- uint32_t u32Cfg;
- int i;
-
- if (u32Ep == 0)
- USBD_SET_CEP_STATE(USB_CEPCTL_STALL);
- else {
- for (i=0; i<USBD_MAX_EP; i++) {
- u32CfgAddr = (uint32_t)&USBD->EPACFG + (uint32_t)(i * 0x28);
- u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
-
- if (((u32Cfg & 0xf0) >> 4) == u32Ep)
- {
- u32CfgAddr = (uint32_t)&USBD->EPARSPCTL + (uint32_t)(i * 0x28);
- u32Cfg = *((__IO uint32_t *) (u32CfgAddr)) & 0xf7; /* avoid clear TOGGLE bit */
- *((__IO uint32_t *) (u32CfgAddr)) = (u32Cfg | USB_EP_RSPCTL_HALT);
- }
- }
- }
-}
-
-/**
- * @brief Clear USB endpoint stall state
- *
- * @param[in] u32Ep USB endpoint
- * @return None
- *
- * @details Clear USB endpoint stall state, endpoint will return ACK/NAK token.
- */
-static __INLINE void USBD_ClearStall(uint32_t u32Ep)
-{
- uint32_t u32CfgAddr;
- uint32_t u32Cfg;
- int i;
-
- for (i=0; i<USBD_MAX_EP; i++) {
- u32CfgAddr = (uint32_t)&USBD->EPACFG + (uint32_t)(i * 0x28);
- u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
-
- if (((u32Cfg & 0xf0) >> 4) == u32Ep)
- {
- u32CfgAddr = (uint32_t)&USBD->EPARSPCTL + (uint32_t)(i * 0x28);
- *((__IO uint32_t *) (u32CfgAddr)) = USB_EP_RSPCTL_TOGGLE;
- }
- }
-}
-
-/**
- * @brief Get USB endpoint stall state
- *
- * @param[in] u32Ep USB endpoint
- * @retval 0: USB endpoint is not stalled.
- * @retval non-0: USB endpoint is stalled.
- *
- * @details Get USB endpoint stall state.
- */
-static __INLINE uint32_t USBD_GetStall(uint32_t u32Ep)
-{
- uint32_t u32CfgAddr;
- uint32_t u32Cfg;
- int i;
-
- for (i=0; i<USBD_MAX_EP; i++) {
- u32CfgAddr = (uint32_t)&USBD->EPACFG + (uint32_t)(i * 0x28);
- u32Cfg = *((__IO uint32_t *) (u32CfgAddr));
-
- if (((u32Cfg & 0xf0) >> 4) == u32Ep)
- {
- u32CfgAddr = (uint32_t)&USBD->EPARSPCTL + (uint32_t)(i * 0x28);
- return ((*((__IO uint32_t *) (u32CfgAddr))) & USB_EP_RSPCTL_HALT);
- }
- }
- return 0;
-}
-
-
-/*-------------------------------------------------------------------------------------------*/
-typedef void (*VENDOR_REQ)(void); /*!<USB Vendor request callback function */
-typedef void (*CLASS_REQ)(void); /*!<USB Class request callback function */
-typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!<USB Standard request "Set Interface" callback function */
-
-void USBD_Open(S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
-void USBD_Start(void);
-void USBD_ProcessSetupPacket(void);
-void USBD_StandardRequest(void);
-void USBD_UpdateDeviceState(void);
-void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
-void USBD_CtrlIn(void);
-void USBD_CtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
-void USBD_SwReset(void);
-void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
-
-
-
-/*@}*/ /* end of group NUC472_442_USBD_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_USBD_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__USBD_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_wdt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,65 +0,0 @@
-/**************************************************************************//**
- * @file wdt.c
- * @version V1.00
- * $Revision: 6 $
- * $Date: 14/10/02 7:19p $
- * @brief NUC472/NUC442 WDT driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_WDT_Driver WDT Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
- @{
-*/
-
-/**
- * @brief This function make WDT module start counting with different time-out interval
- * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
- * - \ref WDT_TIMEOUT_2POW4
- * - \ref WDT_TIMEOUT_2POW6
- * - \ref WDT_TIMEOUT_2POW8
- * - \ref WDT_TIMEOUT_2POW10
- * - \ref WDT_TIMEOUT_2POW12
- * - \ref WDT_TIMEOUT_2POW14
- * - \ref WDT_TIMEOUT_2POW16
- * - \ref WDT_TIMEOUT_2POW18
- * @param[in] u32ResetDelay Reset delay period while WDT time-out happened. Valid values are:
- * - \ref WDT_RESET_DELAY_3CLK
- * - \ref WDT_RESET_DELAY_18CLK
- * - \ref WDT_RESET_DELAY_130CLK
- * - \ref WDT_RESET_DELAY_1026CLK
- * @param[in] u32EnableReset Enable WDT rest system function. Valid values are \ref TRUE and \ref FALSE
- * @param[in] u32EnableWakeup Enable WDT wake-up system function. Valid values are \ref TRUE and \ref FALSE
- * @return None
- */
-void WDT_Open(uint32_t u32TimeoutInterval,
- uint32_t u32ResetDelay,
- uint32_t u32EnableReset,
- uint32_t u32EnableWakeup)
-{
-
- WDT->CTL = u32TimeoutInterval | u32ResetDelay | WDT_CTL_WDTEN_Msk |
- (u32EnableReset << WDT_CTL_RSTEN_Pos) |
- (u32EnableWakeup << WDT_CTL_WKEN_Pos);
- return;
-}
-
-
-/*@}*/ /* end of group NUC472_442_WDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_WDT_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_wdt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,162 +0,0 @@
-/**************************************************************************//**
- * @file wdt.h
- * @version V1.00
- * $Revision: 8 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 WDT driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __WDT_H__
-#define __WDT_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_WDT_Driver WDT Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_WDT_EXPORTED_CONSTANTS WDT Exported Constants
- @{
-*/
-#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^4 * WDT clocks \hideinitializer */
-#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^6 * WDT clocks \hideinitializer */
-#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^8 * WDT clocks \hideinitializer */
-#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^10 * WDT clocks \hideinitializer */
-#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^12 * WDT clocks \hideinitializer */
-#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^14 * WDT clocks \hideinitializer */
-#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^16 * WDT clocks \hideinitializer */
-#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^18 * WDT clocks \hideinitializer */
-
-#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 3 WDT clocks \hideinitializer */
-#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 18 WDT clocks \hideinitializer */
-#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 130 WDT clocks \hideinitializer */
-#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 1026 WDT clocks \hideinitializer */
-
-/*@}*/ /* end of group NUC472_442_WDT_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
- @{
-*/
-
-/**
- * @brief This macro clear WDT time-out reset system flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
-
-/**
- * @brief This macro clear WDT time-out interrupt flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
-
-/**
- * @brief This macro clear WDT time-out wake-up system flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
-
-/**
- * @brief This macro indicate WDT time-out to reset system or not.
- * @return WDT reset system or not
- * @retval 0 WDT did not cause system reset
- * @retval 1 WDT caused system reset
- * \hideinitializer
- */
-#define WDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
-
-/**
- * @brief This macro indicate WDT time-out interrupt occurred or not.
- * @return WDT time-out interrupt occurred or not
- * @retval 0 WDT time-out interrupt did not occur
- * @retval 1 WDT time-out interrupt occurred
- * \hideinitializer
- */
-#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
-
-/**
- * @brief This macro indicate WDT time-out waked system up or not
- * @return WDT time-out waked system up or not
- * @retval 0 WDT did not wake up system
- * @retval 1 WDT waked up system
- * \hideinitializer
- */
-#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
-
-/**
- * @brief This macro is used to reset 18-bit WDT counter.
- * @details If WDT is activated and enabled to reset system, software must reset WDT counter
- * before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
- * \hideinitializer
- */
-#define WDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)
-
-/**
- * @brief This function stops WDT counting and disable WDT module
- * @param None
- * @return None
- */
-__STATIC_INLINE void WDT_Close(void)
-{
- WDT->CTL = 0;
- return;
-}
-
-/**
- * @brief This function enables the WDT time-out interrupt
- * @param None
- * @return None
- */
-__STATIC_INLINE void WDT_EnableInt(void)
-{
- WDT->CTL |= WDT_CTL_INTEN_Msk;
- return;
-}
-
-/**
- * @brief This function disables the WDT time-out interrupt
- * @param None
- * @return None
- */
-__STATIC_INLINE void WDT_DisableInt(void)
-{
- // Do not touch write 1 clear bits
- WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk) ;
- return;
-}
-
-void WDT_Open(uint32_t u32TimeoutInterval,
- uint32_t u32ResetDelay,
- uint32_t u32EnableReset,
- uint32_t u32EnableWakeup);
-
-/*@}*/ /* end of group NUC472_442_WDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_WDT_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__WDT_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_wwdt.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,68 +0,0 @@
-/**************************************************************************//**
- * @file wwdt.c
- * @version V1.00
- * $Revision: 6 $
- * $Date: 14/10/02 7:19p $
- * @brief NUC472/NUC442 WWDT driver source file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-#include "NUC472_442.h"
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_WWDT_Driver WWDT Driver
- @{
-*/
-
-
-/** @addtogroup NUC472_442_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
- @{
-*/
-
-/**
- * @brief This function make WWDT module start counting with different counter period and compared window value
- * @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are:
- * - \ref WWDT_PRESCALER_1
- * - \ref WWDT_PRESCALER_2
- * - \ref WWDT_PRESCALER_4
- * - \ref WWDT_PRESCALER_8
- * - \ref WWDT_PRESCALER_16
- * - \ref WWDT_PRESCALER_32
- * - \ref WWDT_PRESCALER_64
- * - \ref WWDT_PRESCALER_128
- * - \ref WWDT_PRESCALER_192
- * - \ref WWDT_PRESCALER_256
- * - \ref WWDT_PRESCALER_384
- * - \ref WWDT_PRESCALER_512
- * - \ref WWDT_PRESCALER_768
- * - \ref WWDT_PRESCALER_1024
- * - \ref WWDT_PRESCALER_1536
- * - \ref WWDT_PRESCALER_2048
- * @param[in] u32CmpValue Window compared value. Valid values are between 0x0 to 0x3F
- * @param[in] u32EnableInt Enable WWDT interrupt or not. Valid values are \ref TRUE and \ref FALSE
- * @return None
- * @note Application can call this function can only once after boot up
- */
-void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt)
-{
- WWDT->CTL = u32PreScale |
- (u32CmpValue << WWDT_CTL_CMPDAT_Pos)|
- WWDT_CTL_WWDTEN_Msk |
- (u32EnableInt ? WWDT_CTL_INTEN_Msk : 0);
- return;
-}
-
-
-
-
-/*@}*/ /* end of group NUC472_442_WWDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_WWDT_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_wwdt.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,125 +0,0 @@
-/**************************************************************************//**
- * @file wwdt.h
- * @version V1.00
- * $Revision: 9 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 WWDT driver header file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __WWDT_H__
-#define __WWDT_H__
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_WWDT_Driver WWDT Driver
- @{
-*/
-
-/** @addtogroup NUC472_442_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
- @{
-*/
-#define WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1 \hideinitializer
-#define WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 2 \hideinitializer
-#define WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 4 \hideinitializer
-#define WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 8 \hideinitializer
-#define WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 16 \hideinitializer
-#define WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 32 \hideinitializer
-#define WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 64 \hideinitializer
-#define WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 128 \hideinitializer
-#define WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 192 \hideinitializer
-#define WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 256 \hideinitializer
-#define WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 384 \hideinitializer
-#define WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 512 \hideinitializer
-#define WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 768 \hideinitializer
-#define WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1024 \hideinitializer
-#define WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1536 \hideinitializer
-#define WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 2048 \hideinitializer
-
-#define WWDT_RELOAD_WORD (0x00005AA5) ///< Fill this value to RLD register to reload WWDT counter \hideinitializer
-/*@}*/ /* end of group NUC472_442_WWDT_EXPORTED_CONSTANTS */
-
-
-/** @addtogroup NUC472_442_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
- @{
-*/
-
-/**
- * @brief This macro clear WWDT time-out reset system flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
-
-/**
- * @brief This macro clear WWDT compare match interrupt flag.
- * @param None
- * @return None
- * \hideinitializer
- */
-#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
-
-/**
- * @brief This macro is use to get WWDT time-out reset system flag.
- * @return WWDT reset system or not
- * @retval 0 WWDT did not cause system reset
- * @retval 1 WWDT caused system reset
- * \hideinitializer
- */
-#define WWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
-
-/**
- * @brief This macro is used to indicate WWDT compare match interrupt flag.
- * @return WWDT compare match interrupt occurred or not
- * @retval 0 WWDT compare match interrupt did not occur
- * @retval 1 WWDT compare match interrupt occurred
- * \hideinitializer
- */
-#define WWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
-
-/**
- * @brief This macro to reflects current WWDT counter value
- * @param None
- * @return Return current WWDT counter value
- * \hideinitializer
- */
-#define WWDT_GET_COUNTER() (WWDT->CNT)
-
-/**
- * @brief This macro is used to reload the WWDT counter value to 0x3F.
- * @param None
- * @return None
- * @details After WWDT enabled, application must reload WWDT counter while
- * current counter is less than compare value and larger than 0,
- * otherwise WWDT will cause system reset.
- * \hideinitializer
- */
-#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
-
-
-void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
-
-
-/*@}*/ /* end of group NUC472_442_WWDT_EXPORTED_FUNCTIONS */
-
-/*@}*/ /* end of group NUC472_442_WWDT_Driver */
-
-/*@}*/ /* end of group NUC472_442_Device_Driver */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //__WWDT_H__
-
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/NUC472.sct Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-
-LR_IROM1 0x00000000 {
- ER_IROM1 0x00000000 { ; load address = execution address
- *(RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
-
- ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
- }
-
- ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors
- }
-
- RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
- .ANY (+RW +ZI)
- }
-
- ; Too large to place into internal SRAM. So place into external SRAM instead.
- ER_XRAM1 0x60000000 {
- *sal-stack-lwip* (+ZI)
- }
-
- ; Extern SRAM for HEAP
- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
- }
-}
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM
-ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000) ; 1 MB SRAM (external)
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/sys.cpp Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
-extern char Image$$ARM_LIB_HEAP$$Base[];
-extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-
- struct __initial_stackheap r;
- r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
- r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/NUC472.sct Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,37 +0,0 @@
-
-LR_IROM1 0x00000000 {
- ER_IROM1 0x00000000 { ; load address = execution address
- *(RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
- ; uvisor-lib.a (+RW +ZI)
- ;}
-
- ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
- }
-
- ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 142)) { ; Reserve for vectors
- }
-
- RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
- .ANY (+RW +ZI)
- }
-
- ; Too large to place into internal SRAM. So place into external SRAM instead.
- ER_XRAM1 0x60000000 {
- *lwip_* (+ZI)
- aes.o (+ZI)
- mesh_system.o (+ZI)
- }
-
- ; Extern SRAM for HEAP
- ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
- }
-}
-ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM
-ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000) ; 1 MB SRAM (external)
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_STD/sys.cpp Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
-extern char Image$$ARM_LIB_HEAP$$Base[];
-extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-
- struct __initial_stackheap r;
- r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
- r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/NUC472.ld Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,269 +0,0 @@
-/*
- * Nuvoton NUC472 GCC linker script file
- */
-
-StackSize = 0x800;
-
-MEMORY
-{
-
- VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
- FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400
- RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - 0x00000000
- RAM_EXTERN (rwx) : ORIGIN = 0x60000000, LENGTH = 0x00100000
-}
-
-/**
- * Must match cmsis_nvic.h
- */
-__vector_size = 4 * (16 + 142);
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .isr_vector :
- {
- __vector_table = .;
- KEEP(*(.vector_table))
- . = ALIGN(4);
- } > VECTORS
-
- /* ensure that uvisor bss is at the beginning of memory */
- .uvisor.bss (NOLOAD):
- {
- . = ALIGN(32);
- __uvisor_bss_start = .;
-
- /* protected uvisor main bss */
- . = ALIGN(32);
- __uvisor_bss_main_start = .;
- KEEP(*(.keep.uvisor.bss.main))
- . = ALIGN(32);
- __uvisor_bss_main_end = .;
-
- /* protected uvisor secure boxes bss */
- . = ALIGN(32);
- __uvisor_bss_boxes_start = .;
- KEEP(*(.keep.uvisor.bss.boxes))
- . = ALIGN(32);
- __uvisor_bss_boxes_end = .;
-
- /* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
- . = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
- __uvisor_bss_end = .;
- } > RAM_INTERN
-
- .text :
- {
- /* uVisor code and data */
- . = ALIGN(4);
- __uvisor_main_start = .;
- *(.uvisor.main)
- __uvisor_main_end = .;
-
- *(.text*)
-
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- .ARM.exidx :
- {
- __exidx_start = .;
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- __exidx_end = .;
- } > FLASH
-
- /* .stack section doesn't contains any symbols. It is only
- * used for linker to reserve space for the main stack section
- * WARNING: .stack should come immediately after the last secure memory
- * section. This provides stack overflow detection. */
- .stack (NOLOAD):
- {
- __StackLimit = .;
- *(.stack*);
- . += StackSize - (. - __StackLimit);
- } > RAM_INTERN
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ADDR(.stack) + SIZEOF(.stack);
- __StackLimit = ADDR(.stack);
- PROVIDE(__stack = __StackTop);
-
- /* Relocate vector table in SRAM */
- .isr_vector.reloc (NOLOAD) :
- {
- . = ALIGN(1 << LOG2CEIL(__vector_size));
- PROVIDE(__start_vector_table__ = .);
- . += __vector_size;
- PROVIDE(__end_vector_table__ = .);
- } > RAM_INTERN
-
- .data :
- {
- PROVIDE( __etext = LOADADDR(.data) );
-
- __data_start__ = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- /* All data end */
- . = ALIGN(32);
- __data_end__ = .;
-
- } >RAM_INTERN AT>FLASH
-
- /* uvisor configuration data */
- .uvisor.secure :
- {
- . = ALIGN(32);
- __uvisor_secure_start = .;
-
- /* uvisor secure boxes configuration tables */
- . = ALIGN(32);
- __uvisor_cfgtbl_start = .;
- KEEP(*(.keep.uvisor.cfgtbl))
- . = ALIGN(32);
- __uvisor_cfgtbl_end = .;
-
- /* pointers to uvisor secure boxes configuration tables */
- /* note: no further alignment here, we need to have the exact list of pointers */
- __uvisor_cfgtbl_ptr_start = .;
- KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
- KEEP(*(.keep.uvisor.cfgtbl_ptr))
- __uvisor_cfgtbl_ptr_end = .;
-
- /* the following symbols are kept for backward compatibility and will be soon
- * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
- * will need to use uVisor 0.8.x or above, or the security assertions will halt the
- * system */
- /************************/
- __uvisor_data_src = .;
- __uvisor_data_start = .;
- __uvisor_data_end = .;
- /************************/
-
- . = ALIGN(32);
- __uvisor_secure_end = .;
- } >FLASH
-
- .uninitialized (NOLOAD):
- {
- . = ALIGN(32);
- __uninitialized_start = .;
- *(.uninitialized)
- KEEP(*(.keep.uninitialized))
- . = ALIGN(32);
- __uninitialized_end = .;
- } > RAM_INTERN
-
- .bss.extern (NOLOAD):
- {
- __bss_extern_start__ = .;
- /**
- * Place large .bss* sections into external SRAM if internal SRAM is insufficient.
- * Such memory arrangement requires initializing .bss.extern section to zero in startup file. Check startup fiile in cmsis-core-* for support or not.
- */
- *lwip_*.o(.bss*)
- *lwip_*.o(COMMON)
- *mesh_system.o(.bss*)
- __bss_extern_end__ = .;
- } > RAM_EXTERN
-
- .bss (NOLOAD):
- {
- __bss_start__ = .;
- *(.bss*)
- *(COMMON)
- __bss_end__ = .;
- } > RAM_INTERN
-
- .heap (NOLOAD):
- {
- __end__ = .;
- end = __end__;
- *(.heap*);
- . += (ORIGIN(RAM_EXTERN) + LENGTH(RAM_EXTERN) - .);
- __HeapLimit = .;
- } > RAM_EXTERN
- PROVIDE(__heap_size = SIZEOF(.heap));
- PROVIDE(__mbed_sbrk_start = ADDR(.heap));
- PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
-
- /* Provide physical memory boundaries for uVisor. */
- __uvisor_flash_start = ORIGIN(VECTORS);
- __uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
- __uvisor_sram_start = ORIGIN(RAM_INTERN);
- __uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_GCC_ARM/retarget.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,37 +0,0 @@
-/******************************************************************************
- * @file startup_NUC472_442.c
- * @version V0.10
- * $Revision: 11 $
- * $Date: 15/09/02 10:02a $
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for NUC472/442 MCU
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-#include <errno.h>
-
-extern uint32_t __mbed_sbrk_start;
-extern uint32_t __mbed_krbs_start;
-
-/**
- * The default implementation of _sbrk() (in common/retarget.cpp) for GCC_ARM requires one-region model (heap and stack share one region), which doesn't
- * fit two-region model (heap and stack are two distinct regions), for example, NUMAKER-PFM-NUC472 locates heap on external SRAM. Define __wrap__sbrk() to
- * override the default _sbrk(). It is expected to get called through gcc hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
- */
-void *__wrap__sbrk(int incr)
-{
- static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
- uint32_t heap_ind_old = heap_ind;
- uint32_t heap_ind_new = (heap_ind_old + incr + 7) & ~7;
-
- if (heap_ind_new > &__mbed_krbs_start) {
- errno = ENOMEM;
- return (void *) -1;
- }
-
- heap_ind = heap_ind_new;
-
- return (void *) heap_ind_old;
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_IAR/NUC472_442.icf Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__ = 0x00080000;
-define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_IRAM_end__ = 0x20010000;
-define symbol __ICFEDIT_region_XRAM_start__ = 0x60000000;
-define symbol __ICFEDIT_region_XRAM_end__ = 0x60100000;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x800;
-define symbol __ICFEDIT_size_heap__ = 0xC0000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
-define region XRAM_region = mem:[from __ICFEDIT_region_XRAM_start__ to __ICFEDIT_region_XRAM_end__];
-
-define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
-/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
-define block IRAMVEC with alignment = 1024, size = 4 * (16 + 142) { };
-/* Move non-critical libraries to external SRAM while internal SRAM is insufficient. */
-define block XRAM_NC with alignment = 8 { zeroinit object *lwip_*, zeroinit object *mesh_system.o };
-
-
-initialize by copy { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place at start of IRAM_region { block CSTACK };
-place in IRAM_region { block IRAMVEC };
-place in IRAM_region { readwrite };
-place in XRAM_region { block XRAM_NC, block HEAP };
\ No newline at end of file
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis.h Thu Dec 15 11:48:27 2016 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015-2016 Nuvoton - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "NUC472_442.h" -#include "cmsis_nvic.h" - -// Support linker-generated symbol as start of relocated vector table. - -#if defined(__CC_ARM) -extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; -#elif defined(__ICCARM__) - -#elif defined(__GNUC__) -extern uint32_t __start_vector_table__; -#endif - -#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,39 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "cmsis_nvic.h"
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *) SCB->VTOR;
- uint32_t i;
-
- /* Copy and switch to dynamic vectors if the first time called */
- if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
- uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
- vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
- for (i = 0; i < NVIC_NUM_VECTORS; i++) {
- vectors[i] = old_vectors[i];
- }
- SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
- }
- vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *) SCB->VTOR;
- return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/cmsis_nvic.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-#include "cmsis.h"
-
-#define NVIC_USER_IRQ_OFFSET 16
-#define NVIC_USER_IRQ_NUMBER 142
-#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
-
-#if defined(__CC_ARM)
-# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
-#elif defined(__ICCARM__)
-# pragma section = "IRAMVEC"
-# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
-#elif defined(__GNUC__)
-# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
-#endif
-
-
-#define NVIC_FLASH_VECTOR_ADDRESS 0
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Set the ISR for IRQn
- *
- * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM
- * the first time this function is called
- * @param[in] IRQn The Interrupt Request number for which a vector will be registered
- * @param[in] vector The ISR vector to register for IRQn
- */
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-
-/** Get the ISR registered for IRQn
- *
- * Reads the Interrupt Service Routine currently registered for IRQn
- * @param[in] IRQn The Interrupt Request number the vector of which will be read
- * @return Returns the ISR registered for IRQn
- */
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/startup_NUC472_442.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,503 +0,0 @@
-/******************************************************************************
- * @file startup_NUC472_442.c
- * @version V0.10
- * $Revision: 11 $
- * $Date: 15/09/02 10:02a $
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for NUC472/442 MCU
- *
- * @note
- * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-
-/* Suppress warning messages */
-#if defined(__CC_ARM)
-// Suppress warning message: extended constant initialiser used
-#pragma diag_suppress 1296
-#elif defined(__ICCARM__)
-#elif defined(__GNUC__)
-#endif
-
-/* Macro Definitions */
-#if defined(__CC_ARM)
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias(#f)))
-
-#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
-void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
-
-#elif defined(__ICCARM__)
-//#define STRINGIFY(x) #x
-//#define _STRINGIFY(x) STRINGIFY(x)
-#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
-void FUN(void); \
-_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)))
-#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)
-#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS
-
-#elif defined(__GNUC__)
-#define WEAK __attribute__ ((weak))
-#define ALIAS(f) __attribute__ ((weak, alias(#f)))
-
-#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
-void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
-
-#endif
-
-
-/* Initialize segments */
-#if defined(__CC_ARM)
-extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
-extern void __main(void);
-#elif defined(__ICCARM__)
-void __iar_program_start(void);
-#elif defined(__GNUC__)
-extern uint32_t __StackTop;
-extern uint32_t __etext;
-extern uint32_t __data_start__;
-extern uint32_t __data_end__;
-extern uint32_t __bss_start__;
-extern uint32_t __bss_end__;
-extern uint32_t __bss_extern_start__ WEAK;
-extern uint32_t __bss_extern_end__ WEAK;
-
-extern void uvisor_init(void);
-//#if defined(TOOLCHAIN_GCC_ARM)
-//extern void _start(void);
-//#endif
-extern void software_init_hook(void) __attribute__((weak));
-extern void __libc_init_array(void);
-extern int main(void);
-#endif
-
-/* Default empty handler */
-void Default_Handler(void);
-
-/* Reset handler */
-void Reset_Handler(void);
-
-/* Cortex-M4 core handlers */
-WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(MemManage_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(BusFault_Handler , Default_Handler)
-WEAK_ALIAS_FUNC(UsageFault_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(DebugMon_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler)
-WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
-
-/* Peripherals handlers */
-WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection
-WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC
-WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power Down Wake Up
-WEAK_ALIAS_FUNC(SRAMF_IRQHandler, Default_Handler) // 3: Reserved.
-WEAK_ALIAS_FUNC(CLKF_IRQHandler, Default_Handler) // 4: CLKF
- // 5: Reserved.
-WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock
-WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler) // 7: Tamper detection
-WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler) // 8: External Input 0
-WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler) // 9: External Input 1
-WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler) // 10: External Input 2
-WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler) // 11: External Input 3
-WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler) // 12: External Input 4
-WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler) // 13: External Input 5
-WEAK_ALIAS_FUNC(EINT6_IRQHandler, Default_Handler) // 14: External Input 6
-WEAK_ALIAS_FUNC(EINT7_IRQHandler, Default_Handler) // 15: External Input 7
-WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler) // 16: GPIO Port A
-WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler) // 17: GPIO Port B
-WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C
-WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D
-WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E
-WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F
-WEAK_ALIAS_FUNC(GPG_IRQHandler, Default_Handler) // 22: GPIO Port G
-WEAK_ALIAS_FUNC(GPH_IRQHandler, Default_Handler) // 23: GPIO Port H
-WEAK_ALIAS_FUNC(GPI_IRQHandler, Default_Handler) // 24: GPIO Port I
- // 25: Reserved.
- // 26: Reserved.
- // 27: Reserved.
- // 28: Reserved.
- // 29: Reserved.
- // 30: Reserved.
- // 31: Reserved.
-WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0
-WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1
-WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2
-WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler) // 35: Timer 3
- // 36: Reserved.
- // 37: Reserved.
- // 38: Reserved.
- // 39: Reserved.
-WEAK_ALIAS_FUNC(PDMA_IRQHandler, Default_Handler) // 40: Peripheral DMA
- // 41: Reserved.
-WEAK_ALIAS_FUNC(ADC_IRQHandler, Default_Handler) // 42: ADC
- // 43: Reserved.
- // 44: Reserved.
- // 45: Reserved.
-WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler) // 46: Watch Dog Timer
-WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler) // 47: Window Watch Dog Timer
-WEAK_ALIAS_FUNC(EADC0_IRQHandler, Default_Handler) // 48: EDAC 0
-WEAK_ALIAS_FUNC(EADC1_IRQHandler, Default_Handler) // 49: EDAC 1
-WEAK_ALIAS_FUNC(EADC2_IRQHandler, Default_Handler) // 50: EDAC 2
-WEAK_ALIAS_FUNC(EADC3_IRQHandler, Default_Handler) // 51: EDAC 3
- // 52: Reserved.
- // 53: Reserved.
- // 54: Reserved.
- // 55: Reserved.
-WEAK_ALIAS_FUNC(ACMP_IRQHandler, Default_Handler) // 56: Analog Comparator
- // 57: Reserved.
- // 58: Reserved.
- // 59: Reserved.
-WEAK_ALIAS_FUNC(OPA0_IRQHandler, Default_Handler) // 60: OPA 0
-WEAK_ALIAS_FUNC(OPA1_IRQHandler, Default_Handler) // 61: OPA 1
-WEAK_ALIAS_FUNC(ICAP0_IRQHandler, Default_Handler) // 62: ICAP 0
-WEAK_ALIAS_FUNC(ICAP1_IRQHandler, Default_Handler) // 63: ICAP 1
-WEAK_ALIAS_FUNC(PWM0CH0_IRQHandler, Default_Handler) // 64: PWM0 CH0
-WEAK_ALIAS_FUNC(PWM0CH1_IRQHandler, Default_Handler) // 65: PWM0 CH1
-WEAK_ALIAS_FUNC(PWM0CH2_IRQHandler, Default_Handler) // 66: PWM0 CH2
-WEAK_ALIAS_FUNC(PWM0CH3_IRQHandler, Default_Handler) // 67: PWM0 CH3
-WEAK_ALIAS_FUNC(PWM0CH4_IRQHandler, Default_Handler) // 68: PWM0 CH4
-WEAK_ALIAS_FUNC(PWM0CH5_IRQHandler, Default_Handler) // 69: PWM0 CH5
-WEAK_ALIAS_FUNC(PWM0_BRK_IRQHandler, Default_Handler) // 70: PWM0 Break
-WEAK_ALIAS_FUNC(QEI0_IRQHandler, Default_Handler) // 71: QEI 0
-WEAK_ALIAS_FUNC(PWM1CH0_IRQHandler, Default_Handler) // 72: PWM1 CH0
-WEAK_ALIAS_FUNC(PWM1CH1_IRQHandler, Default_Handler) // 73: PWM1 CH1
-WEAK_ALIAS_FUNC(PWM1CH2_IRQHandler, Default_Handler) // 74: PWM1 CH2
-WEAK_ALIAS_FUNC(PWM1CH3_IRQHandler, Default_Handler) // 75: PWM1 CH3
-WEAK_ALIAS_FUNC(PWM1CH4_IRQHandler, Default_Handler) // 76: PWM1 CH4
-WEAK_ALIAS_FUNC(PWM1CH5_IRQHandler, Default_Handler) // 77: PWM1 CH5
-WEAK_ALIAS_FUNC(PWM1_BRK_IRQHandler, Default_Handler) // 78: PWM1 Break
-WEAK_ALIAS_FUNC(QEI1_IRQHandler, Default_Handler) // 79: QEI 1
-WEAK_ALIAS_FUNC(EPWM0_IRQHandler, Default_Handler) // 80: EPWM0
-WEAK_ALIAS_FUNC(EPWM0BRK_IRQHandler, Default_Handler) // 81: EPWM0 Break
-WEAK_ALIAS_FUNC(EPWM1_IRQHandler, Default_Handler) // 82: EPWM1
-WEAK_ALIAS_FUNC(EPWM1BRK_IRQHandler, Default_Handler) // 83: EPWM1 Break
- // 84: Reserved.
- // 85: Reserved.
- // 86: Reserved.
- // 87: Reserved.
-WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler) // 88: USB Device
-WEAK_ALIAS_FUNC(USBH_IRQHandler, Default_Handler) // 89: USB Host
-WEAK_ALIAS_FUNC(USB_OTG_IRQHandler, Default_Handler) // 90: USB OTG
- // 91: Reserved.
-WEAK_ALIAS_FUNC(EMAC_TX_IRQHandler, Default_Handler) // 92: Ethernet MAC TX
-WEAK_ALIAS_FUNC(EMAC_RX_IRQHandler, Default_Handler) // 93: Ethernet MAC RX
- // 94: Reserved.
- // 95: Reserved.
-WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 96: SPI 0
-WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler) // 97: SPI 1
-WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler) // 98: SPI 2
-WEAK_ALIAS_FUNC(SPI3_IRQHandler, Default_Handler) // 99: SPI 3
- // 100: Reserved.
- // 101: Reserved.
- // 102: Reserved.
- // 103: Reserved.
-WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 104: UART 0
-WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 105: UART 1
-WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler) // 106: UART 2
-WEAK_ALIAS_FUNC(UART3_IRQHandler, Default_Handler) // 107: UART 3
-WEAK_ALIAS_FUNC(UART4_IRQHandler, Default_Handler) // 108: UART 4
-WEAK_ALIAS_FUNC(UART5_IRQHandler, Default_Handler) // 109: UART 5
- // 110: Reserved.
- // 111: Reserved.
-WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 112: I2C 0
-WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 113: I2C 1
-WEAK_ALIAS_FUNC(I2C2_IRQHandler, Default_Handler) // 114: I2C 2
-WEAK_ALIAS_FUNC(I2C3_IRQHandler, Default_Handler) // 115: I2C 3
-WEAK_ALIAS_FUNC(I2C4_IRQHandler, Default_Handler) // 116: I2C 4
- // 117: Reserved.
- // 118: Reserved.
- // 119: Reserved.
-WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler) // 120: Smart Card 0
-WEAK_ALIAS_FUNC(SC1_IRQHandler, Default_Handler) // 121: Smart Card 1
-WEAK_ALIAS_FUNC(SC2_IRQHandler, Default_Handler) // 122: Smart Card 2
-WEAK_ALIAS_FUNC(SC3_IRQHandler, Default_Handler) // 123: Smart Card 3
-WEAK_ALIAS_FUNC(SC4_IRQHandler, Default_Handler) // 124: Smart Card 4
-WEAK_ALIAS_FUNC(SC5_IRQHandler, Default_Handler) // 125: Smart Card 5
- // 126: Reserved.
- // 127: Reserved.
-WEAK_ALIAS_FUNC(CAN0_IRQHandler, Default_Handler) // 128: CAN 0
-WEAK_ALIAS_FUNC(CAN1_IRQHandler, Default_Handler) // 129: CAN 1
- // 130: Reserved.
- // 131: Reserved.
-WEAK_ALIAS_FUNC(I2S0_IRQHandler, Default_Handler) // 132: I2S 0
-WEAK_ALIAS_FUNC(I2S1_IRQHandler, Default_Handler) // 133: I2S 1
- // 134: Reserved.
- // 135: Reserved.
-WEAK_ALIAS_FUNC(SD_IRQHandler, Default_Handler) // 136: SD card
- // 137: Reserved.
-WEAK_ALIAS_FUNC(PS2D_IRQHandler, Default_Handler) // 138: PS/2 device
-WEAK_ALIAS_FUNC(CAP_IRQHandler, Default_Handler) // 139: VIN
-WEAK_ALIAS_FUNC(CRYPTO_IRQHandler, Default_Handler) // 140: CRYPTO
-WEAK_ALIAS_FUNC(CRC_IRQHandler, Default_Handler) // 141: CRC
-
-/* Vector table */
-#if defined(__CC_ARM)
-__attribute__ ((section("RESET")))
-const uint32_t __vector_handlers[] = {
-#elif defined(__ICCARM__)
-extern uint32_t CSTACK$$Limit;
-const uint32_t __vector_table[] @ ".intvec" = {
-#elif defined(__GNUC__)
-__attribute__ ((section(".vector_table")))
-const uint32_t __vector_handlers[] = {
-#endif
-
- /* Configure Initial Stack Pointer, using linker-generated symbols */
-#if defined(__CC_ARM)
- (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
-#elif defined(__ICCARM__)
- //(uint32_t) __sfe("CSTACK"),
- (uint32_t) &CSTACK$$Limit,
-#elif defined(__GNUC__)
- (uint32_t) &__StackTop,
-#endif
-
- (uint32_t) Reset_Handler, // Reset Handler
- (uint32_t) NMI_Handler, // NMI Handler
- (uint32_t) HardFault_Handler, // Hard Fault Handler
- (uint32_t) MemManage_Handler, // MPU Fault Handler
- (uint32_t) BusFault_Handler, // Bus Fault Handler
- (uint32_t) UsageFault_Handler, // Usage Fault Handler
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- 0, // Reserved
- (uint32_t) SVC_Handler, // SVCall Handler
- (uint32_t) DebugMon_Handler, // Debug Monitor Handler
- 0, // Reserved
- (uint32_t) PendSV_Handler, // PendSV Handler
- (uint32_t) SysTick_Handler, // SysTick Handler
-
- /* External Interrupts */
- (uint32_t) BOD_IRQHandler, // 0: Brown Out detection
- (uint32_t) IRC_IRQHandler, // 1: Internal RC
- (uint32_t) PWRWU_IRQHandler, // 2: Power Down Wake Up
- (uint32_t) SRAMF_IRQHandler, // 3: Reserved.
- (uint32_t) CLKF_IRQHandler, // 4: CLKF
- (uint32_t) Default_Handler, // 5: Reserved.
- (uint32_t) RTC_IRQHandler, // 6: Real Time Clock
- (uint32_t) TAMPER_IRQHandler, // 7: Tamper detection
- (uint32_t) EINT0_IRQHandler, // 8: External Input 0
- (uint32_t) EINT1_IRQHandler, // 9: External Input 1
- (uint32_t) EINT2_IRQHandler, // 10: External Input 2
- (uint32_t) EINT3_IRQHandler, // 11: External Input 3
- (uint32_t) EINT4_IRQHandler, // 12: External Input 4
- (uint32_t) EINT5_IRQHandler, // 13: External Input 5
- (uint32_t) EINT6_IRQHandler, // 14: External Input 6
- (uint32_t) EINT7_IRQHandler, // 15: External Input 7
- (uint32_t) GPA_IRQHandler, // 16: GPIO Port A
- (uint32_t) GPB_IRQHandler, // 17: GPIO Port B
- (uint32_t) GPC_IRQHandler, // 18: GPIO Port C
- (uint32_t) GPD_IRQHandler, // 19: GPIO Port D
- (uint32_t) GPE_IRQHandler, // 20: GPIO Port E
- (uint32_t) GPF_IRQHandler, // 21: GPIO Port F
- (uint32_t) GPG_IRQHandler, // 22: GPIO Port G
- (uint32_t) GPH_IRQHandler, // 23: GPIO Port H
- (uint32_t) GPI_IRQHandler, // 24: GPIO Port I
- (uint32_t) Default_Handler, // 25: Reserved.
- (uint32_t) Default_Handler, // 26: Reserved.
- (uint32_t) Default_Handler, // 27: Reserved.
- (uint32_t) Default_Handler, // 28: Reserved.
- (uint32_t) Default_Handler, // 29: Reserved.
- (uint32_t) Default_Handler, // 30: Reserved.
- (uint32_t) Default_Handler, // 31: Reserved.
- (uint32_t) TMR0_IRQHandler, // 32: Timer 0
- (uint32_t) TMR1_IRQHandler, // 33: Timer 1
- (uint32_t) TMR2_IRQHandler, // 34: Timer 2
- (uint32_t) TMR3_IRQHandler, // 35: Timer 3
- (uint32_t) Default_Handler, // 36: Reserved.
- (uint32_t) Default_Handler, // 37: Reserved.
- (uint32_t) Default_Handler, // 38: Reserved.
- (uint32_t) Default_Handler, // 39: Reserved.
- (uint32_t) PDMA_IRQHandler, // 40: Peripheral DMA
- (uint32_t) Default_Handler, // 41: Reserved.
- (uint32_t) ADC_IRQHandler, // 42: ADC
- (uint32_t) Default_Handler, // 43: Reserved.
- (uint32_t) Default_Handler, // 44: Reserved.
- (uint32_t) Default_Handler, // 45: Reserved.
- (uint32_t) WDT_IRQHandler, // 46: Watch Dog Timer
- (uint32_t) WWDT_IRQHandler, // 47: Window Watch Dog Timer
- (uint32_t) EADC0_IRQHandler, // 48: EDAC 0
- (uint32_t) EADC1_IRQHandler, // 49: EDAC 1
- (uint32_t) EADC2_IRQHandler, // 50: EDAC 2
- (uint32_t) EADC3_IRQHandler, // 51: EDAC 3
- (uint32_t) Default_Handler, // 52: Reserved.
- (uint32_t) Default_Handler, // 53: Reserved.
- (uint32_t) Default_Handler, // 54: Reserved.
- (uint32_t) Default_Handler, // 55: Reserved.
- (uint32_t) ACMP_IRQHandler, // 56: Analog Comparator
- (uint32_t) Default_Handler, // 57: Reserved.
- (uint32_t) Default_Handler, // 58: Reserved.
- (uint32_t) Default_Handler, // 59: Reserved.
- (uint32_t) OPA0_IRQHandler, // 60: OPA 0
- (uint32_t) OPA1_IRQHandler, // 61: OPA 1
- (uint32_t) ICAP0_IRQHandler, // 62: ICAP 0
- (uint32_t) ICAP1_IRQHandler, // 63: ICAP 1
- (uint32_t) PWM0CH0_IRQHandler, // 64: PWM0 CH0
- (uint32_t) PWM0CH1_IRQHandler, // 65: PWM0 CH1
- (uint32_t) PWM0CH2_IRQHandler, // 66: PWM0 CH2
- (uint32_t) PWM0CH3_IRQHandler, // 67: PWM0 CH3
- (uint32_t) PWM0CH4_IRQHandler, // 68: PWM0 CH4
- (uint32_t) PWM0CH5_IRQHandler, // 69: PWM0 CH5
- (uint32_t) PWM0_BRK_IRQHandler, // 70: PWM0 Break
- (uint32_t) QEI0_IRQHandler, // 71: QEI 0
- (uint32_t) PWM1CH0_IRQHandler, // 72: PWM1 CH0
- (uint32_t) PWM1CH1_IRQHandler, // 73: PWM1 CH1
- (uint32_t) PWM1CH2_IRQHandler, // 74: PWM1 CH2
- (uint32_t) PWM1CH3_IRQHandler, // 75: PWM1 CH3
- (uint32_t) PWM1CH4_IRQHandler, // 76: PWM1 CH4
- (uint32_t) PWM1CH5_IRQHandler, // 77: PWM1 CH5
- (uint32_t) PWM1_BRK_IRQHandler, // 78: PWM1 Break
- (uint32_t) QEI1_IRQHandler, // 79: QEI 1
- (uint32_t) EPWM0_IRQHandler, // 80: EPWM0
- (uint32_t) EPWM0BRK_IRQHandler, // 81: EPWM0 Break
- (uint32_t) EPWM1_IRQHandler, // 82: EPWM1
- (uint32_t) EPWM1BRK_IRQHandler, // 83: EPWM1 Break
- (uint32_t) Default_Handler, // 84: Reserved.
- (uint32_t) Default_Handler, // 85: Reserved.
- (uint32_t) Default_Handler, // 86: Reserved.
- (uint32_t) Default_Handler, // 87: Reserved.
- (uint32_t) USBD_IRQHandler, // 88: USB Device
- (uint32_t) USBH_IRQHandler, // 89: USB Host
- (uint32_t) USB_OTG_IRQHandler, // 90: USB OTG
- (uint32_t) Default_Handler, // 91: Reserved.
- (uint32_t) EMAC_TX_IRQHandler, // 92: Ethernet MAC TX
- (uint32_t) EMAC_RX_IRQHandler, // 93: Ethernet MAC RX
- (uint32_t) Default_Handler, // 94: Reserved.
- (uint32_t) Default_Handler, // 95: Reserved.
- (uint32_t) SPI0_IRQHandler, // 96: SPI 0
- (uint32_t) SPI1_IRQHandler, // 97: SPI 1
- (uint32_t) SPI2_IRQHandler, // 98: SPI 2
- (uint32_t) SPI3_IRQHandler, // 99: SPI 3
- (uint32_t) Default_Handler, // 100: Reserved.
- (uint32_t) Default_Handler, // 101: Reserved.
- (uint32_t) Default_Handler, // 102: Reserved.
- (uint32_t) Default_Handler, // 103: Reserved.
- (uint32_t) UART0_IRQHandler, // 104: UART 0
- (uint32_t) UART1_IRQHandler, // 105: UART 1
- (uint32_t) UART2_IRQHandler, // 106: UART 2
- (uint32_t) UART3_IRQHandler, // 107: UART 3
- (uint32_t) UART4_IRQHandler, // 108: UART 4
- (uint32_t) UART5_IRQHandler, // 109: UART 5
- (uint32_t) Default_Handler, // 110: Reserved.
- (uint32_t) Default_Handler, // 111: Reserved.
- (uint32_t) I2C0_IRQHandler, // 112: I2C 0
- (uint32_t) I2C1_IRQHandler, // 113: I2C 1
- (uint32_t) I2C2_IRQHandler, // 114: I2C 2
- (uint32_t) I2C3_IRQHandler, // 115: I2C 3
- (uint32_t) I2C4_IRQHandler, // 116: I2C 4
- (uint32_t) Default_Handler, // 117: Reserved.
- (uint32_t) Default_Handler, // 118: Reserved.
- (uint32_t) Default_Handler, // 119: Reserved.
- (uint32_t) SC0_IRQHandler, // 120: Smart Card 0
- (uint32_t) SC1_IRQHandler, // 121: Smart Card 1
- (uint32_t) SC2_IRQHandler, // 122: Smart Card 2
- (uint32_t) SC3_IRQHandler, // 123: Smart Card 3
- (uint32_t) SC4_IRQHandler, // 124: Smart Card 4
- (uint32_t) SC5_IRQHandler, // 125: Smart Card 5
- (uint32_t) Default_Handler, // 126: Reserved.
- (uint32_t) Default_Handler, // 127: Reserved.
- (uint32_t) CAN0_IRQHandler, // 128: CAN 0
- (uint32_t) CAN1_IRQHandler, // 129: CAN 1
- (uint32_t) Default_Handler, // 130: Reserved.
- (uint32_t) Default_Handler, // 131: Reserved.
- (uint32_t) I2S0_IRQHandler, // 132: I2S 0
- (uint32_t) I2S1_IRQHandler, // 133: I2S 1
- (uint32_t) Default_Handler, // 134: Reserved.
- (uint32_t) Default_Handler, // 135: Reserved.
- (uint32_t) SD_IRQHandler, // 136: SD card
- (uint32_t) Default_Handler, // 137: Reserved.
- (uint32_t) PS2D_IRQHandler, // 138: PS/2 device
- (uint32_t) CAP_IRQHandler, // 139: VIN
- (uint32_t) CRYPTO_IRQHandler, // 140: CRYPTO
- (uint32_t) CRC_IRQHandler, // 141: CRC
-};
-
-/**
- * \brief This is the code that gets called on processor reset.
- */
-void Reset_Handler(void)
-{
- /* Disable register write-protection function */
- SYS_UnlockReg();
-
- /* Disable branch buffer if VCID is 0 */
- if (SYS->VCID == 0) {
- FMC->FTCTL |= 0x80;
- }
-
- /* Disable Power-on Reset function */
- SYS_DISABLE_POR();
-
- /* Enable register write-protection function */
- SYS_LockReg();
-
- /**
- * Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.
- */
- SystemInit();
-
-#if defined(__CC_ARM)
- __main();
-
-#elif defined(__ICCARM__)
- __iar_program_start();
-
-#elif defined(__GNUC__)
- uint32_t *src_ind = (uint32_t *) &__etext;
- uint32_t *dst_ind = (uint32_t *) &__data_start__;
- uint32_t *dst_end = (uint32_t *) &__data_end__;
-
- /* Move .data section from ROM to RAM */
- if (src_ind != dst_ind) {
- for (; dst_ind < dst_end;) {
- *dst_ind ++ = *src_ind ++;
- }
- }
-
- /* Initialize .bss section to zero */
- dst_ind = (uint32_t *) &__bss_start__;
- dst_end = (uint32_t *) &__bss_end__;
- if (dst_ind != dst_end) {
- for (; dst_ind < dst_end;) {
- *dst_ind ++ = 0;
- }
- }
-
- /* Initialize .bss.extern section to zero */
- dst_ind = (uint32_t *) &__bss_extern_start__;
- dst_end = (uint32_t *) &__bss_extern_end__;
- if (dst_ind != dst_end) {
- for (; dst_ind < dst_end;) {
- *dst_ind ++ = 0;
- }
- }
-
- //uvisor_init();
-
- if (software_init_hook) {
- /**
- * Give control to the RTOS via software_init_hook() which will also call __libc_init_array().
- * Assume software_init_hook() is defined in libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h.
- */
- software_init_hook();
- }
- else {
- __libc_init_array();
- main();
- }
-
-#endif
- /* Infinite loop */
- while (1);
-}
-
-/**
- * \brief Default interrupt handler for unused IRQs.
- */
-void Default_Handler(void)
-{
- while (1);
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-/**************************************************************************//**
- * @file system_NUC472_442.c
- * @version V1.00
- * $Revision: 15 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 system clock init code and assert handler
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
-*****************************************************************************/
-
-#include "NUC472_442.h"
-//#include "rtc.h"
-
-/*----------------------------------------------------------------------------
- Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock)*/
-uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
-uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC}; /*!< System clock source table */
-
-#if defined TARGET_NUMAKER_PFM_NUC472
-static void nu_ebi_init(void);
-#endif
-
-/*----------------------------------------------------------------------------
- Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
-{
- uint32_t u32Freq, u32ClkSrc;
- uint32_t u32HclkDiv;
-
- u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
-
- if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL) {
- /* Use the clock sources directly */
- u32Freq = gau32ClkSrcTbl[u32ClkSrc];
- } else {
- /* Use PLL clock */
- u32Freq = CLK_GetPLLClockFreq();
- }
-
- u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
-
- /* Update System Core Clock */
- SystemCoreClock = u32Freq/u32HclkDiv;
-
- CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
-}
-
-/**
- * Initialize the system
- *
- * @return none
- *
- * @brief Setup the microcontroller system.
- */
-void SystemInit (void)
-{
- //uint32_t u32RTC_EN_Flag = 0;
-
- /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
- (3UL << 11*2) ); /* set CP11 Full Access */
-#endif
-
- /* The code snippet below is for old-version chip and has potential risk, e.g. program reboots and hangs in it with the call to NVIC_SystemReset(). Remove it for new-version chip. */
-#if 0
- /* ------------------ Release Tamper pin ---------------------------------*/
- /* Waiting for 10kHz clock ready */
- CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
-
- u32RTC_EN_Flag = ((CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk) >> CLK_APBCLK0_RTCCKEN_Pos);
-
- if(!u32RTC_EN_Flag) {
- CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Enable
- }
-
- RTC->INIT = RTC_INIT_KEY;
- while(RTC->INIT != 0x1);
-
- if(!(RTC->TAMPCTL & RTC_TAMPCTL_TIEN_Msk)) {
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
-
- while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->SPR[23] = RTC->SPR[23];
- while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
- while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
-
- RTC->RWEN = RTC_WRITE_KEY;
- while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
-
- RTC->INTSTS = RTC_INTSTS_TICKIF_Msk;
- }
-
- if(!u32RTC_EN_Flag) {
- CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Disable
- }
- /*------------------------------------------------------------------------*/
-#endif
-
-#if defined TARGET_NUMAKER_PFM_NUC472
- // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
- nu_ebi_init();
-#endif
-}
-
-#if defined TARGET_NUMAKER_PFM_NUC472
-void nu_ebi_init(void)
-{
- /* Enable IP clock */
- CLK_EnableModuleClock(EBI_MODULE);
-
- /* Configure EBI multi-function pins */
- SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA10MFP_Msk) ) | SYS_GPA_MFPH_PA10MFP_EBI_A20; /* A20. = PA10 */
- SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA9MFP_Msk) ) | SYS_GPA_MFPH_PA9MFP_EBI_A19; /* A19. = PA9 */
- SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA8MFP_Msk) ) | SYS_GPA_MFPH_PA8MFP_EBI_A18; /* A18. = PA8 */
- SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA7MFP_Msk) ) | SYS_GPA_MFPL_PA7MFP_EBI_A17; /* A17. = PA7 */
- SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA6MFP_Msk) ) | SYS_GPA_MFPL_PA6MFP_EBI_A16; /* A16. = PA6 */
- SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB13MFP_Msk) ) | SYS_GPB_MFPH_PB13MFP_EBI_AD15; /* AD15 = PB13 */
-
- SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB12MFP_Msk) ) | SYS_GPB_MFPH_PB12MFP_EBI_AD14; /* AD14 = PB12 */
- SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB11MFP_Msk) ) | SYS_GPB_MFPH_PB11MFP_EBI_AD13; /* AD13 = PB11 */
- SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB10MFP_Msk) ) | SYS_GPB_MFPH_PB10MFP_EBI_AD12; /* AD12 = PB10 */
- SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB9MFP_Msk) ) | SYS_GPB_MFPH_PB9MFP_EBI_AD11; /* AD11 = PB9 */
- SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB8MFP_Msk) ) | SYS_GPB_MFPH_PB8MFP_EBI_AD10; /* AD10 = PB8 */
-
- SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB7MFP_Msk) ) | SYS_GPB_MFPL_PB7MFP_EBI_AD9; /* AD9 = PB7 */
- SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB6MFP_Msk) ) | SYS_GPB_MFPL_PB6MFP_EBI_AD8; /* AD8 = PB6 */
- SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB5MFP_Msk) ) | SYS_GPB_MFPL_PB5MFP_EBI_AD7; /* AD7 = PB5 */
- SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB4MFP_Msk) ) | SYS_GPB_MFPL_PB4MFP_EBI_AD6; /* AD6 = PB4 */
- SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB3MFP_Msk) ) | SYS_GPB_MFPL_PB3MFP_EBI_AD5; /* AD5 = PB3 */
- SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB2MFP_Msk) ) | SYS_GPB_MFPL_PB2MFP_EBI_AD4; /* AD4 = PB2 */
-
- SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA14MFP_Msk) ) | SYS_GPA_MFPH_PA14MFP_EBI_AD3; /* AD3. = PA14 */
- SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA13MFP_Msk) ) | SYS_GPA_MFPH_PA13MFP_EBI_AD2; /* AD2. = PA13 */
- SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA12MFP_Msk) ) | SYS_GPA_MFPH_PA12MFP_EBI_AD1; /* AD1. = PA12 */
- SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA11MFP_Msk) ) | SYS_GPA_MFPH_PA11MFP_EBI_AD0; /* AD0. = PA11 */
-
- SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE6MFP_Msk) ) | SYS_GPE_MFPL_PE6MFP_EBI_nWR; /* PE.6 = nWR */
- SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE7MFP_Msk) ) | SYS_GPE_MFPL_PE7MFP_EBI_nRD; /* PE.7 = nRD */
- SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE8MFP_Msk) ) | SYS_GPE_MFPH_PE8MFP_EBI_ALE; /* PE.8 = ALE */
- SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE9MFP_Msk) ) | SYS_GPE_MFPH_PE9MFP_EBI_nWRH; /* PE.9 = WRH */
- SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE10MFP_Msk) ) | SYS_GPE_MFPH_PE10MFP_EBI_nWRL; /* PE.10 = WRL */
-
- SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE11MFP_Msk) ) | SYS_GPE_MFPH_PE11MFP_EBI_nCS0; /* PE.11 = nCS0 */
- SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE12MFP_Msk) ) | SYS_GPE_MFPH_PE12MFP_EBI_nCS1; /* PE.12 = nCS1 */
- SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE13MFP_Msk) ) | SYS_GPE_MFPH_PE13MFP_EBI_nCS2; /* PE.13 = nCS2 */
- SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE14MFP_Msk) ) | SYS_GPE_MFPH_PE14MFP_EBI_nCS3; /* PE.14 = nCS3 */
-
- const uint32_t u32Timing = 0x21C;
-
- /* Open EBI interface */
- EBI_Open(EBI_BANK0, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
- EBI_Open(EBI_BANK1, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
- EBI_Open(EBI_BANK2, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
- EBI_Open(EBI_BANK3, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
-
- /* Configure EBI timing */
- EBI_SetBusTiming(EBI_BANK0, u32Timing, EBI_MCLKDIV_2);
- EBI_SetBusTiming(EBI_BANK1, u32Timing, EBI_MCLKDIV_2);
- EBI_SetBusTiming(EBI_BANK2, u32Timing, EBI_MCLKDIV_2);
- EBI_SetBusTiming(EBI_BANK3, u32Timing, EBI_MCLKDIV_2);
-}
-#endif
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/**************************************************************************//**
- * @file system_NUC472_442.h
- * @version V1.00
- * $Revision: 5 $
- * $Date: 14/05/29 1:13p $
- * @brief NUC472/NUC442 system clock definition file
- *
- * @note
- * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
- *****************************************************************************/
-#ifndef __SYSTEM_NUC472_442_H__
-#define __SYSTEM_NUC472_442_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-#define __HXT (12000000UL) /*!< High Speed External Crystal Clock Frequency 12MHz */
-#define __LXT (32768UL) /*!< Low Speed External Crystal Clock Frequency 32.768kHz */
-#define __HIRC (22118400UL) /*!< High Speed Internal 22MHz RC Oscillator Frequency */
-#define __LIRC (10000UL) /*!< Low Speed Internal 10kHz RC Oscillator Frequency */
-#define __HSI (__HIRC) /* Factory Default is internal 12MHz */
-
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
-extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
-
-
-/**
- * Initialize the system
- *
- * @return none
- *
- * @brief Setup the microcontroller system.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from CPU registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_NUC472_442_H__ */
-/*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/dma.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_DMA_H
-#define MBED_DMA_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DMA_CAP_NONE (0 << 0)
-
-#define DMA_EVENT_ABORT (1 << 0)
-#define DMA_EVENT_TRANSFER_DONE (1 << 1)
-#define DMA_EVENT_TIMEOUT (1 << 2)
-#define DMA_EVENT_ALL (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT)
-#define DMA_EVENT_MASK DMA_EVENT_ALL
-
-void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,178 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "dma_api.h"
-#include "string.h"
-#include "cmsis.h"
-#include "mbed_assert.h"
-#include "PeripheralNames.h"
-#include "nu_modutil.h"
-#include "nu_bitutil.h"
-#include "dma.h"
-
-struct nu_dma_chn_s {
- void (*handler)(uint32_t, uint32_t);
- uint32_t id;
- uint32_t event;
-};
-
-static int dma_inited = 0;
-static uint32_t dma_chn_mask = 0;
-static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX];
-
-static void pdma_vec(void);
-static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec};
-
-
-void dma_init(void)
-{
- if (dma_inited) {
- return;
- }
-
- dma_inited = 1;
- dma_chn_mask = 0;
- memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
-
- // Reset this module
- SYS_ResetModule(dma_modinit.rsetidx);
-
- // Enable IP clock
- CLK_EnableModuleClock(dma_modinit.clkidx);
-
- PDMA_Open(0);
-
- NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
- NVIC_EnableIRQ(dma_modinit.irq_n);
-}
-
-int dma_channel_allocate(uint32_t capabilities)
-{
- if (! dma_inited) {
- dma_init();
- }
-
-#if 1
- int i = nu_cto(dma_chn_mask);
- if (i != 32) {
- dma_chn_mask |= 1 << i;
- memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
- return i;
- }
-#else
- int i;
-
- for (i = 0; i < PDMA_CH_MAX; i ++) {
- if ((dma_chn_mask & (1 << i)) == 0) {
- // Channel available
- dma_chn_mask |= 1 << i;
- memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
- return i;
- }
- }
-#endif
-
- // No channel available
- return DMA_ERROR_OUT_OF_CHANNELS;
-}
-
-int dma_channel_free(int channelid)
-{
- if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_chn_mask &= ~(1 << channelid);
- }
-
- return 0;
-}
-
-void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
-{
- MBED_ASSERT(dma_chn_mask & (1 << channelid));
-
- dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler;
- dma_chn_arr[channelid].id = id;
- dma_chn_arr[channelid].event = event;
-
- // Set interrupt vector if someone has removed it.
- NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
- NVIC_EnableIRQ(dma_modinit.irq_n);
-}
-
-static void pdma_vec(void)
-{
- uint32_t intsts = PDMA_GET_INT_STATUS();
-
- // Abort
- if (intsts & PDMA_INTSTS_ABTIF_Msk) {
- uint32_t abtsts = PDMA_GET_ABORT_STS();
- // Clear all Abort flags
- PDMA_CLR_ABORT_FLAG(abtsts);
-
- while (abtsts) {
- int chn_id = nu_ctz(abtsts);
- if (dma_chn_mask & (1 << chn_id)) {
- struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
- if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
- dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
- }
- }
- abtsts &= ~(1 << chn_id);
- }
- }
-
- // Transfer done
- if (intsts & PDMA_INTSTS_TDIF_Msk) {
- uint32_t tdsts = PDMA_GET_TD_STS();
- // Clear all transfer done flags
- PDMA_CLR_TD_FLAG(tdsts);
-
- while (tdsts) {
- int chn_id = nu_ctz(tdsts);
- if (dma_chn_mask & (1 << chn_id)) {
- struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
- if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
- dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
- }
- }
- tdsts &= ~(1 << chn_id);
- }
- }
-
- // Table empty
- if (intsts & PDMA_INTSTS_TEIF_Msk) {
- uint32_t scatsts = PDMA_GET_EMPTY_STS();
- // Clear all table empty flags
- PDMA_CLR_EMPTY_FLAG(scatsts);
- }
-
- // Timeout
- uint32_t reqto = intsts & PDMA_INTSTS_REQTOFX_Msk;
- if (reqto) {
- // Clear all Timeout flags
- PDMA->INTSTS = reqto;
-
- while (reqto) {
- int chn_id = nu_ctz(reqto) >> PDMA_INTSTS_REQTOFX_Pos;
- if (dma_chn_mask & (1 << chn_id)) {
- struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
- if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
- dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
- }
- }
- reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFX_Pos));
- }
- }
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "gpio_api.h"
-#include "mbed_assert.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-uint32_t gpio_set(PinName pin)
-{
- if (pin == (PinName) NC) {
- return 0;
- }
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
-
-#if 1
- pin_function(pin, 0 << NU_MFP_POS(pin_index));
-#else
- pinmap_pinout(pin, PinMap_GPIO);
-#endif
-
- return (uint32_t)(1 << pin_index); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
- obj->pin = pin;
-
- if (obj->pin == (PinName) NC) {
- return;
- }
-
- obj->mask = gpio_set(pin);
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
- if (obj->pin == (PinName) NC) {
- return;
- }
-
- pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
- if (obj->pin == (PinName) NC) {
- return;
- }
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
- switch (direction) {
- case PIN_INPUT:
- mode_intern = GPIO_MODE_INPUT;
- break;
-
- case PIN_OUTPUT:
- mode_intern = GPIO_MODE_OUTPUT;
- break;
-
- default:
- return;
- }
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,244 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "gpio_irq_api.h"
-
-#if DEVICE_INTERRUPTIN
-
-#include "gpio_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_bitutil.h"
-
-#define NU_MAX_PIN_PER_PORT 16
-
-struct nu_gpio_irq_var {
- gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
- IRQn_Type irq_n;
- void (*vec)(void);
-};
-
-static void gpio_irq_0_vec(void);
-static void gpio_irq_1_vec(void);
-static void gpio_irq_2_vec(void);
-static void gpio_irq_3_vec(void);
-static void gpio_irq_4_vec(void);
-static void gpio_irq_5_vec(void);
-static void gpio_irq_6_vec(void);
-static void gpio_irq_7_vec(void);
-static void gpio_irq_8_vec(void);
-static void gpio_irq(struct nu_gpio_irq_var *var);
-
-//EINT0_IRQn
-static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
- {{NULL}, GPA_IRQn, gpio_irq_0_vec},
- {{NULL}, GPB_IRQn, gpio_irq_1_vec},
- {{NULL}, GPC_IRQn, gpio_irq_2_vec},
- {{NULL}, GPD_IRQn, gpio_irq_3_vec},
- {{NULL}, GPE_IRQn, gpio_irq_4_vec},
- {{NULL}, GPF_IRQn, gpio_irq_5_vec},
- {{NULL}, GPG_IRQn, gpio_irq_6_vec},
- {{NULL}, GPH_IRQn, gpio_irq_7_vec},
- {{NULL}, GPI_IRQn, gpio_irq_8_vec}
-};
-
-#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
-
-#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
-#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
-#else
-#define NUC472_GPIO_IRQ_DEBOUNCE_ENABLE 0
-#endif
-
-#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
-#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
-#else
-#define NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_IRC10K
-#endif
-
-#ifdef MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
-#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE MBED_CONF_NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
-#else
-#define NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
-#endif
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
-{
- if (pin == NC) {
- return -1;
- }
-
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(pin);
- if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
- return -1;
- }
-
- obj->pin = pin;
- obj->irq_handler = (uint32_t) handler;
- obj->irq_id = id;
-
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
- //gpio_set(pin);
-
-#if NUC472_GPIO_IRQ_DEBOUNCE_ENABLE
- // Configure de-bounce clock source and sampling cycle time
- GPIO_SET_DEBOUNCE_TIME(NUC472_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, NUC472_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
- GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
-#else
- GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
-#endif
-
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- var->obj_arr[pin_index] = obj;
-
- // NOTE: InterruptIn requires IRQ enabled by default.
- gpio_irq_enable(obj);
-
- return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj)
-{
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- NVIC_DisableIRQ(var->irq_n);
- NU_PORT_BASE(port_index)->INTEN = 0;
-
- MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
- var->obj_arr[pin_index] = NULL;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
-{
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- switch (event) {
- case IRQ_RISE:
- if (enable) {
- GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
- }
- else {
- gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
- }
- break;
-
- case IRQ_FALL:
- if (enable) {
- GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
- }
- else {
- gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
- }
- break;
- }
-}
-
-void gpio_irq_enable(gpio_irq_t *obj)
-{
- //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
- NVIC_EnableIRQ(var->irq_n);
-}
-
-void gpio_irq_disable(gpio_irq_t *obj)
-{
- //uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
- struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
-
- NVIC_DisableIRQ(var->irq_n);
-}
-
-static void gpio_irq_0_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 0);
-}
-static void gpio_irq_1_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 1);
-}
-static void gpio_irq_2_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 2);
-}
-static void gpio_irq_3_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 3);
-}
-static void gpio_irq_4_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 4);
-}
-static void gpio_irq_5_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 5);
-}
-static void gpio_irq_6_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 6);
-}
-static void gpio_irq_7_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 7);
-}
-static void gpio_irq_8_vec(void)
-{
- gpio_irq(gpio_irq_var_arr + 8);
-}
-
-static void gpio_irq(struct nu_gpio_irq_var *var)
-{
- uint32_t port_index = var->irq_n - GPA_IRQn;
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t intsrc = gpio_base->INTSRC;
- uint32_t inten = gpio_base->INTEN;
- while (intsrc) {
- int pin_index = nu_ctz(intsrc);
- gpio_irq_t *obj = var->obj_arr[pin_index];
- if (inten & (GPIO_INT_RISING << pin_index)) {
- if (GPIO_PIN_ADDR(port_index, pin_index)) {
- if (obj->irq_handler) {
- ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
- }
- }
- }
-
- if (inten & (GPIO_INT_FALLING << pin_index)) {
- if (! GPIO_PIN_ADDR(port_index, pin_index)) {
- if (obj->irq_handler) {
- ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
- }
- }
- }
-
- intsrc &= ~(1 << pin_index);
- }
- // Clear all interrupt flags
- gpio_base->INTSRC = gpio_base->INTSRC;
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_object.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- uint32_t mask;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
-
- GPIO_PIN_ADDR(port_index, pin_index) = value ? 1 : 0;
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- MBED_ASSERT(obj->pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
-
- return (GPIO_PIN_ADDR(port_index, pin_index) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1048 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "i2c_api.h"
-
-#if DEVICE_I2C
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "nu_bitutil.h"
-#include "critical.h"
-
-#define NU_I2C_DEBUG 0
-
-#if NU_I2C_DEBUG
-struct i2c_s MY_I2C;
-struct i2c_s MY_I2C_2;
-char MY_I2C_STATUS[64];
-int MY_I2C_STATUS_POS = 0;
-uint32_t MY_I2C_TIMEOUT;
-uint32_t MY_I2C_ELAPSED;
-uint32_t MY_I2C_T1;
-uint32_t MY_I2C_T2;
-#endif
-
-struct nu_i2c_var {
- i2c_t * obj;
- void (*vec)(void);
-};
-
-static void i2c0_vec(void);
-static void i2c1_vec(void);
-static void i2c2_vec(void);
-static void i2c3_vec(void);
-static void i2c4_vec(void);
-static void i2c_irq(i2c_t *obj);
-static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
-
-static struct nu_i2c_var i2c0_var = {
- .obj = NULL,
- .vec = i2c0_vec,
-};
-static struct nu_i2c_var i2c1_var = {
- .obj = NULL,
- .vec = i2c1_vec,
-};
-static struct nu_i2c_var i2c2_var = {
- .obj = NULL,
- .vec = i2c2_vec,
-};
-static struct nu_i2c_var i2c3_var = {
- .obj = NULL,
- .vec = i2c3_vec,
-};
-static struct nu_i2c_var i2c4_var = {
- .obj = NULL,
- .vec = i2c4_vec,
-};
-
-static uint32_t i2c_modinit_mask = 0;
-
-static const struct nu_modinit_s i2c_modinit_tab[] = {
- {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
- {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
- {I2C_2, I2C2_MODULE, 0, 0, I2C2_RST, I2C2_IRQn, &i2c2_var},
- {I2C_3, I2C3_MODULE, 0, 0, I2C3_RST, I2C3_IRQn, &i2c3_var},
- {I2C_4, I2C4_MODULE, 0, 0, I2C4_RST, I2C4_IRQn, &i2c4_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
-static int i2c_do_write(i2c_t *obj, char data, int naklastdata);
-static int i2c_do_read(i2c_t *obj, char *data, int naklastdata);
-static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
-#define NU_I2C_TIMEOUT_STAT_INT 500000
-#define NU_I2C_TIMEOUT_STOP 500000
-static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
-static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
-//static int i2c_is_stat_int(i2c_t *obj);
-//static int i2c_is_stop_det(i2c_t *obj);
-static int i2c_is_trsn_done(i2c_t *obj);
-static int i2c_is_tran_started(i2c_t *obj);
-static int i2c_addr2data(int address, int read);
-#if DEVICE_I2CSLAVE
-// Convert mbed address to BSP address.
-static int i2c_addr2bspaddr(int address);
-#endif // #if DEVICE_I2CSLAVE
-static void i2c_enable_int(i2c_t *obj);
-static void i2c_disable_int(i2c_t *obj);
-static int i2c_set_int(i2c_t *obj, int inten);
-
-#if DEVICE_I2C_ASYNCH
-static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
-static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
-static void i2c_rollback_vector_interrupt(i2c_t *obj);
-#endif
-
-#define TRANCTRL_STARTED (1)
-#define TRANCTRL_NAKLASTDATA (1 << 1)
-
-uint32_t us_ticker_read(void);
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl)
-{
- uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
- uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
- obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
- MBED_ASSERT((int)obj->i2c.i2c != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- pinmap_pinout(sda, PinMap_I2C_SDA);
- pinmap_pinout(scl, PinMap_I2C_SCL);
-
-#if DEVICE_I2C_ASYNCH
- obj->i2c.dma_usage = DMA_USAGE_NEVER;
- obj->i2c.event = 0;
- obj->i2c.stop = 0;
- obj->i2c.address = 0;
-#endif
-
- // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
- I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
- // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL. We cannot control interrupt through
- // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- i2c_base->CTL |= (I2C_CTL_INTEN_Msk | I2C_CTL_I2CEN_Msk);
-
- // Enable sync-moce vector interrupt.
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- var->obj = obj;
- obj->i2c.tran_ctrl = 0;
- obj->i2c.stop = 0;
- i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
-
- // Mark this module to be inited.
- int i = modinit - i2c_modinit_tab;
- i2c_modinit_mask |= 1 << i;
-}
-
-int i2c_start(i2c_t *obj)
-{
- return i2c_do_trsn(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk, 1);
-}
-
-int i2c_stop(i2c_t *obj)
-{
- return i2c_do_trsn(obj, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk, 1);
-}
-
-void i2c_frequency(i2c_t *obj, int hz)
-{
- I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
-}
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
-{
- if (i2c_start(obj)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- if (i2c_do_write(obj, i2c_addr2data(address, 1), 0)) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- // Read in bytes
- length = i2c_do_tran(obj, data, length, 1, 1);
-
- // If not repeated start, send stop.
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
-{
- if (i2c_start(obj)) {
- i2c_stop(obj);
- return I2C_ERROR_BUS_BUSY;
- }
-
- if (i2c_do_write(obj, i2c_addr2data(address, 0), 0)) {
- i2c_stop(obj);
- return I2C_ERROR_NO_SLAVE;
- }
-
- // Write out bytes
- length = i2c_do_tran(obj, (char *) data, length, 0, 1);
-
- if (stop) {
- i2c_stop(obj);
- }
-
- return length;
-}
-
-void i2c_reset(i2c_t *obj)
-{
- i2c_stop(obj);
-}
-
-int i2c_byte_read(i2c_t *obj, int last)
-{
- char data = 0;
-
- i2c_do_read(obj, &data, last);
- return data;
-}
-
-int i2c_byte_write(i2c_t *obj, int data)
-{
- return i2c_do_write(obj, (data & 0xFF), 0);
-}
-
-#if DEVICE_I2CSLAVE
-
-// See I2CSlave.h
-#define NoData 0 // the slave has not been addressed
-#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
-#define WriteGeneral 2 // the master is writing to all slave
-#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- i2c_disable_int(obj);
-
- obj->i2c.slaveaddr_state = NoData;
-
- // Switch to not addressed mode
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
-
- i2c_enable_int(obj);
-}
-
-int i2c_slave_receive(i2c_t *obj)
-{
- int slaveaddr_state;
-
- i2c_disable_int(obj);
- slaveaddr_state = obj->i2c.slaveaddr_state;
- i2c_enable_int(obj);
-
- return slaveaddr_state;
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length)
-{
- return i2c_do_tran(obj, data, length, 1, 1);
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length)
-{
- return i2c_do_tran(obj, (char *) data, length, 0, 1);
-}
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- i2c_disable_int(obj);
-
- I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_ENABLE);
-
- i2c_enable_int(obj);
-}
-
-static int i2c_addr2bspaddr(int address)
-{
- return (address >> 1);
-}
-
-#endif // #if DEVICE_I2CSLAVE
-
-static void i2c_enable_int(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
-
- core_util_critical_section_enter();
-
- // Enable I2C interrupt
- NVIC_EnableIRQ(modinit->irq_n);
- obj->i2c.inten = 1;
-
- core_util_critical_section_exit();
-}
-
-static void i2c_disable_int(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
-
- core_util_critical_section_enter();
-
- // Disable I2C interrupt
- NVIC_DisableIRQ(modinit->irq_n);
- obj->i2c.inten = 0;
-
- core_util_critical_section_exit();
-}
-
-static int i2c_set_int(i2c_t *obj, int inten)
-{
- int inten_back;
-
- core_util_critical_section_enter();
-
- inten_back = obj->i2c.inten;
-
- core_util_critical_section_exit();
-
- if (inten) {
- i2c_enable_int(obj);
- }
- else {
- i2c_disable_int(obj);
- }
-
- return inten_back;
-}
-
-int i2c_allow_powerdown(void)
-{
- uint32_t modinit_mask = i2c_modinit_mask;
- while (modinit_mask) {
- int i2c_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- if (var->obj) {
- // Disallow entering power-down mode if I2C transfer is enabled.
- if (i2c_active(var->obj)) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << i2c_idx);
- }
-
- return 1;
-}
-
-static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
-{
- int tran_len = 0;
-
- i2c_disable_int(obj);
- obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
- obj->i2c.tran_beg = buf;
- obj->i2c.tran_pos = buf;
- obj->i2c.tran_end = buf + length;
- i2c_enable_int(obj);
-
- if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
-#if NU_I2C_DEBUG
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- }
- else {
- i2c_disable_int(obj);
- obj->i2c.tran_ctrl = 0;
- tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
- obj->i2c.tran_beg = NULL;
- obj->i2c.tran_pos = NULL;
- obj->i2c.tran_end = NULL;
- i2c_enable_int(obj);
- }
-
- return tran_len;
-}
-
-static int i2c_do_write(i2c_t *obj, char data, int naklastdata)
-{
- char data_[1];
- data_[0] = data;
- return i2c_do_tran(obj, data_, 1, 0, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
-}
-
-static int i2c_do_read(i2c_t *obj, char *data, int naklastdata)
-{
- return i2c_do_tran(obj, data, 1, 1, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
-}
-
-static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- int err = 0;
-
- i2c_disable_int(obj);
-
- if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
- err = I2C_ERROR_BUS_BUSY;
-#if NU_I2C_DEBUG
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- }
- else {
-#if 1
- // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
- uint32_t status = I2C_GET_STATUS(i2c_base);
-
- switch (status) {
- case 0x08: // Start
- case 0x10: // Master Repeat Start
- if (i2c_ctl & I2C_CTL_STA_Msk) {
- return 0;
- }
- else {
- break;
- }
- case 0xF8: // Bus Released
- if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) {
- return 0;
- }
- else {
- break;
- }
- }
-#endif
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
- err = I2C_ERROR_BUS_BUSY;
-#if NU_I2C_DEBUG
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- }
- }
-
- i2c_enable_int(obj);
-
- return err;
-}
-
-static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
-{
- uint32_t t1, t2, elapsed = 0;
- int status_assert = 0;
-
- t1 = us_ticker_read();
- while (1) {
- status_assert = is_status(obj);
- if (status_assert) {
- break;
- }
-
- t2 = us_ticker_read();
- elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
- if (elapsed >= timeout) {
-#if NU_I2C_DEBUG
- MY_I2C_T1 = t1;
- MY_I2C_T2 = t2;
- MY_I2C_ELAPSED = elapsed;
- MY_I2C_TIMEOUT = timeout;
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- break;
- }
- }
-
- return (elapsed >= timeout);
-}
-
-static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
-{
- uint32_t t1, t2, elapsed = 0;
- int tran_started;
- char *tran_pos = NULL;
- char *tran_pos2 = NULL;
-
- i2c_disable_int(obj);
- tran_pos = obj->i2c.tran_pos;
- i2c_enable_int(obj);
- t1 = us_ticker_read();
- while (1) {
- i2c_disable_int(obj);
- tran_started = i2c_is_tran_started(obj);
- i2c_enable_int(obj);
- if (! tran_started) { // Transfer completed or stopped
- break;
- }
-
- i2c_disable_int(obj);
- tran_pos2 = obj->i2c.tran_pos;
- i2c_enable_int(obj);
- t2 = us_ticker_read();
- if (tran_pos2 != tran_pos) { // Transfer on-going
- t1 = t2;
- tran_pos = tran_pos2;
- continue;
- }
-
- elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
- if (elapsed >= timeout) { // Transfer idle
-#if NU_I2C_DEBUG
- MY_I2C = obj->i2c;
- MY_I2C_T1 = t1;
- MY_I2C_T2 = t2;
- MY_I2C_ELAPSED = elapsed;
- MY_I2C_TIMEOUT = timeout;
- MY_I2C_2 = obj->i2c;
- while (1);
-#endif
- break;
- }
- }
-
- return (elapsed >= timeout);
-}
-
-#if 0
-static int i2c_is_stat_int(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
-}
-
-
-static int i2c_is_stop_det(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
-}
-#endif
-
-static int i2c_is_trsn_done(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- int i2c_int;
- uint32_t status;
- int inten_back;
-
- inten_back = i2c_set_int(obj, 0);
- i2c_int = !! (i2c_base->CTL & I2C_CTL_SI_Msk);
- status = I2C_GET_STATUS(i2c_base);
- i2c_set_int(obj, inten_back);
-
- return (i2c_int || status == 0xF8);
-}
-
-static int i2c_is_tran_started(i2c_t *obj)
-{
- int started;
- int inten_back;
-
- inten_back = i2c_set_int(obj, 0);
- started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
- i2c_set_int(obj, inten_back);
-
- return started;
-}
-
-static int i2c_addr2data(int address, int read)
-{
- return read ? (address | 1) : (address & 0xFE);
-}
-
-static void i2c0_vec(void)
-{
- i2c_irq(i2c0_var.obj);
-}
-static void i2c1_vec(void)
-{
- i2c_irq(i2c1_var.obj);
-}
-static void i2c2_vec(void)
-{
- i2c_irq(i2c2_var.obj);
-}
-static void i2c3_vec(void)
-{
- i2c_irq(i2c3_var.obj);
-}
-static void i2c4_vec(void)
-{
- i2c_irq(i2c4_var.obj);
-}
-
-static void i2c_irq(i2c_t *obj)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- uint32_t status;
-
- if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
- I2C_ClearTimeoutFlag(i2c_base);
- return;
- }
-
- status = I2C_GET_STATUS(i2c_base);
-#if NU_I2C_DEBUG
- if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
- MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
- }
- else {
- memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
- MY_I2C_STATUS_POS = 0;
- }
-#endif
-
- switch (status) {
- // Master Transmit
- case 0x28: // Master Transmit Data ACK
- case 0x18: // Master Transmit Address ACK
- case 0x08: // Start
- case 0x10: // Master Repeat Start
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
- else {
- if (status == 0x18) {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
- case 0x30: // Master Transmit Data NACK
- case 0x20: // Master Transmit Address NACK
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- break;
- case 0x38: // Master Arbitration Lost
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- break;
-
- case 0x48: // Master Receive Address NACK
- // Go Master Stop.
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- break;
- case 0x40: // Master Receive Address ACK
- case 0x50: // Master Receive Data ACK
- case 0x58: // Master Receive Data NACK
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- if (status == 0x50 || status == 0x58) {
- *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
- }
-
- if (status == 0x58) {
-#if NU_I2C_DEBUG
- if (obj->i2c.tran_pos != obj->i2c.tran_end) {
- MY_I2C = obj->i2c;
- while (1);
- }
-#endif
- // Go Master Repeat Start
- i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- else {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
- if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
-
- //case 0x00: // Bus error
-
- // Slave Transmit
- case 0xB8: // Slave Transmit Data ACK
- case 0xA8: // Slave Transmit Address ACK
- case 0xB0: // Slave Transmit Arbitration Lost
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
-
- I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
- if (obj->i2c.tran_pos == obj->i2c.tran_end &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- obj->i2c.slaveaddr_state = ReadAddressed;
- break;
- //case 0xA0: // Slave Transmit Repeat Start or Stop
- case 0xC0: // Slave Transmit Data NACK
- case 0xC8: // Slave Transmit Last Data ACK
- obj->i2c.slaveaddr_state = NoData;
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- break;
-
- // Slave Receive
- case 0x80: // Slave Receive Data ACK
- case 0x88: // Slave Receive Data NACK
- case 0x60: // Slave Receive Address ACK
- case 0x68: // Slave Receive Arbitration Lost
- obj->i2c.slaveaddr_state = WriteAddressed;
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- if (status == 0x80 || status == 0x88) {
- *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
- }
-
- if (status == 0x88) {
-#if NU_I2C_DEBUG
- if (obj->i2c.tran_pos != obj->i2c.tran_end) {
- MY_I2C = obj->i2c;
- while (1);
- }
-#endif
- obj->i2c.slaveaddr_state = NoData;
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
- else {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
- if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
- //case 0xA0: // Slave Receive Repeat Start or Stop
-
- // GC mode
- //case 0xA0: // GC mode Repeat Start or Stop
- case 0x90: // GC mode Data ACK
- case 0x98: // GC mode Data NACK
- case 0x70: // GC mode Address ACK
- case 0x78: // GC mode Arbitration Lost
- obj->i2c.slaveaddr_state = WriteAddressed;
- if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
- if (obj->i2c.tran_pos < obj->i2c.tran_end) {
- if (status == 0x90 || status == 0x98) {
- *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
- }
-
- if (status == 0x98) {
-#if NU_I2C_DEBUG
- if (obj->i2c.tran_pos != obj->i2c.tran_end) {
- MY_I2C = obj->i2c;
- while (1);
- }
-#endif
- obj->i2c.slaveaddr_state = NoData;
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
- else {
- uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
- if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
- obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
- // Last data
- i2c_ctl &= ~I2C_CTL_AA_Msk;
- }
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- }
- }
- else {
- obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
- i2c_disable_int(obj);
- break;
- }
- }
- else {
- i2c_disable_int(obj);
- }
- break;
-
- case 0xF8: // Bus Released
- break;
-
- default:
- i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
- }
-}
-
-static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
-{
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- obj->i2c.stop = 0;
-
- obj->i2c.tran_ctrl = 0;
-
- I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
- obj->i2c.slaveaddr_state = NoData;
-}
-
-
-#if DEVICE_I2C_ASYNCH
-
-void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
-{
- // NOTE: NUC472 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
- MBED_ASSERT((address & 0xFFFFFF00) == 0);
-
- // NOTE: First transmit and then receive.
-
- (void) hint;
- obj->i2c.dma_usage = DMA_USAGE_NEVER;
- obj->i2c.stop = stop;
- obj->i2c.address = address;
- obj->i2c.event = event;
- i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
-
- //I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
-
- i2c_enable_vector_interrupt(obj, handler, 1);
- i2c_start(obj);
-}
-
-uint32_t i2c_irq_handler_asynch(i2c_t *obj)
-{
- int event = 0;
-
- I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
- uint32_t status = I2C_GET_STATUS(i2c_base);
- switch (status) {
- case 0x08: // Start
- case 0x10: {// Master Repeat Start
- if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
- I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
- }
- else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
- }
- else {
- event = I2C_EVENT_TRANSFER_COMPLETE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
- break;
- }
-
- case 0x18: // Master Transmit Address ACK
- case 0x28: // Master Transmit Data ACK
- if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
- uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
- I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
- }
- else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- else {
- event = I2C_EVENT_TRANSFER_COMPLETE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
- break;
-
- case 0x20: // Master Transmit Address NACK
- event = I2C_EVENT_ERROR_NO_SLAVE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- break;
-
- case 0x30: // Master Transmit Data NACK
- if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
- event = I2C_EVENT_TRANSFER_EARLY_NACK;
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- }
- else {
- event = I2C_EVENT_TRANSFER_COMPLETE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
- break;
-
- case 0x38: // Master Arbitration Lost
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk); // Enter not addressed SLV mode
- event = I2C_EVENT_ERROR;
- break;
-
- case 0x50: // Master Receive Data ACK
- if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
- rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
- }
- case 0x40: // Master Receive Address ACK
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL_AA_Msk : 0));
- break;
-
- case 0x48: // Master Receive Address NACK
- event = I2C_EVENT_ERROR_NO_SLAVE;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- break;
-
- case 0x58: // Master Receive Data NACK
- if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
- uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
- rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
- }
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
- break;
-
- case 0x00: // Bus error
- event = I2C_EVENT_ERROR;
- i2c_reset(obj);
- break;
-
- default:
- event = I2C_EVENT_ERROR;
- if (obj->i2c.stop) {
- I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
- }
- }
-
- if (event) {
- i2c_rollback_vector_interrupt(obj);
- }
-
- return (event & obj->i2c.event);
-}
-
-uint8_t i2c_active(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- // Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
- uint32_t vec = NVIC_GetVector(modinit->irq_n);
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- return (vec && vec != (uint32_t) var->vec);
-}
-
-void i2c_abort_asynch(i2c_t *obj)
-{
- i2c_rollback_vector_interrupt(obj);
- i2c_stop(obj);
-}
-
-static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
-{
- obj->tx_buff.buffer = (void *) tx;
- obj->tx_buff.length = tx_length;
- obj->tx_buff.pos = 0;
- obj->rx_buff.buffer = rx;
- obj->rx_buff.length = rx_length;
- obj->rx_buff.pos = 0;
-}
-
-static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- if (enable) {
- NVIC_SetVector(modinit->irq_n, handler);
- i2c_enable_int(obj);
- }
- else {
- i2c_disable_int(obj);
- }
-}
-
-static void i2c_rollback_vector_interrupt(i2c_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->i2c.i2c);
-
- struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
- i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
-}
-
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,224 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "lp_ticker_api.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "sleep_api.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "critical.h"
-
-// lp_ticker tick = us = timestamp
-#define US_PER_TICK (1)
-#define US_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR2_INT (US_PER_SEC * 10)
-#define TMR2_CLK_PER_SEC (__LXT)
-#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
-#define TMR3_CLK_PER_SEC (__LXT)
-
-static void tmr2_vec(void);
-static void tmr3_vec(void);
-static void lp_ticker_arm_cd(void);
-
-static int lp_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_clks = 0;
-static volatile uint32_t cd_minor_clks = 0;
-static volatile uint32_t wakeup_tick = (uint32_t) -1;
-
-// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
-// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
-static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
-static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
-
-#define TMR_CMP_MIN 2
-#define TMR_CMP_MAX 0xFFFFFFu
-
-void lp_ticker_init(void)
-{
- if (lp_ticker_inited) {
- return;
- }
- lp_ticker_inited = 1;
-
- counter_major = 0;
- cd_major_minor_clks = 0;
- cd_minor_clks = 0;
- wakeup_tick = (uint32_t) -1;
-
- // Reset module
- SYS_ResetModule(timer2_modinit.rsetidx);
- SYS_ResetModule(timer3_modinit.rsetidx);
-
- // Select IP clock source
- CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
- CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
- // Enable IP clock
- CLK_EnableModuleClock(timer2_modinit.clkidx);
- CLK_EnableModuleClock(timer3_modinit.clkidx);
-
- // Configure clock
- uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
- MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
- uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
- MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
- // Continuous mode
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk;
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
-
- // Set vector
- NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
- NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
-
- NVIC_EnableIRQ(timer2_modinit.irq_n);
- NVIC_EnableIRQ(timer3_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
- lp_ticker_set_interrupt(wakeup_tick);
-
- // Start timer
- TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-}
-
-timestamp_t lp_ticker_read()
-{
- if (! lp_ticker_inited) {
- lp_ticker_init();
- }
-
- TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
-
- do {
- uint64_t major_minor_clks;
- uint32_t minor_clks;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_clks = TIMER_GetCounter(timer2_base);
- uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
- major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
- }
- else {
- major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
-
- // Add power-down compensation
- return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
- }
- while (0);
-}
-
-void lp_ticker_set_interrupt(timestamp_t timestamp)
-{
- uint32_t now = lp_ticker_read();
- wakeup_tick = timestamp;
-
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-
- /**
- * FIXME: Scheduled alarm may go off incorrectly due to wrap around.
- * Conditions in which delta is negative:
- * 1. Wrap around
- * 2. Newly scheduled alarm is behind now
- */
- //int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
- int delta = (int) (timestamp - now);
- if (delta > 0) {
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
- }
- else {
- cd_major_minor_clks = cd_minor_clks = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
- }
-}
-
-void lp_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-void lp_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-static void tmr2_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- counter_major ++;
-}
-
-static void tmr3_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
- if (cd_major_minor_clks == 0) {
- // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
- lp_ticker_irq_handler();
- }
- else {
- lp_ticker_arm_cd();
- }
-}
-
-static void lp_ticker_arm_cd(void)
-{
- TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
-
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 KHz
- uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
- MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
- timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
- timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3 | TIMER_CTL_CNTDATEN_Msk;
-
- cd_minor_clks = cd_major_minor_clks;
- cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
- timer3_base->CMP = cd_minor_clks;
-
- TIMER_EnableInt(timer3_base);
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_Start(timer3_base);
-}
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_lib.json Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,18 +0,0 @@
-{
- "name": "NUC472",
- "config": {
- "gpio-irq-debounce-enable": {
- "help": "Enable GPIO IRQ debounce",
- "value": 0
- },
- "gpio-irq-debounce-clock-source": {
- "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
- "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
- },
-
- "gpio-irq-debounce-sample-rate": {
- "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
- "value": "GPIO_DBCTL_DBCLKSEL_16"
- }
- }
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/pinmap.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,83 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "mbed_assert.h"
-#include "pinmap.h"
-#include "PortNames.h"
-#include "mbed_error.h"
-
-/**
- * Configure pin multi-function
- */
-void pin_function(PinName pin, int data)
-{
- MBED_ASSERT(pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(pin);
- __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8);
- //uint32_t MFP_Pos = NU_MFP_POS(pin_index);
- uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
-
- // E.g.: SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ;
- *GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data;
-
- // [TODO] Disconnect JTAG-DP + SW-DP signals.
- // Warning: Need to reconnect under reset
- //if ((pin == PA_13) || (pin == PA_14)) {
- //
- //}
- //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
- //
- //}
-}
-
-/**
- * Configure pin pull-up/pull-down
- */
-void pin_mode(PinName pin, PinMode mode)
-{
- MBED_ASSERT(pin != (PinName)NC);
- uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
- uint32_t port_index = NU_PINNAME_TO_PORT(pin);
- GPIO_T *gpio_base = NU_PORT_BASE(port_index);
-
- uint32_t mode_intern = GPIO_MODE_INPUT;
-
- switch (mode) {
- case PullUp:
- mode_intern = GPIO_MODE_INPUT;
- break;
-
- case PullDown:
- case PullNone:
- // NOTE: Not support
- return;
-
- case PushPull:
- mode_intern = GPIO_MODE_OUTPUT;
- break;
-
- case OpenDrain:
- mode_intern = GPIO_MODE_OPEN_DRAIN;
- break;
-
- case Quasi:
- mode_intern = GPIO_MODE_QUASI;
- break;
- }
-
- GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
-}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/port_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,99 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "port_api.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT
-
-PinName port_pin(PortName port, int pin_n)
-{
- return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n);
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
-{
- obj->port = port;
- obj->mask = mask;
- obj->direction = dir;
-
- uint32_t i;
- obj->direction = dir;
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- gpio_set(port_pin(port, i));
- }
- }
-
- port_dir(obj, dir);
-}
-
-void port_dir(port_t *obj, PinDirection dir)
-{
- uint32_t i;
- obj->direction = dir;
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- if (dir == PIN_OUTPUT) {
- GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT);
- } else { // PIN_INPUT
- GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT);
- }
- }
- }
-}
-
-void port_mode(port_t *obj, PinMode mode)
-{
- uint32_t i;
-
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- pin_mode(port_pin(obj->port, i), mode);
- }
- }
-}
-
-void port_write(port_t *obj, int value)
-{
- uint32_t i;
- uint32_t port_index = obj->port;
-
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- GPIO_PIN_ADDR(port_index, i) = (value & obj->mask) ? 1 : 0;
- }
- }
-}
-
-int port_read(port_t *obj)
-{
- uint32_t i;
- uint32_t port_index = obj->port;
- int value = 0;
-
- for (i = 0; i < GPIO_PIN_MAX; i++) {
- if (obj->mask & (1 << i)) {
- value = value | (GPIO_PIN_ADDR(port_index, i) << i);
- }
- }
-
- return value;
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,227 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "pwmout_api.h"
-
-#if DEVICE_PWMOUT
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "nu_bitutil.h"
-
-struct nu_pwm_var {
- uint32_t en_msk;
-};
-
-static struct nu_pwm_var pwm0_var = {
- .en_msk = 0
-};
-
-static struct nu_pwm_var pwm1_var = {
- .en_msk = 0
-};
-
-static uint32_t pwm_modinit_mask = 0;
-
-// FIXME: PWM1 2/3 channels fail. PWM registers cannot write after their respective clocks are enabled.
-static const struct nu_modinit_s pwm_modinit_tab[] = {
- {PWM_0_0, PWM0CH01_MODULE, CLK_CLKSEL2_PWM0CH01SEL_HIRC, 0, PWM0_RST, PWM0CH0_IRQn, &pwm0_var},
- {PWM_0_1, PWM0CH01_MODULE, CLK_CLKSEL2_PWM0CH01SEL_HIRC, 0, PWM0_RST, PWM0CH1_IRQn, &pwm0_var},
- {PWM_0_2, PWM0CH23_MODULE, CLK_CLKSEL2_PWM0CH23SEL_HIRC, 0, PWM0_RST, PWM0CH2_IRQn, &pwm0_var},
- {PWM_0_3, PWM0CH23_MODULE, CLK_CLKSEL2_PWM0CH23SEL_HIRC, 0, PWM0_RST, PWM0CH3_IRQn, &pwm0_var},
- {PWM_0_4, PWM0CH45_MODULE, CLK_CLKSEL2_PWM0CH45SEL_HIRC, 0, PWM0_RST, PWM0CH4_IRQn, &pwm0_var},
- {PWM_0_5, PWM0CH45_MODULE, CLK_CLKSEL2_PWM0CH45SEL_HIRC, 0, PWM0_RST, PWM0CH5_IRQn, &pwm0_var},
-
- {PWM_1_0, PWM1CH01_MODULE, CLK_CLKSEL2_PWM1CH01SEL_HIRC, 0, PWM1_RST, PWM1CH0_IRQn, &pwm1_var},
- {PWM_1_1, PWM1CH01_MODULE, CLK_CLKSEL2_PWM1CH01SEL_HIRC, 0, PWM1_RST, PWM1CH1_IRQn, &pwm1_var},
- {PWM_1_2, PWM1CH23_MODULE, CLK_CLKSEL2_PWM1CH23SEL_HIRC, 0, PWM1_RST, PWM1CH2_IRQn, &pwm1_var},
- {PWM_1_3, PWM1CH23_MODULE, CLK_CLKSEL2_PWM1CH23SEL_HIRC, 0, PWM1_RST, PWM1CH3_IRQn, &pwm1_var},
- {PWM_1_4, PWM1CH45_MODULE, CLK_CLKSEL2_PWM1CH45SEL_HIRC, 0, PWM1_RST, PWM1CH4_IRQn, &pwm1_var},
- {PWM_1_5, PWM1CH45_MODULE, CLK_CLKSEL2_PWM1CH45SEL_HIRC, 0, PWM1_RST, PWM1CH5_IRQn, &pwm1_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-static void pwmout_config(pwmout_t* obj);
-
-void pwmout_init(pwmout_t* obj, PinName pin)
-{
- obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM);
- MBED_ASSERT((int) obj->pwm != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->pwm);
-
- // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module.
- if (! ((struct nu_pwm_var *) modinit->var)->en_msk) {
- // Reset this module if no channel enabled
- SYS_ResetModule(modinit->rsetidx);
- }
-
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
- uint32_t chn = NU_MODSUBINDEX(obj->pwm);
-
- // NOTE: Channels 0/1, 2/3, and 4/5 share a clock source.
- if ((((struct nu_pwm_var *) modinit->var)->en_msk & (0x3 << (chn / 2 * 2))) == 0) {
- // Select clock source of paired channels
- CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
- // Enable clock of paired channels
- CLK_EnableModuleClock(modinit->clkidx);
-
- // FIXME: PWM_1_2/3 design bug. PWM_1_2/3 also require PWM_1_0/1 clock enabled.
- if (obj->pwm == PWM_1_2 || obj->pwm == PWM_1_3) {
- CLK_EnableModuleClock(PWM1CH01_MODULE);
- }
- }
-
- // Wire pinout
- pinmap_pinout(pin, PinMap_PWM);
-
- // Default: period = 10 ms, pulse width = 0 ms
- obj->period_us = 1000 * 10;
- obj->pulsewidth_us = 0;
- pwmout_config(obj);
-
- // Enable output of the specified PWM channel
- PWM_EnableOutput(pwm_base, 1 << chn);
- PWM_Start(pwm_base, 1 << chn);
-
- ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn;
-
- // Mark this module to be inited.
- int i = modinit - pwm_modinit_tab;
- pwm_modinit_mask |= 1 << i;
-}
-
-void pwmout_free(pwmout_t* obj)
-{
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
- uint32_t chn = NU_MODSUBINDEX(obj->pwm);
- PWM_ForceStop(pwm_base, 1 << chn);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->pwm);
- ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn);
-
-
- if ((((struct nu_pwm_var *) modinit->var)->en_msk & (0x3 << (chn / 2 * 2))) == 0) {
- // FIXME: PWM_1_2/3 design bug. PWM_1_2/3 also require PWM_1_0/1 clock enabled.
- switch (obj->pwm) {
- case PWM_1_0:
- case PWM_1_1:
- if (pwm1_var.en_msk & 0xC) {
- break;
- }
-
- case PWM_1_2:
- case PWM_1_3:
- if (! (pwm1_var.en_msk & 0x3)) {
- CLK_DisableModuleClock(PWM1CH01_MODULE);
- }
-
- default:
- // Disable clock of paired channels
- CLK_DisableModuleClock(modinit->clkidx);
- }
- }
-
- // Mark this module to be deinited.
- int i = modinit - pwm_modinit_tab;
- pwm_modinit_mask &= ~(1 << i);
-}
-
-void pwmout_write(pwmout_t* obj, float value)
-{
- obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us);
- pwmout_config(obj);
-}
-
-float pwmout_read(pwmout_t* obj)
-{
- return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f);
-}
-
-void pwmout_period(pwmout_t* obj, float seconds)
-{
- pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms)
-{
- pwmout_period_us(obj, ms * 1000);
-}
-
-// Set the PWM period, keeping the duty cycle the same.
-void pwmout_period_us(pwmout_t* obj, int us)
-{
- uint32_t period_us_old = obj->period_us;
- uint32_t pulsewidth_us_old = obj->pulsewidth_us;
- obj->period_us = us;
- obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us);
- pwmout_config(obj);
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds)
-{
- pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
-{
- pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us)
-{
- obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us);
- pwmout_config(obj);
-}
-
-int pwmout_allow_powerdown(void)
-{
- uint32_t modinit_mask = pwm_modinit_mask;
- while (modinit_mask) {
- int pwm_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx;
- if (modinit->modname != NC) {
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname);
- uint32_t chn = NU_MODSUBINDEX(modinit->modname);
- // Disallow entering power-down mode if PWM counter is enabled.
- if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << pwm_idx);
- }
-
- return 1;
-}
-
-static void pwmout_config(pwmout_t* obj)
-{
- PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm);
- uint32_t chn = NU_MODSUBINDEX(obj->pwm);
- // NOTE: Support period < 1s
- //PWM_ConfigOutputChannel(pwm_base, chn, 1000 * 1000 / obj->period_us, obj->pulsewidth_us * 100 / obj->period_us);
- PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, obj->pulsewidth_us * 100 / obj->period_us, obj->period_us);
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "rtc_api.h"
-
-#if DEVICE_RTC
-
-#include "wait_api.h"
-#include "mbed_error.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-
-#define YEAR0 1900
-//#define EPOCH_YR 1970
-static int rtc_inited = 0;
-
-static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
-
-void rtc_init(void)
-{
- if (rtc_inited) {
- return;
- }
- rtc_inited = 1;
-
- // Enable IP clock
- CLK_EnableModuleClock(rtc_modinit.clkidx);
-
- RTC_Open(NULL);
-}
-
-void rtc_free(void)
-{
- // FIXME
-}
-
-int rtc_isenabled(void)
-{
- return rtc_inited;
-}
-
-/*
- struct tm
- tm_sec seconds after the minute 0-61
- tm_min minutes after the hour 0-59
- tm_hour hours since midnight 0-23
- tm_mday day of the month 1-31
- tm_mon months since January 0-11
- tm_year years since 1900
- tm_wday days since Sunday 0-6
- tm_yday days since January 1 0-365
- tm_isdst Daylight Saving Time flag
-*/
-
-time_t rtc_read(void)
-{
- if (! rtc_inited) {
- rtc_init();
- }
-
- S_RTC_TIME_DATA_T rtc_datetime;
- RTC_GetDateAndTime(&rtc_datetime);
-
- struct tm timeinfo;
-
- // Convert struct tm to S_RTC_TIME_DATA_T
- timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
- timeinfo.tm_mon = rtc_datetime.u32Month - 1;
- timeinfo.tm_mday = rtc_datetime.u32Day;
- timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
- timeinfo.tm_hour = rtc_datetime.u32Hour;
- timeinfo.tm_min = rtc_datetime.u32Minute;
- timeinfo.tm_sec = rtc_datetime.u32Second;
-
- // Convert to timestamp
- time_t t = mktime(&timeinfo);
-
- return t;
-}
-
-void rtc_write(time_t t)
-{
- if (! rtc_inited) {
- rtc_init();
- }
-
- // Convert timestamp to struct tm
- struct tm *timeinfo = localtime(&t);
-
- S_RTC_TIME_DATA_T rtc_datetime;
-
- // Convert S_RTC_TIME_DATA_T to struct tm
- rtc_datetime.u32Year = timeinfo->tm_year + YEAR0;
- rtc_datetime.u32Month = timeinfo->tm_mon + 1;
- rtc_datetime.u32Day = timeinfo->tm_mday;
- rtc_datetime.u32DayOfWeek = timeinfo->tm_wday;
- rtc_datetime.u32Hour = timeinfo->tm_hour;
- rtc_datetime.u32Minute = timeinfo->tm_min;
- rtc_datetime.u32Second = timeinfo->tm_sec;
- rtc_datetime.u32TimeScale = RTC_CLOCK_24;
-
- // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
- RTC_SetDateAndTime(&rtc_datetime);
- //nu_nop(6000);
- wait_us(100);
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1117 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "serial_api.h"
-
-#if DEVICE_SERIAL
-
-#include "cmsis.h"
-#include "mbed_error.h"
-#include "mbed_assert.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_bitutil.h"
-
-#if DEVICE_SERIAL_ASYNCH
-#include "dma_api.h"
-#include "dma.h"
-#endif
-
-struct nu_uart_var {
- uint32_t ref_cnt; // Reference count of the H/W module
- serial_t * obj;
- uint32_t fifo_size_tx;
- uint32_t fifo_size_rx;
- void (*vec)(void);
-#if DEVICE_SERIAL_ASYNCH
- void (*vec_async)(void);
- uint8_t pdma_perp_tx;
- uint8_t pdma_perp_rx;
-#endif
-};
-
-static void uart0_vec(void);
-static void uart1_vec(void);
-static void uart2_vec(void);
-static void uart3_vec(void);
-static void uart4_vec(void);
-static void uart5_vec(void);
-static void uart_irq(serial_t *obj);
-
-#if DEVICE_SERIAL_ASYNCH
-static void uart0_vec_async(void);
-static void uart1_vec_async(void);
-static void uart2_vec_async(void);
-static void uart3_vec_async(void);
-static void uart4_vec_async(void);
-static void uart5_vec_async(void);
-static void uart_irq_async(serial_t *obj);
-
-static void uart_dma_handler_tx(uint32_t id, uint32_t event);
-static void uart_dma_handler_rx(uint32_t id, uint32_t event);
-
-static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
-static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
-static int serial_write_async(serial_t *obj);
-static int serial_read_async(serial_t *obj);
-
-static uint32_t serial_rx_event_check(serial_t *obj);
-static uint32_t serial_tx_event_check(serial_t *obj);
-
-static int serial_is_tx_complete(serial_t *obj);
-static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
-
-static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
-static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
-static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
-static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
-static int serial_is_rx_complete(serial_t *obj);
-
-static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
-static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
-#endif
-
-static struct nu_uart_var uart0_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 64,
- .fifo_size_rx = 64,
- .vec = uart0_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart0_vec_async,
- .pdma_perp_tx = PDMA_UART0_TX,
- .pdma_perp_rx = PDMA_UART0_RX
-#endif
-};
-static struct nu_uart_var uart1_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart1_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart1_vec_async,
- .pdma_perp_tx = PDMA_UART1_TX,
- .pdma_perp_rx = PDMA_UART1_RX
-#endif
-};
-static struct nu_uart_var uart2_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart2_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart2_vec_async,
- .pdma_perp_tx = PDMA_UART2_TX,
- .pdma_perp_rx = PDMA_UART2_RX
-#endif
-};
-static struct nu_uart_var uart3_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart3_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart3_vec_async,
- .pdma_perp_tx = PDMA_UART3_TX,
- .pdma_perp_rx = PDMA_UART3_RX
-#endif
-};
-static struct nu_uart_var uart4_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart4_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart4_vec_async,
- .pdma_perp_tx = PDMA_UART4_TX,
- .pdma_perp_rx = PDMA_UART4_RX
-#endif
-};
-static struct nu_uart_var uart5_var = {
- .ref_cnt = 0,
- .obj = NULL,
- .fifo_size_tx = 16,
- .fifo_size_rx = 16,
- .vec = uart5_vec,
-#if DEVICE_SERIAL_ASYNCH
- .vec_async = uart5_vec_async,
- .pdma_perp_tx = PDMA_UART5_TX,
- .pdma_perp_rx = PDMA_UART5_RX
-#endif
-};
-
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-static uint32_t uart_modinit_mask = 0;
-
-static const struct nu_modinit_s uart_modinit_tab[] = {
- {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
- {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
- {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
- {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
- {UART_4, UART4_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART4_RST, UART4_IRQn, &uart4_var},
- {UART_5, UART5_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART5_RST, UART5_IRQn, &uart5_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-extern void mbed_sdk_init(void);
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
- // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
- mbed_sdk_init();
-
- // Determine which UART_x the pins are used for
- uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
- uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
- // Get the peripheral name (UART_x) from the pins and assign it to the object
- obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
- MBED_ASSERT((int)obj->serial.uart != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
-
- if (! var->ref_cnt) {
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Select IP clock source
- CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- pinmap_pinout(tx, PinMap_UART_TX);
- pinmap_pinout(rx, PinMap_UART_RX);
-
- obj->serial.pin_tx = tx;
- obj->serial.pin_rx = rx;
- }
- var->ref_cnt ++;
-
- // Configure the UART module and set its baudrate
- serial_baud(obj, 9600);
- // Configure data bits, parity, and stop bits
- serial_format(obj, 8, ParityNone, 1);
-
- obj->serial.vec = var->vec;
-
-#if DEVICE_SERIAL_ASYNCH
- obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
- obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
- obj->serial.event = 0;
- obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
-#endif
-
- // For stdio management
- if (obj->serial.uart == STDIO_UART) {
- stdio_uart_inited = 1;
- memcpy(&stdio_uart, obj, sizeof(serial_t));
- }
-
- if (var->ref_cnt) {
- // Mark this module to be inited.
- int i = modinit - uart_modinit_tab;
- uart_modinit_mask |= 1 << i;
- }
-}
-
-void serial_free(serial_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
-
- var->ref_cnt --;
- if (! var->ref_cnt) {
-#if DEVICE_SERIAL_ASYNCH
- if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->serial.dma_chn_id_tx);
- obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- }
- if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->serial.dma_chn_id_rx);
- obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-#endif
-
- UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
-
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- NVIC_DisableIRQ(modinit->irq_n);
-
- // Disable IP clock
- CLK_DisableModuleClock(modinit->clkidx);
- }
-
- if (var->obj == obj) {
- var->obj = NULL;
- }
-
- if (obj->serial.uart == STDIO_UART) {
- stdio_uart_inited = 0;
- }
-
- if (! var->ref_cnt) {
- // Mark this module to be deinited.
- int i = modinit - uart_modinit_tab;
- uart_modinit_mask &= ~(1 << i);
- }
-}
-
-void serial_baud(serial_t *obj, int baudrate) {
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- obj->serial.baudrate = baudrate;
- UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- // TODO: Assert for not supported parity and data bits
- obj->serial.databits = data_bits;
- obj->serial.parity = parity;
- obj->serial.stopbits = stop_bits;
-
- uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
- (data_bits == 6) ? UART_WORD_LEN_6 :
- (data_bits == 7) ? UART_WORD_LEN_7 :
- UART_WORD_LEN_8;
- uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
- (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
- UART_PARITY_NONE;
- uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
- UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
- 0, // Don't change baudrate
- databits_intern,
- parity_intern,
- stopbits_intern);
-}
-
-#if DEVICE_SERIAL_FC
-
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- // First, disable flow control completely.
- uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
-
- if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
- // Check if RTS pin matches.
- uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
- MBED_ASSERT(uart_rts == obj->serial.uart);
- // Enable the pin for RTS function
- pinmap_pinout(rxflow, PinMap_UART_RTS);
- // nRTS pin output is high level active
- uart_base->MODEM = (uart_base->MODEM & ~UART_MODEM_RTSACTLV_Msk) | UART_MODEM_RTSACTLV_Msk;
- uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
- // Enable RTS
- uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
- }
-
- if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
- // Check if CTS pin matches.
- uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
- MBED_ASSERT(uart_cts == obj->serial.uart);
- // Enable the pin for CTS function
- pinmap_pinout(txflow, PinMap_UART_CTS);
- // nCTS pin input is high level active
- uart_base->MODEMSTS = (uart_base->MODEMSTS & ~UART_MODEMSTS_CTSACTLV_Msk) | UART_MODEMSTS_CTSACTLV_Msk;
- // Enable CTS
- uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
- }
-}
-
-#endif //DEVICE_SERIAL_FC
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
-{
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- obj->serial.irq_handler = (uint32_t) handler;
- obj->serial.irq_id = id;
-
- // Restore sync-mode vector
- obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
-{
- if (enable) {
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
- NVIC_EnableIRQ(modinit->irq_n);
-
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
- // Multiple serial S/W objects for single UART H/W module possibly.
- // Bind serial S/W object to UART H/W module as interrupt is enabled.
- var->obj = obj;
-
- switch (irq) {
- // NOTE: Setting inten_msk first to avoid race condition
- case RxIrq:
- obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- break;
- case TxIrq:
- obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- break;
- }
- } else { // disable
- switch (irq) {
- case RxIrq:
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
- break;
- case TxIrq:
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
- break;
- }
- }
-}
-
-int serial_getc(serial_t *obj)
-{
- // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
- while (! serial_readable(obj));
- int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
-
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- }
-
- return c;
-}
-
-void serial_putc(serial_t *obj, int c)
-{
- // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much.
- while (! serial_writable(obj));
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
-
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- }
-}
-
-int serial_readable(serial_t *obj)
-{
- //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
- return ! (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk);
-}
-
-int serial_writable(serial_t *obj)
-{
- return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
-}
-
-void serial_pinout_tx(PinName tx)
-{
- pinmap_pinout(tx, PinMap_UART_TX);
-}
-
-void serial_break_set(serial_t *obj)
-{
- ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
-}
-
-void serial_break_clear(serial_t *obj)
-{
- ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
-}
-
-static void uart0_vec(void)
-{
- uart_irq(uart0_var.obj);
-}
-
-static void uart1_vec(void)
-{
- uart_irq(uart1_var.obj);
-}
-
-static void uart2_vec(void)
-{
- uart_irq(uart2_var.obj);
-}
-
-static void uart3_vec(void)
-{
- uart_irq(uart3_var.obj);
-}
-
-static void uart4_vec(void)
-{
- uart_irq(uart4_var.obj);
-}
-
-static void uart5_vec(void)
-{
- uart_irq(uart5_var.obj);
-}
-
-static void uart_irq(serial_t *obj)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
- UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- if (obj->serial.irq_handler) {
- ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
- }
- }
-
- if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
- UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
- if (obj->serial.irq_handler) {
- ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
- }
- }
-
- // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
- uart_base->INTSTS = uart_base->INTSTS;
- uart_base->FIFOSTS = uart_base->FIFOSTS;
-}
-
-
-#if DEVICE_SERIAL_ASYNCH
-int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
-{
- // NOTE: tx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
- tx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
-
- MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
-
- obj->serial.dma_usage_tx = hint;
- serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
-
- // UART IRQ is necessary for both interrupt way and DMA way
- serial_tx_enable_event(obj, event, 1);
- serial_tx_buffer_set(obj, tx, tx_length, tx_width);
- //UART_HAL_DisableTransmitter(obj->serial.address);
- //UART_HAL_FlushTxFifo(obj->serial.address);
- //UART_HAL_EnableTransmitter(obj->serial.address);
-
- int n_word = 0;
- if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
- // Interrupt way
- n_word = serial_write_async(obj);
- serial_tx_enable_interrupt(obj, handler, 1);
- } else {
- // DMA way
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
- ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
- (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- tx_length);
- PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
- ((uint32_t) tx) + (tx_width / 8) * tx_length, // NOTE: End of source address
- PDMA_SAR_INC, // Source address incremental
- (uint32_t) obj->serial.uart, // Destination address
- PDMA_DAR_FIX); // Destination address fixed
- PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->serial.dma_chn_id_tx,
- 0); // Interrupt type. No use here
- // Register DMA event handler
- dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
- serial_tx_enable_interrupt(obj, handler, 1);
- ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
- }
-
- return n_word;
-}
-
-void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
-{
- // NOTE: rx_width is deprecated. Assume its value is databits ceiled to the nearest number among 8, 16, and 32.
- rx_width = (obj->serial.databits <= 8) ? 8 : (obj->serial.databits <= 16) ? 16 : 32;
-
- MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
-
- obj->serial.dma_usage_rx = hint;
- serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
- // DMA doesn't support char match, so fall back to IRQ if it is requested.
- if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
- (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
- char_match != SERIAL_RESERVED_CHAR_MATCH) {
- obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
- dma_channel_free(obj->serial.dma_chn_id_rx);
- obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-
- // UART IRQ is necessary for both interrupt way and DMA way
- serial_rx_enable_event(obj, event, 1);
- serial_rx_buffer_set(obj, rx, rx_length, rx_width);
- serial_rx_set_char_match(obj, char_match);
- //UART_HAL_DisableReceiver(obj->serial.address);
- //UART_HAL_FlushRxFifo(obj->serial.address);
- //UART_HAL_EnableReceiver(obj->serial.address);
-
- if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
- // Interrupt way
- serial_rx_enable_interrupt(obj, handler, 1);
- } else {
- // DMA way
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- PDMA->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
- ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
- (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- rx_length);
- PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
- (uint32_t) obj->serial.uart, // Source address
- PDMA_SAR_FIX, // Source address fixed
- ((uint32_t) rx) + (rx_width / 8) * rx_length, // NOTE: End of destination address
- PDMA_DAR_INC); // Destination address incremental
- PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->serial.dma_chn_id_rx,
- 0); // Interrupt type. No use here
- // Register DMA event handler
- dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
- serial_rx_enable_interrupt(obj, handler, 1);
- ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
- }
-}
-
-void serial_tx_abort_asynch(serial_t *obj)
-{
- // Flush Tx FIFO. Otherwise, output data may get lost on this change.
- while (! UART_IS_TX_EMPTY(((UART_T *) obj->serial.uart)));
-
- if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
- if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->serial.dma_chn_id_tx, 0);
- // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->serial.dma_chn_id_tx);
- PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
- }
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
- }
-
- // Necessary for both interrupt way and DMA way
- serial_irq_set(obj, TxIrq, 0);
- // FIXME: more complete abort operation
- //UART_HAL_DisableTransmitter(obj->serial.serial.address);
- //UART_HAL_FlushTxFifo(obj->serial.serial.address);
-}
-
-void serial_rx_abort_asynch(serial_t *obj)
-{
- if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
- if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->serial.dma_chn_id_rx, 0);
- // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->serial.dma_chn_id_rx);
- PDMA->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
- }
- UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
- }
-
- // Necessary for both interrupt way and DMA way
- serial_irq_set(obj, RxIrq, 0);
- // FIXME: more complete abort operation
- //UART_HAL_DisableReceiver(obj->serial.serial.address);
- //UART_HAL_FlushRxFifo(obj->serial.serial.address);
-}
-
-uint8_t serial_tx_active(serial_t *obj)
-{
- return serial_is_irq_en(obj, TxIrq);
-}
-
-uint8_t serial_rx_active(serial_t *obj)
-{
- return serial_is_irq_en(obj, RxIrq);
-}
-
-int serial_irq_handler_asynch(serial_t *obj)
-{
- int event_rx = 0;
- int event_tx = 0;
-
- // Necessary for both interrupt way and DMA way
- if (serial_is_irq_en(obj, RxIrq)) {
- event_rx = serial_rx_event_check(obj);
- if (event_rx) {
- serial_rx_abort_asynch(obj);
- }
- }
-
- if (serial_is_irq_en(obj, TxIrq)) {
- event_tx = serial_tx_event_check(obj);
- if (event_tx) {
- serial_tx_abort_asynch(obj);
- }
- }
-
- return (obj->serial.event & (event_rx | event_tx));
-}
-
-int serial_allow_powerdown(void)
-{
- uint32_t modinit_mask = uart_modinit_mask;
- while (modinit_mask) {
- int uart_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx;
- if (modinit->modname != NC) {
- UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
- // Disallow entering power-down mode if Tx FIFO has data to flush
- if (! UART_IS_TX_EMPTY((uart_base))) {
- return 0;
- }
- // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going
- if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
- return 0;
- }
- // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going
- if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << uart_idx);
- }
-
- return 1;
-}
-
-static void uart0_vec_async(void)
-{
- uart_irq_async(uart0_var.obj);
-}
-
-static void uart1_vec_async(void)
-{
- uart_irq_async(uart1_var.obj);
-}
-
-static void uart2_vec_async(void)
-{
- uart_irq_async(uart2_var.obj);
-}
-
-static void uart3_vec_async(void)
-{
- uart_irq_async(uart3_var.obj);
-}
-
-static void uart4_vec_async(void)
-{
- uart_irq_async(uart4_var.obj);
-}
-
-static void uart5_vec_async(void)
-{
- uart_irq_async(uart5_var.obj);
-}
-
-static void uart_irq_async(serial_t *obj)
-{
- if (serial_is_irq_en(obj, RxIrq)) {
- (*obj->serial.irq_handler_rx_async)();
- }
- if (serial_is_irq_en(obj, TxIrq)) {
- (*obj->serial.irq_handler_tx_async)();
- }
-}
-
-static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
-{
- obj->char_match = char_match;
- obj->char_found = 0;
-}
-
-static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
-{
- obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
- obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
-
- //if (event & SERIAL_EVENT_TX_COMPLETE) {
- //}
-}
-
-static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
-{
- obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
- obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
-
- //if (event & SERIAL_EVENT_RX_COMPLETE) {
- //}
- //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
- //}
- if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
- }
- if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
- }
- if (event & SERIAL_EVENT_RX_OVERFLOW) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
- }
- //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
- //}
-}
-
-static int serial_is_tx_complete(serial_t *obj)
-{
- // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
- //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
- // FIXME: Premature abort???
- return (obj->tx_buff.pos == obj->tx_buff.length);
-}
-
-static int serial_is_rx_complete(serial_t *obj)
-{
- //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
- return (obj->rx_buff.pos == obj->rx_buff.length);
-}
-
-static uint32_t serial_tx_event_check(serial_t *obj)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
- UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
- }
-
- uint32_t event = 0;
-
- if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
- serial_write_async(obj);
- }
-
- if (serial_is_tx_complete(obj)) {
- event |= SERIAL_EVENT_TX_COMPLETE;
- }
-
- return event;
-}
-
-static uint32_t serial_rx_event_check(serial_t *obj)
-{
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
- // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
- UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- }
-
- uint32_t event = 0;
-
- if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
- }
- if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
- event |= SERIAL_EVENT_RX_FRAMING_ERROR;
- }
- if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
- event |= SERIAL_EVENT_RX_PARITY_ERROR;
- }
-
- if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
- uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
- event |= SERIAL_EVENT_RX_OVERFLOW;
- }
-
- if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
- serial_read_async(obj);
- }
-
- if (serial_is_rx_complete(obj)) {
- event |= SERIAL_EVENT_RX_COMPLETE;
- }
- if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
- event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
- // FIXME: Timing to reset char_found?
- //obj->char_found = 0;
- }
-
- return event;
-}
-
-static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
-{
- serial_t *obj = (serial_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect UART IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->tx_buff.pos = obj->tx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- uart_irq_async(obj);
-}
-
-static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
-{
- serial_t *obj = (serial_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect UART IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->rx_buff.pos = obj->rx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- uart_irq_async(obj);
-}
-
-static int serial_write_async(serial_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
-
- uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
- uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
- if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
- tx_fifo_busy = tx_fifo_max;
- }
- uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
- if (tx_fifo_free == 0) {
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- }
- return 0;
- }
-
- uint32_t bytes_per_word = obj->tx_buff.width / 8;
-
- uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
- int n_words = 0;
- while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
- switch (bytes_per_word) {
- case 4:
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- case 2:
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- case 1:
- UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
- }
-
- n_words ++;
- tx_fifo_free -= bytes_per_word;
- obj->tx_buff.pos ++;
- }
-
- if (n_words) {
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
- }
- }
-
- return n_words;
-}
-
-static int serial_read_async(serial_t *obj)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
- //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
- //if (rx_fifo_free == 0) {
- // return 0;
- //}
-
- uint32_t bytes_per_word = obj->rx_buff.width / 8;
-
- uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
- int n_words = 0;
- while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
- switch (bytes_per_word) {
- case 4:
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- case 2:
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- case 1:
- *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
- }
-
- n_words ++;
- rx_fifo_busy -= bytes_per_word;
- obj->rx_buff.pos ++;
-
- if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
- obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
- uint8_t *rx_cmp = rx;
- switch (bytes_per_word) {
- case 4:
- rx_cmp -= 2;
- case 2:
- rx_cmp --;
- case 1:
- rx_cmp --;
- }
- if (*rx_cmp == obj->char_match) {
- obj->char_found = 1;
- break;
- }
- }
- }
-
- if (n_words) {
- // Simulate clear of the interrupt flag
- if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
- UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
- }
- }
-
- return n_words;
-}
-
-static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
-{
- obj->tx_buff.buffer = (void *) tx;
- obj->tx_buff.length = length;
- obj->tx_buff.pos = 0;
- obj->tx_buff.width = width;
-}
-
-static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
-{
- obj->rx_buff.buffer = rx;
- obj->rx_buff.length = length;
- obj->rx_buff.pos = 0;
- obj->rx_buff.width = width;
-}
-
-static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- // Necessary for both interrupt way and DMA way
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
- // With our own async vector, tx/rx handlers can be different.
- obj->serial.vec = var->vec_async;
- obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
- serial_irq_set(obj, TxIrq, enable);
-}
-
-static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->serial.uart);
-
- // Necessary for both interrupt way and DMA way
- struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
- // With our own async vector, tx/rx handlers can be different.
- obj->serial.vec = var->vec_async;
- obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
- serial_irq_set(obj, RxIrq, enable);
-}
-
-static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
-{
- if (*dma_usage != DMA_USAGE_NEVER) {
- if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
- }
- if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_usage = DMA_USAGE_NEVER;
- }
- }
- else {
- dma_channel_free(*dma_ch);
- *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
- }
-}
-
-static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
-{
- int inten_msk = 0;
-
- switch (irq) {
- case RxIrq:
- inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
- break;
- case TxIrq:
- inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
- break;
- }
-
- return !! inten_msk;
-}
-
-#endif // #if DEVICE_SERIAL_ASYNCH
-#endif // #if DEVICE_SERIAL
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,120 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "sleep_api.h"
-#include "serial_api.h"
-#include "lp_ticker_api.h"
-
-#if DEVICE_SLEEP
-
-#include "cmsis.h"
-#include "device.h"
-#include "objects.h"
-#include "PeripheralPins.h"
-
-void us_ticker_prepare_sleep(struct sleep_s *obj);
-void us_ticker_wakeup_from_sleep(struct sleep_s *obj);
-static void mbed_enter_sleep(struct sleep_s *obj);
-static void mbed_exit_sleep(struct sleep_s *obj);
-
-int serial_allow_powerdown(void);
-int spi_allow_powerdown(void);
-int i2c_allow_powerdown(void);
-int pwmout_allow_powerdown(void);
-
-/**
- * Enter Idle mode.
- */
-void sleep(void)
-{
- struct sleep_s sleep_obj;
- sleep_obj.powerdown = 0;
- mbed_enter_sleep(&sleep_obj);
- mbed_exit_sleep(&sleep_obj);
-}
-
-/**
- * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode.
- */
-void deepsleep(void)
-{
- struct sleep_s sleep_obj;
- sleep_obj.powerdown = 1;
- mbed_enter_sleep(&sleep_obj);
- mbed_exit_sleep(&sleep_obj);
-}
-
-static void mbed_enter_sleep(struct sleep_s *obj)
-{
- // Check if serial allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = serial_allow_powerdown();
- }
- // Check if spi allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = spi_allow_powerdown();
- }
- // Check if i2c allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = i2c_allow_powerdown();
- }
- // Check if pwmout allows entering power-down mode
- if (obj->powerdown) {
- obj->powerdown = pwmout_allow_powerdown();
- }
- // TODO: Check if other peripherals allow entering power-down mode
-
- obj->start_us = lp_ticker_read();
- // Let us_ticker prepare for power-down or reject it.
- us_ticker_prepare_sleep(obj);
-
- // NOTE(STALE): To pass mbed-drivers test, timer requires to be fine-grained, so its implementation needs HIRC rather than LIRC/LXT as its clock source.
- // But as CLK_PowerDown()/CLK_Idle() is called, HIRC will be disabled and timer cannot keep counting and alarm. To overcome the dilemma,
- // just make CPU halt and compromise power saving.
- // NOTE: As CLK_PowerDown()/CLK_Idle() is called, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
-
- if (obj->powerdown) { // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled)
- SYS_UnlockReg();
- CLK_PowerDown();
- SYS_LockReg();
- }
- else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled)
- // NOTE: NUC472's CLK_Idle() will also disable HIRC/HXT.
- SYS_UnlockReg();
- SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
- CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
- __WFI();
- SYS_LockReg();
- }
- __NOP();
- __NOP();
- __NOP();
- __NOP();
-
- obj->end_us = lp_ticker_read();
- obj->period_us = (obj->end_us > obj->start_us) ? (obj->end_us - obj->start_us) : (uint32_t) ((uint64_t) obj->end_us + 0xFFFFFFFFu - obj->start_us);
- // Let us_ticker recover from power-down.
- us_ticker_wakeup_from_sleep(obj);
-}
-
-static void mbed_exit_sleep(struct sleep_s *obj)
-{
- // TODO: TO BE CONTINUED
-
- (void)obj;
-}
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,768 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "spi_api.h"
-
-#if DEVICE_SPI
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "nu_bitutil.h"
-
-#if DEVICE_SPI_ASYNCH
-#include "dma_api.h"
-#include "dma.h"
-#endif
-
-#define NU_SPI_FRAME_MIN 8
-#define NU_SPI_FRAME_MAX 32
-#define NU_SPI_FIFO_DEPTH 8
-
-struct nu_spi_var {
-#if DEVICE_SPI_ASYNCH
- uint8_t pdma_perp_tx;
- uint8_t pdma_perp_rx;
-#endif
-};
-
-static struct nu_spi_var spi0_var = {
-#if DEVICE_SPI_ASYNCH
- .pdma_perp_tx = PDMA_SPI0_TX,
- .pdma_perp_rx = PDMA_SPI0_RX
-#endif
-};
-static struct nu_spi_var spi1_var = {
-#if DEVICE_SPI_ASYNCH
- .pdma_perp_tx = PDMA_SPI1_TX,
- .pdma_perp_rx = PDMA_SPI1_RX
-#endif
-};
-static struct nu_spi_var spi2_var = {
-#if DEVICE_SPI_ASYNCH
- .pdma_perp_tx = PDMA_SPI2_TX,
- .pdma_perp_rx = PDMA_SPI2_RX
-#endif
-};
-static struct nu_spi_var spi3_var = {
-#if DEVICE_SPI_ASYNCH
- .pdma_perp_tx = PDMA_SPI3_TX,
- .pdma_perp_rx = PDMA_SPI3_RX
-#endif
-};
-
-#if DEVICE_SPI_ASYNCH
-static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable);
-static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable);
-static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit);
-static uint32_t spi_master_read_asynch(spi_t *obj);
-static uint32_t spi_event_check(spi_t *obj);
-static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable);
-static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
-static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx);
-static uint8_t spi_get_data_width(spi_t *obj);
-static int spi_is_tx_complete(spi_t *obj);
-static int spi_is_rx_complete(spi_t *obj);
-static int spi_writeable(spi_t * obj);
-static int spi_readable(spi_t * obj);
-static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma);
-static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma);
-#endif
-
-static uint32_t spi_modinit_mask = 0;
-
-static const struct nu_modinit_s spi_modinit_tab[] = {
- {SPI_0, SPI0_MODULE, 0, 0, SPI0_RST, SPI0_IRQn, &spi0_var},
- {SPI_1, SPI1_MODULE, 0, 0, SPI1_RST, SPI1_IRQn, &spi1_var},
- {SPI_2, SPI2_MODULE, 0, 0, SPI2_RST, SPI2_IRQn, &spi2_var},
- {SPI_3, SPI3_MODULE, 0, 0, SPI3_RST, SPI3_IRQn, &spi3_var},
-
- {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
-};
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
- // Determine which SPI_x the pins are used for
- uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
- uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
- uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
- uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
- uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
- uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
- obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl);
- MBED_ASSERT((int)obj->spi.spi != NC);
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- // Reset this module
- SYS_ResetModule(modinit->rsetidx);
-
- // Enable IP clock
- CLK_EnableModuleClock(modinit->clkidx);
-
- //SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- pinmap_pinout(mosi, PinMap_SPI_MOSI);
- pinmap_pinout(miso, PinMap_SPI_MISO);
- pinmap_pinout(sclk, PinMap_SPI_SCLK);
- pinmap_pinout(ssel, PinMap_SPI_SSEL);
-
- obj->spi.pin_mosi = mosi;
- obj->spi.pin_miso = miso;
- obj->spi.pin_sclk = sclk;
- obj->spi.pin_ssel = ssel;
-
- // Configure the SPI data format and frequency
- //spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
- //spi_frequency(obj, 1000000);
-
-#if DEVICE_SPI_ASYNCH
- obj->spi.dma_usage = DMA_USAGE_NEVER;
- obj->spi.event = 0;
- obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
-#endif
-
- // Mark this module to be inited.
- int i = modinit - spi_modinit_tab;
- spi_modinit_mask |= 1 << i;
-}
-
-void spi_free(spi_t *obj)
-{
-#if DEVICE_SPI_ASYNCH
- if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->spi.dma_chn_id_tx);
- obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- }
- if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- dma_channel_free(obj->spi.dma_chn_id_rx);
- obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-#endif
-
- SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi));
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOVIEN_MASK | SPI_FIFO_RXTHIEN_MASK | SPI_FIFO_TXTHIEN_MASK));
- NVIC_DisableIRQ(modinit->irq_n);
-
- // Disable IP clock
- CLK_DisableModuleClock(modinit->clkidx);
-
- //((struct nu_spi_var *) modinit->var)->obj = NULL;
-
- // Mark this module to be deinited.
- int i = modinit - spi_modinit_tab;
- spi_modinit_mask &= ~(1 << i);
-}
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
- MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
-
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- // NOTE 1: All configurations should be ready before enabling SPI peripheral.
- // NOTE 2: Re-configuration is allowed only as SPI peripheral is idle.
- while (SPI_IS_BUSY(spi_base));
- SPI_DISABLE(spi_base);
-
- SPI_Open(spi_base,
- slave ? SPI_SLAVE : SPI_MASTER,
- (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3,
- bits,
- SPI_GetBusClock(spi_base));
- // NOTE: Hardcode to be MSB first.
- SPI_SET_MSB_FIRST(spi_base);
-
- if (! slave) {
- // Master
- if (obj->spi.pin_ssel != NC) {
- // Configure SS as low active.
- SPI_EnableAutoSS(spi_base, SPI_SS0, SPI_SS_ACTIVE_LOW);
- // NOTE: In NUC472 series, all SPI SS pins are SS0, so we can hardcode SS0 here.
- }
- else {
- SPI_DisableAutoSS(spi_base);
- }
- }
- else {
- // Slave
- // Configure SS as low active.
- spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
- // NOTE: SPI_SS0 is defined as the slave select input in Slave mode.
- }
-}
-
-void spi_frequency(spi_t *obj, int hz)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- while (SPI_IS_BUSY(spi_base));
- SPI_DISABLE(spi_base);
-
- SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz);
-}
-
-
-int spi_master_write(spi_t *obj, int value)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- // NOTE: Data in receive FIFO can be read out via ICE.
- SPI_ENABLE(spi_base);
-
- // Wait for tx buffer empty
- while(! spi_writeable(obj));
- SPI_WRITE_TX(spi_base, value);
-
- // Wait for rx buffer full
- while (! spi_readable(obj));
- int value2 = SPI_READ_RX(spi_base);
-
- SPI_DISABLE(spi_base);
-
- return value2;
-}
-
-#if DEVICE_SPISLAVE
-int spi_slave_receive(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- SPI_ENABLE(spi_base);
-
- return spi_readable(obj);
-};
-
-int spi_slave_read(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- SPI_ENABLE(spi_base);
-
- // Wait for rx buffer full
- while (! spi_readable(obj));
- int value = SPI_READ_RX(spi_base);
- return value;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- SPI_ENABLE(spi_base);
-
- // Wait for tx buffer empty
- while(! spi_writeable(obj));
- SPI_WRITE_TX(spi_base, value);
-}
-#endif
-
-#if DEVICE_SPI_ASYNCH
-void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
-{
- //MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX);
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
- SPI_SET_DATA_WIDTH(spi_base, bit_width);
-
- obj->spi.dma_usage = hint;
- spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx);
- uint32_t data_width = spi_get_data_width(obj);
- // Conditions to go DMA way:
- // (1) No DMA support for non-8 multiple data width.
- // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx.
- if ((data_width % 8) ||
- (tx_length < rx_length)) {
- obj->spi.dma_usage = DMA_USAGE_NEVER;
- dma_channel_free(obj->spi.dma_chn_id_tx);
- obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
- dma_channel_free(obj->spi.dma_chn_id_rx);
- obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-
- // SPI IRQ is necessary for both interrupt way and DMA way
- spi_enable_event(obj, event, 1);
- spi_buffer_set(obj, tx, tx_length, rx, rx_length);
-
- SPI_ENABLE(spi_base);
-
- if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
- // Interrupt way
- spi_master_write_asynch(obj, NU_SPI_FIFO_DEPTH / 2);
- spi_enable_vector_interrupt(obj, handler, 1);
- spi_master_enable_interrupt(obj, 1);
- } else {
- // DMA way
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- // Configure tx DMA
- PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->spi.dma_chn_id_tx,
- ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->spi.dma_chn_id_tx,
- (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- tx_length);
- PDMA_SetTransferAddr(obj->spi.dma_chn_id_tx,
- ((uint32_t) tx) + (data_width / 8) * tx_length, // NOTE: End of source address
- PDMA_SAR_INC, // Source address incremental
- (uint32_t) &spi_base->TX, // Destination address
- PDMA_DAR_FIX); // Destination address fixed
- PDMA_SetBurstType(obj->spi.dma_chn_id_tx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->spi.dma_chn_id_tx,
- 0); // Interrupt type. No use here
- // Register DMA event handler
- dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
-
- // Configure rx DMA
- PDMA->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel
- PDMA_SetTransferMode(obj->spi.dma_chn_id_rx,
- ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
- 0, // Scatter-gather disabled
- 0); // Scatter-gather descriptor address
- PDMA_SetTransferCnt(obj->spi.dma_chn_id_rx,
- (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
- rx_length);
- PDMA_SetTransferAddr(obj->spi.dma_chn_id_rx,
- (uint32_t) &spi_base->RX, // Source address
- PDMA_SAR_FIX, // Source address fixed
- ((uint32_t) rx) + (data_width / 8) * rx_length, // NOTE: End of destination address
- PDMA_DAR_INC); // Destination address incremental
- PDMA_SetBurstType(obj->spi.dma_chn_id_rx,
- PDMA_REQ_SINGLE, // Single mode
- 0); // Burst size
- PDMA_EnableInt(obj->spi.dma_chn_id_rx,
- 0); // Interrupt type. No use here
- // Register DMA event handler
- dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
-
- // Start tx/rx DMA transfer
- spi_enable_vector_interrupt(obj, handler, 1);
- // NOTE: It is safer to start rx DMA first and then tx DMA. Otherwise, receive FIFO is subject to overflow by tx DMA.
- SPI_TRIGGER_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
- SPI_TRIGGER_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
- spi_master_enable_interrupt(obj, 1);
- }
-}
-
-/**
- * Abort an SPI transfer
- * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing
- * transfers
- * @param[in] obj The SPI peripheral to stop
- */
-void spi_abort_asynch(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- if (obj->spi.dma_usage != DMA_USAGE_NEVER) {
- // Receive FIFO Overrun in case of tx length > rx length on DMA way
- if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
- spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
- }
-
- if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->spi.dma_chn_id_tx, 0);
- // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->spi.dma_chn_id_tx);
- PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx);
- }
- SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
-
- if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
- PDMA_DisableInt(obj->spi.dma_chn_id_rx, 0);
- // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
- //PDMA_STOP(obj->spi.dma_chn_id_rx);
- PDMA->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx);
- }
- SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi)));
- }
-
- // Necessary for both interrupt way and DMA way
- spi_enable_vector_interrupt(obj, 0, 0);
- spi_master_enable_interrupt(obj, 0);
-
- // FIXME: SPI H/W may get out of state without the busy check.
- while (SPI_IS_BUSY(spi_base));
- SPI_DISABLE(spi_base);
-
- SPI_ClearRxFIFO(spi_base);
- SPI_ClearTxFIFO(spi_base);
-}
-
-/**
- * Handle the SPI interrupt
- * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way,
- * it is unlikely that the RX FIFO will overflow.
- * @param[in] obj The SPI peripheral that generated the interrupt
- * @return
- */
-uint32_t spi_irq_handler_asynch(spi_t *obj)
-{
- // Check for SPI events
- uint32_t event = spi_event_check(obj);
- if (event) {
- spi_abort_asynch(obj);
- }
-
- return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0);
-}
-
-uint8_t spi_active(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
- // FIXME
- /*
- if ((obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length)
- || (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) ){
- return 1;
- } else {
- // interrupts are disabled, all transaction have been completed
- // TODO: checking rx fifo, it reports data eventhough RFDF is not set
- return DSPI_HAL_GetIntMode(obj->spi.address, kDspiRxFifoDrainRequest);
- }*/
-
- //return SPI_IS_BUSY(spi_base);
- return (spi_base->CTL & SPI_CTL_SPIEN_Msk);
-}
-
-int spi_allow_powerdown(void)
-{
- uint32_t modinit_mask = spi_modinit_mask;
- while (modinit_mask) {
- int spi_idx = nu_ctz(modinit_mask);
- const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx;
- if (modinit->modname != NC) {
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname);
- // Disallow entering power-down mode if SPI transfer is enabled.
- if (spi_base->CTL & SPI_CTL_SPIEN_Msk) {
- return 0;
- }
- }
- modinit_mask &= ~(1 << spi_idx);
- }
-
- return 1;
-}
-
-static int spi_writeable(spi_t * obj)
-{
- // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive
- //return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))) && (SPI_GET_RX_FIFO_COUNT(((SPI_T *) NU_MODBASE(obj->spi.spi))) < NU_SPI_FIFO_DEPTH);
- return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
-}
-
-static int spi_readable(spi_t * obj)
-{
- return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)));
-}
-
-static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable)
-{
- obj->spi.event &= ~SPI_EVENT_ALL;
- obj->spi.event |= (event & SPI_EVENT_ALL);
- if (event & SPI_EVENT_RX_OVERFLOW) {
- SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOVIEN_MASK);
- }
-}
-
-static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable)
-{
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- if (enable) {
- NVIC_SetVector(modinit->irq_n, handler);
- NVIC_EnableIRQ(modinit->irq_n);
- }
- else {
- //NVIC_SetVector(modinit->irq_n, handler);
- NVIC_DisableIRQ(modinit->irq_n);
- }
-}
-
-static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- if (enable) {
- SPI_SetFIFOThreshold(spi_base, 4, 4);
- //SPI_SET_SUSPEND_CYCLE(spi_base, 4);
- // Enable tx/rx FIFO threshold interrupt
- SPI_EnableInt(spi_base, SPI_FIFO_RXTHIEN_MASK | SPI_FIFO_TXTHIEN_MASK);
- }
- else {
- SPI_DisableInt(spi_base, SPI_FIFO_RXTHIEN_MASK | SPI_FIFO_TXTHIEN_MASK);
- }
-}
-
-static uint32_t spi_event_check(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
- uint32_t event = 0;
-
- if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
- uint32_t n_rec = spi_master_read_asynch(obj);
- spi_master_write_asynch(obj, n_rec);
- }
-
- if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) {
- event |= SPI_EVENT_COMPLETE;
- }
-
- // Receive FIFO Overrun
- if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) {
- spi_base->STATUS = SPI_STATUS_RXOVIF_Msk;
- // In case of tx length > rx length on DMA way
- if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
- event |= SPI_EVENT_RX_OVERFLOW;
- }
- }
-
- // Receive Time-Out
- if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) {
- spi_base->STATUS = SPI_STATUS_RXTOIF_Msk;
- //event |= SPI_EVENT_ERROR;
- }
- // Transmit FIFO Under-Run
- if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) {
- spi_base->STATUS = SPI_STATUS_TXUFIF_Msk;
- event |= SPI_EVENT_ERROR;
- }
-
- return event;
-}
-
-/**
- * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full
- * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed.
- * @param[in] obj The SPI object on which to operate
- * @param[in] tx_limit The maximum number of words to send
- * @return The number of SPI words that have been transfered
- */
-static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
-{
- uint32_t n_words = 0;
- uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
- uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
- uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
- max_tx = NU_MIN(max_tx, tx_limit);
- uint8_t data_width = spi_get_data_width(obj);
- uint8_t bytes_per_word = (data_width + 7) / 8;
- uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- while ((n_words < max_tx) && spi_writeable(obj)) {
- if (spi_is_tx_complete(obj)) {
- // Transmit dummy as transmit buffer is empty
- SPI_WRITE_TX(spi_base, 0);
- }
- else {
- switch (bytes_per_word) {
- case 4:
- SPI_WRITE_TX(spi_base, nu_get32_le(tx));
- tx += 4;
- break;
- case 2:
- SPI_WRITE_TX(spi_base, nu_get16_le(tx));
- tx += 2;
- break;
- case 1:
- SPI_WRITE_TX(spi_base, *((uint8_t *) tx));
- tx += 1;
- break;
- }
-
- obj->tx_buff.pos ++;
- }
- n_words ++;
- }
-
- //Return the number of words that have been sent
- return n_words;
-}
-
-/**
- * Read SPI words out of the RX FIFO
- * Continues reading words out of the RX FIFO until the following condition is met:
- * o There are no more words in the FIFO
- * OR BOTH OF:
- * o At least as many words as the TX buffer have been received
- * o At least as many words as the RX buffer have been received
- * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size
- * @param[in] obj The SPI object on which to operate
- * @return Returns the number of words extracted from the RX FIFO
- */
-static uint32_t spi_master_read_asynch(spi_t *obj)
-{
- uint32_t n_words = 0;
- uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
- uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
- uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
- uint8_t data_width = spi_get_data_width(obj);
- uint8_t bytes_per_word = (data_width + 7) / 8;
- uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- while ((n_words < max_rx) && spi_readable(obj)) {
- if (spi_is_rx_complete(obj)) {
- // Disregard as receive buffer is full
- SPI_READ_RX(spi_base);
- }
- else {
- switch (bytes_per_word) {
- case 4: {
- uint32_t val = SPI_READ_RX(spi_base);
- nu_set32_le(rx, val);
- rx += 4;
- break;
- }
- case 2: {
- uint16_t val = SPI_READ_RX(spi_base);
- nu_set16_le(rx, val);
- rx += 2;
- break;
- }
- case 1:
- *rx ++ = SPI_READ_RX(spi_base);
- break;
- }
-
- obj->rx_buff.pos ++;
- }
- n_words ++;
- }
-
- // Return the number of words received
- return n_words;
-}
-
-static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
-{
- obj->tx_buff.buffer = (void *) tx;
- obj->tx_buff.length = tx_length;
- obj->tx_buff.pos = 0;
- obj->tx_buff.width = spi_get_data_width(obj);
- obj->rx_buff.buffer = rx;
- obj->rx_buff.length = rx_length;
- obj->rx_buff.pos = 0;
- obj->rx_buff.width = spi_get_data_width(obj);
-}
-
-static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx)
-{
- if (*dma_usage != DMA_USAGE_NEVER) {
- if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE);
- }
- if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE);
- }
-
- if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) {
- *dma_usage = DMA_USAGE_NEVER;
- }
- }
-
- if (*dma_usage == DMA_USAGE_NEVER) {
- dma_channel_free(*dma_ch_tx);
- *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS;
- dma_channel_free(*dma_ch_rx);
- *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS;
- }
-}
-
-static uint8_t spi_get_data_width(spi_t *obj)
-{
- SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
-
- return ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos);
-}
-
-static int spi_is_tx_complete(spi_t *obj)
-{
- // ???: Exclude tx fifo empty check due to no such interrupt on DMA way
- return (obj->tx_buff.pos == obj->tx_buff.length);
- //return (obj->tx_buff.pos == obj->tx_buff.length && SPI_GET_TX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))));
-}
-
-static int spi_is_rx_complete(spi_t *obj)
-{
- return (obj->rx_buff.pos == obj->rx_buff.length);
-}
-
-static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma)
-{
- spi_t *obj = (spi_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect SPI IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->tx_buff.pos = obj->tx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
- vec();
-}
-
-static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma)
-{
- spi_t *obj = (spi_t *) id;
-
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_ABORT) {
- }
- // Expect SPI IRQ will catch this transfer done event
- if (event_dma & DMA_EVENT_TRANSFER_DONE) {
- obj->rx_buff.pos = obj->rx_buff.length;
- }
- // FIXME: Pass this error to caller
- if (event_dma & DMA_EVENT_TIMEOUT) {
- }
-
- const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab);
- MBED_ASSERT(modinit != NULL);
- MBED_ASSERT(modinit->modname == obj->spi.spi);
-
- void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n);
- vec();
-}
-
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,100 +0,0 @@
-/*
- * Hardware entropy collector for NUC472's RNGA
- *
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-#if DEVICE_TRNG
-
-#include <stdlib.h>
-#include <string.h>
-#include "cmsis.h"
-#include "NUC472_442.h"
-#include "us_ticker_api.h"
-#include "trng_api.h"
-
-/*
- * Get Random number generator.
- */
-static volatile int g_PRNG_done;
-
-void CRYPTO_IRQHandler()
-{
- if (PRNG_GET_INT_FLAG()) {
- g_PRNG_done = 1;
- PRNG_CLR_INT_FLAG();
- }
-}
-
-static void trng_get(unsigned char *pConversionData)
-{
- uint32_t *p32ConversionData;
-
- p32ConversionData = (uint32_t *)pConversionData;
-
- PRNG_Open(PRNG_KEY_SIZE_256, 1, us_ticker_read());
- PRNG_Start();
- while (!g_PRNG_done);
-
- PRNG_Read(p32ConversionData);
-}
-
-void trng_init(trng_t *obj)
-{
- (void)obj;
- /* Unlock protected registers */
- SYS_UnlockReg();
- /* Enable IP clock */
- CLK_EnableModuleClock(CRPT_MODULE);
-
- /* Lock protected registers */
- SYS_LockReg();
-
- NVIC_EnableIRQ(CRPT_IRQn);
- PRNG_ENABLE_INT();
-}
-
-void trng_free(trng_t *obj)
-{
- (void)obj;
- PRNG_DISABLE_INT();
- NVIC_DisableIRQ(CRPT_IRQn);
-}
-
-int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
-{
- (void)obj;
-
- *output_length = 0;
- if (length < 32) {
- unsigned char tmpBuff[32];
- trng_get(tmpBuff);
- memcpy(output, &tmpBuff, length);
- *output_length = length;
- } else {
- for (int i = 0; i < (length/32); i++) {
- trng_get(output);
- *output_length += 32;
- output += 32;
- }
- }
-
- return 0;
-}
-
-#endif
-
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,280 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "us_ticker_api.h"
-#include "sleep_api.h"
-#include "mbed_assert.h"
-#include "nu_modutil.h"
-#include "nu_miscutil.h"
-#include "critical.h"
-
-// us_ticker tick = us = timestamp
-#define US_PER_TICK 1
-#define US_PER_SEC (1000 * 1000)
-
-#define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1LORES_CLK_PER_SEC (__LIRC)
-
-#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
-#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
-#define US_PER_TMR1LORES_CLK (US_PER_SEC / TMR1LORES_CLK_PER_SEC)
-
-#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
-#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
-
-
-// Determine to use lo-res/hi-res timer according to CD period
-#define US_TMR_SEP_CD 1000
-
-static void tmr0_vec(void);
-static void tmr1_vec(void);
-static void us_ticker_arm_cd(void);
-
-static int us_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t pd_comp_us = 0; // Power-down compenstaion for normal counter
-static volatile uint32_t cd_major_minor_us = 0;
-static volatile uint32_t cd_minor_us = 0;
-static volatile int cd_hires_tmr_armed = 0; // Flag of armed or not of hi-res timer for CD counter
-
-// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
-// NOTE: Choose clock source of timer:
-// 1. HIRC: Be the most accurate but might cause unknown HardFault.
-// 2. HXT: Less accurate and cannot pass mbed-drivers test.
-// 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
-// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
-static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-static const struct nu_modinit_s timer1lores_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
-static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
-
-#define TMR_CMP_MIN 2
-#define TMR_CMP_MAX 0xFFFFFFu
-
-void us_ticker_init(void)
-{
- if (us_ticker_inited) {
- return;
- }
-
- counter_major = 0;
- pd_comp_us = 0;
- cd_major_minor_us = 0;
- cd_minor_us = 0;
- cd_hires_tmr_armed = 0;
- us_ticker_inited = 1;
-
- // Reset IP
- SYS_ResetModule(timer0hires_modinit.rsetidx);
- SYS_ResetModule(timer1lores_modinit.rsetidx);
-
- // Select IP clock source
- CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
- CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
- // Enable IP clock
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- CLK_EnableModuleClock(timer1lores_modinit.clkidx);
-
- // Timer for normal counter
- uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
- MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
- uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
- MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0 | TIMER_CTL_CNTDATEN_Msk;
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
-
- NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
- NVIC_SetVector(timer1lores_modinit.irq_n, (uint32_t) timer1lores_modinit.var);
-
- NVIC_EnableIRQ(timer0hires_modinit.irq_n);
- NVIC_EnableIRQ(timer1lores_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
-}
-
-uint32_t us_ticker_read()
-{
- if (! us_ticker_inited) {
- us_ticker_init();
- }
-
- TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
-
- do {
- uint32_t major_minor_us;
- uint32_t minor_us;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
- uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
- major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
- }
- else {
- major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
-
- // Add power-down compensation
- return (major_minor_us + pd_comp_us) / US_PER_TICK;
- }
- while (0);
-}
-
-void us_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-}
-
-void us_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
-}
-
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
- cd_hires_tmr_armed = 0;
-
- int delta = (int) (timestamp - us_ticker_read());
- if (delta > 0) {
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
- }
- else {
- cd_major_minor_us = cd_minor_us = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer1lores_modinit.irq_n);
- }
-}
-
-void us_ticker_prepare_sleep(struct sleep_s *obj)
-{
- // Reject power-down if hi-res timer (HIRC/HXT) is now armed for CD counter.
- if (obj->powerdown) {
- obj->powerdown = ! cd_hires_tmr_armed;
- }
-
- core_util_critical_section_enter();
-
- if (obj->powerdown) {
- // NOTE: On entering power-down mode, HIRC/HXT will be disabled in normal mode, but not in ICE mode. This may cause confusion in development.
- // To not be inconsistent due to above, always disable clock source of normal counter, and then re-enable it and make compensation on wakeup from power-down.
- CLK_DisableModuleClock(timer0hires_modinit.clkidx);
- }
-
- core_util_critical_section_exit();
-}
-
-void us_ticker_wakeup_from_sleep(struct sleep_s *obj)
-{
- core_util_critical_section_enter();
-
- if (obj->powerdown) {
- // Calculate power-down compensation
- pd_comp_us += obj->period_us;
-
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- }
-
- core_util_critical_section_exit();
-}
-
-static void tmr0_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- counter_major ++;
-}
-
-static void tmr1_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
- cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
- cd_hires_tmr_armed = 0;
- if (cd_major_minor_us == 0) {
- // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
- us_ticker_irq_handler();
- }
- else {
- us_ticker_arm_cd();
- }
-}
-
-static void us_ticker_arm_cd(void)
-{
- TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1lores_modinit.modname);
- uint32_t tmr1_clk_per_sec;
- uint32_t us_per_tmr1_clk;
-
- /**
- * Reserve US_TMR_SEP_CD-plus alarm period for hi-res timer
- * 1. period >= US_TMR_SEP_CD * 2. Divide into two rounds:
- * US_TMR_SEP_CD * n (lo-res timer)
- * US_TMR_SEP_CD + period % US_TMR_SEP_CD (hi-res timer)
- * 2. period < US_TMR_SEP_CD * 2. Just one round:
- * period (hi-res timer)
- */
- if (cd_major_minor_us >= US_TMR_SEP_CD * 2) {
- cd_minor_us = cd_major_minor_us - cd_major_minor_us % US_TMR_SEP_CD - US_TMR_SEP_CD;
-
- CLK_SetModuleClock(timer1lores_modinit.clkidx, timer1lores_modinit.clksrc, timer1lores_modinit.clkdiv);
- tmr1_clk_per_sec = TMR1LORES_CLK_PER_SEC;
- us_per_tmr1_clk = US_PER_TMR1LORES_CLK;
-
- cd_hires_tmr_armed = 0;
- }
- else {
- cd_minor_us = cd_major_minor_us;
-
- CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
- tmr1_clk_per_sec = TMR1HIRES_CLK_PER_SEC;
- us_per_tmr1_clk = US_PER_TMR1HIRES_CLK;
-
- cd_hires_tmr_armed = 1;
- }
-
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 MHz
- uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1lores_modinit.modname));
- uint32_t prescale_timer1 = clk_timer1 / tmr1_clk_per_sec - 1;
- MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
- MBED_ASSERT((clk_timer1 % tmr1_clk_per_sec) == 0);
- timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
- timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1 | TIMER_CTL_CNTDATEN_Msk;
-
- uint32_t cmp_timer1 = cd_minor_us / us_per_tmr1_clk;
- cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
- timer1_base->CMP = cmp_timer1;
-
- TIMER_EnableInt(timer1_base);
- TIMER_Start(timer1_base);
-}
--- a/targets/TARGET_NUVOTON/mbed_rtx.h Thu Dec 15 11:48:27 2016 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,94 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - -#if defined(TARGET_NUMAKER_PFM_NUC472) - -#ifndef OS_TASKCNT -#define OS_TASKCNT 14 -#endif -#ifndef OS_MAINSTKSIZE -#define OS_MAINSTKSIZE 256 -#endif -#ifndef OS_CLOCK -#define OS_CLOCK 84000000 -#endif - -#if defined(__CC_ARM) - extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[]; - extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[]; - extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; - extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[]; - #define HEAP_START ((unsigned char*) Image$$ARM_LIB_HEAP$$ZI$$Base) - #define HEAP_SIZE ((uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length) - #define ISR_STACK_START ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base) - #define ISR_STACK_SIZE ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length) -#elif defined(__GNUC__) - extern uint32_t __StackTop[]; - extern uint32_t __StackLimit[]; - extern uint32_t __end__[]; - extern uint32_t __HeapLimit[]; - #define HEAP_START ((unsigned char*)__end__) - #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) - #define ISR_STACK_START ((unsigned char*)__StackLimit) - #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) -#elif defined(__ICCARM__) - /* No region declarations needed */ -#else - #error "no toolchain defined" -#endif - -#elif defined(TARGET_NUMAKER_PFM_M453) - -#ifndef OS_TASKCNT -#define OS_TASKCNT 14 -#endif -#ifndef OS_MAINSTKSIZE -#define OS_MAINSTKSIZE 256 -#endif -#ifndef OS_CLOCK -#define OS_CLOCK 72000000 -#endif - -#if defined(__CC_ARM) - extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[]; - extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[]; - extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; - extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[]; - #define HEAP_START ((unsigned char*) Image$$ARM_LIB_HEAP$$ZI$$Base) - #define HEAP_SIZE ((uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length) - #define ISR_STACK_START ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base) - #define ISR_STACK_SIZE ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length) -#elif defined(__GNUC__) - extern uint32_t __StackTop[]; - extern uint32_t __StackLimit[]; - extern uint32_t __end__[]; - extern uint32_t __HeapLimit[]; - #define HEAP_START ((unsigned char*)__end__) - #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) - #define ISR_STACK_START ((unsigned char*)__StackLimit) - #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) -#elif defined(__ICCARM__) - /* No region declarations needed */ -#else - #error "no toolchain defined" -#endif - -#endif - -#endif // MBED_MBED_RTX_H
--- a/targets/TARGET_NUVOTON/nu_bitutil.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef NU_BIT_UTIL_H
-#define NU_BIT_UTIL_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-__STATIC_INLINE int nu_clz(uint32_t x)
-{
- return __CLZ(x);
-}
-
-__STATIC_INLINE int nu_clo(uint32_t x)
-{
- return nu_clz(~x);
-}
-
-__STATIC_INLINE int nu_ctz(uint32_t x)
-{
- int c = __CLZ(x & -x);
- return x ? 31 - c : c;
-}
-
-__STATIC_INLINE int nu_cto(uint32_t x)
-{
- return nu_ctz(~x);
-}
-
-
-__STATIC_INLINE uint16_t nu_get16_le(const uint8_t *pos)
-{
- uint16_t val;
-
- val = *pos ++;
- val += (*pos << 8);
-
- return val;
-}
-
-__STATIC_INLINE void nu_set16_le(uint8_t *pos, uint16_t val)
-{
- *pos ++ = val & 0xFF;
- *pos = val >> 8;
-}
-
-__STATIC_INLINE uint32_t nu_get32_le(const uint8_t *pos)
-{
- uint32_t val;
-
- val = *pos ++;
- val += (*pos ++ << 8);
- val += (*pos ++ << 16);
- val += (*pos ++ << 24);
-
- return val;
-}
-
-__STATIC_INLINE void nu_set32_le(uint8_t *pos, uint32_t val)
-{
- *pos ++ = val & 0xFF;
- *pos ++ = (val >> 8) & 0xFF;
- *pos ++ = (val >> 16) & 0xFF;
- *pos = (val >> 24) & 0xFF;
-}
-
-__STATIC_INLINE uint16_t nu_get16_be(const uint8_t *pos)
-{
- uint16_t val;
-
- val = *pos ++;
- val <<= 8;
- val += *pos;
-
- return val;
-}
-
-__STATIC_INLINE void nu_set16_be(uint8_t *pos, uint16_t val)
-{
- *pos ++ = val >> 8;
- *pos = (val & 0xFF);
-}
-
-__STATIC_INLINE uint32_t nu_get32_be(const uint8_t *pos)
-{
- uint32_t val;
-
- val = *pos ++;
- val <<= 8;
- val += *pos ++;
- val <<= 8;
- val += *pos ++;
- val <<= 8;
- val += *pos;
-
- return val;
-}
-
-__STATIC_INLINE void nu_set32_be(uint8_t *pos, uint32_t val)
-{
- *pos ++ = val >> 24;
- *pos ++ = val >> 16;
- *pos ++ = val >> 8;
- *pos ++ = (val & 0xFF);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/nu_miscutil.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "mbed_assert.h"
-#include "PinNames.h"
-#include "nu_miscutil.h"
-
-void nu_nop(uint32_t n)
-{
- uint32_t times = n / 10;
- uint32_t rmn = n % 10;
-
- while (times --) {
- __NOP();
- __NOP();
- __NOP();
- __NOP();
- __NOP();
- __NOP();
- __NOP();
- __NOP();
- __NOP();
- __NOP();
- }
-
- switch (rmn) {
- case 9:
- __NOP();
- case 8:
- __NOP();
- case 7:
- __NOP();
- case 6:
- __NOP();
- case 5:
- __NOP();
- case 4:
- __NOP();
- case 3:
- __NOP();
- case 2:
- __NOP();
- case 1:
- __NOP();
- default:
- break;
- }
-}
--- a/targets/TARGET_NUVOTON/nu_miscutil.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef NU_MISC_UTIL_H
-#define NU_MISC_UTIL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NU_MAX(a,b) ((a)>(b)?(a):(b))
-#define NU_MIN(a,b) ((a)<(b)?(a):(b))
-#define NU_CLAMP(x, min, max) NU_MIN(NU_MAX((x), (min)), (max))
-
-void nu_nop(uint32_t n);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/targets/TARGET_NUVOTON/nu_modutil.c Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "mbed_assert.h"
-#include "PinNames.h"
-#include "nu_modutil.h"
-
-const struct nu_modinit_s *get_modinit(uint32_t modname, const struct nu_modinit_s *modprop_tab)
-{
- MBED_ASSERT(modprop_tab != NULL);
- const struct nu_modinit_s *modprop_ind = modprop_tab;
- while (modprop_ind->modname != NC) {
- if (modname == modprop_ind->modname) {
- return modprop_ind;
- }
- else {
- modprop_ind ++;
- }
- }
-
- return NULL;
-}
--- a/targets/TARGET_NUVOTON/nu_modutil.h Thu Dec 15 11:48:27 2016 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015-2016 Nuvoton
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef NU_MODULE_UTIL_H
-#define NU_MODULE_UTIL_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct nu_modinit_s {
- int modname;
- uint32_t clkidx;
- uint32_t clksrc;
- uint32_t clkdiv;
- uint32_t rsetidx;
-
- IRQn_Type irq_n;
- //int irq_n;
-
- void *var;
-};
-
-const struct nu_modinit_s *get_modinit(uint32_t modname, const struct nu_modinit_s *modprop_tab);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif