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TARGET_NUCLEO_F072RB/stm32f0xx_hal_spi.h@93:e188a91d3eaa, 2015-02-03 (annotated)

Committer:: Kojto
Date:: Tue Feb 03 15:31:20 2015 +0000
Revision:: 93:e188a91d3eaa
Parent:: 92:4fc01daae5a5

Release 93 of the mbed library



Main changes:



- Renesas RZ_A1H bugfixes - i2c, ticker

- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,

                Dragonfly 411RE,

- BusXXX - is connected method, plus operators addition

- LPC8xx - I2c fixes

- timestamp_t reverted to uint32_t

- RTX - fixes regarding stack (alignment, magic word)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_spi.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
Kojto	93:e188a91d3eaa	5	* @version V1.2.0
Kojto	93:e188a91d3eaa	6	* @date 11-December-2014
bogdanm	85:024bf7f99721	7	* @brief Header file of SPI HAL module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
bogdanm	85:024bf7f99721	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_SPI_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_SPI_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup SPI
bogdanm	85:024bf7f99721	54	* @{
bogdanm	85:024bf7f99721	55	*/
bogdanm	85:024bf7f99721	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	58	/** @defgroup SPI_Exported_Types SPI Exported Types
bogdanm	92:4fc01daae5a5	59	* @{
bogdanm	92:4fc01daae5a5	60	*/
bogdanm	85:024bf7f99721	61
bogdanm	85:024bf7f99721	62	/**
bogdanm	85:024bf7f99721	63	* @brief SPI Configuration Structure definition
bogdanm	85:024bf7f99721	64	*/
bogdanm	85:024bf7f99721	65	typedef struct
bogdanm	85:024bf7f99721	66	{
bogdanm	85:024bf7f99721	67	uint32_t Mode; /*!< Specifies the SPI operating mode.
bogdanm	85:024bf7f99721	68	This parameter can be a value of @ref SPI_mode */
bogdanm	85:024bf7f99721	69
bogdanm	85:024bf7f99721	70	uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
bogdanm	85:024bf7f99721	71	This parameter can be a value of @ref SPI_Direction */
bogdanm	85:024bf7f99721	72
bogdanm	85:024bf7f99721	73	uint32_t DataSize; /*!< Specifies the SPI data size.
bogdanm	85:024bf7f99721	74	This parameter can be a value of @ref SPI_data_size */
bogdanm	85:024bf7f99721	75
bogdanm	85:024bf7f99721	76	uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm	85:024bf7f99721	77	This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm	85:024bf7f99721	78
bogdanm	85:024bf7f99721	79	uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm	85:024bf7f99721	80	This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm	85:024bf7f99721	81
bogdanm	85:024bf7f99721	82	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm	85:024bf7f99721	83	hardware (NSS pin) or by software using the SSI bit.
bogdanm	85:024bf7f99721	84	This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm	85:024bf7f99721	85
bogdanm	85:024bf7f99721	86	uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm	85:024bf7f99721	87	used to configure the transmit and receive SCK clock.
bogdanm	85:024bf7f99721	88	This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm	85:024bf7f99721	89	@note The communication clock is derived from the master
bogdanm	85:024bf7f99721	90	clock. The slave clock does not need to be set. */
bogdanm	85:024bf7f99721	91
bogdanm	85:024bf7f99721	92	uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm	85:024bf7f99721	93	This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm	85:024bf7f99721	94
bogdanm	85:024bf7f99721	95	uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
bogdanm	85:024bf7f99721	96	This parameter can be a value of @ref SPI_TI_mode */
bogdanm	85:024bf7f99721	97
bogdanm	85:024bf7f99721	98	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm	85:024bf7f99721	99	This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm	85:024bf7f99721	100
bogdanm	85:024bf7f99721	101	uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
bogdanm	85:024bf7f99721	102	This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
bogdanm	85:024bf7f99721	103
bogdanm	85:024bf7f99721	104	uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
bogdanm	85:024bf7f99721	105	CRC Length is only used with Data8 and Data16, not other data size
bogdanm	85:024bf7f99721	106	This parameter must 0 or 1 or 2*/
bogdanm	85:024bf7f99721	107
bogdanm	85:024bf7f99721	108	uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
Kojto	93:e188a91d3eaa	109	This parameter can be a value of @ref SPI_NSSP_Mode
bogdanm	85:024bf7f99721	110	This mode is activated by the NSSP bit in the SPIx_CR2 register and
bogdanm	85:024bf7f99721	111	it takes effect only if the SPI interface is configured as Motorola SPI
bogdanm	85:024bf7f99721	112	master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
bogdanm	85:024bf7f99721	113	CPOL setting is ignored).. */
bogdanm	85:024bf7f99721	114	} SPI_InitTypeDef;
bogdanm	85:024bf7f99721	115
bogdanm	85:024bf7f99721	116	/**
bogdanm	85:024bf7f99721	117	* @brief HAL State structures definition
bogdanm	85:024bf7f99721	118	*/
bogdanm	85:024bf7f99721	119	typedef enum
bogdanm	85:024bf7f99721	120	{
Kojto	93:e188a91d3eaa	121	HAL_SPI_STATE_RESET = 0x00, /!< Peripheral not Initialized /
bogdanm	85:024bf7f99721	122	HAL_SPI_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	85:024bf7f99721	123	HAL_SPI_STATE_BUSY = 0x02, /!< an internal process is ongoing /
Kojto	93:e188a91d3eaa	124	HAL_SPI_STATE_BUSY_TX = 0x03, /!< Data Transmission process is ongoing /
bogdanm	85:024bf7f99721	125	HAL_SPI_STATE_BUSY_RX = 0x04, /!< Data Reception process is ongoing /
Kojto	93:e188a91d3eaa	126	HAL_SPI_STATE_BUSY_TX_RX = 0x05, /!< Data Transmission and Reception process is ongoing /
Kojto	93:e188a91d3eaa	127	HAL_SPI_STATE_ERROR = 0x06 /!< SPI error state /
bogdanm	85:024bf7f99721	128	}HAL_SPI_StateTypeDef;
bogdanm	85:024bf7f99721	129
bogdanm	85:024bf7f99721	130	/**
bogdanm	85:024bf7f99721	131	* @brief SPI handle Structure definition
bogdanm	85:024bf7f99721	132	*/
bogdanm	85:024bf7f99721	133	typedef struct __SPI_HandleTypeDef
bogdanm	85:024bf7f99721	134	{
Kojto	93:e188a91d3eaa	135	SPI_TypeDef Instance; /!< SPI registers base address */
bogdanm	85:024bf7f99721	136
Kojto	93:e188a91d3eaa	137	SPI_InitTypeDef Init; /!< SPI communication parameters /
bogdanm	85:024bf7f99721	138
Kojto	93:e188a91d3eaa	139	uint8_t pTxBuffPtr; /!< Pointer to SPI Tx transfer Buffer */
bogdanm	85:024bf7f99721	140
Kojto	93:e188a91d3eaa	141	uint16_t TxXferSize; /!< SPI Tx Transfer size /
bogdanm	85:024bf7f99721	142
Kojto	93:e188a91d3eaa	143	uint16_t TxXferCount; /!< SPI Tx Transfer Counter /
bogdanm	85:024bf7f99721	144
Kojto	93:e188a91d3eaa	145	uint8_t pRxBuffPtr; /!< Pointer to SPI Rx transfer Buffer */
bogdanm	85:024bf7f99721	146
Kojto	93:e188a91d3eaa	147	uint16_t RxXferSize; /!< SPI Rx Transfer size /
bogdanm	85:024bf7f99721	148
Kojto	93:e188a91d3eaa	149	uint16_t RxXferCount; /!< SPI Rx Transfer Counter /
bogdanm	85:024bf7f99721	150
Kojto	93:e188a91d3eaa	151	uint32_t CRCSize; /!< SPI CRC size used for the transfer /
bogdanm	85:024bf7f99721	152
Kojto	93:e188a91d3eaa	153	void (RxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Rx IRQ handler /
bogdanm	85:024bf7f99721	154
Kojto	93:e188a91d3eaa	155	void (TxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Tx IRQ handler /
bogdanm	85:024bf7f99721	156
Kojto	93:e188a91d3eaa	157	DMA_HandleTypeDef hdmatx; /!< SPI Tx DMA Handle parameters */
bogdanm	85:024bf7f99721	158
Kojto	93:e188a91d3eaa	159	DMA_HandleTypeDef hdmarx; /!< SPI Rx DMA Handle parameters */
bogdanm	85:024bf7f99721	160
Kojto	93:e188a91d3eaa	161	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	85:024bf7f99721	162
Kojto	93:e188a91d3eaa	163	HAL_SPI_StateTypeDef State; /!< SPI communication state /
bogdanm	85:024bf7f99721	164
Kojto	93:e188a91d3eaa	165	__IO uint32_t ErrorCode; /*!< SPI Error code
Kojto	93:e188a91d3eaa	166	This parameter can be a value of @ref SPI_Error */
bogdanm	85:024bf7f99721	167
bogdanm	85:024bf7f99721	168	}SPI_HandleTypeDef;
bogdanm	85:024bf7f99721	169
bogdanm	92:4fc01daae5a5	170	/**
bogdanm	92:4fc01daae5a5	171	* @}
bogdanm	92:4fc01daae5a5	172	*/
bogdanm	92:4fc01daae5a5	173
bogdanm	85:024bf7f99721	174	/* Exported constants --------------------------------------------------------*/
bogdanm	85:024bf7f99721	175
bogdanm	92:4fc01daae5a5	176	/** @defgroup SPI_Exported_Constants SPI Exported Constants
bogdanm	85:024bf7f99721	177	* @{
bogdanm	85:024bf7f99721	178	*/
bogdanm	85:024bf7f99721	179
Kojto	93:e188a91d3eaa	180	/** @defgroup SPI_Error SPI Error
Kojto	93:e188a91d3eaa	181	* @{
Kojto	93:e188a91d3eaa	182	*/
Kojto	93:e188a91d3eaa	183	#define HAL_SPI_ERROR_NONE ((uint32_t)0x00000000) /!< No error /
Kojto	93:e188a91d3eaa	184	#define HAL_SPI_ERROR_MODF ((uint32_t)0x00000001) /!< MODF error /
Kojto	93:e188a91d3eaa	185	#define HAL_SPI_ERROR_CRC ((uint32_t)0x00000002) /!< CRC error /
Kojto	93:e188a91d3eaa	186	#define HAL_SPI_ERROR_OVR ((uint32_t)0x00000004) /!< OVR error /
Kojto	93:e188a91d3eaa	187	#define HAL_SPI_ERROR_FRE ((uint32_t)0x00000008) /!< FRE error /
Kojto	93:e188a91d3eaa	188	#define HAL_SPI_ERROR_DMA ((uint32_t)0x00000010) /!< DMA transfer error /
Kojto	93:e188a91d3eaa	189	#define HAL_SPI_ERROR_FLAG ((uint32_t)0x00000020) /!< Error on BSY/TXE/FTLVL/FRLVL Flag /
Kojto	93:e188a91d3eaa	190	#define HAL_SPI_ERROR_UNKNOW ((uint32_t)0x00000040) /!< Unknow Error error /
Kojto	93:e188a91d3eaa	191	/**
Kojto	93:e188a91d3eaa	192	* @}
Kojto	93:e188a91d3eaa	193	*/
Kojto	93:e188a91d3eaa	194
bogdanm	92:4fc01daae5a5	195	/** @defgroup SPI_mode SPI mode
bogdanm	85:024bf7f99721	196	* @{
bogdanm	85:024bf7f99721	197	*/
bogdanm	85:024bf7f99721	198	#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	199	#define SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI)
bogdanm	85:024bf7f99721	200	#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) \|\| \
bogdanm	85:024bf7f99721	201	((MODE) == SPI_MODE_MASTER))
bogdanm	85:024bf7f99721	202	/**
bogdanm	85:024bf7f99721	203	* @}
bogdanm	85:024bf7f99721	204	*/
bogdanm	85:024bf7f99721	205
bogdanm	92:4fc01daae5a5	206	/** @defgroup SPI_Direction SPI Direction
bogdanm	85:024bf7f99721	207	* @{
bogdanm	85:024bf7f99721	208	*/
bogdanm	85:024bf7f99721	209	#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	210	#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
bogdanm	85:024bf7f99721	211	#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm	85:024bf7f99721	212
bogdanm	85:024bf7f99721	213	#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) \|\| \
bogdanm	85:024bf7f99721	214	((MODE) == SPI_DIRECTION_2LINES_RXONLY) \|\|\
bogdanm	85:024bf7f99721	215	((MODE) == SPI_DIRECTION_1LINE))
bogdanm	85:024bf7f99721	216
bogdanm	85:024bf7f99721	217	#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
bogdanm	85:024bf7f99721	218
bogdanm	85:024bf7f99721	219	#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)\|\| \
bogdanm	85:024bf7f99721	220	((MODE) == SPI_DIRECTION_1LINE))
bogdanm	85:024bf7f99721	221	/**
bogdanm	85:024bf7f99721	222	* @}
bogdanm	85:024bf7f99721	223	*/
bogdanm	85:024bf7f99721	224
Kojto	93:e188a91d3eaa	225	/** @defgroup SPI_data_size SPI Data size
bogdanm	85:024bf7f99721	226	* @{
bogdanm	85:024bf7f99721	227	*/
Kojto	93:e188a91d3eaa	228	#define SPI_DATASIZE_4BIT ((uint32_t)0x0300) /!< SPI Datasize = 4bits /
Kojto	93:e188a91d3eaa	229	#define SPI_DATASIZE_5BIT ((uint32_t)0x0400) /!< SPI Datasize = 5bits /
Kojto	93:e188a91d3eaa	230	#define SPI_DATASIZE_6BIT ((uint32_t)0x0500) /!< SPI Datasize = 6bits /
Kojto	93:e188a91d3eaa	231	#define SPI_DATASIZE_7BIT ((uint32_t)0x0600) /!< SPI Datasize = 7bits /
Kojto	93:e188a91d3eaa	232	#define SPI_DATASIZE_8BIT ((uint32_t)0x0700) /!< SPI Datasize = 8bits /
Kojto	93:e188a91d3eaa	233	#define SPI_DATASIZE_9BIT ((uint32_t)0x0800) /!< SPI Datasize = 9bits /
Kojto	93:e188a91d3eaa	234	#define SPI_DATASIZE_10BIT ((uint32_t)0x0900) /!< SPI Datasize = 10bits /
Kojto	93:e188a91d3eaa	235	#define SPI_DATASIZE_11BIT ((uint32_t)0x0A00) /!< SPI Datasize = 11bits /
Kojto	93:e188a91d3eaa	236	#define SPI_DATASIZE_12BIT ((uint32_t)0x0B00) /!< SPI Datasize = 12bits /
Kojto	93:e188a91d3eaa	237	#define SPI_DATASIZE_13BIT ((uint32_t)0x0C00) /!< SPI Datasize = 13bits /
Kojto	93:e188a91d3eaa	238	#define SPI_DATASIZE_14BIT ((uint32_t)0x0D00) /!< SPI Datasize = 14bits /
Kojto	93:e188a91d3eaa	239	#define SPI_DATASIZE_15BIT ((uint32_t)0x0E00) /!< SPI Datasize = 15bits /
Kojto	93:e188a91d3eaa	240	#define SPI_DATASIZE_16BIT ((uint32_t)0x0F00) /!< SPI Datasize = 16bits /
bogdanm	85:024bf7f99721	241	#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) \|\| \
bogdanm	85:024bf7f99721	242	((DATASIZE) == SPI_DATASIZE_15BIT) \|\| \
bogdanm	85:024bf7f99721	243	((DATASIZE) == SPI_DATASIZE_14BIT) \|\| \
bogdanm	85:024bf7f99721	244	((DATASIZE) == SPI_DATASIZE_13BIT) \|\| \
bogdanm	85:024bf7f99721	245	((DATASIZE) == SPI_DATASIZE_12BIT) \|\| \
bogdanm	85:024bf7f99721	246	((DATASIZE) == SPI_DATASIZE_11BIT) \|\| \
bogdanm	85:024bf7f99721	247	((DATASIZE) == SPI_DATASIZE_10BIT) \|\| \
bogdanm	85:024bf7f99721	248	((DATASIZE) == SPI_DATASIZE_9BIT) \|\| \
bogdanm	85:024bf7f99721	249	((DATASIZE) == SPI_DATASIZE_8BIT) \|\| \
bogdanm	85:024bf7f99721	250	((DATASIZE) == SPI_DATASIZE_7BIT) \|\| \
bogdanm	85:024bf7f99721	251	((DATASIZE) == SPI_DATASIZE_6BIT) \|\| \
bogdanm	85:024bf7f99721	252	((DATASIZE) == SPI_DATASIZE_5BIT) \|\| \
bogdanm	85:024bf7f99721	253	((DATASIZE) == SPI_DATASIZE_4BIT))
bogdanm	85:024bf7f99721	254
bogdanm	85:024bf7f99721	255	/**
bogdanm	85:024bf7f99721	256	* @}
bogdanm	85:024bf7f99721	257	*/
bogdanm	85:024bf7f99721	258
bogdanm	92:4fc01daae5a5	259	/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
bogdanm	85:024bf7f99721	260	* @{
bogdanm	85:024bf7f99721	261	*/
Kojto	93:e188a91d3eaa	262	#define SPI_POLARITY_LOW ((uint32_t)0x00000000) /!< SPI polarity Low /
Kojto	93:e188a91d3eaa	263	#define SPI_POLARITY_HIGH SPI_CR1_CPOL /!< SPI polarity High /
bogdanm	85:024bf7f99721	264	#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) \|\| \
bogdanm	85:024bf7f99721	265	((CPOL) == SPI_POLARITY_HIGH))
bogdanm	85:024bf7f99721	266	/**
bogdanm	85:024bf7f99721	267	* @}
bogdanm	85:024bf7f99721	268	*/
bogdanm	85:024bf7f99721	269
bogdanm	92:4fc01daae5a5	270	/** @defgroup SPI_Clock_Phase SPI Clock Phase
bogdanm	85:024bf7f99721	271	* @{
bogdanm	85:024bf7f99721	272	*/
Kojto	93:e188a91d3eaa	273	#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) /!< SPI Phase 1EDGE /
Kojto	93:e188a91d3eaa	274	#define SPI_PHASE_2EDGE SPI_CR1_CPHA /!< SPI Phase 2EDGE /
bogdanm	85:024bf7f99721	275	#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) \|\| \
bogdanm	85:024bf7f99721	276	((CPHA) == SPI_PHASE_2EDGE))
bogdanm	85:024bf7f99721	277	/**
bogdanm	85:024bf7f99721	278	* @}
bogdanm	85:024bf7f99721	279	*/
bogdanm	85:024bf7f99721	280
bogdanm	92:4fc01daae5a5	281	/** @defgroup SPI_Slave_Select_management SPI Slave Select management
bogdanm	85:024bf7f99721	282	* @{
bogdanm	85:024bf7f99721	283	*/
bogdanm	85:024bf7f99721	284	#define SPI_NSS_SOFT SPI_CR1_SSM
bogdanm	85:024bf7f99721	285	#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	286	#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	287	#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) \|\| \
bogdanm	85:024bf7f99721	288	((NSS) == SPI_NSS_HARD_INPUT) \|\| \
bogdanm	85:024bf7f99721	289	((NSS) == SPI_NSS_HARD_OUTPUT))
bogdanm	92:4fc01daae5a5	290	/**
bogdanm	85:024bf7f99721	291	* @}
bogdanm	85:024bf7f99721	292	*/
bogdanm	85:024bf7f99721	293
Kojto	93:e188a91d3eaa	294	/** @defgroup SPI_NSSP_Mode SPI NSS pulse management
bogdanm	85:024bf7f99721	295	* @{
bogdanm	85:024bf7f99721	296	*/
bogdanm	85:024bf7f99721	297	#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
bogdanm	85:024bf7f99721	298	#define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	299
bogdanm	85:024bf7f99721	300	#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) \|\| \
bogdanm	85:024bf7f99721	301	((NSSP) == SPI_NSS_PULSE_DISABLED))
bogdanm	85:024bf7f99721	302	/**
bogdanm	85:024bf7f99721	303	* @}
bogdanm	85:024bf7f99721	304	*/
bogdanm	85:024bf7f99721	305
bogdanm	92:4fc01daae5a5	306	/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
bogdanm	85:024bf7f99721	307	* @{
bogdanm	85:024bf7f99721	308	*/
bogdanm	85:024bf7f99721	309	#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	310	#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	311	#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	312	#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
bogdanm	85:024bf7f99721	313	#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	314	#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
bogdanm	85:024bf7f99721	315	#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
bogdanm	85:024bf7f99721	316	#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
bogdanm	85:024bf7f99721	317	#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) \|\| \
bogdanm	85:024bf7f99721	318	((PRESCALER) == SPI_BAUDRATEPRESCALER_4) \|\| \
bogdanm	85:024bf7f99721	319	((PRESCALER) == SPI_BAUDRATEPRESCALER_8) \|\| \
bogdanm	85:024bf7f99721	320	((PRESCALER) == SPI_BAUDRATEPRESCALER_16) \|\| \
bogdanm	85:024bf7f99721	321	((PRESCALER) == SPI_BAUDRATEPRESCALER_32) \|\| \
bogdanm	85:024bf7f99721	322	((PRESCALER) == SPI_BAUDRATEPRESCALER_64) \|\| \
bogdanm	85:024bf7f99721	323	((PRESCALER) == SPI_BAUDRATEPRESCALER_128) \|\| \
bogdanm	85:024bf7f99721	324	((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
bogdanm	85:024bf7f99721	325	/**
bogdanm	85:024bf7f99721	326	* @}
bogdanm	85:024bf7f99721	327	*/
bogdanm	85:024bf7f99721	328
bogdanm	92:4fc01daae5a5	329	/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
bogdanm	85:024bf7f99721	330	* @{
bogdanm	85:024bf7f99721	331	*/
bogdanm	85:024bf7f99721	332	#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	333	#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm	85:024bf7f99721	334	#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) \|\| \
bogdanm	85:024bf7f99721	335	((BIT) == SPI_FIRSTBIT_LSB))
bogdanm	85:024bf7f99721	336	/**
bogdanm	85:024bf7f99721	337	* @}
bogdanm	85:024bf7f99721	338	*/
bogdanm	85:024bf7f99721	339
bogdanm	92:4fc01daae5a5	340	/** @defgroup SPI_TI_mode SPI TI mode
bogdanm	85:024bf7f99721	341	* @{
bogdanm	85:024bf7f99721	342	*/
bogdanm	85:024bf7f99721	343	#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	344	#define SPI_TIMODE_ENABLED SPI_CR2_FRF
bogdanm	85:024bf7f99721	345	#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) \|\| \
bogdanm	85:024bf7f99721	346	((MODE) == SPI_TIMODE_ENABLED))
bogdanm	85:024bf7f99721	347	/**
bogdanm	85:024bf7f99721	348	* @}
bogdanm	85:024bf7f99721	349	*/
bogdanm	85:024bf7f99721	350
bogdanm	92:4fc01daae5a5	351	/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
bogdanm	85:024bf7f99721	352	* @{
bogdanm	85:024bf7f99721	353	*/
bogdanm	85:024bf7f99721	354	#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	355	#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
bogdanm	85:024bf7f99721	356	#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) \|\| \
bogdanm	85:024bf7f99721	357	((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
bogdanm	85:024bf7f99721	358	/**
bogdanm	85:024bf7f99721	359	* @}
bogdanm	85:024bf7f99721	360	*/
bogdanm	85:024bf7f99721	361
bogdanm	92:4fc01daae5a5	362	/** @defgroup SPI_CRC_length SPI CRC length
bogdanm	85:024bf7f99721	363	* @{
bogdanm	85:024bf7f99721	364	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	365	* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
bogdanm	85:024bf7f99721	366	* SPI_CRC_LENGTH_8BIT : CRC 8bit
bogdanm	85:024bf7f99721	367	* SPI_CRC_LENGTH_16BIT : CRC 16bit
bogdanm	85:024bf7f99721	368	*/
bogdanm	85:024bf7f99721	369	#define SPI_CRC_LENGTH_DATASIZE 0
bogdanm	85:024bf7f99721	370	#define SPI_CRC_LENGTH_8BIT 1
bogdanm	85:024bf7f99721	371	#define SPI_CRC_LENGTH_16BIT 2
bogdanm	85:024bf7f99721	372	#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) \|\|\
bogdanm	85:024bf7f99721	373	((LENGTH) == SPI_CRC_LENGTH_8BIT) \|\| \
bogdanm	85:024bf7f99721	374	((LENGTH) == SPI_CRC_LENGTH_16BIT))
bogdanm	85:024bf7f99721	375	/**
bogdanm	85:024bf7f99721	376	* @}
bogdanm	85:024bf7f99721	377	*/
bogdanm	85:024bf7f99721	378
bogdanm	92:4fc01daae5a5	379	/** @defgroup SPI_FIFO_reception_threshold SPI FIFO reception threshold
bogdanm	85:024bf7f99721	380	* @{
bogdanm	85:024bf7f99721	381	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	382	* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
Kojto	93:e188a91d3eaa	383	* RXNE event is generated if the FIFO
bogdanm	85:024bf7f99721	384	* level is greater or equal to 1/2(16-bits).
Kojto	93:e188a91d3eaa	385	* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
Kojto	93:e188a91d3eaa	386	* level is greater or equal to 1/4(8 bits). */
bogdanm	85:024bf7f99721	387	#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
bogdanm	85:024bf7f99721	388	#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
bogdanm	85:024bf7f99721	389	#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
bogdanm	85:024bf7f99721	390
bogdanm	85:024bf7f99721	391	/**
bogdanm	85:024bf7f99721	392	* @}
bogdanm	85:024bf7f99721	393	*/
bogdanm	85:024bf7f99721	394
bogdanm	92:4fc01daae5a5	395	/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
bogdanm	85:024bf7f99721	396	* @brief SPI Interrupt definition
bogdanm	85:024bf7f99721	397	* Elements values convention: 0xXXXXXXXX
bogdanm	85:024bf7f99721	398	* - XXXXXXXX : Interrupt control mask
Kojto	93:e188a91d3eaa	399	* @{
Kojto	93:e188a91d3eaa	400	*/
bogdanm	85:024bf7f99721	401	#define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm	85:024bf7f99721	402	#define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm	85:024bf7f99721	403	#define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm	85:024bf7f99721	404	/**
bogdanm	85:024bf7f99721	405	* @}
bogdanm	85:024bf7f99721	406	*/
bogdanm	85:024bf7f99721	407
bogdanm	85:024bf7f99721	408
bogdanm	92:4fc01daae5a5	409	/** @defgroup SPI_Flag_definition SPI Flag definition
bogdanm	85:024bf7f99721	410	* @brief Flag definition
bogdanm	85:024bf7f99721	411	* Elements values convention: 0xXXXXYYYY
bogdanm	85:024bf7f99721	412	* - XXXX : Flag register Index
bogdanm	85:024bf7f99721	413	* - YYYY : Flag mask
bogdanm	92:4fc01daae5a5	414	* @{
bogdanm	85:024bf7f99721	415	*/
bogdanm	92:4fc01daae5a5	416	#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
bogdanm	92:4fc01daae5a5	417	#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
bogdanm	92:4fc01daae5a5	418	#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
bogdanm	92:4fc01daae5a5	419	#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
bogdanm	92:4fc01daae5a5	420	#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
bogdanm	92:4fc01daae5a5	421	#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
bogdanm	92:4fc01daae5a5	422	#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
bogdanm	92:4fc01daae5a5	423	#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
bogdanm	92:4fc01daae5a5	424	#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
bogdanm	92:4fc01daae5a5	425	/**
bogdanm	92:4fc01daae5a5	426	* @}
bogdanm	92:4fc01daae5a5	427	*/
bogdanm	85:024bf7f99721	428
bogdanm	92:4fc01daae5a5	429	/** @defgroup SPI_transmission_fifo_status_level SPI transmission fifo status level
bogdanm	85:024bf7f99721	430	* @{
bogdanm	85:024bf7f99721	431	*/
Kojto	93:e188a91d3eaa	432	#define SPI_FTLVL_EMPTY ((uint32_t)0x0000)
Kojto	93:e188a91d3eaa	433	#define SPI_FTLVL_QUARTER_FULL ((uint32_t)0x0800)
Kojto	93:e188a91d3eaa	434	#define SPI_FTLVL_HALF_FULL ((uint32_t)0x1000)
Kojto	93:e188a91d3eaa	435	#define SPI_FTLVL_FULL ((uint32_t)0x1800)
bogdanm	85:024bf7f99721	436
bogdanm	85:024bf7f99721	437	/**
bogdanm	85:024bf7f99721	438	* @}
bogdanm	85:024bf7f99721	439	*/
bogdanm	85:024bf7f99721	440
bogdanm	92:4fc01daae5a5	441	/** @defgroup SPI_reception_fifo_status_level SPI reception fifo status level
bogdanm	85:024bf7f99721	442	* @{
bogdanm	85:024bf7f99721	443	*/
Kojto	93:e188a91d3eaa	444	#define SPI_FRLVL_EMPTY ((uint32_t)0x0000)
Kojto	93:e188a91d3eaa	445	#define SPI_FRLVL_QUARTER_FULL ((uint32_t)0x0200)
Kojto	93:e188a91d3eaa	446	#define SPI_FRLVL_HALF_FULL ((uint32_t)0x0400)
Kojto	93:e188a91d3eaa	447	#define SPI_FRLVL_FULL ((uint32_t)0x0600)
bogdanm	85:024bf7f99721	448	/**
bogdanm	85:024bf7f99721	449	* @}
bogdanm	85:024bf7f99721	450	*/
bogdanm	85:024bf7f99721	451
bogdanm	85:024bf7f99721	452	/**
bogdanm	85:024bf7f99721	453	* @}
bogdanm	85:024bf7f99721	454	*/
bogdanm	85:024bf7f99721	455
bogdanm	85:024bf7f99721	456
bogdanm	85:024bf7f99721	457	/* Exported macros ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	458	/** @defgroup SPI_Exported_Macros SPI Exported Macros
bogdanm	92:4fc01daae5a5	459	* @{
bogdanm	92:4fc01daae5a5	460	*/
bogdanm	92:4fc01daae5a5	461
bogdanm	85:024bf7f99721	462	/** @brief Reset SPI handle state
bogdanm	85:024bf7f99721	463	* @param __HANDLE__: SPI handle.
bogdanm	85:024bf7f99721	464	* @retval None
bogdanm	85:024bf7f99721	465	*/
bogdanm	85:024bf7f99721	466	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm	85:024bf7f99721	467
bogdanm	85:024bf7f99721	468	/** @brief Enables or disables the specified SPI interrupts.
Kojto	93:e188a91d3eaa	469	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	470	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	93:e188a91d3eaa	471	* @param __INTERRUPT__ : specifies the interrupt source to enable or disable.
bogdanm	85:024bf7f99721	472	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	473	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm	85:024bf7f99721	474	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm	85:024bf7f99721	475	* @arg SPI_IT_ERR: Error interrupt enable
bogdanm	85:024bf7f99721	476	* @retval None
bogdanm	85:024bf7f99721	477	*/
bogdanm	85:024bf7f99721	478	#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 \|= (__INTERRUPT__))
Kojto	93:e188a91d3eaa	479	#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
bogdanm	85:024bf7f99721	480
bogdanm	85:024bf7f99721	481	/** @brief Checks if the specified SPI interrupt source is enabled or disabled.
Kojto	93:e188a91d3eaa	482	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	483	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	93:e188a91d3eaa	484	* @param __INTERRUPT__ : specifies the SPI interrupt source to check.
bogdanm	85:024bf7f99721	485	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	486	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm	85:024bf7f99721	487	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm	85:024bf7f99721	488	* @arg SPI_IT_ERR: Error interrupt enable
bogdanm	85:024bf7f99721	489	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	490	*/
bogdanm	85:024bf7f99721	491	#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	85:024bf7f99721	492
bogdanm	85:024bf7f99721	493	/** @brief Checks whether the specified SPI flag is set or not.
Kojto	93:e188a91d3eaa	494	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	495	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
Kojto	93:e188a91d3eaa	496	* @param __FLAG__ : specifies the flag to check.
bogdanm	85:024bf7f99721	497	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	498	* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm	85:024bf7f99721	499	* @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm	85:024bf7f99721	500	* @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm	85:024bf7f99721	501	* @arg SPI_FLAG_MODF: Mode fault flag
bogdanm	85:024bf7f99721	502	* @arg SPI_FLAG_OVR: Overrun flag
bogdanm	85:024bf7f99721	503	* @arg SPI_FLAG_BSY: Busy flag
bogdanm	85:024bf7f99721	504	* @arg SPI_FLAG_FRE: Frame format error flag
Kojto	93:e188a91d3eaa	505	* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
Kojto	93:e188a91d3eaa	506	* @arg SPI_FLAG_FRLVL: SPI fifo reception level
bogdanm	85:024bf7f99721	507	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	508	*/
bogdanm	85:024bf7f99721	509	#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm	85:024bf7f99721	510
bogdanm	85:024bf7f99721	511	/** @brief Clears the SPI CRCERR pending flag.
Kojto	93:e188a91d3eaa	512	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	513	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	514	* @retval None
bogdanm	85:024bf7f99721	515	*/
bogdanm	92:4fc01daae5a5	516	#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
bogdanm	85:024bf7f99721	517
bogdanm	85:024bf7f99721	518	/** @brief Clears the SPI MODF pending flag.
Kojto	93:e188a91d3eaa	519	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	520	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	521	*
bogdanm	85:024bf7f99721	522	* @retval None
bogdanm	85:024bf7f99721	523	*/
Kojto	93:e188a91d3eaa	524	#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{\
Kojto	93:e188a91d3eaa	525	__IO uint32_t tmpreg;\
Kojto	93:e188a91d3eaa	526	tmpreg = (__HANDLE__)->Instance->SR;\
Kojto	93:e188a91d3eaa	527	UNUSED(tmpreg); \
Kojto	93:e188a91d3eaa	528	(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);\
Kojto	93:e188a91d3eaa	529	}while(0)
bogdanm	85:024bf7f99721	530
bogdanm	85:024bf7f99721	531	/** @brief Clears the SPI OVR pending flag.
Kojto	93:e188a91d3eaa	532	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	533	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	534	*
bogdanm	85:024bf7f99721	535	* @retval None
bogdanm	85:024bf7f99721	536	*/
Kojto	93:e188a91d3eaa	537	#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{ \
Kojto	93:e188a91d3eaa	538	__IO uint32_t tmpreg; \
Kojto	93:e188a91d3eaa	539	tmpreg = (__HANDLE__)->Instance->DR; \
Kojto	93:e188a91d3eaa	540	tmpreg = (__HANDLE__)->Instance->SR; \
Kojto	93:e188a91d3eaa	541	UNUSED(tmpreg); \
Kojto	93:e188a91d3eaa	542	} while(0)
Kojto	93:e188a91d3eaa	543
bogdanm	85:024bf7f99721	544	/** @brief Clears the SPI FRE pending flag.
Kojto	93:e188a91d3eaa	545	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	546	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	547	*
bogdanm	85:024bf7f99721	548	* @retval None
bogdanm	85:024bf7f99721	549	*/
Kojto	93:e188a91d3eaa	550	#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) do{\
Kojto	93:e188a91d3eaa	551	__IO uint32_t tmpreg;\
Kojto	93:e188a91d3eaa	552	tmpreg = ((__HANDLE__)->Instance->SR);\
Kojto	93:e188a91d3eaa	553	UNUSED(tmpreg); \
Kojto	93:e188a91d3eaa	554	}while(0)
bogdanm	85:024bf7f99721	555	/** @brief Enables the SPI.
Kojto	93:e188a91d3eaa	556	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	557	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	558	* @retval None
bogdanm	85:024bf7f99721	559	*/
bogdanm	85:024bf7f99721	560	#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= SPI_CR1_SPE)
bogdanm	85:024bf7f99721	561
bogdanm	85:024bf7f99721	562	/** @brief Disables the SPI.
Kojto	93:e188a91d3eaa	563	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	564	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	565	* @retval None
bogdanm	85:024bf7f99721	566	*/
Kojto	93:e188a91d3eaa	567	#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
bogdanm	85:024bf7f99721	568
bogdanm	85:024bf7f99721	569	/** @brief Sets the SPI transmit-only mode.
Kojto	93:e188a91d3eaa	570	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	571	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	572	* @retval None
bogdanm	85:024bf7f99721	573	*/
bogdanm	85:024bf7f99721	574	#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= SPI_CR1_BIDIOE)
bogdanm	85:024bf7f99721	575
bogdanm	85:024bf7f99721	576	/** @brief Sets the SPI receive-only mode.
Kojto	93:e188a91d3eaa	577	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	578	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	579	* @retval None
bogdanm	85:024bf7f99721	580	*/
Kojto	93:e188a91d3eaa	581	#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
bogdanm	85:024bf7f99721	582
bogdanm	85:024bf7f99721	583	/** @brief Resets the CRC calculation of the SPI.
Kojto	93:e188a91d3eaa	584	* @param __HANDLE__ : specifies the SPI Handle.
bogdanm	85:024bf7f99721	585	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	586	* @retval None
bogdanm	85:024bf7f99721	587	*/
bogdanm	85:024bf7f99721	588	#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
bogdanm	85:024bf7f99721	589	(__HANDLE__)->Instance->CR1 \|= SPI_CR1_CRCEN;}while(0)
bogdanm	85:024bf7f99721	590
bogdanm	85:024bf7f99721	591
bogdanm	85:024bf7f99721	592	#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
bogdanm	92:4fc01daae5a5	593	/**
bogdanm	92:4fc01daae5a5	594	* @}
bogdanm	92:4fc01daae5a5	595	*/
bogdanm	92:4fc01daae5a5	596
bogdanm	85:024bf7f99721	597	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	598	/** @addtogroup SPI_Exported_Functions
bogdanm	92:4fc01daae5a5	599	* @{
bogdanm	92:4fc01daae5a5	600	*/
bogdanm	85:024bf7f99721	601
bogdanm	92:4fc01daae5a5	602	/** @addtogroup SPI_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	603	* @{
bogdanm	92:4fc01daae5a5	604	*/
bogdanm	92:4fc01daae5a5	605
bogdanm	85:024bf7f99721	606	/* Initialization and de-initialization functions ****************************/
bogdanm	85:024bf7f99721	607	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	608	HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	609	HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	610	void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	611	void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
bogdanm	92:4fc01daae5a5	612	/**
bogdanm	92:4fc01daae5a5	613	* @}
bogdanm	92:4fc01daae5a5	614	*/
bogdanm	85:024bf7f99721	615
bogdanm	92:4fc01daae5a5	616	/** @addtogroup SPI_Exported_Functions_Group2
bogdanm	92:4fc01daae5a5	617	* @{
bogdanm	92:4fc01daae5a5	618	*/
bogdanm	92:4fc01daae5a5	619
bogdanm	85:024bf7f99721	620	/* IO operation functions *****************************************************/
bogdanm	85:024bf7f99721	621	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
bogdanm	85:024bf7f99721	622	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
bogdanm	85:024bf7f99721	623	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
bogdanm	85:024bf7f99721	624	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	625	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	626	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm	85:024bf7f99721	627	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	628	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	629	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
Kojto	93:e188a91d3eaa	630	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	631	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	632	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	633	HAL_StatusTypeDef HAL_SPI_FlushRxFifo(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	634
bogdanm	85:024bf7f99721	635	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	636	void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	637	void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	638	void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	639	void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	640	void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	641	void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	642	void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
bogdanm	92:4fc01daae5a5	643	/**
bogdanm	92:4fc01daae5a5	644	* @}
bogdanm	92:4fc01daae5a5	645	*/
bogdanm	85:024bf7f99721	646
bogdanm	92:4fc01daae5a5	647	/** @addtogroup SPI_Exported_Functions_Group3
bogdanm	92:4fc01daae5a5	648	* @{
bogdanm	92:4fc01daae5a5	649	*/
bogdanm	92:4fc01daae5a5	650
bogdanm	85:024bf7f99721	651	/* Peripheral State and Error functions ***************************************/
bogdanm	85:024bf7f99721	652	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
Kojto	93:e188a91d3eaa	653	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
bogdanm	92:4fc01daae5a5	654	/**
bogdanm	92:4fc01daae5a5	655	* @}
bogdanm	92:4fc01daae5a5	656	*/
bogdanm	85:024bf7f99721	657
bogdanm	85:024bf7f99721	658	/**
bogdanm	85:024bf7f99721	659	* @}
bogdanm	92:4fc01daae5a5	660	*/
bogdanm	92:4fc01daae5a5	661
bogdanm	92:4fc01daae5a5	662	/**
bogdanm	92:4fc01daae5a5	663	* @}
bogdanm	85:024bf7f99721	664	*/
bogdanm	85:024bf7f99721	665
bogdanm	85:024bf7f99721	666	/**
bogdanm	85:024bf7f99721	667	* @}
bogdanm	85:024bf7f99721	668	*/
bogdanm	85:024bf7f99721	669
bogdanm	85:024bf7f99721	670	#ifdef __cplusplus
bogdanm	85:024bf7f99721	671	}
bogdanm	85:024bf7f99721	672	#endif
bogdanm	85:024bf7f99721	673
bogdanm	85:024bf7f99721	674	#endif /* __STM32F0xx_HAL_SPI_H */
bogdanm	85:024bf7f99721	675
bogdanm	85:024bf7f99721	676	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	92:4fc01daae5a5	677

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
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TARGET_NUCLEO_F072RB/stm32f0xx_hal_spi.h@93:e188a91d3eaa, 2015-02-03 (annotated)

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