mbed - my fork

Users » filartrix » Code » mbed

my fork

TARGET_NUCLEO_F072RB/stm32f0xx_hal_spi.h@85:024bf7f99721, 2014-06-11 (annotated)

Committer:: bogdanm
Date:: Wed Jun 11 15:14:05 2014 +0100
Revision:: 85:024bf7f99721
Child:: 92:4fc01daae5a5

Release 85 of the mbed library



Main changes:



- K64F Ethernet fixes

- Updated tests

- Fixes for various mbed targets

- Code cleanup: fixed warnings, more consistent code style

- GCC support for K64F



There is a known issue with the I2C interface on some ST targets. If you

find the I2C interface problematic on your ST board, please log a bug

against this on mbed.org.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_spi.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
bogdanm	85:024bf7f99721	5	* @version V1.0.0
bogdanm	85:024bf7f99721	6	* @date 28-May-2014
bogdanm	85:024bf7f99721	7	* @brief Header file of SPI HAL module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
bogdanm	85:024bf7f99721	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_SPI_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_SPI_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup SPI
bogdanm	85:024bf7f99721	54	* @{
bogdanm	85:024bf7f99721	55	*/
bogdanm	85:024bf7f99721	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	58
bogdanm	85:024bf7f99721	59	/**
bogdanm	85:024bf7f99721	60	* @brief SPI Configuration Structure definition
bogdanm	85:024bf7f99721	61	*/
bogdanm	85:024bf7f99721	62	typedef struct
bogdanm	85:024bf7f99721	63	{
bogdanm	85:024bf7f99721	64	uint32_t Mode; /*!< Specifies the SPI operating mode.
bogdanm	85:024bf7f99721	65	This parameter can be a value of @ref SPI_mode */
bogdanm	85:024bf7f99721	66
bogdanm	85:024bf7f99721	67	uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
bogdanm	85:024bf7f99721	68	This parameter can be a value of @ref SPI_Direction */
bogdanm	85:024bf7f99721	69
bogdanm	85:024bf7f99721	70	uint32_t DataSize; /*!< Specifies the SPI data size.
bogdanm	85:024bf7f99721	71	This parameter can be a value of @ref SPI_data_size */
bogdanm	85:024bf7f99721	72
bogdanm	85:024bf7f99721	73	uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm	85:024bf7f99721	74	This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm	85:024bf7f99721	75
bogdanm	85:024bf7f99721	76	uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm	85:024bf7f99721	77	This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm	85:024bf7f99721	78
bogdanm	85:024bf7f99721	79	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm	85:024bf7f99721	80	hardware (NSS pin) or by software using the SSI bit.
bogdanm	85:024bf7f99721	81	This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm	85:024bf7f99721	82
bogdanm	85:024bf7f99721	83	uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm	85:024bf7f99721	84	used to configure the transmit and receive SCK clock.
bogdanm	85:024bf7f99721	85	This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm	85:024bf7f99721	86	@note The communication clock is derived from the master
bogdanm	85:024bf7f99721	87	clock. The slave clock does not need to be set. */
bogdanm	85:024bf7f99721	88
bogdanm	85:024bf7f99721	89	uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm	85:024bf7f99721	90	This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm	85:024bf7f99721	91
bogdanm	85:024bf7f99721	92	uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not .
bogdanm	85:024bf7f99721	93	This parameter can be a value of @ref SPI_TI_mode */
bogdanm	85:024bf7f99721	94
bogdanm	85:024bf7f99721	95	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm	85:024bf7f99721	96	This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm	85:024bf7f99721	97
bogdanm	85:024bf7f99721	98	uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
bogdanm	85:024bf7f99721	99	This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
bogdanm	85:024bf7f99721	100
bogdanm	85:024bf7f99721	101	uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
bogdanm	85:024bf7f99721	102	CRC Length is only used with Data8 and Data16, not other data size
bogdanm	85:024bf7f99721	103	This parameter must 0 or 1 or 2*/
bogdanm	85:024bf7f99721	104
bogdanm	85:024bf7f99721	105	uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
bogdanm	85:024bf7f99721	106	This mode is activated by the NSSP bit in the SPIx_CR2 register and
bogdanm	85:024bf7f99721	107	it takes effect only if the SPI interface is configured as Motorola SPI
bogdanm	85:024bf7f99721	108	master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
bogdanm	85:024bf7f99721	109	CPOL setting is ignored).. */
bogdanm	85:024bf7f99721	110	} SPI_InitTypeDef;
bogdanm	85:024bf7f99721	111
bogdanm	85:024bf7f99721	112	/**
bogdanm	85:024bf7f99721	113	* @brief HAL State structures definition
bogdanm	85:024bf7f99721	114	*/
bogdanm	85:024bf7f99721	115	typedef enum
bogdanm	85:024bf7f99721	116	{
bogdanm	85:024bf7f99721	117	HAL_SPI_STATE_RESET = 0x00, /!< Peripheral not Initialized /
bogdanm	85:024bf7f99721	118	HAL_SPI_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	85:024bf7f99721	119	HAL_SPI_STATE_BUSY = 0x02, /!< an internal process is ongoing /
bogdanm	85:024bf7f99721	120	HAL_SPI_STATE_BUSY_TX = 0x03, /!< Data Transmission process is ongoing /
bogdanm	85:024bf7f99721	121	HAL_SPI_STATE_BUSY_RX = 0x04, /!< Data Reception process is ongoing /
bogdanm	85:024bf7f99721	122	HAL_SPI_STATE_BUSY_TX_RX = 0x05, /!< Data Transmission and Reception process is ongoing /
bogdanm	85:024bf7f99721	123	HAL_SPI_STATE_TIMEOUT = 0x06, /!< Timeout state /
bogdanm	85:024bf7f99721	124	HAL_SPI_STATE_ERROR = 0x07 /!< Data Transmission and Reception process is ongoing /
bogdanm	85:024bf7f99721	125
bogdanm	85:024bf7f99721	126	}HAL_SPI_StateTypeDef;
bogdanm	85:024bf7f99721	127
bogdanm	85:024bf7f99721	128	/**
bogdanm	85:024bf7f99721	129	* @brief HAL SPI Error Code structure definition
bogdanm	85:024bf7f99721	130	*/
bogdanm	85:024bf7f99721	131	typedef enum
bogdanm	85:024bf7f99721	132	{
bogdanm	85:024bf7f99721	133	HAL_SPI_ERROR_NONE = 0x00, /!< No error /
bogdanm	85:024bf7f99721	134	HAL_SPI_ERROR_MODF = 0x01, /!< MODF error /
bogdanm	85:024bf7f99721	135	HAL_SPI_ERROR_CRC = 0x02, /!< CRC error /
bogdanm	85:024bf7f99721	136	HAL_SPI_ERROR_OVR = 0x04, /!< OVR error /
bogdanm	85:024bf7f99721	137	HAL_SPI_ERROR_FRE = 0x08, /!< FRE error /
bogdanm	85:024bf7f99721	138	HAL_SPI_ERROR_DMA = 0x10, /!< DMA transfer error /
bogdanm	85:024bf7f99721	139	HAL_SPI_ERROR_FLAG = 0x20, /!< Error on BSY/TXE/FTLVL/FRLVL Flag /
bogdanm	85:024bf7f99721	140	HAL_SPI_ERROR_UNKNOW = 0x40, /!< Unknow Error error /
bogdanm	85:024bf7f99721	141	}HAL_SPI_ErrorTypeDef;
bogdanm	85:024bf7f99721	142
bogdanm	85:024bf7f99721	143	/**
bogdanm	85:024bf7f99721	144	* @brief SPI handle Structure definition
bogdanm	85:024bf7f99721	145	*/
bogdanm	85:024bf7f99721	146	typedef struct __SPI_HandleTypeDef
bogdanm	85:024bf7f99721	147	{
bogdanm	85:024bf7f99721	148	SPI_TypeDef Instance; / SPI registers base address */
bogdanm	85:024bf7f99721	149
bogdanm	85:024bf7f99721	150	SPI_InitTypeDef Init; /* SPI communication parameters */
bogdanm	85:024bf7f99721	151
bogdanm	85:024bf7f99721	152	uint8_t pTxBuffPtr; / Pointer to SPI Tx transfer Buffer */
bogdanm	85:024bf7f99721	153
bogdanm	85:024bf7f99721	154	uint16_t TxXferSize; /* SPI Tx Transfer size */
bogdanm	85:024bf7f99721	155
bogdanm	85:024bf7f99721	156	uint16_t TxXferCount; /* SPI Tx Transfer Counter */
bogdanm	85:024bf7f99721	157
bogdanm	85:024bf7f99721	158	uint8_t pRxBuffPtr; / Pointer to SPI Rx transfer Buffer */
bogdanm	85:024bf7f99721	159
bogdanm	85:024bf7f99721	160	uint16_t RxXferSize; /* SPI Rx Transfer size */
bogdanm	85:024bf7f99721	161
bogdanm	85:024bf7f99721	162	uint16_t RxXferCount; /* SPI Rx Transfer Counter */
bogdanm	85:024bf7f99721	163
bogdanm	85:024bf7f99721	164	uint32_t CRCSize; /* SPI CRC size used for the transfer */
bogdanm	85:024bf7f99721	165
bogdanm	85:024bf7f99721	166	void (RxISR)(struct __SPI_HandleTypeDef hspi); /* function pointer on Rx IRQ handler */
bogdanm	85:024bf7f99721	167
bogdanm	85:024bf7f99721	168	void (TxISR)(struct __SPI_HandleTypeDef hspi); /* function pointer on Tx IRQ handler */
bogdanm	85:024bf7f99721	169
bogdanm	85:024bf7f99721	170	DMA_HandleTypeDef hdmatx; / SPI Tx DMA Handle parameters */
bogdanm	85:024bf7f99721	171
bogdanm	85:024bf7f99721	172	DMA_HandleTypeDef hdmarx; / SPI Rx DMA Handle parameters */
bogdanm	85:024bf7f99721	173
bogdanm	85:024bf7f99721	174	HAL_LockTypeDef Lock; /* Locking object */
bogdanm	85:024bf7f99721	175
bogdanm	85:024bf7f99721	176	HAL_SPI_StateTypeDef State; /* SPI communication state */
bogdanm	85:024bf7f99721	177
bogdanm	85:024bf7f99721	178	HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
bogdanm	85:024bf7f99721	179
bogdanm	85:024bf7f99721	180	}SPI_HandleTypeDef;
bogdanm	85:024bf7f99721	181
bogdanm	85:024bf7f99721	182	/* Exported constants --------------------------------------------------------*/
bogdanm	85:024bf7f99721	183
bogdanm	85:024bf7f99721	184	/** @defgroup SPI_Exported_Constants
bogdanm	85:024bf7f99721	185	* @{
bogdanm	85:024bf7f99721	186	*/
bogdanm	85:024bf7f99721	187
bogdanm	85:024bf7f99721	188	/** @defgroup SPI_mode
bogdanm	85:024bf7f99721	189	* @{
bogdanm	85:024bf7f99721	190	*/
bogdanm	85:024bf7f99721	191
bogdanm	85:024bf7f99721	192	#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	193	#define SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI)
bogdanm	85:024bf7f99721	194	#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) \|\| \
bogdanm	85:024bf7f99721	195	((MODE) == SPI_MODE_MASTER))
bogdanm	85:024bf7f99721	196	/**
bogdanm	85:024bf7f99721	197	* @}
bogdanm	85:024bf7f99721	198	*/
bogdanm	85:024bf7f99721	199
bogdanm	85:024bf7f99721	200	/** @defgroup SPI_Direction
bogdanm	85:024bf7f99721	201	* @{
bogdanm	85:024bf7f99721	202	*/
bogdanm	85:024bf7f99721	203	#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	204	#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
bogdanm	85:024bf7f99721	205	#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm	85:024bf7f99721	206
bogdanm	85:024bf7f99721	207	#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) \|\| \
bogdanm	85:024bf7f99721	208	((MODE) == SPI_DIRECTION_2LINES_RXONLY) \|\|\
bogdanm	85:024bf7f99721	209	((MODE) == SPI_DIRECTION_1LINE))
bogdanm	85:024bf7f99721	210
bogdanm	85:024bf7f99721	211	#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
bogdanm	85:024bf7f99721	212
bogdanm	85:024bf7f99721	213	#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)\|\| \
bogdanm	85:024bf7f99721	214	((MODE) == SPI_DIRECTION_1LINE))
bogdanm	85:024bf7f99721	215	/**
bogdanm	85:024bf7f99721	216	* @}
bogdanm	85:024bf7f99721	217	*/
bogdanm	85:024bf7f99721	218
bogdanm	85:024bf7f99721	219	/** @defgroup SPI_data_size
bogdanm	85:024bf7f99721	220	* @{
bogdanm	85:024bf7f99721	221	*/
bogdanm	85:024bf7f99721	222
bogdanm	85:024bf7f99721	223	#define SPI_DATASIZE_4BIT ((uint16_t)0x0300)
bogdanm	85:024bf7f99721	224	#define SPI_DATASIZE_5BIT ((uint16_t)0x0400)
bogdanm	85:024bf7f99721	225	#define SPI_DATASIZE_6BIT ((uint16_t)0x0500)
bogdanm	85:024bf7f99721	226	#define SPI_DATASIZE_7BIT ((uint16_t)0x0600)
bogdanm	85:024bf7f99721	227	#define SPI_DATASIZE_8BIT ((uint16_t)0x0700)
bogdanm	85:024bf7f99721	228	#define SPI_DATASIZE_9BIT ((uint16_t)0x0800)
bogdanm	85:024bf7f99721	229	#define SPI_DATASIZE_10BIT ((uint16_t)0x0900)
bogdanm	85:024bf7f99721	230	#define SPI_DATASIZE_11BIT ((uint16_t)0x0A00)
bogdanm	85:024bf7f99721	231	#define SPI_DATASIZE_12BIT ((uint16_t)0x0B00)
bogdanm	85:024bf7f99721	232	#define SPI_DATASIZE_13BIT ((uint16_t)0x0C00)
bogdanm	85:024bf7f99721	233	#define SPI_DATASIZE_14BIT ((uint16_t)0x0D00)
bogdanm	85:024bf7f99721	234	#define SPI_DATASIZE_15BIT ((uint16_t)0x0E00)
bogdanm	85:024bf7f99721	235	#define SPI_DATASIZE_16BIT ((uint16_t)0x0F00)
bogdanm	85:024bf7f99721	236	#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) \|\| \
bogdanm	85:024bf7f99721	237	((DATASIZE) == SPI_DATASIZE_15BIT) \|\| \
bogdanm	85:024bf7f99721	238	((DATASIZE) == SPI_DATASIZE_14BIT) \|\| \
bogdanm	85:024bf7f99721	239	((DATASIZE) == SPI_DATASIZE_13BIT) \|\| \
bogdanm	85:024bf7f99721	240	((DATASIZE) == SPI_DATASIZE_12BIT) \|\| \
bogdanm	85:024bf7f99721	241	((DATASIZE) == SPI_DATASIZE_11BIT) \|\| \
bogdanm	85:024bf7f99721	242	((DATASIZE) == SPI_DATASIZE_10BIT) \|\| \
bogdanm	85:024bf7f99721	243	((DATASIZE) == SPI_DATASIZE_9BIT) \|\| \
bogdanm	85:024bf7f99721	244	((DATASIZE) == SPI_DATASIZE_8BIT) \|\| \
bogdanm	85:024bf7f99721	245	((DATASIZE) == SPI_DATASIZE_7BIT) \|\| \
bogdanm	85:024bf7f99721	246	((DATASIZE) == SPI_DATASIZE_6BIT) \|\| \
bogdanm	85:024bf7f99721	247	((DATASIZE) == SPI_DATASIZE_5BIT) \|\| \
bogdanm	85:024bf7f99721	248	((DATASIZE) == SPI_DATASIZE_4BIT))
bogdanm	85:024bf7f99721	249
bogdanm	85:024bf7f99721	250	/**
bogdanm	85:024bf7f99721	251	* @}
bogdanm	85:024bf7f99721	252	*/
bogdanm	85:024bf7f99721	253
bogdanm	85:024bf7f99721	254	/** @defgroup SPI_Clock_Polarity
bogdanm	85:024bf7f99721	255	* @{
bogdanm	85:024bf7f99721	256	*/
bogdanm	85:024bf7f99721	257
bogdanm	85:024bf7f99721	258	#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	259	#define SPI_POLARITY_HIGH SPI_CR1_CPOL
bogdanm	85:024bf7f99721	260	#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) \|\| \
bogdanm	85:024bf7f99721	261	((CPOL) == SPI_POLARITY_HIGH))
bogdanm	85:024bf7f99721	262	/**
bogdanm	85:024bf7f99721	263	* @}
bogdanm	85:024bf7f99721	264	*/
bogdanm	85:024bf7f99721	265
bogdanm	85:024bf7f99721	266	/** @defgroup SPI_Clock_Phase
bogdanm	85:024bf7f99721	267	* @{
bogdanm	85:024bf7f99721	268	*/
bogdanm	85:024bf7f99721	269
bogdanm	85:024bf7f99721	270	#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	271	#define SPI_PHASE_2EDGE SPI_CR1_CPHA
bogdanm	85:024bf7f99721	272	#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) \|\| \
bogdanm	85:024bf7f99721	273	((CPHA) == SPI_PHASE_2EDGE))
bogdanm	85:024bf7f99721	274	/**
bogdanm	85:024bf7f99721	275	* @}
bogdanm	85:024bf7f99721	276	*/
bogdanm	85:024bf7f99721	277
bogdanm	85:024bf7f99721	278	/** @defgroup SPI_Slave_Select_management
bogdanm	85:024bf7f99721	279	* @{
bogdanm	85:024bf7f99721	280	*/
bogdanm	85:024bf7f99721	281
bogdanm	85:024bf7f99721	282	#define SPI_NSS_SOFT SPI_CR1_SSM
bogdanm	85:024bf7f99721	283	#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	284	#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	285	#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) \|\| \
bogdanm	85:024bf7f99721	286	((NSS) == SPI_NSS_HARD_INPUT) \|\| \
bogdanm	85:024bf7f99721	287	((NSS) == SPI_NSS_HARD_OUTPUT))
bogdanm	85:024bf7f99721	288
bogdanm	85:024bf7f99721	289	/**
bogdanm	85:024bf7f99721	290	* @}
bogdanm	85:024bf7f99721	291	*/
bogdanm	85:024bf7f99721	292
bogdanm	85:024bf7f99721	293
bogdanm	85:024bf7f99721	294	/** @defgroup SPI_NSS pulse management
bogdanm	85:024bf7f99721	295	* @{
bogdanm	85:024bf7f99721	296	*/
bogdanm	85:024bf7f99721	297	#define SPI_NSS_PULSE_ENABLED SPI_CR2_NSSP
bogdanm	85:024bf7f99721	298	#define SPI_NSS_PULSE_DISABLED ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	299
bogdanm	85:024bf7f99721	300	#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLED) \|\| \
bogdanm	85:024bf7f99721	301	((NSSP) == SPI_NSS_PULSE_DISABLED))
bogdanm	85:024bf7f99721	302
bogdanm	85:024bf7f99721	303	/**
bogdanm	85:024bf7f99721	304	* @}
bogdanm	85:024bf7f99721	305	*/
bogdanm	85:024bf7f99721	306
bogdanm	85:024bf7f99721	307
bogdanm	85:024bf7f99721	308	/** @defgroup SPI_BaudRate_Prescaler
bogdanm	85:024bf7f99721	309	* @{
bogdanm	85:024bf7f99721	310	*/
bogdanm	85:024bf7f99721	311
bogdanm	85:024bf7f99721	312	#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	313	#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	314	#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	315	#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
bogdanm	85:024bf7f99721	316	#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	317	#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
bogdanm	85:024bf7f99721	318	#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
bogdanm	85:024bf7f99721	319	#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
bogdanm	85:024bf7f99721	320	#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) \|\| \
bogdanm	85:024bf7f99721	321	((PRESCALER) == SPI_BAUDRATEPRESCALER_4) \|\| \
bogdanm	85:024bf7f99721	322	((PRESCALER) == SPI_BAUDRATEPRESCALER_8) \|\| \
bogdanm	85:024bf7f99721	323	((PRESCALER) == SPI_BAUDRATEPRESCALER_16) \|\| \
bogdanm	85:024bf7f99721	324	((PRESCALER) == SPI_BAUDRATEPRESCALER_32) \|\| \
bogdanm	85:024bf7f99721	325	((PRESCALER) == SPI_BAUDRATEPRESCALER_64) \|\| \
bogdanm	85:024bf7f99721	326	((PRESCALER) == SPI_BAUDRATEPRESCALER_128) \|\| \
bogdanm	85:024bf7f99721	327	((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
bogdanm	85:024bf7f99721	328	/**
bogdanm	85:024bf7f99721	329	* @}
bogdanm	85:024bf7f99721	330	*/
bogdanm	85:024bf7f99721	331
bogdanm	85:024bf7f99721	332	/** @defgroup SPI_MSB_LSB_transmission
bogdanm	85:024bf7f99721	333	* @{
bogdanm	85:024bf7f99721	334	*/
bogdanm	85:024bf7f99721	335
bogdanm	85:024bf7f99721	336	#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	337	#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm	85:024bf7f99721	338	#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) \|\| \
bogdanm	85:024bf7f99721	339	((BIT) == SPI_FIRSTBIT_LSB))
bogdanm	85:024bf7f99721	340	/**
bogdanm	85:024bf7f99721	341	* @}
bogdanm	85:024bf7f99721	342	*/
bogdanm	85:024bf7f99721	343
bogdanm	85:024bf7f99721	344	/** @defgroup SPI_TI_mode
bogdanm	85:024bf7f99721	345	* @{
bogdanm	85:024bf7f99721	346	*/
bogdanm	85:024bf7f99721	347
bogdanm	85:024bf7f99721	348	#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	349	#define SPI_TIMODE_ENABLED SPI_CR2_FRF
bogdanm	85:024bf7f99721	350	#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) \|\| \
bogdanm	85:024bf7f99721	351	((MODE) == SPI_TIMODE_ENABLED))
bogdanm	85:024bf7f99721	352	/**
bogdanm	85:024bf7f99721	353	* @}
bogdanm	85:024bf7f99721	354	*/
bogdanm	85:024bf7f99721	355
bogdanm	85:024bf7f99721	356	/** @defgroup SPI_CRC_Calculation
bogdanm	85:024bf7f99721	357	* @{
bogdanm	85:024bf7f99721	358	*/
bogdanm	85:024bf7f99721	359
bogdanm	85:024bf7f99721	360	#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	361	#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
bogdanm	85:024bf7f99721	362	#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) \|\| \
bogdanm	85:024bf7f99721	363	((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
bogdanm	85:024bf7f99721	364	/**
bogdanm	85:024bf7f99721	365	* @}
bogdanm	85:024bf7f99721	366	*/
bogdanm	85:024bf7f99721	367
bogdanm	85:024bf7f99721	368	/** @defgroup SPI_CRC_length
bogdanm	85:024bf7f99721	369	* @{
bogdanm	85:024bf7f99721	370	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	371	* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
bogdanm	85:024bf7f99721	372	* SPI_CRC_LENGTH_8BIT : CRC 8bit
bogdanm	85:024bf7f99721	373	* SPI_CRC_LENGTH_16BIT : CRC 16bit
bogdanm	85:024bf7f99721	374	*/
bogdanm	85:024bf7f99721	375	#define SPI_CRC_LENGTH_DATASIZE 0
bogdanm	85:024bf7f99721	376	#define SPI_CRC_LENGTH_8BIT 1
bogdanm	85:024bf7f99721	377	#define SPI_CRC_LENGTH_16BIT 2
bogdanm	85:024bf7f99721	378	#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) \|\|\
bogdanm	85:024bf7f99721	379	((LENGTH) == SPI_CRC_LENGTH_8BIT) \|\| \
bogdanm	85:024bf7f99721	380	((LENGTH) == SPI_CRC_LENGTH_16BIT))
bogdanm	85:024bf7f99721	381	/**
bogdanm	85:024bf7f99721	382	* @}
bogdanm	85:024bf7f99721	383	*/
bogdanm	85:024bf7f99721	384
bogdanm	85:024bf7f99721	385	/** @defgroup SPI_FIFO_reception_threshold
bogdanm	85:024bf7f99721	386	* @{
bogdanm	85:024bf7f99721	387	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	388	* SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
bogdanm	85:024bf7f99721	389	* level is greater or equal to 1/2(16-bits).
bogdanm	85:024bf7f99721	390	* SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
bogdanm	85:024bf7f99721	391	* level is greater or equal to 1/4(8 bits).
bogdanm	85:024bf7f99721	392	*/
bogdanm	85:024bf7f99721	393	#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
bogdanm	85:024bf7f99721	394	#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
bogdanm	85:024bf7f99721	395	#define SPI_RXFIFO_THRESHOLD_HF ((uint32_t)0x0)
bogdanm	85:024bf7f99721	396
bogdanm	85:024bf7f99721	397	/**
bogdanm	85:024bf7f99721	398	* @}
bogdanm	85:024bf7f99721	399	*/
bogdanm	85:024bf7f99721	400
bogdanm	85:024bf7f99721	401	/** @defgroup SPI_Interrupt_configuration_definition
bogdanm	85:024bf7f99721	402	* @brief SPI Interrupt definition
bogdanm	85:024bf7f99721	403	* Elements values convention: 0xXXXXXXXX
bogdanm	85:024bf7f99721	404	* - XXXXXXXX : Interrupt control mask
bogdanm	85:024bf7f99721	405	* @{
bogdanm	85:024bf7f99721	406	*/
bogdanm	85:024bf7f99721	407	#define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm	85:024bf7f99721	408	#define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm	85:024bf7f99721	409	#define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm	85:024bf7f99721	410	#define IS_SPI_IT(IT) (((IT) == SPI_IT_TXE) \|\| \
bogdanm	85:024bf7f99721	411	((IT) == SPI_IT_RXNE) \|\| \
bogdanm	85:024bf7f99721	412	((IT) == SPI_IT_ERR))
bogdanm	85:024bf7f99721	413	/**
bogdanm	85:024bf7f99721	414	* @}
bogdanm	85:024bf7f99721	415	*/
bogdanm	85:024bf7f99721	416
bogdanm	85:024bf7f99721	417
bogdanm	85:024bf7f99721	418	/** @defgroup SPI_Flag_definition
bogdanm	85:024bf7f99721	419	* @brief Flag definition
bogdanm	85:024bf7f99721	420	* Elements values convention: 0xXXXXYYYY
bogdanm	85:024bf7f99721	421	* - XXXX : Flag register Index
bogdanm	85:024bf7f99721	422	* - YYYY : Flag mask
bogdanm	85:024bf7f99721	423	*/
bogdanm	85:024bf7f99721	424	#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
bogdanm	85:024bf7f99721	425	#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
bogdanm	85:024bf7f99721	426	#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
bogdanm	85:024bf7f99721	427	#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
bogdanm	85:024bf7f99721	428	#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
bogdanm	85:024bf7f99721	429	#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
bogdanm	85:024bf7f99721	430	#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
bogdanm	85:024bf7f99721	431	#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
bogdanm	85:024bf7f99721	432	#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
bogdanm	85:024bf7f99721	433	#define IS_SPI_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXNE) \|\| \
bogdanm	85:024bf7f99721	434	((FLAG) == SPI_FLAG_TXE) \|\| \
bogdanm	85:024bf7f99721	435	((FLAG) == SPI_FLAG_BSY) \|\| \
bogdanm	85:024bf7f99721	436	((FLAG) == SPI_FLAG_CRCERR)\|\| \
bogdanm	85:024bf7f99721	437	((FLAG) == SPI_FLAG_MODF) \|\| \
bogdanm	85:024bf7f99721	438	((FLAG) == SPI_FLAG_OVR) \|\| \
bogdanm	85:024bf7f99721	439	((FLAG) == SPI_FLAG_FTLVL) \|\| \
bogdanm	85:024bf7f99721	440	((FLAG) == SPI_FLAG_FRLVL) \|\| \
bogdanm	85:024bf7f99721	441	((FLAG) == SPI_IT_FRE))
bogdanm	85:024bf7f99721	442
bogdanm	85:024bf7f99721	443
bogdanm	85:024bf7f99721	444	/** @defgroup SPI_transmission_fifo_status_level
bogdanm	85:024bf7f99721	445	* @{
bogdanm	85:024bf7f99721	446	*/
bogdanm	85:024bf7f99721	447
bogdanm	85:024bf7f99721	448	#define SPI_FTLVL_EMPTY ((uint16_t)0x0000)
bogdanm	85:024bf7f99721	449	#define SPI_FTLVL_QUARTER_FULL ((uint16_t)0x0800)
bogdanm	85:024bf7f99721	450	#define SPI_FTLVL_HALF_FULL ((uint16_t)0x1000)
bogdanm	85:024bf7f99721	451	#define SPI_FTLVL_FULL ((uint16_t)0x1800)
bogdanm	85:024bf7f99721	452
bogdanm	85:024bf7f99721	453
bogdanm	85:024bf7f99721	454	/**
bogdanm	85:024bf7f99721	455	* @}
bogdanm	85:024bf7f99721	456	*/
bogdanm	85:024bf7f99721	457
bogdanm	85:024bf7f99721	458	/** @defgroup SPI_reception_fifo_status_level
bogdanm	85:024bf7f99721	459	* @{
bogdanm	85:024bf7f99721	460	*/
bogdanm	85:024bf7f99721	461	#define SPI_FRLVL_EMPTY ((uint16_t)0x0000)
bogdanm	85:024bf7f99721	462	#define SPI_FRLVL_QUARTER_FULL ((uint16_t)0x0200)
bogdanm	85:024bf7f99721	463	#define SPI_FRLVL_HALF_FULL ((uint16_t)0x0400)
bogdanm	85:024bf7f99721	464	#define SPI_FRLVL_FULL ((uint16_t)0x0600)
bogdanm	85:024bf7f99721	465
bogdanm	85:024bf7f99721	466	/**
bogdanm	85:024bf7f99721	467	* @}
bogdanm	85:024bf7f99721	468	*/
bogdanm	85:024bf7f99721	469
bogdanm	85:024bf7f99721	470	/**
bogdanm	85:024bf7f99721	471	* @}
bogdanm	85:024bf7f99721	472	*/
bogdanm	85:024bf7f99721	473
bogdanm	85:024bf7f99721	474
bogdanm	85:024bf7f99721	475	/* Exported macros ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	476
bogdanm	85:024bf7f99721	477	/** @brief Reset SPI handle state
bogdanm	85:024bf7f99721	478	* @param __HANDLE__: SPI handle.
bogdanm	85:024bf7f99721	479	* @retval None
bogdanm	85:024bf7f99721	480	*/
bogdanm	85:024bf7f99721	481	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm	85:024bf7f99721	482
bogdanm	85:024bf7f99721	483	/** @brief Enables or disables the specified SPI interrupts.
bogdanm	85:024bf7f99721	484	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	485	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	486	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm	85:024bf7f99721	487	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	488	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm	85:024bf7f99721	489	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm	85:024bf7f99721	490	* @arg SPI_IT_ERR: Error interrupt enable
bogdanm	85:024bf7f99721	491	* @retval None
bogdanm	85:024bf7f99721	492	*/
bogdanm	85:024bf7f99721	493
bogdanm	85:024bf7f99721	494	#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	495	#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
bogdanm	85:024bf7f99721	496
bogdanm	85:024bf7f99721	497	/** @brief Checks if the specified SPI interrupt source is enabled or disabled.
bogdanm	85:024bf7f99721	498	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	499	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	500	* @param __INTERRUPT__: specifies the SPI interrupt source to check.
bogdanm	85:024bf7f99721	501	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	502	* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm	85:024bf7f99721	503	* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm	85:024bf7f99721	504	* @arg SPI_IT_ERR: Error interrupt enable
bogdanm	85:024bf7f99721	505	* @retval The new state of __IT__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	506	*/
bogdanm	85:024bf7f99721	507	#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	85:024bf7f99721	508
bogdanm	85:024bf7f99721	509	/** @brief Checks whether the specified SPI flag is set or not.
bogdanm	85:024bf7f99721	510	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	511	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	512	* @param __FLAG__: specifies the flag to check.
bogdanm	85:024bf7f99721	513	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	514	* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm	85:024bf7f99721	515	* @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm	85:024bf7f99721	516	* @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm	85:024bf7f99721	517	* @arg SPI_FLAG_MODF: Mode fault flag
bogdanm	85:024bf7f99721	518	* @arg SPI_FLAG_OVR: Overrun flag
bogdanm	85:024bf7f99721	519	* @arg SPI_FLAG_BSY: Busy flag
bogdanm	85:024bf7f99721	520	* @arg SPI_FLAG_FRE: Frame format error flag
bogdanm	85:024bf7f99721	521	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	85:024bf7f99721	522	*/
bogdanm	85:024bf7f99721	523	#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm	85:024bf7f99721	524
bogdanm	85:024bf7f99721	525	/** @brief Clears the SPI CRCERR pending flag.
bogdanm	85:024bf7f99721	526	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	527	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	528	* @retval None
bogdanm	85:024bf7f99721	529	*/
bogdanm	85:024bf7f99721	530	#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= (uint16_t)(~SPI_FLAG_CRCERR))
bogdanm	85:024bf7f99721	531
bogdanm	85:024bf7f99721	532	/** @brief Clears the SPI MODF pending flag.
bogdanm	85:024bf7f99721	533	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	534	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	535	*
bogdanm	85:024bf7f99721	536	* @retval None
bogdanm	85:024bf7f99721	537	*/
bogdanm	85:024bf7f99721	538	#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
bogdanm	85:024bf7f99721	539	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE);}while(0)
bogdanm	85:024bf7f99721	540
bogdanm	85:024bf7f99721	541	/** @brief Clears the SPI OVR pending flag.
bogdanm	85:024bf7f99721	542	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	543	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	544	*
bogdanm	85:024bf7f99721	545	* @retval None
bogdanm	85:024bf7f99721	546	*/
bogdanm	85:024bf7f99721	547	#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
bogdanm	85:024bf7f99721	548	(__HANDLE__)->Instance->SR;}while(0)
bogdanm	85:024bf7f99721	549
bogdanm	85:024bf7f99721	550	/** @brief Clears the SPI FRE pending flag.
bogdanm	85:024bf7f99721	551	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	552	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	553	*
bogdanm	85:024bf7f99721	554	* @retval None
bogdanm	85:024bf7f99721	555	*/
bogdanm	85:024bf7f99721	556	#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
bogdanm	85:024bf7f99721	557
bogdanm	85:024bf7f99721	558	/** @brief Enables the SPI.
bogdanm	85:024bf7f99721	559	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	560	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	561	* @retval None
bogdanm	85:024bf7f99721	562	*/
bogdanm	85:024bf7f99721	563	#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= SPI_CR1_SPE)
bogdanm	85:024bf7f99721	564
bogdanm	85:024bf7f99721	565	/** @brief Disables the SPI.
bogdanm	85:024bf7f99721	566	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	567	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	568	* @retval None
bogdanm	85:024bf7f99721	569	*/
bogdanm	85:024bf7f99721	570	#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_SPE))
bogdanm	85:024bf7f99721	571
bogdanm	85:024bf7f99721	572	/** @brief Sets the SPI transmit-only mode.
bogdanm	85:024bf7f99721	573	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	574	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	575	* @retval None
bogdanm	85:024bf7f99721	576	*/
bogdanm	85:024bf7f99721	577	#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= SPI_CR1_BIDIOE)
bogdanm	85:024bf7f99721	578
bogdanm	85:024bf7f99721	579	/** @brief Sets the SPI receive-only mode.
bogdanm	85:024bf7f99721	580	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	581	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	582	* @retval None
bogdanm	85:024bf7f99721	583	*/
bogdanm	85:024bf7f99721	584	#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_BIDIOE))
bogdanm	85:024bf7f99721	585
bogdanm	85:024bf7f99721	586	/** @brief Resets the CRC calculation of the SPI.
bogdanm	85:024bf7f99721	587	* @param __HANDLE__: specifies the SPI Handle.
bogdanm	85:024bf7f99721	588	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm	85:024bf7f99721	589	* @retval None
bogdanm	85:024bf7f99721	590	*/
bogdanm	85:024bf7f99721	591	#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
bogdanm	85:024bf7f99721	592	(__HANDLE__)->Instance->CR1 \|= SPI_CR1_CRCEN;}while(0)
bogdanm	85:024bf7f99721	593
bogdanm	85:024bf7f99721	594
bogdanm	85:024bf7f99721	595	#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
bogdanm	85:024bf7f99721	596
bogdanm	85:024bf7f99721	597	/* Exported functions --------------------------------------------------------*/
bogdanm	85:024bf7f99721	598
bogdanm	85:024bf7f99721	599	/* Initialization and de-initialization functions ****************************/
bogdanm	85:024bf7f99721	600	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	601	HAL_StatusTypeDef HAL_SPI_InitExtended(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	602	HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	603	void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	604	void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	605
bogdanm	85:024bf7f99721	606	/* IO operation functions *****************************************************/
bogdanm	85:024bf7f99721	607	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
bogdanm	85:024bf7f99721	608	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
bogdanm	85:024bf7f99721	609	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
bogdanm	85:024bf7f99721	610	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	611	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	612	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm	85:024bf7f99721	613	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	614	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
bogdanm	85:024bf7f99721	615	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm	85:024bf7f99721	616	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	617	void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	618	void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	619	void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	620	void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	621
bogdanm	85:024bf7f99721	622	/* Peripheral State and Error functions ***************************************/
bogdanm	85:024bf7f99721	623	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
bogdanm	85:024bf7f99721	624
bogdanm	85:024bf7f99721	625	/**
bogdanm	85:024bf7f99721	626	* @}
bogdanm	85:024bf7f99721	627	*/
bogdanm	85:024bf7f99721	628
bogdanm	85:024bf7f99721	629	/**
bogdanm	85:024bf7f99721	630	* @}
bogdanm	85:024bf7f99721	631	*/
bogdanm	85:024bf7f99721	632
bogdanm	85:024bf7f99721	633	#ifdef __cplusplus
bogdanm	85:024bf7f99721	634	}
bogdanm	85:024bf7f99721	635	#endif
bogdanm	85:024bf7f99721	636
bogdanm	85:024bf7f99721	637	#endif /* __STM32F0xx_HAL_SPI_H */
bogdanm	85:024bf7f99721	638
bogdanm	85:024bf7f99721	639	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F072RB/stm32f0xx_hal_spi.h@85:024bf7f99721, 2014-06-11 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning