mbed libraries for KL25Z
KL25Z/core_cmInstr.h@0:8024c367e29f, 2012-10-05 (annotated)
- Committer:
- emilmont
- Date:
- Fri Oct 05 09:16:41 2012 +0000
- Revision:
- 0:8024c367e29f
- Child:
- 2:e9a661555b58
First release of the mbed libraries for KL25Z
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 0:8024c367e29f | 1 | /**************************************************************************//** |
emilmont | 0:8024c367e29f | 2 | * @file core_cmInstr.h |
emilmont | 0:8024c367e29f | 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File |
emilmont | 0:8024c367e29f | 4 | * @version V3.02 |
emilmont | 0:8024c367e29f | 5 | * @date 08. May 2012 |
emilmont | 0:8024c367e29f | 6 | * |
emilmont | 0:8024c367e29f | 7 | * @note |
emilmont | 0:8024c367e29f | 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. |
emilmont | 0:8024c367e29f | 9 | * |
emilmont | 0:8024c367e29f | 10 | * @par |
emilmont | 0:8024c367e29f | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
emilmont | 0:8024c367e29f | 12 | * processor based microcontrollers. This file can be freely distributed |
emilmont | 0:8024c367e29f | 13 | * within development tools that are supporting such ARM based processors. |
emilmont | 0:8024c367e29f | 14 | * |
emilmont | 0:8024c367e29f | 15 | * @par |
emilmont | 0:8024c367e29f | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
emilmont | 0:8024c367e29f | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
emilmont | 0:8024c367e29f | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
emilmont | 0:8024c367e29f | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
emilmont | 0:8024c367e29f | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
emilmont | 0:8024c367e29f | 21 | * |
emilmont | 0:8024c367e29f | 22 | ******************************************************************************/ |
emilmont | 0:8024c367e29f | 23 | |
emilmont | 0:8024c367e29f | 24 | #ifndef __CORE_CMINSTR_H |
emilmont | 0:8024c367e29f | 25 | #define __CORE_CMINSTR_H |
emilmont | 0:8024c367e29f | 26 | |
emilmont | 0:8024c367e29f | 27 | |
emilmont | 0:8024c367e29f | 28 | /* ########################## Core Instruction Access ######################### */ |
emilmont | 0:8024c367e29f | 29 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
emilmont | 0:8024c367e29f | 30 | Access to dedicated instructions |
emilmont | 0:8024c367e29f | 31 | @{ |
emilmont | 0:8024c367e29f | 32 | */ |
emilmont | 0:8024c367e29f | 33 | |
emilmont | 0:8024c367e29f | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
emilmont | 0:8024c367e29f | 35 | /* ARM armcc specific functions */ |
emilmont | 0:8024c367e29f | 36 | |
emilmont | 0:8024c367e29f | 37 | #if (__ARMCC_VERSION < 400677) |
emilmont | 0:8024c367e29f | 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
emilmont | 0:8024c367e29f | 39 | #endif |
emilmont | 0:8024c367e29f | 40 | |
emilmont | 0:8024c367e29f | 41 | |
emilmont | 0:8024c367e29f | 42 | /** \brief No Operation |
emilmont | 0:8024c367e29f | 43 | |
emilmont | 0:8024c367e29f | 44 | No Operation does nothing. This instruction can be used for code alignment purposes. |
emilmont | 0:8024c367e29f | 45 | */ |
emilmont | 0:8024c367e29f | 46 | #define __NOP __nop |
emilmont | 0:8024c367e29f | 47 | |
emilmont | 0:8024c367e29f | 48 | |
emilmont | 0:8024c367e29f | 49 | /** \brief Wait For Interrupt |
emilmont | 0:8024c367e29f | 50 | |
emilmont | 0:8024c367e29f | 51 | Wait For Interrupt is a hint instruction that suspends execution |
emilmont | 0:8024c367e29f | 52 | until one of a number of events occurs. |
emilmont | 0:8024c367e29f | 53 | */ |
emilmont | 0:8024c367e29f | 54 | #define __WFI __wfi |
emilmont | 0:8024c367e29f | 55 | |
emilmont | 0:8024c367e29f | 56 | |
emilmont | 0:8024c367e29f | 57 | /** \brief Wait For Event |
emilmont | 0:8024c367e29f | 58 | |
emilmont | 0:8024c367e29f | 59 | Wait For Event is a hint instruction that permits the processor to enter |
emilmont | 0:8024c367e29f | 60 | a low-power state until one of a number of events occurs. |
emilmont | 0:8024c367e29f | 61 | */ |
emilmont | 0:8024c367e29f | 62 | #define __WFE __wfe |
emilmont | 0:8024c367e29f | 63 | |
emilmont | 0:8024c367e29f | 64 | |
emilmont | 0:8024c367e29f | 65 | /** \brief Send Event |
emilmont | 0:8024c367e29f | 66 | |
emilmont | 0:8024c367e29f | 67 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
emilmont | 0:8024c367e29f | 68 | */ |
emilmont | 0:8024c367e29f | 69 | #define __SEV __sev |
emilmont | 0:8024c367e29f | 70 | |
emilmont | 0:8024c367e29f | 71 | |
emilmont | 0:8024c367e29f | 72 | /** \brief Instruction Synchronization Barrier |
emilmont | 0:8024c367e29f | 73 | |
emilmont | 0:8024c367e29f | 74 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
emilmont | 0:8024c367e29f | 75 | so that all instructions following the ISB are fetched from cache or |
emilmont | 0:8024c367e29f | 76 | memory, after the instruction has been completed. |
emilmont | 0:8024c367e29f | 77 | */ |
emilmont | 0:8024c367e29f | 78 | #define __ISB() __isb(0xF) |
emilmont | 0:8024c367e29f | 79 | |
emilmont | 0:8024c367e29f | 80 | |
emilmont | 0:8024c367e29f | 81 | /** \brief Data Synchronization Barrier |
emilmont | 0:8024c367e29f | 82 | |
emilmont | 0:8024c367e29f | 83 | This function acts as a special kind of Data Memory Barrier. |
emilmont | 0:8024c367e29f | 84 | It completes when all explicit memory accesses before this instruction complete. |
emilmont | 0:8024c367e29f | 85 | */ |
emilmont | 0:8024c367e29f | 86 | #define __DSB() __dsb(0xF) |
emilmont | 0:8024c367e29f | 87 | |
emilmont | 0:8024c367e29f | 88 | |
emilmont | 0:8024c367e29f | 89 | /** \brief Data Memory Barrier |
emilmont | 0:8024c367e29f | 90 | |
emilmont | 0:8024c367e29f | 91 | This function ensures the apparent order of the explicit memory operations before |
emilmont | 0:8024c367e29f | 92 | and after the instruction, without ensuring their completion. |
emilmont | 0:8024c367e29f | 93 | */ |
emilmont | 0:8024c367e29f | 94 | #define __DMB() __dmb(0xF) |
emilmont | 0:8024c367e29f | 95 | |
emilmont | 0:8024c367e29f | 96 | |
emilmont | 0:8024c367e29f | 97 | /** \brief Reverse byte order (32 bit) |
emilmont | 0:8024c367e29f | 98 | |
emilmont | 0:8024c367e29f | 99 | This function reverses the byte order in integer value. |
emilmont | 0:8024c367e29f | 100 | |
emilmont | 0:8024c367e29f | 101 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 102 | \return Reversed value |
emilmont | 0:8024c367e29f | 103 | */ |
emilmont | 0:8024c367e29f | 104 | #define __REV __rev |
emilmont | 0:8024c367e29f | 105 | |
emilmont | 0:8024c367e29f | 106 | |
emilmont | 0:8024c367e29f | 107 | /** \brief Reverse byte order (16 bit) |
emilmont | 0:8024c367e29f | 108 | |
emilmont | 0:8024c367e29f | 109 | This function reverses the byte order in two unsigned short values. |
emilmont | 0:8024c367e29f | 110 | |
emilmont | 0:8024c367e29f | 111 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 112 | \return Reversed value |
emilmont | 0:8024c367e29f | 113 | */ |
emilmont | 0:8024c367e29f | 114 | #ifndef __NO_EMBEDDED_ASM |
emilmont | 0:8024c367e29f | 115 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
emilmont | 0:8024c367e29f | 116 | { |
emilmont | 0:8024c367e29f | 117 | rev16 r0, r0 |
emilmont | 0:8024c367e29f | 118 | bx lr |
emilmont | 0:8024c367e29f | 119 | } |
emilmont | 0:8024c367e29f | 120 | #endif |
emilmont | 0:8024c367e29f | 121 | |
emilmont | 0:8024c367e29f | 122 | /** \brief Reverse byte order in signed short value |
emilmont | 0:8024c367e29f | 123 | |
emilmont | 0:8024c367e29f | 124 | This function reverses the byte order in a signed short value with sign extension to integer. |
emilmont | 0:8024c367e29f | 125 | |
emilmont | 0:8024c367e29f | 126 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 127 | \return Reversed value |
emilmont | 0:8024c367e29f | 128 | */ |
emilmont | 0:8024c367e29f | 129 | #ifndef __NO_EMBEDDED_ASM |
emilmont | 0:8024c367e29f | 130 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) |
emilmont | 0:8024c367e29f | 131 | { |
emilmont | 0:8024c367e29f | 132 | revsh r0, r0 |
emilmont | 0:8024c367e29f | 133 | bx lr |
emilmont | 0:8024c367e29f | 134 | } |
emilmont | 0:8024c367e29f | 135 | #endif |
emilmont | 0:8024c367e29f | 136 | |
emilmont | 0:8024c367e29f | 137 | |
emilmont | 0:8024c367e29f | 138 | /** \brief Rotate Right in unsigned value (32 bit) |
emilmont | 0:8024c367e29f | 139 | |
emilmont | 0:8024c367e29f | 140 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
emilmont | 0:8024c367e29f | 141 | |
emilmont | 0:8024c367e29f | 142 | \param [in] value Value to rotate |
emilmont | 0:8024c367e29f | 143 | \param [in] value Number of Bits to rotate |
emilmont | 0:8024c367e29f | 144 | \return Rotated value |
emilmont | 0:8024c367e29f | 145 | */ |
emilmont | 0:8024c367e29f | 146 | #define __ROR __ror |
emilmont | 0:8024c367e29f | 147 | |
emilmont | 0:8024c367e29f | 148 | |
emilmont | 0:8024c367e29f | 149 | #if (__CORTEX_M >= 0x03) |
emilmont | 0:8024c367e29f | 150 | |
emilmont | 0:8024c367e29f | 151 | /** \brief Reverse bit order of value |
emilmont | 0:8024c367e29f | 152 | |
emilmont | 0:8024c367e29f | 153 | This function reverses the bit order of the given value. |
emilmont | 0:8024c367e29f | 154 | |
emilmont | 0:8024c367e29f | 155 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 156 | \return Reversed value |
emilmont | 0:8024c367e29f | 157 | */ |
emilmont | 0:8024c367e29f | 158 | #define __RBIT __rbit |
emilmont | 0:8024c367e29f | 159 | |
emilmont | 0:8024c367e29f | 160 | |
emilmont | 0:8024c367e29f | 161 | /** \brief LDR Exclusive (8 bit) |
emilmont | 0:8024c367e29f | 162 | |
emilmont | 0:8024c367e29f | 163 | This function performs a exclusive LDR command for 8 bit value. |
emilmont | 0:8024c367e29f | 164 | |
emilmont | 0:8024c367e29f | 165 | \param [in] ptr Pointer to data |
emilmont | 0:8024c367e29f | 166 | \return value of type uint8_t at (*ptr) |
emilmont | 0:8024c367e29f | 167 | */ |
emilmont | 0:8024c367e29f | 168 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
emilmont | 0:8024c367e29f | 169 | |
emilmont | 0:8024c367e29f | 170 | |
emilmont | 0:8024c367e29f | 171 | /** \brief LDR Exclusive (16 bit) |
emilmont | 0:8024c367e29f | 172 | |
emilmont | 0:8024c367e29f | 173 | This function performs a exclusive LDR command for 16 bit values. |
emilmont | 0:8024c367e29f | 174 | |
emilmont | 0:8024c367e29f | 175 | \param [in] ptr Pointer to data |
emilmont | 0:8024c367e29f | 176 | \return value of type uint16_t at (*ptr) |
emilmont | 0:8024c367e29f | 177 | */ |
emilmont | 0:8024c367e29f | 178 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
emilmont | 0:8024c367e29f | 179 | |
emilmont | 0:8024c367e29f | 180 | |
emilmont | 0:8024c367e29f | 181 | /** \brief LDR Exclusive (32 bit) |
emilmont | 0:8024c367e29f | 182 | |
emilmont | 0:8024c367e29f | 183 | This function performs a exclusive LDR command for 32 bit values. |
emilmont | 0:8024c367e29f | 184 | |
emilmont | 0:8024c367e29f | 185 | \param [in] ptr Pointer to data |
emilmont | 0:8024c367e29f | 186 | \return value of type uint32_t at (*ptr) |
emilmont | 0:8024c367e29f | 187 | */ |
emilmont | 0:8024c367e29f | 188 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
emilmont | 0:8024c367e29f | 189 | |
emilmont | 0:8024c367e29f | 190 | |
emilmont | 0:8024c367e29f | 191 | /** \brief STR Exclusive (8 bit) |
emilmont | 0:8024c367e29f | 192 | |
emilmont | 0:8024c367e29f | 193 | This function performs a exclusive STR command for 8 bit values. |
emilmont | 0:8024c367e29f | 194 | |
emilmont | 0:8024c367e29f | 195 | \param [in] value Value to store |
emilmont | 0:8024c367e29f | 196 | \param [in] ptr Pointer to location |
emilmont | 0:8024c367e29f | 197 | \return 0 Function succeeded |
emilmont | 0:8024c367e29f | 198 | \return 1 Function failed |
emilmont | 0:8024c367e29f | 199 | */ |
emilmont | 0:8024c367e29f | 200 | #define __STREXB(value, ptr) __strex(value, ptr) |
emilmont | 0:8024c367e29f | 201 | |
emilmont | 0:8024c367e29f | 202 | |
emilmont | 0:8024c367e29f | 203 | /** \brief STR Exclusive (16 bit) |
emilmont | 0:8024c367e29f | 204 | |
emilmont | 0:8024c367e29f | 205 | This function performs a exclusive STR command for 16 bit values. |
emilmont | 0:8024c367e29f | 206 | |
emilmont | 0:8024c367e29f | 207 | \param [in] value Value to store |
emilmont | 0:8024c367e29f | 208 | \param [in] ptr Pointer to location |
emilmont | 0:8024c367e29f | 209 | \return 0 Function succeeded |
emilmont | 0:8024c367e29f | 210 | \return 1 Function failed |
emilmont | 0:8024c367e29f | 211 | */ |
emilmont | 0:8024c367e29f | 212 | #define __STREXH(value, ptr) __strex(value, ptr) |
emilmont | 0:8024c367e29f | 213 | |
emilmont | 0:8024c367e29f | 214 | |
emilmont | 0:8024c367e29f | 215 | /** \brief STR Exclusive (32 bit) |
emilmont | 0:8024c367e29f | 216 | |
emilmont | 0:8024c367e29f | 217 | This function performs a exclusive STR command for 32 bit values. |
emilmont | 0:8024c367e29f | 218 | |
emilmont | 0:8024c367e29f | 219 | \param [in] value Value to store |
emilmont | 0:8024c367e29f | 220 | \param [in] ptr Pointer to location |
emilmont | 0:8024c367e29f | 221 | \return 0 Function succeeded |
emilmont | 0:8024c367e29f | 222 | \return 1 Function failed |
emilmont | 0:8024c367e29f | 223 | */ |
emilmont | 0:8024c367e29f | 224 | #define __STREXW(value, ptr) __strex(value, ptr) |
emilmont | 0:8024c367e29f | 225 | |
emilmont | 0:8024c367e29f | 226 | |
emilmont | 0:8024c367e29f | 227 | /** \brief Remove the exclusive lock |
emilmont | 0:8024c367e29f | 228 | |
emilmont | 0:8024c367e29f | 229 | This function removes the exclusive lock which is created by LDREX. |
emilmont | 0:8024c367e29f | 230 | |
emilmont | 0:8024c367e29f | 231 | */ |
emilmont | 0:8024c367e29f | 232 | #define __CLREX __clrex |
emilmont | 0:8024c367e29f | 233 | |
emilmont | 0:8024c367e29f | 234 | |
emilmont | 0:8024c367e29f | 235 | /** \brief Signed Saturate |
emilmont | 0:8024c367e29f | 236 | |
emilmont | 0:8024c367e29f | 237 | This function saturates a signed value. |
emilmont | 0:8024c367e29f | 238 | |
emilmont | 0:8024c367e29f | 239 | \param [in] value Value to be saturated |
emilmont | 0:8024c367e29f | 240 | \param [in] sat Bit position to saturate to (1..32) |
emilmont | 0:8024c367e29f | 241 | \return Saturated value |
emilmont | 0:8024c367e29f | 242 | */ |
emilmont | 0:8024c367e29f | 243 | #define __SSAT __ssat |
emilmont | 0:8024c367e29f | 244 | |
emilmont | 0:8024c367e29f | 245 | |
emilmont | 0:8024c367e29f | 246 | /** \brief Unsigned Saturate |
emilmont | 0:8024c367e29f | 247 | |
emilmont | 0:8024c367e29f | 248 | This function saturates an unsigned value. |
emilmont | 0:8024c367e29f | 249 | |
emilmont | 0:8024c367e29f | 250 | \param [in] value Value to be saturated |
emilmont | 0:8024c367e29f | 251 | \param [in] sat Bit position to saturate to (0..31) |
emilmont | 0:8024c367e29f | 252 | \return Saturated value |
emilmont | 0:8024c367e29f | 253 | */ |
emilmont | 0:8024c367e29f | 254 | #define __USAT __usat |
emilmont | 0:8024c367e29f | 255 | |
emilmont | 0:8024c367e29f | 256 | |
emilmont | 0:8024c367e29f | 257 | /** \brief Count leading zeros |
emilmont | 0:8024c367e29f | 258 | |
emilmont | 0:8024c367e29f | 259 | This function counts the number of leading zeros of a data value. |
emilmont | 0:8024c367e29f | 260 | |
emilmont | 0:8024c367e29f | 261 | \param [in] value Value to count the leading zeros |
emilmont | 0:8024c367e29f | 262 | \return number of leading zeros in value |
emilmont | 0:8024c367e29f | 263 | */ |
emilmont | 0:8024c367e29f | 264 | #define __CLZ __clz |
emilmont | 0:8024c367e29f | 265 | |
emilmont | 0:8024c367e29f | 266 | #endif /* (__CORTEX_M >= 0x03) */ |
emilmont | 0:8024c367e29f | 267 | |
emilmont | 0:8024c367e29f | 268 | |
emilmont | 0:8024c367e29f | 269 | |
emilmont | 0:8024c367e29f | 270 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ |
emilmont | 0:8024c367e29f | 271 | /* IAR iccarm specific functions */ |
emilmont | 0:8024c367e29f | 272 | |
emilmont | 0:8024c367e29f | 273 | #include <cmsis_iar.h> |
emilmont | 0:8024c367e29f | 274 | |
emilmont | 0:8024c367e29f | 275 | |
emilmont | 0:8024c367e29f | 276 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ |
emilmont | 0:8024c367e29f | 277 | /* TI CCS specific functions */ |
emilmont | 0:8024c367e29f | 278 | |
emilmont | 0:8024c367e29f | 279 | #include <cmsis_ccs.h> |
emilmont | 0:8024c367e29f | 280 | |
emilmont | 0:8024c367e29f | 281 | |
emilmont | 0:8024c367e29f | 282 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ |
emilmont | 0:8024c367e29f | 283 | /* GNU gcc specific functions */ |
emilmont | 0:8024c367e29f | 284 | |
emilmont | 0:8024c367e29f | 285 | /** \brief No Operation |
emilmont | 0:8024c367e29f | 286 | |
emilmont | 0:8024c367e29f | 287 | No Operation does nothing. This instruction can be used for code alignment purposes. |
emilmont | 0:8024c367e29f | 288 | */ |
emilmont | 0:8024c367e29f | 289 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) |
emilmont | 0:8024c367e29f | 290 | { |
emilmont | 0:8024c367e29f | 291 | __ASM volatile ("nop"); |
emilmont | 0:8024c367e29f | 292 | } |
emilmont | 0:8024c367e29f | 293 | |
emilmont | 0:8024c367e29f | 294 | |
emilmont | 0:8024c367e29f | 295 | /** \brief Wait For Interrupt |
emilmont | 0:8024c367e29f | 296 | |
emilmont | 0:8024c367e29f | 297 | Wait For Interrupt is a hint instruction that suspends execution |
emilmont | 0:8024c367e29f | 298 | until one of a number of events occurs. |
emilmont | 0:8024c367e29f | 299 | */ |
emilmont | 0:8024c367e29f | 300 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) |
emilmont | 0:8024c367e29f | 301 | { |
emilmont | 0:8024c367e29f | 302 | __ASM volatile ("wfi"); |
emilmont | 0:8024c367e29f | 303 | } |
emilmont | 0:8024c367e29f | 304 | |
emilmont | 0:8024c367e29f | 305 | |
emilmont | 0:8024c367e29f | 306 | /** \brief Wait For Event |
emilmont | 0:8024c367e29f | 307 | |
emilmont | 0:8024c367e29f | 308 | Wait For Event is a hint instruction that permits the processor to enter |
emilmont | 0:8024c367e29f | 309 | a low-power state until one of a number of events occurs. |
emilmont | 0:8024c367e29f | 310 | */ |
emilmont | 0:8024c367e29f | 311 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) |
emilmont | 0:8024c367e29f | 312 | { |
emilmont | 0:8024c367e29f | 313 | __ASM volatile ("wfe"); |
emilmont | 0:8024c367e29f | 314 | } |
emilmont | 0:8024c367e29f | 315 | |
emilmont | 0:8024c367e29f | 316 | |
emilmont | 0:8024c367e29f | 317 | /** \brief Send Event |
emilmont | 0:8024c367e29f | 318 | |
emilmont | 0:8024c367e29f | 319 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
emilmont | 0:8024c367e29f | 320 | */ |
emilmont | 0:8024c367e29f | 321 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) |
emilmont | 0:8024c367e29f | 322 | { |
emilmont | 0:8024c367e29f | 323 | __ASM volatile ("sev"); |
emilmont | 0:8024c367e29f | 324 | } |
emilmont | 0:8024c367e29f | 325 | |
emilmont | 0:8024c367e29f | 326 | |
emilmont | 0:8024c367e29f | 327 | /** \brief Instruction Synchronization Barrier |
emilmont | 0:8024c367e29f | 328 | |
emilmont | 0:8024c367e29f | 329 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
emilmont | 0:8024c367e29f | 330 | so that all instructions following the ISB are fetched from cache or |
emilmont | 0:8024c367e29f | 331 | memory, after the instruction has been completed. |
emilmont | 0:8024c367e29f | 332 | */ |
emilmont | 0:8024c367e29f | 333 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) |
emilmont | 0:8024c367e29f | 334 | { |
emilmont | 0:8024c367e29f | 335 | __ASM volatile ("isb"); |
emilmont | 0:8024c367e29f | 336 | } |
emilmont | 0:8024c367e29f | 337 | |
emilmont | 0:8024c367e29f | 338 | |
emilmont | 0:8024c367e29f | 339 | /** \brief Data Synchronization Barrier |
emilmont | 0:8024c367e29f | 340 | |
emilmont | 0:8024c367e29f | 341 | This function acts as a special kind of Data Memory Barrier. |
emilmont | 0:8024c367e29f | 342 | It completes when all explicit memory accesses before this instruction complete. |
emilmont | 0:8024c367e29f | 343 | */ |
emilmont | 0:8024c367e29f | 344 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) |
emilmont | 0:8024c367e29f | 345 | { |
emilmont | 0:8024c367e29f | 346 | __ASM volatile ("dsb"); |
emilmont | 0:8024c367e29f | 347 | } |
emilmont | 0:8024c367e29f | 348 | |
emilmont | 0:8024c367e29f | 349 | |
emilmont | 0:8024c367e29f | 350 | /** \brief Data Memory Barrier |
emilmont | 0:8024c367e29f | 351 | |
emilmont | 0:8024c367e29f | 352 | This function ensures the apparent order of the explicit memory operations before |
emilmont | 0:8024c367e29f | 353 | and after the instruction, without ensuring their completion. |
emilmont | 0:8024c367e29f | 354 | */ |
emilmont | 0:8024c367e29f | 355 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) |
emilmont | 0:8024c367e29f | 356 | { |
emilmont | 0:8024c367e29f | 357 | __ASM volatile ("dmb"); |
emilmont | 0:8024c367e29f | 358 | } |
emilmont | 0:8024c367e29f | 359 | |
emilmont | 0:8024c367e29f | 360 | |
emilmont | 0:8024c367e29f | 361 | /** \brief Reverse byte order (32 bit) |
emilmont | 0:8024c367e29f | 362 | |
emilmont | 0:8024c367e29f | 363 | This function reverses the byte order in integer value. |
emilmont | 0:8024c367e29f | 364 | |
emilmont | 0:8024c367e29f | 365 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 366 | \return Reversed value |
emilmont | 0:8024c367e29f | 367 | */ |
emilmont | 0:8024c367e29f | 368 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) |
emilmont | 0:8024c367e29f | 369 | { |
emilmont | 0:8024c367e29f | 370 | uint32_t result; |
emilmont | 0:8024c367e29f | 371 | |
emilmont | 0:8024c367e29f | 372 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
emilmont | 0:8024c367e29f | 373 | return(result); |
emilmont | 0:8024c367e29f | 374 | } |
emilmont | 0:8024c367e29f | 375 | |
emilmont | 0:8024c367e29f | 376 | |
emilmont | 0:8024c367e29f | 377 | /** \brief Reverse byte order (16 bit) |
emilmont | 0:8024c367e29f | 378 | |
emilmont | 0:8024c367e29f | 379 | This function reverses the byte order in two unsigned short values. |
emilmont | 0:8024c367e29f | 380 | |
emilmont | 0:8024c367e29f | 381 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 382 | \return Reversed value |
emilmont | 0:8024c367e29f | 383 | */ |
emilmont | 0:8024c367e29f | 384 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) |
emilmont | 0:8024c367e29f | 385 | { |
emilmont | 0:8024c367e29f | 386 | uint32_t result; |
emilmont | 0:8024c367e29f | 387 | |
emilmont | 0:8024c367e29f | 388 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
emilmont | 0:8024c367e29f | 389 | return(result); |
emilmont | 0:8024c367e29f | 390 | } |
emilmont | 0:8024c367e29f | 391 | |
emilmont | 0:8024c367e29f | 392 | |
emilmont | 0:8024c367e29f | 393 | /** \brief Reverse byte order in signed short value |
emilmont | 0:8024c367e29f | 394 | |
emilmont | 0:8024c367e29f | 395 | This function reverses the byte order in a signed short value with sign extension to integer. |
emilmont | 0:8024c367e29f | 396 | |
emilmont | 0:8024c367e29f | 397 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 398 | \return Reversed value |
emilmont | 0:8024c367e29f | 399 | */ |
emilmont | 0:8024c367e29f | 400 | __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) |
emilmont | 0:8024c367e29f | 401 | { |
emilmont | 0:8024c367e29f | 402 | uint32_t result; |
emilmont | 0:8024c367e29f | 403 | |
emilmont | 0:8024c367e29f | 404 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
emilmont | 0:8024c367e29f | 405 | return(result); |
emilmont | 0:8024c367e29f | 406 | } |
emilmont | 0:8024c367e29f | 407 | |
emilmont | 0:8024c367e29f | 408 | |
emilmont | 0:8024c367e29f | 409 | /** \brief Rotate Right in unsigned value (32 bit) |
emilmont | 0:8024c367e29f | 410 | |
emilmont | 0:8024c367e29f | 411 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
emilmont | 0:8024c367e29f | 412 | |
emilmont | 0:8024c367e29f | 413 | \param [in] value Value to rotate |
emilmont | 0:8024c367e29f | 414 | \param [in] value Number of Bits to rotate |
emilmont | 0:8024c367e29f | 415 | \return Rotated value |
emilmont | 0:8024c367e29f | 416 | */ |
emilmont | 0:8024c367e29f | 417 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) |
emilmont | 0:8024c367e29f | 418 | { |
emilmont | 0:8024c367e29f | 419 | |
emilmont | 0:8024c367e29f | 420 | __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); |
emilmont | 0:8024c367e29f | 421 | return(op1); |
emilmont | 0:8024c367e29f | 422 | } |
emilmont | 0:8024c367e29f | 423 | |
emilmont | 0:8024c367e29f | 424 | |
emilmont | 0:8024c367e29f | 425 | #if (__CORTEX_M >= 0x03) |
emilmont | 0:8024c367e29f | 426 | |
emilmont | 0:8024c367e29f | 427 | /** \brief Reverse bit order of value |
emilmont | 0:8024c367e29f | 428 | |
emilmont | 0:8024c367e29f | 429 | This function reverses the bit order of the given value. |
emilmont | 0:8024c367e29f | 430 | |
emilmont | 0:8024c367e29f | 431 | \param [in] value Value to reverse |
emilmont | 0:8024c367e29f | 432 | \return Reversed value |
emilmont | 0:8024c367e29f | 433 | */ |
emilmont | 0:8024c367e29f | 434 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
emilmont | 0:8024c367e29f | 435 | { |
emilmont | 0:8024c367e29f | 436 | uint32_t result; |
emilmont | 0:8024c367e29f | 437 | |
emilmont | 0:8024c367e29f | 438 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
emilmont | 0:8024c367e29f | 439 | return(result); |
emilmont | 0:8024c367e29f | 440 | } |
emilmont | 0:8024c367e29f | 441 | |
emilmont | 0:8024c367e29f | 442 | |
emilmont | 0:8024c367e29f | 443 | /** \brief LDR Exclusive (8 bit) |
emilmont | 0:8024c367e29f | 444 | |
emilmont | 0:8024c367e29f | 445 | This function performs a exclusive LDR command for 8 bit value. |
emilmont | 0:8024c367e29f | 446 | |
emilmont | 0:8024c367e29f | 447 | \param [in] ptr Pointer to data |
emilmont | 0:8024c367e29f | 448 | \return value of type uint8_t at (*ptr) |
emilmont | 0:8024c367e29f | 449 | */ |
emilmont | 0:8024c367e29f | 450 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) |
emilmont | 0:8024c367e29f | 451 | { |
emilmont | 0:8024c367e29f | 452 | uint8_t result; |
emilmont | 0:8024c367e29f | 453 | |
emilmont | 0:8024c367e29f | 454 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
emilmont | 0:8024c367e29f | 455 | return(result); |
emilmont | 0:8024c367e29f | 456 | } |
emilmont | 0:8024c367e29f | 457 | |
emilmont | 0:8024c367e29f | 458 | |
emilmont | 0:8024c367e29f | 459 | /** \brief LDR Exclusive (16 bit) |
emilmont | 0:8024c367e29f | 460 | |
emilmont | 0:8024c367e29f | 461 | This function performs a exclusive LDR command for 16 bit values. |
emilmont | 0:8024c367e29f | 462 | |
emilmont | 0:8024c367e29f | 463 | \param [in] ptr Pointer to data |
emilmont | 0:8024c367e29f | 464 | \return value of type uint16_t at (*ptr) |
emilmont | 0:8024c367e29f | 465 | */ |
emilmont | 0:8024c367e29f | 466 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) |
emilmont | 0:8024c367e29f | 467 | { |
emilmont | 0:8024c367e29f | 468 | uint16_t result; |
emilmont | 0:8024c367e29f | 469 | |
emilmont | 0:8024c367e29f | 470 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
emilmont | 0:8024c367e29f | 471 | return(result); |
emilmont | 0:8024c367e29f | 472 | } |
emilmont | 0:8024c367e29f | 473 | |
emilmont | 0:8024c367e29f | 474 | |
emilmont | 0:8024c367e29f | 475 | /** \brief LDR Exclusive (32 bit) |
emilmont | 0:8024c367e29f | 476 | |
emilmont | 0:8024c367e29f | 477 | This function performs a exclusive LDR command for 32 bit values. |
emilmont | 0:8024c367e29f | 478 | |
emilmont | 0:8024c367e29f | 479 | \param [in] ptr Pointer to data |
emilmont | 0:8024c367e29f | 480 | \return value of type uint32_t at (*ptr) |
emilmont | 0:8024c367e29f | 481 | */ |
emilmont | 0:8024c367e29f | 482 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) |
emilmont | 0:8024c367e29f | 483 | { |
emilmont | 0:8024c367e29f | 484 | uint32_t result; |
emilmont | 0:8024c367e29f | 485 | |
emilmont | 0:8024c367e29f | 486 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
emilmont | 0:8024c367e29f | 487 | return(result); |
emilmont | 0:8024c367e29f | 488 | } |
emilmont | 0:8024c367e29f | 489 | |
emilmont | 0:8024c367e29f | 490 | |
emilmont | 0:8024c367e29f | 491 | /** \brief STR Exclusive (8 bit) |
emilmont | 0:8024c367e29f | 492 | |
emilmont | 0:8024c367e29f | 493 | This function performs a exclusive STR command for 8 bit values. |
emilmont | 0:8024c367e29f | 494 | |
emilmont | 0:8024c367e29f | 495 | \param [in] value Value to store |
emilmont | 0:8024c367e29f | 496 | \param [in] ptr Pointer to location |
emilmont | 0:8024c367e29f | 497 | \return 0 Function succeeded |
emilmont | 0:8024c367e29f | 498 | \return 1 Function failed |
emilmont | 0:8024c367e29f | 499 | */ |
emilmont | 0:8024c367e29f | 500 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) |
emilmont | 0:8024c367e29f | 501 | { |
emilmont | 0:8024c367e29f | 502 | uint32_t result; |
emilmont | 0:8024c367e29f | 503 | |
emilmont | 0:8024c367e29f | 504 | __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
emilmont | 0:8024c367e29f | 505 | return(result); |
emilmont | 0:8024c367e29f | 506 | } |
emilmont | 0:8024c367e29f | 507 | |
emilmont | 0:8024c367e29f | 508 | |
emilmont | 0:8024c367e29f | 509 | /** \brief STR Exclusive (16 bit) |
emilmont | 0:8024c367e29f | 510 | |
emilmont | 0:8024c367e29f | 511 | This function performs a exclusive STR command for 16 bit values. |
emilmont | 0:8024c367e29f | 512 | |
emilmont | 0:8024c367e29f | 513 | \param [in] value Value to store |
emilmont | 0:8024c367e29f | 514 | \param [in] ptr Pointer to location |
emilmont | 0:8024c367e29f | 515 | \return 0 Function succeeded |
emilmont | 0:8024c367e29f | 516 | \return 1 Function failed |
emilmont | 0:8024c367e29f | 517 | */ |
emilmont | 0:8024c367e29f | 518 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) |
emilmont | 0:8024c367e29f | 519 | { |
emilmont | 0:8024c367e29f | 520 | uint32_t result; |
emilmont | 0:8024c367e29f | 521 | |
emilmont | 0:8024c367e29f | 522 | __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
emilmont | 0:8024c367e29f | 523 | return(result); |
emilmont | 0:8024c367e29f | 524 | } |
emilmont | 0:8024c367e29f | 525 | |
emilmont | 0:8024c367e29f | 526 | |
emilmont | 0:8024c367e29f | 527 | /** \brief STR Exclusive (32 bit) |
emilmont | 0:8024c367e29f | 528 | |
emilmont | 0:8024c367e29f | 529 | This function performs a exclusive STR command for 32 bit values. |
emilmont | 0:8024c367e29f | 530 | |
emilmont | 0:8024c367e29f | 531 | \param [in] value Value to store |
emilmont | 0:8024c367e29f | 532 | \param [in] ptr Pointer to location |
emilmont | 0:8024c367e29f | 533 | \return 0 Function succeeded |
emilmont | 0:8024c367e29f | 534 | \return 1 Function failed |
emilmont | 0:8024c367e29f | 535 | */ |
emilmont | 0:8024c367e29f | 536 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) |
emilmont | 0:8024c367e29f | 537 | { |
emilmont | 0:8024c367e29f | 538 | uint32_t result; |
emilmont | 0:8024c367e29f | 539 | |
emilmont | 0:8024c367e29f | 540 | __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
emilmont | 0:8024c367e29f | 541 | return(result); |
emilmont | 0:8024c367e29f | 542 | } |
emilmont | 0:8024c367e29f | 543 | |
emilmont | 0:8024c367e29f | 544 | |
emilmont | 0:8024c367e29f | 545 | /** \brief Remove the exclusive lock |
emilmont | 0:8024c367e29f | 546 | |
emilmont | 0:8024c367e29f | 547 | This function removes the exclusive lock which is created by LDREX. |
emilmont | 0:8024c367e29f | 548 | |
emilmont | 0:8024c367e29f | 549 | */ |
emilmont | 0:8024c367e29f | 550 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) |
emilmont | 0:8024c367e29f | 551 | { |
emilmont | 0:8024c367e29f | 552 | __ASM volatile ("clrex"); |
emilmont | 0:8024c367e29f | 553 | } |
emilmont | 0:8024c367e29f | 554 | |
emilmont | 0:8024c367e29f | 555 | |
emilmont | 0:8024c367e29f | 556 | /** \brief Signed Saturate |
emilmont | 0:8024c367e29f | 557 | |
emilmont | 0:8024c367e29f | 558 | This function saturates a signed value. |
emilmont | 0:8024c367e29f | 559 | |
emilmont | 0:8024c367e29f | 560 | \param [in] value Value to be saturated |
emilmont | 0:8024c367e29f | 561 | \param [in] sat Bit position to saturate to (1..32) |
emilmont | 0:8024c367e29f | 562 | \return Saturated value |
emilmont | 0:8024c367e29f | 563 | */ |
emilmont | 0:8024c367e29f | 564 | #define __SSAT(ARG1,ARG2) \ |
emilmont | 0:8024c367e29f | 565 | ({ \ |
emilmont | 0:8024c367e29f | 566 | uint32_t __RES, __ARG1 = (ARG1); \ |
emilmont | 0:8024c367e29f | 567 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
emilmont | 0:8024c367e29f | 568 | __RES; \ |
emilmont | 0:8024c367e29f | 569 | }) |
emilmont | 0:8024c367e29f | 570 | |
emilmont | 0:8024c367e29f | 571 | |
emilmont | 0:8024c367e29f | 572 | /** \brief Unsigned Saturate |
emilmont | 0:8024c367e29f | 573 | |
emilmont | 0:8024c367e29f | 574 | This function saturates an unsigned value. |
emilmont | 0:8024c367e29f | 575 | |
emilmont | 0:8024c367e29f | 576 | \param [in] value Value to be saturated |
emilmont | 0:8024c367e29f | 577 | \param [in] sat Bit position to saturate to (0..31) |
emilmont | 0:8024c367e29f | 578 | \return Saturated value |
emilmont | 0:8024c367e29f | 579 | */ |
emilmont | 0:8024c367e29f | 580 | #define __USAT(ARG1,ARG2) \ |
emilmont | 0:8024c367e29f | 581 | ({ \ |
emilmont | 0:8024c367e29f | 582 | uint32_t __RES, __ARG1 = (ARG1); \ |
emilmont | 0:8024c367e29f | 583 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
emilmont | 0:8024c367e29f | 584 | __RES; \ |
emilmont | 0:8024c367e29f | 585 | }) |
emilmont | 0:8024c367e29f | 586 | |
emilmont | 0:8024c367e29f | 587 | |
emilmont | 0:8024c367e29f | 588 | /** \brief Count leading zeros |
emilmont | 0:8024c367e29f | 589 | |
emilmont | 0:8024c367e29f | 590 | This function counts the number of leading zeros of a data value. |
emilmont | 0:8024c367e29f | 591 | |
emilmont | 0:8024c367e29f | 592 | \param [in] value Value to count the leading zeros |
emilmont | 0:8024c367e29f | 593 | \return number of leading zeros in value |
emilmont | 0:8024c367e29f | 594 | */ |
emilmont | 0:8024c367e29f | 595 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) |
emilmont | 0:8024c367e29f | 596 | { |
emilmont | 0:8024c367e29f | 597 | uint8_t result; |
emilmont | 0:8024c367e29f | 598 | |
emilmont | 0:8024c367e29f | 599 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); |
emilmont | 0:8024c367e29f | 600 | return(result); |
emilmont | 0:8024c367e29f | 601 | } |
emilmont | 0:8024c367e29f | 602 | |
emilmont | 0:8024c367e29f | 603 | #endif /* (__CORTEX_M >= 0x03) */ |
emilmont | 0:8024c367e29f | 604 | |
emilmont | 0:8024c367e29f | 605 | |
emilmont | 0:8024c367e29f | 606 | |
emilmont | 0:8024c367e29f | 607 | |
emilmont | 0:8024c367e29f | 608 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ |
emilmont | 0:8024c367e29f | 609 | /* TASKING carm specific functions */ |
emilmont | 0:8024c367e29f | 610 | |
emilmont | 0:8024c367e29f | 611 | /* |
emilmont | 0:8024c367e29f | 612 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
emilmont | 0:8024c367e29f | 613 | * Please use "carm -?i" to get an up to date list of all intrinsics, |
emilmont | 0:8024c367e29f | 614 | * Including the CMSIS ones. |
emilmont | 0:8024c367e29f | 615 | */ |
emilmont | 0:8024c367e29f | 616 | |
emilmont | 0:8024c367e29f | 617 | #endif |
emilmont | 0:8024c367e29f | 618 | |
emilmont | 0:8024c367e29f | 619 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
emilmont | 0:8024c367e29f | 620 | |
emilmont | 0:8024c367e29f | 621 | #endif /* __CORE_CMINSTR_H */ |