Emilio Monti / mbed-KL25Z

mbed libraries for KL25Z

Dependents:   FRDM_RGBLED

KL25Z/core_cmInstr.h@2:e9a661555b58, 2012-10-10 (annotated)

Committer:
emilmont
Date:
Wed Oct 10 14:14:12 2012 +0000
Revision:
2:e9a661555b58
Parent:
0:8024c367e29f
Child:
9:663789d7729f
Add PWM and I2C implementation;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 2:e9a661555b58 1 /**************************************************************************//**
emilmont 2:e9a661555b58 2 * @file core_cmInstr.h
emilmont 2:e9a661555b58 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 2:e9a661555b58 4 * @version V3.02
emilmont 2:e9a661555b58 5 * @date 08. May 2012
emilmont 2:e9a661555b58 6 *
emilmont 2:e9a661555b58 7 * @note
emilmont 2:e9a661555b58 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 2:e9a661555b58 9 *
emilmont 2:e9a661555b58 10 * @par
emilmont 2:e9a661555b58 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 2:e9a661555b58 12 * processor based microcontrollers. This file can be freely distributed
emilmont 2:e9a661555b58 13 * within development tools that are supporting such ARM based processors.
emilmont 2:e9a661555b58 14 *
emilmont 2:e9a661555b58 15 * @par
emilmont 2:e9a661555b58 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 2:e9a661555b58 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 2:e9a661555b58 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 2:e9a661555b58 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 2:e9a661555b58 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 2:e9a661555b58 21 *
emilmont 2:e9a661555b58 22 ******************************************************************************/
emilmont 2:e9a661555b58 23
emilmont 2:e9a661555b58 24 #ifndef __CORE_CMINSTR_H
emilmont 2:e9a661555b58 25 #define __CORE_CMINSTR_H
emilmont 2:e9a661555b58 26
emilmont 2:e9a661555b58 27
emilmont 2:e9a661555b58 28 /* ########################## Core Instruction Access ######################### */
emilmont 2:e9a661555b58 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 2:e9a661555b58 30 Access to dedicated instructions
emilmont 2:e9a661555b58 31 @{
emilmont 2:e9a661555b58 32 */
emilmont 2:e9a661555b58 33
emilmont 2:e9a661555b58 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 2:e9a661555b58 35 /* ARM armcc specific functions */
emilmont 2:e9a661555b58 36
emilmont 2:e9a661555b58 37 #if (__ARMCC_VERSION < 400677)
emilmont 2:e9a661555b58 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 2:e9a661555b58 39 #endif
emilmont 2:e9a661555b58 40
emilmont 2:e9a661555b58 41
emilmont 2:e9a661555b58 42 /** \brief No Operation
emilmont 2:e9a661555b58 43
emilmont 2:e9a661555b58 44 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 2:e9a661555b58 45 */
emilmont 2:e9a661555b58 46 #define __NOP __nop
emilmont 2:e9a661555b58 47
emilmont 2:e9a661555b58 48
emilmont 2:e9a661555b58 49 /** \brief Wait For Interrupt
emilmont 2:e9a661555b58 50
emilmont 2:e9a661555b58 51 Wait For Interrupt is a hint instruction that suspends execution
emilmont 2:e9a661555b58 52 until one of a number of events occurs.
emilmont 2:e9a661555b58 53 */
emilmont 2:e9a661555b58 54 #define __WFI __wfi
emilmont 2:e9a661555b58 55
emilmont 2:e9a661555b58 56
emilmont 2:e9a661555b58 57 /** \brief Wait For Event
emilmont 2:e9a661555b58 58
emilmont 2:e9a661555b58 59 Wait For Event is a hint instruction that permits the processor to enter
emilmont 2:e9a661555b58 60 a low-power state until one of a number of events occurs.
emilmont 2:e9a661555b58 61 */
emilmont 2:e9a661555b58 62 #define __WFE __wfe
emilmont 2:e9a661555b58 63
emilmont 2:e9a661555b58 64
emilmont 2:e9a661555b58 65 /** \brief Send Event
emilmont 2:e9a661555b58 66
emilmont 2:e9a661555b58 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 2:e9a661555b58 68 */
emilmont 2:e9a661555b58 69 #define __SEV __sev
emilmont 2:e9a661555b58 70
emilmont 2:e9a661555b58 71
emilmont 2:e9a661555b58 72 /** \brief Instruction Synchronization Barrier
emilmont 2:e9a661555b58 73
emilmont 2:e9a661555b58 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 2:e9a661555b58 75 so that all instructions following the ISB are fetched from cache or
emilmont 2:e9a661555b58 76 memory, after the instruction has been completed.
emilmont 2:e9a661555b58 77 */
emilmont 2:e9a661555b58 78 #define __ISB() __isb(0xF)
emilmont 2:e9a661555b58 79
emilmont 2:e9a661555b58 80
emilmont 2:e9a661555b58 81 /** \brief Data Synchronization Barrier
emilmont 2:e9a661555b58 82
emilmont 2:e9a661555b58 83 This function acts as a special kind of Data Memory Barrier.
emilmont 2:e9a661555b58 84 It completes when all explicit memory accesses before this instruction complete.
emilmont 2:e9a661555b58 85 */
emilmont 2:e9a661555b58 86 #define __DSB() __dsb(0xF)
emilmont 2:e9a661555b58 87
emilmont 2:e9a661555b58 88
emilmont 2:e9a661555b58 89 /** \brief Data Memory Barrier
emilmont 2:e9a661555b58 90
emilmont 2:e9a661555b58 91 This function ensures the apparent order of the explicit memory operations before
emilmont 2:e9a661555b58 92 and after the instruction, without ensuring their completion.
emilmont 2:e9a661555b58 93 */
emilmont 2:e9a661555b58 94 #define __DMB() __dmb(0xF)
emilmont 2:e9a661555b58 95
emilmont 2:e9a661555b58 96
emilmont 2:e9a661555b58 97 /** \brief Reverse byte order (32 bit)
emilmont 2:e9a661555b58 98
emilmont 2:e9a661555b58 99 This function reverses the byte order in integer value.
emilmont 2:e9a661555b58 100
emilmont 2:e9a661555b58 101 \param [in] value Value to reverse
emilmont 2:e9a661555b58 102 \return Reversed value
emilmont 2:e9a661555b58 103 */
emilmont 2:e9a661555b58 104 #define __REV __rev
emilmont 2:e9a661555b58 105
emilmont 2:e9a661555b58 106
emilmont 2:e9a661555b58 107 /** \brief Reverse byte order (16 bit)
emilmont 2:e9a661555b58 108
emilmont 2:e9a661555b58 109 This function reverses the byte order in two unsigned short values.
emilmont 2:e9a661555b58 110
emilmont 2:e9a661555b58 111 \param [in] value Value to reverse
emilmont 2:e9a661555b58 112 \return Reversed value
emilmont 2:e9a661555b58 113 */
emilmont 2:e9a661555b58 114 #ifndef __NO_EMBEDDED_ASM
emilmont 2:e9a661555b58 115 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 2:e9a661555b58 116 {
emilmont 2:e9a661555b58 117 rev16 r0, r0
emilmont 2:e9a661555b58 118 bx lr
emilmont 2:e9a661555b58 119 }
emilmont 2:e9a661555b58 120 #endif
emilmont 2:e9a661555b58 121
emilmont 2:e9a661555b58 122 /** \brief Reverse byte order in signed short value
emilmont 2:e9a661555b58 123
emilmont 2:e9a661555b58 124 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 2:e9a661555b58 125
emilmont 2:e9a661555b58 126 \param [in] value Value to reverse
emilmont 2:e9a661555b58 127 \return Reversed value
emilmont 2:e9a661555b58 128 */
emilmont 2:e9a661555b58 129 #ifndef __NO_EMBEDDED_ASM
emilmont 2:e9a661555b58 130 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 2:e9a661555b58 131 {
emilmont 2:e9a661555b58 132 revsh r0, r0
emilmont 2:e9a661555b58 133 bx lr
emilmont 2:e9a661555b58 134 }
emilmont 2:e9a661555b58 135 #endif
emilmont 2:e9a661555b58 136
emilmont 2:e9a661555b58 137
emilmont 2:e9a661555b58 138 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 2:e9a661555b58 139
emilmont 2:e9a661555b58 140 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 2:e9a661555b58 141
emilmont 2:e9a661555b58 142 \param [in] value Value to rotate
emilmont 2:e9a661555b58 143 \param [in] value Number of Bits to rotate
emilmont 2:e9a661555b58 144 \return Rotated value
emilmont 2:e9a661555b58 145 */
emilmont 2:e9a661555b58 146 #define __ROR __ror
emilmont 2:e9a661555b58 147
emilmont 2:e9a661555b58 148
emilmont 2:e9a661555b58 149 #if (__CORTEX_M >= 0x03)
emilmont 2:e9a661555b58 150
emilmont 2:e9a661555b58 151 /** \brief Reverse bit order of value
emilmont 2:e9a661555b58 152
emilmont 2:e9a661555b58 153 This function reverses the bit order of the given value.
emilmont 2:e9a661555b58 154
emilmont 2:e9a661555b58 155 \param [in] value Value to reverse
emilmont 2:e9a661555b58 156 \return Reversed value
emilmont 2:e9a661555b58 157 */
emilmont 2:e9a661555b58 158 #define __RBIT __rbit
emilmont 2:e9a661555b58 159
emilmont 2:e9a661555b58 160
emilmont 2:e9a661555b58 161 /** \brief LDR Exclusive (8 bit)
emilmont 2:e9a661555b58 162
emilmont 2:e9a661555b58 163 This function performs a exclusive LDR command for 8 bit value.
emilmont 2:e9a661555b58 164
emilmont 2:e9a661555b58 165 \param [in] ptr Pointer to data
emilmont 2:e9a661555b58 166 \return value of type uint8_t at (*ptr)
emilmont 2:e9a661555b58 167 */
emilmont 2:e9a661555b58 168 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 2:e9a661555b58 169
emilmont 2:e9a661555b58 170
emilmont 2:e9a661555b58 171 /** \brief LDR Exclusive (16 bit)
emilmont 2:e9a661555b58 172
emilmont 2:e9a661555b58 173 This function performs a exclusive LDR command for 16 bit values.
emilmont 2:e9a661555b58 174
emilmont 2:e9a661555b58 175 \param [in] ptr Pointer to data
emilmont 2:e9a661555b58 176 \return value of type uint16_t at (*ptr)
emilmont 2:e9a661555b58 177 */
emilmont 2:e9a661555b58 178 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 2:e9a661555b58 179
emilmont 2:e9a661555b58 180
emilmont 2:e9a661555b58 181 /** \brief LDR Exclusive (32 bit)
emilmont 2:e9a661555b58 182
emilmont 2:e9a661555b58 183 This function performs a exclusive LDR command for 32 bit values.
emilmont 2:e9a661555b58 184
emilmont 2:e9a661555b58 185 \param [in] ptr Pointer to data
emilmont 2:e9a661555b58 186 \return value of type uint32_t at (*ptr)
emilmont 2:e9a661555b58 187 */
emilmont 2:e9a661555b58 188 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 2:e9a661555b58 189
emilmont 2:e9a661555b58 190
emilmont 2:e9a661555b58 191 /** \brief STR Exclusive (8 bit)
emilmont 2:e9a661555b58 192
emilmont 2:e9a661555b58 193 This function performs a exclusive STR command for 8 bit values.
emilmont 2:e9a661555b58 194
emilmont 2:e9a661555b58 195 \param [in] value Value to store
emilmont 2:e9a661555b58 196 \param [in] ptr Pointer to location
emilmont 2:e9a661555b58 197 \return 0 Function succeeded
emilmont 2:e9a661555b58 198 \return 1 Function failed
emilmont 2:e9a661555b58 199 */
emilmont 2:e9a661555b58 200 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 2:e9a661555b58 201
emilmont 2:e9a661555b58 202
emilmont 2:e9a661555b58 203 /** \brief STR Exclusive (16 bit)
emilmont 2:e9a661555b58 204
emilmont 2:e9a661555b58 205 This function performs a exclusive STR command for 16 bit values.
emilmont 2:e9a661555b58 206
emilmont 2:e9a661555b58 207 \param [in] value Value to store
emilmont 2:e9a661555b58 208 \param [in] ptr Pointer to location
emilmont 2:e9a661555b58 209 \return 0 Function succeeded
emilmont 2:e9a661555b58 210 \return 1 Function failed
emilmont 2:e9a661555b58 211 */
emilmont 2:e9a661555b58 212 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 2:e9a661555b58 213
emilmont 2:e9a661555b58 214
emilmont 2:e9a661555b58 215 /** \brief STR Exclusive (32 bit)
emilmont 2:e9a661555b58 216
emilmont 2:e9a661555b58 217 This function performs a exclusive STR command for 32 bit values.
emilmont 2:e9a661555b58 218
emilmont 2:e9a661555b58 219 \param [in] value Value to store
emilmont 2:e9a661555b58 220 \param [in] ptr Pointer to location
emilmont 2:e9a661555b58 221 \return 0 Function succeeded
emilmont 2:e9a661555b58 222 \return 1 Function failed
emilmont 2:e9a661555b58 223 */
emilmont 2:e9a661555b58 224 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 2:e9a661555b58 225
emilmont 2:e9a661555b58 226
emilmont 2:e9a661555b58 227 /** \brief Remove the exclusive lock
emilmont 2:e9a661555b58 228
emilmont 2:e9a661555b58 229 This function removes the exclusive lock which is created by LDREX.
emilmont 2:e9a661555b58 230
emilmont 2:e9a661555b58 231 */
emilmont 2:e9a661555b58 232 #define __CLREX __clrex
emilmont 2:e9a661555b58 233
emilmont 2:e9a661555b58 234
emilmont 2:e9a661555b58 235 /** \brief Signed Saturate
emilmont 2:e9a661555b58 236
emilmont 2:e9a661555b58 237 This function saturates a signed value.
emilmont 2:e9a661555b58 238
emilmont 2:e9a661555b58 239 \param [in] value Value to be saturated
emilmont 2:e9a661555b58 240 \param [in] sat Bit position to saturate to (1..32)
emilmont 2:e9a661555b58 241 \return Saturated value
emilmont 2:e9a661555b58 242 */
emilmont 2:e9a661555b58 243 #define __SSAT __ssat
emilmont 2:e9a661555b58 244
emilmont 2:e9a661555b58 245
emilmont 2:e9a661555b58 246 /** \brief Unsigned Saturate
emilmont 2:e9a661555b58 247
emilmont 2:e9a661555b58 248 This function saturates an unsigned value.
emilmont 2:e9a661555b58 249
emilmont 2:e9a661555b58 250 \param [in] value Value to be saturated
emilmont 2:e9a661555b58 251 \param [in] sat Bit position to saturate to (0..31)
emilmont 2:e9a661555b58 252 \return Saturated value
emilmont 2:e9a661555b58 253 */
emilmont 2:e9a661555b58 254 #define __USAT __usat
emilmont 2:e9a661555b58 255
emilmont 2:e9a661555b58 256
emilmont 2:e9a661555b58 257 /** \brief Count leading zeros
emilmont 2:e9a661555b58 258
emilmont 2:e9a661555b58 259 This function counts the number of leading zeros of a data value.
emilmont 2:e9a661555b58 260
emilmont 2:e9a661555b58 261 \param [in] value Value to count the leading zeros
emilmont 2:e9a661555b58 262 \return number of leading zeros in value
emilmont 2:e9a661555b58 263 */
emilmont 2:e9a661555b58 264 #define __CLZ __clz
emilmont 2:e9a661555b58 265
emilmont 2:e9a661555b58 266 #endif /* (__CORTEX_M >= 0x03) */
emilmont 2:e9a661555b58 267
emilmont 2:e9a661555b58 268
emilmont 2:e9a661555b58 269
emilmont 2:e9a661555b58 270 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 2:e9a661555b58 271 /* IAR iccarm specific functions */
emilmont 2:e9a661555b58 272
emilmont 2:e9a661555b58 273 #include <cmsis_iar.h>
emilmont 2:e9a661555b58 274
emilmont 2:e9a661555b58 275
emilmont 2:e9a661555b58 276 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 2:e9a661555b58 277 /* TI CCS specific functions */
emilmont 2:e9a661555b58 278
emilmont 2:e9a661555b58 279 #include <cmsis_ccs.h>
emilmont 2:e9a661555b58 280
emilmont 2:e9a661555b58 281
emilmont 2:e9a661555b58 282 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 2:e9a661555b58 283 /* GNU gcc specific functions */
emilmont 2:e9a661555b58 284
emilmont 2:e9a661555b58 285 /** \brief No Operation
emilmont 2:e9a661555b58 286
emilmont 2:e9a661555b58 287 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 2:e9a661555b58 288 */
emilmont 2:e9a661555b58 289 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
emilmont 2:e9a661555b58 290 {
emilmont 2:e9a661555b58 291 __ASM volatile ("nop");
emilmont 2:e9a661555b58 292 }
emilmont 2:e9a661555b58 293
emilmont 2:e9a661555b58 294
emilmont 2:e9a661555b58 295 /** \brief Wait For Interrupt
emilmont 2:e9a661555b58 296
emilmont 2:e9a661555b58 297 Wait For Interrupt is a hint instruction that suspends execution
emilmont 2:e9a661555b58 298 until one of a number of events occurs.
emilmont 2:e9a661555b58 299 */
emilmont 2:e9a661555b58 300 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
emilmont 2:e9a661555b58 301 {
emilmont 2:e9a661555b58 302 __ASM volatile ("wfi");
emilmont 2:e9a661555b58 303 }
emilmont 2:e9a661555b58 304
emilmont 2:e9a661555b58 305
emilmont 2:e9a661555b58 306 /** \brief Wait For Event
emilmont 2:e9a661555b58 307
emilmont 2:e9a661555b58 308 Wait For Event is a hint instruction that permits the processor to enter
emilmont 2:e9a661555b58 309 a low-power state until one of a number of events occurs.
emilmont 2:e9a661555b58 310 */
emilmont 2:e9a661555b58 311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
emilmont 2:e9a661555b58 312 {
emilmont 2:e9a661555b58 313 __ASM volatile ("wfe");
emilmont 2:e9a661555b58 314 }
emilmont 2:e9a661555b58 315
emilmont 2:e9a661555b58 316
emilmont 2:e9a661555b58 317 /** \brief Send Event
emilmont 2:e9a661555b58 318
emilmont 2:e9a661555b58 319 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 2:e9a661555b58 320 */
emilmont 2:e9a661555b58 321 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
emilmont 2:e9a661555b58 322 {
emilmont 2:e9a661555b58 323 __ASM volatile ("sev");
emilmont 2:e9a661555b58 324 }
emilmont 2:e9a661555b58 325
emilmont 2:e9a661555b58 326
emilmont 2:e9a661555b58 327 /** \brief Instruction Synchronization Barrier
emilmont 2:e9a661555b58 328
emilmont 2:e9a661555b58 329 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 2:e9a661555b58 330 so that all instructions following the ISB are fetched from cache or
emilmont 2:e9a661555b58 331 memory, after the instruction has been completed.
emilmont 2:e9a661555b58 332 */
emilmont 2:e9a661555b58 333 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
emilmont 2:e9a661555b58 334 {
emilmont 2:e9a661555b58 335 __ASM volatile ("isb");
emilmont 2:e9a661555b58 336 }
emilmont 2:e9a661555b58 337
emilmont 2:e9a661555b58 338
emilmont 2:e9a661555b58 339 /** \brief Data Synchronization Barrier
emilmont 2:e9a661555b58 340
emilmont 2:e9a661555b58 341 This function acts as a special kind of Data Memory Barrier.
emilmont 2:e9a661555b58 342 It completes when all explicit memory accesses before this instruction complete.
emilmont 2:e9a661555b58 343 */
emilmont 2:e9a661555b58 344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
emilmont 2:e9a661555b58 345 {
emilmont 2:e9a661555b58 346 __ASM volatile ("dsb");
emilmont 2:e9a661555b58 347 }
emilmont 2:e9a661555b58 348
emilmont 2:e9a661555b58 349
emilmont 2:e9a661555b58 350 /** \brief Data Memory Barrier
emilmont 2:e9a661555b58 351
emilmont 2:e9a661555b58 352 This function ensures the apparent order of the explicit memory operations before
emilmont 2:e9a661555b58 353 and after the instruction, without ensuring their completion.
emilmont 2:e9a661555b58 354 */
emilmont 2:e9a661555b58 355 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
emilmont 2:e9a661555b58 356 {
emilmont 2:e9a661555b58 357 __ASM volatile ("dmb");
emilmont 2:e9a661555b58 358 }
emilmont 2:e9a661555b58 359
emilmont 2:e9a661555b58 360
emilmont 2:e9a661555b58 361 /** \brief Reverse byte order (32 bit)
emilmont 2:e9a661555b58 362
emilmont 2:e9a661555b58 363 This function reverses the byte order in integer value.
emilmont 2:e9a661555b58 364
emilmont 2:e9a661555b58 365 \param [in] value Value to reverse
emilmont 2:e9a661555b58 366 \return Reversed value
emilmont 2:e9a661555b58 367 */
emilmont 2:e9a661555b58 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 2:e9a661555b58 369 {
emilmont 2:e9a661555b58 370 uint32_t result;
emilmont 2:e9a661555b58 371
emilmont 2:e9a661555b58 372 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
emilmont 2:e9a661555b58 373 return(result);
emilmont 2:e9a661555b58 374 }
emilmont 2:e9a661555b58 375
emilmont 2:e9a661555b58 376
emilmont 2:e9a661555b58 377 /** \brief Reverse byte order (16 bit)
emilmont 2:e9a661555b58 378
emilmont 2:e9a661555b58 379 This function reverses the byte order in two unsigned short values.
emilmont 2:e9a661555b58 380
emilmont 2:e9a661555b58 381 \param [in] value Value to reverse
emilmont 2:e9a661555b58 382 \return Reversed value
emilmont 2:e9a661555b58 383 */
emilmont 2:e9a661555b58 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 2:e9a661555b58 385 {
emilmont 2:e9a661555b58 386 uint32_t result;
emilmont 2:e9a661555b58 387
emilmont 2:e9a661555b58 388 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
emilmont 2:e9a661555b58 389 return(result);
emilmont 2:e9a661555b58 390 }
emilmont 2:e9a661555b58 391
emilmont 2:e9a661555b58 392
emilmont 2:e9a661555b58 393 /** \brief Reverse byte order in signed short value
emilmont 2:e9a661555b58 394
emilmont 2:e9a661555b58 395 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 2:e9a661555b58 396
emilmont 2:e9a661555b58 397 \param [in] value Value to reverse
emilmont 2:e9a661555b58 398 \return Reversed value
emilmont 2:e9a661555b58 399 */
emilmont 2:e9a661555b58 400 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 2:e9a661555b58 401 {
emilmont 2:e9a661555b58 402 uint32_t result;
emilmont 2:e9a661555b58 403
emilmont 2:e9a661555b58 404 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
emilmont 2:e9a661555b58 405 return(result);
emilmont 2:e9a661555b58 406 }
emilmont 2:e9a661555b58 407
emilmont 2:e9a661555b58 408
emilmont 2:e9a661555b58 409 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 2:e9a661555b58 410
emilmont 2:e9a661555b58 411 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 2:e9a661555b58 412
emilmont 2:e9a661555b58 413 \param [in] value Value to rotate
emilmont 2:e9a661555b58 414 \param [in] value Number of Bits to rotate
emilmont 2:e9a661555b58 415 \return Rotated value
emilmont 2:e9a661555b58 416 */
emilmont 2:e9a661555b58 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emilmont 2:e9a661555b58 418 {
emilmont 2:e9a661555b58 419
emilmont 2:e9a661555b58 420 __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
emilmont 2:e9a661555b58 421 return(op1);
emilmont 2:e9a661555b58 422 }
emilmont 2:e9a661555b58 423
emilmont 2:e9a661555b58 424
emilmont 2:e9a661555b58 425 #if (__CORTEX_M >= 0x03)
emilmont 2:e9a661555b58 426
emilmont 2:e9a661555b58 427 /** \brief Reverse bit order of value
emilmont 2:e9a661555b58 428
emilmont 2:e9a661555b58 429 This function reverses the bit order of the given value.
emilmont 2:e9a661555b58 430
emilmont 2:e9a661555b58 431 \param [in] value Value to reverse
emilmont 2:e9a661555b58 432 \return Reversed value
emilmont 2:e9a661555b58 433 */
emilmont 2:e9a661555b58 434 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 2:e9a661555b58 435 {
emilmont 2:e9a661555b58 436 uint32_t result;
emilmont 2:e9a661555b58 437
emilmont 2:e9a661555b58 438 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 2:e9a661555b58 439 return(result);
emilmont 2:e9a661555b58 440 }
emilmont 2:e9a661555b58 441
emilmont 2:e9a661555b58 442
emilmont 2:e9a661555b58 443 /** \brief LDR Exclusive (8 bit)
emilmont 2:e9a661555b58 444
emilmont 2:e9a661555b58 445 This function performs a exclusive LDR command for 8 bit value.
emilmont 2:e9a661555b58 446
emilmont 2:e9a661555b58 447 \param [in] ptr Pointer to data
emilmont 2:e9a661555b58 448 \return value of type uint8_t at (*ptr)
emilmont 2:e9a661555b58 449 */
emilmont 2:e9a661555b58 450 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 2:e9a661555b58 451 {
emilmont 2:e9a661555b58 452 uint8_t result;
emilmont 2:e9a661555b58 453
emilmont 2:e9a661555b58 454 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 2:e9a661555b58 455 return(result);
emilmont 2:e9a661555b58 456 }
emilmont 2:e9a661555b58 457
emilmont 2:e9a661555b58 458
emilmont 2:e9a661555b58 459 /** \brief LDR Exclusive (16 bit)
emilmont 2:e9a661555b58 460
emilmont 2:e9a661555b58 461 This function performs a exclusive LDR command for 16 bit values.
emilmont 2:e9a661555b58 462
emilmont 2:e9a661555b58 463 \param [in] ptr Pointer to data
emilmont 2:e9a661555b58 464 \return value of type uint16_t at (*ptr)
emilmont 2:e9a661555b58 465 */
emilmont 2:e9a661555b58 466 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 2:e9a661555b58 467 {
emilmont 2:e9a661555b58 468 uint16_t result;
emilmont 2:e9a661555b58 469
emilmont 2:e9a661555b58 470 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 2:e9a661555b58 471 return(result);
emilmont 2:e9a661555b58 472 }
emilmont 2:e9a661555b58 473
emilmont 2:e9a661555b58 474
emilmont 2:e9a661555b58 475 /** \brief LDR Exclusive (32 bit)
emilmont 2:e9a661555b58 476
emilmont 2:e9a661555b58 477 This function performs a exclusive LDR command for 32 bit values.
emilmont 2:e9a661555b58 478
emilmont 2:e9a661555b58 479 \param [in] ptr Pointer to data
emilmont 2:e9a661555b58 480 \return value of type uint32_t at (*ptr)
emilmont 2:e9a661555b58 481 */
emilmont 2:e9a661555b58 482 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 2:e9a661555b58 483 {
emilmont 2:e9a661555b58 484 uint32_t result;
emilmont 2:e9a661555b58 485
emilmont 2:e9a661555b58 486 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 2:e9a661555b58 487 return(result);
emilmont 2:e9a661555b58 488 }
emilmont 2:e9a661555b58 489
emilmont 2:e9a661555b58 490
emilmont 2:e9a661555b58 491 /** \brief STR Exclusive (8 bit)
emilmont 2:e9a661555b58 492
emilmont 2:e9a661555b58 493 This function performs a exclusive STR command for 8 bit values.
emilmont 2:e9a661555b58 494
emilmont 2:e9a661555b58 495 \param [in] value Value to store
emilmont 2:e9a661555b58 496 \param [in] ptr Pointer to location
emilmont 2:e9a661555b58 497 \return 0 Function succeeded
emilmont 2:e9a661555b58 498 \return 1 Function failed
emilmont 2:e9a661555b58 499 */
emilmont 2:e9a661555b58 500 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 2:e9a661555b58 501 {
emilmont 2:e9a661555b58 502 uint32_t result;
emilmont 2:e9a661555b58 503
emilmont 2:e9a661555b58 504 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 2:e9a661555b58 505 return(result);
emilmont 2:e9a661555b58 506 }
emilmont 2:e9a661555b58 507
emilmont 2:e9a661555b58 508
emilmont 2:e9a661555b58 509 /** \brief STR Exclusive (16 bit)
emilmont 2:e9a661555b58 510
emilmont 2:e9a661555b58 511 This function performs a exclusive STR command for 16 bit values.
emilmont 2:e9a661555b58 512
emilmont 2:e9a661555b58 513 \param [in] value Value to store
emilmont 2:e9a661555b58 514 \param [in] ptr Pointer to location
emilmont 2:e9a661555b58 515 \return 0 Function succeeded
emilmont 2:e9a661555b58 516 \return 1 Function failed
emilmont 2:e9a661555b58 517 */
emilmont 2:e9a661555b58 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 2:e9a661555b58 519 {
emilmont 2:e9a661555b58 520 uint32_t result;
emilmont 2:e9a661555b58 521
emilmont 2:e9a661555b58 522 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 2:e9a661555b58 523 return(result);
emilmont 2:e9a661555b58 524 }
emilmont 2:e9a661555b58 525
emilmont 2:e9a661555b58 526
emilmont 2:e9a661555b58 527 /** \brief STR Exclusive (32 bit)
emilmont 2:e9a661555b58 528
emilmont 2:e9a661555b58 529 This function performs a exclusive STR command for 32 bit values.
emilmont 2:e9a661555b58 530
emilmont 2:e9a661555b58 531 \param [in] value Value to store
emilmont 2:e9a661555b58 532 \param [in] ptr Pointer to location
emilmont 2:e9a661555b58 533 \return 0 Function succeeded
emilmont 2:e9a661555b58 534 \return 1 Function failed
emilmont 2:e9a661555b58 535 */
emilmont 2:e9a661555b58 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 2:e9a661555b58 537 {
emilmont 2:e9a661555b58 538 uint32_t result;
emilmont 2:e9a661555b58 539
emilmont 2:e9a661555b58 540 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 2:e9a661555b58 541 return(result);
emilmont 2:e9a661555b58 542 }
emilmont 2:e9a661555b58 543
emilmont 2:e9a661555b58 544
emilmont 2:e9a661555b58 545 /** \brief Remove the exclusive lock
emilmont 2:e9a661555b58 546
emilmont 2:e9a661555b58 547 This function removes the exclusive lock which is created by LDREX.
emilmont 2:e9a661555b58 548
emilmont 2:e9a661555b58 549 */
emilmont 2:e9a661555b58 550 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
emilmont 2:e9a661555b58 551 {
emilmont 2:e9a661555b58 552 __ASM volatile ("clrex");
emilmont 2:e9a661555b58 553 }
emilmont 2:e9a661555b58 554
emilmont 2:e9a661555b58 555
emilmont 2:e9a661555b58 556 /** \brief Signed Saturate
emilmont 2:e9a661555b58 557
emilmont 2:e9a661555b58 558 This function saturates a signed value.
emilmont 2:e9a661555b58 559
emilmont 2:e9a661555b58 560 \param [in] value Value to be saturated
emilmont 2:e9a661555b58 561 \param [in] sat Bit position to saturate to (1..32)
emilmont 2:e9a661555b58 562 \return Saturated value
emilmont 2:e9a661555b58 563 */
emilmont 2:e9a661555b58 564 #define __SSAT(ARG1,ARG2) \
emilmont 2:e9a661555b58 565 ({ \
emilmont 2:e9a661555b58 566 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 2:e9a661555b58 567 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 2:e9a661555b58 568 __RES; \
emilmont 2:e9a661555b58 569 })
emilmont 2:e9a661555b58 570
emilmont 2:e9a661555b58 571
emilmont 2:e9a661555b58 572 /** \brief Unsigned Saturate
emilmont 2:e9a661555b58 573
emilmont 2:e9a661555b58 574 This function saturates an unsigned value.
emilmont 2:e9a661555b58 575
emilmont 2:e9a661555b58 576 \param [in] value Value to be saturated
emilmont 2:e9a661555b58 577 \param [in] sat Bit position to saturate to (0..31)
emilmont 2:e9a661555b58 578 \return Saturated value
emilmont 2:e9a661555b58 579 */
emilmont 2:e9a661555b58 580 #define __USAT(ARG1,ARG2) \
emilmont 2:e9a661555b58 581 ({ \
emilmont 2:e9a661555b58 582 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 2:e9a661555b58 583 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 2:e9a661555b58 584 __RES; \
emilmont 2:e9a661555b58 585 })
emilmont 2:e9a661555b58 586
emilmont 2:e9a661555b58 587
emilmont 2:e9a661555b58 588 /** \brief Count leading zeros
emilmont 2:e9a661555b58 589
emilmont 2:e9a661555b58 590 This function counts the number of leading zeros of a data value.
emilmont 2:e9a661555b58 591
emilmont 2:e9a661555b58 592 \param [in] value Value to count the leading zeros
emilmont 2:e9a661555b58 593 \return number of leading zeros in value
emilmont 2:e9a661555b58 594 */
emilmont 2:e9a661555b58 595 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
emilmont 2:e9a661555b58 596 {
emilmont 2:e9a661555b58 597 uint8_t result;
emilmont 2:e9a661555b58 598
emilmont 2:e9a661555b58 599 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 2:e9a661555b58 600 return(result);
emilmont 2:e9a661555b58 601 }
emilmont 2:e9a661555b58 602
emilmont 2:e9a661555b58 603 #endif /* (__CORTEX_M >= 0x03) */
emilmont 2:e9a661555b58 604
emilmont 2:e9a661555b58 605
emilmont 2:e9a661555b58 606
emilmont 2:e9a661555b58 607
emilmont 2:e9a661555b58 608 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 2:e9a661555b58 609 /* TASKING carm specific functions */
emilmont 2:e9a661555b58 610
emilmont 2:e9a661555b58 611 /*
emilmont 2:e9a661555b58 612 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 2:e9a661555b58 613 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 2:e9a661555b58 614 * Including the CMSIS ones.
emilmont 2:e9a661555b58 615 */
emilmont 2:e9a661555b58 616
emilmont 2:e9a661555b58 617 #endif
emilmont 2:e9a661555b58 618
emilmont 2:e9a661555b58 619 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 2:e9a661555b58 620
emilmont 2:e9a661555b58 621 #endif /* __CORE_CMINSTR_H */