sx1261/2 driver
Dependents: alarm_slave iq_sx126x sx126x_simple_TX_shield_2020a sx126x_simple_RX_shield_2020a ... more
Driver for SX1261 or SX1262
sx12xx.h@9:34f1f2bbe7b3, 2018-11-25 (annotated)
- Committer:
- Wayne Roberts
- Date:
- Sun Nov 25 15:06:59 2018 -0800
- Revision:
- 9:34f1f2bbe7b3
- Parent:
- 8:66d3e344d61c
- Child:
- 10:8905722dd5e6
define xtal trim registers
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Wayne Roberts |
1:497af0bd9e53 | 1 | #include "mbed.h" |
Wayne Roberts |
1:497af0bd9e53 | 2 | #ifndef SX126x_H |
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1:497af0bd9e53 | 3 | #define SX126x_H |
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1:497af0bd9e53 | 4 | |
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1:497af0bd9e53 | 5 | #define RC_TICKS_PER_MS 0.015625 /* 64KHz */ |
Wayne Roberts |
1:497af0bd9e53 | 6 | #define RC_TICKS_PER_US 15.625 /* 64KHz */ |
Wayne Roberts |
1:497af0bd9e53 | 7 | |
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2:e6e159c8ab4d | 8 | #define XTAL_FREQ_HZ 32000000 |
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1:497af0bd9e53 | 9 | #define FREQ_DIV 33554432 |
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1:497af0bd9e53 | 10 | #define FREQ_STEP 0.95367431640625 // ( ( double )( XTAL_FREQ / ( double )FREQ_DIV ) ) |
Wayne Roberts |
2:e6e159c8ab4d | 11 | #define MHZ_TO_FRF 1048576 // = (1<<25) / Fxtal_MHz |
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2:e6e159c8ab4d | 12 | #define KHZ_TO_FRF 1048.576 |
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7:fe8c0186ee50 | 13 | #define HZ_TO_FRF 1.048576 // = (1<<25) / Fxtal_Hz |
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1:497af0bd9e53 | 14 | |
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1:497af0bd9e53 | 15 | /***************************************************************/ |
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1:497af0bd9e53 | 16 | #define OPCODE_CLEAR_IRQ_STATUS 0x02 |
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1:497af0bd9e53 | 17 | #define OPCODE_CLEAR_DEVICE_ERRORS 0x07 |
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1:497af0bd9e53 | 18 | #define OPCODE_SET_DIO_IRQ_PARAMS 0x08 |
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1:497af0bd9e53 | 19 | #define OPCODE_WRITE_REGISTER 0x0d |
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1:497af0bd9e53 | 20 | #define OPCODE_WRITE_BUFFER 0x0e |
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1:497af0bd9e53 | 21 | #define OPCODE_GET_PACKET_TYPE 0x11 |
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1:497af0bd9e53 | 22 | #define OPCODE_GET_IRQ_STATUS 0x12 |
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1:497af0bd9e53 | 23 | #define OPCODE_GET_RX_BUFFER_STATUS 0x13 |
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1:497af0bd9e53 | 24 | #define OPCODE_GET_PACKET_STATUS 0x14 |
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1:497af0bd9e53 | 25 | #define OPCODE_GET_RSSIINST 0x15 |
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1:497af0bd9e53 | 26 | #define OPCODE_GET_DEVICE_ERRORS 0x17 |
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1:497af0bd9e53 | 27 | #define OPCODE_READ_REGISTER 0x1d |
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1:497af0bd9e53 | 28 | #define OPCODE_READ_BUFFER 0x1e |
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1:497af0bd9e53 | 29 | #define OPCODE_SET_STANDBY 0x80 |
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1:497af0bd9e53 | 30 | #define OPCODE_SET_RX 0x82 |
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1:497af0bd9e53 | 31 | #define OPCODE_SET_TX 0x83 |
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1:497af0bd9e53 | 32 | #define OPCODE_SET_SLEEP 0x84 |
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1:497af0bd9e53 | 33 | #define OPCODE_SET_RF_FREQUENCY 0x86 |
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8:66d3e344d61c | 34 | #define OPCODE_SET_CAD_PARAM 0x88 |
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1:497af0bd9e53 | 35 | #define OPCODE_CALIBRATE 0x89 |
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1:497af0bd9e53 | 36 | #define OPCODE_SET_PACKET_TYPE 0x8a |
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1:497af0bd9e53 | 37 | #define OPCODE_SET_MODULATION_PARAMS 0x8b |
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1:497af0bd9e53 | 38 | #define OPCODE_SET_PACKET_PARAMS 0x8c |
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1:497af0bd9e53 | 39 | #define OPCODE_SET_TX_PARAMS 0x8e |
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1:497af0bd9e53 | 40 | #define OPCODE_SET_BUFFER_BASE_ADDR 0x8f |
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1:497af0bd9e53 | 41 | #define OPCODE_SET_PA_CONFIG 0x95 |
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1:497af0bd9e53 | 42 | #define OPCODE_SET_REGULATOR_MODE 0x96 |
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1:497af0bd9e53 | 43 | #define OPCODE_SET_DIO3_AS_TCXO_CTRL 0x97 |
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1:497af0bd9e53 | 44 | #define OPCODE_SET_DIO2_AS_RFSWITCH 0x9d |
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1:497af0bd9e53 | 45 | #define OPCODE_SET_LORA_SYMBOL_TIMEOUT 0xa0 |
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1:497af0bd9e53 | 46 | #define OPCODE_GET_STATUS 0xc0 |
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4:b941bceb401d | 47 | #define OPCODE_SET_FS 0xc1 |
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8:66d3e344d61c | 48 | #define OPCODE_SET_CAD 0xc5 |
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5:8b75387af4e0 | 49 | #define OPCODE_SET_TX_CARRIER 0xd1 |
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5:8b75387af4e0 | 50 | #define OPCODE_SET_TX_PREAMBLE 0xd2 |
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1:497af0bd9e53 | 51 | /***************************************************************/ |
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3:f6f2f8adcd22 | 52 | #define PACKET_TYPE_GFSK 0 |
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1:497af0bd9e53 | 53 | #define PACKET_TYPE_LORA 1 |
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1:497af0bd9e53 | 54 | |
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1:497af0bd9e53 | 55 | #define HEADER_TYPE_VARIABLE_LENGTH 0 |
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1:497af0bd9e53 | 56 | #define HEADER_TYPE_FIXED_LENGTH 1 |
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1:497af0bd9e53 | 57 | |
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5:8b75387af4e0 | 58 | #define LROA_CRC_OFF 0 |
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5:8b75387af4e0 | 59 | #define LORA_CRC_ON 1 |
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1:497af0bd9e53 | 60 | |
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1:497af0bd9e53 | 61 | #define STANDARD_IQ 0 |
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1:497af0bd9e53 | 62 | #define INVERTED_IQ 1 |
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1:497af0bd9e53 | 63 | |
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1:497af0bd9e53 | 64 | /* direct register access */ |
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2:e6e159c8ab4d | 65 | #define REG_ADDR_IRQ_STATUS 0x58a // 16bit |
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2:e6e159c8ab4d | 66 | #define REG_ADDR_IRQ_MASK 0x58c // 16bit |
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2:e6e159c8ab4d | 67 | #define REG_ADDR_MODCFG 0x680 // 8bit |
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2:e6e159c8ab4d | 68 | #define REG_ADDR_BITRATE 0x6a1 // 24bit fsk |
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2:e6e159c8ab4d | 69 | #define REG_ADDR_FREQDEV 0x6a4 // 18bit fsk |
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2:e6e159c8ab4d | 70 | #define REG_ADDR_SHAPECFG 0x6a7 // 5bit |
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7:fe8c0186ee50 | 71 | #define REG_ADDR_FSK_DEMOD_CFO 0x6b0 // 12bit center frequency offset |
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2:e6e159c8ab4d | 72 | #define REG_ADDR_FSK_PKTCTRL0 0x6b3 // 8bit |
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2:e6e159c8ab4d | 73 | #define REG_ADDR_FSK_PKTCTRL1 0x6b4 // 3bit |
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2:e6e159c8ab4d | 74 | #define REG_ADDR_FSK_PREAMBLE_TXLEN 0x6b5 // 16bit |
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2:e6e159c8ab4d | 75 | #define REG_ADDR_FSK_SYNC_LEN 0x6b7 // 7bit |
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5:8b75387af4e0 | 76 | #define REG_ADDR_FSK_PKTCTRL1A 0x6b8 // 14bit 5bits+9bits |
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2:e6e159c8ab4d | 77 | #define REG_ADDR_FSK_PKTCTRL2 0x6ba // 8bit |
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2:e6e159c8ab4d | 78 | #define REG_ADDR_FSK_PAYLOAD_LEN 0x6bb // 8bit |
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5:8b75387af4e0 | 79 | #define REG_ADDR_FSK_CRCINIT 0x6bc // 16bit |
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5:8b75387af4e0 | 80 | #define REG_ADDR_FSK_CRCPOLY 0x6be // 16bit |
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2:e6e159c8ab4d | 81 | #define REG_ADDR_SYNCADDR 0x6c0 // 64bit fsk |
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2:e6e159c8ab4d | 82 | #define REG_ADDR_NODEADDR 0x6cd // 8bit fsk |
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5:8b75387af4e0 | 83 | #define REG_ADDR_BROADCAST 0x6ce // 8bit fsk |
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2:e6e159c8ab4d | 84 | #define REG_ADDR_NODEADDRCOMP 0x6cf // 2bit fsk |
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2:e6e159c8ab4d | 85 | |
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2:e6e159c8ab4d | 86 | #define REG_ADDR_LORA_TXPKTLEN 0x702 // 8bit |
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2:e6e159c8ab4d | 87 | #define REG_ADDR_LORA_CONFIG0 0x703 // 8bit bw/sf |
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2:e6e159c8ab4d | 88 | #define REG_ADDR_LORA_CONFIG1 0x704 // 8bit ppm_offset, fixlen, invertiq, cr |
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2:e6e159c8ab4d | 89 | #define REG_ADDR_LORA_CONFIG2 0x705 // 8bit crcType |
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2:e6e159c8ab4d | 90 | #define REG_ADDR_LORA_IRQ_MASK 0x70a // 24bit |
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8:66d3e344d61c | 91 | #define REG_ADDR_LORA_CONFIG9 0x724 // 8bit |
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2:e6e159c8ab4d | 92 | #define REG_ADDR_LORA_PREAMBLE_SYMBNB 0x73a // 16bit |
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8:66d3e344d61c | 93 | #define REG_ADDR_LORA_CAD_PN_RATIO 0x73e // 8bit |
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8:66d3e344d61c | 94 | #define REG_ADDR_LORA_CAD_MINPEAK 0x73f // 8bit |
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2:e6e159c8ab4d | 95 | #define REG_ADDR_LORA_SYNC 0x740 // config22, config23: frame sync peak position |
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7:fe8c0186ee50 | 96 | #define REG_ADDR_LORA_STATUS 0x76b // |
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2:e6e159c8ab4d | 97 | |
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2:e6e159c8ab4d | 98 | #define REG_ADDR_DIGFECTL 0x804 // 6bits |
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2:e6e159c8ab4d | 99 | #define REG_ADDR_BWSEL 0x807 // 5bits |
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2:e6e159c8ab4d | 100 | #define REG_ADDR_RANDOM 0x819 // ro |
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5:8b75387af4e0 | 101 | #define REG_ADDR_PA_CTRL0 0x880 // 8bits |
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5:8b75387af4e0 | 102 | #define REG_ADDR_PA_CTRL1 0x881 // 8bits |
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5:8b75387af4e0 | 103 | #define REG_ADDR_DIG_CTRL 0x882 // 8bits |
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5:8b75387af4e0 | 104 | #define REG_ADDR_PWR_CTRL 0x883 // 8bits |
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5:8b75387af4e0 | 105 | #define REG_ADDR_I_GAIN 0x884 // 8bits integral gain in pi filter |
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5:8b75387af4e0 | 106 | #define REG_ADDR_P_GAIN 0x885 // 8bits proportional gain in pi filter |
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2:e6e159c8ab4d | 107 | #define REG_ADDR_RFFREQ 0x88b // 31bits |
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2:e6e159c8ab4d | 108 | #define REG_ADDR_FREQ_OFFSET 0x88f // 19bits |
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2:e6e159c8ab4d | 109 | #define REG_ADDR_ANACTRL6 0x8d7 // 6bits |
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2:e6e159c8ab4d | 110 | #define REG_ADDR_ANACTRL7 0x8d8 // 6bits |
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2:e6e159c8ab4d | 111 | #define REG_ADDR_ANACTRL15 0x8e1 // 7bits |
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9:34f1f2bbe7b3 | 112 | #define REG_ADDR_ANACTRL16 0x8e2 |
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5:8b75387af4e0 | 113 | #define REG_ADDR_PA_CTRL1B 0x8e6 |
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5:8b75387af4e0 | 114 | #define REG_ADDR_OCP 0x8e7 // 6bits Imax 2.5mA steps |
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5:8b75387af4e0 | 115 | #define REG_ADDR_IMAX_OFFSET 0x8e8 // 5bits OCP offset |
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9:34f1f2bbe7b3 | 116 | #define REG_ADDR_XTA_TRIM 0x911 // crystal trim only in xosc |
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9:34f1f2bbe7b3 | 117 | #define REG_ADDR_XTB_TRIM 0x912 // crystal trim only in xosc |
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2:e6e159c8ab4d | 118 | #define REG_ADDR_ 0x |
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2:e6e159c8ab4d | 119 | |
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2:e6e159c8ab4d | 120 | /**********************************************/ |
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1:497af0bd9e53 | 121 | |
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1:497af0bd9e53 | 122 | #define SET_RAMP_10U 0x00 |
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1:497af0bd9e53 | 123 | #define SET_RAMP_20U 0x01 |
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1:497af0bd9e53 | 124 | #define SET_RAMP_40U 0x02 |
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1:497af0bd9e53 | 125 | #define SET_RAMP_80U 0x03 |
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1:497af0bd9e53 | 126 | #define SET_RAMP_200U 0x04 |
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1:497af0bd9e53 | 127 | #define SET_RAMP_800U 0x05 |
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1:497af0bd9e53 | 128 | #define SET_RAMP_1700U 0x06 |
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1:497af0bd9e53 | 129 | #define SET_RAMP_3400U 0x07 |
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1:497af0bd9e53 | 130 | |
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1:497af0bd9e53 | 131 | |
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1:497af0bd9e53 | 132 | |
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1:497af0bd9e53 | 133 | typedef union { |
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1:497af0bd9e53 | 134 | struct { |
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1:497af0bd9e53 | 135 | uint8_t rtcWakeup : 1; // 0 |
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1:497af0bd9e53 | 136 | uint8_t rfu : 1; // 1 |
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1:497af0bd9e53 | 137 | uint8_t warmStart : 1; // 2 |
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1:497af0bd9e53 | 138 | } bits; |
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1:497af0bd9e53 | 139 | uint8_t octet; |
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1:497af0bd9e53 | 140 | } sleepConfig_t; |
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1:497af0bd9e53 | 141 | |
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1:497af0bd9e53 | 142 | typedef union { |
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1:497af0bd9e53 | 143 | struct { |
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1:497af0bd9e53 | 144 | uint8_t PreambleLengthHi; // param1 |
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1:497af0bd9e53 | 145 | uint8_t PreambleLengthLo; // param2 |
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1:497af0bd9e53 | 146 | uint8_t HeaderType; // param3 |
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1:497af0bd9e53 | 147 | uint8_t PayloadLength; // param4 |
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1:497af0bd9e53 | 148 | uint8_t CRCType; // param5 |
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1:497af0bd9e53 | 149 | uint8_t InvertIQ; // param6 |
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1:497af0bd9e53 | 150 | uint8_t unused[2]; |
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1:497af0bd9e53 | 151 | } lora; |
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1:497af0bd9e53 | 152 | struct { |
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1:497af0bd9e53 | 153 | uint8_t PreambleLengthHi; // param1 |
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1:497af0bd9e53 | 154 | uint8_t PreambleLengthLo; // param2 |
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1:497af0bd9e53 | 155 | uint8_t PreambleDetectorLength; // param3 |
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1:497af0bd9e53 | 156 | uint8_t SyncWordLength; // param4 |
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1:497af0bd9e53 | 157 | uint8_t AddrComp; // param5 |
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1:497af0bd9e53 | 158 | uint8_t PacketType; // param6 |
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1:497af0bd9e53 | 159 | uint8_t PayloadLength; // param7 |
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1:497af0bd9e53 | 160 | uint8_t CRCType; // param8 |
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2:e6e159c8ab4d | 161 | uint8_t Whitening; // param9 |
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1:497af0bd9e53 | 162 | } gfsk; |
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6:cd4b02a7e65d | 163 | uint8_t buf[9]; |
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1:497af0bd9e53 | 164 | } PacketParams_t; |
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1:497af0bd9e53 | 165 | |
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1:497af0bd9e53 | 166 | |
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1:497af0bd9e53 | 167 | #define LORA_BW_7 0x00 // 7.81 kHz real |
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1:497af0bd9e53 | 168 | #define LORA_BW_10 0x08 // 10.42 kHz real |
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1:497af0bd9e53 | 169 | #define LORA_BW_15 0x01 // 15.63 kHz real |
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1:497af0bd9e53 | 170 | #define LORA_BW_20 0x09 // 20.83 kHz real |
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1:497af0bd9e53 | 171 | #define LORA_BW_31 0x02 // 31.25 kHz real |
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1:497af0bd9e53 | 172 | #define LORA_BW_41 0x0A // 41.67 kHz real |
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1:497af0bd9e53 | 173 | #define LORA_BW_62 0x03 // 62.50 kHz real |
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1:497af0bd9e53 | 174 | #define LORA_BW_125 0x04 // 125 kHz real |
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1:497af0bd9e53 | 175 | #define LORA_BW_250 0x05 // 250 kHz real |
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1:497af0bd9e53 | 176 | #define LORA_BW_500 0x06 // 500 kHz real |
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1:497af0bd9e53 | 177 | |
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1:497af0bd9e53 | 178 | #define LORA_CR_4_5 1 |
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1:497af0bd9e53 | 179 | #define LORA_CR_4_6 2 |
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1:497af0bd9e53 | 180 | #define LORA_CR_4_7 3 |
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1:497af0bd9e53 | 181 | #define LORA_CR_4_8 4 |
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1:497af0bd9e53 | 182 | |
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1:497af0bd9e53 | 183 | #define GFSK_PREAMBLE_DETECTOR_OFF 0x00 |
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1:497af0bd9e53 | 184 | #define GFSK_PREAMBLE_DETECTOR_LENGTH_8BITS 0x04 |
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1:497af0bd9e53 | 185 | #define GFSK_PREAMBLE_DETECTOR_LENGTH_16BITS 0x05 |
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1:497af0bd9e53 | 186 | #define GFSK_PREAMBLE_DETECTOR_LENGTH_24BITS 0x06 |
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1:497af0bd9e53 | 187 | #define GFSK_PREAMBLE_DETECTOR_LENGTH_32BITS 0x07 |
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1:497af0bd9e53 | 188 | |
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2:e6e159c8ab4d | 189 | #define GFSK_WHITENING_OFF 0 |
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2:e6e159c8ab4d | 190 | #define GFSK_WHITENING_ON 1 |
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2:e6e159c8ab4d | 191 | |
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1:497af0bd9e53 | 192 | #define GFSK_CRC_OFF 0x01 |
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1:497af0bd9e53 | 193 | #define GFSK_CRC_1_BYTE 0x00 |
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1:497af0bd9e53 | 194 | #define GFSK_CRC_2_BYTE 0x02 |
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1:497af0bd9e53 | 195 | #define GFSK_CRC_1_BYTE_INV 0x04 |
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1:497af0bd9e53 | 196 | #define GFSK_CRC_2_BYTE_INV 0x06 |
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1:497af0bd9e53 | 197 | |
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1:497af0bd9e53 | 198 | #define GFSK_RX_BW_4800 0x1F |
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1:497af0bd9e53 | 199 | #define GFSK_RX_BW_5800 0x17 |
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1:497af0bd9e53 | 200 | #define GFSK_RX_BW_7300 0x0F |
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1:497af0bd9e53 | 201 | #define GFSK_RX_BW_9700 0x1E |
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1:497af0bd9e53 | 202 | #define GFSK_RX_BW_11700 0x16 |
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1:497af0bd9e53 | 203 | #define GFSK_RX_BW_14600 0x0E |
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1:497af0bd9e53 | 204 | #define GFSK_RX_BW_19500 0x1D |
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1:497af0bd9e53 | 205 | #define GFSK_RX_BW_23400 0x15 |
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1:497af0bd9e53 | 206 | #define GFSK_RX_BW_29300 0x0D |
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1:497af0bd9e53 | 207 | #define GFSK_RX_BW_39000 0x1C |
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1:497af0bd9e53 | 208 | #define GFSK_RX_BW_46900 0x14 |
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1:497af0bd9e53 | 209 | #define GFSK_RX_BW_58600 0x0C |
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1:497af0bd9e53 | 210 | #define GFSK_RX_BW_78200 0x1B |
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1:497af0bd9e53 | 211 | #define GFSK_RX_BW_93800 0x13 |
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1:497af0bd9e53 | 212 | #define GFSK_RX_BW_117300 0x0B |
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1:497af0bd9e53 | 213 | #define GFSK_RX_BW_156200 0x1A |
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1:497af0bd9e53 | 214 | #define GFSK_RX_BW_187200 0x12 |
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1:497af0bd9e53 | 215 | #define GFSK_RX_BW_234300 0x0A |
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1:497af0bd9e53 | 216 | #define GFSK_RX_BW_312000 0x19 |
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1:497af0bd9e53 | 217 | #define GFSK_RX_BW_373600 0x11 |
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1:497af0bd9e53 | 218 | #define GFSK_RX_BW_467000 0x09 |
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1:497af0bd9e53 | 219 | |
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1:497af0bd9e53 | 220 | #define GFSK_SHAPE_NONE 0x00 |
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1:497af0bd9e53 | 221 | #define GFSK_SHAPE_BT0_3 0x08 |
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1:497af0bd9e53 | 222 | #define GFSK_SHAPE_BT0_5 0x09 |
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1:497af0bd9e53 | 223 | #define GFSK_SHAPE_BT0_7 0x0a |
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1:497af0bd9e53 | 224 | #define GFSK_SHAPE_BT1_0 0x0b |
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1:497af0bd9e53 | 225 | |
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1:497af0bd9e53 | 226 | typedef enum { |
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1:497af0bd9e53 | 227 | STBY_RC = 0, |
Wayne Roberts |
1:497af0bd9e53 | 228 | STBY_XOSC |
Wayne Roberts |
1:497af0bd9e53 | 229 | } stby_t; |
Wayne Roberts |
1:497af0bd9e53 | 230 | |
Wayne Roberts |
2:e6e159c8ab4d | 231 | #define MOD_TYPE_IQ 0 |
Wayne Roberts |
2:e6e159c8ab4d | 232 | #define MOD_TYPE_FSK 1 |
Wayne Roberts |
2:e6e159c8ab4d | 233 | #define MOD_TYPE_MSK 2 |
Wayne Roberts |
2:e6e159c8ab4d | 234 | #define MOD_TYPE_LORA 3 |
Wayne Roberts |
2:e6e159c8ab4d | 235 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 236 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 237 | uint8_t mod_order : 2; // 0,1 modulation size 2points to 16points |
Wayne Roberts |
2:e6e159c8ab4d | 238 | uint8_t mod_type : 2; // 2,3 IQ, FSK, MSK, LoRa |
Wayne Roberts |
2:e6e159c8ab4d | 239 | uint8_t data_src : 1; // 4 |
Wayne Roberts |
2:e6e159c8ab4d | 240 | uint8_t clk_src : 2; // 5,6 |
Wayne Roberts |
2:e6e159c8ab4d | 241 | uint8_t mod_en : 1; // 7 |
Wayne Roberts |
2:e6e159c8ab4d | 242 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 243 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 244 | } modCfg_t; // at 0x680 fsk |
Wayne Roberts |
2:e6e159c8ab4d | 245 | |
Wayne Roberts |
2:e6e159c8ab4d | 246 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 247 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 248 | uint8_t bt : 2; // 0,1 0=BT0.3 1=BT0.5 2=BT0.7 3=BT1.0 |
Wayne Roberts |
2:e6e159c8ab4d | 249 | uint8_t double_rate : 1; // 2 double oversampling rate |
Wayne Roberts |
2:e6e159c8ab4d | 250 | uint8_t pulse_shape : 2; // 3,4 0=noFilter 1=gaussian 2=RRC |
Wayne Roberts |
2:e6e159c8ab4d | 251 | uint8_t res : 3; // 5,6,7 |
Wayne Roberts |
2:e6e159c8ab4d | 252 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 253 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 254 | } shapeCfg_t; // at 0x6a7 fsk |
Wayne Roberts |
2:e6e159c8ab4d | 255 | |
Wayne Roberts |
2:e6e159c8ab4d | 256 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 257 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 258 | uint8_t pkt_start_p : 1; // 0 ros1 |
Wayne Roberts |
2:e6e159c8ab4d | 259 | uint8_t pkt_abort_p : 1; // 1 ros1 |
Wayne Roberts |
2:e6e159c8ab4d | 260 | uint8_t pkt_sw_clr_p : 1; // 2 ros1 |
Wayne Roberts |
2:e6e159c8ab4d | 261 | uint8_t crl_status_p : 1; // 3 ros1 |
Wayne Roberts |
2:e6e159c8ab4d | 262 | uint8_t clk_en : 1; // 4 ro |
Wayne Roberts |
2:e6e159c8ab4d | 263 | uint8_t pkt_rx_ntx : 1; // 5 |
Wayne Roberts |
2:e6e159c8ab4d | 264 | uint8_t pkt_len_format : 1; // 6 |
Wayne Roberts |
2:e6e159c8ab4d | 265 | uint8_t cont_rx : 1; // 7 |
Wayne Roberts |
2:e6e159c8ab4d | 266 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 267 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 268 | } pktCtrl0_t; // at 0x6b3 fsk |
Wayne Roberts |
2:e6e159c8ab4d | 269 | |
Wayne Roberts |
2:e6e159c8ab4d | 270 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 271 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 272 | uint8_t preamble_len_rx : 2; // 0,1 number of preamble bits detected |
Wayne Roberts |
5:8b75387af4e0 | 273 | uint8_t preamble_det_on : 1; // 2 enable rx-sde preamble detector |
Wayne Roberts |
5:8b75387af4e0 | 274 | uint8_t res : 5; // 7 |
Wayne Roberts |
2:e6e159c8ab4d | 275 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 276 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 277 | } pktCtrl1_t; // at 0x6b4 fsk |
Wayne Roberts |
2:e6e159c8ab4d | 278 | |
Wayne Roberts |
2:e6e159c8ab4d | 279 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 280 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 281 | uint16_t whit_init_val : 9; // 0...8 at 0x6b9 |
Wayne Roberts |
5:8b75387af4e0 | 282 | uint16_t infinite_seq_en : 1; // 9 |
Wayne Roberts |
5:8b75387af4e0 | 283 | uint16_t infinite_seq_select : 2; // 10,11 |
Wayne Roberts |
5:8b75387af4e0 | 284 | uint16_t cont_tx : 1; // 12 |
Wayne Roberts |
5:8b75387af4e0 | 285 | uint16_t sync_det_on : 1; // 13 |
Wayne Roberts |
5:8b75387af4e0 | 286 | uint16_t res : 2; // 14,15 |
Wayne Roberts |
5:8b75387af4e0 | 287 | } bits; |
Wayne Roberts |
5:8b75387af4e0 | 288 | uint16_t word; |
Wayne Roberts |
5:8b75387af4e0 | 289 | } PktCtrl1a_t; // at 0x6b8 |
Wayne Roberts |
5:8b75387af4e0 | 290 | |
Wayne Roberts |
5:8b75387af4e0 | 291 | typedef union { |
Wayne Roberts |
5:8b75387af4e0 | 292 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 293 | uint8_t crc_disable : 1; // 0 |
Wayne Roberts |
2:e6e159c8ab4d | 294 | uint8_t crc_len : 1; // 1 0=1byte 1=2byte |
Wayne Roberts |
2:e6e159c8ab4d | 295 | uint8_t crc_inv : 1; // 2 |
Wayne Roberts |
2:e6e159c8ab4d | 296 | uint8_t crc_in_fifo : 1; // 3 |
Wayne Roberts |
2:e6e159c8ab4d | 297 | uint8_t whit_enable : 1; // 4 |
Wayne Roberts |
2:e6e159c8ab4d | 298 | uint8_t manchester_en : 1; // 5 |
Wayne Roberts |
2:e6e159c8ab4d | 299 | uint8_t rssi_mode : 2; // 6,7 |
Wayne Roberts |
2:e6e159c8ab4d | 300 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 301 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 302 | } pktCtrl2_t; // at 0x6ba fsk |
Wayne Roberts |
2:e6e159c8ab4d | 303 | |
Wayne Roberts |
2:e6e159c8ab4d | 304 | |
Wayne Roberts |
2:e6e159c8ab4d | 305 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 306 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 307 | uint8_t modem_sf: 4; // 0,1,2,3 |
Wayne Roberts |
2:e6e159c8ab4d | 308 | uint8_t modem_bw: 4; // 4,5,6,7 |
Wayne Roberts |
2:e6e159c8ab4d | 309 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 310 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 311 | } loraConfig0_t; // at 0x703 |
Wayne Roberts |
2:e6e159c8ab4d | 312 | |
Wayne Roberts |
2:e6e159c8ab4d | 313 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 314 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 315 | uint8_t tx_coding_rate : 3; // 0,1,2 |
Wayne Roberts |
2:e6e159c8ab4d | 316 | uint8_t ppm_offset : 2; // 3,4 aka long range mode |
Wayne Roberts |
2:e6e159c8ab4d | 317 | uint8_t tx_mode : 1; // 5 |
Wayne Roberts |
2:e6e159c8ab4d | 318 | uint8_t rx_invert_iq : 1; // 6 |
Wayne Roberts |
2:e6e159c8ab4d | 319 | uint8_t implicit_header : 1; // 7 0=variable length packet |
Wayne Roberts |
2:e6e159c8ab4d | 320 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 321 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 322 | } loraConfig1_t; // at 0x704 |
Wayne Roberts |
2:e6e159c8ab4d | 323 | |
Wayne Roberts |
2:e6e159c8ab4d | 324 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 325 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 326 | uint8_t cad_rxtx : 2; // 0,1 |
Wayne Roberts |
2:e6e159c8ab4d | 327 | uint8_t tx_payload_crc16_en : 1; // 2 |
Wayne Roberts |
2:e6e159c8ab4d | 328 | uint8_t cont_rx : 1; // 3 |
Wayne Roberts |
2:e6e159c8ab4d | 329 | uint8_t freeze_dagc_upon_synch : 2; // 4,5 |
Wayne Roberts |
2:e6e159c8ab4d | 330 | uint8_t fine_sync_en : 1; // 6 |
Wayne Roberts |
2:e6e159c8ab4d | 331 | uint8_t res : 1; // 7 |
Wayne Roberts |
2:e6e159c8ab4d | 332 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 333 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 334 | } loraConfig2_t; // at 0x705 |
Wayne Roberts |
2:e6e159c8ab4d | 335 | |
Wayne Roberts |
2:e6e159c8ab4d | 336 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 337 | struct { |
Wayne Roberts |
7:fe8c0186ee50 | 338 | uint32_t est_freq_error :20; // 0..19 |
Wayne Roberts |
7:fe8c0186ee50 | 339 | uint32_t header_crc16_en : 1; // 20 |
Wayne Roberts |
7:fe8c0186ee50 | 340 | uint32_t rf_en_request : 2; // 21,22 |
Wayne Roberts |
7:fe8c0186ee50 | 341 | uint32_t raw_ranging_result_available : 1; // 23 |
Wayne Roberts |
7:fe8c0186ee50 | 342 | uint32_t unused : 8; // 24..31 |
Wayne Roberts |
7:fe8c0186ee50 | 343 | } bits; |
Wayne Roberts |
7:fe8c0186ee50 | 344 | uint32_t dword; |
Wayne Roberts |
7:fe8c0186ee50 | 345 | } loraStatus1_t; // at 0x76b |
Wayne Roberts |
7:fe8c0186ee50 | 346 | |
Wayne Roberts |
7:fe8c0186ee50 | 347 | typedef union { |
Wayne Roberts |
7:fe8c0186ee50 | 348 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 349 | uint8_t inv_edge : 1; // 0 |
Wayne Roberts |
2:e6e159c8ab4d | 350 | uint8_t swap_iq : 1; // 1 |
Wayne Roberts |
2:e6e159c8ab4d | 351 | uint8_t dig_fe_clear : 1; // 2 |
Wayne Roberts |
2:e6e159c8ab4d | 352 | uint8_t lora_ngfsk : 1; // 3 data buffer selection lora/gfsk |
Wayne Roberts |
2:e6e159c8ab4d | 353 | uint8_t adc_from_dio : 1; // 4 |
Wayne Roberts |
2:e6e159c8ab4d | 354 | uint8_t lora_pre_cf_en : 1; // 5 |
Wayne Roberts |
2:e6e159c8ab4d | 355 | uint8_t res : 2; // 6,7 |
Wayne Roberts |
2:e6e159c8ab4d | 356 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 357 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 358 | } digFeCtrl_t; // at 0x804 |
Wayne Roberts |
2:e6e159c8ab4d | 359 | |
Wayne Roberts |
2:e6e159c8ab4d | 360 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 361 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 362 | uint8_t exp : 3; // 0,1,2 |
Wayne Roberts |
2:e6e159c8ab4d | 363 | uint8_t mant : 2; // 3,4 |
Wayne Roberts |
2:e6e159c8ab4d | 364 | uint8_t res : 3; // 5,6,7 |
Wayne Roberts |
2:e6e159c8ab4d | 365 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 366 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 367 | } bwSel_t; // at 0x807 rx_bw |
Wayne Roberts |
2:e6e159c8ab4d | 368 | |
Wayne Roberts |
2:e6e159c8ab4d | 369 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 370 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 371 | uint8_t reg_pa_discharge_en : 1; // 0 |
Wayne Roberts |
5:8b75387af4e0 | 372 | uint8_t reg_pa_boost_en : 1; // 1 |
Wayne Roberts |
5:8b75387af4e0 | 373 | uint8_t dac_pol : 2; // 2,3 |
Wayne Roberts |
5:8b75387af4e0 | 374 | } bits; |
Wayne Roberts |
5:8b75387af4e0 | 375 | uint8_t octet; |
Wayne Roberts |
5:8b75387af4e0 | 376 | } paCtrl0_t; // at 0x880 |
Wayne Roberts |
5:8b75387af4e0 | 377 | |
Wayne Roberts |
5:8b75387af4e0 | 378 | typedef union { |
Wayne Roberts |
5:8b75387af4e0 | 379 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 380 | uint8_t boost_delay : 6; // 0,1,2,3,4,5 |
Wayne Roberts |
5:8b75387af4e0 | 381 | uint8_t boost_width : 2; // 6,7 |
Wayne Roberts |
5:8b75387af4e0 | 382 | } bits; |
Wayne Roberts |
5:8b75387af4e0 | 383 | uint8_t octet; |
Wayne Roberts |
5:8b75387af4e0 | 384 | } paCtrl1_t; // at 0x881 |
Wayne Roberts |
5:8b75387af4e0 | 385 | |
Wayne Roberts |
5:8b75387af4e0 | 386 | typedef union { |
Wayne Roberts |
5:8b75387af4e0 | 387 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 388 | uint8_t ramp_on : 1; // 0 |
Wayne Roberts |
5:8b75387af4e0 | 389 | uint8_t ramp_down : 1; // 1 |
Wayne Roberts |
5:8b75387af4e0 | 390 | uint8_t ramp_up : 1; // 2 |
Wayne Roberts |
5:8b75387af4e0 | 391 | uint8_t ramp_status : 1; // 3 |
Wayne Roberts |
5:8b75387af4e0 | 392 | uint8_t force_dac_code_en : 1; // 4 |
Wayne Roberts |
5:8b75387af4e0 | 393 | uint8_t pa_mod_en : 1; // 5 |
Wayne Roberts |
5:8b75387af4e0 | 394 | } bits; |
Wayne Roberts |
5:8b75387af4e0 | 395 | uint8_t octet; |
Wayne Roberts |
5:8b75387af4e0 | 396 | } DigCtrl_t; // at 0x882 |
Wayne Roberts |
5:8b75387af4e0 | 397 | |
Wayne Roberts |
5:8b75387af4e0 | 398 | typedef union { |
Wayne Roberts |
5:8b75387af4e0 | 399 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 400 | uint8_t tx_pwr : 5; // 0,1,2,3,4 |
Wayne Roberts |
5:8b75387af4e0 | 401 | uint8_t ramp_time : 3; // 5,6,7 |
Wayne Roberts |
5:8b75387af4e0 | 402 | } bits; |
Wayne Roberts |
5:8b75387af4e0 | 403 | uint8_t octet; |
Wayne Roberts |
5:8b75387af4e0 | 404 | } PwrCtrl_t; // at 0x883 |
Wayne Roberts |
5:8b75387af4e0 | 405 | |
Wayne Roberts |
5:8b75387af4e0 | 406 | |
Wayne Roberts |
5:8b75387af4e0 | 407 | |
Wayne Roberts |
5:8b75387af4e0 | 408 | |
Wayne Roberts |
5:8b75387af4e0 | 409 | typedef union { |
Wayne Roberts |
5:8b75387af4e0 | 410 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 411 | uint8_t pa_hp_ena_ana : 1; // 0 |
Wayne Roberts |
2:e6e159c8ab4d | 412 | uint8_t tx_ena_bat : 1; // 1 |
Wayne Roberts |
5:8b75387af4e0 | 413 | uint8_t pa_dctrim_select_ana : 4; // 2,3,4,5 paDutyCycle |
Wayne Roberts |
2:e6e159c8ab4d | 414 | uint8_t res : 2; // 6,7 |
Wayne Roberts |
2:e6e159c8ab4d | 415 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 416 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 417 | } AnaCtrl6_t; // at 0x8d7 |
Wayne Roberts |
2:e6e159c8ab4d | 418 | |
Wayne Roberts |
2:e6e159c8ab4d | 419 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 420 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 421 | uint8_t pa_lp_ena_ana : 1; // 0 |
Wayne Roberts |
2:e6e159c8ab4d | 422 | uint8_t pa_clamp_code_bat : 3; // 1,2,3 |
Wayne Roberts |
2:e6e159c8ab4d | 423 | uint8_t pa_clamp_override_bat : 1; // 4 |
Wayne Roberts |
5:8b75387af4e0 | 424 | uint8_t pa_hp_sel_ana : 3; // 5,6,7 hpMax |
Wayne Roberts |
2:e6e159c8ab4d | 425 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 426 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 427 | } AnaCtrl7_t; // at 0x8d8 |
Wayne Roberts |
2:e6e159c8ab4d | 428 | |
Wayne Roberts |
2:e6e159c8ab4d | 429 | typedef union { |
Wayne Roberts |
2:e6e159c8ab4d | 430 | struct { |
Wayne Roberts |
2:e6e159c8ab4d | 431 | uint8_t reg_pa_comp_poarity_ana : 1; // 0 |
Wayne Roberts |
2:e6e159c8ab4d | 432 | uint8_t reg_pa_comp_en_ana : 1; // 1 |
Wayne Roberts |
2:e6e159c8ab4d | 433 | uint8_t fir_dac_sign_ana : 2; // 2,3 |
Wayne Roberts |
2:e6e159c8ab4d | 434 | uint8_t fir_dac_pole_ana : 3; // 4,5,6 |
Wayne Roberts |
2:e6e159c8ab4d | 435 | uint8_t res : 1; // 7 |
Wayne Roberts |
2:e6e159c8ab4d | 436 | } bits; |
Wayne Roberts |
2:e6e159c8ab4d | 437 | uint8_t octet; |
Wayne Roberts |
2:e6e159c8ab4d | 438 | } AnaCtrl15_t; // at 0x8e1 |
Wayne Roberts |
2:e6e159c8ab4d | 439 | |
Wayne Roberts |
1:497af0bd9e53 | 440 | typedef union { |
Wayne Roberts |
1:497af0bd9e53 | 441 | struct { |
Wayne Roberts |
5:8b75387af4e0 | 442 | uint8_t force_ref : 1; // 0 |
Wayne Roberts |
5:8b75387af4e0 | 443 | uint8_t pa_voltage_lim_en : 1; // 1 |
Wayne Roberts |
5:8b75387af4e0 | 444 | uint8_t pa_current_lim_en : 1; // 2 |
Wayne Roberts |
5:8b75387af4e0 | 445 | uint8_t tx_mode_bat : 1; // 3 deviceSel 0=hipower 1=lopower take precedence over hpp_mode |
Wayne Roberts |
5:8b75387af4e0 | 446 | uint8_t hp_mode : 1; // 4 hi-power submode 0=14dBm LUT, 1=20dBm LUT |
Wayne Roberts |
5:8b75387af4e0 | 447 | } bits; |
Wayne Roberts |
5:8b75387af4e0 | 448 | uint8_t octet; |
Wayne Roberts |
5:8b75387af4e0 | 449 | } PaCtrl1b_t; // at 0x8e6 |
Wayne Roberts |
5:8b75387af4e0 | 450 | |
Wayne Roberts |
5:8b75387af4e0 | 451 | typedef union { |
Wayne Roberts |
5:8b75387af4e0 | 452 | struct { |
Wayne Roberts |
1:497af0bd9e53 | 453 | uint8_t spreadingFactor; // param1 |
Wayne Roberts |
1:497af0bd9e53 | 454 | uint8_t bandwidth; // param2 |
Wayne Roberts |
1:497af0bd9e53 | 455 | uint8_t codingRate; // param3 |
Wayne Roberts |
1:497af0bd9e53 | 456 | uint8_t LowDatarateOptimize; // param4 |
Wayne Roberts |
1:497af0bd9e53 | 457 | } lora; |
Wayne Roberts |
1:497af0bd9e53 | 458 | struct { |
Wayne Roberts |
1:497af0bd9e53 | 459 | uint8_t bitrateHi; // param1 |
Wayne Roberts |
1:497af0bd9e53 | 460 | uint8_t bitrateMid; // param2 |
Wayne Roberts |
1:497af0bd9e53 | 461 | uint8_t bitrateLo; // param3 |
Wayne Roberts |
1:497af0bd9e53 | 462 | uint8_t PulseShape; // param4 |
Wayne Roberts |
2:e6e159c8ab4d | 463 | uint8_t bandwidth; // param5 |
Wayne Roberts |
2:e6e159c8ab4d | 464 | uint8_t fdevHi; // param6 |
Wayne Roberts |
1:497af0bd9e53 | 465 | uint8_t fdevMid; // param7 |
Wayne Roberts |
2:e6e159c8ab4d | 466 | uint8_t fdevLo; // param8 |
Wayne Roberts |
1:497af0bd9e53 | 467 | } gfsk; |
Wayne Roberts |
1:497af0bd9e53 | 468 | uint8_t buf[8]; |
Wayne Roberts |
1:497af0bd9e53 | 469 | } ModulationParams_t; |
Wayne Roberts |
1:497af0bd9e53 | 470 | |
Wayne Roberts |
1:497af0bd9e53 | 471 | typedef union { |
Wayne Roberts |
1:497af0bd9e53 | 472 | struct { // |
Wayne Roberts |
3:f6f2f8adcd22 | 473 | uint16_t TxDone : 1; // 0 |
Wayne Roberts |
3:f6f2f8adcd22 | 474 | uint16_t RxDone : 1; // 1 |
Wayne Roberts |
3:f6f2f8adcd22 | 475 | uint16_t PreambleDetected : 1; // 2 |
Wayne Roberts |
3:f6f2f8adcd22 | 476 | uint16_t SyncWordValid : 1; // 3 |
Wayne Roberts |
3:f6f2f8adcd22 | 477 | uint16_t HeaderValid : 1; // 4 |
Wayne Roberts |
3:f6f2f8adcd22 | 478 | uint16_t HeaderErr : 1; // 5 |
Wayne Roberts |
3:f6f2f8adcd22 | 479 | uint16_t CrCerr : 1; // 6 |
Wayne Roberts |
3:f6f2f8adcd22 | 480 | uint16_t CadDone : 1; // 7 |
Wayne Roberts |
3:f6f2f8adcd22 | 481 | uint16_t CadDetected : 1; // 8 |
Wayne Roberts |
3:f6f2f8adcd22 | 482 | uint16_t Timeout : 1; // 9 |
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3:f6f2f8adcd22 | 483 | uint16_t res : 6; // 10,11,12,13,14,15 |
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1:497af0bd9e53 | 484 | } bits; |
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1:497af0bd9e53 | 485 | uint16_t word; |
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1:497af0bd9e53 | 486 | } IrqFlags_t; |
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1:497af0bd9e53 | 487 | |
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1:497af0bd9e53 | 488 | typedef union { |
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1:497af0bd9e53 | 489 | struct { // |
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1:497af0bd9e53 | 490 | uint8_t _reserved : 1; // 0 |
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1:497af0bd9e53 | 491 | uint8_t cmdStatus : 3; // 1,2,3 |
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1:497af0bd9e53 | 492 | uint8_t chipMode : 3; // 4,5,6 |
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1:497af0bd9e53 | 493 | uint8_t reserved_ : 1; // 7 |
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1:497af0bd9e53 | 494 | } bits; |
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1:497af0bd9e53 | 495 | uint8_t octet; |
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1:497af0bd9e53 | 496 | } status_t; |
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1:497af0bd9e53 | 497 | |
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1:497af0bd9e53 | 498 | typedef enum { |
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1:497af0bd9e53 | 499 | CHIPMODE_NONE = 0, |
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1:497af0bd9e53 | 500 | CHIPMODE_RX, |
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1:497af0bd9e53 | 501 | CHIPMODE_TX |
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1:497af0bd9e53 | 502 | } chipMote_e; |
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1:497af0bd9e53 | 503 | |
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1:497af0bd9e53 | 504 | class SX126x { |
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1:497af0bd9e53 | 505 | public: |
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1:497af0bd9e53 | 506 | SX126x(SPI&, PinName nss, PinName busy, PinName dio1); |
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1:497af0bd9e53 | 507 | |
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1:497af0bd9e53 | 508 | |
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1:497af0bd9e53 | 509 | void hw_reset(PinName nrst); |
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2:e6e159c8ab4d | 510 | void xfer(uint8_t opcode, uint8_t writeLen, uint8_t readLen, uint8_t* buf); |
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1:497af0bd9e53 | 511 | void setPacketType(uint8_t); |
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3:f6f2f8adcd22 | 512 | uint8_t getPacketType(void); |
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1:497af0bd9e53 | 513 | uint8_t setMHz(float); |
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2:e6e159c8ab4d | 514 | float getMHz(void); |
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1:497af0bd9e53 | 515 | |
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1:497af0bd9e53 | 516 | /* start_tx and start_rx assumes DIO1 is connected, and only pin used to generate radio interrupt */ |
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1:497af0bd9e53 | 517 | void start_tx(uint8_t pktLen); // tx_buf must be filled prior to calling |
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1:497af0bd9e53 | 518 | |
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1:497af0bd9e53 | 519 | #define RX_TIMEOUT_SINGLE 0x000000 /* stop RX after first packet */ |
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1:497af0bd9e53 | 520 | #define RX_TIMEOUT_CONTINUOUS 0xffffff /* keep RXing */ |
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1:497af0bd9e53 | 521 | void start_rx(unsigned); |
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1:497af0bd9e53 | 522 | |
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2:e6e159c8ab4d | 523 | void ReadBuffer(uint8_t size, uint8_t offset); |
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1:497af0bd9e53 | 524 | void SetDIO2AsRfSwitchCtrl(uint8_t); |
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1:497af0bd9e53 | 525 | void set_tx_dbm(bool is1262, int8_t dbm); |
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1:497af0bd9e53 | 526 | uint32_t readReg(uint16_t addr, uint8_t len); |
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1:497af0bd9e53 | 527 | void writeReg(uint16_t addr, uint32_t data, uint8_t len); |
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1:497af0bd9e53 | 528 | void setStandby(stby_t); |
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1:497af0bd9e53 | 529 | void setSleep(bool warmStart, bool rtcWakeup); |
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4:b941bceb401d | 530 | void setFS(void); |
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8:66d3e344d61c | 531 | void setCAD(void); |
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5:8b75387af4e0 | 532 | void setBufferBase(uint8_t txAddr, uint8_t rxAddr); |
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1:497af0bd9e53 | 533 | |
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1:497af0bd9e53 | 534 | static Callback<void()> dio1_topHalf; // low latency ISR context |
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1:497af0bd9e53 | 535 | void service(void); |
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1:497af0bd9e53 | 536 | Callback<void()> txDone; // user context |
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4:b941bceb401d | 537 | Callback<void()> chipModeChange; // read chipMode_e chipMode |
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1:497af0bd9e53 | 538 | void (*rxDone)(uint8_t size, float rssi, float snr); // user context |
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1:497af0bd9e53 | 539 | void (*timeout)(bool tx); // user context |
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8:66d3e344d61c | 540 | void (*cadDone)(bool detected); // user context |
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1:497af0bd9e53 | 541 | |
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1:497af0bd9e53 | 542 | //! RF transmit packet buffer |
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1:497af0bd9e53 | 543 | uint8_t tx_buf[256]; // lora fifo size |
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1:497af0bd9e53 | 544 | |
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1:497af0bd9e53 | 545 | //! RF receive packet buffer |
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1:497af0bd9e53 | 546 | uint8_t rx_buf[256]; // lora fifo size |
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1:497af0bd9e53 | 547 | |
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1:497af0bd9e53 | 548 | /** Test if dio1 pin is asserted |
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1:497af0bd9e53 | 549 | */ |
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1:497af0bd9e53 | 550 | inline bool getDIO1(void) { return dio1.read(); } |
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1:497af0bd9e53 | 551 | void PrintChipStatus(status_t); |
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1:497af0bd9e53 | 552 | chipMote_e chipMode; |
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1:497af0bd9e53 | 553 | |
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1:497af0bd9e53 | 554 | private: |
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1:497af0bd9e53 | 555 | SPI& spi; |
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1:497af0bd9e53 | 556 | DigitalOut nss; |
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1:497af0bd9e53 | 557 | DigitalIn busy; |
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1:497af0bd9e53 | 558 | InterruptIn dio1; |
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1:497af0bd9e53 | 559 | static void dio1isr(void); |
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1:497af0bd9e53 | 560 | bool sleeping; |
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1:497af0bd9e53 | 561 | }; |
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1:497af0bd9e53 | 562 | |
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1:497af0bd9e53 | 563 | #endif /* SX126x_H */ |
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1:497af0bd9e53 | 564 |