wayne roberts / sx126x

sx1261/2 driver

Dependents:   alarm_slave iq_sx126x sx126x_simple_TX_shield_2020a sx126x_simple_RX_shield_2020a ... more

Driver for SX1261 or SX1262

sx12xx.h@1:497af0bd9e53, 2018-05-22 (annotated)

Committer:
Wayne Roberts
Date:
Tue May 22 14:26:32 2018 -0700
Revision:
1:497af0bd9e53
Child:
2:e6e159c8ab4d
update to be interchangable with sx127x driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Wayne Roberts 1:497af0bd9e53 1 #include "mbed.h"
Wayne Roberts 1:497af0bd9e53 2 #ifndef SX126x_H
Wayne Roberts 1:497af0bd9e53 3 #define SX126x_H
Wayne Roberts 1:497af0bd9e53 4
Wayne Roberts 1:497af0bd9e53 5 #define RC_TICKS_PER_MS 0.015625 /* 64KHz */
Wayne Roberts 1:497af0bd9e53 6 #define RC_TICKS_PER_US 15.625 /* 64KHz */
Wayne Roberts 1:497af0bd9e53 7
Wayne Roberts 1:497af0bd9e53 8 #define XTAL_FREQ 32000000
Wayne Roberts 1:497af0bd9e53 9 #define FREQ_DIV 33554432
Wayne Roberts 1:497af0bd9e53 10 #define FREQ_STEP 0.95367431640625 // ( ( double )( XTAL_FREQ / ( double )FREQ_DIV ) )
Wayne Roberts 1:497af0bd9e53 11
Wayne Roberts 1:497af0bd9e53 12 /***************************************************************/
Wayne Roberts 1:497af0bd9e53 13 #define OPCODE_CLEAR_IRQ_STATUS 0x02
Wayne Roberts 1:497af0bd9e53 14 #define OPCODE_CLEAR_DEVICE_ERRORS 0x07
Wayne Roberts 1:497af0bd9e53 15 #define OPCODE_SET_DIO_IRQ_PARAMS 0x08
Wayne Roberts 1:497af0bd9e53 16 #define OPCODE_WRITE_REGISTER 0x0d
Wayne Roberts 1:497af0bd9e53 17 #define OPCODE_WRITE_BUFFER 0x0e
Wayne Roberts 1:497af0bd9e53 18 #define OPCODE_GET_PACKET_TYPE 0x11
Wayne Roberts 1:497af0bd9e53 19 #define OPCODE_GET_IRQ_STATUS 0x12
Wayne Roberts 1:497af0bd9e53 20 #define OPCODE_GET_RX_BUFFER_STATUS 0x13
Wayne Roberts 1:497af0bd9e53 21 #define OPCODE_GET_PACKET_STATUS 0x14
Wayne Roberts 1:497af0bd9e53 22 #define OPCODE_GET_RSSIINST 0x15
Wayne Roberts 1:497af0bd9e53 23 #define OPCODE_GET_DEVICE_ERRORS 0x17
Wayne Roberts 1:497af0bd9e53 24 #define OPCODE_READ_REGISTER 0x1d
Wayne Roberts 1:497af0bd9e53 25 #define OPCODE_READ_BUFFER 0x1e
Wayne Roberts 1:497af0bd9e53 26 #define OPCODE_SET_STANDBY 0x80
Wayne Roberts 1:497af0bd9e53 27 #define OPCODE_SET_RX 0x82
Wayne Roberts 1:497af0bd9e53 28 #define OPCODE_SET_TX 0x83
Wayne Roberts 1:497af0bd9e53 29 #define OPCODE_SET_SLEEP 0x84
Wayne Roberts 1:497af0bd9e53 30 #define OPCODE_SET_RF_FREQUENCY 0x86
Wayne Roberts 1:497af0bd9e53 31 #define OPCODE_CALIBRATE 0x89
Wayne Roberts 1:497af0bd9e53 32 #define OPCODE_SET_PACKET_TYPE 0x8a
Wayne Roberts 1:497af0bd9e53 33 #define OPCODE_SET_MODULATION_PARAMS 0x8b
Wayne Roberts 1:497af0bd9e53 34 #define OPCODE_SET_PACKET_PARAMS 0x8c
Wayne Roberts 1:497af0bd9e53 35 #define OPCODE_SET_TX_PARAMS 0x8e
Wayne Roberts 1:497af0bd9e53 36 #define OPCODE_SET_BUFFER_BASE_ADDR 0x8f
Wayne Roberts 1:497af0bd9e53 37 #define OPCODE_SET_PA_CONFIG 0x95
Wayne Roberts 1:497af0bd9e53 38 #define OPCODE_SET_REGULATOR_MODE 0x96
Wayne Roberts 1:497af0bd9e53 39 #define OPCODE_SET_DIO3_AS_TCXO_CTRL 0x97
Wayne Roberts 1:497af0bd9e53 40 #define OPCODE_SET_DIO2_AS_RFSWITCH 0x9d
Wayne Roberts 1:497af0bd9e53 41 #define OPCODE_SET_LORA_SYMBOL_TIMEOUT 0xa0
Wayne Roberts 1:497af0bd9e53 42 #define OPCODE_GET_STATUS 0xc0
Wayne Roberts 1:497af0bd9e53 43 #define OPCODE_SET_TX_CONTINUOUS 0xd1
Wayne Roberts 1:497af0bd9e53 44 /***************************************************************/
Wayne Roberts 1:497af0bd9e53 45 #define PACKET_TYPE_GFSK 1
Wayne Roberts 1:497af0bd9e53 46 #define PACKET_TYPE_LORA 1
Wayne Roberts 1:497af0bd9e53 47
Wayne Roberts 1:497af0bd9e53 48 #define HEADER_TYPE_VARIABLE_LENGTH 0
Wayne Roberts 1:497af0bd9e53 49 #define HEADER_TYPE_FIXED_LENGTH 1
Wayne Roberts 1:497af0bd9e53 50
Wayne Roberts 1:497af0bd9e53 51 #define CRC_OFF 0
Wayne Roberts 1:497af0bd9e53 52 #define CRC_ON 0
Wayne Roberts 1:497af0bd9e53 53
Wayne Roberts 1:497af0bd9e53 54 #define STANDARD_IQ 0
Wayne Roberts 1:497af0bd9e53 55 #define INVERTED_IQ 1
Wayne Roberts 1:497af0bd9e53 56
Wayne Roberts 1:497af0bd9e53 57 /* direct register access */
Wayne Roberts 1:497af0bd9e53 58 #define REG_ADDR_LORA_CONFIG0 0x0703 // 8bit bw/sf
Wayne Roberts 1:497af0bd9e53 59 #define REG_ADDR_LORA_IRQ_MASK 0x070a // 24bit
Wayne Roberts 1:497af0bd9e53 60 #define REG_ADDR_LORA_SYNC 0x0740 // config22, config23: frame sync peak position
Wayne Roberts 1:497af0bd9e53 61 #define REG_ADDR_RANDOM 0x0819
Wayne Roberts 1:497af0bd9e53 62 #define REG_ADDR_OCP 0x08e7
Wayne Roberts 1:497af0bd9e53 63 #define REG_ADDR_
Wayne Roberts 1:497af0bd9e53 64
Wayne Roberts 1:497af0bd9e53 65 #define SET_RAMP_10U 0x00
Wayne Roberts 1:497af0bd9e53 66 #define SET_RAMP_20U 0x01
Wayne Roberts 1:497af0bd9e53 67 #define SET_RAMP_40U 0x02
Wayne Roberts 1:497af0bd9e53 68 #define SET_RAMP_80U 0x03
Wayne Roberts 1:497af0bd9e53 69 #define SET_RAMP_200U 0x04
Wayne Roberts 1:497af0bd9e53 70 #define SET_RAMP_800U 0x05
Wayne Roberts 1:497af0bd9e53 71 #define SET_RAMP_1700U 0x06
Wayne Roberts 1:497af0bd9e53 72 #define SET_RAMP_3400U 0x07
Wayne Roberts 1:497af0bd9e53 73
Wayne Roberts 1:497af0bd9e53 74
Wayne Roberts 1:497af0bd9e53 75
Wayne Roberts 1:497af0bd9e53 76 typedef union {
Wayne Roberts 1:497af0bd9e53 77 struct {
Wayne Roberts 1:497af0bd9e53 78 uint8_t rtcWakeup : 1; // 0
Wayne Roberts 1:497af0bd9e53 79 uint8_t rfu : 1; // 1
Wayne Roberts 1:497af0bd9e53 80 uint8_t warmStart : 1; // 2
Wayne Roberts 1:497af0bd9e53 81 } bits;
Wayne Roberts 1:497af0bd9e53 82 uint8_t octet;
Wayne Roberts 1:497af0bd9e53 83 } sleepConfig_t;
Wayne Roberts 1:497af0bd9e53 84
Wayne Roberts 1:497af0bd9e53 85 typedef union {
Wayne Roberts 1:497af0bd9e53 86 struct {
Wayne Roberts 1:497af0bd9e53 87 uint8_t PreambleLengthHi; // param1
Wayne Roberts 1:497af0bd9e53 88 uint8_t PreambleLengthLo; // param2
Wayne Roberts 1:497af0bd9e53 89 uint8_t HeaderType; // param3
Wayne Roberts 1:497af0bd9e53 90 uint8_t PayloadLength; // param4
Wayne Roberts 1:497af0bd9e53 91 uint8_t CRCType; // param5
Wayne Roberts 1:497af0bd9e53 92 uint8_t InvertIQ; // param6
Wayne Roberts 1:497af0bd9e53 93 uint8_t unused[2];
Wayne Roberts 1:497af0bd9e53 94 } lora;
Wayne Roberts 1:497af0bd9e53 95 struct {
Wayne Roberts 1:497af0bd9e53 96 uint8_t PreambleLengthHi; // param1
Wayne Roberts 1:497af0bd9e53 97 uint8_t PreambleLengthLo; // param2
Wayne Roberts 1:497af0bd9e53 98 uint8_t PreambleDetectorLength; // param3
Wayne Roberts 1:497af0bd9e53 99 uint8_t SyncWordLength; // param4
Wayne Roberts 1:497af0bd9e53 100 uint8_t AddrComp; // param5
Wayne Roberts 1:497af0bd9e53 101 uint8_t PacketType; // param6
Wayne Roberts 1:497af0bd9e53 102 uint8_t PayloadLength; // param7
Wayne Roberts 1:497af0bd9e53 103 uint8_t CRCType; // param8
Wayne Roberts 1:497af0bd9e53 104 } gfsk;
Wayne Roberts 1:497af0bd9e53 105 uint8_t buf[8];
Wayne Roberts 1:497af0bd9e53 106 } PacketParams_t;
Wayne Roberts 1:497af0bd9e53 107
Wayne Roberts 1:497af0bd9e53 108
Wayne Roberts 1:497af0bd9e53 109 #define LORA_BW_7 0x00 // 7.81 kHz real
Wayne Roberts 1:497af0bd9e53 110 #define LORA_BW_10 0x08 // 10.42 kHz real
Wayne Roberts 1:497af0bd9e53 111 #define LORA_BW_15 0x01 // 15.63 kHz real
Wayne Roberts 1:497af0bd9e53 112 #define LORA_BW_20 0x09 // 20.83 kHz real
Wayne Roberts 1:497af0bd9e53 113 #define LORA_BW_31 0x02 // 31.25 kHz real
Wayne Roberts 1:497af0bd9e53 114 #define LORA_BW_41 0x0A // 41.67 kHz real
Wayne Roberts 1:497af0bd9e53 115 #define LORA_BW_62 0x03 // 62.50 kHz real
Wayne Roberts 1:497af0bd9e53 116 #define LORA_BW_125 0x04 // 125 kHz real
Wayne Roberts 1:497af0bd9e53 117 #define LORA_BW_250 0x05 // 250 kHz real
Wayne Roberts 1:497af0bd9e53 118 #define LORA_BW_500 0x06 // 500 kHz real
Wayne Roberts 1:497af0bd9e53 119
Wayne Roberts 1:497af0bd9e53 120 #define LORA_CR_4_5 1
Wayne Roberts 1:497af0bd9e53 121 #define LORA_CR_4_6 2
Wayne Roberts 1:497af0bd9e53 122 #define LORA_CR_4_7 3
Wayne Roberts 1:497af0bd9e53 123 #define LORA_CR_4_8 4
Wayne Roberts 1:497af0bd9e53 124
Wayne Roberts 1:497af0bd9e53 125 #define GFSK_PREAMBLE_DETECTOR_OFF 0x00
Wayne Roberts 1:497af0bd9e53 126 #define GFSK_PREAMBLE_DETECTOR_LENGTH_8BITS 0x04
Wayne Roberts 1:497af0bd9e53 127 #define GFSK_PREAMBLE_DETECTOR_LENGTH_16BITS 0x05
Wayne Roberts 1:497af0bd9e53 128 #define GFSK_PREAMBLE_DETECTOR_LENGTH_24BITS 0x06
Wayne Roberts 1:497af0bd9e53 129 #define GFSK_PREAMBLE_DETECTOR_LENGTH_32BITS 0x07
Wayne Roberts 1:497af0bd9e53 130
Wayne Roberts 1:497af0bd9e53 131 #define GFSK_CRC_OFF 0x01
Wayne Roberts 1:497af0bd9e53 132 #define GFSK_CRC_1_BYTE 0x00
Wayne Roberts 1:497af0bd9e53 133 #define GFSK_CRC_2_BYTE 0x02
Wayne Roberts 1:497af0bd9e53 134 #define GFSK_CRC_1_BYTE_INV 0x04
Wayne Roberts 1:497af0bd9e53 135 #define GFSK_CRC_2_BYTE_INV 0x06
Wayne Roberts 1:497af0bd9e53 136
Wayne Roberts 1:497af0bd9e53 137 #define GFSK_RX_BW_4800 0x1F
Wayne Roberts 1:497af0bd9e53 138 #define GFSK_RX_BW_5800 0x17
Wayne Roberts 1:497af0bd9e53 139 #define GFSK_RX_BW_7300 0x0F
Wayne Roberts 1:497af0bd9e53 140 #define GFSK_RX_BW_9700 0x1E
Wayne Roberts 1:497af0bd9e53 141 #define GFSK_RX_BW_11700 0x16
Wayne Roberts 1:497af0bd9e53 142 #define GFSK_RX_BW_14600 0x0E
Wayne Roberts 1:497af0bd9e53 143 #define GFSK_RX_BW_19500 0x1D
Wayne Roberts 1:497af0bd9e53 144 #define GFSK_RX_BW_23400 0x15
Wayne Roberts 1:497af0bd9e53 145 #define GFSK_RX_BW_29300 0x0D
Wayne Roberts 1:497af0bd9e53 146 #define GFSK_RX_BW_39000 0x1C
Wayne Roberts 1:497af0bd9e53 147 #define GFSK_RX_BW_46900 0x14
Wayne Roberts 1:497af0bd9e53 148 #define GFSK_RX_BW_58600 0x0C
Wayne Roberts 1:497af0bd9e53 149 #define GFSK_RX_BW_78200 0x1B
Wayne Roberts 1:497af0bd9e53 150 #define GFSK_RX_BW_93800 0x13
Wayne Roberts 1:497af0bd9e53 151 #define GFSK_RX_BW_117300 0x0B
Wayne Roberts 1:497af0bd9e53 152 #define GFSK_RX_BW_156200 0x1A
Wayne Roberts 1:497af0bd9e53 153 #define GFSK_RX_BW_187200 0x12
Wayne Roberts 1:497af0bd9e53 154 #define GFSK_RX_BW_234300 0x0A
Wayne Roberts 1:497af0bd9e53 155 #define GFSK_RX_BW_312000 0x19
Wayne Roberts 1:497af0bd9e53 156 #define GFSK_RX_BW_373600 0x11
Wayne Roberts 1:497af0bd9e53 157 #define GFSK_RX_BW_467000 0x09
Wayne Roberts 1:497af0bd9e53 158
Wayne Roberts 1:497af0bd9e53 159 #define GFSK_SHAPE_NONE 0x00
Wayne Roberts 1:497af0bd9e53 160 #define GFSK_SHAPE_BT0_3 0x08
Wayne Roberts 1:497af0bd9e53 161 #define GFSK_SHAPE_BT0_5 0x09
Wayne Roberts 1:497af0bd9e53 162 #define GFSK_SHAPE_BT0_7 0x0a
Wayne Roberts 1:497af0bd9e53 163 #define GFSK_SHAPE_BT1_0 0x0b
Wayne Roberts 1:497af0bd9e53 164
Wayne Roberts 1:497af0bd9e53 165 typedef enum {
Wayne Roberts 1:497af0bd9e53 166 STBY_RC = 0,
Wayne Roberts 1:497af0bd9e53 167 STBY_XOSC
Wayne Roberts 1:497af0bd9e53 168 } stby_t;
Wayne Roberts 1:497af0bd9e53 169
Wayne Roberts 1:497af0bd9e53 170 typedef union {
Wayne Roberts 1:497af0bd9e53 171 struct {
Wayne Roberts 1:497af0bd9e53 172 uint8_t spreadingFactor; // param1
Wayne Roberts 1:497af0bd9e53 173 uint8_t bandwidth; // param2
Wayne Roberts 1:497af0bd9e53 174 uint8_t codingRate; // param3
Wayne Roberts 1:497af0bd9e53 175 uint8_t LowDatarateOptimize; // param4
Wayne Roberts 1:497af0bd9e53 176 } lora;
Wayne Roberts 1:497af0bd9e53 177 struct {
Wayne Roberts 1:497af0bd9e53 178 uint8_t bitrateHi; // param1
Wayne Roberts 1:497af0bd9e53 179 uint8_t bitrateMid; // param2
Wayne Roberts 1:497af0bd9e53 180 uint8_t bitrateLo; // param3
Wayne Roberts 1:497af0bd9e53 181 uint8_t PulseShape; // param4
Wayne Roberts 1:497af0bd9e53 182 uint8_t bandwith; // param5
Wayne Roberts 1:497af0bd9e53 183 uint8_t fdevHi; // param6
Wayne Roberts 1:497af0bd9e53 184 uint8_t fdevMid; // param7
Wayne Roberts 1:497af0bd9e53 185 uint8_t fdevLo; // param8
Wayne Roberts 1:497af0bd9e53 186 } gfsk;
Wayne Roberts 1:497af0bd9e53 187 uint8_t buf[8];
Wayne Roberts 1:497af0bd9e53 188 } ModulationParams_t;
Wayne Roberts 1:497af0bd9e53 189
Wayne Roberts 1:497af0bd9e53 190 typedef union {
Wayne Roberts 1:497af0bd9e53 191 struct { //
Wayne Roberts 1:497af0bd9e53 192 uint8_t TxDone : 1; // 0
Wayne Roberts 1:497af0bd9e53 193 uint8_t RxDone : 1; // 1
Wayne Roberts 1:497af0bd9e53 194 uint8_t PreambleDetected : 1; // 2
Wayne Roberts 1:497af0bd9e53 195 uint8_t SyncWordValid : 1; // 3
Wayne Roberts 1:497af0bd9e53 196 uint8_t HeaderValid : 1; // 4
Wayne Roberts 1:497af0bd9e53 197 uint8_t HeaderErr : 1; // 5
Wayne Roberts 1:497af0bd9e53 198 uint8_t CrCerr : 1; // 6
Wayne Roberts 1:497af0bd9e53 199 uint8_t CadDone : 1; // 7
Wayne Roberts 1:497af0bd9e53 200 uint8_t CadDetected : 1; // 8
Wayne Roberts 1:497af0bd9e53 201 uint8_t Timeout : 1; // 9
Wayne Roberts 1:497af0bd9e53 202 } bits;
Wayne Roberts 1:497af0bd9e53 203 uint16_t word;
Wayne Roberts 1:497af0bd9e53 204 } IrqFlags_t;
Wayne Roberts 1:497af0bd9e53 205
Wayne Roberts 1:497af0bd9e53 206 typedef union {
Wayne Roberts 1:497af0bd9e53 207 struct { //
Wayne Roberts 1:497af0bd9e53 208 uint8_t _reserved : 1; // 0
Wayne Roberts 1:497af0bd9e53 209 uint8_t cmdStatus : 3; // 1,2,3
Wayne Roberts 1:497af0bd9e53 210 uint8_t chipMode : 3; // 4,5,6
Wayne Roberts 1:497af0bd9e53 211 uint8_t reserved_ : 1; // 7
Wayne Roberts 1:497af0bd9e53 212 } bits;
Wayne Roberts 1:497af0bd9e53 213 uint8_t octet;
Wayne Roberts 1:497af0bd9e53 214 } status_t;
Wayne Roberts 1:497af0bd9e53 215
Wayne Roberts 1:497af0bd9e53 216 typedef enum {
Wayne Roberts 1:497af0bd9e53 217 CHIPMODE_NONE = 0,
Wayne Roberts 1:497af0bd9e53 218 CHIPMODE_RX,
Wayne Roberts 1:497af0bd9e53 219 CHIPMODE_TX
Wayne Roberts 1:497af0bd9e53 220 } chipMote_e;
Wayne Roberts 1:497af0bd9e53 221
Wayne Roberts 1:497af0bd9e53 222 class SX126x {
Wayne Roberts 1:497af0bd9e53 223 public:
Wayne Roberts 1:497af0bd9e53 224 SX126x(SPI&, PinName nss, PinName busy, PinName dio1);
Wayne Roberts 1:497af0bd9e53 225
Wayne Roberts 1:497af0bd9e53 226
Wayne Roberts 1:497af0bd9e53 227 void hw_reset(PinName nrst);
Wayne Roberts 1:497af0bd9e53 228 void xfer(uint8_t opcode, uint8_t len, uint8_t* buf);
Wayne Roberts 1:497af0bd9e53 229 void setPacketType(uint8_t);
Wayne Roberts 1:497af0bd9e53 230 uint8_t setMHz(float);
Wayne Roberts 1:497af0bd9e53 231
Wayne Roberts 1:497af0bd9e53 232 /* start_tx and start_rx assumes DIO1 is connected, and only pin used to generate radio interrupt */
Wayne Roberts 1:497af0bd9e53 233 void start_tx(uint8_t pktLen); // tx_buf must be filled prior to calling
Wayne Roberts 1:497af0bd9e53 234
Wayne Roberts 1:497af0bd9e53 235 #define RX_TIMEOUT_SINGLE 0x000000 /* stop RX after first packet */
Wayne Roberts 1:497af0bd9e53 236 #define RX_TIMEOUT_CONTINUOUS 0xffffff /* keep RXing */
Wayne Roberts 1:497af0bd9e53 237 void start_rx(unsigned);
Wayne Roberts 1:497af0bd9e53 238
Wayne Roberts 1:497af0bd9e53 239 void ReadBuffer(uint8_t size);
Wayne Roberts 1:497af0bd9e53 240 void SetDIO2AsRfSwitchCtrl(uint8_t);
Wayne Roberts 1:497af0bd9e53 241 void set_tx_dbm(bool is1262, int8_t dbm);
Wayne Roberts 1:497af0bd9e53 242 uint32_t readReg(uint16_t addr, uint8_t len);
Wayne Roberts 1:497af0bd9e53 243 void writeReg(uint16_t addr, uint32_t data, uint8_t len);
Wayne Roberts 1:497af0bd9e53 244 void setStandby(stby_t);
Wayne Roberts 1:497af0bd9e53 245 void setSleep(bool warmStart, bool rtcWakeup);
Wayne Roberts 1:497af0bd9e53 246
Wayne Roberts 1:497af0bd9e53 247 static Callback<void()> dio1_topHalf; // low latency ISR context
Wayne Roberts 1:497af0bd9e53 248 void service(void);
Wayne Roberts 1:497af0bd9e53 249 Callback<void()> txDone; // user context
Wayne Roberts 1:497af0bd9e53 250 void (*rxDone)(uint8_t size, float rssi, float snr); // user context
Wayne Roberts 1:497af0bd9e53 251 void (*timeout)(bool tx); // user context
Wayne Roberts 1:497af0bd9e53 252
Wayne Roberts 1:497af0bd9e53 253 //! RF transmit packet buffer
Wayne Roberts 1:497af0bd9e53 254 uint8_t tx_buf[256]; // lora fifo size
Wayne Roberts 1:497af0bd9e53 255
Wayne Roberts 1:497af0bd9e53 256 //! RF receive packet buffer
Wayne Roberts 1:497af0bd9e53 257 uint8_t rx_buf[256]; // lora fifo size
Wayne Roberts 1:497af0bd9e53 258
Wayne Roberts 1:497af0bd9e53 259 /** Test if dio1 pin is asserted
Wayne Roberts 1:497af0bd9e53 260 */
Wayne Roberts 1:497af0bd9e53 261 inline bool getDIO1(void) { return dio1.read(); }
Wayne Roberts 1:497af0bd9e53 262 void PrintChipStatus(status_t);
Wayne Roberts 1:497af0bd9e53 263 //bool txing;
Wayne Roberts 1:497af0bd9e53 264 chipMote_e chipMode;
Wayne Roberts 1:497af0bd9e53 265
Wayne Roberts 1:497af0bd9e53 266 private:
Wayne Roberts 1:497af0bd9e53 267 SPI& spi;
Wayne Roberts 1:497af0bd9e53 268 DigitalOut nss;
Wayne Roberts 1:497af0bd9e53 269 DigitalIn busy;
Wayne Roberts 1:497af0bd9e53 270 InterruptIn dio1;
Wayne Roberts 1:497af0bd9e53 271 static void dio1isr(void);
Wayne Roberts 1:497af0bd9e53 272 bool sleeping;
Wayne Roberts 1:497af0bd9e53 273 };
Wayne Roberts 1:497af0bd9e53 274
Wayne Roberts 1:497af0bd9e53 275 #endif /* SX126x_H */
Wayne Roberts 1:497af0bd9e53 276