wayne roberts / sx126x

sx1261/2 driver

Dependents:   alarm_slave iq_sx126x sx126x_simple_TX_shield_2020a sx126x_simple_RX_shield_2020a ... more

Driver for SX1261 or SX1262

sx12xx.h@3:f6f2f8adcd22, 2018-07-03 (annotated)

Committer:
Wayne Roberts
Date:
Tue Jul 03 15:38:55 2018 -0700
Revision:
3:f6f2f8adcd22
Parent:
2:e6e159c8ab4d
Child:
4:b941bceb401d
add getPacketType

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Wayne Roberts 1:497af0bd9e53 1 #include "mbed.h"
Wayne Roberts 1:497af0bd9e53 2 #ifndef SX126x_H
Wayne Roberts 1:497af0bd9e53 3 #define SX126x_H
Wayne Roberts 1:497af0bd9e53 4
Wayne Roberts 1:497af0bd9e53 5 #define RC_TICKS_PER_MS 0.015625 /* 64KHz */
Wayne Roberts 1:497af0bd9e53 6 #define RC_TICKS_PER_US 15.625 /* 64KHz */
Wayne Roberts 1:497af0bd9e53 7
Wayne Roberts 2:e6e159c8ab4d 8 #define XTAL_FREQ_HZ 32000000
Wayne Roberts 1:497af0bd9e53 9 #define FREQ_DIV 33554432
Wayne Roberts 1:497af0bd9e53 10 #define FREQ_STEP 0.95367431640625 // ( ( double )( XTAL_FREQ / ( double )FREQ_DIV ) )
Wayne Roberts 2:e6e159c8ab4d 11 #define MHZ_TO_FRF 1048576 // = (1<<25) / Fxtal_MHz
Wayne Roberts 2:e6e159c8ab4d 12 #define KHZ_TO_FRF 1048.576
Wayne Roberts 1:497af0bd9e53 13
Wayne Roberts 1:497af0bd9e53 14 /***************************************************************/
Wayne Roberts 1:497af0bd9e53 15 #define OPCODE_CLEAR_IRQ_STATUS 0x02
Wayne Roberts 1:497af0bd9e53 16 #define OPCODE_CLEAR_DEVICE_ERRORS 0x07
Wayne Roberts 1:497af0bd9e53 17 #define OPCODE_SET_DIO_IRQ_PARAMS 0x08
Wayne Roberts 1:497af0bd9e53 18 #define OPCODE_WRITE_REGISTER 0x0d
Wayne Roberts 1:497af0bd9e53 19 #define OPCODE_WRITE_BUFFER 0x0e
Wayne Roberts 1:497af0bd9e53 20 #define OPCODE_GET_PACKET_TYPE 0x11
Wayne Roberts 1:497af0bd9e53 21 #define OPCODE_GET_IRQ_STATUS 0x12
Wayne Roberts 1:497af0bd9e53 22 #define OPCODE_GET_RX_BUFFER_STATUS 0x13
Wayne Roberts 1:497af0bd9e53 23 #define OPCODE_GET_PACKET_STATUS 0x14
Wayne Roberts 1:497af0bd9e53 24 #define OPCODE_GET_RSSIINST 0x15
Wayne Roberts 1:497af0bd9e53 25 #define OPCODE_GET_DEVICE_ERRORS 0x17
Wayne Roberts 1:497af0bd9e53 26 #define OPCODE_READ_REGISTER 0x1d
Wayne Roberts 1:497af0bd9e53 27 #define OPCODE_READ_BUFFER 0x1e
Wayne Roberts 1:497af0bd9e53 28 #define OPCODE_SET_STANDBY 0x80
Wayne Roberts 1:497af0bd9e53 29 #define OPCODE_SET_RX 0x82
Wayne Roberts 1:497af0bd9e53 30 #define OPCODE_SET_TX 0x83
Wayne Roberts 1:497af0bd9e53 31 #define OPCODE_SET_SLEEP 0x84
Wayne Roberts 1:497af0bd9e53 32 #define OPCODE_SET_RF_FREQUENCY 0x86
Wayne Roberts 1:497af0bd9e53 33 #define OPCODE_CALIBRATE 0x89
Wayne Roberts 1:497af0bd9e53 34 #define OPCODE_SET_PACKET_TYPE 0x8a
Wayne Roberts 1:497af0bd9e53 35 #define OPCODE_SET_MODULATION_PARAMS 0x8b
Wayne Roberts 1:497af0bd9e53 36 #define OPCODE_SET_PACKET_PARAMS 0x8c
Wayne Roberts 1:497af0bd9e53 37 #define OPCODE_SET_TX_PARAMS 0x8e
Wayne Roberts 1:497af0bd9e53 38 #define OPCODE_SET_BUFFER_BASE_ADDR 0x8f
Wayne Roberts 1:497af0bd9e53 39 #define OPCODE_SET_PA_CONFIG 0x95
Wayne Roberts 1:497af0bd9e53 40 #define OPCODE_SET_REGULATOR_MODE 0x96
Wayne Roberts 1:497af0bd9e53 41 #define OPCODE_SET_DIO3_AS_TCXO_CTRL 0x97
Wayne Roberts 1:497af0bd9e53 42 #define OPCODE_SET_DIO2_AS_RFSWITCH 0x9d
Wayne Roberts 1:497af0bd9e53 43 #define OPCODE_SET_LORA_SYMBOL_TIMEOUT 0xa0
Wayne Roberts 1:497af0bd9e53 44 #define OPCODE_GET_STATUS 0xc0
Wayne Roberts 1:497af0bd9e53 45 #define OPCODE_SET_TX_CONTINUOUS 0xd1
Wayne Roberts 1:497af0bd9e53 46 /***************************************************************/
Wayne Roberts 3:f6f2f8adcd22 47 #define PACKET_TYPE_GFSK 0
Wayne Roberts 1:497af0bd9e53 48 #define PACKET_TYPE_LORA 1
Wayne Roberts 1:497af0bd9e53 49
Wayne Roberts 1:497af0bd9e53 50 #define HEADER_TYPE_VARIABLE_LENGTH 0
Wayne Roberts 1:497af0bd9e53 51 #define HEADER_TYPE_FIXED_LENGTH 1
Wayne Roberts 1:497af0bd9e53 52
Wayne Roberts 1:497af0bd9e53 53 #define CRC_OFF 0
Wayne Roberts 1:497af0bd9e53 54 #define CRC_ON 0
Wayne Roberts 1:497af0bd9e53 55
Wayne Roberts 1:497af0bd9e53 56 #define STANDARD_IQ 0
Wayne Roberts 1:497af0bd9e53 57 #define INVERTED_IQ 1
Wayne Roberts 1:497af0bd9e53 58
Wayne Roberts 1:497af0bd9e53 59 /* direct register access */
Wayne Roberts 2:e6e159c8ab4d 60 #define REG_ADDR_IRQ_STATUS 0x58a // 16bit
Wayne Roberts 2:e6e159c8ab4d 61 #define REG_ADDR_IRQ_MASK 0x58c // 16bit
Wayne Roberts 2:e6e159c8ab4d 62 #define REG_ADDR_MODCFG 0x680 // 8bit
Wayne Roberts 2:e6e159c8ab4d 63 #define REG_ADDR_BITRATE 0x6a1 // 24bit fsk
Wayne Roberts 2:e6e159c8ab4d 64 #define REG_ADDR_FREQDEV 0x6a4 // 18bit fsk
Wayne Roberts 2:e6e159c8ab4d 65 #define REG_ADDR_SHAPECFG 0x6a7 // 5bit
Wayne Roberts 2:e6e159c8ab4d 66 #define REG_ADDR_FSK_PKTCTRL0 0x6b3 // 8bit
Wayne Roberts 2:e6e159c8ab4d 67 #define REG_ADDR_FSK_PKTCTRL1 0x6b4 // 3bit
Wayne Roberts 2:e6e159c8ab4d 68 #define REG_ADDR_FSK_PREAMBLE_TXLEN 0x6b5 // 16bit
Wayne Roberts 2:e6e159c8ab4d 69 #define REG_ADDR_FSK_SYNC_LEN 0x6b7 // 7bit
Wayne Roberts 2:e6e159c8ab4d 70 #define REG_ADDR_FSK_PKTCTRL2 0x6ba // 8bit
Wayne Roberts 2:e6e159c8ab4d 71 #define REG_ADDR_FSK_PAYLOAD_LEN 0x6bb // 8bit
Wayne Roberts 2:e6e159c8ab4d 72 #define REG_ADDR_SYNCADDR 0x6c0 // 64bit fsk
Wayne Roberts 2:e6e159c8ab4d 73 #define REG_ADDR_NODEADDR 0x6cd // 8bit fsk
Wayne Roberts 2:e6e159c8ab4d 74 #define REG_ADDR_NODEADDRCOMP 0x6cf // 2bit fsk
Wayne Roberts 2:e6e159c8ab4d 75
Wayne Roberts 2:e6e159c8ab4d 76 #define REG_ADDR_LORA_TXPKTLEN 0x702 // 8bit
Wayne Roberts 2:e6e159c8ab4d 77 #define REG_ADDR_LORA_CONFIG0 0x703 // 8bit bw/sf
Wayne Roberts 2:e6e159c8ab4d 78 #define REG_ADDR_LORA_CONFIG1 0x704 // 8bit ppm_offset, fixlen, invertiq, cr
Wayne Roberts 2:e6e159c8ab4d 79 #define REG_ADDR_LORA_CONFIG2 0x705 // 8bit crcType
Wayne Roberts 2:e6e159c8ab4d 80 #define REG_ADDR_LORA_IRQ_MASK 0x70a // 24bit
Wayne Roberts 2:e6e159c8ab4d 81 #define REG_ADDR_LORA_PREAMBLE_SYMBNB 0x73a // 16bit
Wayne Roberts 2:e6e159c8ab4d 82 #define REG_ADDR_LORA_SYNC 0x740 // config22, config23: frame sync peak position
Wayne Roberts 2:e6e159c8ab4d 83
Wayne Roberts 2:e6e159c8ab4d 84 #define REG_ADDR_DIGFECTL 0x804 // 6bits
Wayne Roberts 2:e6e159c8ab4d 85 #define REG_ADDR_BWSEL 0x807 // 5bits
Wayne Roberts 2:e6e159c8ab4d 86 #define REG_ADDR_RANDOM 0x819 // ro
Wayne Roberts 2:e6e159c8ab4d 87 #define REG_ADDR_RFFREQ 0x88b // 31bits
Wayne Roberts 2:e6e159c8ab4d 88 #define REG_ADDR_FREQ_OFFSET 0x88f // 19bits
Wayne Roberts 2:e6e159c8ab4d 89 #define REG_ADDR_ANACTRL6 0x8d7 // 6bits
Wayne Roberts 2:e6e159c8ab4d 90 #define REG_ADDR_ANACTRL7 0x8d8 // 6bits
Wayne Roberts 2:e6e159c8ab4d 91 #define REG_ADDR_ANACTRL15 0x8e1 // 7bits
Wayne Roberts 2:e6e159c8ab4d 92 #define REG_ADDR_OCP 0x8e7
Wayne Roberts 2:e6e159c8ab4d 93 #define REG_ADDR_ 0x
Wayne Roberts 2:e6e159c8ab4d 94
Wayne Roberts 2:e6e159c8ab4d 95 /**********************************************/
Wayne Roberts 1:497af0bd9e53 96
Wayne Roberts 1:497af0bd9e53 97 #define SET_RAMP_10U 0x00
Wayne Roberts 1:497af0bd9e53 98 #define SET_RAMP_20U 0x01
Wayne Roberts 1:497af0bd9e53 99 #define SET_RAMP_40U 0x02
Wayne Roberts 1:497af0bd9e53 100 #define SET_RAMP_80U 0x03
Wayne Roberts 1:497af0bd9e53 101 #define SET_RAMP_200U 0x04
Wayne Roberts 1:497af0bd9e53 102 #define SET_RAMP_800U 0x05
Wayne Roberts 1:497af0bd9e53 103 #define SET_RAMP_1700U 0x06
Wayne Roberts 1:497af0bd9e53 104 #define SET_RAMP_3400U 0x07
Wayne Roberts 1:497af0bd9e53 105
Wayne Roberts 1:497af0bd9e53 106
Wayne Roberts 1:497af0bd9e53 107
Wayne Roberts 1:497af0bd9e53 108 typedef union {
Wayne Roberts 1:497af0bd9e53 109 struct {
Wayne Roberts 1:497af0bd9e53 110 uint8_t rtcWakeup : 1; // 0
Wayne Roberts 1:497af0bd9e53 111 uint8_t rfu : 1; // 1
Wayne Roberts 1:497af0bd9e53 112 uint8_t warmStart : 1; // 2
Wayne Roberts 1:497af0bd9e53 113 } bits;
Wayne Roberts 1:497af0bd9e53 114 uint8_t octet;
Wayne Roberts 1:497af0bd9e53 115 } sleepConfig_t;
Wayne Roberts 1:497af0bd9e53 116
Wayne Roberts 1:497af0bd9e53 117 typedef union {
Wayne Roberts 1:497af0bd9e53 118 struct {
Wayne Roberts 1:497af0bd9e53 119 uint8_t PreambleLengthHi; // param1
Wayne Roberts 1:497af0bd9e53 120 uint8_t PreambleLengthLo; // param2
Wayne Roberts 1:497af0bd9e53 121 uint8_t HeaderType; // param3
Wayne Roberts 1:497af0bd9e53 122 uint8_t PayloadLength; // param4
Wayne Roberts 1:497af0bd9e53 123 uint8_t CRCType; // param5
Wayne Roberts 1:497af0bd9e53 124 uint8_t InvertIQ; // param6
Wayne Roberts 1:497af0bd9e53 125 uint8_t unused[2];
Wayne Roberts 1:497af0bd9e53 126 } lora;
Wayne Roberts 1:497af0bd9e53 127 struct {
Wayne Roberts 1:497af0bd9e53 128 uint8_t PreambleLengthHi; // param1
Wayne Roberts 1:497af0bd9e53 129 uint8_t PreambleLengthLo; // param2
Wayne Roberts 1:497af0bd9e53 130 uint8_t PreambleDetectorLength; // param3
Wayne Roberts 1:497af0bd9e53 131 uint8_t SyncWordLength; // param4
Wayne Roberts 1:497af0bd9e53 132 uint8_t AddrComp; // param5
Wayne Roberts 1:497af0bd9e53 133 uint8_t PacketType; // param6
Wayne Roberts 1:497af0bd9e53 134 uint8_t PayloadLength; // param7
Wayne Roberts 1:497af0bd9e53 135 uint8_t CRCType; // param8
Wayne Roberts 2:e6e159c8ab4d 136 uint8_t Whitening; // param9
Wayne Roberts 1:497af0bd9e53 137 } gfsk;
Wayne Roberts 1:497af0bd9e53 138 uint8_t buf[8];
Wayne Roberts 1:497af0bd9e53 139 } PacketParams_t;
Wayne Roberts 1:497af0bd9e53 140
Wayne Roberts 1:497af0bd9e53 141
Wayne Roberts 1:497af0bd9e53 142 #define LORA_BW_7 0x00 // 7.81 kHz real
Wayne Roberts 1:497af0bd9e53 143 #define LORA_BW_10 0x08 // 10.42 kHz real
Wayne Roberts 1:497af0bd9e53 144 #define LORA_BW_15 0x01 // 15.63 kHz real
Wayne Roberts 1:497af0bd9e53 145 #define LORA_BW_20 0x09 // 20.83 kHz real
Wayne Roberts 1:497af0bd9e53 146 #define LORA_BW_31 0x02 // 31.25 kHz real
Wayne Roberts 1:497af0bd9e53 147 #define LORA_BW_41 0x0A // 41.67 kHz real
Wayne Roberts 1:497af0bd9e53 148 #define LORA_BW_62 0x03 // 62.50 kHz real
Wayne Roberts 1:497af0bd9e53 149 #define LORA_BW_125 0x04 // 125 kHz real
Wayne Roberts 1:497af0bd9e53 150 #define LORA_BW_250 0x05 // 250 kHz real
Wayne Roberts 1:497af0bd9e53 151 #define LORA_BW_500 0x06 // 500 kHz real
Wayne Roberts 1:497af0bd9e53 152
Wayne Roberts 1:497af0bd9e53 153 #define LORA_CR_4_5 1
Wayne Roberts 1:497af0bd9e53 154 #define LORA_CR_4_6 2
Wayne Roberts 1:497af0bd9e53 155 #define LORA_CR_4_7 3
Wayne Roberts 1:497af0bd9e53 156 #define LORA_CR_4_8 4
Wayne Roberts 1:497af0bd9e53 157
Wayne Roberts 1:497af0bd9e53 158 #define GFSK_PREAMBLE_DETECTOR_OFF 0x00
Wayne Roberts 1:497af0bd9e53 159 #define GFSK_PREAMBLE_DETECTOR_LENGTH_8BITS 0x04
Wayne Roberts 1:497af0bd9e53 160 #define GFSK_PREAMBLE_DETECTOR_LENGTH_16BITS 0x05
Wayne Roberts 1:497af0bd9e53 161 #define GFSK_PREAMBLE_DETECTOR_LENGTH_24BITS 0x06
Wayne Roberts 1:497af0bd9e53 162 #define GFSK_PREAMBLE_DETECTOR_LENGTH_32BITS 0x07
Wayne Roberts 1:497af0bd9e53 163
Wayne Roberts 2:e6e159c8ab4d 164 #define GFSK_WHITENING_OFF 0
Wayne Roberts 2:e6e159c8ab4d 165 #define GFSK_WHITENING_ON 1
Wayne Roberts 2:e6e159c8ab4d 166
Wayne Roberts 1:497af0bd9e53 167 #define GFSK_CRC_OFF 0x01
Wayne Roberts 1:497af0bd9e53 168 #define GFSK_CRC_1_BYTE 0x00
Wayne Roberts 1:497af0bd9e53 169 #define GFSK_CRC_2_BYTE 0x02
Wayne Roberts 1:497af0bd9e53 170 #define GFSK_CRC_1_BYTE_INV 0x04
Wayne Roberts 1:497af0bd9e53 171 #define GFSK_CRC_2_BYTE_INV 0x06
Wayne Roberts 1:497af0bd9e53 172
Wayne Roberts 1:497af0bd9e53 173 #define GFSK_RX_BW_4800 0x1F
Wayne Roberts 1:497af0bd9e53 174 #define GFSK_RX_BW_5800 0x17
Wayne Roberts 1:497af0bd9e53 175 #define GFSK_RX_BW_7300 0x0F
Wayne Roberts 1:497af0bd9e53 176 #define GFSK_RX_BW_9700 0x1E
Wayne Roberts 1:497af0bd9e53 177 #define GFSK_RX_BW_11700 0x16
Wayne Roberts 1:497af0bd9e53 178 #define GFSK_RX_BW_14600 0x0E
Wayne Roberts 1:497af0bd9e53 179 #define GFSK_RX_BW_19500 0x1D
Wayne Roberts 1:497af0bd9e53 180 #define GFSK_RX_BW_23400 0x15
Wayne Roberts 1:497af0bd9e53 181 #define GFSK_RX_BW_29300 0x0D
Wayne Roberts 1:497af0bd9e53 182 #define GFSK_RX_BW_39000 0x1C
Wayne Roberts 1:497af0bd9e53 183 #define GFSK_RX_BW_46900 0x14
Wayne Roberts 1:497af0bd9e53 184 #define GFSK_RX_BW_58600 0x0C
Wayne Roberts 1:497af0bd9e53 185 #define GFSK_RX_BW_78200 0x1B
Wayne Roberts 1:497af0bd9e53 186 #define GFSK_RX_BW_93800 0x13
Wayne Roberts 1:497af0bd9e53 187 #define GFSK_RX_BW_117300 0x0B
Wayne Roberts 1:497af0bd9e53 188 #define GFSK_RX_BW_156200 0x1A
Wayne Roberts 1:497af0bd9e53 189 #define GFSK_RX_BW_187200 0x12
Wayne Roberts 1:497af0bd9e53 190 #define GFSK_RX_BW_234300 0x0A
Wayne Roberts 1:497af0bd9e53 191 #define GFSK_RX_BW_312000 0x19
Wayne Roberts 1:497af0bd9e53 192 #define GFSK_RX_BW_373600 0x11
Wayne Roberts 1:497af0bd9e53 193 #define GFSK_RX_BW_467000 0x09
Wayne Roberts 1:497af0bd9e53 194
Wayne Roberts 1:497af0bd9e53 195 #define GFSK_SHAPE_NONE 0x00
Wayne Roberts 1:497af0bd9e53 196 #define GFSK_SHAPE_BT0_3 0x08
Wayne Roberts 1:497af0bd9e53 197 #define GFSK_SHAPE_BT0_5 0x09
Wayne Roberts 1:497af0bd9e53 198 #define GFSK_SHAPE_BT0_7 0x0a
Wayne Roberts 1:497af0bd9e53 199 #define GFSK_SHAPE_BT1_0 0x0b
Wayne Roberts 1:497af0bd9e53 200
Wayne Roberts 1:497af0bd9e53 201 typedef enum {
Wayne Roberts 1:497af0bd9e53 202 STBY_RC = 0,
Wayne Roberts 1:497af0bd9e53 203 STBY_XOSC
Wayne Roberts 1:497af0bd9e53 204 } stby_t;
Wayne Roberts 1:497af0bd9e53 205
Wayne Roberts 2:e6e159c8ab4d 206 #define MOD_TYPE_IQ 0
Wayne Roberts 2:e6e159c8ab4d 207 #define MOD_TYPE_FSK 1
Wayne Roberts 2:e6e159c8ab4d 208 #define MOD_TYPE_MSK 2
Wayne Roberts 2:e6e159c8ab4d 209 #define MOD_TYPE_LORA 3
Wayne Roberts 2:e6e159c8ab4d 210 typedef union {
Wayne Roberts 2:e6e159c8ab4d 211 struct {
Wayne Roberts 2:e6e159c8ab4d 212 uint8_t mod_order : 2; // 0,1 modulation size 2points to 16points
Wayne Roberts 2:e6e159c8ab4d 213 uint8_t mod_type : 2; // 2,3 IQ, FSK, MSK, LoRa
Wayne Roberts 2:e6e159c8ab4d 214 uint8_t data_src : 1; // 4
Wayne Roberts 2:e6e159c8ab4d 215 uint8_t clk_src : 2; // 5,6
Wayne Roberts 2:e6e159c8ab4d 216 uint8_t mod_en : 1; // 7
Wayne Roberts 2:e6e159c8ab4d 217 } bits;
Wayne Roberts 2:e6e159c8ab4d 218 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 219 } modCfg_t; // at 0x680 fsk
Wayne Roberts 2:e6e159c8ab4d 220
Wayne Roberts 2:e6e159c8ab4d 221 typedef union {
Wayne Roberts 2:e6e159c8ab4d 222 struct {
Wayne Roberts 2:e6e159c8ab4d 223 uint8_t bt : 2; // 0,1 0=BT1.0 1=BT0.5 2=BT0.3
Wayne Roberts 2:e6e159c8ab4d 224 uint8_t double_rate : 1; // 2 double oversampling rate
Wayne Roberts 2:e6e159c8ab4d 225 uint8_t pulse_shape : 2; // 3,4 0=noFilter 1=gaussian 2=RRC
Wayne Roberts 2:e6e159c8ab4d 226 uint8_t res : 3; // 5,6,7
Wayne Roberts 2:e6e159c8ab4d 227 } bits;
Wayne Roberts 2:e6e159c8ab4d 228 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 229 } shapeCfg_t; // at 0x6a7 fsk
Wayne Roberts 2:e6e159c8ab4d 230
Wayne Roberts 2:e6e159c8ab4d 231 typedef union {
Wayne Roberts 2:e6e159c8ab4d 232 struct {
Wayne Roberts 2:e6e159c8ab4d 233 uint8_t pkt_start_p : 1; // 0 ros1
Wayne Roberts 2:e6e159c8ab4d 234 uint8_t pkt_abort_p : 1; // 1 ros1
Wayne Roberts 2:e6e159c8ab4d 235 uint8_t pkt_sw_clr_p : 1; // 2 ros1
Wayne Roberts 2:e6e159c8ab4d 236 uint8_t crl_status_p : 1; // 3 ros1
Wayne Roberts 2:e6e159c8ab4d 237 uint8_t clk_en : 1; // 4 ro
Wayne Roberts 2:e6e159c8ab4d 238 uint8_t pkt_rx_ntx : 1; // 5
Wayne Roberts 2:e6e159c8ab4d 239 uint8_t pkt_len_format : 1; // 6
Wayne Roberts 2:e6e159c8ab4d 240 uint8_t cont_rx : 1; // 7
Wayne Roberts 2:e6e159c8ab4d 241 } bits;
Wayne Roberts 2:e6e159c8ab4d 242 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 243 } pktCtrl0_t; // at 0x6b3 fsk
Wayne Roberts 2:e6e159c8ab4d 244
Wayne Roberts 2:e6e159c8ab4d 245 typedef union {
Wayne Roberts 2:e6e159c8ab4d 246 struct {
Wayne Roberts 2:e6e159c8ab4d 247 uint8_t preamble_len_rx : 2; // 0,1 number of preamble bits detected
Wayne Roberts 2:e6e159c8ab4d 248 uint8_t preamble_det_on : 1; // 2 enable rx-sde preamble detector
Wayne Roberts 2:e6e159c8ab4d 249 uint8_t res : 1; // 7
Wayne Roberts 2:e6e159c8ab4d 250 } bits;
Wayne Roberts 2:e6e159c8ab4d 251 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 252 } pktCtrl1_t; // at 0x6b4 fsk
Wayne Roberts 2:e6e159c8ab4d 253
Wayne Roberts 2:e6e159c8ab4d 254 typedef union {
Wayne Roberts 2:e6e159c8ab4d 255 struct {
Wayne Roberts 2:e6e159c8ab4d 256 uint8_t crc_disable : 1; // 0
Wayne Roberts 2:e6e159c8ab4d 257 uint8_t crc_len : 1; // 1 0=1byte 1=2byte
Wayne Roberts 2:e6e159c8ab4d 258 uint8_t crc_inv : 1; // 2
Wayne Roberts 2:e6e159c8ab4d 259 uint8_t crc_in_fifo : 1; // 3
Wayne Roberts 2:e6e159c8ab4d 260 uint8_t whit_enable : 1; // 4
Wayne Roberts 2:e6e159c8ab4d 261 uint8_t manchester_en : 1; // 5
Wayne Roberts 2:e6e159c8ab4d 262 uint8_t rssi_mode : 2; // 6,7
Wayne Roberts 2:e6e159c8ab4d 263 } bits;
Wayne Roberts 2:e6e159c8ab4d 264 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 265 } pktCtrl2_t; // at 0x6ba fsk
Wayne Roberts 2:e6e159c8ab4d 266
Wayne Roberts 2:e6e159c8ab4d 267
Wayne Roberts 2:e6e159c8ab4d 268 typedef union {
Wayne Roberts 2:e6e159c8ab4d 269 struct {
Wayne Roberts 2:e6e159c8ab4d 270 uint8_t modem_sf: 4; // 0,1,2,3
Wayne Roberts 2:e6e159c8ab4d 271 uint8_t modem_bw: 4; // 4,5,6,7
Wayne Roberts 2:e6e159c8ab4d 272 } bits;
Wayne Roberts 2:e6e159c8ab4d 273 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 274 } loraConfig0_t; // at 0x703
Wayne Roberts 2:e6e159c8ab4d 275
Wayne Roberts 2:e6e159c8ab4d 276 typedef union {
Wayne Roberts 2:e6e159c8ab4d 277 struct {
Wayne Roberts 2:e6e159c8ab4d 278 uint8_t tx_coding_rate : 3; // 0,1,2
Wayne Roberts 2:e6e159c8ab4d 279 uint8_t ppm_offset : 2; // 3,4 aka long range mode
Wayne Roberts 2:e6e159c8ab4d 280 uint8_t tx_mode : 1; // 5
Wayne Roberts 2:e6e159c8ab4d 281 uint8_t rx_invert_iq : 1; // 6
Wayne Roberts 2:e6e159c8ab4d 282 uint8_t implicit_header : 1; // 7 0=variable length packet
Wayne Roberts 2:e6e159c8ab4d 283 } bits;
Wayne Roberts 2:e6e159c8ab4d 284 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 285 } loraConfig1_t; // at 0x704
Wayne Roberts 2:e6e159c8ab4d 286
Wayne Roberts 2:e6e159c8ab4d 287 typedef union {
Wayne Roberts 2:e6e159c8ab4d 288 struct {
Wayne Roberts 2:e6e159c8ab4d 289 uint8_t cad_rxtx : 2; // 0,1
Wayne Roberts 2:e6e159c8ab4d 290 uint8_t tx_payload_crc16_en : 1; // 2
Wayne Roberts 2:e6e159c8ab4d 291 uint8_t cont_rx : 1; // 3
Wayne Roberts 2:e6e159c8ab4d 292 uint8_t freeze_dagc_upon_synch : 2; // 4,5
Wayne Roberts 2:e6e159c8ab4d 293 uint8_t fine_sync_en : 1; // 6
Wayne Roberts 2:e6e159c8ab4d 294 uint8_t res : 1; // 7
Wayne Roberts 2:e6e159c8ab4d 295 } bits;
Wayne Roberts 2:e6e159c8ab4d 296 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 297 } loraConfig2_t; // at 0x705
Wayne Roberts 2:e6e159c8ab4d 298
Wayne Roberts 2:e6e159c8ab4d 299 typedef union {
Wayne Roberts 2:e6e159c8ab4d 300 struct {
Wayne Roberts 2:e6e159c8ab4d 301 uint8_t inv_edge : 1; // 0
Wayne Roberts 2:e6e159c8ab4d 302 uint8_t swap_iq : 1; // 1
Wayne Roberts 2:e6e159c8ab4d 303 uint8_t dig_fe_clear : 1; // 2
Wayne Roberts 2:e6e159c8ab4d 304 uint8_t lora_ngfsk : 1; // 3 data buffer selection lora/gfsk
Wayne Roberts 2:e6e159c8ab4d 305 uint8_t adc_from_dio : 1; // 4
Wayne Roberts 2:e6e159c8ab4d 306 uint8_t lora_pre_cf_en : 1; // 5
Wayne Roberts 2:e6e159c8ab4d 307 uint8_t res : 2; // 6,7
Wayne Roberts 2:e6e159c8ab4d 308 } bits;
Wayne Roberts 2:e6e159c8ab4d 309 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 310 } digFeCtrl_t; // at 0x804
Wayne Roberts 2:e6e159c8ab4d 311
Wayne Roberts 2:e6e159c8ab4d 312 typedef union {
Wayne Roberts 2:e6e159c8ab4d 313 struct {
Wayne Roberts 2:e6e159c8ab4d 314 uint8_t exp : 3; // 0,1,2
Wayne Roberts 2:e6e159c8ab4d 315 uint8_t mant : 2; // 3,4
Wayne Roberts 2:e6e159c8ab4d 316 uint8_t res : 3; // 5,6,7
Wayne Roberts 2:e6e159c8ab4d 317 } bits;
Wayne Roberts 2:e6e159c8ab4d 318 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 319 } bwSel_t; // at 0x807 rx_bw
Wayne Roberts 2:e6e159c8ab4d 320
Wayne Roberts 2:e6e159c8ab4d 321 typedef union {
Wayne Roberts 2:e6e159c8ab4d 322 struct {
Wayne Roberts 2:e6e159c8ab4d 323 uint8_t pa_hp_ena_ana : 1; // 0
Wayne Roberts 2:e6e159c8ab4d 324 uint8_t tx_ena_bat : 1; // 1
Wayne Roberts 2:e6e159c8ab4d 325 uint8_t pa_dctrim_select_ana : 4; // 2,3,4,5
Wayne Roberts 2:e6e159c8ab4d 326 uint8_t res : 2; // 6,7
Wayne Roberts 2:e6e159c8ab4d 327 } bits;
Wayne Roberts 2:e6e159c8ab4d 328 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 329 } AnaCtrl6_t; // at 0x8d7
Wayne Roberts 2:e6e159c8ab4d 330
Wayne Roberts 2:e6e159c8ab4d 331 typedef union {
Wayne Roberts 2:e6e159c8ab4d 332 struct {
Wayne Roberts 2:e6e159c8ab4d 333 uint8_t pa_lp_ena_ana : 1; // 0
Wayne Roberts 2:e6e159c8ab4d 334 uint8_t pa_clamp_code_bat : 3; // 1,2,3
Wayne Roberts 2:e6e159c8ab4d 335 uint8_t pa_clamp_override_bat : 1; // 4
Wayne Roberts 2:e6e159c8ab4d 336 uint8_t pa_hp_sel_ana : 1; // 5,6,7
Wayne Roberts 2:e6e159c8ab4d 337 } bits;
Wayne Roberts 2:e6e159c8ab4d 338 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 339 } AnaCtrl7_t; // at 0x8d8
Wayne Roberts 2:e6e159c8ab4d 340
Wayne Roberts 2:e6e159c8ab4d 341 typedef union {
Wayne Roberts 2:e6e159c8ab4d 342 struct {
Wayne Roberts 2:e6e159c8ab4d 343 uint8_t reg_pa_comp_poarity_ana : 1; // 0
Wayne Roberts 2:e6e159c8ab4d 344 uint8_t reg_pa_comp_en_ana : 1; // 1
Wayne Roberts 2:e6e159c8ab4d 345 uint8_t fir_dac_sign_ana : 2; // 2,3
Wayne Roberts 2:e6e159c8ab4d 346 uint8_t fir_dac_pole_ana : 3; // 4,5,6
Wayne Roberts 2:e6e159c8ab4d 347 uint8_t res : 1; // 7
Wayne Roberts 2:e6e159c8ab4d 348 } bits;
Wayne Roberts 2:e6e159c8ab4d 349 uint8_t octet;
Wayne Roberts 2:e6e159c8ab4d 350 } AnaCtrl15_t; // at 0x8e1
Wayne Roberts 2:e6e159c8ab4d 351
Wayne Roberts 1:497af0bd9e53 352 typedef union {
Wayne Roberts 1:497af0bd9e53 353 struct {
Wayne Roberts 1:497af0bd9e53 354 uint8_t spreadingFactor; // param1
Wayne Roberts 1:497af0bd9e53 355 uint8_t bandwidth; // param2
Wayne Roberts 1:497af0bd9e53 356 uint8_t codingRate; // param3
Wayne Roberts 1:497af0bd9e53 357 uint8_t LowDatarateOptimize; // param4
Wayne Roberts 1:497af0bd9e53 358 } lora;
Wayne Roberts 1:497af0bd9e53 359 struct {
Wayne Roberts 1:497af0bd9e53 360 uint8_t bitrateHi; // param1
Wayne Roberts 1:497af0bd9e53 361 uint8_t bitrateMid; // param2
Wayne Roberts 1:497af0bd9e53 362 uint8_t bitrateLo; // param3
Wayne Roberts 1:497af0bd9e53 363 uint8_t PulseShape; // param4
Wayne Roberts 2:e6e159c8ab4d 364 uint8_t bandwidth; // param5
Wayne Roberts 2:e6e159c8ab4d 365 uint8_t fdevHi; // param6
Wayne Roberts 1:497af0bd9e53 366 uint8_t fdevMid; // param7
Wayne Roberts 2:e6e159c8ab4d 367 uint8_t fdevLo; // param8
Wayne Roberts 1:497af0bd9e53 368 } gfsk;
Wayne Roberts 1:497af0bd9e53 369 uint8_t buf[8];
Wayne Roberts 1:497af0bd9e53 370 } ModulationParams_t;
Wayne Roberts 1:497af0bd9e53 371
Wayne Roberts 1:497af0bd9e53 372 typedef union {
Wayne Roberts 1:497af0bd9e53 373 struct { //
Wayne Roberts 3:f6f2f8adcd22 374 uint16_t TxDone : 1; // 0
Wayne Roberts 3:f6f2f8adcd22 375 uint16_t RxDone : 1; // 1
Wayne Roberts 3:f6f2f8adcd22 376 uint16_t PreambleDetected : 1; // 2
Wayne Roberts 3:f6f2f8adcd22 377 uint16_t SyncWordValid : 1; // 3
Wayne Roberts 3:f6f2f8adcd22 378 uint16_t HeaderValid : 1; // 4
Wayne Roberts 3:f6f2f8adcd22 379 uint16_t HeaderErr : 1; // 5
Wayne Roberts 3:f6f2f8adcd22 380 uint16_t CrCerr : 1; // 6
Wayne Roberts 3:f6f2f8adcd22 381 uint16_t CadDone : 1; // 7
Wayne Roberts 3:f6f2f8adcd22 382 uint16_t CadDetected : 1; // 8
Wayne Roberts 3:f6f2f8adcd22 383 uint16_t Timeout : 1; // 9
Wayne Roberts 3:f6f2f8adcd22 384 uint16_t res : 6; // 10,11,12,13,14,15
Wayne Roberts 1:497af0bd9e53 385 } bits;
Wayne Roberts 1:497af0bd9e53 386 uint16_t word;
Wayne Roberts 1:497af0bd9e53 387 } IrqFlags_t;
Wayne Roberts 1:497af0bd9e53 388
Wayne Roberts 1:497af0bd9e53 389 typedef union {
Wayne Roberts 1:497af0bd9e53 390 struct { //
Wayne Roberts 1:497af0bd9e53 391 uint8_t _reserved : 1; // 0
Wayne Roberts 1:497af0bd9e53 392 uint8_t cmdStatus : 3; // 1,2,3
Wayne Roberts 1:497af0bd9e53 393 uint8_t chipMode : 3; // 4,5,6
Wayne Roberts 1:497af0bd9e53 394 uint8_t reserved_ : 1; // 7
Wayne Roberts 1:497af0bd9e53 395 } bits;
Wayne Roberts 1:497af0bd9e53 396 uint8_t octet;
Wayne Roberts 1:497af0bd9e53 397 } status_t;
Wayne Roberts 1:497af0bd9e53 398
Wayne Roberts 1:497af0bd9e53 399 typedef enum {
Wayne Roberts 1:497af0bd9e53 400 CHIPMODE_NONE = 0,
Wayne Roberts 1:497af0bd9e53 401 CHIPMODE_RX,
Wayne Roberts 1:497af0bd9e53 402 CHIPMODE_TX
Wayne Roberts 1:497af0bd9e53 403 } chipMote_e;
Wayne Roberts 1:497af0bd9e53 404
Wayne Roberts 1:497af0bd9e53 405 class SX126x {
Wayne Roberts 1:497af0bd9e53 406 public:
Wayne Roberts 1:497af0bd9e53 407 SX126x(SPI&, PinName nss, PinName busy, PinName dio1);
Wayne Roberts 1:497af0bd9e53 408
Wayne Roberts 1:497af0bd9e53 409
Wayne Roberts 1:497af0bd9e53 410 void hw_reset(PinName nrst);
Wayne Roberts 2:e6e159c8ab4d 411 void xfer(uint8_t opcode, uint8_t writeLen, uint8_t readLen, uint8_t* buf);
Wayne Roberts 1:497af0bd9e53 412 void setPacketType(uint8_t);
Wayne Roberts 3:f6f2f8adcd22 413 uint8_t getPacketType(void);
Wayne Roberts 1:497af0bd9e53 414 uint8_t setMHz(float);
Wayne Roberts 2:e6e159c8ab4d 415 float getMHz(void);
Wayne Roberts 1:497af0bd9e53 416
Wayne Roberts 1:497af0bd9e53 417 /* start_tx and start_rx assumes DIO1 is connected, and only pin used to generate radio interrupt */
Wayne Roberts 1:497af0bd9e53 418 void start_tx(uint8_t pktLen); // tx_buf must be filled prior to calling
Wayne Roberts 1:497af0bd9e53 419
Wayne Roberts 1:497af0bd9e53 420 #define RX_TIMEOUT_SINGLE 0x000000 /* stop RX after first packet */
Wayne Roberts 1:497af0bd9e53 421 #define RX_TIMEOUT_CONTINUOUS 0xffffff /* keep RXing */
Wayne Roberts 1:497af0bd9e53 422 void start_rx(unsigned);
Wayne Roberts 1:497af0bd9e53 423
Wayne Roberts 2:e6e159c8ab4d 424 void ReadBuffer(uint8_t size, uint8_t offset);
Wayne Roberts 1:497af0bd9e53 425 void SetDIO2AsRfSwitchCtrl(uint8_t);
Wayne Roberts 1:497af0bd9e53 426 void set_tx_dbm(bool is1262, int8_t dbm);
Wayne Roberts 1:497af0bd9e53 427 uint32_t readReg(uint16_t addr, uint8_t len);
Wayne Roberts 1:497af0bd9e53 428 void writeReg(uint16_t addr, uint32_t data, uint8_t len);
Wayne Roberts 1:497af0bd9e53 429 void setStandby(stby_t);
Wayne Roberts 1:497af0bd9e53 430 void setSleep(bool warmStart, bool rtcWakeup);
Wayne Roberts 1:497af0bd9e53 431
Wayne Roberts 1:497af0bd9e53 432 static Callback<void()> dio1_topHalf; // low latency ISR context
Wayne Roberts 1:497af0bd9e53 433 void service(void);
Wayne Roberts 1:497af0bd9e53 434 Callback<void()> txDone; // user context
Wayne Roberts 1:497af0bd9e53 435 void (*rxDone)(uint8_t size, float rssi, float snr); // user context
Wayne Roberts 1:497af0bd9e53 436 void (*timeout)(bool tx); // user context
Wayne Roberts 1:497af0bd9e53 437
Wayne Roberts 1:497af0bd9e53 438 //! RF transmit packet buffer
Wayne Roberts 1:497af0bd9e53 439 uint8_t tx_buf[256]; // lora fifo size
Wayne Roberts 1:497af0bd9e53 440
Wayne Roberts 1:497af0bd9e53 441 //! RF receive packet buffer
Wayne Roberts 1:497af0bd9e53 442 uint8_t rx_buf[256]; // lora fifo size
Wayne Roberts 1:497af0bd9e53 443
Wayne Roberts 1:497af0bd9e53 444 /** Test if dio1 pin is asserted
Wayne Roberts 1:497af0bd9e53 445 */
Wayne Roberts 1:497af0bd9e53 446 inline bool getDIO1(void) { return dio1.read(); }
Wayne Roberts 1:497af0bd9e53 447 void PrintChipStatus(status_t);
Wayne Roberts 1:497af0bd9e53 448 chipMote_e chipMode;
Wayne Roberts 1:497af0bd9e53 449
Wayne Roberts 1:497af0bd9e53 450 private:
Wayne Roberts 1:497af0bd9e53 451 SPI& spi;
Wayne Roberts 1:497af0bd9e53 452 DigitalOut nss;
Wayne Roberts 1:497af0bd9e53 453 DigitalIn busy;
Wayne Roberts 1:497af0bd9e53 454 InterruptIn dio1;
Wayne Roberts 1:497af0bd9e53 455 static void dio1isr(void);
Wayne Roberts 1:497af0bd9e53 456 bool sleeping;
Wayne Roberts 1:497af0bd9e53 457 };
Wayne Roberts 1:497af0bd9e53 458
Wayne Roberts 1:497af0bd9e53 459 #endif /* SX126x_H */
Wayne Roberts 1:497af0bd9e53 460