Diff: i2c_mbed_fpga.cpp

Revision:

15:83bbc18cccbc

Parent:

14:062850afdf38

Child:

16:a0bfe33f8a4a

diff -r 062850afdf38 -r 83bbc18cccbc i2c_mbed_fpga.cpp
--- a/i2c_mbed_fpga.cpp	Thu Apr 22 11:35:17 2021 +0000
+++ b/i2c_mbed_fpga.cpp	Wed May 12 10:09:04 2021 +0000
@@ -31,29 +31,61 @@
 
 /** i2c enter key to open I2C window
 */
-int i2c_mbed_fpga::i2c_window_open(){
+//int i2c_mbed_fpga::i2c_window_open(){
+//    char i2cMessage[3];
+//    *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
+//    *(i2cMessage+1) = (char)(0xD0)& 0xff;
+//    *(i2cMessage+2) = (char)(0xD0)& 0xff;  
+//    return i2c_word_write(i2cMessage);
+//}
+
+/** i2c enter key to Start the motor
+*/
+//int i2c_mbed_fpga::i2c_motor_start(){
+//    char i2cMessage[3];
+//    *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
+//    *(i2cMessage+1) = (char)(0xCA)& 0xff;
+//    *(i2cMessage+2) = (char)(0xFE)& 0xff;  
+//    return i2c_word_write(i2cMessage);
+//}
+
+
+/** i2c enter key to open I2C configuration mode entry
+*/
+int i2c_mbed_fpga::i2c_config_mode_entry(){
     char i2cMessage[3];
-    *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
-    *(i2cMessage+1) = (char)(0xD0)& 0xff;
-    *(i2cMessage+2) = (char)(0xD0)& 0xff;  
+    *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
+    *(i2cMessage+1) = (char)(0x1D)& 0xff;
+    *(i2cMessage+2) = (char)(0xEA)& 0xff;  
     return i2c_word_write(i2cMessage);
 }
 
-/** i2c enter key to Start the motor
+/** i2c ram start up flag set to skip OTP copy 
 */
-int i2c_mbed_fpga::i2c_motor_start(){
+int i2c_mbed_fpga::i2c_skip_app_copy(){
     char i2cMessage[3];
-    *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
-    *(i2cMessage+1) = (char)(0xCA)& 0xff;
-    *(i2cMessage+2) = (char)(0xFE)& 0xff;  
+    *(i2cMessage+0) = (char)(I2C_STARTUP_FLAGS_1)& 0xff;
+    *(i2cMessage+1) = (char)(0x05)& 0xff;
+    *(i2cMessage+2) = (char)(0x00)& 0xff;  
     return i2c_word_write(i2cMessage);
 }
 
+/** i2c soft reset 
+*/
+int i2c_mbed_fpga::i2c_soft_reset(){
+    char i2cMessage[3];
+    *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
+    *(i2cMessage+1) = (char)(0xC1)& 0xff;
+    *(i2cMessage+2) = (char)(0xA0)& 0xff;  
+    return i2c_word_write(i2cMessage);
+}
+
+
 /** i2c to set the 50k PWM
 */
 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
-    nv_gen_ctrl_val &= ~NV_PWM_36K_MASK;
-    nv_gen_ctrl_val |= pwm50k << NV_PWM_36K_OFFSET;
+    nv_gen_ctrl_val &= ~NV_PWM_50K_MASK;
+    nv_gen_ctrl_val |= pwm50k << NV_PWM_50K_OFFSET;
     char i2cMessage[3];
     *(i2cMessage+0) = (char)(I2C_GEN_CTRL >> 0)& 0xff;
     *(i2cMessage+1) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
@@ -253,12 +285,12 @@
 */
 int i2c_mbed_fpga::i2c_set_fall_time_blank(unsigned int blank_time){
     int ack = 0;
-    nv_gen_ctrl_val &= ~NV_FLAT_BANK_MASK;
-    nv_gen_ctrl_val |= blank_time << NV_FLAT_BANK_OFFSET;
+    nv_dig_config_val &= ~NV_FLAT_BLANK_MASK;
+    nv_dig_config_val |= blank_time << NV_FLAT_BLANK_OFFSET;
     char i2cMessage[3];
-    *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
-    *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
-    *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;  
+    *(i2cMessage+0)= (char)(I2C_DIGITAL_CFG >> 0)& 0xff;
+    *(i2cMessage+1)= (char)(nv_dig_config_val >> 8)& 0xff;
+    *(i2cMessage+2)= (char)(nv_dig_config_val >> 0)& 0xff;  
     ack += i2c_word_write(i2cMessage);
     
     return ack; 
@@ -269,16 +301,19 @@
 */
 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
     int ack = 0;
-    nv_comm_ctrl_val &= ~NV_I_ZC_TH_LOW_MASK;
-    nv_comm_ctrl_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
-    nv_comm_ctrl_val &= ~NV_I_ZC_TH_HIGH_MASK;
-    nv_comm_ctrl_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
+    nv_i_zc_th_low_val &= ~NV_I_ZC_TH_LOW_MASK;
+    nv_i_zc_th_low_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
+    nv_i_zc_th_high_val &= ~NV_I_ZC_TH_HIGH_MASK;
+    nv_i_zc_th_high_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
     char i2cMessage[3];
-    *(i2cMessage+0) = (char)(I2C_COMM >> 0)& 0xff;
-    *(i2cMessage+1) = (char)(nv_comm_ctrl_val >> 8)& 0xff;
-    *(i2cMessage+2) = (char)(nv_comm_ctrl_val >> 0)& 0xff;  
+    *(i2cMessage+0) = (char)(I2C_I_ZC_TH_LOW >> 0)& 0xff;
+    *(i2cMessage+1) = (char)(nv_i_zc_th_low_val >> 8)& 0xff;
+    *(i2cMessage+2) = (char)(nv_i_zc_th_low_val >> 0)& 0xff;  
     ack += i2c_word_write(i2cMessage);
-    
+    *(i2cMessage+0) = (char)(I2C_I_ZC_TH_HIGH >> 0)& 0xff;
+    *(i2cMessage+1) = (char)(nv_i_zc_th_high_val >> 8)& 0xff;
+    *(i2cMessage+2) = (char)(nv_i_zc_th_high_val >> 0)& 0xff;  
+    ack += i2c_word_write(i2cMessage);
     return ack; 
 }
 
@@ -286,16 +321,19 @@
 */
 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
     int ack = 0;
-    nv_comm_ctrl_val &= ~NV_DI_TH_1ST_MASK;
-    nv_comm_ctrl_val |= di_1st << NV_DI_TH_1ST_OFFSET;
-    nv_comm_ctrl_val &= ~NV_DI_TH_2ND_MASK;
-    nv_comm_ctrl_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
+    nv_di_th_1st_val &= ~NV_DI_TH_1ST_MASK;
+    nv_di_th_1st_val |= di_1st << NV_DI_TH_1ST_OFFSET;
+    nv_di_th_2nd_val &= ~NV_DI_TH_2ND_MASK;
+    nv_di_th_2nd_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
     char i2cMessage[3];
-    *(i2cMessage+0) = (char)(I2C_COMM >> 0)& 0xff;
-    *(i2cMessage+1) = (char)(nv_comm_ctrl_val >> 8)& 0xff;
-    *(i2cMessage+2) = (char)(nv_comm_ctrl_val >> 0)& 0xff;   
+    *(i2cMessage+0) = (char)(I2C_DI_TH_1ST >> 0)& 0xff;
+    *(i2cMessage+1) = (char)(nv_di_th_1st_val >> 8)& 0xff;
+    *(i2cMessage+2) = (char)(nv_di_th_1st_val >> 0)& 0xff;   
     ack += i2c_word_write(i2cMessage);
-    
+    *(i2cMessage+0) = (char)(I2C_DI_TH_2ND >> 0)& 0xff;
+    *(i2cMessage+1) = (char)(nv_di_th_2nd_val >> 8)& 0xff;
+    *(i2cMessage+2) = (char)(nv_di_th_2nd_val >> 0)& 0xff;   
+    ack += i2c_word_write(i2cMessage);
     return ack; 
 }