Ben Willems / Mbed 2 deprecated MLX90418_I2C_master_bwi

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Dependencies:   mbed

i2c_mbed_fpga.cpp@15:83bbc18cccbc, 2021-05-12 (annotated)

Committer:
wuliqunyy
Date:
Wed May 12 10:09:04 2021 +0000
Revision:
15:83bbc18cccbc
Parent:
14:062850afdf38
Child:
16:a0bfe33f8a4a
New start up communication state machine working

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 6:019ab407ac3c 3 DigitalOut led3(LED3);
wuliqunyy 0:fe3c7dde9771 4
wuliqunyy 6:019ab407ac3c 5 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 6 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 7 *
wuliqunyy 6:019ab407ac3c 8 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 9 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 10 */
wuliqunyy 6:019ab407ac3c 11 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 6:019ab407ac3c 12 int ack = 0;
wuliqunyy 14:062850afdf38 13 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 1, true); //restart
wuliqunyy 14:062850afdf38 14 ack += i2c_master.read(I2C_SLAVE_ADDR, word+1, 2, false); //stop bit
wuliqunyy 6:019ab407ac3c 15 wait_us(100);
wuliqunyy 6:019ab407ac3c 16 return (ack == 0) ? 0 : 1;
wuliqunyy 6:019ab407ac3c 17 }
wuliqunyy 0:fe3c7dde9771 18
wuliqunyy 0:fe3c7dde9771 19 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 20 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 21 *
wuliqunyy 0:fe3c7dde9771 22 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 23 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 24 */
wuliqunyy 5:daab0e0e67e2 25 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 26 int ack = 0;
wuliqunyy 14:062850afdf38 27 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 3, false);
wuliqunyy 6:019ab407ac3c 28 return ack;
wuliqunyy 0:fe3c7dde9771 29 }
wuliqunyy 0:fe3c7dde9771 30
wuliqunyy 0:fe3c7dde9771 31
wuliqunyy 5:daab0e0e67e2 32 /** i2c enter key to open I2C window
wuliqunyy 0:fe3c7dde9771 33 */
wuliqunyy 15:83bbc18cccbc 34 //int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 15:83bbc18cccbc 35 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 36 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 37 // *(i2cMessage+1) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 38 // *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 39 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 40 //}
wuliqunyy 15:83bbc18cccbc 41
wuliqunyy 15:83bbc18cccbc 42 /** i2c enter key to Start the motor
wuliqunyy 15:83bbc18cccbc 43 */
wuliqunyy 15:83bbc18cccbc 44 //int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 15:83bbc18cccbc 45 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 46 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 47 // *(i2cMessage+1) = (char)(0xCA)& 0xff;
wuliqunyy 15:83bbc18cccbc 48 // *(i2cMessage+2) = (char)(0xFE)& 0xff;
wuliqunyy 15:83bbc18cccbc 49 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 50 //}
wuliqunyy 15:83bbc18cccbc 51
wuliqunyy 15:83bbc18cccbc 52
wuliqunyy 15:83bbc18cccbc 53 /** i2c enter key to open I2C configuration mode entry
wuliqunyy 15:83bbc18cccbc 54 */
wuliqunyy 15:83bbc18cccbc 55 int i2c_mbed_fpga::i2c_config_mode_entry(){
wuliqunyy 14:062850afdf38 56 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 57 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 58 *(i2cMessage+1) = (char)(0x1D)& 0xff;
wuliqunyy 15:83bbc18cccbc 59 *(i2cMessage+2) = (char)(0xEA)& 0xff;
wuliqunyy 14:062850afdf38 60 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 61 }
wuliqunyy 0:fe3c7dde9771 62
wuliqunyy 15:83bbc18cccbc 63 /** i2c ram start up flag set to skip OTP copy
wuliqunyy 0:fe3c7dde9771 64 */
wuliqunyy 15:83bbc18cccbc 65 int i2c_mbed_fpga::i2c_skip_app_copy(){
wuliqunyy 14:062850afdf38 66 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 67 *(i2cMessage+0) = (char)(I2C_STARTUP_FLAGS_1)& 0xff;
wuliqunyy 15:83bbc18cccbc 68 *(i2cMessage+1) = (char)(0x05)& 0xff;
wuliqunyy 15:83bbc18cccbc 69 *(i2cMessage+2) = (char)(0x00)& 0xff;
wuliqunyy 14:062850afdf38 70 return i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 71 }
wuliqunyy 12:9f8c7f4da5f6 72
wuliqunyy 15:83bbc18cccbc 73 /** i2c soft reset
wuliqunyy 15:83bbc18cccbc 74 */
wuliqunyy 15:83bbc18cccbc 75 int i2c_mbed_fpga::i2c_soft_reset(){
wuliqunyy 15:83bbc18cccbc 76 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 77 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 78 *(i2cMessage+1) = (char)(0xC1)& 0xff;
wuliqunyy 15:83bbc18cccbc 79 *(i2cMessage+2) = (char)(0xA0)& 0xff;
wuliqunyy 15:83bbc18cccbc 80 return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 81 }
wuliqunyy 15:83bbc18cccbc 82
wuliqunyy 15:83bbc18cccbc 83
wuliqunyy 12:9f8c7f4da5f6 84 /** i2c to set the 50k PWM
wuliqunyy 12:9f8c7f4da5f6 85 */
wuliqunyy 12:9f8c7f4da5f6 86 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
wuliqunyy 15:83bbc18cccbc 87 nv_gen_ctrl_val &= ~NV_PWM_50K_MASK;
wuliqunyy 15:83bbc18cccbc 88 nv_gen_ctrl_val |= pwm50k << NV_PWM_50K_OFFSET;
wuliqunyy 14:062850afdf38 89 char i2cMessage[3];
wuliqunyy 14:062850afdf38 90 *(i2cMessage+0) = (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 91 *(i2cMessage+1) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 92 *(i2cMessage+2) = (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 93 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 94 }
wuliqunyy 6:019ab407ac3c 95
wuliqunyy 12:9f8c7f4da5f6 96
wuliqunyy 12:9f8c7f4da5f6 97
wuliqunyy 6:019ab407ac3c 98 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 99 */
wuliqunyy 6:019ab407ac3c 100 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 101 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 102 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 14:062850afdf38 103 char i2cMessage[3];
wuliqunyy 14:062850afdf38 104 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 105 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 106 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 107 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 108 }
wuliqunyy 6:019ab407ac3c 109
wuliqunyy 6:019ab407ac3c 110 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 111 */
wuliqunyy 6:019ab407ac3c 112 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 113 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 114 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 115 char i2cMessage[3];
wuliqunyy 14:062850afdf38 116 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 117 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 118 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 119 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 120 }
wuliqunyy 6:019ab407ac3c 121
wuliqunyy 6:019ab407ac3c 122 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 123 */
wuliqunyy 6:019ab407ac3c 124 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 125 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 126 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 14:062850afdf38 127 char i2cMessage[3];
wuliqunyy 14:062850afdf38 128 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 129 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 130 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 131 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 132 }
wuliqunyy 6:019ab407ac3c 133
wuliqunyy 6:019ab407ac3c 134 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 135 */
wuliqunyy 6:019ab407ac3c 136 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 137 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 138 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 14:062850afdf38 139 char i2cMessage[3];
wuliqunyy 14:062850afdf38 140 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 141 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 142 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 143 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 144 }
wuliqunyy 6:019ab407ac3c 145
wuliqunyy 6:019ab407ac3c 146
wuliqunyy 6:019ab407ac3c 147 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 148 */
wuliqunyy 6:019ab407ac3c 149 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 150 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 151 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 14:062850afdf38 152 char i2cMessage[3];
wuliqunyy 14:062850afdf38 153 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 154 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 155 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 156 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 157 }
wuliqunyy 6:019ab407ac3c 158
wuliqunyy 6:019ab407ac3c 159 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 160 */
wuliqunyy 6:019ab407ac3c 161 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 162 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 163 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 164 char i2cMessage[3];
wuliqunyy 14:062850afdf38 165 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 166 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 167 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 168 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 169 }
wuliqunyy 6:019ab407ac3c 170
wuliqunyy 6:019ab407ac3c 171 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 172 */
wuliqunyy 6:019ab407ac3c 173 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 174 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 175 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 14:062850afdf38 176 char i2cMessage[3];
wuliqunyy 14:062850afdf38 177 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 178 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 179 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 180 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 181 }
wuliqunyy 6:019ab407ac3c 182
wuliqunyy 6:019ab407ac3c 183 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 184 */
wuliqunyy 6:019ab407ac3c 185 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 186 int ack = 0;
wuliqunyy 6:019ab407ac3c 187 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 188 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 189 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 190 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 191 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 192 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 193 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 194 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 14:062850afdf38 195 char i2cMessage[3];
wuliqunyy 14:062850afdf38 196 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 197 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 198 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 199 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 200 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 201 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 202 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 203 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 204 *(i2cMessage+0) = (char)(I2C_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 14:062850afdf38 205 *(i2cMessage+1) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 206 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 207 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 208
wuliqunyy 6:019ab407ac3c 209 return ack;
wuliqunyy 6:019ab407ac3c 210 }
wuliqunyy 6:019ab407ac3c 211
wuliqunyy 6:019ab407ac3c 212 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 213 */
wuliqunyy 6:019ab407ac3c 214 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 215 int ack = 0;
wuliqunyy 6:019ab407ac3c 216 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 217 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 218 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 219 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 220 char i2cMessage[3];
wuliqunyy 14:062850afdf38 221 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 222 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 223 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 224 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 225 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 226 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 227 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 228 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 229
wuliqunyy 6:019ab407ac3c 230 return ack;
wuliqunyy 6:019ab407ac3c 231 }
wuliqunyy 6:019ab407ac3c 232
wuliqunyy 6:019ab407ac3c 233 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 234 */
wuliqunyy 6:019ab407ac3c 235 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 236 int ack = 0;
wuliqunyy 6:019ab407ac3c 237 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 238 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 239 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 240 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 241 char i2cMessage[3];
wuliqunyy 14:062850afdf38 242 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 243 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 244 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 245 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 246 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 247 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 248 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 249 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 250
wuliqunyy 6:019ab407ac3c 251 return ack;
wuliqunyy 9:76a0b9f29a2d 252 }
wuliqunyy 9:76a0b9f29a2d 253
wuliqunyy 14:062850afdf38 254 /** i2c to set the rough regulation gain
wuliqunyy 12:9f8c7f4da5f6 255 */
wuliqunyy 12:9f8c7f4da5f6 256 int i2c_mbed_fpga::i2c_set_rough_gain(unsigned int rough_gain){
wuliqunyy 12:9f8c7f4da5f6 257 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 258 nv_gen_ctrl_val &= ~NV_ROUGH_GAIN_MASK;
wuliqunyy 12:9f8c7f4da5f6 259 nv_gen_ctrl_val |= rough_gain << NV_ROUGH_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 260 char i2cMessage[3];
wuliqunyy 14:062850afdf38 261 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 262 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 263 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 264 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 265
wuliqunyy 12:9f8c7f4da5f6 266 return ack;
wuliqunyy 12:9f8c7f4da5f6 267 }
wuliqunyy 12:9f8c7f4da5f6 268
wuliqunyy 14:062850afdf38 269 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 270 */
wuliqunyy 14:062850afdf38 271 int i2c_mbed_fpga::i2c_set_ehp_reg_gain(unsigned int ehp_gain){
wuliqunyy 14:062850afdf38 272 int ack = 0;
wuliqunyy 14:062850afdf38 273 nv_gen_ctrl_val &= ~NV_EHP_REG_GAIN_MASK;
wuliqunyy 14:062850afdf38 274 nv_gen_ctrl_val |= ehp_gain << NV_EHP_REG_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 275 char i2cMessage[3];
wuliqunyy 14:062850afdf38 276 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 277 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 278 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 279 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 280
wuliqunyy 14:062850afdf38 281 return ack;
wuliqunyy 14:062850afdf38 282 }
wuliqunyy 14:062850afdf38 283
wuliqunyy 14:062850afdf38 284 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 285 */
wuliqunyy 14:062850afdf38 286 int i2c_mbed_fpga::i2c_set_fall_time_blank(unsigned int blank_time){
wuliqunyy 14:062850afdf38 287 int ack = 0;
wuliqunyy 15:83bbc18cccbc 288 nv_dig_config_val &= ~NV_FLAT_BLANK_MASK;
wuliqunyy 15:83bbc18cccbc 289 nv_dig_config_val |= blank_time << NV_FLAT_BLANK_OFFSET;
wuliqunyy 14:062850afdf38 290 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 291 *(i2cMessage+0)= (char)(I2C_DIGITAL_CFG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 292 *(i2cMessage+1)= (char)(nv_dig_config_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 293 *(i2cMessage+2)= (char)(nv_dig_config_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 294 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 295
wuliqunyy 14:062850afdf38 296 return ack;
wuliqunyy 14:062850afdf38 297 }
wuliqunyy 12:9f8c7f4da5f6 298
wuliqunyy 12:9f8c7f4da5f6 299
wuliqunyy 12:9f8c7f4da5f6 300 /** i2c to set the current threshold for I_didt
wuliqunyy 12:9f8c7f4da5f6 301 */
wuliqunyy 12:9f8c7f4da5f6 302 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
wuliqunyy 12:9f8c7f4da5f6 303 int ack = 0;
wuliqunyy 15:83bbc18cccbc 304 nv_i_zc_th_low_val &= ~NV_I_ZC_TH_LOW_MASK;
wuliqunyy 15:83bbc18cccbc 305 nv_i_zc_th_low_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
wuliqunyy 15:83bbc18cccbc 306 nv_i_zc_th_high_val &= ~NV_I_ZC_TH_HIGH_MASK;
wuliqunyy 15:83bbc18cccbc 307 nv_i_zc_th_high_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
wuliqunyy 14:062850afdf38 308 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 309 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_LOW >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 310 *(i2cMessage+1) = (char)(nv_i_zc_th_low_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 311 *(i2cMessage+2) = (char)(nv_i_zc_th_low_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 312 ack += i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 313 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_HIGH >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 314 *(i2cMessage+1) = (char)(nv_i_zc_th_high_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 315 *(i2cMessage+2) = (char)(nv_i_zc_th_high_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 316 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 317 return ack;
wuliqunyy 12:9f8c7f4da5f6 318 }
wuliqunyy 12:9f8c7f4da5f6 319
wuliqunyy 12:9f8c7f4da5f6 320 /** i2c to set the di current threshold for didt
wuliqunyy 12:9f8c7f4da5f6 321 */
wuliqunyy 12:9f8c7f4da5f6 322 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
wuliqunyy 12:9f8c7f4da5f6 323 int ack = 0;
wuliqunyy 15:83bbc18cccbc 324 nv_di_th_1st_val &= ~NV_DI_TH_1ST_MASK;
wuliqunyy 15:83bbc18cccbc 325 nv_di_th_1st_val |= di_1st << NV_DI_TH_1ST_OFFSET;
wuliqunyy 15:83bbc18cccbc 326 nv_di_th_2nd_val &= ~NV_DI_TH_2ND_MASK;
wuliqunyy 15:83bbc18cccbc 327 nv_di_th_2nd_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
wuliqunyy 14:062850afdf38 328 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 329 *(i2cMessage+0) = (char)(I2C_DI_TH_1ST >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 330 *(i2cMessage+1) = (char)(nv_di_th_1st_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 331 *(i2cMessage+2) = (char)(nv_di_th_1st_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 332 ack += i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 333 *(i2cMessage+0) = (char)(I2C_DI_TH_2ND >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 334 *(i2cMessage+1) = (char)(nv_di_th_2nd_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 335 *(i2cMessage+2) = (char)(nv_di_th_2nd_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 336 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 337 return ack;
wuliqunyy 12:9f8c7f4da5f6 338 }
wuliqunyy 12:9f8c7f4da5f6 339
wuliqunyy 12:9f8c7f4da5f6 340
wuliqunyy 12:9f8c7f4da5f6 341
wuliqunyy 12:9f8c7f4da5f6 342
wuliqunyy 11:b86aea372744 343 /** i2c to clean the I2C controller settins
wuliqunyy 11:b86aea372744 344 */
wuliqunyy 11:b86aea372744 345 int i2c_mbed_fpga::i2c_clear_spd_ctrl(){
wuliqunyy 11:b86aea372744 346 int ack = 0;
wuliqunyy 11:b86aea372744 347 nv_spd_control_1_val = 0;
wuliqunyy 11:b86aea372744 348 nv_spd_control_2_val = 0;
wuliqunyy 14:062850afdf38 349 char i2cMessage[3];
wuliqunyy 14:062850afdf38 350 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 351 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 352 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 353 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 354 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 355 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 356 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 357 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 358
wuliqunyy 11:b86aea372744 359 return ack;
wuliqunyy 11:b86aea372744 360 }
wuliqunyy 11:b86aea372744 361
wuliqunyy 14:062850afdf38 362 /** i2c to set the I2C speed input mode
wuliqunyy 14:062850afdf38 363 */
wuliqunyy 14:062850afdf38 364 int i2c_mbed_fpga::i2c_set_input_mode(unsigned int mode){
wuliqunyy 14:062850afdf38 365 int ack = 0;
wuliqunyy 14:062850afdf38 366 nv_application_cfg_val &= ~NV_INPUT_MODE_CFG_MASK;
wuliqunyy 14:062850afdf38 367 nv_application_cfg_val |= mode << NV_INPUT_MODE_CFG_OFFSET;
wuliqunyy 14:062850afdf38 368 char i2cMessage[3];
wuliqunyy 14:062850afdf38 369 *(i2cMessage+0) = (char)(I2C_APPLICATION_CFG >> 0)& 0xff;
wuliqunyy 14:062850afdf38 370 *(i2cMessage+1) = (char)(nv_application_cfg_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 371 *(i2cMessage+2) = (char)(nv_application_cfg_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 372 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 373 return ack;
wuliqunyy 14:062850afdf38 374 }
wuliqunyy 14:062850afdf38 375
wuliqunyy 14:062850afdf38 376
wuliqunyy 11:b86aea372744 377
wuliqunyy 9:76a0b9f29a2d 378 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 379 */
wuliqunyy 9:76a0b9f29a2d 380 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 381 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 382 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 383 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 14:062850afdf38 384 char i2cMessage[3];
wuliqunyy 14:062850afdf38 385 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 386 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 387 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 388 ack += i2c_word_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 389
wuliqunyy 9:76a0b9f29a2d 390 return ack;
wuliqunyy 9:76a0b9f29a2d 391 }
wuliqunyy 9:76a0b9f29a2d 392
wuliqunyy 12:9f8c7f4da5f6 393 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 12:9f8c7f4da5f6 394 */
wuliqunyy 12:9f8c7f4da5f6 395 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 12:9f8c7f4da5f6 396 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 397 ram_open_duty_val = duty;
wuliqunyy 14:062850afdf38 398 char i2cMessage[3];
wuliqunyy 14:062850afdf38 399 *(i2cMessage+0) = (char)(I2C_SPEED_DUTY)& 0xff;
wuliqunyy 14:062850afdf38 400 *(i2cMessage+1) = (char)(ram_open_duty_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 401 *(i2cMessage+2) = (char)(ram_open_duty_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 402 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 403
wuliqunyy 12:9f8c7f4da5f6 404 return ack;
wuliqunyy 12:9f8c7f4da5f6 405 }
wuliqunyy 12:9f8c7f4da5f6 406
wuliqunyy 11:b86aea372744 407 /** i2c to set the speed curve type
wuliqunyy 11:b86aea372744 408 */
wuliqunyy 11:b86aea372744 409 int i2c_mbed_fpga::i2c_set_curve_type(unsigned int curvetype){
wuliqunyy 11:b86aea372744 410 int ack = 0;
wuliqunyy 11:b86aea372744 411 nv_spd_control_1_val &= ~NV_CURVE_MODE_MASK;
wuliqunyy 11:b86aea372744 412 nv_spd_control_1_val |= curvetype << NV_CURVE_MODE_OFFSET;
wuliqunyy 14:062850afdf38 413 char i2cMessage[3];
wuliqunyy 14:062850afdf38 414 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 415 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 416 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 417 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 418
wuliqunyy 11:b86aea372744 419 return ack;
wuliqunyy 11:b86aea372744 420 }
wuliqunyy 11:b86aea372744 421
wuliqunyy 11:b86aea372744 422 /** i2c to set the open dc ini
wuliqunyy 11:b86aea372744 423 */
wuliqunyy 11:b86aea372744 424 int i2c_mbed_fpga::i2c_set_dc_ini(unsigned int ini){
wuliqunyy 11:b86aea372744 425 int ack = 0;
wuliqunyy 11:b86aea372744 426 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_INI_MASK;
wuliqunyy 11:b86aea372744 427 nv_spd_control_2_val |= ini << NV_DC_OPENLOOP_INI_OFFSET;
wuliqunyy 14:062850afdf38 428 char i2cMessage[3];
wuliqunyy 14:062850afdf38 429 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 430 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 431 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 432 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 433
wuliqunyy 11:b86aea372744 434 return ack;
wuliqunyy 11:b86aea372744 435 }
wuliqunyy 11:b86aea372744 436
wuliqunyy 11:b86aea372744 437 /** i2c to set the open dc slew rate
wuliqunyy 11:b86aea372744 438 */
wuliqunyy 11:b86aea372744 439 int i2c_mbed_fpga::i2c_set_dc_sr(unsigned int sr){
wuliqunyy 11:b86aea372744 440 int ack = 0;
wuliqunyy 11:b86aea372744 441 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_SR_MASK;
wuliqunyy 11:b86aea372744 442 nv_spd_control_2_val |= sr << NV_DC_OPENLOOP_SR_OFFSET;
wuliqunyy 14:062850afdf38 443 char i2cMessage[3];
wuliqunyy 14:062850afdf38 444 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 445 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 446 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 447 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 448
wuliqunyy 11:b86aea372744 449 return ack;
wuliqunyy 11:b86aea372744 450 }
wuliqunyy 11:b86aea372744 451
wuliqunyy 12:9f8c7f4da5f6 452