Ben Willems / Mbed 2 deprecated MLX90418_I2C_master_bwi

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Dependencies:   mbed

i2c_mbed_fpga.cpp@14:062850afdf38, 2021-04-22 (annotated)

Committer:
wuliqunyy
Date:
Thu Apr 22 11:35:17 2021 +0000
Revision:
14:062850afdf38
Parent:
12:9f8c7f4da5f6
Child:
15:83bbc18cccbc
working version with DOE2 CL;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 6:019ab407ac3c 3 DigitalOut led3(LED3);
wuliqunyy 0:fe3c7dde9771 4
wuliqunyy 6:019ab407ac3c 5 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 6 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 7 *
wuliqunyy 6:019ab407ac3c 8 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 9 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 10 */
wuliqunyy 6:019ab407ac3c 11 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 6:019ab407ac3c 12 int ack = 0;
wuliqunyy 14:062850afdf38 13 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 1, true); //restart
wuliqunyy 14:062850afdf38 14 ack += i2c_master.read(I2C_SLAVE_ADDR, word+1, 2, false); //stop bit
wuliqunyy 6:019ab407ac3c 15 wait_us(100);
wuliqunyy 6:019ab407ac3c 16 return (ack == 0) ? 0 : 1;
wuliqunyy 6:019ab407ac3c 17 }
wuliqunyy 0:fe3c7dde9771 18
wuliqunyy 0:fe3c7dde9771 19 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 20 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 21 *
wuliqunyy 0:fe3c7dde9771 22 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 23 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 24 */
wuliqunyy 5:daab0e0e67e2 25 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 26 int ack = 0;
wuliqunyy 14:062850afdf38 27 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 3, false);
wuliqunyy 6:019ab407ac3c 28 return ack;
wuliqunyy 0:fe3c7dde9771 29 }
wuliqunyy 0:fe3c7dde9771 30
wuliqunyy 0:fe3c7dde9771 31
wuliqunyy 5:daab0e0e67e2 32 /** i2c enter key to open I2C window
wuliqunyy 0:fe3c7dde9771 33 */
wuliqunyy 5:daab0e0e67e2 34 int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 14:062850afdf38 35 char i2cMessage[3];
wuliqunyy 14:062850afdf38 36 *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 14:062850afdf38 37 *(i2cMessage+1) = (char)(0xD0)& 0xff;
wuliqunyy 14:062850afdf38 38 *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 14:062850afdf38 39 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 40 }
wuliqunyy 0:fe3c7dde9771 41
wuliqunyy 5:daab0e0e67e2 42 /** i2c enter key to Start the motor
wuliqunyy 0:fe3c7dde9771 43 */
wuliqunyy 5:daab0e0e67e2 44 int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 14:062850afdf38 45 char i2cMessage[3];
wuliqunyy 14:062850afdf38 46 *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 14:062850afdf38 47 *(i2cMessage+1) = (char)(0xCA)& 0xff;
wuliqunyy 14:062850afdf38 48 *(i2cMessage+2) = (char)(0xFE)& 0xff;
wuliqunyy 14:062850afdf38 49 return i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 50 }
wuliqunyy 12:9f8c7f4da5f6 51
wuliqunyy 12:9f8c7f4da5f6 52 /** i2c to set the 50k PWM
wuliqunyy 12:9f8c7f4da5f6 53 */
wuliqunyy 12:9f8c7f4da5f6 54 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
wuliqunyy 12:9f8c7f4da5f6 55 nv_gen_ctrl_val &= ~NV_PWM_36K_MASK;
wuliqunyy 12:9f8c7f4da5f6 56 nv_gen_ctrl_val |= pwm50k << NV_PWM_36K_OFFSET;
wuliqunyy 14:062850afdf38 57 char i2cMessage[3];
wuliqunyy 14:062850afdf38 58 *(i2cMessage+0) = (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 59 *(i2cMessage+1) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 60 *(i2cMessage+2) = (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 61 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 62 }
wuliqunyy 6:019ab407ac3c 63
wuliqunyy 12:9f8c7f4da5f6 64
wuliqunyy 12:9f8c7f4da5f6 65
wuliqunyy 6:019ab407ac3c 66 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 67 */
wuliqunyy 6:019ab407ac3c 68 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 69 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 70 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 14:062850afdf38 71 char i2cMessage[3];
wuliqunyy 14:062850afdf38 72 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 73 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 74 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 75 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 76 }
wuliqunyy 6:019ab407ac3c 77
wuliqunyy 6:019ab407ac3c 78 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 79 */
wuliqunyy 6:019ab407ac3c 80 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 81 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 82 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 83 char i2cMessage[3];
wuliqunyy 14:062850afdf38 84 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 85 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 86 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 87 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 88 }
wuliqunyy 6:019ab407ac3c 89
wuliqunyy 6:019ab407ac3c 90 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 91 */
wuliqunyy 6:019ab407ac3c 92 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 93 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 94 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 14:062850afdf38 95 char i2cMessage[3];
wuliqunyy 14:062850afdf38 96 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 97 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 98 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 99 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 100 }
wuliqunyy 6:019ab407ac3c 101
wuliqunyy 6:019ab407ac3c 102 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 103 */
wuliqunyy 6:019ab407ac3c 104 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 105 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 106 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 14:062850afdf38 107 char i2cMessage[3];
wuliqunyy 14:062850afdf38 108 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 109 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 110 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 111 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 112 }
wuliqunyy 6:019ab407ac3c 113
wuliqunyy 6:019ab407ac3c 114
wuliqunyy 6:019ab407ac3c 115 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 116 */
wuliqunyy 6:019ab407ac3c 117 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 118 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 119 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 14:062850afdf38 120 char i2cMessage[3];
wuliqunyy 14:062850afdf38 121 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 122 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 123 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 124 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 125 }
wuliqunyy 6:019ab407ac3c 126
wuliqunyy 6:019ab407ac3c 127 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 128 */
wuliqunyy 6:019ab407ac3c 129 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 130 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 131 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 132 char i2cMessage[3];
wuliqunyy 14:062850afdf38 133 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 134 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 135 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 136 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 137 }
wuliqunyy 6:019ab407ac3c 138
wuliqunyy 6:019ab407ac3c 139 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 140 */
wuliqunyy 6:019ab407ac3c 141 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 142 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 143 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 14:062850afdf38 144 char i2cMessage[3];
wuliqunyy 14:062850afdf38 145 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 146 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 147 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 148 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 149 }
wuliqunyy 6:019ab407ac3c 150
wuliqunyy 6:019ab407ac3c 151 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 152 */
wuliqunyy 6:019ab407ac3c 153 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 154 int ack = 0;
wuliqunyy 6:019ab407ac3c 155 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 156 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 157 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 158 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 159 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 160 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 161 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 162 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 14:062850afdf38 163 char i2cMessage[3];
wuliqunyy 14:062850afdf38 164 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 165 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 166 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 167 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 168 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 169 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 170 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 171 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 172 *(i2cMessage+0) = (char)(I2C_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 14:062850afdf38 173 *(i2cMessage+1) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 174 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 175 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 176
wuliqunyy 6:019ab407ac3c 177 return ack;
wuliqunyy 6:019ab407ac3c 178 }
wuliqunyy 6:019ab407ac3c 179
wuliqunyy 6:019ab407ac3c 180 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 181 */
wuliqunyy 6:019ab407ac3c 182 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 183 int ack = 0;
wuliqunyy 6:019ab407ac3c 184 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 185 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 186 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 187 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 188 char i2cMessage[3];
wuliqunyy 14:062850afdf38 189 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 190 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 191 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 192 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 193 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 194 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 195 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 196 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 197
wuliqunyy 6:019ab407ac3c 198 return ack;
wuliqunyy 6:019ab407ac3c 199 }
wuliqunyy 6:019ab407ac3c 200
wuliqunyy 6:019ab407ac3c 201 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 202 */
wuliqunyy 6:019ab407ac3c 203 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 204 int ack = 0;
wuliqunyy 6:019ab407ac3c 205 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 206 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 207 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 208 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 209 char i2cMessage[3];
wuliqunyy 14:062850afdf38 210 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 211 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 212 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 213 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 214 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 215 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 216 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 217 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 218
wuliqunyy 6:019ab407ac3c 219 return ack;
wuliqunyy 9:76a0b9f29a2d 220 }
wuliqunyy 9:76a0b9f29a2d 221
wuliqunyy 14:062850afdf38 222 /** i2c to set the rough regulation gain
wuliqunyy 12:9f8c7f4da5f6 223 */
wuliqunyy 12:9f8c7f4da5f6 224 int i2c_mbed_fpga::i2c_set_rough_gain(unsigned int rough_gain){
wuliqunyy 12:9f8c7f4da5f6 225 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 226 nv_gen_ctrl_val &= ~NV_ROUGH_GAIN_MASK;
wuliqunyy 12:9f8c7f4da5f6 227 nv_gen_ctrl_val |= rough_gain << NV_ROUGH_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 228 char i2cMessage[3];
wuliqunyy 14:062850afdf38 229 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 230 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 231 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 232 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 233
wuliqunyy 12:9f8c7f4da5f6 234 return ack;
wuliqunyy 12:9f8c7f4da5f6 235 }
wuliqunyy 12:9f8c7f4da5f6 236
wuliqunyy 14:062850afdf38 237 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 238 */
wuliqunyy 14:062850afdf38 239 int i2c_mbed_fpga::i2c_set_ehp_reg_gain(unsigned int ehp_gain){
wuliqunyy 14:062850afdf38 240 int ack = 0;
wuliqunyy 14:062850afdf38 241 nv_gen_ctrl_val &= ~NV_EHP_REG_GAIN_MASK;
wuliqunyy 14:062850afdf38 242 nv_gen_ctrl_val |= ehp_gain << NV_EHP_REG_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 243 char i2cMessage[3];
wuliqunyy 14:062850afdf38 244 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 245 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 246 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 247 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 248
wuliqunyy 14:062850afdf38 249 return ack;
wuliqunyy 14:062850afdf38 250 }
wuliqunyy 14:062850afdf38 251
wuliqunyy 14:062850afdf38 252 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 253 */
wuliqunyy 14:062850afdf38 254 int i2c_mbed_fpga::i2c_set_fall_time_blank(unsigned int blank_time){
wuliqunyy 14:062850afdf38 255 int ack = 0;
wuliqunyy 14:062850afdf38 256 nv_gen_ctrl_val &= ~NV_FLAT_BANK_MASK;
wuliqunyy 14:062850afdf38 257 nv_gen_ctrl_val |= blank_time << NV_FLAT_BANK_OFFSET;
wuliqunyy 14:062850afdf38 258 char i2cMessage[3];
wuliqunyy 14:062850afdf38 259 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 260 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 261 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 262 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 263
wuliqunyy 14:062850afdf38 264 return ack;
wuliqunyy 14:062850afdf38 265 }
wuliqunyy 12:9f8c7f4da5f6 266
wuliqunyy 12:9f8c7f4da5f6 267
wuliqunyy 12:9f8c7f4da5f6 268 /** i2c to set the current threshold for I_didt
wuliqunyy 12:9f8c7f4da5f6 269 */
wuliqunyy 12:9f8c7f4da5f6 270 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
wuliqunyy 12:9f8c7f4da5f6 271 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 272 nv_comm_ctrl_val &= ~NV_I_ZC_TH_LOW_MASK;
wuliqunyy 12:9f8c7f4da5f6 273 nv_comm_ctrl_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 274 nv_comm_ctrl_val &= ~NV_I_ZC_TH_HIGH_MASK;
wuliqunyy 12:9f8c7f4da5f6 275 nv_comm_ctrl_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
wuliqunyy 14:062850afdf38 276 char i2cMessage[3];
wuliqunyy 14:062850afdf38 277 *(i2cMessage+0) = (char)(I2C_COMM >> 0)& 0xff;
wuliqunyy 14:062850afdf38 278 *(i2cMessage+1) = (char)(nv_comm_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 279 *(i2cMessage+2) = (char)(nv_comm_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 280 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 281
wuliqunyy 12:9f8c7f4da5f6 282 return ack;
wuliqunyy 12:9f8c7f4da5f6 283 }
wuliqunyy 12:9f8c7f4da5f6 284
wuliqunyy 12:9f8c7f4da5f6 285 /** i2c to set the di current threshold for didt
wuliqunyy 12:9f8c7f4da5f6 286 */
wuliqunyy 12:9f8c7f4da5f6 287 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
wuliqunyy 12:9f8c7f4da5f6 288 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 289 nv_comm_ctrl_val &= ~NV_DI_TH_1ST_MASK;
wuliqunyy 12:9f8c7f4da5f6 290 nv_comm_ctrl_val |= di_1st << NV_DI_TH_1ST_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 291 nv_comm_ctrl_val &= ~NV_DI_TH_2ND_MASK;
wuliqunyy 12:9f8c7f4da5f6 292 nv_comm_ctrl_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
wuliqunyy 14:062850afdf38 293 char i2cMessage[3];
wuliqunyy 14:062850afdf38 294 *(i2cMessage+0) = (char)(I2C_COMM >> 0)& 0xff;
wuliqunyy 14:062850afdf38 295 *(i2cMessage+1) = (char)(nv_comm_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 296 *(i2cMessage+2) = (char)(nv_comm_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 297 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 298
wuliqunyy 12:9f8c7f4da5f6 299 return ack;
wuliqunyy 12:9f8c7f4da5f6 300 }
wuliqunyy 12:9f8c7f4da5f6 301
wuliqunyy 12:9f8c7f4da5f6 302
wuliqunyy 12:9f8c7f4da5f6 303
wuliqunyy 12:9f8c7f4da5f6 304
wuliqunyy 11:b86aea372744 305 /** i2c to clean the I2C controller settins
wuliqunyy 11:b86aea372744 306 */
wuliqunyy 11:b86aea372744 307 int i2c_mbed_fpga::i2c_clear_spd_ctrl(){
wuliqunyy 11:b86aea372744 308 int ack = 0;
wuliqunyy 11:b86aea372744 309 nv_spd_control_1_val = 0;
wuliqunyy 11:b86aea372744 310 nv_spd_control_2_val = 0;
wuliqunyy 14:062850afdf38 311 char i2cMessage[3];
wuliqunyy 14:062850afdf38 312 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 313 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 314 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 315 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 316 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 317 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 318 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 319 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 320
wuliqunyy 11:b86aea372744 321 return ack;
wuliqunyy 11:b86aea372744 322 }
wuliqunyy 11:b86aea372744 323
wuliqunyy 14:062850afdf38 324 /** i2c to set the I2C speed input mode
wuliqunyy 14:062850afdf38 325 */
wuliqunyy 14:062850afdf38 326 int i2c_mbed_fpga::i2c_set_input_mode(unsigned int mode){
wuliqunyy 14:062850afdf38 327 int ack = 0;
wuliqunyy 14:062850afdf38 328 nv_application_cfg_val &= ~NV_INPUT_MODE_CFG_MASK;
wuliqunyy 14:062850afdf38 329 nv_application_cfg_val |= mode << NV_INPUT_MODE_CFG_OFFSET;
wuliqunyy 14:062850afdf38 330 char i2cMessage[3];
wuliqunyy 14:062850afdf38 331 *(i2cMessage+0) = (char)(I2C_APPLICATION_CFG >> 0)& 0xff;
wuliqunyy 14:062850afdf38 332 *(i2cMessage+1) = (char)(nv_application_cfg_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 333 *(i2cMessage+2) = (char)(nv_application_cfg_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 334 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 335 return ack;
wuliqunyy 14:062850afdf38 336 }
wuliqunyy 14:062850afdf38 337
wuliqunyy 14:062850afdf38 338
wuliqunyy 11:b86aea372744 339
wuliqunyy 9:76a0b9f29a2d 340 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 341 */
wuliqunyy 9:76a0b9f29a2d 342 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 343 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 344 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 345 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 14:062850afdf38 346 char i2cMessage[3];
wuliqunyy 14:062850afdf38 347 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 348 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 349 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 350 ack += i2c_word_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 351
wuliqunyy 9:76a0b9f29a2d 352 return ack;
wuliqunyy 9:76a0b9f29a2d 353 }
wuliqunyy 9:76a0b9f29a2d 354
wuliqunyy 12:9f8c7f4da5f6 355 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 12:9f8c7f4da5f6 356 */
wuliqunyy 12:9f8c7f4da5f6 357 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 12:9f8c7f4da5f6 358 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 359 ram_open_duty_val = duty;
wuliqunyy 14:062850afdf38 360 char i2cMessage[3];
wuliqunyy 14:062850afdf38 361 *(i2cMessage+0) = (char)(I2C_SPEED_DUTY)& 0xff;
wuliqunyy 14:062850afdf38 362 *(i2cMessage+1) = (char)(ram_open_duty_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 363 *(i2cMessage+2) = (char)(ram_open_duty_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 364 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 365
wuliqunyy 12:9f8c7f4da5f6 366 return ack;
wuliqunyy 12:9f8c7f4da5f6 367 }
wuliqunyy 12:9f8c7f4da5f6 368
wuliqunyy 11:b86aea372744 369 /** i2c to set the speed curve type
wuliqunyy 11:b86aea372744 370 */
wuliqunyy 11:b86aea372744 371 int i2c_mbed_fpga::i2c_set_curve_type(unsigned int curvetype){
wuliqunyy 11:b86aea372744 372 int ack = 0;
wuliqunyy 11:b86aea372744 373 nv_spd_control_1_val &= ~NV_CURVE_MODE_MASK;
wuliqunyy 11:b86aea372744 374 nv_spd_control_1_val |= curvetype << NV_CURVE_MODE_OFFSET;
wuliqunyy 14:062850afdf38 375 char i2cMessage[3];
wuliqunyy 14:062850afdf38 376 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 377 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 378 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 379 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 380
wuliqunyy 11:b86aea372744 381 return ack;
wuliqunyy 11:b86aea372744 382 }
wuliqunyy 11:b86aea372744 383
wuliqunyy 11:b86aea372744 384 /** i2c to set the open dc ini
wuliqunyy 11:b86aea372744 385 */
wuliqunyy 11:b86aea372744 386 int i2c_mbed_fpga::i2c_set_dc_ini(unsigned int ini){
wuliqunyy 11:b86aea372744 387 int ack = 0;
wuliqunyy 11:b86aea372744 388 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_INI_MASK;
wuliqunyy 11:b86aea372744 389 nv_spd_control_2_val |= ini << NV_DC_OPENLOOP_INI_OFFSET;
wuliqunyy 14:062850afdf38 390 char i2cMessage[3];
wuliqunyy 14:062850afdf38 391 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 392 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 393 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 394 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 395
wuliqunyy 11:b86aea372744 396 return ack;
wuliqunyy 11:b86aea372744 397 }
wuliqunyy 11:b86aea372744 398
wuliqunyy 11:b86aea372744 399 /** i2c to set the open dc slew rate
wuliqunyy 11:b86aea372744 400 */
wuliqunyy 11:b86aea372744 401 int i2c_mbed_fpga::i2c_set_dc_sr(unsigned int sr){
wuliqunyy 11:b86aea372744 402 int ack = 0;
wuliqunyy 11:b86aea372744 403 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_SR_MASK;
wuliqunyy 11:b86aea372744 404 nv_spd_control_2_val |= sr << NV_DC_OPENLOOP_SR_OFFSET;
wuliqunyy 14:062850afdf38 405 char i2cMessage[3];
wuliqunyy 14:062850afdf38 406 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 407 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 408 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 409 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 410
wuliqunyy 11:b86aea372744 411 return ack;
wuliqunyy 11:b86aea372744 412 }
wuliqunyy 11:b86aea372744 413
wuliqunyy 12:9f8c7f4da5f6 414