Ben Willems / Mbed 2 deprecated MLX90418_I2C_master_bwi

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependencies:   mbed

i2c_mbed_fpga.cpp@12:9f8c7f4da5f6, 2021-03-24 (annotated)

Committer:
wuliqunyy
Date:
Wed Mar 24 14:17:25 2021 +0000
Revision:
12:9f8c7f4da5f6
Parent:
11:b86aea372744
Child:
14:062850afdf38
doe2 version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 6:019ab407ac3c 3 DigitalOut led3(LED3);
wuliqunyy 0:fe3c7dde9771 4
wuliqunyy 6:019ab407ac3c 5 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 6 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 7 *
wuliqunyy 6:019ab407ac3c 8 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 9 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 10 */
wuliqunyy 6:019ab407ac3c 11 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 6:019ab407ac3c 12 int ack = 0;
wuliqunyy 6:019ab407ac3c 13 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 2, true); //restart
wuliqunyy 6:019ab407ac3c 14 ack += i2c_master.read(I2C_SLAVE_ADDR, word+2, 2, false); //stop bit
wuliqunyy 6:019ab407ac3c 15 wait_us(100);
wuliqunyy 6:019ab407ac3c 16 return (ack == 0) ? 0 : 1;
wuliqunyy 6:019ab407ac3c 17 }
wuliqunyy 0:fe3c7dde9771 18
wuliqunyy 12:9f8c7f4da5f6 19 //I2C read even NAK happens
wuliqunyy 12:9f8c7f4da5f6 20 int i2c_mbed_fpga::i2c_word_read_by_byte(char *word){
wuliqunyy 12:9f8c7f4da5f6 21 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 22 i2c_master.start();
wuliqunyy 12:9f8c7f4da5f6 23 ack = i2c_master.write(I2C_SLAVE_ADDR);
wuliqunyy 12:9f8c7f4da5f6 24 ack = i2c_master.write(*word);
wuliqunyy 12:9f8c7f4da5f6 25 ack = i2c_master.write(*(word+1));
wuliqunyy 12:9f8c7f4da5f6 26 i2c_master.start();
wuliqunyy 12:9f8c7f4da5f6 27 *(word+2) = i2c_master.read(1);
wuliqunyy 12:9f8c7f4da5f6 28 *(word+3) = i2c_master.read(1);
wuliqunyy 12:9f8c7f4da5f6 29 i2c_master.stop();
wuliqunyy 12:9f8c7f4da5f6 30 return ack;
wuliqunyy 12:9f8c7f4da5f6 31 }
wuliqunyy 12:9f8c7f4da5f6 32
wuliqunyy 12:9f8c7f4da5f6 33
wuliqunyy 0:fe3c7dde9771 34 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 35 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 36 *
wuliqunyy 0:fe3c7dde9771 37 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 38 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 39 */
wuliqunyy 5:daab0e0e67e2 40 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 41 int ack = 0;
wuliqunyy 6:019ab407ac3c 42 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
wuliqunyy 5:daab0e0e67e2 43 return ack;
wuliqunyy 0:fe3c7dde9771 44 }
wuliqunyy 12:9f8c7f4da5f6 45 //I2C write even NAK happens
wuliqunyy 12:9f8c7f4da5f6 46 int i2c_mbed_fpga::i2c_word_write_by_byte(char *word){
wuliqunyy 12:9f8c7f4da5f6 47 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 48 i2c_master.start();
wuliqunyy 12:9f8c7f4da5f6 49 ack = i2c_master.write(I2C_SLAVE_ADDR);
wuliqunyy 12:9f8c7f4da5f6 50 ack = i2c_master.write(*word);
wuliqunyy 12:9f8c7f4da5f6 51 ack = i2c_master.write(*(word+1));
wuliqunyy 12:9f8c7f4da5f6 52 ack = i2c_master.write(*(word+2));
wuliqunyy 12:9f8c7f4da5f6 53 ack = i2c_master.write(*(word+3));
wuliqunyy 12:9f8c7f4da5f6 54 i2c_master.stop();
wuliqunyy 12:9f8c7f4da5f6 55 return ack;
wuliqunyy 12:9f8c7f4da5f6 56 }
wuliqunyy 0:fe3c7dde9771 57
wuliqunyy 0:fe3c7dde9771 58
wuliqunyy 6:019ab407ac3c 59 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 60 * ==> Safe write with 3 times read back check
wuliqunyy 0:fe3c7dde9771 61 *
wuliqunyy 0:fe3c7dde9771 62 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 63 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 64 */
wuliqunyy 6:019ab407ac3c 65 int i2c_mbed_fpga::i2c_word_safe_write(char *word){
wuliqunyy 6:019ab407ac3c 66 int ack = 0;
wuliqunyy 6:019ab407ac3c 67 char readBuff[4];
wuliqunyy 6:019ab407ac3c 68 std::copy(word, word+4, readBuff);
wuliqunyy 6:019ab407ac3c 69 int i = 0;
wuliqunyy 6:019ab407ac3c 70 do{
wuliqunyy 6:019ab407ac3c 71 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 4, false);
wuliqunyy 6:019ab407ac3c 72 wait_us(100);
wuliqunyy 6:019ab407ac3c 73 ack +=i2c_word_read(readBuff);
wuliqunyy 6:019ab407ac3c 74 wait_us(100);
wuliqunyy 6:019ab407ac3c 75 if( *(readBuff+2) == *(word+2) && *(readBuff+3) == *(word+3) ){
wuliqunyy 6:019ab407ac3c 76 ack++;
wuliqunyy 6:019ab407ac3c 77 }
wuliqunyy 6:019ab407ac3c 78 i++;
wuliqunyy 6:019ab407ac3c 79 }while ( ack!=0 && i<3 );
wuliqunyy 6:019ab407ac3c 80 return ack;
wuliqunyy 0:fe3c7dde9771 81 }
wuliqunyy 0:fe3c7dde9771 82
wuliqunyy 0:fe3c7dde9771 83
wuliqunyy 5:daab0e0e67e2 84 /** i2c enter key to open I2C window
wuliqunyy 0:fe3c7dde9771 85 */
wuliqunyy 5:daab0e0e67e2 86 int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 10:a8390614edcc 87 char i2cMessage[4];
wuliqunyy 12:9f8c7f4da5f6 88 *(i2cMessage+0) = (char)(NVADDR_CUST_ID3 >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 89 *(i2cMessage+1) = (char)(NVADDR_CUST_ID3 >> 0)& 0xff;
wuliqunyy 10:a8390614edcc 90 *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 10:a8390614edcc 91 *(i2cMessage+3) = (char)(0xD0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 92 return i2c_word_write_by_byte(i2cMessage);
wuliqunyy 0:fe3c7dde9771 93 }
wuliqunyy 0:fe3c7dde9771 94
wuliqunyy 5:daab0e0e67e2 95 /** i2c enter key to Start the motor
wuliqunyy 0:fe3c7dde9771 96 */
wuliqunyy 5:daab0e0e67e2 97 int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 10:a8390614edcc 98 char i2cMessage[4];
wuliqunyy 12:9f8c7f4da5f6 99 *(i2cMessage+0) = (char)(NVADDR_CUST_ID3 >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 100 *(i2cMessage+1) = (char)(NVADDR_CUST_ID3 >> 0)& 0xff;
wuliqunyy 10:a8390614edcc 101 *(i2cMessage+2) = (char)(0xCA)& 0xff;
wuliqunyy 10:a8390614edcc 102 *(i2cMessage+3) = (char)(0xFE)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 103 return i2c_word_write_by_byte(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 104 }
wuliqunyy 12:9f8c7f4da5f6 105
wuliqunyy 12:9f8c7f4da5f6 106 /** i2c to set the 50k PWM
wuliqunyy 12:9f8c7f4da5f6 107 */
wuliqunyy 12:9f8c7f4da5f6 108 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
wuliqunyy 12:9f8c7f4da5f6 109 nv_gen_ctrl_val &= ~NV_PWM_36K_MASK;
wuliqunyy 12:9f8c7f4da5f6 110 nv_gen_ctrl_val |= pwm50k << NV_PWM_36K_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 111 char i2cMessage[4];
wuliqunyy 12:9f8c7f4da5f6 112 *(i2cMessage+0) = (char)(NVADDR_NV_GEN_CTRL >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 113 *(i2cMessage+1) = (char)(NVADDR_NV_GEN_CTRL >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 114 *(i2cMessage+2) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 115 *(i2cMessage+3) = (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 10:a8390614edcc 116 return i2c_word_safe_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 117 }
wuliqunyy 6:019ab407ac3c 118
wuliqunyy 12:9f8c7f4da5f6 119
wuliqunyy 12:9f8c7f4da5f6 120
wuliqunyy 6:019ab407ac3c 121 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 122 */
wuliqunyy 6:019ab407ac3c 123 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 124 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 125 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 126 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 127 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 128 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 129 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 130 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 131 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 132 }
wuliqunyy 6:019ab407ac3c 133
wuliqunyy 6:019ab407ac3c 134 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 135 */
wuliqunyy 6:019ab407ac3c 136 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 137 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 138 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 6:019ab407ac3c 139 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 140 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 141 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 142 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 143 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 144 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 145 }
wuliqunyy 6:019ab407ac3c 146
wuliqunyy 6:019ab407ac3c 147 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 148 */
wuliqunyy 6:019ab407ac3c 149 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 150 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 151 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 6:019ab407ac3c 152 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 153 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 154 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 155 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 156 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 157 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 158 }
wuliqunyy 6:019ab407ac3c 159
wuliqunyy 6:019ab407ac3c 160 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 161 */
wuliqunyy 6:019ab407ac3c 162 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 163 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 164 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 6:019ab407ac3c 165 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 166 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 167 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 168 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 169 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 170 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 171 }
wuliqunyy 6:019ab407ac3c 172
wuliqunyy 6:019ab407ac3c 173
wuliqunyy 6:019ab407ac3c 174 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 175 */
wuliqunyy 6:019ab407ac3c 176 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 177 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 178 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 179 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 180 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 181 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 182 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 183 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 184 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 185 }
wuliqunyy 6:019ab407ac3c 186
wuliqunyy 6:019ab407ac3c 187 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 188 */
wuliqunyy 6:019ab407ac3c 189 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 190 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 191 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 6:019ab407ac3c 192 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 193 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 194 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 195 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 196 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 197 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 198 }
wuliqunyy 6:019ab407ac3c 199
wuliqunyy 6:019ab407ac3c 200 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 201 */
wuliqunyy 6:019ab407ac3c 202 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 203 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 204 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 6:019ab407ac3c 205 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 206 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 207 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 208 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 209 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 210 return i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 211 }
wuliqunyy 6:019ab407ac3c 212
wuliqunyy 6:019ab407ac3c 213 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 214 */
wuliqunyy 6:019ab407ac3c 215 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 216 int ack = 0;
wuliqunyy 6:019ab407ac3c 217 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 218 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 219 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 220 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 221 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 222 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 223 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 224 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 6:019ab407ac3c 225 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 226 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 227 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 228 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 229 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 230 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 231
wuliqunyy 9:76a0b9f29a2d 232 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 233 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 234 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 235 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 236 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 237
wuliqunyy 9:76a0b9f29a2d 238 *(i2cMessage+0) = (char)(NVADDR_NV_WIND_BRAKE >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 239 *(i2cMessage+1) = (char)(NVADDR_NV_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 240 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 241 *(i2cMessage+3) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 242 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 243
wuliqunyy 6:019ab407ac3c 244 return ack;
wuliqunyy 6:019ab407ac3c 245 }
wuliqunyy 6:019ab407ac3c 246
wuliqunyy 6:019ab407ac3c 247 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 248 */
wuliqunyy 6:019ab407ac3c 249 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 250 int ack = 0;
wuliqunyy 6:019ab407ac3c 251 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 252 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 253 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 254 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 255 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 256 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 257 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 258 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 259 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 260 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 261
wuliqunyy 9:76a0b9f29a2d 262 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 263 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 264 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 265 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 266 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 267
wuliqunyy 6:019ab407ac3c 268 return ack;
wuliqunyy 6:019ab407ac3c 269 }
wuliqunyy 6:019ab407ac3c 270
wuliqunyy 6:019ab407ac3c 271 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 272 */
wuliqunyy 6:019ab407ac3c 273 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 274 int ack = 0;
wuliqunyy 6:019ab407ac3c 275 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 276 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 277 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 278 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 279 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 280 *(i2cMessage+0) = (char)(NVADDR_NV_POSITION >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 281 *(i2cMessage+1) = (char)(NVADDR_NV_POSITION >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 282 *(i2cMessage+2) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 283 *(i2cMessage+3) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 284 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 285
wuliqunyy 9:76a0b9f29a2d 286 *(i2cMessage+0) = (char)(NVADDR_NV_START_UP >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 287 *(i2cMessage+1) = (char)(NVADDR_NV_START_UP >> 0)& 0xff;
wuliqunyy 7:5fb0ad55b339 288 *(i2cMessage+2) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 7:5fb0ad55b339 289 *(i2cMessage+3) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 6:019ab407ac3c 290 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 291
wuliqunyy 6:019ab407ac3c 292 return ack;
wuliqunyy 9:76a0b9f29a2d 293 }
wuliqunyy 9:76a0b9f29a2d 294
wuliqunyy 12:9f8c7f4da5f6 295 /** i2c to set the open loop mode
wuliqunyy 12:9f8c7f4da5f6 296 */
wuliqunyy 12:9f8c7f4da5f6 297 int i2c_mbed_fpga::i2c_set_rough_gain(unsigned int rough_gain){
wuliqunyy 12:9f8c7f4da5f6 298 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 299 nv_gen_ctrl_val &= ~NV_ROUGH_GAIN_MASK;
wuliqunyy 12:9f8c7f4da5f6 300 nv_gen_ctrl_val |= rough_gain << NV_ROUGH_GAIN_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 301 char i2cMessage[4];
wuliqunyy 12:9f8c7f4da5f6 302 *(i2cMessage+0) = (char)(NVADDR_NV_GEN_CTRL >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 303 *(i2cMessage+1) = (char)(NVADDR_NV_GEN_CTRL >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 304 *(i2cMessage+2) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 305 *(i2cMessage+3) = (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 306 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 307
wuliqunyy 12:9f8c7f4da5f6 308 return ack;
wuliqunyy 12:9f8c7f4da5f6 309 }
wuliqunyy 12:9f8c7f4da5f6 310
wuliqunyy 12:9f8c7f4da5f6 311
wuliqunyy 12:9f8c7f4da5f6 312
wuliqunyy 12:9f8c7f4da5f6 313 /** i2c to set the current threshold for I_didt
wuliqunyy 12:9f8c7f4da5f6 314 */
wuliqunyy 12:9f8c7f4da5f6 315 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
wuliqunyy 12:9f8c7f4da5f6 316 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 317 nv_comm_ctrl_val &= ~NV_I_ZC_TH_LOW_MASK;
wuliqunyy 12:9f8c7f4da5f6 318 nv_comm_ctrl_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 319 nv_comm_ctrl_val &= ~NV_I_ZC_TH_HIGH_MASK;
wuliqunyy 12:9f8c7f4da5f6 320 nv_comm_ctrl_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 321 char i2cMessage[4];
wuliqunyy 12:9f8c7f4da5f6 322 *(i2cMessage+0) = (char)(NVADDR_NV_COMM >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 323 *(i2cMessage+1) = (char)(NVADDR_NV_COMM >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 324 *(i2cMessage+2) = (char)(nv_comm_ctrl_val >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 325 *(i2cMessage+3) = (char)(nv_comm_ctrl_val >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 326 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 327
wuliqunyy 12:9f8c7f4da5f6 328 return ack;
wuliqunyy 12:9f8c7f4da5f6 329 }
wuliqunyy 12:9f8c7f4da5f6 330
wuliqunyy 12:9f8c7f4da5f6 331 /** i2c to set the di current threshold for didt
wuliqunyy 12:9f8c7f4da5f6 332 */
wuliqunyy 12:9f8c7f4da5f6 333 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
wuliqunyy 12:9f8c7f4da5f6 334 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 335 nv_comm_ctrl_val &= ~NV_DI_TH_1ST_MASK;
wuliqunyy 12:9f8c7f4da5f6 336 nv_comm_ctrl_val |= di_1st << NV_DI_TH_1ST_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 337 nv_comm_ctrl_val &= ~NV_DI_TH_2ND_MASK;
wuliqunyy 12:9f8c7f4da5f6 338 nv_comm_ctrl_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
wuliqunyy 12:9f8c7f4da5f6 339 char i2cMessage[4];
wuliqunyy 12:9f8c7f4da5f6 340 *(i2cMessage+0) = (char)(NVADDR_NV_COMM >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 341 *(i2cMessage+1) = (char)(NVADDR_NV_COMM >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 342 *(i2cMessage+2) = (char)(nv_comm_ctrl_val >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 343 *(i2cMessage+3) = (char)(nv_comm_ctrl_val >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 344 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 345
wuliqunyy 12:9f8c7f4da5f6 346 return ack;
wuliqunyy 12:9f8c7f4da5f6 347 }
wuliqunyy 12:9f8c7f4da5f6 348
wuliqunyy 12:9f8c7f4da5f6 349
wuliqunyy 12:9f8c7f4da5f6 350
wuliqunyy 12:9f8c7f4da5f6 351
wuliqunyy 11:b86aea372744 352 /** i2c to clean the I2C controller settins
wuliqunyy 11:b86aea372744 353 */
wuliqunyy 11:b86aea372744 354 int i2c_mbed_fpga::i2c_clear_spd_ctrl(){
wuliqunyy 11:b86aea372744 355 int ack = 0;
wuliqunyy 11:b86aea372744 356 nv_spd_control_1_val = 0;
wuliqunyy 11:b86aea372744 357 nv_spd_control_2_val = 0;
wuliqunyy 11:b86aea372744 358 char i2cMessage[4];
wuliqunyy 11:b86aea372744 359 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_1 >> 8)& 0xff;
wuliqunyy 11:b86aea372744 360 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 11:b86aea372744 361 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 11:b86aea372744 362 *(i2cMessage+3) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 11:b86aea372744 363 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 11:b86aea372744 364
wuliqunyy 11:b86aea372744 365 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_2 >> 8)& 0xff;
wuliqunyy 11:b86aea372744 366 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 11:b86aea372744 367 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 11:b86aea372744 368 *(i2cMessage+3) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 11:b86aea372744 369 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 11:b86aea372744 370
wuliqunyy 11:b86aea372744 371 return ack;
wuliqunyy 11:b86aea372744 372 }
wuliqunyy 11:b86aea372744 373
wuliqunyy 11:b86aea372744 374
wuliqunyy 9:76a0b9f29a2d 375 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 376 */
wuliqunyy 9:76a0b9f29a2d 377 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 378 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 379 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 380 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 9:76a0b9f29a2d 381 char i2cMessage[4];
wuliqunyy 9:76a0b9f29a2d 382 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_1 >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 383 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 384 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 9:76a0b9f29a2d 385 *(i2cMessage+3) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 9:76a0b9f29a2d 386 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 387
wuliqunyy 9:76a0b9f29a2d 388 return ack;
wuliqunyy 9:76a0b9f29a2d 389 }
wuliqunyy 9:76a0b9f29a2d 390
wuliqunyy 12:9f8c7f4da5f6 391 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 12:9f8c7f4da5f6 392 */
wuliqunyy 12:9f8c7f4da5f6 393 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 12:9f8c7f4da5f6 394 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 395 ram_open_duty_val = duty;
wuliqunyy 12:9f8c7f4da5f6 396 char i2cMessage[4];
wuliqunyy 12:9f8c7f4da5f6 397 *(i2cMessage+0) = (char)(0x10)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 398 *(i2cMessage+1) = (char)(0x00)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 399 *(i2cMessage+2) = (char)(ram_open_duty_val >> 8)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 400 *(i2cMessage+3) = (char)(ram_open_duty_val >> 0)& 0xff;
wuliqunyy 12:9f8c7f4da5f6 401 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 402
wuliqunyy 12:9f8c7f4da5f6 403 return ack;
wuliqunyy 12:9f8c7f4da5f6 404 }
wuliqunyy 12:9f8c7f4da5f6 405
wuliqunyy 11:b86aea372744 406 /** i2c to set the speed curve type
wuliqunyy 11:b86aea372744 407 */
wuliqunyy 11:b86aea372744 408 int i2c_mbed_fpga::i2c_set_curve_type(unsigned int curvetype){
wuliqunyy 11:b86aea372744 409 int ack = 0;
wuliqunyy 11:b86aea372744 410 nv_spd_control_1_val &= ~NV_CURVE_MODE_MASK;
wuliqunyy 11:b86aea372744 411 nv_spd_control_1_val |= curvetype << NV_CURVE_MODE_OFFSET;
wuliqunyy 11:b86aea372744 412 char i2cMessage[4];
wuliqunyy 11:b86aea372744 413 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_1 >> 8)& 0xff;
wuliqunyy 11:b86aea372744 414 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 11:b86aea372744 415 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 11:b86aea372744 416 *(i2cMessage+3) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 11:b86aea372744 417 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 11:b86aea372744 418
wuliqunyy 11:b86aea372744 419 return ack;
wuliqunyy 11:b86aea372744 420 }
wuliqunyy 11:b86aea372744 421
wuliqunyy 11:b86aea372744 422 /** i2c to set the open dc ini
wuliqunyy 11:b86aea372744 423 */
wuliqunyy 11:b86aea372744 424 int i2c_mbed_fpga::i2c_set_dc_ini(unsigned int ini){
wuliqunyy 11:b86aea372744 425 int ack = 0;
wuliqunyy 11:b86aea372744 426 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_INI_MASK;
wuliqunyy 11:b86aea372744 427 nv_spd_control_2_val |= ini << NV_DC_OPENLOOP_INI_OFFSET;
wuliqunyy 11:b86aea372744 428 char i2cMessage[4];
wuliqunyy 11:b86aea372744 429 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_2 >> 8)& 0xff;
wuliqunyy 11:b86aea372744 430 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 11:b86aea372744 431 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 11:b86aea372744 432 *(i2cMessage+3) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 11:b86aea372744 433 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 11:b86aea372744 434
wuliqunyy 11:b86aea372744 435 return ack;
wuliqunyy 11:b86aea372744 436 }
wuliqunyy 11:b86aea372744 437
wuliqunyy 11:b86aea372744 438 /** i2c to set the open dc slew rate
wuliqunyy 11:b86aea372744 439 */
wuliqunyy 11:b86aea372744 440 int i2c_mbed_fpga::i2c_set_dc_sr(unsigned int sr){
wuliqunyy 11:b86aea372744 441 int ack = 0;
wuliqunyy 11:b86aea372744 442 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_SR_MASK;
wuliqunyy 11:b86aea372744 443 nv_spd_control_2_val |= sr << NV_DC_OPENLOOP_SR_OFFSET;
wuliqunyy 11:b86aea372744 444 char i2cMessage[4];
wuliqunyy 11:b86aea372744 445 *(i2cMessage+0) = (char)(NVADDR_NV_SPD_CTRL_2 >> 8)& 0xff;
wuliqunyy 11:b86aea372744 446 *(i2cMessage+1) = (char)(NVADDR_NV_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 11:b86aea372744 447 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 11:b86aea372744 448 *(i2cMessage+3) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 11:b86aea372744 449 ack += i2c_word_safe_write(i2cMessage);
wuliqunyy 11:b86aea372744 450
wuliqunyy 11:b86aea372744 451 return ack;
wuliqunyy 11:b86aea372744 452 }
wuliqunyy 11:b86aea372744 453
wuliqunyy 12:9f8c7f4da5f6 454