Ben Willems / Mbed 2 deprecated MLX90418_I2C_master_bwi

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Dependencies:   mbed

i2c_mbed_fpga.cpp@17:5b17c9dc85b2, 2021-05-27 (annotated)

Committer:
bwi
Date:
Thu May 27 13:35:24 2021 +0000
Branch:
master-bwi
Revision:
17:5b17c9dc85b2
Parent:
16:a0bfe33f8a4a 
Changed reset pin for the FPGA. Set current limit level to max.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wuliqunyy 0:fe3c7dde9771 1 #include "mbed.h"
wuliqunyy 0:fe3c7dde9771 2 #include "i2c_mbed_fpga.h"
wuliqunyy 16:a0bfe33f8a4a 3
wuliqunyy 0:fe3c7dde9771 4
wuliqunyy 6:019ab407ac3c 5 /** i2c read from slave DUT
wuliqunyy 6:019ab407ac3c 6 * retun 0 on success, otherwise fails
wuliqunyy 6:019ab407ac3c 7 *
wuliqunyy 6:019ab407ac3c 8 * @param i2c_master specifies the i2c interface
wuliqunyy 6:019ab407ac3c 9 * @param word is 4byte, first 2bytes as addr, the rest 2bytes to store data
wuliqunyy 6:019ab407ac3c 10 */
wuliqunyy 6:019ab407ac3c 11 int i2c_mbed_fpga::i2c_word_read(char *word){
wuliqunyy 6:019ab407ac3c 12 int ack = 0;
wuliqunyy 14:062850afdf38 13 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 1, true); //restart
wuliqunyy 14:062850afdf38 14 ack += i2c_master.read(I2C_SLAVE_ADDR, word+1, 2, false); //stop bit
wuliqunyy 6:019ab407ac3c 15 wait_us(100);
wuliqunyy 6:019ab407ac3c 16 return (ack == 0) ? 0 : 1;
wuliqunyy 6:019ab407ac3c 17 }
wuliqunyy 0:fe3c7dde9771 18
wuliqunyy 0:fe3c7dde9771 19 /** i2c write to slave DUT
wuliqunyy 6:019ab407ac3c 20 * ==> one time write, not read back check
wuliqunyy 0:fe3c7dde9771 21 *
wuliqunyy 0:fe3c7dde9771 22 * @param i2c_master specifies the i2c interface
wuliqunyy 0:fe3c7dde9771 23 * @param word is considered as 4byte char data
wuliqunyy 0:fe3c7dde9771 24 */
wuliqunyy 5:daab0e0e67e2 25 int i2c_mbed_fpga::i2c_word_write(char *word){
wuliqunyy 6:019ab407ac3c 26 int ack = 0;
wuliqunyy 14:062850afdf38 27 ack = i2c_master.write(I2C_SLAVE_ADDR, word, 3, false);
wuliqunyy 6:019ab407ac3c 28 return ack;
wuliqunyy 0:fe3c7dde9771 29 }
wuliqunyy 0:fe3c7dde9771 30
wuliqunyy 0:fe3c7dde9771 31
wuliqunyy 16:a0bfe33f8a4a 32 /** i2c enter key to open I2C window (for old releases)
wuliqunyy 0:fe3c7dde9771 33 */
wuliqunyy 15:83bbc18cccbc 34 //int i2c_mbed_fpga::i2c_window_open(){
wuliqunyy 15:83bbc18cccbc 35 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 36 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 37 // *(i2cMessage+1) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 38 // *(i2cMessage+2) = (char)(0xD0)& 0xff;
wuliqunyy 15:83bbc18cccbc 39 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 40 //}
wuliqunyy 15:83bbc18cccbc 41
wuliqunyy 16:a0bfe33f8a4a 42 /** i2c enter key to Start the motor (for old releases)
wuliqunyy 15:83bbc18cccbc 43 */
wuliqunyy 15:83bbc18cccbc 44 //int i2c_mbed_fpga::i2c_motor_start(){
wuliqunyy 15:83bbc18cccbc 45 // char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 46 // *(i2cMessage+0) = (char)(I2C_CUST_ID3)& 0xff;
wuliqunyy 15:83bbc18cccbc 47 // *(i2cMessage+1) = (char)(0xCA)& 0xff;
wuliqunyy 15:83bbc18cccbc 48 // *(i2cMessage+2) = (char)(0xFE)& 0xff;
wuliqunyy 15:83bbc18cccbc 49 // return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 50 //}
wuliqunyy 15:83bbc18cccbc 51
wuliqunyy 15:83bbc18cccbc 52
wuliqunyy 15:83bbc18cccbc 53 /** i2c enter key to open I2C configuration mode entry
wuliqunyy 15:83bbc18cccbc 54 */
wuliqunyy 15:83bbc18cccbc 55 int i2c_mbed_fpga::i2c_config_mode_entry(){
wuliqunyy 14:062850afdf38 56 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 57 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 58 *(i2cMessage+1) = (char)(0x1D)& 0xff;
wuliqunyy 15:83bbc18cccbc 59 *(i2cMessage+2) = (char)(0xEA)& 0xff;
wuliqunyy 14:062850afdf38 60 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 61 }
wuliqunyy 0:fe3c7dde9771 62
wuliqunyy 16:a0bfe33f8a4a 63 /** i2c enter MLX key to open I2C MLX configuration mode entry
wuliqunyy 16:a0bfe33f8a4a 64 */
wuliqunyy 16:a0bfe33f8a4a 65 int i2c_mbed_fpga::i2c_mlx_mode_entry(){
wuliqunyy 16:a0bfe33f8a4a 66 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 67 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 68 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 69 *(i2cMessage+1) = (char)(0x35)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 70 *(i2cMessage+2) = (char)(0x4B)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 71 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 72 *(i2cMessage+0) = (char)(I2C_COMMAND_KEY)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 73 *(i2cMessage+1) = (char)(0x65)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 74 *(i2cMessage+2) = (char)(0xA9)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 75 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 76
wuliqunyy 16:a0bfe33f8a4a 77 return ack;
wuliqunyy 16:a0bfe33f8a4a 78 }
wuliqunyy 16:a0bfe33f8a4a 79
wuliqunyy 16:a0bfe33f8a4a 80
wuliqunyy 15:83bbc18cccbc 81 /** i2c ram start up flag set to skip OTP copy
wuliqunyy 0:fe3c7dde9771 82 */
wuliqunyy 15:83bbc18cccbc 83 int i2c_mbed_fpga::i2c_skip_app_copy(){
wuliqunyy 14:062850afdf38 84 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 85 *(i2cMessage+0) = (char)(I2C_STARTUP_FLAGS_1)& 0xff;
wuliqunyy 15:83bbc18cccbc 86 *(i2cMessage+1) = (char)(0x05)& 0xff;
wuliqunyy 15:83bbc18cccbc 87 *(i2cMessage+2) = (char)(0x00)& 0xff;
wuliqunyy 14:062850afdf38 88 return i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 89 }
wuliqunyy 12:9f8c7f4da5f6 90
wuliqunyy 15:83bbc18cccbc 91 /** i2c soft reset
wuliqunyy 15:83bbc18cccbc 92 */
wuliqunyy 15:83bbc18cccbc 93 int i2c_mbed_fpga::i2c_soft_reset(){
wuliqunyy 15:83bbc18cccbc 94 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 95 *(i2cMessage+0) = (char)(I2C_COMMAND_CONTROL)& 0xff;
wuliqunyy 15:83bbc18cccbc 96 *(i2cMessage+1) = (char)(0xC1)& 0xff;
wuliqunyy 15:83bbc18cccbc 97 *(i2cMessage+2) = (char)(0xA0)& 0xff;
wuliqunyy 15:83bbc18cccbc 98 return i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 99 }
wuliqunyy 15:83bbc18cccbc 100
wuliqunyy 15:83bbc18cccbc 101
wuliqunyy 12:9f8c7f4da5f6 102 /** i2c to set the 50k PWM
wuliqunyy 12:9f8c7f4da5f6 103 */
wuliqunyy 12:9f8c7f4da5f6 104 int i2c_mbed_fpga::i2c_set_50k_pwm(unsigned int pwm50k){
wuliqunyy 15:83bbc18cccbc 105 nv_gen_ctrl_val &= ~NV_PWM_50K_MASK;
wuliqunyy 15:83bbc18cccbc 106 nv_gen_ctrl_val |= pwm50k << NV_PWM_50K_OFFSET;
wuliqunyy 14:062850afdf38 107 char i2cMessage[3];
wuliqunyy 14:062850afdf38 108 *(i2cMessage+0) = (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 109 *(i2cMessage+1) = (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 110 *(i2cMessage+2) = (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 111 return i2c_word_write(i2cMessage);
wuliqunyy 0:fe3c7dde9771 112 }
wuliqunyy 6:019ab407ac3c 113
wuliqunyy 12:9f8c7f4da5f6 114
wuliqunyy 12:9f8c7f4da5f6 115
wuliqunyy 6:019ab407ac3c 116 /** i2c to set the Postion Pulse width
wuliqunyy 6:019ab407ac3c 117 */
wuliqunyy 6:019ab407ac3c 118 int i2c_mbed_fpga::i2c_set_position_pulse_width(unsigned int mantisaa_2b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 119 nv_positin_val &= ~NV_POSITION_PULSE_TIME_MASK;
wuliqunyy 6:019ab407ac3c 120 nv_positin_val |= ((exponent_3b << 2) | mantisaa_2b) << NV_POSITION_PULSE_TIME_OFFSET;
wuliqunyy 14:062850afdf38 121 char i2cMessage[3];
wuliqunyy 14:062850afdf38 122 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 123 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 124 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 125 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 126 }
wuliqunyy 6:019ab407ac3c 127
wuliqunyy 6:019ab407ac3c 128 /** i2c to set the Postion Pulse duty cycle
wuliqunyy 6:019ab407ac3c 129 */
wuliqunyy 6:019ab407ac3c 130 int i2c_mbed_fpga::i2c_set_position_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 131 nv_positin_val &= ~NV_POSITION_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 132 nv_positin_val |= duty_2b << NV_POSITION_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 133 char i2cMessage[3];
wuliqunyy 14:062850afdf38 134 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 135 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 136 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 137 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 138 }
wuliqunyy 6:019ab407ac3c 139
wuliqunyy 6:019ab407ac3c 140 /** i2c to enable the Postion Pulse majority volting
wuliqunyy 6:019ab407ac3c 141 */
wuliqunyy 6:019ab407ac3c 142 int i2c_mbed_fpga::i2c_set_position_maj_vote(unsigned int maj_1b){
wuliqunyy 6:019ab407ac3c 143 nv_positin_val &= ~NV_POSI_MAJO_VOTE_MASK;
wuliqunyy 6:019ab407ac3c 144 nv_positin_val |= maj_1b << NV_POSI_MAJO_VOTE_OFFSET;
wuliqunyy 14:062850afdf38 145 char i2cMessage[3];
wuliqunyy 14:062850afdf38 146 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 147 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 148 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 149 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 150 }
wuliqunyy 6:019ab407ac3c 151
wuliqunyy 6:019ab407ac3c 152 /** i2c to set the anti-cogging rotation direction
wuliqunyy 6:019ab407ac3c 153 */
wuliqunyy 6:019ab407ac3c 154 int i2c_mbed_fpga::i2c_set_position_anti_cog(unsigned int cog_1b){
wuliqunyy 6:019ab407ac3c 155 nv_positin_val &= ~NV_ANTI_COG_MASK;
wuliqunyy 6:019ab407ac3c 156 nv_positin_val |= cog_1b << NV_ANTI_COG_OFFSET;
wuliqunyy 14:062850afdf38 157 char i2cMessage[3];
wuliqunyy 14:062850afdf38 158 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 159 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 160 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 161 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 162 }
wuliqunyy 6:019ab407ac3c 163
wuliqunyy 6:019ab407ac3c 164
wuliqunyy 6:019ab407ac3c 165 /** i2c to set the Start Up Pulse width (pulse train)
wuliqunyy 6:019ab407ac3c 166 */
wuliqunyy 6:019ab407ac3c 167 int i2c_mbed_fpga::i2c_set_start_up_pulse_width(unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 168 nv_start_up_val &= ~NV_START_UP_TIME_MASK;
wuliqunyy 8:2554218db1e6 169 nv_start_up_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_START_UP_TIME_OFFSET;
wuliqunyy 14:062850afdf38 170 char i2cMessage[3];
wuliqunyy 14:062850afdf38 171 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 172 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 173 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 174 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 175 }
wuliqunyy 6:019ab407ac3c 176
wuliqunyy 6:019ab407ac3c 177 /** i2c to set the Start up Pulse duty cycle (pulse train)
wuliqunyy 6:019ab407ac3c 178 */
wuliqunyy 6:019ab407ac3c 179 int i2c_mbed_fpga::i2c_set_start_up_duty(unsigned int duty_2b){
wuliqunyy 6:019ab407ac3c 180 nv_start_up_val &= ~NV_START_DUTY_MASK;
wuliqunyy 6:019ab407ac3c 181 nv_start_up_val |= duty_2b << NV_START_DUTY_OFFSET;
wuliqunyy 14:062850afdf38 182 char i2cMessage[3];
wuliqunyy 14:062850afdf38 183 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 184 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 185 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 186 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 187 }
wuliqunyy 6:019ab407ac3c 188
wuliqunyy 6:019ab407ac3c 189 /** i2c to set the Start up commutation number of EHPs (pulse train)
wuliqunyy 6:019ab407ac3c 190 */
wuliqunyy 6:019ab407ac3c 191 int i2c_mbed_fpga::i2c_set_start_up_num_comm(unsigned int comm){
wuliqunyy 6:019ab407ac3c 192 nv_start_up_val &= ~NV_COMM_START_NUM_MASK;
wuliqunyy 6:019ab407ac3c 193 nv_start_up_val |= comm << NV_COMM_START_NUM_OFFSET;
wuliqunyy 14:062850afdf38 194 char i2cMessage[3];
wuliqunyy 14:062850afdf38 195 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 196 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 197 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 198 return i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 199 }
wuliqunyy 6:019ab407ac3c 200
wuliqunyy 6:019ab407ac3c 201 /** i2c to set the Soft Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 202 */
wuliqunyy 6:019ab407ac3c 203 int i2c_mbed_fpga::i2c_set_soft_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b, unsigned int step_size, unsigned int num_steps){
wuliqunyy 6:019ab407ac3c 204 int ack = 0;
wuliqunyy 6:019ab407ac3c 205 nv_start_up_val &= ~NV_SOFT_START_MASK;
wuliqunyy 6:019ab407ac3c 206 nv_start_up_val |= enbale << NV_SOFT_START_OFFSET;
wuliqunyy 6:019ab407ac3c 207 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 208 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 6:019ab407ac3c 209 nv_start_up_val &= ~NV_SOFT_STEP_SIZE_MASK;
wuliqunyy 6:019ab407ac3c 210 nv_start_up_val |= step_size << NV_SOFT_STEP_SIZE_OFFSET;
wuliqunyy 6:019ab407ac3c 211 nv_wind_brake_val &= ~NV_SOFT_NUM_STEP_MASK;
wuliqunyy 6:019ab407ac3c 212 nv_wind_brake_val |= num_steps << NV_SOFT_NUM_STEP_OFFSET;
wuliqunyy 14:062850afdf38 213 char i2cMessage[3];
wuliqunyy 14:062850afdf38 214 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 215 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 216 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 217 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 218 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 219 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 220 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 221 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 222 *(i2cMessage+0) = (char)(I2C_WIND_BRAKE >> 0)& 0xff;
wuliqunyy 14:062850afdf38 223 *(i2cMessage+1) = (char)(nv_wind_brake_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 224 *(i2cMessage+2) = (char)(nv_wind_brake_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 225 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 226
wuliqunyy 6:019ab407ac3c 227 return ack;
wuliqunyy 6:019ab407ac3c 228 }
wuliqunyy 6:019ab407ac3c 229
wuliqunyy 6:019ab407ac3c 230 /** i2c to set the High Torque Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 231 */
wuliqunyy 6:019ab407ac3c 232 int i2c_mbed_fpga::i2c_set_high_torque_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 233 int ack = 0;
wuliqunyy 6:019ab407ac3c 234 nv_start_up_val &= ~NV_LONG_START_MASK;
wuliqunyy 6:019ab407ac3c 235 nv_start_up_val |= enbale << NV_LONG_START_OFFSET;
wuliqunyy 6:019ab407ac3c 236 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 237 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 238 char i2cMessage[3];
wuliqunyy 14:062850afdf38 239 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 240 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 241 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 242 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 243 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 244 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 245 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 246 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 247
wuliqunyy 6:019ab407ac3c 248 return ack;
wuliqunyy 6:019ab407ac3c 249 }
wuliqunyy 6:019ab407ac3c 250
wuliqunyy 6:019ab407ac3c 251 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 6:019ab407ac3c 252 */
wuliqunyy 6:019ab407ac3c 253 int i2c_mbed_fpga::i2c_set_single_pulse_start_up(unsigned int enbale, unsigned int mantisaa_3b, unsigned int exponent_3b){
wuliqunyy 6:019ab407ac3c 254 int ack = 0;
wuliqunyy 6:019ab407ac3c 255 nv_start_up_val &= ~NV_SINGLE_PULSE_START_MASK;
wuliqunyy 6:019ab407ac3c 256 nv_start_up_val |= enbale << NV_SINGLE_PULSE_START_OFFSET;
wuliqunyy 6:019ab407ac3c 257 nv_positin_val &= ~NV_FIRST_NON_FLAT_TIME_MASK;
wuliqunyy 6:019ab407ac3c 258 nv_positin_val |= ((exponent_3b << 3) | mantisaa_3b) << NV_FIRST_NON_FLAT_TIME_OFFSET;
wuliqunyy 14:062850afdf38 259 char i2cMessage[3];
wuliqunyy 14:062850afdf38 260 *(i2cMessage+0) = (char)(I2C_POSITION >> 0)& 0xff;
wuliqunyy 14:062850afdf38 261 *(i2cMessage+1) = (char)(nv_positin_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 262 *(i2cMessage+2) = (char)(nv_positin_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 263 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 264 *(i2cMessage+0) = (char)(I2C_START_UP >> 0)& 0xff;
wuliqunyy 14:062850afdf38 265 *(i2cMessage+1) = (char)(nv_start_up_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 266 *(i2cMessage+2) = (char)(nv_start_up_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 267 ack += i2c_word_write(i2cMessage);
wuliqunyy 6:019ab407ac3c 268
wuliqunyy 6:019ab407ac3c 269 return ack;
wuliqunyy 9:76a0b9f29a2d 270 }
wuliqunyy 9:76a0b9f29a2d 271
wuliqunyy 14:062850afdf38 272 /** i2c to set the rough regulation gain
wuliqunyy 12:9f8c7f4da5f6 273 */
wuliqunyy 12:9f8c7f4da5f6 274 int i2c_mbed_fpga::i2c_set_rough_gain(unsigned int rough_gain){
wuliqunyy 12:9f8c7f4da5f6 275 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 276 nv_gen_ctrl_val &= ~NV_ROUGH_GAIN_MASK;
wuliqunyy 12:9f8c7f4da5f6 277 nv_gen_ctrl_val |= rough_gain << NV_ROUGH_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 278 char i2cMessage[3];
wuliqunyy 14:062850afdf38 279 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 280 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 281 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 282 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 283
wuliqunyy 12:9f8c7f4da5f6 284 return ack;
wuliqunyy 12:9f8c7f4da5f6 285 }
wuliqunyy 12:9f8c7f4da5f6 286
wuliqunyy 14:062850afdf38 287 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 288 */
wuliqunyy 14:062850afdf38 289 int i2c_mbed_fpga::i2c_set_ehp_reg_gain(unsigned int ehp_gain){
wuliqunyy 14:062850afdf38 290 int ack = 0;
wuliqunyy 14:062850afdf38 291 nv_gen_ctrl_val &= ~NV_EHP_REG_GAIN_MASK;
wuliqunyy 14:062850afdf38 292 nv_gen_ctrl_val |= ehp_gain << NV_EHP_REG_GAIN_OFFSET;
wuliqunyy 14:062850afdf38 293 char i2cMessage[3];
wuliqunyy 14:062850afdf38 294 *(i2cMessage+0)= (char)(I2C_GEN_CTRL >> 0)& 0xff;
wuliqunyy 14:062850afdf38 295 *(i2cMessage+1)= (char)(nv_gen_ctrl_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 296 *(i2cMessage+2)= (char)(nv_gen_ctrl_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 297 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 298
wuliqunyy 14:062850afdf38 299 return ack;
wuliqunyy 14:062850afdf38 300 }
wuliqunyy 14:062850afdf38 301
wuliqunyy 14:062850afdf38 302 /** i2c to set the ehp regulation gain
wuliqunyy 14:062850afdf38 303 */
wuliqunyy 14:062850afdf38 304 int i2c_mbed_fpga::i2c_set_fall_time_blank(unsigned int blank_time){
wuliqunyy 14:062850afdf38 305 int ack = 0;
wuliqunyy 15:83bbc18cccbc 306 nv_dig_config_val &= ~NV_FLAT_BLANK_MASK;
wuliqunyy 15:83bbc18cccbc 307 nv_dig_config_val |= blank_time << NV_FLAT_BLANK_OFFSET;
wuliqunyy 14:062850afdf38 308 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 309 *(i2cMessage+0)= (char)(I2C_DIGITAL_CFG >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 310 *(i2cMessage+1)= (char)(nv_dig_config_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 311 *(i2cMessage+2)= (char)(nv_dig_config_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 312 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 313
wuliqunyy 14:062850afdf38 314 return ack;
wuliqunyy 14:062850afdf38 315 }
wuliqunyy 12:9f8c7f4da5f6 316
wuliqunyy 12:9f8c7f4da5f6 317
wuliqunyy 12:9f8c7f4da5f6 318 /** i2c to set the current threshold for I_didt
wuliqunyy 12:9f8c7f4da5f6 319 */
wuliqunyy 12:9f8c7f4da5f6 320 int i2c_mbed_fpga::i2c_set_comm_i_thres(unsigned int i_thr_low, unsigned int i_thr_high){
wuliqunyy 12:9f8c7f4da5f6 321 int ack = 0;
wuliqunyy 15:83bbc18cccbc 322 nv_i_zc_th_low_val &= ~NV_I_ZC_TH_LOW_MASK;
wuliqunyy 15:83bbc18cccbc 323 nv_i_zc_th_low_val |= i_thr_low << NV_I_ZC_TH_LOW_OFFSET;
wuliqunyy 15:83bbc18cccbc 324 nv_i_zc_th_high_val &= ~NV_I_ZC_TH_HIGH_MASK;
wuliqunyy 15:83bbc18cccbc 325 nv_i_zc_th_high_val |= i_thr_high << NV_I_ZC_TH_HIGH_OFFSET;
wuliqunyy 14:062850afdf38 326 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 327 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_LOW >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 328 *(i2cMessage+1) = (char)(nv_i_zc_th_low_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 329 *(i2cMessage+2) = (char)(nv_i_zc_th_low_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 330 ack += i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 331 *(i2cMessage+0) = (char)(I2C_I_ZC_TH_HIGH >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 332 *(i2cMessage+1) = (char)(nv_i_zc_th_high_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 333 *(i2cMessage+2) = (char)(nv_i_zc_th_high_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 334 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 335 return ack;
wuliqunyy 12:9f8c7f4da5f6 336 }
wuliqunyy 12:9f8c7f4da5f6 337
wuliqunyy 12:9f8c7f4da5f6 338 /** i2c to set the di current threshold for didt
wuliqunyy 12:9f8c7f4da5f6 339 */
wuliqunyy 12:9f8c7f4da5f6 340 int i2c_mbed_fpga::i2c_set_comm_di_thres(unsigned int di_1st, unsigned int di_2nd){
wuliqunyy 12:9f8c7f4da5f6 341 int ack = 0;
wuliqunyy 15:83bbc18cccbc 342 nv_di_th_1st_val &= ~NV_DI_TH_1ST_MASK;
wuliqunyy 15:83bbc18cccbc 343 nv_di_th_1st_val |= di_1st << NV_DI_TH_1ST_OFFSET;
wuliqunyy 15:83bbc18cccbc 344 nv_di_th_2nd_val &= ~NV_DI_TH_2ND_MASK;
wuliqunyy 15:83bbc18cccbc 345 nv_di_th_2nd_val |= di_2nd << NV_DI_TH_2ND_OFFSET;
wuliqunyy 14:062850afdf38 346 char i2cMessage[3];
wuliqunyy 15:83bbc18cccbc 347 *(i2cMessage+0) = (char)(I2C_DI_TH_1ST >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 348 *(i2cMessage+1) = (char)(nv_di_th_1st_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 349 *(i2cMessage+2) = (char)(nv_di_th_1st_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 350 ack += i2c_word_write(i2cMessage);
wuliqunyy 15:83bbc18cccbc 351 *(i2cMessage+0) = (char)(I2C_DI_TH_2ND >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 352 *(i2cMessage+1) = (char)(nv_di_th_2nd_val >> 8)& 0xff;
wuliqunyy 15:83bbc18cccbc 353 *(i2cMessage+2) = (char)(nv_di_th_2nd_val >> 0)& 0xff;
wuliqunyy 15:83bbc18cccbc 354 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 355 return ack;
wuliqunyy 12:9f8c7f4da5f6 356 }
wuliqunyy 12:9f8c7f4da5f6 357
wuliqunyy 12:9f8c7f4da5f6 358
wuliqunyy 12:9f8c7f4da5f6 359
wuliqunyy 12:9f8c7f4da5f6 360
wuliqunyy 11:b86aea372744 361 /** i2c to clean the I2C controller settins
wuliqunyy 11:b86aea372744 362 */
wuliqunyy 11:b86aea372744 363 int i2c_mbed_fpga::i2c_clear_spd_ctrl(){
wuliqunyy 11:b86aea372744 364 int ack = 0;
wuliqunyy 11:b86aea372744 365 nv_spd_control_1_val = 0;
wuliqunyy 11:b86aea372744 366 nv_spd_control_2_val = 0;
wuliqunyy 14:062850afdf38 367 char i2cMessage[3];
wuliqunyy 14:062850afdf38 368 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 369 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 370 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 371 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 372 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 373 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 374 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 375 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 376
wuliqunyy 11:b86aea372744 377 return ack;
wuliqunyy 11:b86aea372744 378 }
wuliqunyy 11:b86aea372744 379
wuliqunyy 14:062850afdf38 380 /** i2c to set the I2C speed input mode
wuliqunyy 14:062850afdf38 381 */
wuliqunyy 14:062850afdf38 382 int i2c_mbed_fpga::i2c_set_input_mode(unsigned int mode){
wuliqunyy 14:062850afdf38 383 int ack = 0;
wuliqunyy 14:062850afdf38 384 nv_application_cfg_val &= ~NV_INPUT_MODE_CFG_MASK;
wuliqunyy 14:062850afdf38 385 nv_application_cfg_val |= mode << NV_INPUT_MODE_CFG_OFFSET;
wuliqunyy 14:062850afdf38 386 char i2cMessage[3];
wuliqunyy 14:062850afdf38 387 *(i2cMessage+0) = (char)(I2C_APPLICATION_CFG >> 0)& 0xff;
wuliqunyy 14:062850afdf38 388 *(i2cMessage+1) = (char)(nv_application_cfg_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 389 *(i2cMessage+2) = (char)(nv_application_cfg_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 390 ack += i2c_word_write(i2cMessage);
wuliqunyy 14:062850afdf38 391 return ack;
wuliqunyy 14:062850afdf38 392 }
wuliqunyy 14:062850afdf38 393
wuliqunyy 14:062850afdf38 394
wuliqunyy 11:b86aea372744 395
wuliqunyy 9:76a0b9f29a2d 396 /** i2c to set the open loop mode
wuliqunyy 9:76a0b9f29a2d 397 */
wuliqunyy 9:76a0b9f29a2d 398 int i2c_mbed_fpga::i2c_set_loop_mode(unsigned int openloop){
wuliqunyy 9:76a0b9f29a2d 399 int ack = 0;
wuliqunyy 9:76a0b9f29a2d 400 nv_spd_control_1_val &= ~NV_SPD_LOOP_MODE_MASK;
wuliqunyy 9:76a0b9f29a2d 401 nv_spd_control_1_val |= openloop << NV_SPD_LOOP_MODE_OFFSET;
wuliqunyy 14:062850afdf38 402 char i2cMessage[3];
wuliqunyy 14:062850afdf38 403 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 404 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 405 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 406 ack += i2c_word_write(i2cMessage);
wuliqunyy 9:76a0b9f29a2d 407
wuliqunyy 9:76a0b9f29a2d 408 return ack;
wuliqunyy 9:76a0b9f29a2d 409 }
wuliqunyy 9:76a0b9f29a2d 410
wuliqunyy 12:9f8c7f4da5f6 411 /** i2c to set the Single Pulse Start Up (pulse train)
wuliqunyy 12:9f8c7f4da5f6 412 */
wuliqunyy 12:9f8c7f4da5f6 413 int i2c_mbed_fpga::i2c_set_open_loop_duty(unsigned int duty){
wuliqunyy 12:9f8c7f4da5f6 414 int ack = 0;
wuliqunyy 12:9f8c7f4da5f6 415 ram_open_duty_val = duty;
wuliqunyy 14:062850afdf38 416 char i2cMessage[3];
wuliqunyy 14:062850afdf38 417 *(i2cMessage+0) = (char)(I2C_SPEED_DUTY)& 0xff;
wuliqunyy 14:062850afdf38 418 *(i2cMessage+1) = (char)(ram_open_duty_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 419 *(i2cMessage+2) = (char)(ram_open_duty_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 420 ack += i2c_word_write(i2cMessage);
wuliqunyy 12:9f8c7f4da5f6 421
wuliqunyy 12:9f8c7f4da5f6 422 return ack;
wuliqunyy 12:9f8c7f4da5f6 423 }
wuliqunyy 12:9f8c7f4da5f6 424
wuliqunyy 11:b86aea372744 425 /** i2c to set the speed curve type
wuliqunyy 11:b86aea372744 426 */
wuliqunyy 11:b86aea372744 427 int i2c_mbed_fpga::i2c_set_curve_type(unsigned int curvetype){
wuliqunyy 11:b86aea372744 428 int ack = 0;
wuliqunyy 11:b86aea372744 429 nv_spd_control_1_val &= ~NV_CURVE_MODE_MASK;
wuliqunyy 11:b86aea372744 430 nv_spd_control_1_val |= curvetype << NV_CURVE_MODE_OFFSET;
wuliqunyy 14:062850afdf38 431 char i2cMessage[3];
wuliqunyy 14:062850afdf38 432 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_1 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 433 *(i2cMessage+1) = (char)(nv_spd_control_1_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 434 *(i2cMessage+2) = (char)(nv_spd_control_1_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 435 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 436
wuliqunyy 11:b86aea372744 437 return ack;
wuliqunyy 11:b86aea372744 438 }
wuliqunyy 11:b86aea372744 439
wuliqunyy 11:b86aea372744 440 /** i2c to set the open dc ini
wuliqunyy 11:b86aea372744 441 */
wuliqunyy 11:b86aea372744 442 int i2c_mbed_fpga::i2c_set_dc_ini(unsigned int ini){
wuliqunyy 11:b86aea372744 443 int ack = 0;
wuliqunyy 11:b86aea372744 444 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_INI_MASK;
wuliqunyy 11:b86aea372744 445 nv_spd_control_2_val |= ini << NV_DC_OPENLOOP_INI_OFFSET;
wuliqunyy 14:062850afdf38 446 char i2cMessage[3];
wuliqunyy 14:062850afdf38 447 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 448 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 449 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 450 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 451
wuliqunyy 11:b86aea372744 452 return ack;
wuliqunyy 11:b86aea372744 453 }
wuliqunyy 11:b86aea372744 454
wuliqunyy 11:b86aea372744 455 /** i2c to set the open dc slew rate
wuliqunyy 11:b86aea372744 456 */
wuliqunyy 11:b86aea372744 457 int i2c_mbed_fpga::i2c_set_dc_sr(unsigned int sr){
wuliqunyy 11:b86aea372744 458 int ack = 0;
wuliqunyy 11:b86aea372744 459 nv_spd_control_2_val &= ~NV_DC_OPENLOOP_SR_MASK;
wuliqunyy 11:b86aea372744 460 nv_spd_control_2_val |= sr << NV_DC_OPENLOOP_SR_OFFSET;
wuliqunyy 14:062850afdf38 461 char i2cMessage[3];
wuliqunyy 14:062850afdf38 462 *(i2cMessage+0) = (char)(I2C_SPD_CTRL_2 >> 0)& 0xff;
wuliqunyy 14:062850afdf38 463 *(i2cMessage+1) = (char)(nv_spd_control_2_val >> 8)& 0xff;
wuliqunyy 14:062850afdf38 464 *(i2cMessage+2) = (char)(nv_spd_control_2_val >> 0)& 0xff;
wuliqunyy 14:062850afdf38 465 ack += i2c_word_write(i2cMessage);
wuliqunyy 11:b86aea372744 466
wuliqunyy 11:b86aea372744 467 return ack;
wuliqunyy 11:b86aea372744 468 }
wuliqunyy 11:b86aea372744 469
wuliqunyy 16:a0bfe33f8a4a 470 /** i2c to set the target CLIM during start up
wuliqunyy 16:a0bfe33f8a4a 471 */
wuliqunyy 16:a0bfe33f8a4a 472 int i2c_mbed_fpga::i2c_set_clim_start_up(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 473 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 474 nv_clim_user_1_val &= ~NV_TARGET_CLIM_USER_PULSES_MASK;
wuliqunyy 16:a0bfe33f8a4a 475 nv_clim_user_1_val |= clim << NV_TARGET_CLIM_USER_PULSES_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 476 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 477 *(i2cMessage+0) = (char)(I2C_CLIM_USER_1 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 478 *(i2cMessage+1) = (char)(nv_clim_user_1_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 479 *(i2cMessage+2) = (char)(nv_clim_user_1_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 480 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 481
wuliqunyy 16:a0bfe33f8a4a 482 return ack;
wuliqunyy 16:a0bfe33f8a4a 483 }
wuliqunyy 12:9f8c7f4da5f6 484
wuliqunyy 16:a0bfe33f8a4a 485 /** i2c to set the target CLIM during brake
wuliqunyy 16:a0bfe33f8a4a 486 */
wuliqunyy 16:a0bfe33f8a4a 487 int i2c_mbed_fpga::i2c_set_clim_brake(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 488 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 489 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_BRAKE_MASK;
wuliqunyy 16:a0bfe33f8a4a 490 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_BRAKE_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 491 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 492 *(i2cMessage+0) = (char)(I2C_CLIM_USER_0 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 493 *(i2cMessage+1) = (char)(nv_clim_user_0_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 494 *(i2cMessage+2) = (char)(nv_clim_user_0_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 495 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 496
wuliqunyy 16:a0bfe33f8a4a 497 return ack;
wuliqunyy 16:a0bfe33f8a4a 498 }
wuliqunyy 16:a0bfe33f8a4a 499
wuliqunyy 16:a0bfe33f8a4a 500 /** i2c to set the target CLIM during run time
wuliqunyy 16:a0bfe33f8a4a 501 */
wuliqunyy 16:a0bfe33f8a4a 502 int i2c_mbed_fpga::i2c_set_clim_run_time(unsigned int clim){
wuliqunyy 16:a0bfe33f8a4a 503 int ack = 0;
wuliqunyy 16:a0bfe33f8a4a 504 nv_clim_user_0_val &= ~NV_TARGET_CLIM_USER_MOTOR_MASK;
wuliqunyy 16:a0bfe33f8a4a 505 nv_clim_user_0_val |= clim << NV_TARGET_CLIM_USER_MOTOR_OFFSET;
wuliqunyy 16:a0bfe33f8a4a 506 char i2cMessage[3];
wuliqunyy 16:a0bfe33f8a4a 507 *(i2cMessage+0) = (char)(I2C_CLIM_USER_0 >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 508 *(i2cMessage+1) = (char)(nv_clim_user_0_val >> 8)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 509 *(i2cMessage+2) = (char)(nv_clim_user_0_val >> 0)& 0xff;
wuliqunyy 16:a0bfe33f8a4a 510 ack += i2c_word_write(i2cMessage);
wuliqunyy 16:a0bfe33f8a4a 511
wuliqunyy 16:a0bfe33f8a4a 512 return ack;
wuliqunyy 16:a0bfe33f8a4a 513 }
wuliqunyy 16:a0bfe33f8a4a 514
wuliqunyy 16:a0bfe33f8a4a 515
wuliqunyy 16:a0bfe33f8a4a 516 /** i2c to read I2C_CLIM_CALIB
wuliqunyy 16:a0bfe33f8a4a 517 */
wuliqunyy 16:a0bfe33f8a4a 518